code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_rca_clk;
reg clock; //input clock
reg [31:0] tb_a, tb_b; //32bits 2 input
reg tb_ci; //carry in
wire [31:0] tb_s_rca; //32bits sum(output)
wire tb_co_rca; //carry out
parameter STEP = 10; //define STEP=10ns
rca_clk U0_rca_clk (
.clock(clock),
.a(tb_a),
.b(tb_b),
.ci(tb_ci),
.s_rca(tb_s_rca),
.co_rca(tb_co_rca)
);
//express by instance
always #(STEP / 2) clock = ~clock; //every 5ns, invert clock
initial begin
clock = 1'b1;
tb_a = 32'h0;
tb_b = 32'h0;
tb_ci = 1'b0; //at first, input(a,b,ci)=(0,0,0)
#(STEP);
tb_a = 32'hFFFF_FFFF;
tb_b = 32'h0;
tb_ci = 1'b1; //after 10ns, input(a,b,ci)=(hFFFF_FFFF,0,1)
#(STEP);
tb_a = 32'h0000_FFFF;
tb_b = 32'hFFFF_0000;
tb_ci = 1'b0; //after 10ns, input(a,b,ci)=(h0000_FFFF,hFFFF_0000,0)
#(STEP);
tb_a = 32'h135f_a562;
tb_b = 32'h3561_4642;
tb_ci = 1'b0; //after 10ns, input(a,b,ci)=(h135f_a562,h3561_4642,0)
#(STEP * 2);
$stop; //after 20ns, stop
end
endmodule
| 6.819511 |
module tb_rca_net;
// TB_SIGNALS
reg clk, reset;
reg [7:0] num1;
reg [7:0] num2;
wire [8:0] sum_out;
// Instantiate the Unit Under Test (UUT)
rca uut (
.num1(num1),
.num2(num2),
.sum (sum_out)
);
initial begin
$dumpfile("tb_rca_net.vcd");
$dumpvars(0, tb_rca_net);
// Initialize Inputs
clk = 0;
reset = 0;
reset = 1;
#1;
reset = 0;
#10;
#30000 $finish;
end
always #10 clk = ~clk;
always @(clk, reset) begin
if (reset) begin
num1 <= 8'b0;
num2 <= 8'b0;
end else begin
num1 = num1 + 1;
if (num1[3:0] == 4'b1111) num2 = num2 + 1;
end
end
endmodule
| 7.21298 |
module tb_rd_control ();
reg clk;
reg reset;
reg active;
wire [3:0] rd_en;
wire [31:0] rd_addr;
always begin
#5;
clk = ~clk;
end
initial begin
clk = 1'b0;
reset = 1'b1;
active = 1'b0;
#10;
reset = 1'b0;
#10;
#10;
active = 1'b1;
#10;
$stop;
#10;
#10;
#10;
#10;
#10;
#10;
$stop;
end
rd_control addr (
.clk(clk),
.reset(reset),
.active(active),
.rd_en(rd_en),
.rd_addr(rd_addr)
);
endmodule
| 6.552346 |
module tb;
`define NULL 0
`define CYCLE 20
integer fp; // file handler
integer handle;
reg clk;
reg nrst;
//reg [8*1-1:0] strings;
reg [8*32-1:0] strings;
reg [8*5-1:0] cmd, op1, op2;
//reg [0:8*32-1] strings;
reg [255:0] str;
initial begin
nrst = 1'b1;
clk = 1'b0;
forever #(`CYCLE / 2) clk = ~clk;
end
initial begin
handle = 1;
fp = $fopen("tb/tb_readline.dat", "r");
if (fp == `NULL) begin
$display("file handle was NULL");
$finish;
end
while (!$feof(
fp
)) begin
//$fgets(strings, fp);
$fscanf(fp, "%s %h %h\n", cmd, op1, op2);
//strings = $fgetc(fp);
//$display("strings: %s",strings);
//$display("strings: %s",strings[8*16-1:8*10]);
//$display("handle: %d",handle);
//$display("fp: %d",fp);
$display("cmd op1 op2: %6s %4h %8h", cmd, op1, op2);
handle = handle + 1;
end
$fclose(fp);
$finish;
end
endmodule
| 7.134967 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // synchronous
reg [31:0] s_data_fill; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // valid synchronous, ready asynchronous
wire valid_var;
master m0 (
.clk(clk_tb),
.reset(reset_tb),
.trans_data(data_tb),
.ready(ready),
.data(data),
.valid(valid),
.valid_var(valid_var)
);
slave s0 (
.clk(clk_tb),
.reset(reset_tb),
.data(data),
.valid(valid),
.ready(ready),
.valid_var(valid_var),
.s_data_fill(s_data_fill)
);
// clock generation
initial begin
clk_tb = 0;
forever begin
#halfperiod clk_tb = ~clk_tb;
end
end
// reset generation
initial begin
reset_tb = 1;
#reset_delay reset_tb = 0;
end
// transmit data generation
initial begin
data_tb = 32'b0;
#195;
data_tb = 32'h20220503;
#10;
data_tb = 32'b0;
#200;
data_tb = 32'h10000006;
end
initial begin
s_data_fill = 32'h10000006;
#192;
s_data_fill = 32'b0;
end
endmodule
| 7.015571 |
module tb_receiver (
input clk,
input rst,
input en,
input [3:0] data,
output reg [3:0] expected,
output reg failure
);
always @(posedge clk or posedge rst)
if (rst) begin
expected <= 1;
failure <= 0;
end else if (en) begin
if (data == expected) begin
$display("Receive %d", data);
failure <= 0;
end else begin
$display("Failure: receive %d, expected %d", data, expected);
failure <= 1;
end
expected <= expected + 1;
end else begin
failure <= 0;
end
endmodule
| 7.305894 |
module TestBench ();
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
// Clks
wire clk1f;
wire clk2f; // clock in @2f
wire clk4f; // clock in @4f
wire reset;
// Serial Parallel input
wire valido;
// Inputs
wire [7:0] in0;
wire [7:0] in1;
wire [7:0] in2;
wire [7:0] in3;
wire [3:0] valid_in;
// For ff 8bits + 1 valid for mux
wire [7:0] out0m;
wire [7:0] out1m;
wire [7:0] out2m;
wire [7:0] out3m;
wire [3:0] valid_outm;
// For ff 8bits + 1 valid for tester
wire [7:0] out0t;
wire [7:0] out1t;
wire [7:0] out2t;
wire [7:0] out3t;
wire [3:0] valid_outt;
// For ff 8bits + 1 valid for mux
wire [7:0] out0m_s;
wire [7:0] out1m_s;
wire [7:0] out2m_s;
wire [7:0] out3m_s;
wire [3:0] valid_outm_s;
// For ff 8bits + 1 valid for tester
wire [7:0] out0t_s;
wire [7:0] out1t_s;
wire [7:0] out2t_s;
wire [7:0] out3t_s;
wire [3:0] valid_outt_s;
recir_idle recir_idle_TB (
// For ff 8buts + 1 valid for mux
.out0m (out0m),
.out1m (out1m),
.out2m (out2m),
.out3m (out3m),
.valid_outm(valid_outm),
// For ff 8buts + 1 valid for tester
.out0t (out0t),
.out1t (out1t),
.out2t (out2t),
.out3t (out3t),
.valid_outt(valid_outt),
// Clks
.clk1f (clk1f),
.clk2f (clk2f), // clock in @2f
.clk4f (clk4f), // clock in @4f
.reset (reset),
// Serial Parallel input
.valido (valido),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.valid_in(valid_in)
);
recir_idle_syn recir_idle_syn_TB (
// For ff 8buts + 1 valid for mux
.out0m (out0m_s),
.out1m (out1m_s),
.out2m (out2m_s),
.out3m (out3m_s),
.valid_outm(valid_outm_s),
// For ff 8buts + 1 valid for tester
.out0t (out0t_s),
.out1t (out1t_s),
.out2t (out2t_s),
.out3t (out3t_s),
.valid_outt(valid_outt_s),
// Clks
.clk1f (clk1f),
.clk2f (clk2f), // clock in @2f
.clk4f (clk4f), // clock in @4f
.reset (reset),
// Serial Parallel input
.valido (valido),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.valid_in(valid_in)
);
t_recir_idle t_recir_idle_TB (
// For ff 8buts + 1 valid for mux
.out0m (out0m),
.out1m (out1m),
.out2m (out2m),
.out3m (out3m),
.valid_outm (valid_outm),
// For ff 8buts + 1 valid for tester
.out0t (out0t),
.out1t (out1t),
.out2t (out2t),
.out3t (out3t),
.valid_outt (valid_outt),
// For structural
// For ff 8buts + 1 valid for mux
.out0m_s (out0m_s),
.out1m_s (out1m_s),
.out2m_s (out2m_s),
.out3m_s (out3m_s),
.valid_outm_s(valid_outm_s),
// For ff 8buts + 1 valid for tester
.out0t_s (out0t_s),
.out1t_s (out1t_s),
.out2t_s (out2t_s),
.out3t_s (out3t_s),
.valid_outt_s(valid_outt_s),
// Clks
.clk1f (clk1f),
.clk2f (clk2f), // clock in @2f
.clk4f (clk4f), // clock in @4f
.reset (reset),
// Serial Parallel input
.valido (valido),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.valid_in(valid_in)
);
endmodule
| 7.747207 |
module tb_record_play;
reg clk_i;
reg button_a;
reg button_b;
wire [4:0] leds_o;
initial begin
$from_myhdl(clk_i, button_a, button_b);
$to_myhdl(leds_o);
end
record_play dut (
clk_i,
button_a,
button_b,
leds_o
);
endmodule
| 6.534233 |
module tb_reg32bit ();
wire [31:0] q;
reg [31:0] d;
reg clk, reset;
reg_32bit register (
q,
d,
clk,
reset
);
always @(clk) #5 clk <= ~clk;
initial
$monitor("clk: ", clk, " Reset = ", reset, " D = %b ", d, "Q = %b ", q, " time = ", $time);
initial begin
clk = 1'b1;
reset = 1'b0;
#20 reset = 1'b1;
#20 d = 32'hAFAFAFAF;
#200 $finish;
end
endmodule
| 7.279752 |
module : tb_regFile
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_regFile();
reg clock;
reg reset;
reg wEn;
reg [31:0] write_data;
reg [4:0] read_sel1;
reg [4:0] read_sel2;
reg [4:0] write_sel;
wire [31:0] read_data1;
wire [31:0] read_data2;
regFile uut (
.clock(clock),
.reset(reset),
.wEn(wEn), // Write Enable
.write_data(write_data),
.read_sel1(read_sel1),
.read_sel2(read_sel2),
.write_sel(write_sel),
.read_data1(read_data1),
.read_data2(read_data2)
);
always #5 clock = ~clock;
integer data;
integer addr;
initial begin
clock = 1'b1;
reset = 1'b1;
wEn = 1'b0;
write_data = 32'h00000000;
read_sel1 = 5'd0;
read_sel2 = 5'd1;
write_sel = 5'd0;
#1
#20
reset = 1'b0;
#10
// Write data to each register
data = 31;
for(addr=0; addr<32; addr= addr+1) begin
wEn = 1'b1;
write_sel = addr;
write_data = data;
#10
data = data - 1;
end
wEn = 1'b0;
#10
// Check write data
data = 30;
for(addr=1; addr<32; addr= addr+1) begin
if(uut.register_file[addr] != data) begin
$display("\nError: unexpected data in register file!");
$display("\ntb_regFile --> Test Failed!\n\n");
$stop();
end
data = data - 1;
end
#10
// Read data from each register
data = 30;
for(addr=1; addr<32; addr= addr+1) begin
read_sel1 = addr;
read_sel2 = addr;
#10
if(read_data1 != data) begin
$display("\nError: unexpected data from read_data1!");
$display("\ntb_regFile --> Test Failed!\n\n");
$stop();
end
if(read_data2 != data) begin
$display("\nError: unexpected data from read_data2!");
$display("\ntb_regFile --> Test Failed!\n\n");
$stop();
end
data = data - 1;
end
read_sel1 =0;
#10
// Check that register 0 is always 0x00000000
if(read_data1 != 0) begin
$display("\nError: Register 0 is not 0x00000000!");
$display("\ntb_regFile --> Test Failed!\n\n");
$stop();
end
#10
read_sel1 = 1;
write_sel = 1;
write_data = 32'hffffffff;
wEn = 1'b1;
#1 // small delay before clock edge
// read during write check - make sure old data is read
if(read_data1 != 30) begin
$display("\nError: Did not read old data with read during write!");
$display("\ntb_regFile --> Test Failed!\n\n");
$stop();
end
#9
wEn = 1'b0;
#10
$display("\ntb_regFile --> Test Passed!\n\n");
$stop();
end
endmodule
| 8.600464 |
module tb_regFile_hier ( /*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] read1Data; // From top of rf_hier.v
wire [15:0] read2Data; // From top of rf_hier.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [ 2:0] read1RegSel; // To top of rf_hier.v
reg [ 2:0] read2RegSel; // To top of rf_hier.v
reg writeEn; // To top of rf_hier.v
reg [15:0] writeData; // To top of rf_hier.v
reg [ 2:0] writeRegSel; // To top of rf_hier.v
// End of automatics
integer cycle_count;
wire clk;
wire rst;
reg fail;
// Instantiate the module we want to verify
regFile_hier DUT ( /*AUTOINST*/
// Outputs
.read1Data (read1Data[15:0]),
.read2Data (read2Data[15:0]),
// Inputs
.read1RegSel(read1RegSel[2:0]),
.read2RegSel(read2RegSel[2:0]),
.writeRegSel(writeRegSel[2:0]),
.writeData (writeData[15:0]),
.writeEn (writeEn)
);
// Pull out clk and rst from clkgenerator module
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
// ref_rf is our reference register file
reg [15:0] ref_rf [7:0];
reg [15:0] ref_r1data;
reg [15:0] ref_r2data;
initial begin
cycle_count = 0;
ref_rf[0] = 0;
ref_rf[1] = 0;
ref_rf[2] = 0;
ref_rf[3] = 0;
ref_rf[4] = 0;
ref_rf[5] = 0;
ref_rf[6] = 0;
ref_rf[7] = 0;
ref_r1data = 0;
ref_r2data = 0;
writeEn = 0;
fail = 0;
$dumpvars;
end
always @(posedge clk) begin
// create 2 random read ports
read1RegSel = $random % 8;
read2RegSel = $random % 8;
// create random data
writeData = $random % 65536;
// create a random write port
writeRegSel = $random % 8;
// randomly choose whether to write or not
writeEn = $random % 2;
// Read values from reference model
ref_r1data = ref_rf[read1RegSel];
ref_r2data = ref_rf[read2RegSel];
// Reference model. We compare simulation against this
// Write data into reference model
if ((cycle_count >= 2) && writeEn) begin
ref_rf[writeRegSel] = writeData;
end
// Delay for simulation to occur
#10
// Print log of what transpired
$display(
"Cycle: %d R1: %d Sim: %d Exp: %d R2: %d Sim: %d Exp: %d W: %d data: %d enable: %d",
cycle_count,
read1RegSel,
read1Data,
ref_r1data,
read2RegSel,
read2Data,
ref_r2data,
writeRegSel,
writeData,
writeEn
);
if (!rst && ((ref_r1data !== read1Data) || (ref_r2data !== read2Data))) begin
$display("ERRORCHECK: Incorrect read data");
fail = 1;
end
cycle_count = cycle_count + 1;
if (cycle_count > 50) begin
if (fail) $display("TEST FAILED");
else $display("TEST PASSED");
$finish;
end
end
endmodule
| 7.156617 |
module tb_register ();
reg rst;
reg clk;
reg en;
reg [7:0] din;
wire [6:0] qout;
register regi (
rst,
clk,
en,
din,
qout
);
initial begin
clk = 1'b0;
repeat (30) #10 clk = ~clk;
end
initial begin
rst <= 1'b0;
#40;
rst <= 1'b1;
din <= 4'b01001111;
en <= 1'b0;
#20;
en <= 1'b1;
#20;
din <= 4'b01001011;
#5;
rst <= 1'b0;
#20;
$finish;
end
endmodule
| 6.508049 |
module tb_register12bit_cgrundey ();
reg [11:0] reg_in;
reg enable;
wire [11:0] reg_out;
clk M1 (
enable,
clk_out
);
register12bit_cgrundey M2 (
clk_out,
reg_in,
reg_out
);
initial begin
enable = 1'b1;
reg_in = 12'd160;
#200 reg_in = 12'd250;
#200 reg_in = 12'd54;
end
endmodule
| 7.137969 |
module: registerFile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_RegisterFile;
// Inputs
reg [4:0] Rn;
reg [4:0] Rm;
reg RegWr;
reg [4:0] Rd;
reg [63:0] data;
reg clk;
// Outputs
wire [63:0] out1;
wire [63:0] out2;
// Instantiate the Unit Under Test (UUT)
registerFile uut (
.Rn(Rn),
.Rm(Rm),
.RegWr(RegWr),
.Rd(Rd),
.data(data),
.clk(clk),
.out1(out1),
.out2(out2)
);
always #50 clk = !clk;
initial begin
// Initialize Inputs
Rn = 31;
Rm = 27;
RegWr = 1;
Rd = 27;
data = 256;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.614083 |
module RegistersBankTestbench;
reg clock;
reg [1:0] readReg1;
reg [1:0] readReg2;
reg [1:0] readReg3;
reg [1:0] writeReg;
reg [7:0] writeData;
reg [7:0] memWrite;
wire [7:0] data1;
wire [7:0] data2;
wire [7:0] data3;
wire [7:0] memRead;
wire [7:0] raRead;
// sinais de controle
reg RegWrite;
reg RegMemWrite;
reg isSendType0;
RegistersBank dut (
clock,
readReg1,
readReg2,
readReg3,
writeReg,
writeData,
memWrite,
data1,
data2,
data3,
memRead,
raRead,
RegWrite,
RegMemWrite,
isSendType0
);
initial begin
clock = 0;
readReg1 = 0;
readReg2 = 0;
readReg3 = 0;
writeReg = 0;
writeData = 0;
memWrite = 0;
RegWrite = 0;
RegMemWrite = 0;
isSendType0 = 0;
$display("Teste 1: Escrevendo em $t0");
$display("Supondo que existe o valor 2 armazenado em $mem");
dut.registersA[1] = 2;
$display(
"Dessa forma, iremos supor que chegou o valor 2 na entrada writeData do banco de registradores");
$display("Valor de $t0 antes: %d", dut.registersA[2]);
readReg1 = 2;
readReg2 = 1;
readReg3 = 1;
writeReg = 2;
writeData = 'b00000010;
RegWrite = 1;
#1 clock = 1;
#1 clock = 0;
$display("Valor de $t0 depois: %d", dut.registersA[2]);
$display("Teste 2: Instrucao send do tipo 0");
$display("Ainda supondo que existe o valor 2 armazenado em $mem");
$display("Enviando o valor de $mem para $t2");
$display("Valor de $t2 antes: %d", dut.registersB[0]);
readReg1 = 1;
readReg2 = 0;
readReg3 = 0;
writeReg = 0;
writeData = 'b00000010;
RegWrite = 1;
isSendType0 = 1;
#1 clock = 1;
#1 clock = 0;
$display("Valor de $t2 depois: %d", dut.registersB[0]);
$display("Teste 3: Instrucao send do tipo 1");
$display("Ainda supondo que existe o valor 2 armazenado em $mem");
$display("Enviando o valor de $t2 para $t1");
$display("Valor de $t1 antes: %d", dut.registersA[3]);
readReg1 = 3;
readReg2 = 0;
readReg3 = 0;
writeReg = 3;
writeData = 'b00000010;
RegWrite = 1;
isSendType0 = 0;
#1 clock = 1;
#1 clock = 0;
$display("Valor de $t1 depois: %d", dut.registersA[3]);
end
initial begin
$monitor(
"Time=%0d, Clock=%d, RegWrite=%b, RegMemWrite=%b, readReg1=%d, readReg2=%d, readReg3=%d, writeReg=%d, writeData=%d, memWrite=%d, data1=%d, data2=%d, data3=%d, memRead=%d",
$time, clock, RegWrite, RegMemWrite, readReg1, readReg2, readReg3, writeReg, writeData,
memWrite, data1, data2, data3, memRead);
end
endmodule
| 6.816238 |
module tb_register_controller ();
reg clock;
reg [7:0] rx_in;
wire [7:0] tx_out;
wire [3:0] Byte_0;
wire [3:0] Byte_1;
wire [3:0] Byte_2;
wire [3:0] Byte_3;
wire [3:0] Byte_4;
wire [3:0] Byte_5;
always #1 clock = ~clock;
register_controller tb_register_Controller_DUT (
//INPUTS
.clock (clock),
.rx_in (rx_in),
//OUTPUS
.tx_out(tx_out),
.Byte_0(Byte_0),
.Byte_1(Byte_1),
.Byte_2(Byte_2),
.Byte_3(Byte_3),
.Byte_4(Byte_4),
.Byte_5(Byte_5)
);
initial begin
clock = 0;
#100 rx_in = 7'b00000011;
$display("Register Module Test Bench Finialized");
$stop;
end
endmodule
| 7.141602 |
module tb_register_file;
reg clk, reset;
reg WrEn; // write enable
reg [0:2] sel; // ppp value
reg [0:`DATA_WIDTH - 1] wr_data;
reg [0:`ADDR_WIDTH - 1] rd_addr_0, rd_addr_1, wr_addr;
wire [0:`DATA_WIDTH - 1] rd_data_0, rd_data_1;
always #(0.5 * `CLK_CYCLE) clk = ~clk;
// Instantiation of DUT
register_file register_file_dut (
.clk(clk),
.reset(reset),
.we(WrEn),
.sel(sel),
.data_in(wr_data),
.addr_wr(wr_addr),
.addr_rd_0(rd_addr_0),
.addr_rd_1(rd_addr_1),
.data_out_0(rd_data_0),
.data_out_1(rd_data_1)
);
integer out_file;
initial begin : test
integer count;
reg [0:63] initial_data;
out_file = $fopen("RF_contents.res", "w");
reset = 1;
clk = 1;
#(`CLK_CYCLE) reset = 0;
initial_data = 64'hffff_ffff_ffff_ffff;
WrEn = 0;
sel = 3'b000;
#(0.2 * `CLK_CYCLE)
// Writes the content of RF into files
for (
count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1
) begin
rd_addr_0 = count;
#(0.3 * `CLK_CYCLE) $fdisplay(out_file, "$%1d : %h", count, rd_data_0);
#(0.7 * `CLK_CYCLE);
end
// Tests internal forwarding
WrEn = 1;
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
wr_addr = count;
wr_data = initial_data;
rd_addr_0 = count;
rd_addr_1 = count;
#(`CLK_CYCLE);
end
// Tests selective writing
initial_data = 64'h1111_1111_1111_1111;
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
sel = count;
wr_addr = count;
wr_data = initial_data;
rd_addr_0 = count;
rd_addr_1 = count;
#(`CLK_CYCLE);
end
// Writes the content of RF into files
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
rd_addr_0 = count;
#(0.1 * `CLK_CYCLE) $fdisplay(out_file, "$%1d : %h", count, rd_data_0);
end
#(5 * `CLK_CYCLE) $fclose(out_file);
$finish;
end
endmodule
| 6.997046 |
module tb_register_file_syn;
reg clk, reset;
reg WrEn; // write enable
reg [0:2] sel; // ppp value
reg [0:`DATA_WIDTH - 1] wr_data;
reg [0:`ADDR_WIDTH - 1] rd_addr_0, rd_addr_1, wr_addr;
wire [0:`DATA_WIDTH - 1] rd_data_0, rd_data_1;
always #(0.5 * `CLK_CYCLE) clk = ~clk;
// Instantiation of DUT
register_file register_file_dut (
.clk(clk),
.reset(reset),
.we(WrEn),
.sel(sel),
.data_in(wr_data),
.addr_wr(wr_addr),
.addr_rd_0(rd_addr_0),
.addr_rd_1(rd_addr_1),
.data_out_0(rd_data_0),
.data_out_1(rd_data_1)
);
integer out_file;
initial begin : test
integer count;
reg [0:63] initial_data;
out_file = $fopen("RF_contents_syn.res", "w");
reset = 1;
clk = 1;
#(`CLK_CYCLE) reset = 0;
initial_data = 64'hffff_ffff_ffff_ffff;
WrEn = 0;
sel = 3'b000;
#(0.2 * `CLK_CYCLE)
// Writes the content of RF into files
for (
count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1
) begin
rd_addr_0 = count;
#(0.3 * `CLK_CYCLE) $fdisplay(out_file, "$%1d : %h", count, rd_data_0);
#(0.7 * `CLK_CYCLE);
end
// Tests internal forwarding
WrEn = 1;
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
wr_addr = count;
wr_data = initial_data;
rd_addr_0 = count;
rd_addr_1 = count;
#(`CLK_CYCLE);
end
// Tests selective writing
initial_data = 64'h1111_1111_1111_1111;
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
sel = count;
wr_addr = count;
wr_data = initial_data;
rd_addr_0 = count;
rd_addr_1 = count;
#(`CLK_CYCLE);
end
// Writes the content of RF into files
for (count = 0; count < 2 ** `ADDR_WIDTH; count = count + 1) begin
rd_addr_0 = count;
#(0.9 * `CLK_CYCLE) $fdisplay(out_file, "$%1d : %h", count, rd_data_0);
#(0.1 * `CLK_CYCLE);
end
#(5 * `CLK_CYCLE) $fclose(out_file);
$finish;
end
initial begin
$sdf_annotate("./netlist/register_file.sdf", register_file_dut,, "sdf.log", "MAXIMUM",
"1.0:1.0:1.0", "FROM_MAXIMUM");
$enable_warnings;
$log("ncsim.log");
end
endmodule
| 6.997046 |
module Tb_Registros;
reg [7:0] Mux_a_Reg;
reg [2:0] Sel_RX;
reg [2:0] Sel_RY;
reg [7:0] R0;
reg Load_Store;
reg i_Clk;
reg i_Reset;
wire [7:0] RX;
wire [7:0] RY;
Registros uut (
.Mux_a_Reg(Mux_a_Reg),
.Sel_RX(Sel_RX),
.Sel_RY(Sel_RY),
.R0(R0),
.Load_Store(Load_Store),
.i_Clk(i_Clk),
.i_Reset(i_Reset),
.RX(RX),
.RY(RY)
);
initial begin
i_Reset = 1;
i_Clk = 0;
Sel_RX = 0;
Sel_RY = 0;
Load_Store = 0;
R0 = 0;
Mux_a_Reg = 0;
#2 i_Reset = 0;
Load_Store = 0;
Mux_a_Reg = 8'b00000000;
#2 Sel_RX = 3'b000;
Load_Store = 1;
Mux_a_Reg = 8'b00000010;
#2 Sel_RX = 3'b001;
Load_Store = 1;
Mux_a_Reg = 8'b00000011;
#2 Sel_RX = 3'b010;
Load_Store = 1;
Mux_a_Reg = 8'b00000100;
#2 Sel_RX = 3'b011;
Load_Store = 1;
Mux_a_Reg = 8'b00000101;
#2 Sel_RX = 3'b100;
Load_Store = 1;
Mux_a_Reg = 8'b00000110;
#2 Sel_RX = 3'b101;
Load_Store = 1;
Mux_a_Reg = 8'b00000111;
#2 Sel_RX = 3'b110;
Load_Store = 1;
Mux_a_Reg = 8'b00001000;
#2 Sel_RX = 3'b111;
Load_Store = 1;
Mux_a_Reg = 8'b00001001;
#2 Sel_RX = 3'b011;
Load_Store = 0;
#2 Sel_RY = 3'b111;
Load_Store = 0;
end
always #1 i_Clk = !i_Clk;
endmodule
| 6.830561 |
module TB_regis_nao_bloq;
reg TB_clear, TB_clock, TB_in;
wire TB_Q3, TB_Q2, TB_Q1, TB_Q0;
// parameter stop_time = 1000;
// initial # stop_time ;
registrador_nao_bloqueante dut (
TB_in,
TB_clear,
TB_clock,
TB_Q0,
TB_Q1,
TB_Q2,
TB_Q3
);
initial begin
TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b1;
TB_clock = 1'b1;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b1;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b1;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b0;
TB_in = 1'b0;
#20 TB_clear = 1'b0;
TB_clock = 1'b1;
TB_in = 1'b0;
#20;
end
//always
//begin
// #35 TB_clock = !TB_clock ;
//#10 TB_in = ! TB_in;
// end
endmodule
| 6.812593 |
module tb_REG_SHIFT_PLOAD;
reg [31:0] Din;
reg p_load;
reg start_tx;
reg reset;
reg clk;
reg clk_tx;
wire tx_done;
wire tx_busy;
wire Dout;
REG_SHIFT_PLOAD DUT (
Din,
p_load,
start_tx,
reset,
clk,
clk_tx,
tx_done,
tx_busy,
Dout
);
initial begin
$dumpvars(0, tb_REG_SHIFT_PLOAD);
$dumpfile("my.vcd");
clk = 0;
forever #5 clk = ~clk;
end
initial begin
clk_tx = 0;
forever #10 clk_tx = ~clk_tx;
end
initial begin
reset = 1;
#5 display;
reset = 0;
Din = 32'hF0F0FF0F;
p_load = 1'b1;
start_tx = 1'b0;
#15 display;
p_load = 1'b0;
start_tx = 1'b1;
#5 display;
#5 display;
#5 display;
#5 display;
#5 display;
#5 display;
#650 $finish;
end
task display;
$display(
"r = %0h, clk = %0h, clk_tx = %0h, Din = %0h, p_load = %0h, start_tx = %0h, tx_done = %0h, tx_busy = %0h, Dout = %0h,",
reset, clk, clk_tx, Din, p_load, start_tx, tx_done, tx_busy, Dout);
endtask
endmodule
| 6.922928 |
module tb_relu_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam NUM = {DATA_WIDTH{1'b1}};
// interface
reg clk;
reg rst_n;
reg [ NUM_INPUT_DATA-1:0] i_valid;
reg [ WIDTH_INPUT_DATA-1:0] i_data_bus;
wire [ NUM_OUTPUT_DATA-1:0] o_valid;
wire [WIDTH_OUTPUT_DATA-1:0] o_data_bus; //{o_data_a, o_data_b}
reg i_en;
initial begin
clk = 1'b0;
rst_n = 1'b1;
i_data_bus = ZERO_POINT;
i_valid = 1'b0;
i_en = 1'b1;
// reset
#10 rst_n = 1'b0;
// input activate below zero (negative)
#10 rst_n = 1'b1;
i_data_bus = {1'b1, {(DATA_WIDTH - 1) {1'b0}}};
i_valid = 1'b1;
// input activate larger than zero
#10
// i_data_bus = {1'b0, {(DATA_WIDTH-1){1'b1}}};
i_data_bus = ZERO_POINT;
i_valid = 1'b1;
#2600 $stop;
end
integer i;
always begin
@(posedge clk)
for (i = 0; i < NUM; i = i + 1) begin
i_data_bus = i_data_bus + 2'sb01;
end
end
always #5 clk = ~clk;
relu_seq #(
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.rst_n(rst_n),
.i_data_bus(i_data_bus),
.i_valid(i_valid),
.o_data_bus(o_data_bus),
.o_valid(o_valid),
.i_en(i_en)
);
endmodule
| 6.930274 |
module tb_reset #(
parameter ASSERT_TIME = 32
) (
output rst_out
);
reg tb_rst;
initial tb_rst <= 1'b1;
task assert_reset;
begin
tb_rst = 1'b1;
#ASSERT_TIME;
tb_rst = 1'b0;
$display("-#- %15.t | %m: tb_rst asserted!", $time);
end
endtask
assign rst_out = tb_rst;
endmodule
| 7.710531 |
module. It should be instantiated
// and connected to both the DUT
//
//
// Parameters:
// None
//
// Notes :
//
// Multicycle and False Paths
// None - this is a testbench file only, and is not intended for synthesis
//
`timescale 1ns/1ps
module tb_resetgen (
input clk,
output reg reset
);
//***************************************************************************
// Parameter definitions
//***************************************************************************
//***************************************************************************
// Register declarations
//***************************************************************************
//***************************************************************************
// Code
//***************************************************************************
initial
begin
reset = 1'b0;
end // initial
task assert_reset (
input [31:0] num_clk
);
begin
$display("%t Asserting reset for %d clocks",$realtime, num_clk);
reset = 1'b1;
repeat (num_clk) @(posedge clk);
$display("%t Deasserting reset",$realtime);
reset = 1'b0;
end
endtask
endmodule
| 7.134595 |
module TB_reset_block();
wire reset_o;
reg reset_i;
reg areset;
reg clk;
reg state;
reg [31:0] counter;
reset_block #(
.DELAY(`SIM_RESET_DELAY),
.WIDTH(`SIM_RESET_WIDTH)
) reset_block (
.clk(clk), .async_reset_i(areset), .reset_i(reset_i), .reset_o(reset_o)
);
initial begin
$dumpvars;
clk<=1'b0;
areset<=1'b1;
reset_i<=1'b1;
state<=1'b0;
counter<=32'b0;
#1
areset<=1'b0;
`ifdef DEBUG
$display("starting sim");
`endif
#`SIMLENGTH
$display("FAILED: simulation timed out");
$finish;
end
always begin
#1 clk <=~clk;
end
always @(posedge clk) begin
counter<=counter + 1;
reset_i<=1'b0;
case (state)
0: begin
if (counter == 3) begin
if (reset_o) begin
$display("FAILED: expected no reset 0");
$finish;
end
end
if (counter == `SIM_RESET_DELAY + 3) begin
if (~reset_o) begin
$display("FAILED: expected reset 0");
$finish;
end
end
if (counter == `SIM_RESET_DELAY + `SIM_RESET_WIDTH + 3) begin
if (reset_o) begin
$display("FAILED: expected reset deassert 0");
$finish;
end else begin
state<=1'b1;
counter<=32'b0;
reset_i<=1'b1;
end
end
end
1: begin
if (counter == 0) begin
if (reset_o) begin
$display("FAILED: expected no reset 1");
$finish;
end
end
if (counter == `SIM_RESET_DELAY + 2) begin
if (~reset_o) begin
$display("FAILED: expected reset 1");
$finish;
end
end
if (counter == `SIM_RESET_DELAY + `SIM_RESET_WIDTH + 4) begin
if (reset_o) begin
$display("FAILED: expected reset deassert 1");
$finish;
end else begin
$display("PASSED");
$finish;
end
end
end
endcase
end
endmodule
| 7.040415 |
module checks the data received from the DUT against
// the data stored in a FIFO
//
// Parameters:
//
// Tasks:
// start_chk : Enables the checker
//
// Functions:
//
// Internal variables:
// reg enabled;
//
//
// Notes :
//
//
// Multicycle and False Paths
// None - this is a testbench file only, and is not intended for synthesis
//
// All times in this testbench are expressed in units of nanoseconds, with a
// precision of 1ps increments
`timescale 1ns/1ps
module tb_resp_checker (
input [7:0] data_in,
input frm_err,
input strobe
);
//***************************************************************************
// Parameter definitions
//***************************************************************************
//***************************************************************************
// Register declarations
//***************************************************************************
reg enabled = 1'b0;
reg [7:0] my_data;
reg [7:0] char_received;
//***************************************************************************
// Tasks
//***************************************************************************
// Enables the checker
task enable;
input new_enable;
begin
enabled = new_enable;
end
endtask
task is_done (
);
begin
if (!tb_char_fifo_i0.is_empty(1'b0))
$display("%t ERROR Data FIFO is not empty when expected",$realtime);
end
endtask
//***************************************************************************
// Code
//***************************************************************************
always @(posedge strobe)
begin
if (enabled)
begin
my_data = tb_char_fifo_i0.pop(1'b0);
char_received = data_in;
#1; // Wait to ensure that the output data is valid after the rising
// edge of the strobe
if (data_in !== my_data)
begin
$display(
"%t ERROR Character mismatch. Expected %x (%c), received %x (%c)",
$realtime, my_data, my_data, data_in, data_in);
end
else
begin
$display("%t Character received %x (%c)", $realtime, my_data,my_data);
end
end // if enabled
end // always
always @(posedge frm_err)
begin
if (enabled)
begin
$display("%t ERROR Frame Error Detected", $realtime);
end // if enabled
end // always
endmodule
| 6.949591 |
module: retnuoCl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_retnuoCl;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
retnuoCl uut (
.lfsr(lfsr),
.out(out)
);
initial begin
// Initialize Inputs
lfsr = 16'b0000000000000000;
$display("set lsfr to : %d", lfsr);
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, out=%b, (hex): %h", lfsr, out, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule
| 7.20633 |
module tb_RE_Control;
parameter s_IDLE = 2'b00; //States for the main FSM
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000; //States for the sub-FSM
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100;
parameter s_ADC_2 = 3'b101;
parameter s_END = 3'b110;
reg r_Init = 1'b0;
reg r_Clock = 1'b0;
reg r_Reset = 1'b0;
reg r_Exp_increase = 1'b0;
reg r_Exp_decrease = 1'b0;
wire w_NRE_1;
wire w_NRE_2;
wire w_ADC;
wire w_Expose;
wire w_Erase;
wire [4:0] w_count_time;
wire [1:0] w_Main_FSM;
wire [2:0] w_RD_FSM;
wire [1:0] w_RD_timer;
//Instantiation of RE_Control, called UUT (Unit Under Test)
RE_Control UUT (
.IN_Init(r_Init),
.IN_Clock(r_Clock),
.IN_Reset(r_Reset),
.IN_Exp_increase(r_Exp_increase),
.IN_Exp_decrease(r_Exp_decrease),
.OUT_NRE_1(w_NRE_1),
.OUT_NRE_2(w_NRE_2),
.OUT_ADC(w_ADC),
.OUT_Expose(w_Expose),
.OUT_Erase(w_Erase),
.OUT_count_time(w_count_time),
.OUT_Main_FSM(w_Main_FSM),
.OUT_RD_FSM(w_RD_FSM),
.OUT_RD_timer(w_RD_timer)
);
always #2 r_Clock <= !r_Clock;
initial begin //Function calls to create a *.vcd file
$dumpfile("dump.vcd"); //NECESSARY JUST TO SIMULATE IN edaplayground.com
$dumpvars(1); //WITH EITHER VERILOG OR SYSTEMVERILOG
end
initial begin //Initial block
r_Reset <= 1'b1;
#10 //20us seconds
r_Reset <= 1'b0;
#8 r_Exp_increase <= 1'b1;
#8 r_Exp_increase <= 1'b0;
#5 r_Exp_increase <= 1'b1;
#8 r_Exp_increase <= 1'b0;
#5 r_Exp_increase <= 1'b1;
#8 r_Exp_increase <= 1'b0;
#5 r_Exp_increase <= 1'b1;
#8 r_Exp_increase <= 1'b0;
#5 r_Exp_decrease <= 1'b1;
#8 r_Exp_decrease <= 1'b0;
#5 r_Exp_decrease <= 1'b1;
#8 r_Exp_decrease <= 1'b0;
#5 r_Init <= 1'b1;
#5 r_Init <= 1'b0;
#60 $display("Test Complete");
end
endmodule
| 6.673291 |
module tb_rf_modulator;
reg clk;
reg rst_n;
wire [5:0] video;
wire [6:0] rf;
//Accumulate 3 signals
// Color
// VSYNC
// HSYNC
reg [31:0] color_acc;
reg [31:0] vsync_acc;
reg [31:0] hsync_acc;
//Make dummy signal
always @(posedge clk) begin
if (!rst_n) begin
color_acc <= 0;
vsync_acc <= 0;
hsync_acc <= 0;
end else begin
color_acc <= color_acc + 512035;
vsync_acc <= vsync_acc + 18477;
hsync_acc <= hsync_acc + 59;
end
end
assign video = 2 * color_acc[15] + (hsync_acc[15] | hsync_acc[15]) << 4;
waever waever1 (
.clk(clk),
.reset(!rst_n),
.video(video),
.rf(rf)
);
localparam CLK_PERIOD = 6;
always #(CLK_PERIOD / 2) clk = ~clk;
integer file;
initial begin
file = $fopen("rf.dat", "wb");
$dumpfile("tb_rf_modulator.vcd");
$dumpvars(0, tb_rf_modulator);
end
always @(posedge clk) begin
$fwrite(file, "%u", rf);
end
initial begin
#1 rst_n <= 1'bx;
clk <= 1'bx;
#(CLK_PERIOD * 3) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
repeat (5) @(posedge clk);
rst_n <= 1;
@(posedge clk);
repeat (1000000) @(posedge clk);
$finish(2);
end
endmodule
| 6.576049 |
module TB_rgb2gray;
`timescale 10ns/10ns
reg clk;
reg [11:0] rgb_in;
wire [11:0] gray_out;
grayScale UUT(clk, rgb_in, gray_out);
initial begin
#20;
rgb_in = 12'b1111_1111_1111;
#20;
rgb_in = 12'b1010_1010_1010;
$stop;
end
always @(posedge clk) begin
clk =#10 ~ clk;
end
endmodule
| 6.527697 |
module TB_Ring ();
reg en;
wire clk_out;
Ring #(3, 17) UUT (
en,
clk_out
);
initial begin
#200 en = 1'b0;
#200 en = 1'b0;
#200 en = 1'b1;
#100000 $stop;
end
endmodule
| 6.827656 |
module tb_ripple_carry ();
reg [3:0] A, B; // Declaration of two four-bit inputs
reg cin; // and the one-bit input carry
wire [3:0] s; // Declaration of the five-bit outputs
wire cout; // internal carry wires
ripple_carry DUT (
s,
cout,
cin,
A,
B
);
initial begin
#10 A = 4'b0000;
B = 4'b0001;
cin = 1'b0;
#10 A = 4'b0001;
B = 4'b0001;
cin = 1'b0;
#10 A = 4'b0010;
B = 4'b0001;
cin = 1'b1;
#10 A = 4'b0100;
B = 4'b0001;
cin = 1'b1;
end
endmodule
| 7.753905 |
module ripple_test_bench ();
reg [3:0] A, B;
reg Cin;
wire [3:0] Sout;
wire Cout;
ripple_carry_adder F6 (
Sout,
Cout,
A,
B,
Cin
);
initial begin
A = 4'd0;
B = 4'd0;
Cin = 1'b0;
#5 A = 4'd3;
B = 4'd4;
#5 A = 4'd2;
B = 4'd5;
#5 A = 4'd10;
B = 4'd5;
#5 A = 4'd10;
B = 4'd5;
Cin = 1'b1;
#10 $finish;
end
endmodule
| 6.602528 |
module tb_ripple_counter;
// Inputs
reg clk, reset;
// Output
wire [1:0] q;
// Instantiate the Unit Under Test (UUT)
ripple_counter uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_ripple_counter.vcd");
$dumpvars(0, tb_ripple_counter);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #1547 reset = ~reset;
endmodule
| 7.002753 |
module : RISC_V_Core
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
module tb_RISC_V_Core ();
reg clock, reset, start;
reg [19:0] prog_address;
reg report; // performance reporting
// module RISC_V_Core #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, OFFSET_BITS = 3, ADDRESS_BITS = 20)
RISC_V_Core CORE (
.clock(clock),
.reset(reset),
.start(start),
.prog_address(prog_address),
.from_peripheral(),
.from_peripheral_data(),
.from_peripheral_valid(),
.to_peripheral(),
.to_peripheral_data(),
.to_peripheral_valid(),
.report(report)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
report = 0;
prog_address = 'h04;
repeat (1) @ (posedge clock);
reset = 0;
start = 1;
repeat (1) @ (posedge clock);
start = 0;
repeat (1) @ (posedge clock);
end
endmodule
| 8.748131 |
module tb_riscv ();
reg clk;
reg rst_n;
wire [31:0] x1 = tb_riscv.m_riscv_soc.top.m_regs.regs[1];
wire [31:0] x2 = tb_riscv.m_riscv_soc.top.m_regs.regs[2];
wire [31:0] x3 = tb_riscv.m_riscv_soc.top.m_regs.regs[3];
wire [31:0] x26 = tb_riscv.m_riscv_soc.top.m_regs.regs[26];
wire [31:0] x27 = tb_riscv.m_riscv_soc.top.m_regs.regs[27];
wire [31:0] x29 = tb_riscv.m_riscv_soc.top.m_regs.regs[29];
wire [31:0] x30 = tb_riscv.m_riscv_soc.top.m_regs.regs[30];
initial begin
$dumpfile("rsicv.vcd"); // 指定记录模拟波形的文件
$dumpvars(0, tb_riscv); // 指定记录的模块层级
clk <= 'b0;
rst_n <= 'b0;
#30;
rst_n <= 'b1;
#15000 $finish;
end
always #10 clk <= ~clk;
//rom 初始值
initial begin
// 这里是16进制的读入，需要将readmemb改为readmemh
// 读取测试文件
$readmemh("../tb/inst_txt/rv32ui-p-jalr.txt", tb_riscv.m_riscv_soc.m_rom.rom_mem);
// $display("x27 register value is %d",tb_riscv_add.m_riscv_soc.m_rom.rom_mem[0]);
// $display("x27 register value is %d",tb_riscv_add.m_riscv_soc.m_rom.rom_mem[1]);
// $display("x27 register value is %d",tb_riscv_add.m_riscv_soc.m_rom.rom_mem[2]);
end
// always@(posedge clk)begin
// // $display("x27 register value is %d",tb_riscv_add.m_riscv_soc.m_rom.rom_mem[0]);
// $display("x27 register value is %d",tb_riscv_add.m_riscv_soc.top.m_regs.regs[27]);
// $display("x28 register value is %d",tb_riscv_add.m_riscv_soc.top.m_regs.regs[28]);
// $display("x29 register value is %d",tb_riscv_add.m_riscv_soc.top.m_regs.regs[29]);
// $display("---------------------------");
// $display("---------------------------");
// end
integer r;
initial begin
wait (x26 == 32'b1);
#200;
if (x27 == 32'b1) begin
$display("############################");
$display("######## pass !!!#########");
$display("############################");
end else begin
$display("############################");
$display("######## fail !!!#########");
$display("############################");
$display("fail testnum = %2d", x3);
for (r = 1; r < 32; r = r + 1) begin
$display("x%2d register value is %d", r, tb_riscv.m_riscv_soc.top.m_regs.regs[r]);
end
end
end
riscv_soc m_riscv_soc (
.clk (clk),
.rst_n(rst_n)
);
endmodule
| 7.067704 |
module tb_RISCV_CPU ();
parameter nb = 32;
parameter INSTR_WIDTH = 32;
parameter MEM_ADDR_SIZE = 12;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] PC_i;
wire [INSTR_WIDTH-1:0] INSTR_i;
wire MEM_READ_i;
wire MEM_WRITE_i;
wire DUMP_i;
wire [nb-1:0] ADDR_MEM_i;
wire [nb-1:0] WR_DATA_i;
wire [nb-1:0] RD_DATA_i;
clk_RISCV CG (
.CLK (CLK_i),
.RST_n(RST_n_i),
.DUMP (DUMP_i)
);
IRAM IR (
.CLK(CLK_i),
.RST_n(RST_n_i),
.ADDRESS(PC_i[MEM_ADDR_SIZE-1:0]),
.DOUT(INSTR_i)
);
DRAM DR (
.CLK(CLK_i),
.RST_n(RST_n_i),
.RD(MEM_READ_i),
.WR(MEM_WRITE_i),
.DUMP(DUMP_i),
.ADDRESS(ADDR_MEM_i[MEM_ADDR_SIZE-1:0]),
.DATAIN(WR_DATA_i),
.DATAOUT(RD_DATA_i)
);
RISCV_CPU DUT (
.CLK(CLK_i),
.RST_n(RST_n_i),
.INSTR(INSTR_i),
.READ_DATA(RD_DATA_i),
.PC(PC_i),
.ADDR_MEM(ADDR_MEM_i),
.WRITE_DATA(WR_DATA_i),
.MEM_WRITE(MEM_WRITE_i),
.MEM_READ(MEM_READ_i)
);
endmodule
| 7.079136 |
module tb_RISCV_CPU_abs ();
parameter nb = 32;
parameter INSTR_WIDTH = 32;
parameter MEM_ADDR_SIZE = 12;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] PC_i;
wire [INSTR_WIDTH-1:0] INSTR_i;
wire MEM_READ_i;
wire MEM_WRITE_i;
wire DUMP_i;
wire [nb-1:0] ADDR_MEM_i;
wire [nb-1:0] WR_DATA_i;
wire [nb-1:0] RD_DATA_i;
clk_RISCV_abs CG (
.CLK (CLK_i),
.RST_n(RST_n_i),
.DUMP (DUMP_i)
);
IRAM #(
.file_path("../tb/instruction_ram_dump_abs.txt")
) IR (
.CLK(CLK_i),
.RST_n(RST_n_i),
.ADDRESS(PC_i[MEM_ADDR_SIZE-1:0]),
.DOUT(INSTR_i)
);
DRAM #(
.dump_path("../tb/final_data_ram_dump_abs.txt")
) DR (
.CLK(CLK_i),
.RST_n(RST_n_i),
.RD(MEM_READ_i),
.WR(MEM_WRITE_i),
.DUMP(DUMP_i),
.ADDRESS(ADDR_MEM_i[MEM_ADDR_SIZE-1:0]),
.DATAIN(WR_DATA_i),
.DATAOUT(RD_DATA_i)
);
RISCV_CPU_abs DUT (
.CLK(CLK_i),
.RST_n(RST_n_i),
.INSTR(INSTR_i),
.READ_DATA(RD_DATA_i),
.PC(PC_i),
.ADDR_MEM(ADDR_MEM_i),
.WRITE_DATA(WR_DATA_i),
.MEM_WRITE(MEM_WRITE_i),
.MEM_READ(MEM_READ_i)
);
endmodule
| 7.30689 |
module tb_RISC_16bit #(
parameter W = 16
) ();
reg clk;
reg reset;
wire [W-9:0] PC_addr;
wire [W-1:0] alu_out;
wire [2:0] alu_s;
wire [2:0] state;
wire [2:0] nstate;
RISC_16bit UUT (
.clk (clk),
.reset (reset),
.PC_addr(PC_addr),
.alu_out(alu_out),
.alu_s (alu_s),
.state (state),
.nstate (nstate)
);
initial begin
clk = 0;
reset = 1;
forever #5 clk = ~clk;
end
initial begin
#10 reset = 0;
#15;
#10;
end
endmodule
| 6.736813 |
module tb_RISC_16bit_ControlUnit #(
parameter W = 16
) ();
reg clk;
reg reset;
reg RF_Rp_zero;
wire [W-9:0] PC_addr;
wire PC_clr; //
wire D_addr_sel;
wire [W-9:0] D_addr;
wire D_rd;
wire D_wr;
wire [W-9:0] RF_W_data;
wire RF_s1;
wire RF_s0;
wire [ 3:0] RF_W_addr;
wire RF_W_wr;
wire [ 3:0] RF_Rp_addr;
wire RF_Rp_rd;
wire [ 3:0] RF_Rq_addr;
wire RF_Rq_rd;
wire [ 2:0] alu_s;
wire [W-1:0] R_data;
wire [W-1:0] instruction;
wire [ 2:0] state;
wire [ 2:0] nstate;
RISC_16bit_ControlUnit UUT (
.clk(clk),
.reset(reset),
.RF_Rp_zero(RF_Rp_zero),
.PC_addr(PC_addr),
.PC_clr(PC_clr),
.D_addr_sel(D_addr_sel),
.D_addr(D_addr),
.D_rd(D_rd),
.D_wr(D_wr),
.RF_W_data(RF_W_data),
.RF_s1(RF_s1),
.RF_s0(RF_s0),
.RF_W_addr(RF_W_addr),
.RF_W_wr(RF_W_wr),
.RF_Rp_addr(RF_Rp_addr),
.RF_Rp_rd(RF_Rp_rd),
.RF_Rq_addr(RF_Rq_addr),
.RF_Rq_rd(RF_Rq_rd),
.alu_s(alu_s),
.R_data(R_data),
.instruction(instruction),
.state(state),
.nstate(nstate)
);
initial begin
clk = 0;
reset = 1;
RF_Rp_zero = 0;
forever #5 clk = ~clk;
end
initial begin
#10 reset = 0;
#15;
#10;
end
endmodule
| 6.736813 |
module tb_RISC_16bit_Datapath #(
parameter W = 16
) ();
reg clk;
reg [W-1:0] R_data;
reg [W-9:0] RF_W_data; // A, B input;
reg RF_s1;
reg RF_s0;
reg [ 3:0] RF_W_addr;
reg W_wr;
reg [ 3:0] RF_Rp_addr;
reg Rp_rd;
reg [ 3:0] RF_Rq_addr;
reg Rq_rd;
reg [ 2:0] alu_s;
wire [W-1:0] alu_out_wire;
wire RF_Rp_zero;
wire [W-1:0] Rp_data_wire;
wire [W-1:0] Rq_data_wire;
RISC_16bit_Datapath UUT (
.clk(clk),
.R_data(R_data),
.RF_W_data(RF_W_data),
.RF_s1(RF_s1),
.RF_s0(RF_s0),
.RF_W_addr(RF_W_addr),
.W_wr(W_wr),
.RF_Rp_addr(RF_Rp_addr),
.Rp_rd(Rp_rd),
.RF_Rq_addr(RF_Rq_addr),
.Rq_rd(Rq_rd),
.alu_s(alu_s),
.alu_out_wire(alu_out_wire),
.RF_Rp_zero(RF_Rp_zero),
.Rp_data_wire(Rp_data_wire),
.Rq_data_wire(Rq_data_wire)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
#10 Rp_rd = 1'b1;
Rq_rd = 1'b1;
RF_Rp_addr = 4'b0101;
RF_Rq_addr = 4'b0110;
alu_s = 3'b000;
RF_s0 = 1'b0;
RF_s1 = 1'b0;
#15 W_wr = 1;
RF_W_addr = 4'b1111;
end
endmodule
| 6.736813 |
module tb_RISC_16bit_test #(
parameter W = 16
) ();
reg clk;
reg reset;
wire [W-9:0] PC_addr;
wire [W-1:0] alu_out;
wire [2:0] alu_s;
wire [2:0] state;
wire [2:0] nstate;
RISC_16bit_test UUT (
.clk (clk),
.reset (reset),
.PC_addr(PC_addr),
.alu_out(alu_out),
.alu_s (alu_s),
.state (state),
.nstate (nstate)
);
initial begin
clk = 0;
reset = 1;
forever #5 clk = ~clk;
end
initial begin
#10 reset = 0;
#15;
#10;
end
endmodule
| 6.736813 |
module : tb_RISC_V_Core
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
module tb_RISC_V_Core();
reg clock, reset, start;
reg [19:0] prog_address;
reg report; // performance reporting
// module RISC_V_Core #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, OFFSET_BITS = 3, ADDRESS_BITS = 20)
RISC_V_Core CORE (
.clock(clock),
.reset(reset),
.start(start),
.prog_address(prog_address),
.report(report)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
report = 0;
prog_address = 'h0;
//repeat (2) @ (posedge clock);
#4;
reset = 0;
start = 1;
#2;
//repeat (1) @ (posedge clock);
start = 0;
repeat (1) @ (posedge clock);
end
initial begin
$dumpfile("RISC_V_Core.vcd");
$dumpvars(0, CORE);
end
endmodule
| 8.302029 |
module : tb_double_tx
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
`timescale 1ps/1ps
module tb_RISC_V_Core_MM ();
reg clock, reset, start, stall;
reg [19:0] prog_address;
wire report; // performance reporting
wire [31:0] current_pc;
// MM I/O
wire status;
// For I/O functions
reg [1:0] from_peripheral;
reg [31:0] from_peripheral_data;
reg from_peripheral_valid;
wire [1:0] to_peripheral;
wire [31:0] to_peripheral_data;
wire to_peripheral_valid;
//assign report = ( (current_pc >= 32'h00000a2c) & (current_pc <= 32'h00000a70) );
assign report = (current_pc == 32'h00000118);
/*
always@(posedge clock)begin
if(current_pc == 32'h000000ec) $stop();
end
*/
// module RISC_V_Core #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, OFFSET_BITS = 3, ADDRESS_BITS = 20)
RISC_V_Core #(
.CORE(0),
.DATA_WIDTH(32),
.INDEX_BITS(6),
.OFFSET_BITS(3),
.ADDRESS_BITS(32)
) CORE (
.clock(clock),
.reset(reset),
.start(start),
.stall_in(stall),
.prog_address(prog_address),
.from_peripheral(from_peripheral),
.from_peripheral_data(from_peripheral_data),
.from_peripheral_valid(from_peripheral_valid),
.to_peripheral(to_peripheral),
.to_peripheral_data(to_peripheral_data),
.to_peripheral_valid(to_peripheral_valid),
.report(report),
.current_pc(current_pc),
// I/O Ports
.mm_reg(status),
.pixel_clock(),
.fb_read_addr(),
.red(),
.green(),
.blue(),
.clock_baud_gen(),
.serial_rx(),
.serial_tx()
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
stall = 0;
prog_address = 'h0;
#10
reset = 0;
stall = 0;
#1000
$stop();
end
endmodule
| 8.202371 |
module tb_ri_limit_checker (
// Inputs - System.
aclk_i,
aresetn_i,
// Inputs
valid_i,
ready_i,
last_i,
id_i
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
//----------------------------------------------------------------------
parameter IS_ICM = 0;
parameter RI_LIMIT = 0;
parameter MNUM = 0;
parameter ID_W = IS_ICM ? `AXI_SIDW : `AXI_MIDW;
//----------------------------------------------------------------------
// PORT DECLARATIONS
//----------------------------------------------------------------------
// Inputs - System.
input aclk_i; // AXI system clock.
input aresetn_i; // AXI system reset.
// Inputs.
input valid_i;
input ready_i;
input last_i;
input [ID_W-1:0] id_i;
// Reg & Wire Variables.
reg [ID_W-1:0] id_prev_r;
reg last_prev_r;
reg tx_occured_r;
wire ri_limit_1_broken;
//--------------------------------------------------------------
// Capture ID and LAST from the previous beat.
always @(posedge aclk_i or negedge aresetn_i) begin : id_last_prev_r_PROC
if (~aresetn_i) begin
id_prev_r <= {ID_W{1'b0}};
last_prev_r <= 1'b0;
tx_occured_r <= 1'b0;
end else begin
if (valid_i & ready_i) begin
id_prev_r <= id_i;
last_prev_r <= last_i;
tx_occured_r <= 1'b1;
end
end
end // id_last_prev_r_PROC
//--------------------------------------------------------------
// Decode Error Condition.
// When new valid is asserted check that the id matches the previous
// beats ID, unless LAST was asserted for the previous beat.
// tx_occured_r is used so that we don't always flag an error on
// the first beat of the sim.
assign ri_limit_1_broken = valid_i & tx_occured_r & ((id_prev_r != id_i) & ~last_prev_r);
//--------------------------------------------------------------
// Report Error.
always @(posedge aclk_i) begin
if (ri_limit_1_broken & RI_LIMIT) begin
$display("ERROR: %0d - RI LIMIT CHECKER -> Read interleaving depth of 1 exceeded.", $time);
$display("ERROR: %0d - RI LIMIT CHECKER -> @ MASTER %0d.", $time, MNUM);
$display("ERROR: %0d - RI LIMIT CHECKER -> New ID %0h occured.", $time, id_i);
$display("ERROR: %0d - RI LIMIT CHECKER -> Prev ID %0h not completed.", $time, id_prev_r);
end
end
endmodule
| 7.283601 |
module tb_rmii_loopback ();
reg arst_n;
reg PHY0_REF_CLK;
reg PHY1_REF_CLK;
initial begin
$dumpfile("./vcd/tb_rmii_repeater.vcd");
$dumpvars(0, rmii_repeater);
PHY0_REF_CLK <= 1'b0;
PHY1_REF_CLK <= 1'b0;
arst_n <= 1;
#100 arst_n <= 0;
#100 arst_n <= 1;
#200000 $finish;
end
always begin
#10 PHY0_REF_CLK <= 1;
#10 PHY0_REF_CLK <= 0;
end
always begin
#10 PHY1_REF_CLK <= 1;
#10 PHY1_REF_CLK <= 0;
end
reg PHY0_CRS;
reg PHY0_RXD0;
reg PHY0_RXD1;
task preamble;
begin
PHY0_RXD0 <= 1'b1;
PHY0_RXD1 <= 1'b0;
#20 PHY0_RXD0 <= 1'b1;
PHY0_RXD1 <= 1'b0;
#20 PHY0_RXD0 <= 1'b1;
PHY0_RXD1 <= 1'b0;
#20 PHY0_RXD0 <= 1'b1;
PHY0_RXD1 <= 1'b1;
#20;
end
endtask
initial begin
PHY0_CRS <= 1'b0;
PHY0_RXD0 <= 1'b0;
PHY0_RXD1 <= 1'b0;
#1000 PHY0_CRS <= 1'b1;
preamble();
PHY0_RXD0 <= 1'b1;
PHY0_RXD1 <= 1'b0;
#100000 PHY0_CRS <= 1'b0;
end
TOP_RMII_repeater rmii_repeater (
.arst_n(arst_n),
/* PHY0 */
.PHY0_RST(PHY0_RST),
.PHY0_TX_EN(PHY0_TX_EN),
.PHY0_TXD0(PHY0_TXD0),
.PHY0_TXD1(PHY0_TXD1),
.PHY0_CRS(PHY0_CRS),
.PHY0_RXD0(PHY0_RXD0),
.PHY0_RXD1(PHY0_RXD1),
.PHY0_REF_CLK(PHY0_REF_CLK),
/* PHY1 */
.PHY1_RST(PHY1_RST),
.PHY1_TX_EN(PHY1_TX_EN),
.PHY1_TXD0(PHY1_TXD0),
.PHY1_TXD1(PHY1_TXD1),
.PHY1_CRS(PHY1_CRS),
.PHY1_RXD0(PHY1_RXD0),
.PHY1_RXD1(PHY1_RXD1),
.PHY1_REF_CLK(PHY1_REF_CLK)
);
endmodule
| 6.998667 |
module: RO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_RO;
// Inputs
reg RESET;
// Outputs
wire CLK_O;
// Instantiate the Unit Under Test (UUT)
RO uut (
.RESET(RESET),
.CLK_O(CLK_O)
);
initial begin
// Initialize Inputs
RESET = 1;
// Wait 100 ns for global reset to finish
#100;
RESET = 0;
// Add stimulus here
end
endmodule
| 6.909776 |
module tb_rom_ctrl ();
//input
reg sys_clk;
reg sys_rst_n;
reg key1;
reg key2;
//output
wire [7:0] addr;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
key1 <= 1'b0;
key2 <= 1'b0;
#30 sys_rst_n <= 1'b1;
#700_000
//key1
key1 <= 1'b1;
#20 key1 <= 1'b0;
#20_000 key1 <= 1'b1;
#20 key1 <= 1'b0;
#600_000
//key2
key2 <= 1'b1;
#20 key2 <= 1'b0;
#20_000 key2 <= 1'b1;
#20 key2 <= 1'b0;
#600_000
//
key1 <= 1'b1;
#20 key1 <= 1'b0;
#20_000 key2 <= 1'b1;
#20 key2 <= 1'b0;
#20_000 key2 <= 1'b1;
#20 key2 <= 1'b0;
end
always #10 sys_clk = ~sys_clk;
rom_ctrl #(
.CNT_MAX(24'd99)
) rom_ctrl_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.key1 (key1),
.key2 (key2),
.addr(addr)
);
endmodule
| 7.341808 |
module tb_rotate_led ();
reg clk, reset, pause, fast, rt;
wire [4:0] dout;
rotate_led UUT (
.clk(clk),
.reset(reset),
.pause(pause),
.fast(fast),
.rt(rt),
.dout(dout)
);
//Period of the Base Clock
parameter T = 20;
initial begin
clk = 0;
forever #(T / 2) clk = ~clk;
end
initial begin
//Test Vector # 1
pause <= 0;
rt <= 1;
fast <= 1;
reset_dut;
#250
//Test Vector # 2
pause <= 1;
rt <= 1;
fast <= 1;
#40
//Test Vector # 3
pause <= 0;
rt <= 1;
fast <= 1;
#160
//Test Vector # 4
pause <= 0;
rt <= 0;
fast <= 1;
#640
//Test Vector # 5
pause <= 0;
rt <= 1;
fast <= 0;
#500
//Test Vector # 6
pause <= 0;
rt <= 0;
fast <= 0;
#800 $stop;
end
//Reset Sequence Task
task reset_dut;
begin
reset <= 1;
@(posedge clk);
reset <= 0;
end
endtask
endmodule
| 6.806908 |
module tb_rs232 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tx;
//reg define
reg sys_clk;
reg sys_rst_n;
reg rx;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位和输入信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
rx <= 1'b1;
#20;
sys_rst_n <= 1'b1;
end
//调用任务rx_byte
initial begin
#200 rx_byte();
end
//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号
always #10 sys_clk = ~sys_clk;
//创建任务rx_byte，本次任务调用rx_bit任务，发送8次数据，分别为0~7
task rx_byte(); //因为不需要外部传递参数，所以括号中没有输入
integer j;
for (j = 0; j < 8; j = j + 1) //调用8次rx_bit任务，每次发送的值从0变化7
rx_bit(j);
endtask
//创建任务rx_bit，每次发送的数据有10位，data的值分别为0到7由j的值传递进来
task rx_bit(input [7:0] data);
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0;
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7];
9: rx <= 1'b1;
endcase
#(5208 * 20); //每发送1位数据延时5208个时钟周期
end
endtask
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------------------ rs232_inst ------------------------
rs232 rs232_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.rx (rx), //input rx
.tx(tx) //output tx
);
endmodule
| 7.523568 |
module tb_rst_ctrl;
// rst_ctrl Parameters
parameter real PERIOD_SRC = 5;
parameter real PERIOD_SYS = 4;
// rst_ctrl Inputs
reg src_clk = 0;
reg sys_clk = 0;
reg arstn = 1;
reg pll_locked = 0;
// rst_ctrl Outputs
wire rstn_pll;
wire rstn_sys;
wire rstn_mac;
initial begin
forever #(PERIOD_SRC / 2) src_clk = ~src_clk;
end
initial begin
forever #(PERIOD_SYS / 2) sys_clk = ~sys_clk;
end
initial begin
#41 arstn = 0;
#52 arstn = 1;
end
rst_ctrl u_rst_ctrl (
.src_clk (src_clk),
.sys_clk (sys_clk),
.arstn (arstn),
.pll_locked(pll_locked),
.rstn_pll(rstn_pll),
.rstn_sys(rstn_sys),
.rstn_mac(rstn_mac)
);
initial begin
#(45 + PERIOD_SRC * 20) pll_locked = 1;
#(PERIOD_SRC * 300) $finish;
end
endmodule
| 7.347006 |
module tb_RS_Decoder ();
reg [0:59] msg_in;
wire [0:43] msg_out;
wire valid;
RS_Decoder decode (
msg_in,
msg_out,
valid
);
initial begin
msg_in = 60'h123456789AB33cc;
#50 $display("TC01: No errors");
if (msg_out != 44'h123456789AB) $display("Result is wrong");
msg_in = 60'h123F56789AB33cc;
#50 $display("TC02: 1 error");
if (msg_out != 44'h123456789AB) $display("Result is wrong");
msg_in = 60'h12345B789AB31cc;
#50 $display("TC03: 2 errors");
if (msg_out != 44'h123456789AB) $display("Result is wrong");
msg_in = 60'hda5FFa98630c809;
#50 $display("TC04: 2 errors");
if (msg_out != 44'hda501a98630) $display("Result is wrong.");
msg_in = 60'h5b0128d3ff08b32;
#50 $display("TC05: 1 error");
if (msg_out != 44'h5b9128d3ff0) $display("Result is wrong.");
end
endmodule
| 6.635579 |
module tb_rtc ();
reg clk;
reg rst_n;
wire interrupt;
reg io_address = 1'b0;
reg io_read = 1'b0;
wire [ 7:0] io_readdata;
reg io_write = 1'b0;
reg [ 7:0] io_writedata = 8'd0;
reg [ 7:0] mgmt_address = 8'd0;
reg mgmt_write = 1'b0;
reg [31:0] mgmt_writedata = 32'd0;
rtc rtc_inst (
.clk (clk),
.rst_n(rst_n),
.interrupt(interrupt), //output
//io slave
.io_address (io_address), //input
.io_read (io_read), //input
.io_readdata (io_readdata), //output [7:0]
.io_write (io_write), //input
.io_writedata(io_writedata), //input [7:0]
//mgmt slave
/*
128.[26:0]: cycles in second
129.[12:0]: cycles in 122.07031 us
*/
.mgmt_address (mgmt_address), //input [7:0]
.mgmt_write (mgmt_write), //input
.mgmt_writedata(mgmt_writedata) //input [31:0]
);
//------------------------------------------------------------------------------
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
integer finished = 0;
reg [255:0] dumpfile_name;
initial begin
if ($value$plusargs("dumpfile=%s", dumpfile_name) == 0) begin
dumpfile_name = "default.vcd";
end
$dumpfile(dumpfile_name);
$dumpvars(0);
$dumpon();
$display("START");
rst_n = 1'b0;
#10 rst_n = 1'b1;
while (finished == 0) begin
if ($time > 200000) $finish_and_return(-1);
#10;
//$dumpflush();
end
#60;
$dumpoff();
$finish_and_return(0);
end
//------------------------------------------------------------------------------
endmodule
| 7.447439 |
module tb_RTL_SYNC_FIFO ();
reg [7:0] din;
reg clk;
reg we;
reg EOD_in;
reg re;
reg rst;
integer i;
initial begin
$dumpfile("./vcd/tb_rtl_sync_fifo.vcd");
$dumpvars(0, rtl_sync_fifo);
rst <= 1'b1;
clk <= 1'b0;
din <= 8'b0;
we <= 1'b0;
re <= 1'b0;
#1000 rst <= 1'b0;
#1000 we <= 1'b1;
#1000 re <= 1'b1;
#1000 we <= 1'b0;
#10000 $finish;
end
always @(posedge clk) begin
din <= din + 1'b1;
end
always begin
clk <= 1'b0;
#10;
clk <= 1'b1;
#10;
end
RTL_SYNC_FIFO #(
.DATA_WIDTH(8),
.FIFO_DEPTH_POWER(8),
.AFULL_CNT(200),
.AEMPTY_CNT(10)
) rtl_sync_fifo (
.rst(rst),
.din(din),
.clk(clk),
.wen(we),
.dout(),
.ren(re),
.empty_flag(),
.aempty_flag(aempty_flag),
.full_flag(full_flag),
.afull_flag(afull_flag)
// my original signal
);
endmodule
| 7.06836 |
module tb_rx_byte_aligner;
reg clk;
reg reset;
reg [7:0]byte_i;
wire [7:0]byte_o;
wire synced;
wire reset_g;
GSR
GSR_INST (
.GSR_N(1'b1),
.CLK(1'b0)
);
mipi_rx_byte_aligner inst1( .clk_i(clk),
.reset_i(reset),
.byte_i(byte_i),
.byte_o(byte_o),
.byte_valid_o(synced));
task sendbyte;
input [7:0]byte;
begin
byte_i = byte;
clk = 1'b1;
#4
clk = 1'b0;
#4;
end
endtask
initial begin
clk = 1'b1;
reset = 1'b1;
clk = 1'b1;
#4
clk = 1'b0;
#4;
#50
reset = 1'b0;
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h77); //B8 2B 11
sendbyte(8'h25);
sendbyte(8'h42);
sendbyte(8'hCE);
sendbyte(8'h22);
sendbyte(8'h22);
sendbyte(8'h22);
sendbyte(8'h62);
sendbyte(8'h30);
sendbyte(8'h22);
sendbyte(8'h02);
reset = 1'h1;
#5
clk = 1'b1;
#4
clk = 1'b0;
#4;
#50
reset = 1'b0;
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h70); //B8 20 50 11
sendbyte(8'h41);
sendbyte(8'hA0);
sendbyte(8'h22);
sendbyte(8'h72);
sendbyte(8'h22);
sendbyte(8'h22);
sendbyte(8'h22);
sendbyte(8'h3A);
sendbyte(8'h22);
sendbyte(8'h22);
reset = 1'h1;
#5
clk = 1'b1;
#4
clk = 1'b0;
#4;
#50
reset = 1'b0;
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h5C); //B8 2A 11
sendbyte(8'h95);
sendbyte(8'h08);
sendbyte(8'h1F);
sendbyte(8'h08);
sendbyte(8'h08);
sendbyte(8'h88);
sendbyte(8'h08);
sendbyte(8'h17);
sendbyte(8'h08);
sendbyte(8'h08);
reset = 1'h1;
#5
clk = 1'b1;
#4
clk = 1'b0;
#4;
#50
reset = 1'b0;
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h5C); //B8 60 10
sendbyte(8'h30);
sendbyte(8'h88);
sendbyte(8'h08);
sendbyte(8'hA9);
sendbyte(8'h88);
sendbyte(8'h88);
sendbyte(8'h08);
sendbyte(8'h17);
sendbyte(8'h08);
sendbyte(8'h08);
reset = 1'h1;
#5
clk = 1'b1;
#4
clk = 1'b0;
#4;
#50
reset = 1'b0;
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'h00);
sendbyte(8'hE0); //B8 60 11
sendbyte(8'h82);
sendbyte(8'h45);
sendbyte(8'h40);
sendbyte(8'hC4);
sendbyte(8'h45);
sendbyte(8'h40);
sendbyte(8'h08);
sendbyte(8'h17);
sendbyte(8'h08);
sendbyte(8'h08);
reset = 1'h1;
end
endmodule
| 6.839329 |
module tb_rx_fsm ();
reg clk_wr;
reg clk_rd;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 50 MHz clk_wr:
initial begin
clk_wr = 1'b1;
forever begin
#10 clk_wr = ~clk_wr;
end
end
// 100 MHz clk_rd:
initial begin
clk_rd = 1'b1;
#2
forever begin
#5 clk_rd = ~clk_rd;
end
end
reg in_rx_data;
reg in_op_ack;
wire [7:0] out_op;
wire [31:0] out_address;
wire [31:0] out_data;
rx_fsm #(
.BAUD(5_000_000) // 波特率是时钟频率的1/10
) component (
.clk_wr(clk_wr),
.clk_rd(clk_rd),
.wr_rst_n(rst_n),
.rd_rst_n(rst_n),
.in_rx_data(in_rx_data),
.op_ack(in_op_ack),
.op(out_op),
.address(out_address),
.data(out_data)
);
initial begin
rx_task(64'hfea1b2c3_6c7d8e9c);
rx_task(64'hfdc9b8a7_10244096);
rx_task(64'hfc123456_abcd0123); // bad op = fc
#10000;
$finish;
end
task rx_task;
input reg [63:0] rx_task_data;
reg [7:0] one_byte;
begin
in_rx_data = 1'b1;
in_op_ack = 1'b0;
#55;
repeat (8) begin
one_byte = rx_task_data[63:56];
rx_task_data = rx_task_data << 8;
in_rx_data = 1'b0; // leading bit 0
#200;
repeat (8) begin
in_rx_data = one_byte[0];
one_byte = one_byte >> 1;
#200;
end
in_rx_data = 1'b1; // end bit 1
#200;
end
#300;
in_op_ack = 1'b1;
#40;
in_op_ack = 1'b0;
#100;
end
endtask
initial begin
$dumpfile("tb_rx_fsm.vcd");
$dumpvars(0, component);
end
endmodule
| 6.827902 |
module tb_s2mm ();
reg clk = 0;
always @(*) clk <= #1 ~clk;
reg [15:0] resetn_reg = 0;
wire resetn;
wire send_data;
always @(posedge clk) resetn_reg <= {resetn_reg[14:0], 1'b1};
assign resetn = resetn_reg[12];
assign send_data = resetn_reg[15];
initial begin
wait (send_data == 1);
@(posedge clk);
axilite_wr(16'h10, 32'hc000_0000); //s2mm addr
axilite_wr(16'h18, 32'd6); //s2m size
axilite_wr(16'h0, 32'h1); //ap start
axis128_wr(16'd48, 128'hffee_ddcc_bbaa_0099_8877_6655_4433_2211);
axis128_wr(16'd48, 128'heeff_ccdd_bbaa_0099_8877_6655_4433_2211);
end
reg [127:0] axis_in_tdata = 0;
reg [ 15:0] axis_in_tkeep = 16'hFFFF;
reg axis_in_tlast = 0;
reg axis_in_tvalid = 0;
wire axis_in_tready;
reg [ 15:0] s_axi_araddr = 0;
wire s_axi_arready;
reg s_axi_arvalid = 0;
wire [ 31:0] s_axi_rdata;
reg s_axi_rready = 1;
wire [ 1:0] s_axi_rresp;
wire s_axi_rvalid;
reg [ 15:0] s_axi_awaddr = 0;
wire s_axi_awready;
reg s_axi_awvalid = 0;
reg s_axi_bready = 1;
wire s_axi_bresp;
wire s_axi_bvalid;
reg [ 31:0] s_axi_wdata = 0;
wire s_axi_wready;
reg [ 3:0] s_axi_wstrb = 0;
reg s_axi_wvalid = 0;
design_1 design_1_i (
.resetn(resetn),
.axis_in_tdata(axis_in_tdata),
.axis_in_tkeep(axis_in_tkeep),
.axis_in_tlast(axis_in_tlast),
.axis_in_tready(axis_in_tready),
.axis_in_tvalid(axis_in_tvalid),
.clk(clk),
.s_axi_control_araddr(s_axi_araddr),
.s_axi_control_arready(s_axi_arready),
.s_axi_control_arvalid(s_axi_arvalid),
.s_axi_control_awaddr(s_axi_awaddr),
.s_axi_control_awready(s_axi_awready),
.s_axi_control_awvalid(s_axi_awvalid),
.s_axi_control_bready(s_axi_bready),
.s_axi_control_bresp(s_axi_bresp),
.s_axi_control_bvalid(s_axi_bvalid),
.s_axi_control_rdata(s_axi_rdata),
.s_axi_control_rready(s_axi_rready),
.s_axi_control_rresp(s_axi_rresp),
.s_axi_control_rvalid(s_axi_rvalid),
.s_axi_control_wdata(s_axi_wdata),
.s_axi_control_wready(s_axi_wready),
.s_axi_control_wstrb(s_axi_wstrb),
.s_axi_control_wvalid(s_axi_wvalid)
);
//Task to write given data at the given address using axilite interface
task axilite_wr;
input [15:0] address;
input [31:0] data;
begin
@(posedge clk) s_axi_awaddr <= address;
s_axi_awvalid <= 1'b1;
wait ((s_axi_awvalid && s_axi_awready) == 1);
@(posedge clk) s_axi_awvalid <= 1'b0;
s_axi_wdata <= data;
s_axi_wstrb <= 4'hF;
s_axi_wvalid <= 1'b1;
wait ((s_axi_wvalid && s_axi_wready) == 1);
@(posedge clk) s_axi_wvalid <= 1'b0;
wait ((s_axi_bvalid && s_axi_bready) == 1);
@(posedge clk);
end
endtask
task axis128_wr;
input [15:0] num_bytes;
input [127:0] start_data;
reg [15:0] num_iterations;
reg [15:0] iter_count;
begin
$display("--------------------Inside AXIS write function------------------");
num_iterations = num_bytes >> 4;
iter_count = 0;
$display("--------------------No. of iterations = %d----------------------", num_iterations);
repeat (num_iterations) begin
axis_in_tvalid <= 1'b1;
axis_in_tdata <= axis_in_tdata + start_data;
axis_in_tlast <= (iter_count == (num_iterations - 1)) ? 1'b1 : 1'b0;
iter_count <= iter_count + 1'b1;
// @(posedge clk);
wait ((axis_in_tvalid && axis_in_tready && ~clk) == 1);
@(posedge clk);
$display("axis_in_tdata = %32h", axis_in_tdata);
end //repeat
axis_in_tvalid <= 1'b0;
axis_in_tlast <= 1'b0;
$display("-------------------Exiting AXIS write function--------------------");
end
endtask
endmodule
| 7.620385 |
module tb_S2P;
// Inputs
reg clk;
reg rst;
reg start;
// Outputs
wire [3:0] parallel_data;
wire serial_in;
wire data_flag;
// DUT
data_generator dat_gen (
.clk(clk),
.rst(rst),
.enable(start),
.serial_in(serial_in),
.data_flag(data_flag)
);
serial_2_parallel dut (
.clk(clk),
.rst(rst),
.start(start),
.serial_in(serial_in),
.data_flag(data_flag),
.parallel_data(parallel_data)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
start = 1;
// Wait 10 ns for global reset to finish
#10;
rst = 1;
end
always #5 clk <= ~clk;
initial begin
#100000 $stop;
end
/*always @(posedge clk) begin
data_flag = 0;
if(i == 7) begin
serial_in = $unsigned($random)%2;
data_flag = 1;
i = i-1;
end
else if(i == 0) i = 7;
else i = i-1;
end*/
endmodule
| 6.699513 |
module tb_sale_machine ();
parameter CHARGE_WIDTH = 2;
reg clk_inst;
reg rst_n_inst;
reg ten_inst;
reg twenty_inst;
reg fifty_inst;
wire out_inst;
wire [CHARGE_WIDTH-1:0] charge_inst;
sale_machine #(
.CHARGE_WIDTH(CHARGE_WIDTH)
) sale_machine_inst (
.clk(clk_inst),
.rst_n(rst_n_inst),
.ten(ten_inst),
.twenty(twenty_inst),
.fifty(fifty_inst),
.out(out_inst),
.charge(charge_inst)
);
always #25 clk_inst = ~clk_inst;
initial begin
rst_n_inst = 0;
clk_inst = 0;
#20 rst_n_inst = 1;
#10 input_eighty(ten_inst, twenty_inst, fifty_inst);
end
task input_eighty;
output ten_inst_1;
output twenty_inst_1;
output fifty_inst_1;
fork
begin
@(posedge clk_inst) #1 ten_inst_1 = 1;
twenty_inst_1 = 0;
fifty_inst_1 = 0;
end
begin
@(posedge clk_inst) #2 ten_inst_1 = 0;
twenty_inst_1 = 1;
fifty_inst_1 = 0;
end
begin
@(posedge clk_inst) #3 ten_inst_1 = 0;
twenty_inst_1 = 0;
fifty_inst_1 = 1;
end
join_any
endtask
initial begin
$wlfdumpvars(); //保存所有的波形
end
endmodule
| 6.545279 |
module tb_salidas;
reg Rst;
reg Clk;
reg [7:0] Rx;
reg [7:0] Ry;
reg [7:0] num;
reg [1:0] outbus;
wire [7:0] DataOut_Bus;
wire [7:0] Addres_Data_Bus;
wire LE;
salidas uut (
.Rst(Rst),
.Clk(Clk),
.Rx(Rx),
.Ry(Ry),
.num(num),
.outbus(outbus),
.DataOut_Bus(DataOut_Bus),
.Addres_Data_Bus(Addres_Data_Bus),
.LE(LE)
);
initial begin
Rst = 1;
Clk = 0;
Rx = 0;
Ry = 0;
num = 0;
outbus = 0;
#2 Rst = 0;
Rx = 8'd5;
Ry = 8'd6;
num = 8'd2;
outbus = 0;
#2 outbus = 2'b01;
#2 outbus = 2'b10;
#2 outbus = 2'b11;
end
always #1 Clk = !Clk;
endmodule
| 6.586853 |
module: samcoupe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_samcoupe;
// Inputs
reg clk24;
reg clk12;
reg clk6;
reg ear;
reg clkps2;
reg dataps2;
reg rst_n;
// Outputs
wire [1:0] r;
wire [1:0] g;
wire [1:0] b;
wire bright;
wire csync;
wire audio_out_left;
wire audio_out_right;
wire [18:0] sram_addr;
wire sram_we_n;
// Bidirs
wire [7:0] sram_data;
// Instantiate the Unit Under Test (UUT)
samcoupe uut (
.clk24(clk24),
.clk12(clk12),
.clk6(clk6),
.master_reset_n(rst_n),
.r(r),
.g(g),
.b(b),
.bright(bright),
.csync(csync),
.ear(ear),
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
.clkps2(clkps2),
.dataps2(dataps2),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
);
sram_sim memoria (
.a(sram_addr[15:0]),
.d(sram_data),
.we_n(sram_we_n)
);
initial begin
// Initialize Inputs
clk24 = 1;
clk12 = 1;
clk6 = 1;
ear = 0;
clkps2 = 1;
dataps2 = 1;
rst_n = 0;
// Add stimulus here
#100;
rst_n = 1;
end
always begin
clk24 = #(1000/48.0) ~clk24;
end
always begin
clk12 = #(1000/24.0) ~clk12;
end
always begin
clk6 = #(1000/12.0) ~clk6;
end
endmodule
| 6.699229 |
module is to test the sample rate controller
*/
module tb_sample_rate_controller();
reg clk;
reg reset_n;
reg en;
wire [15:0] sample_rate;
wire go;
assign sample_rate = 16'd100;
parameter CLK_HALF_PERIOD = 20; // 25Mhz
parameter RST_DEASSERT_DELAY = 100;
parameter EN_ASSERTION_DELAY = 120;
parameter END_SIM_DELAY = 10000;
// Generate the clock
initial
begin
clk = 1'b0;
end
always
begin
#CLK_HALF_PERIOD clk = ~clk;
end
// Generate the reset_n
initial
begin
reset_n = 1'b0;
#RST_DEASSERT_DELAY reset_n = 1'b1;
end
// Generate the en
initial
begin
en = 1'b0;
#EN_ASSERTION_DELAY en = 1'b1;
end
// Stop the sim
initial
begin
#END_SIM_DELAY;
$stop;
$finish; // close the simulation
end
sample_rate_controller dut
(
.clk(clk),
.reset_n(reset_n),
.en(en),
.sample_rate(sample_rate),
.go(go)
);
endmodule
| 7.58345 |
module tb_SA_Data_mover;
parameter FIFO_DATA_WIDTH = 8;
parameter FIFO_DEPTH = 14;
parameter PE_SIZE = 14;
parameter integer MEM0_DEPTH = 896;
parameter integer MEM1_DEPTH = 896;
parameter integer MEM0_ADDR_WIDTH = 10;
parameter integer MEM1_ADDR_WIDTH = 10;
parameter integer MEM0_DATA_WIDTH = 112;
parameter integer MEM1_DATA_WIDTH = 112;
parameter integer OC = 64;
reg clk;
reg rst_n;
reg en;
reg [(FIFO_DATA_WIDTH*PE_SIZE)-1:0] rdata_i;
wire [PE_SIZE-1:0] rden_o;
wire [MEM0_DATA_WIDTH-1:0] mem0_d0;
/*wire [FIFO_DATA_WIDTH*PE_SIZE-1:0] buffer_1,buffer_2,buffer_3,buffer_4,buffer_5,buffer_6,buffer_7,buffer_8,buffer_9,buffer_10,
buffer_11,buffer_12,buffer_13,buffer_14;
assign*/
always #5 clk = ~clk;
integer i;
initial begin
clk = 0;
rst_n = 0;
en = 0;
rdata_i = 0;
#50 rst_n = 1'b1;
#20
for (i = 0; i < 70 + 70 - 1; i = i + 1) begin
@(posedge clk);
#1;
if (i == 0) begin
en <= 1;
rdata_i <= {((FIFO_DATA_WIDTH * PE_SIZE)) {1'b0}};
end else if (i < 70) begin
if (i == 69) begin
en <= 1'b0;
rdata_i <= 0;
end else begin
rdata_i <= (rdata_i >> 8) | {{i[FIFO_DATA_WIDTH-1:0]},{((FIFO_DATA_WIDTH*PE_SIZE)-FIFO_DATA_WIDTH){1'b0}}};
end
end else begin
rdata_i <= (rdata_i >> 8) | {{8'b0},{((FIFO_DATA_WIDTH*PE_SIZE)-FIFO_DATA_WIDTH){1'b0}}};
end
end
end
SA_Data_mover #(
.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH),
.PE_SIZE(PE_SIZE),
.MEM0_DEPTH(MEM0_DEPTH),
.MEM1_DEPTH(MEM1_DEPTH),
.MEM0_ADDR_WIDTH(MEM0_ADDR_WIDTH),
.MEM1_ADDR_WIDTH(MEM1_ADDR_WIDTH),
.MEM0_DATA_WIDTH(MEM0_DATA_WIDTH),
.MEM1_DATA_WIDTH(MEM1_DATA_WIDTH),
.OC(OC)
) DUT (
.clk(clk),
.rst_n(rst_n),
.en(en),
.rden_o(rden_o),
.rdata_i(rdata_i),
.mem0_d0(mem0_d0)
);
endmodule
| 6.590882 |
module t_Sequential_Binary_Multiplier;
parameter dp_width = 5; // Set to width of datapath
wire [2*dp_width -1:0] Product; // Output from multiplier
wire Ready;
reg [dp_width -1:0] Multiplicand, Multiplier; // Inputs to multiplier
reg Start, clock, reset_b;
// Instantiate multiplier
Sequential_Binary_Multiplier M0 (
Product,
Ready,
Multiplicand,
Multiplier,
Start,
clock,
reset_b
);
// Generate stimulus waveforms
initial #200 $finish;
initial begin
Start = 0;
reset_b = 0;
#2 Start = 1;
reset_b = 1;
Multiplicand = 5'b10111;
Multiplier = 5'b10011;
#10 Start = 0;
end
initial begin
clock = 0;
repeat (26) #5 clock = ~clock;
end
// Display results and compare with Table 8.5
always @(posedge clock) begin
$dumpfile("tb_sbm.vcd");
$dumpvars;
$strobe("C=%b A=%b Q=%b P=%b time=%0d", M0.C, M0.A, M0.Q, M0.P, $time);
end
endmodule
| 7.172672 |
module*/
`timescale 1 ns / 1 ps
module tb_sbox();
wire [7:0] data_out;
reg [7:0] counter = 0;
reg [7:0] insert;
reg [7:0] result = 0;
integer test_vector;
initial
test_vector = $fopen("sbox_testVector.txt","r");
always
#10 counter = counter + 1;
always
#10
if (! $feof(test_vector))
begin
$fscanf(test_vector,"%h %h\n",insert,result);
end
else
$fclose(test_vector);
always@(result)
if (result == data_out)
$display("time = %3t | input = %02h | output = %02h | expected = %02h | PASS",
$time,insert,data_out,result);
else
$display("time = %8t | input = %08h | output = %08h | expected = %08h | FAIL",
$time,insert,data_out,result);
sbox DUT (
.in (insert),
.out(data_out)
);
endmodule
| 6.729021 |
module tb_sc ();
reg clk, rst;
main A (
rst,
clk
);
always #5 clk = ~clk;
initial begin
$monitor($time, " r0=%d, r1=%d, r3=%d r4=%d mem16=%d", A.regs.reg_num[0], A.regs.reg_num[1],
A.regs.reg_num[3], A.regs.reg_num[4], A.D_mem.d_mem[16]);
rst = 1'b1;
clk = 1'b0;
#1 rst = 1'b0;
repeat (12) @(negedge clk);
$finish;
end
initial begin
$dumpfile("sc.vcd");
$dumpvars(0, tb_sc);
end
endmodule
| 6.555518 |
module tb_scaler_5 ();
reg [1:0] d;
wire [3:0] q;
scaler_5 scaler0 (
.d(d),
.q(q)
);
initial begin
d <= 0;
#10 d <= 2'b01;
#10 d <= 2'b10;
#10 d <= 2'b11;
#10 $finish;
end
endmodule
| 6.988045 |
module: asic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_scandoubler;
// Inputs
reg clk12;
reg clk24;
// Outputs
wire [18:0] vramaddr;
wire [18:0] cpuramaddr;
wire hsync, vsync;
// Audio and video
wire [1:0] sam_r, sam_g, sam_b;
wire sam_bright;
// scandoubler
wire hsync_pal, vsync_pal;
wire [2:0] ri = {sam_r, sam_bright};
wire [2:0] gi = {sam_g, sam_bright};
wire [2:0] bi = {sam_b, sam_bright};
wire [2:0] r, g, b;
// Instantiate the Unit Under Test (UUT)
asic el_asic (
.clk(clk12),
.rst_n(1'b1),
.mreq_n(1'b1),
.iorq_n(1'b1),
.rd_n(1'b1),
.wr_n(1'b1),
.cpuaddr(16'h1234),
.data_from_cpu(8'h00),
.data_to_cpu(),
.data_enable_n(),
.wait_n(),
.vramaddr(),
.cpuramaddr(),
.data_from_ram(8'b10101011),
.ramwr_n(),
.romcs_n(),
.ramcs_n(),
.asic_is_using_ram(),
.ear(1'b1),
.mic(),
.beep(),
.keyboard(8'hFF),
.rdmsel(),
.disc1_n(),
.disc2_n(),
.r(sam_r),
.g(sam_g),
.b(sam_b),
.bright(sam_bright),
.csync(),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
.int_n()
);
vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
.clkvideo(clk12),
.clkvga(clk24),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
initial begin
// Initialize Inputs
clk12 = 1;
clk24 = 1;
end
always begin
clk24 = #(500/24.0) ~clk24;
end
always begin
clk12 = #(500/12.0) ~clk12;
end
endmodule
| 6.618777 |
module dummy_proc #(
parameter DATA_WIDTH = 16
) (
input wire reset,
input wire clk,
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire s_ready,
output wire [DATA_WIDTH-1:0] m_data,
output wire m_valid,
input wire m_ready
);
reg [1:0] reg_busy = 0;
always @(posedge clk) begin
// reg_busy <= {$random()};
reg_busy <= reg_busy + 1;
end
wire busy = (reg_busy != 0);
assign m_data = s_data;
assign m_valid = s_valid && !busy;
assign s_ready = m_ready && !busy;
endmodule
| 7.363305 |
module TB_scheduler_partial #(
parameter W = 59
);
// Inputs
reg clk;
reg rst;
reg wr;
reg [W-2:0] task_in;
reg [8*W-1:0] running_tasks_in;
reg action, subtract_en;
// Outputs
wire [8*W-1:0] running_tasks;
wire v_exch, busy_ready, v_active;
wire [W-2:0] task_exch;
// Instantiate the Unit Under Test (UUT)
Scheduler_partial #(W) SP (
.clk(clk),
.rst(rst),
.wr(wr),
.subtract_en(subtract_en),
.action(action),
.task_in(task_in),
.running_tasks_in((rst) ? 0 : running_tasks_in),
.v_exch(v_exch),
.v_active(v_active),
.busy_ready(busy_ready),
.task_exch(task_exch),
.running_tasks_out(running_tasks)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial forever #2 running_tasks_in <= (rst) ? 0 : running_tasks;
initial begin
// Initialize Inputs
action <= 1;
subtract_en <= 0;
wr <= 0;
rst <= 1;
#2 rst <= 0;
////// first task
wr <= 1;
task_in <= {W{$random}};
////// remaining tasks
forever begin
#2 wr <= 0;
@(negedge busy_ready) wr <= 1'b1;
task_in <= (v_active) ? task_in : {W{$random}};
end
end
endmodule
| 7.041905 |
module tb_scoreboard (
///////////////////////////////////////////
input wire C_syn_rco, // from synthesizable counter A, B, C
input wire C_syn_load,
input wire [3:0] C_syn_Q,
///////////////////////////////////////////
output reg clk,
output reg reset,
output reg [1:0] tb_mode, // choose from 00, 01, 10, 11
output reg [3:0] tb_D,
output reg tb_enable,
output reg scb_load,
output reg scb_rco, // 2^nbits - 1 = #
output reg [3:0] scb_Q
); // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire wrco, wload;
wire [3:0] wQ;
////////////// Logic
`include "./testers/driver.v"
`include "./testers/checker.v"
parameter ITERATIONS = 100;
integer log;
initial begin
$dumpfile("scoreboard.vcd");
$dumpvars(0); // "dumpping" variables
log = $fopen("./log_txt/tb_scoreboard.log");
$fdisplay(log, "time=%5d, Simulation Start", $time);
$fdisplay(log, "time=%5d, Starting Reset", $time);
//////// task initial begin
t_drv_initial();
$fdisplay(log, "time=%5d, Reset Completed", $time);
$fdisplay(log, "time=%5d, Starting Test", $time);
fork
// t_loading(ITERATIONS);
t_loading(ITERATIONS);
checker(ITERATIONS);
join
$fdisplay(log, "time=%5d, Test Completed Loading ", $time);
$fdisplay(log, "time=%5d, Simulation Completed", $time);
$fclose(log);
#200 $finish;
end
// clock logic
initial clk <= 0; // Initial value to avoid indeterminations
always #10 clk <= ~clk; // toggle every 10ns
///////////////////////////////////////////////////////////////////////////////////////////
//////////// Scoreboard
////////////
///////////////////////////////////////////////////////////////////////////////////////////
scoreboard_counter scoreboard_ind(/*AUTOINST*/
// outputs
.scb_Q (wQ),
.scb_load (wload),
.scb_rco (wrco),
// inputs
.scb_clk (clk),
.scb_reset (reset),
.scb_enable (tb_enable),
.scb_mode (tb_mode), // choose from 00, 01, 10, 11
.scb_D (tb_D)
);
always @(*) begin
scb_rco = wrco;
scb_load = wload;
scb_Q = wQ;
end
endmodule
| 7.549901 |
module tb_sdckgen;
// Local declarations
// {{{
reg clk, reset;
reg cfg_clk90, cfg_shutdown;
reg [7:0] cfg_ckspd;
wire w_ckstb, w_halfck;
wire [7:0] w_ckwide;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation
// {{{
initial begin
$dumpfile("tb_sdckgen.vcd");
$dumpvars(0, tb_sdckgen);
reset = 1'b1;
clk = 0;
forever #5 clk = !clk;
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Test script
// {{{
task capture_beats;
begin
repeat (5) begin
wait (w_ckstb);
@(posedge clk);
end
end
endtask
initial begin
{cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h0fc;
repeat (5) @(posedge clk) @(posedge clk) reset <= 0;
// 100kHz (10us)
capture_beats;
// 200 kHz (5us)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h07f;
capture_beats;
// 400 kHz (2.52us)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h041;
capture_beats;
// 1MHz (1us)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h01b;
capture_beats;
// 5MHz (200ns)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h007;
capture_beats;
// 12MHz (80ns)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h004;
capture_beats;
// 25MHz (40ns)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h003;
capture_beats;
// 50MHz (20ns)
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h002;
capture_beats;
// 100MHz
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h001;
capture_beats;
// 200MHz
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h000;
capture_beats;
// 25MHz, CLK90
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h103;
capture_beats;
// 25MHz, CLK90
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h102;
capture_beats;
// 100MHz, CLK90
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h101;
capture_beats;
// 200MHz, CLK90
@(posedge clk) {cfg_shutdown, cfg_clk90, cfg_ckspd} = 10'h100;
capture_beats;
$finish;
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Module under test
// {{{
sdckgen u_ckgen (
// {{{
.i_clk(clk),
.i_reset(reset),
//
.i_cfg_clk90(cfg_clk90),
.i_cfg_ckspd(cfg_ckspd),
.i_cfg_shutdown(cfg_shutdown),
//
.o_ckstb(w_ckstb),
.o_hlfck(w_halfck),
.o_ckwide(w_ckwide)
// }}}
);
// }}}
endmodule
| 7.075031 |
module tb_sdio;
// Local declarations
// {{{
parameter [1:0] OPT_SERDES = 1'b1;
parameter [1:0] OPT_DDR = 1'b1;
parameter [0:0] OPT_VCD = 1'b0;
localparam AW = 3, DW = 32;
localparam VCD_FILE = "trace.vcd";
reg [2:0] ckcounter;
wire clk, hsclk;
reg reset;
wire bfm_cyc, bfm_stb, bfm_we, bfm_stall, bfm_ack, bfm_err;
wire [AW-1:0] bfm_addr;
wire [DW-1:0] bfm_data, bfm_idata;
wire [DW/8-1:0] bfm_sel;
wire sd_cmd, sd_ck;
wire [3:0] sd_dat;
wire interrupt;
wire [31:0] scope_debug;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Clock/reset generation
// {{{
localparam realtime CLK_PERIOD = 10.0; // 100MHz
initial begin
ckcounter = 0;
forever #(CLK_PERIOD / 8) ckcounter = ckcounter + 1;
end
assign hsclk = ckcounter[0];
assign clk = ckcounter[2];
initial begin
reset <= 0;
@(posedge hsclk) reset <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) reset <= 0;
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Unit under test
// {{{
sdio_top #(
// {{{
.LGFIFO(12),
.NUMIO(4),
.MW(32),
.OPT_SERDES(OPT_SERDES),
.OPT_DDR(OPT_DDR),
.OPT_CARD_DETECT(0),
.LGTIMEOUT(10),
.OPT_EMMC(1'b0)
// }}}
) u_sdio (
// {{{
.i_clk(clk),
.i_reset(reset),
.i_hsclk(hsclk),
//
.i_wb_cyc(bfm_cyc),
.i_wb_stb(bfm_stb),
.i_wb_we(bfm_we),
.i_wb_addr(bfm_addr),
.i_wb_data(bfm_data),
.i_wb_sel(bfm_sel),
.o_wb_stall(bfm_stall),
.o_wb_ack(bfm_ack),
.o_wb_data(bfm_idata),
//
.o_ck(sd_ck),
.i_ds(1'b0),
.io_cmd(sd_cmd),
.io_dat(sd_dat),
.i_card_detect(1'b1),
.o_int(interrupt),
.o_debug(scope_debug)
// }}}
);
assign bfm_err = 1'b0;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Wishbone bus functional model
// {{{
wb_bfm #(
.AW(AW),
.DW(DW),
.LGFIFO(4)
) u_bfm (
.i_clk(clk),
.i_reset(reset),
//
.o_wb_cyc(bfm_cyc),
.o_wb_stb(bfm_stb),
.o_wb_we(bfm_we),
.o_wb_addr(bfm_addr),
.o_wb_data(bfm_data),
.o_wb_sel(bfm_sel),
.i_wb_stall(bfm_stall),
.i_wb_ack(bfm_ack),
.i_wb_data(bfm_idata),
.i_wb_err(bfm_err)
);
// }}}
////////////////////////////////////////////////////////////////////////
//
// SDIO Device model
// {{{
mdl_sdio u_sdcard (
.sd_clk(sd_ck),
.sd_cmd(sd_cmd),
.sd_dat(sd_dat)
);
// }}}
////////////////////////////////////////////////////////////////////////
//
// VCD generation
// {{{
initial
if (OPT_VCD && VCD_FILE != 0) begin
$dumpfile(VCD_FILE);
$dumpvars(0, tb_sdio);
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Test script
// {{{
reg error_flag;
`include `SCRIPT
initial begin
error_flag = 1'b0;
@(posedge clk);
wait (!reset);
@(posedge clk);
testscript;
if (error_flag) begin
$display("TEST FAIL!");
end else begin
$display("Test pass");
end
$finish;
end
// }}}
endmodule
| 7.380832 |
module tb_sdp_ram ();
parameter MEM_ADDR_WIDTH = 9;
parameter MEM_WORD_WIDTH = 64;
parameter MEM_WR_MASK_WIDTH = MEM_WORD_WIDTH / 8;
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 100; // clk cycle
parameter rst_delay = 20;
parameter rst_period = 5;
parameter STREAM_LEN = 512;
reg clk;
reg rst_n;
reg [ MEM_ADDR_WIDTH-1:0] rd_addr;
reg [ MEM_ADDR_WIDTH-1:0] wr_addr;
reg [ MEM_WORD_WIDTH-1:0] wr_data_in;
reg [MEM_WR_MASK_WIDTH-1:0] wr_data_mask;
reg wr_data_en;
wire [ MEM_WORD_WIDTH-1:0] rd_data_out;
// Variables for Simulation
integer in_file, out_file;
integer ii, jj;
integer temp;
// clk generate
initial begin
#(clk_period) clk = 0;
forever begin
#(clk_period / 2) clk = ~clk;
end
end
// rst generate
initial begin
#(clk_period) rst_n = 1;
#(clk_period * rst_delay) rst_n = 0;
#(clk_period * rst_period) rst_n = 1;
end
// Sim data generate
initial begin
$vcdpluson;
end
reg [MEM_WORD_WIDTH-1:0] input_data[STREAM_LEN-1:0];
// Load the input file
initial begin
in_file = $fopen("../../testdata/input_sdp_ram.txt", "r");
out_file = $fopen("../../testdata/output_sdp_ram.txt", "w");
end
initial begin
for (ii = 0; ii < STREAM_LEN; ii = ii + 1) begin
temp = $fscanf(in_file, "%x", input_data[ii]);
end
end
initial begin
#(clk_period * start_delay);
wr_addr = -1;
rd_addr = -1;
wr_data_mask = 8'b11111111;
// Send the data and enable signal
for (jj = 0; jj < STREAM_LEN; jj = jj + 1) begin
@(posedge clk);
wr_addr <= wr_addr + 1;
wr_data_en <= 1;
wr_data_in <= input_data[jj];
end
@(posedge clk);
wr_data_en <= 0;
#(clk_period * 10);
// Begin read from BRAM
for (jj = 0; jj < STREAM_LEN; jj = jj + 1) begin
@(posedge clk);
rd_addr <= rd_addr + 1;
if (jj > 1) begin
$fdisplay(out_file, "%x", rd_data_out);
end
end
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
#(clk_period * 10);
$finish;
end // initial begin
// DUT instantition
sdp_ram u_sdp_ram (
.clk(clk),
.rst_n(rst_n),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.wr_data_in(wr_data_in),
.wr_data_mask(wr_data_mask),
.wr_data_en(wr_data_en),
.rd_data_out(rd_data_out)
);
endmodule
| 7.383146 |
module tb_sdp_ram_rdonly ();
parameter MEM_ADDR_WIDTH = 9;
parameter MEM_WORD_WIDTH = 64;
parameter MEM_WR_MASK_WIDTH = MEM_WORD_WIDTH / 8;
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 100; // clk cycle
parameter rst_delay = 20;
parameter rst_period = 5;
parameter STREAM_LEN = 512;
localparam MIF_FILE_NAME = "../../testdata/ram_init.mif";
reg clk;
reg rst_n;
reg [ MEM_ADDR_WIDTH-1:0] rd_addr;
reg [ MEM_ADDR_WIDTH-1:0] wr_addr;
reg [ MEM_WORD_WIDTH-1:0] wr_data_in;
reg [MEM_WR_MASK_WIDTH-1:0] wr_data_mask;
reg wr_data_en;
wire [ MEM_WORD_WIDTH-1:0] rd_data_out;
// Variables for Simulation
integer in_file, out_file;
integer ii, jj;
integer temp;
// clk generate
initial begin
#(clk_period) clk = 0;
forever begin
#(clk_period / 2) clk = ~clk;
end
end
// rst generate
initial begin
#(clk_period) rst_n = 1;
#(clk_period * rst_delay) rst_n = 0;
#(clk_period * rst_period) rst_n = 1;
end
// Sim data generate
initial begin
$vcdpluson;
end
reg [MEM_WORD_WIDTH-1:0] input_data[STREAM_LEN-1:0];
// Load the input file
initial begin
out_file = $fopen("../../testdata/output_sdp_ram_rdonly.txt", "w");
end
initial begin
#(clk_period * start_delay);
wr_addr = -1;
rd_addr = -1;
wr_data_mask = 8'b11111111;
wr_data_en <= 0;
@(posedge clk);
#(clk_period * 10);
// Begin read from BRAM
for (jj = 0; jj < STREAM_LEN; jj = jj + 1) begin
@(posedge clk);
rd_addr <= rd_addr + 1;
if (jj > 1) begin
$fdisplay(out_file, "%x", rd_data_out);
end
end
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
#(clk_period * 10);
$finish;
end // initial begin
// DUT instantition
sdp_ram #(
.MIF_FILE(MIF_FILE_NAME)
) u_sdp_ram (
.clk(clk),
.rst_n(rst_n),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.wr_data_in(wr_data_in),
.wr_data_mask(wr_data_mask),
.wr_data_en(wr_data_en),
.rd_data_out(rd_data_out)
);
endmodule
| 7.464556 |
module tb_sdram_ctrl ();
reg clk_100m;
reg clk_100m_shift;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 100 MHz clk and clk_shift:
initial begin
clk_100m = 1'b1;
forever begin
#5 clk_100m = ~clk_100m;
end
end
initial begin
clk_100m_shift = 1'b0;
#7
forever begin
#5 clk_100m_shift = ~clk_100m_shift;
end
end
wire [15:0] sdr_dq;
wire [12:0] sdr_addr;
wire [1:0] sdr_ba;
wire [3:0] sdr_cmd;
wire [1:0] sdr_dqm;
reg [31:0] in_addr;
reg in_wr_req;
reg [3:0] in_wr_dqm;
reg [31:0] in_wr_data;
reg in_rd_req;
initial begin
in_wr_req = 1'b0;
in_wr_data = 31'b0;
in_addr = 31'b0;
in_wr_dqm = 4'b0000;
in_rd_req = 1'b0;
end
initial begin
#429
// write data 0xa1b2c3d4 to address 32'b10_1111101000000_100000110_0:
// BA = 2, ROW = 8000, COL = 262
in_wr_req = 1'b1;
in_addr = 32'b10_1111101000000_100000110_0;
in_wr_data = 32'ha1b2c3d4;
in_wr_dqm = 4'b0000;
#40 in_wr_req = 1'b0;
end
initial begin
#489
// write data 0x??e5f6?? to address 32'b10_1111101000000_100000110_0:
// BA = 2, ROW = 8000, COL = 262
in_wr_req = 1'b1;
in_addr = 32'b10_1111101000000_100000110_0;
in_wr_data = 32'h00e5f600;
in_wr_dqm = 4'b1001;
#40 in_wr_req = 1'b0;
end
initial begin
#568
// read data from address 32'b10_1111101000000_100000110_0:
// BA = 2, ROW = 8000, COL = 262
in_rd_req = 1'b1;
in_addr = 32'b10_1111101000000_100000110_0;
#40 in_rd_req = 1'b0;
end
initial begin
#956
// read data from address 32'b10_1111101000000_100000110_0:
// BA = 2, ROW = 8000, COL = 262
in_rd_req = 1'b1;
in_addr = 32'b10_1111101000000_100000110_0;
#200 in_rd_req = 1'b0;
end
sdram_ctrl #(
.SDR_TPOWERUP(200), // speed power up from 200 us to 200 ns
.SDR_INIT_AREF_COUNT(2), // aref x2 when init
.SDR_REFRESH_CYCLE_TIME(6_400_000) // set refresh cycle to 6.4 ms to speed up test
) component (
.clk (clk_100m),
.rst_n(rst_n),
// connect in top:
.in_addr(in_addr),
.in_wr_req(in_wr_req),
.in_wr_data(in_wr_data),
.in_wr_dqm(in_wr_dqm),
.in_rd_req(in_rd_req),
// connect to SDR:
.out_wr_dqm(sdr_dqm),
.inout_data(sdr_dq),
.cmd(sdr_cmd),
.ba(sdr_ba),
.addr(sdr_addr)
);
mt48lc16m16a2 sdram_inst (
.Dq(sdr_dq),
.Addr(sdr_addr),
.Ba(sdr_ba),
.Clk(clk_100m_shift),
.Cke(1'b1),
.Cs_n(sdr_cmd[3]),
.Ras_n(sdr_cmd[2]),
.Cas_n(sdr_cmd[1]),
.We_n(sdr_cmd[0]),
.Dqm(sdr_dqm)
);
initial begin
$dumpfile("tb_sdram_ctrl.vcd");
$dumpvars(0, component);
$dumpvars(0, sdram_inst);
#3000 $finish;
end
endmodule
| 6.548358 |
module tb_sdram_init ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
//clk_gen
wire clk_50m; //PLL输出50M时钟
wire clk_100m; //PLL输出100M时钟
wire clk_100m_shift; //PLL输出100M时钟,相位偏移-30deg
wire locked; //PLL时钟锁定信号
wire rst_n; //复位信号,低有效
//sdram_init
wire [ 3:0] init_cmd; //初始化阶段指令
wire [ 1:0] init_ba; //初始化阶段L-Bank地址
wire [12:0] init_addr; //初始化阶段地址总线
wire init_end; //初始化完成信号
//reg define
reg sys_clk; //系统时钟
reg sys_rst_n; //复位信号
//defparam
//重定义仿真模型中的相关参数
defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽
defparam sdram_model_plus_inst.data_bits = 16; //数据位宽
defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽
defparam sdram_model_plus_inst.mem_sizes = 2 * 1024 * 1024; //L-Bank容量
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//rst_n:复位信号
assign rst_n = sys_rst_n & locked;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- clk_gen_inst -------------
clk_gen clk_gen_inst (
.inclk0(sys_clk),
.areset(~sys_rst_n),
.c0 (clk_50m),
.c1 (clk_100m),
.c2 (clk_100m_shift),
.locked(locked)
);
//------------- sdram_init_inst -------------
sdram_init sdram_init_inst (
.sys_clk (clk_100m),
.sys_rst_n(rst_n),
.init_cmd (init_cmd),
.init_ba (init_ba),
.init_addr(init_addr),
.init_end (init_end)
);
//-------------sdram_model_plus_inst-------------
sdram_model_plus sdram_model_plus_inst (
.Dq (),
.Addr (init_addr),
.Ba (init_ba),
.Clk (clk_100m_shift),
.Cke (1'b1),
.Cs_n (init_cmd[3]),
.Ras_n(init_cmd[2]),
.Cas_n(init_cmd[1]),
.We_n (init_cmd[0]),
.Dqm (2'b0),
.Debug(1'b1)
);
endmodule
| 7.021773 |
module tb_sdrd_SPIctrl;
/*----------------------------------*/
/* parameters */
/*----------------------------------*/
parameter P_CYCLE_CLK = 10;
parameter STB = 1;
parameter outfile = "output.txt";
/*----------------------------------*/
/* regsters */
/*----------------------------------*/
/*----------------------------------*/
/* regs and wires */
/*----------------------------------*/
reg r_clk;
reg r_rst_x;
reg [ 31:0] r_spin_access_adr;
reg [ 1:0] r_spin_datatype;
reg r_do;
wire w_spi_busy;
wire w_spi_init;
wire [255:0] w_spiout_fatprm;
wire w_spiout_fat_valid;
wire w_spiout_rgbwr;
wire [ 63:0] w_spiout_rgbdata;
wire w_cs;
wire w_di;
wire w_gnd1;
wire w_vcc;
wire w_sclk;
wire w_gnd2;
/*----------------------------------*/
/* testmodule */
/*----------------------------------*/
sdrd_SPIctrl u_sdrd_SPIctrl (
.CLK (r_clk),
.RST_X (r_rst_x),
.SPIN_ACCESS_ADR (r_spin_access_adr),
.SPIN_DATATYPE (r_spin_datatype),
.DO (w_do),
.SPI_BUSY (w_spi_busy),
.SPI_INIT (w_spi_init),
.SPIOUT_FATPRM (w_spiout_fatprm),
.SPIOUT_FAT_VALID(w_spiout_fat_valid),
.SPIOUT_RGBWR (w_spiout_rgbwr),
.SPIOUT_RGBDATA (w_spiout_rgbdata),
.CS (w_cs),
.DI (w_di),
.GND1 (w_gnd1),
.VCC (w_vcc),
.SCLK (w_sclk),
.GND2 (w_gnd2)
);
tb_sdcard sdcard (
.CS (w_cs),
.DI (w_di),
.GND1(w_gnd1),
.VCC (w_vcc),
.CLK (w_sclk),
.GND2(w_gnd2),
.DO (w_do)
);
/*----------------------------------*/
/* generate clk */
/*----------------------------------*/
always begin
#(P_CYCLE_CLK / 2) r_clk = ~r_clk;
end
/*----------------------------------*/
/* body */
/*----------------------------------*/
initial begin
r_clk = 0;
r_rst_x = 0;
r_spin_access_adr = 0;
r_spin_datatype = 0;
r_do = 0;
#(STB) r_rst_x = 1;
#(P_CYCLE_CLK) r_spin_access_adr = 32'h00;
r_spin_datatype = 2'd2;
end
endmodule
| 7.058725 |
module: sdtest
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_sdtest;
// Inputs
reg clk;
reg rst;
reg spi_do;
// Outputs
wire spi_clk;
wire spi_di;
wire spi_cs;
wire test_in_progress;
wire test_result;
// Instantiate the Unit Under Test (UUT)
sdtest uut (
.clk(clk),
.rst(rst),
.spi_clk(spi_clk),
.spi_di(spi_di),
.spi_do(spi_do),
.spi_cs(spi_cs),
.test_in_progress(test_in_progress),
.test_result(test_result)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
spi_do = 1;
// Wait 100 ns for global reset to finish
// Add stimulus here
@(negedge test_in_progress);
repeat (16)
@(posedge clk);
$finish;
end
always begin
clk = #5 ~clk;
end
endmodule
| 6.772562 |
module tb_sd_send;
reg ex_clk, sd_clk, reset, send_en;
reg [37:0] cmd_content;
reg [47:0] correct_send;
wire sd_cmd, sending;
wire [3:0] sd_dat;
integer index;
sd_send uut (
ex_clk,
sd_clk,
reset,
send_en,
cmd_content,
sending,
sd_cmd,
sd_dat
);
task RESET;
begin
$display("\n-----System Reset-----\n");
reset = 1;
#10;
reset = 0;
#10;
end
endtask
task CHECK_SEND;
begin
if (sending) begin
if (correct_send[index] != sd_cmd) begin
$display("[ERR] SD_CMD (%b) does not match expected value (%b)", sd_cmd,
correct_send[index]);
$stop;
end else index = index - 1;
end else index = 47;
end
endtask
always begin
sd_clk = ~sd_clk;
ex_clk = ~ex_clk;
#5;
end
always @(posedge sd_clk) CHECK_SEND;
always @(negedge sd_clk)
$display(
"state: %b, crc_load: %b, crc: %b, crc_ready: %b, crc_index: %0d, index: %0d, tx_index: %0d, sd_cmd: %0b, uut.cmd_token: %b, time: %0d",
uut.PS,
uut.crc_load,
uut.cmd_crc,
uut.crc_ready,
uut.crc_gen.index,
index,
uut.transmitter.index,
sd_cmd,
uut.cmd_token,
$time
);
initial begin
// $monitor("state: %b, crc_prep: %b, crc: %b, crc_ready: %b, crc_index: %0d, index: %0d, tx_index: %0d, sd_cmd: %0b, uut.cmd_token: %b, time: %0d",
// uut.PS, uut.crc_prep, uut.cmd_crc, uut.crc_ready, uut.crc_gen.index, index, uut.transmitter.index, sd_cmd, uut.cmd_token, $time);
sd_clk = 0;
ex_clk = 0;
reset = 0;
send_en = 0;
cmd_content = 0;
correct_send = 0;
#2; // Don't want everything changing on edge of clk
RESET;
$display("\n-----Testing CMD0-----\n");
cmd_content = 38'b0;
correct_send = 48'b010000000000000000000000000000000000000010010101;
send_en = 1'b1;
#20;
send_en = 1'b0;
#1000;
RESET;
$display("\n-----TESTING CMD17-----\n");
cmd_content = 38'b01000100000000000000000000000000000000;
correct_send = 48'b010101000100000000000000000000000000000001010101;
send_en = 1'b1;
#20;
send_en = 1'b0;
#1000;
$finish(2);
end
endmodule
| 7.103496 |
module tb_segment7;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
lab3ex uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for (
i = 0; i < 30; i = i + 1
) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end
endmodule
| 6.669573 |
module tb_seg_595_static ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的时钟输入
wire ds; //串行数据输入
wire oe; //输出使能信号
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//对sys_clk,sys_rst_n赋初始值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#100 sys_rst_n <= 1'b1;
end
//clk:产生时钟
always #10 sys_clk <= ~sys_clk;
//重新定义参数值，缩短仿真时间
defparam seg_595_static_inst.seg_static_inst.CNT_WAIT_MAX = 10;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------seg_595_static_inst-------------
seg_595_static seg_595_static_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低电平有效
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //输出使能信号
);
endmodule
| 8.260895 |
module tb_seg_dynamic ();
//input
reg sys_clk;
reg sys_rst_n;
reg [19:0] data;
reg [ 5:0] point;
reg sign;
reg seg_en;
//output
wire [ 5:0] sel;
wire [ 7:0] seg;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
data <= 20'd0;
point <= 6'b0;
sign <= 1'b0;
seg_en <= 1'b0;
#30 sys_rst_n <= 1'b1;
data <= 20'd9876;
point <= 6'b000_010;
sign <= 1'b1;
seg_en <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
defparam seg_dynamic_inst.CNT_MAX = 20'd5;
seg_dynamic seg_dynamic_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.data (data),
.point (point),
.sign (sign),
.seg_en (seg_en),
.sel(sel),
.seg(seg)
);
endmodule
| 7.091586 |
module tb_seg_static ();
// seg_static Inputs
reg sys_clk ;
reg sys_rst_n ;
// seg_static Outputs
wire [5:0] sel;
wire [7:0] seg;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
seg_static #(
.CNT_MAX(25'd24)
) seg_static_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.sel(sel),
.seg(seg)
);
endmodule
| 7.338977 |
module tb_selector ();
reg [2:0] c_sel;
reg [7:0] Result;
reg [7:0] Datain_Bus;
reg [7:0] num;
reg [7:0] Adress_Instruction_Bus;
reg [7:0] Ry;
wire [7:0] selector;
selector uut (
.c_sel(c_sel),
.Result(Result),
.Datain_Bus(Datain_Bus),
.num(num),
.Ry(Ry),
.Adress_Instruction_Bus(Adress_Instruction_Bus),
.selector(selector)
);
initial begin
c_sel = 3'd0;
Result = 8'd0;
Datain_Bus = 8'd1;
num = 8'd2;
Ry = 8'd4;
Adress_Instruction_Bus = 8'd3;
#2 c_sel = 3'd1;
#2 c_sel = 3'd2;
#2 c_sel = 3'd3;
#2 c_sel = 3'd4;
end
endmodule
| 7.063898 |
module tb_sender (
input clk,
input rst,
output reg [3:0] data,
output reg en,
input ack,
input [7:0] gap_from,
input [7:0] gap_to
);
reg can_send;
always @(posedge clk or posedge rst)
if (rst) can_send <= 1;
else if (ack) can_send <= 1;
else if (en) can_send <= 0;
reg [7:0] cnt;
always @(posedge clk or posedge rst)
if (rst) begin
data <= 0;
en <= 0;
cnt <= 0;
end else if (cnt != 0) begin
cnt <= cnt - 1;
en <= 0;
end else if (!en && can_send) begin
$display("Sending %d", data + 1);
data <= data + 1;
en <= 1;
cnt <= $urandom_range(gap_from, gap_to);
end else begin
en <= 0;
end
endmodule
| 7.501668 |
module tb_send_control;
reg clk, busy, rst;
wire [15:0] segment_num;
wire [7:0] txid, txid_inter, aux;
wire start_sending;
reg start_frame, oneframe_done;
send_control uut (
.clk125MHz(clk),
.RST(rst),
// .switches(8'b01010000),
// .switches(8'b01011111),
.switches(8'b01010000),
.busy(busy),
.start_frame(start_frame),
.oneframe_done(oneframe_done),
// output
.segment_num_inter(segment_num),
.txid_inter(txid_inter),
.aux_inter(aux),
.redundancy(),
.start_sending(start_sending)
);
initial begin
$dumpfile("send_control.vcd");
$dumpvars(0, tb_send_control);
end
initial begin
clk = 0;
busy = 0;
oneframe_done = 0;
start_frame = 0;
rst = 0;
#20;
start_frame = 1;
#8;
start_frame = 0;
#4000;
oneframe_done = 1;
#8;
oneframe_done = 0;
#4000; // stop here.
#20;
start_frame = 1;
#8;
start_frame = 0;
#4000;
oneframe_done = 1;
#8;
oneframe_done = 0;
#2000;
$finish;
end
always #4 begin
clk <= !clk;
end
endmodule
| 6.786488 |
module tb ();
reg D_IN;
reg RST;
reg CLK;
wire MATCH;
integer fd_in;
integer fd_out;
integer test;
integer fp;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
fd_out = $fopen("./seq.out", "w");
fd_in = $fopen("./pattern.in", "r");
$fmonitor(fd_out, "At time %t ns, CLK=%d, RST=%d, D_IN=%d, MATCH=%d", $time, CLK, RST, D_IN,
MATCH);
RST = 1;
CLK = 1;
#8 RST = 0;
#1000 $fclose(fd_out);
end
always @(posedge CLK) begin
fp = $fscanf(fd_in, "%1b", D_IN);
end
seq_detect U_SEQ_DETECT (
D_IN,
CLK,
RST,
MATCH
);
endmodule
| 7.002324 |
module tb_seq_detect ();
wire p_flag;
reg p_din, p_clk, p_rst_n;
reg [35:0] data = 36'b0000_1100_0010_0110_1001_1011_0010_0001_1101;
seq_detect dec (
.flag (p_flag),
.clk (p_clk),
.din (p_din),
.rst_n(p_rst_n)
);
initial begin
p_clk = 1'b1;
forever #5 p_clk = ~p_clk;
end
integer k;
initial begin
p_rst_n = 1'b0;
p_din = 1'bx;
#7 p_rst_n = 1'b1;
for (k = 0; k < 36; k = k + 1) begin
#10;
p_din = data[35];
data = data << 1;
end
#20 $finish;
end
initial begin
$monitor($time, " rst = %b, din = %b, flag = %b", p_rst_n, p_din, p_flag);
$dumpfile("tb_seq_detect.vcd");
$dumpvars(0, tb_seq_detect);
end
endmodule
| 7.61768 |
module tb_serialAdder4bit();
wire [3:0] Acc;
wire SI2;
reg SI;
reg clr, clk, ShftCtrl;
integer i;
serialAdder_4bit sa( Acc,SI2, SI, ShftCtrl, clr, clk );
always @(posedge clk) begin
$display("ShftCtrl = %b ", ShftCtrl, " SI = %b ", SI," SI2:= ",SI2 ," Acc = %b ", Acc, "Clk: = ",clk," dff_out = %b ", sa.dff.q, "time = ", $time);
end
reg [19:0] sequence;
initial begin
ShftCtrl = 1;
clk = 1'b0;
clr = 1'b0;
#2 clr = 1'b1;
sequence = 20'b0100_0011_0010_0001_0000;
for(i=0; i<24; i= i+1) begin
if( i<20 )
SI = sequence[i];
#2 clk = 1'b1;
#2 clk = 1'b0;
end
end
endmodule
| 6.578503 |
module tb_SerialAdd;
reg clk, reset, a, b;
wire c_out;
wire [3:0] s_out;
SerialAdd SA (
a,
b,
clk,
reset,
c_out,
s_out
);
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
a = 0;
b = 0;
reset = 1;
//a=1111,b=1010,s=1001,c=1
#20 reset = 0;
a = 1;
b = 0;
#10 a = 1;
b = 1;
#10 a = 1;
b = 0;
#10 a = 1;
b = 1;
#10 reset = 1;
//a=1000,b=0011,s=1011,c=0
#20 reset = 0;
a = 0;
b = 1;
#10 a = 0;
b = 1;
#10 a = 0;
b = 0;
#10 a = 1;
b = 0;
#10 reset = 1;
#10 $finish;
end
endmodule
| 6.937421 |
module: serializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_serializer;
wire [7:0] data;
wire clk;
wire send;
wire txd;
serializer_gen_test generator (
.data(data),
.send(send),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
serializer #(
.WIDTH(8)
)
uut(
.data(data),
.rst(0),
.clk(clk),
.send(send),
.txd(txd)
);
serializer_check_test writer (
.clk(clk),
.txd(txd)
);
endmodule
| 7.107914 |
module name: tb_Serial_Adder
Created By: Ard Aunario
Date Created: 9/13/19
Description: Testbench for Serial_Adder
Revised:
********************************************************
*******************************************************/
`timescale 1 ns / 1 ps
`define CLK_PER 10
module tb_Serial_Adder();
parameter SIZE = 8;
reg CLK, RST, START;
reg [SIZE-1:0] A, B;
wire [SIZE:0] SUM;
/* UUT - Serial Adder */
Serial_Adder UUT(SUM, CLK, RST, START, A, B);
/* Clock */
initial begin
CLK = 1'b0;
forever #(`CLK_PER/2) CLK = ~CLK;
end
/* Monitor */
initial
$monitor("RST = %b START = %b A = %d B = %d CURRENT_STATE = %b --- SUM = %d",
RST,
START,
A,
B,
UUT.FSM_1.CURRENT_STATE,
SUM
);
/* Initial */
initial begin
RST = 0; START = 0; A = 'd143; B = 'd57;
#(`CLK_PER) RST = 1; START = 1;
#(`CLK_PER * 10) START = 0; A = 'd67; B = 'd33;
#(`CLK_PER * 2) START = 1;
#(`CLK_PER * 12);
end
endmodule
| 7.372984 |
module tb_serial_crc_ccitt;
reg clk;
reg reset;
reg enable;
reg init;
reg data_in;
wire [15:0] crc_out;
serial_crc_ccitt dut (
clk,
reset,
enable,
init,
data_in,
crc_out
);
initial begin
clk = 0;
data_in = 0;
init = 0;
enable = 1;
forever #10 clk = ~clk;
end
task resetit;
begin
@(negedge clk) reset = 1'b1;
@(negedge clk) reset = 1'b0;
end
endtask
initial begin
resetit;
data_in = 1'b0;
repeat (30) begin
data_in = {$random} % 2;
#10;
end
#10 $stop;
end
initial begin
$monitor("data_in=%b, crc_out=%b", data_in, crc_out);
end
endmodule
| 7.130267 |
module tb_serial_transmit;
localparam LEN_CODED_BLOCK = 66;
reg [9:0] counter;
reg clock;
reg reset;
reg block_clock;
reg tx_clock;
reg [LEN_CODED_BLOCK-1 : 0] data;
wire tx_bit;
initial begin
clock = 0;
reset = 1;
counter = 0;
data = {LEN_CODED_BLOCK{1'b0}};
#6 reset = 0;
#4 block_clock = 1;
data = 66'h2_0f_0f_0f_0f_0f_0f_0f_0f;
#2 block_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
#2 tx_clock = 0;
#2 tx_clock = 1;
end
always #2 clock = ~clock;
serial_transmitter #(
.LEN_CODED_BLOCK(LEN_CODED_BLOCK)
) u_serial_transmitter (
.i_clock (clock),
.i_reset (reset),
.i_data (data),
.i_block_clock (block_clock),
.i_transmit_clock(tx_clock),
.o_tx_bit (tx_bit)
);
endmodule
| 6.66482 |
module TB_serial_uart();
wire serial_in;
wire serial_out;
wire [7:0] data_out;
wire busy;
wire gotdata;
reg ostrb;
reg clk;
reg [7:0] testval;
reg reset;
assign serial_in=serial_out;
serial_uart #(
) uart(.serial_in(serial_in), .serial_out(serial_out), .clk(clk), .reset(reset),
.as_data_i(testval), .as_data_o(data_out), .as_dstrb_i(ostrb), .as_busy_o(busy), .as_dstrb_o(gotdata));
reg [5:0] sim_cnt;
reg [63:0]words_sent;
reg [63:0]words_received;
initial begin
$dumpvars;
clk<=1'b0;
words_sent<=64'b0;
words_received<=64'b0;
reset<=1'b1;
sim_cnt<=6'b0;
#2 reset<=1'b0;
`ifdef DEBUG
$display("starting sim");
`endif
#`SIMLENGTH
if (words_sent - words_received <= 1)
$display("PASSED");
else
$display("FAILED: lost data");
$finish;
end
always begin
#1 clk <=~clk;
end
reg busy_cleared;
reg gotdata_cleared;
always @(posedge clk) begin
if (reset) begin
busy_cleared<=1'b1;
testval<=8'b0;
ostrb<=1'b0;
gotdata_cleared<=1'b1;
end else begin
if (~busy & busy_cleared) begin
`ifdef DEBUG
$display("sent word: %d",testval +1'b1);
`endif
ostrb<=1'b1;
busy_cleared<=1'b0;
sim_cnt<=sim_cnt + 6'b1;
testval<=testval+8'b1;
words_sent<=words_sent + 64'b1;
end else if (busy) begin
ostrb<=1'b0;
busy_cleared<=1'b1;
end
if (gotdata & gotdata_cleared) begin
`ifdef DEBUG
$display("got word: %d",data_out);
`endif
words_received<=words_received + 64'b1;
if (!(testval === data_out)) begin
$display("FAILED: data mismatch");
$finish;
end
gotdata_cleared<=1'b0;
end else if (~gotdata) begin
gotdata_cleared<=1'b1;
end
end
end
endmodule
| 6.604073 |
module tb_sete_segmentos;
//Input
reg [3:0] Num_Binario;
//Outputs
wire Segmento_A, Segmento_B, Segmento_C, Segmento_D, Segmento_E, Segmento_F, Segmento_G;
integer i;
//Instancia a unidade a ser testada
sete_segmentos uut (
.Num_Binario(Num_Binario),
.Segmento_A (Segmento_A),
.Segmento_B (Segmento_B),
.Segmento_C (Segmento_C),
.Segmento_D (Segmento_D),
.Segmento_E (Segmento_E),
.Segmento_F (Segmento_F),
.Segmento_G (Segmento_G)
);
//Inputs de teste
initial begin
for (i = 0; i < 16; i = i + 1) begin
Num_Binario = i;
#20;
end
end
endmodule
| 6.529645 |
module tb_set_alarm;
// set_alarm Parameters
parameter PERIOD = 10;
// set_alarm Inputs
reg signal = 0;
reg load = 0;
reg moveRightBtn = 0;
reg moveLeftBtn = 0;
reg incrementBtn = 0;
reg decrementBtn = 0;
// set_alarm Outputs
wire [3:0] load_seconds;
wire [2:0] load_minutes;
// initial
// begin
// forever #(PERIOD/2) clk=~clk;
// end
initial begin
forever #(PERIOD) signal = ~signal;
end
// initial
// begin
// #(PERIOD*2) rst_n = 1;
// end
initial begin
#(PERIOD * 10) load = 1;
#(PERIOD * 20) load = 0;
end
initial begin
#(PERIOD * 11) incrementBtn = 1;
#(PERIOD) incrementBtn = 0;
#(PERIOD * 3) incrementBtn = 1;
#(PERIOD) incrementBtn = 0;
end
initial begin
#(PERIOD * 13) moveRightBtn = 1;
#(PERIOD) moveRightBtn = 0;
end
set_alarm u_set_alarm (
.signal (signal),
.load (load),
.moveRightBtn(moveRightBtn),
.moveLeftBtn (moveLeftBtn),
.incrementBtn(incrementBtn),
.decrementBtn(decrementBtn),
.load_seconds(load_seconds[3:0]),
.load_minutes(load_minutes[2:0])
);
initial begin
$finish;
end
endmodule
| 7.849587 |
module: SignExtensionUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_SEU;
// Inputs
reg [25:0] instruction;
reg [1:0] seuSignal;
// Outputs
wire [63:0] seuOutput;
// Instantiate the Unit Under Test (UUT)
SignExtensionUnit uut (
.instruction(instruction),
.seuSignal(seuSignal),
.seuOutput(seuOutput)
);
initial begin
// Initialize Inputs
instruction = 12'b000110001111;
seuSignal = 00;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
instruction = 26'b00000000000000000000111111;
seuSignal = 01;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
instruction = 19'b1000000000000000000;
seuSignal = 10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
instruction = 9'b100010000;
seuSignal = 11;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.426185 |
module
`timescale 1ns/1ns
module tb_Seven_Seg();
reg [3:0] Seg_in;
wire [6:0] Seg_out;
Seven_Seg DUT_Seven_Seg(Seg_in, Seg_out);
initial
begin
#5 Seg_in=4'b0000;
#5 Seg_in=4'b0001;
#5 Seg_in=4'b0010;
#5 Seg_in=4'b0011;
#5 Seg_in=4'b0100;
#5 Seg_in=4'b0101;
#5 Seg_in=4'b0110;
#5 Seg_in=4'b0111;
#5 Seg_in=4'b1000;
#5 Seg_in=4'b1001;
#5 Seg_in=4'b1010;
#5 Seg_in=4'b1011;
#5 Seg_in=4'b1100;
#5 Seg_in=4'b1101;
#5 Seg_in=4'b1110;
#5 Seg_in=4'b1111;
end
endmodule
| 6.608387 |
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