code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_Seven_Seg_Display ();
wire [6:0] Display;
reg [6:0] BCD;
Seven_Seg_Display DUT (
Display,
BCD
);
initial begin
#5 BCD = 4'b0000;
#5 BCD = 4'b0001;
#5 BCD = 4'b0010;
#5 BCD = 4'b0011;
#5 BCD = 4'b0100;
#5 BCD = 4'b0101;
#5 BCD = 4'b0110;
#5 BCD = 4'b0111;
#5 BCD = 4'b1000;
#5 BCD = 4'b1001;
#5 BCD = 4'b1010;
#5 BCD = 4'b1011;
#5 BCD = 4'b1100;
#5 BCD = 4'b1101;
#5 BCD = 4'b1110;
#5 BCD = 4'b1111;
end
endmodule
| 6.686807 |
module : tb_seven_stage_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_factorial();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/factorial6140.vmh";
parameter TEST_NAME = "Factorial";
parameter LOG_FILE = "factorial_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00009d80) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module : tb_seven_stage_cache_top_fibonacci
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_fibonacci();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/fibonacci1536.vmh";
parameter TEST_NAME = "Fibonacci";
parameter LOG_FILE = "fibonacci_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000015) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module : tb_seven_stage_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_gcd();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/gcd1536.vmh";
parameter TEST_NAME = "Greatest Common Denominator";
parameter LOG_FILE = "gcd_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000010) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module : tb_seven_stage_cache_top_hanoi
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_hanoi();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/hanoi1536.vmh";
parameter TEST_NAME = "Hanoi";
parameter LOG_FILE = "hanoi_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h0000000f) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module : tb_seven_stage_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_mandelbrot();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/short_mandelbrot6140.vmh";
parameter TEST_NAME = "Mandelbrot";
parameter LOG_FILE = "mandelbrot_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000002) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module : tb_seven_stage_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_seven_stage_cache_top_primes();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/prime_number_counter6140.vmh";
parameter TEST_NAME = "Prime Number Counter";
parameter LOG_FILE = "primes_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
seven_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h0000000f) begin
$display("\ntb_seven_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_seven_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.317527 |
module tb_left_rotate;
reg clk, load;
reg [2:0] amount;
reg [7:0] data;
wire [7:0] out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
left_rotate UUT (
.clk(clk),
.load(load),
.amount(amount),
.data(data),
.out(out)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
// load data (load not enabled, should not load)
data = 8'hff;
load = 0;
amount = 0;
#period;
if (out === 8'hff) begin
$display("test 1 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
// enable load
data = 8'haa;
load = 1;
amount = 0;
#period;
if (out !== 8'haa) begin
$display("test 2 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
// enable load, amount should not make a difference
data = 8'h01;
load = 1;
amount = 2;
#period;
if (out !== 8'h01) begin
$display("test 3 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
// shift
load = 0;
amount = 1;
#period;
if (out !== 8'h02) begin
$display("test 4 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 2;
#period;
if (out !== 8'h08) begin
$display("test 5 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 3;
#period;
if (out !== 8'h40) begin
$display("test 6 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 4;
#period;
if (out !== 8'h04) begin
$display("test 7 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 5;
#period;
if (out !== 8'h80) begin
$display("test 8 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 6;
#period;
if (out !== 8'h20) begin
$display("test 9 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
amount = 7;
#period;
if (out !== 8'h10) begin
$display("test 10 failed");
$finish;
end else $display("load =%b, amount = %b, out=%b", load, amount, out);
$display("all tests passed");
$finish;
end
endmodule
| 6.692446 |
module tb_shifter8;
reg tb_clk, tb_reset_n; // 2 regs
reg [2:0] tb_op; // 3bits reg tb_op
reg [1:0] tb_shamt; // 2bits reg tb_shamt
reg [7:0] tb_d_in; // 8bits reg tb_d_in
wire [7:0] tb_d_out; // 8bits wire tb_d_out
shifter8 U0_shifter8 (
.clk(tb_clk),
.reset_n(tb_reset_n),
.op(tb_op),
.shamt(tb_shamt),
.d_in(tb_d_in),
.d_out(tb_d_out)
); // instance by using shifter8
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; // every 5ns, invert tb_clk
end
initial begin
tb_reset_n = 0;
tb_op = 3'b000;
tb_shamt = 2'b00;
tb_d_in = 8'b00000000; // input
#10;
tb_reset_n = 1;
tb_d_in = 8'b11101110; // every 10ns, change inputs
#10;
tb_op = 3'b001;
tb_shamt = 2'b01;
#10;
tb_op = 3'b010;
#10;
tb_op = 3'b100;
#10;
tb_shamt = 2'b10;
tb_op = 3'b010;
#10;
tb_shamt = 2'b01;
tb_op = 3'b011;
#10;
$stop; // stop
end
endmodule
| 6.748092 |
module tb_shiftreg;
parameter n = 4;
wire [n-1:0] Q;
reg EN, in, CLK;
shiftreg shifte (
Q,
EN,
in,
CLK
);
initial begin
CLK = 0;
end
always #2 CLK = ~CLK;
initial $monitor($time, " EN=%b in=%b Q=%b\n", EN, in, Q);
initial begin
in = 0;
EN = 0;
#4 in = 1;
EN = 1;
#4 in = 1;
EN = 0;
#4 in = 0;
EN = 1;
#5 $finish;
end
endmodule
| 6.935148 |
module tb_shift_counter;
wire [7:0] count;
reg clk, reset;
shift_counter counter (
count,
clk,
reset
);
initial begin
clk <= 0;
#0 reset <= 1;
#20 reset <= 0;
#95 reset <= 1;
#105 reset <= 0;
end
initial begin
repeat (100) begin
#10 clk = ~clk;
end
end
endmodule
| 6.90184 |
module tb_shift_custom;
// Parameters
parameter SYS_PERIOD = 20; // 系统时钟
parameter VGA_PERIOD = 20; // VGA时钟
// sobel_img_gen Outputs
reg VGA_HS;
reg VGA_VS;
reg VGA_DE;
reg [11:0] VGA_X;
reg [11:0] VGA_Y;
wire o_sobel_data;
// shift_custom Inputs
reg vga_clk = 0;
reg rst_n = 0;
reg [ 7:0] din = 0;
reg din_vld = 0;
// shift_custom Outputs
wire [7:0] px1, xp2, px3, px4, px5;
// vga_clk
initial begin
forever #(VGA_PERIOD / 2) vga_clk = ~vga_clk;
end
// rst_n
initial begin
#(SYS_PERIOD * 2) rst_n = 1;
end
// inst sobel_img_gen
sobel_img_gen u_sobel_img_gen (
// sys
.rst_n (rst_n),
.vga_clk (vga_clk),
// output
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS),
.VGA_DE (VGA_DE),
.VGA_X (VGA_X[11:0]),
.VGA_Y (VGA_Y[11:0]),
.o_sobel_data(o_sobel_data)
);
// inst shift_custom
shift_custom #(
.ROW(30),
.COL(30)
) u_shift_custom (
// sys
.vga_clk(vga_clk),
.rst_n (rst_n),
// input
.din (o_sobel_data),
.din_vld(VGA_DE),
// output
.px1 (px1[7:0]),
.px2 (px2[7:0]),
.px3 (px3[7:0]),
.px4 (px4[7:0]),
.px5 (px5[7:0])
);
// end time
initial begin
#((VGA_PERIOD * 30 * 30) * 3);
$stop;
end
endmodule
| 8.138566 |
module tb_shift_line_buffer;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire [7:0] taps0x;
wire [7:0] taps1x;
wire [7:0] taps2x;
//------------- generate system signals ------------------------------------
initial begin
sclk = 1;
s_rst_n <= 0;
din <= 'd0;
in_line_vaild <= 0;
#100 s_rst_n <= 1;
#100 in_line_vaild <= 1'b1;
data_generate();
end
always #10 sclk = ~sclk;
shift_line_buffer shift_line_buffer_inst (
.line_clk (sclk),
.s_rst_n (s_rst_n),
.in_line_vaild(in_line_vaild), //一直为高
.din (din),
.vsync (vsync),
.taps0x (taps0x),
.taps1x (taps1x),
.taps2x (taps2x),
.done (done)
);
task data_generate();
integer i;
begin
for (i = 0; i < 1000; i = i + 1) begin
#20 din <= din + 1;
end
in_line_vaild <= 0;
end
endtask
endmodule
| 6.653422 |
module tb_shift_reg ();
parameter WIDTH = 8;
reg clk;
reg d;
reg en;
reg reset;
wire [WIDTH-1:0] q;
ShiftReg #(WIDTH) sreg (
.clk(clk),
.d(d),
.en(en),
.reset(reset),
.q(q)
);
initial begin
clk = 0;
d = 0;
en = 0;
reset = 1;
#5 en = 1;
d = 1;
#10 reset = 0;
d = 0;
#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 0;
#10 reset = 1;
#10 d = 1;
end
always begin
#5 clk = ~clk;
end
endmodule
| 6.846966 |
module tb_shift_register;
parameter DEPTH = 4;
parameter WIDTH = 4;
reg clk;
reg rst_n;
reg en;
reg [WIDTH-1:0] d;
wire [WIDTH-1:0] q;
shift_register #(
.DEPTH(DEPTH),
.WIDTH(WIDTH)
) _shift_register (
.clk (clk),
.rst_n(rst_n),
.en (en),
.d (d),
.q (q)
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_shift_register.vcd");
$dumpvars(0, tb_shift_register);
#1 rst_n <= 1'bx;
clk <= 1'bx;
en <= 1'bx;
d <= {WIDTH{1'bx}};
#(CLK_PERIOD) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
en <= 0;
d <= 0;
repeat (5) @(posedge clk);
rst_n <= 1;
@(posedge clk);
d <= 1;
@(posedge clk);
en <= 1;
@(posedge clk);
d <= 2;
@(posedge clk);
d <= 3;
@(posedge clk);
d <= 4;
@(posedge clk);
d <= 5;
@(posedge clk);
if (q !== 1) $display("result == ", 1, " expected but ", q);
d <= 6;
@(posedge clk);
if (q !== 2) $display("result == ", 2, " expected but ", q);
d <= 7;
@(posedge clk);
if (q !== 3) $display("result == ", 3, " expected but ", q);
d <= 8;
@(posedge clk);
if (q !== 4) $display("result == ", 4, " expected but ", q);
en <= 0;
@(posedge clk);
if (q !== 5) $display("result == ", 5, " expected but ", q);
repeat (5) @(posedge clk);
$finish(2);
end
endmodule
| 7.38506 |
module tb_Shif_reg4 ();
reg Data_In, reset;
reg clock = 0;
wire Data_out;
Shif_reg4 DUT (
Data_out,
Data_In,
clock,
reset
);
always #5 clock = ~clock; // clock declaration
initial begin
Data_In = 1'b0;
reset = 0; // apply serial input
#10 reset = 1'b1;
#10 Data_In = 1'b1;
#9 Data_In = 1'b0;
#9 Data_In = 1'b1;
end
endmodule
| 6.608219 |
module tb_sie ();
reg usb_clk;
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
reg usb_clk_rx;
initial usb_clk_rx = 1'b0;
always #10 usb_clk_rx = ~usb_clk_rx;
reg usb_rst;
task waitclock;
begin
@(posedge usb_clk);
#1;
end
endtask
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
wire txp;
wire txm;
wire txoe;
softusb_tx tx (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.txp (txp),
.txm (txm),
.txoe(txoe),
.low_speed(1'b1),
.generate_eop(1'b0)
);
reg rxreset;
softusb_rx rx (
.usb_clk(usb_clk_rx),
.rxreset(rxreset),
.rx (txp),
.rxp(txp),
.rxm(txm),
.rx_data (),
.rx_valid (),
.rx_active(),
.low_speed(1'b1)
);
initial begin
$dumpfile("softusb_sie.vcd");
$dumpvars(0, tx);
$dumpvars(0, rx);
usb_rst = 1'b1;
rxreset = 1'b1;
tx_valid = 1'b0;
waitclock;
waitclock;
usb_rst = 1'b0;
@(posedge usb_clk);
@(posedge usb_clk);
rxreset = 1'b0;
tx_data = 8'h80;
tx_valid = 1'b1;
#3000;
tx_data = 8'h2d;
#9000;
tx_valid = 1'b0;
#40000;
$finish;
end
endmodule
| 6.501981 |
module: signExtend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_sigExtend;
// Inputs
reg [15:0] i_data;
// Outputs
wire [31:0] o_data;
// Instantiate the Unit Under Test (UUT)
signExtend uut (
.i_data(i_data),
.o_data(o_data)
);
initial begin
// Initialize Inputs
i_data = 0;
// Wait 100 ns for global reset to finish
#100;
#20; i_data = 16'b1000_0000_0000_1111;
#20; i_data = 16'b0000_0000_0000_1111;
#20; i_data = 16'b1000_0000_0000_1111;
#20; i_data = 16'b0000_0000_0000_1111;
end
endmodule
| 6.52184 |
module tb_sigmoid_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam NUM = {DATA_WIDTH{1'b1}};
// interface
reg clk;
reg rst_n;
reg [ NUM_INPUT_DATA-1:0] i_valid;
reg [ WIDTH_INPUT_DATA-1:0] i_data_bus;
wire [ NUM_OUTPUT_DATA-1:0] o_valid;
wire [WIDTH_OUTPUT_DATA-1:0] o_data_bus; //{o_data_a, o_data_b}
reg i_en;
initial begin
clk = 1'b0;
rst_n = 1'b1;
i_data_bus = ZERO_POINT;
i_valid = 1'b0;
i_en = 1'b1;
// reset
#10 rst_n = 1'b0;
// input activate below zero (negative)
#10 rst_n = 1'b1;
i_data_bus = {1'b1, {(DATA_WIDTH - 1) {1'b0}}};
i_valid = 1'b1;
// input activate larger than zero
#10
// i_data_bus = {1'b0, {(DATA_WIDTH-1){1'b1}}};
i_data_bus = {DATA_WIDTH{1'b1}};
i_valid = 1'b1;
#2600 $stop;
end
integer i;
always begin
@(posedge clk)
for (i = 0; i < NUM; i = i + 1) begin
i_data_bus = i_data_bus + 2'sb01;
end
end
always #5 clk = ~clk;
sigmoid_seq #(
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.rst_n(rst_n),
.i_data_bus(i_data_bus),
.i_valid(i_valid),
.o_data_bus(o_data_bus),
.o_valid(o_valid),
.i_en(i_en)
);
endmodule
| 7.060484 |
module tb_signal_gen;
// Praramers
parameter INPUT_PORTS = 3;
// Inputs
reg clk;
reg rst;
reg req;
// Outputs
wire [INPUT_PORTS-1:0] stm_value;
wire gnt;
// Instantiate the Unit Under Test (UUT)
signal_gen #(
.INPUT_PORTS(INPUT_PORTS)
) uut (
.clk(clk),
.rst(rst),
.req(req),
.stm_value(stm_value),
.gnt(gnt)
);
parameter PERIOD = 10;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
initial begin
// Initialize Inputs
rst = 1;
req = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
req = 0;
// Add stimulus here
#100;
req = 1;
$display($time, " << Starting the Simulation >>");
#100;
req = 0;
$monitor(" %0d %b", $time, gnt);
wait (gnt) begin
$display($time, " << Finishing the Simulation >>");
$stop;
end
end
endmodule
| 7.430905 |
module tb_signal_transfer ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_signal_transfer.vcd");
$dumpvars(0, tb_signal_transfer);
#1000000 $finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg s_reset = 1'b1;
initial #(S_RATE * 100) s_reset <= 1'b0;
reg m_clk = 1'b1;
always #(M_RATE / 2.0) m_clk = ~m_clk;
reg m_reset = 1'b1;
initial #(M_RATE * 100) m_reset <= 1'b0;
parameter ASYNC = 1;
parameter CAPACITY_WIDTH = 8;
reg enable = 1;
reg s_valid;
wire m_valid;
reg m_ready;
jelly_signal_transfer #(
.ASYNC (ASYNC),
.CAPACITY_WIDTH(CAPACITY_WIDTH)
) i_signal_transfer (
.s_reset(s_reset),
.s_clk (s_clk),
.s_valid(s_valid),
.m_reset(m_reset),
.m_clk (m_clk),
.m_valid(m_valid),
.m_ready(m_ready)
);
integer count_s;
always @(posedge s_clk) begin
if (s_reset) begin
s_valid <= 1'b0;
count_s <= 0;
end else begin
s_valid <= {$random()} & enable;
count_s <= count_s + s_valid;
end
end
integer count_m;
always @(posedge m_clk) begin
if (m_reset) begin
m_ready <= 1'b0;
count_m <= 0;
end else begin
m_ready <= {$random()};
count_m <= count_m + (m_valid & m_ready);
end
end
initial begin
#100000;
enable = 0;
#10000;
$finish();
end
endmodule
| 8.62057 |
module tb_signedextender;
reg [ 4:0] in = 5'b11001;
wire [15:0] out;
SignedExtender5to16 uut (
.in (in),
.out(out)
);
initial begin
#20 in = 5'b00111;
end
endmodule
| 6.683495 |
module tb_signed_divide_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_signed_divide_multicycle.vcd");
$dumpvars(0, tb_signed_divide_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter DATA_WIDTH = 32;
reg cke = 1'b1;
reg signed [DATA_WIDTH-1:0] s_data0 = 7;
reg signed [DATA_WIDTH-1:0] s_data1 = 2;
reg s_valid = 1;
wire s_ready;
wire signed [DATA_WIDTH-1:0] m_quotient;
wire signed [DATA_WIDTH-1:0] m_remainder;
wire m_valid;
wire m_ready = 1'b1;
wire signed [DATA_WIDTH-1:0] exp_quotient;
wire signed [DATA_WIDTH-1:0] exp_remainder;
always @(posedge clk) begin
if (s_valid & s_ready) begin
s_data0 <= {$random()};
s_data1 <= {$random()} + 1;
end
if (m_valid & m_ready) begin
$display("%d %d", exp_quotient, exp_remainder);
$display("%d %d", m_quotient, m_remainder);
end
end
jelly_signed_divide_multicycle #(
.DATA_WIDTH(DATA_WIDTH)
) i_signed_divide_multicycle (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data0(s_data0),
.s_data1(s_data1),
.s_valid(s_valid),
.s_ready(s_ready),
.m_quotient (m_quotient),
.m_remainder(m_remainder),
.m_valid (m_valid),
.m_ready (m_ready)
);
jelly_cpu_divider #(
.DATA_WIDTH(DATA_WIDTH)
) i_cpu_divider (
.reset(reset),
.clk (clk),
.op_div (s_valid & s_ready),
.op_signed (1'b1),
.op_set_remainder(1'b0),
.op_set_quotient (1'b0),
.in_data0(s_data0),
.in_data1(s_data1),
.out_en (),
.out_quotient (exp_quotient),
.out_remainder(exp_remainder),
.busy()
);
wire quotient_ng = m_valid & (exp_quotient != m_quotient);
wire remainder_ng = m_valid & (exp_remainder != m_remainder);
endmodule
| 7.351884 |
module tb_ext_sign ();
parameter NB_IN = 16;
parameter NB_OUT = 32;
reg [ NB_IN-1:0] i_data;
wire [NB_OUT-1:0] o_data;
initial begin
i_data = 16'd7;
#40 i_data = 16'd57;
#40 i_data = 16'd273;
#40 i_data = 16'hff01;
#200 $finish;
end
ext_sign ext_sign (
.i_data(i_data),
.o_data(o_data)
);
endmodule
| 7.514208 |
module tb_sign_extender ();
reg signed [7:0] in;
reg s;
wire [15:0] out;
integer i, j;
sign_extender uut (
.In (in),
.S (s),
.Out(out)
);
initial begin
$display("Starting Testbench");
//testing signed things
in = 8'b11111111;
s = 1;
#5;
in = 8'b00001111;
s = 1;
#5;
in = 8'b11111111;
s = 0;
#5;
in = 8'b00001111;
s = 0;
#5;
end
endmodule
| 7.307135 |
module tb_sim;
`include "bch_params.vh"
parameter T = 4;
parameter OPTION = "SERIAL";
parameter DATA_BITS = 64;
parameter BITS = 8;
parameter REG_RATIO = 1;
parameter SEED = 0;
localparam BCH_PARAMS = bch_params(DATA_BITS, T);
reg [31:0] seed = SEED;
integer samples = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
end
localparam TCQ = 1;
reg clk = 0;
reg reset = 0;
reg [DATA_BITS-1:0] din = 0;
reg [$clog2(T+2)-1:0] nerr = 0;
reg [`BCH_CODE_BITS(BCH_PARAMS)-1:0] error = 0;
function [DATA_BITS-1:0] randk;
input [31:0] useless;
integer i;
begin
for (i = 0; i < (31 + DATA_BITS) / 32; i = i + 1)
if (i * 32 > DATA_BITS) begin
if (DATA_BITS % 32)
/* Placate isim */
randk[i*32+:(DATA_BITS%32)?(DATA_BITS%32) : 1] = $random(
seed
);
end else randk[i*32+:32] = $random(seed);
end
endfunction
function integer n_errors;
input [31:0] useless;
integer i;
begin
n_errors = (32'h7fff_ffff & $random(seed)) % (T + 1);
end
endfunction
function [`BCH_CODE_BITS(BCH_PARAMS)-1:0] rande;
input [31:0] nerr;
integer i;
begin
rande = 0;
while (nerr) begin
i = (32'h7fff_ffff & $random(seed)) % (`BCH_CODE_BITS(BCH_PARAMS));
if (!((1 << i) & rande)) begin
rande = rande | (1 << i);
nerr = nerr - 1;
end
end
end
endfunction
reg encode_start = 0;
wire wrong;
wire ready;
reg active = 0;
sim #(BCH_PARAMS, OPTION, BITS, REG_RATIO) u_sim (
.clk(clk),
.reset(1'b0),
.data_in(din),
.error(error),
.ready(ready),
.encode_start(active),
.wrong(wrong)
);
always #5 clk = ~clk;
always @(posedge wrong) #10 $finish;
reg [31:0] s;
always @(posedge clk) begin
if (ready) begin
s = seed;
#1;
din <= randk(0);
#1;
nerr <= n_errors(0);
#1;
error <= rande(nerr);
#1;
active <= 1;
$display("%x %d flips - %x (seed = %d)", din, nerr, error, s);
samples = samples + 1;
if (samples > 16) $finish();
end
end
initial begin
$display("GF(2^%1d) (%1d, %1d/%1d, %1d) %s", `BCH_M(BCH_PARAMS), `BCH_N(BCH_PARAMS),
`BCH_K(BCH_PARAMS), DATA_BITS, `BCH_T(BCH_PARAMS), OPTION);
@(posedge clk);
@(posedge clk);
reset <= #1 1;
@(posedge clk);
@(posedge clk);
reset <= #1 0;
end
endmodule
| 6.638818 |
module tb_simple_fsm;
reg clk, reset, in;
wire out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
simple_fsm UUT (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
in = 0;
#period;
// goes to state 0
if (out !== 1) begin
$display("test 1 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
// start fsm
reset = 0;
in = 0;
#period;
// goes to state 1
if (out !== 0) begin
$display("test 2 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
in = 0;
#period;
// goes to state 0
if (out !== 1) begin
$display("test 3 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
in = 1;
#period;
// stays in state 0
if (out !== 1) begin
$display("test 4 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
in = 0;
#period;
// goes to state 1
if (out !== 0) begin
$display("test 5 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
in = 1;
#period;
// stays in state 1
if (out !== 0) begin
$display("test 6 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
// check reset again
reset = 1;
in = 1;
#period;
// goes to state 0
if (out !== 1) begin
$display("test 7 failed");
$finish;
end else $display("clk=%b, reset=%b, in=%b, out=%b", clk, reset, in, out);
$display("all tests passed");
$finish;
end
endmodule
| 8.263991 |
module tb_Simple_AXI_RAM;
parameter NUM_SLOTS = 5;
parameter ADDR_WIDTH_BITS = $clog2(NUM_SLOTS);
parameter DATA_WIDTH_BYTES = 4;
parameter DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
// Interface Signals
reg clk;
reg rst; // reset on high
// AXI4-Lite Interface Signals
// Read address channel
reg ARVALID;
wire ARREADY;
reg [ ADDR_WIDTH_BITS-1:0] ARADDR;
reg [ 3:0] ARPROT; // Not used in this device
// Read data channel
wire RVALID;
reg RREADY;
wire [ DATA_WIDTH_BITS-1:0] RDATA;
wire [ 1:0] RRESP;
// Write address channel
reg AWVALID;
wire AWREADY;
reg [ ADDR_WIDTH_BITS-1:0] AWADDR;
reg [ 3:0] AWPROT; // Not used in this device
// Write data channel
reg WVALID;
wire WREADY;
reg [ DATA_WIDTH_BITS-1:0] WDATA;
reg [DATA_WIDTH_BYTES-1:0] WSTRB;
// Write response channel
wire BVALID;
reg BREADY;
wire [ 1:0] BRESP;
// Other signals
wire [ DATA_WIDTH_BITS-1:0] stored_data [NUM_SLOTS-1:0];
// DUT
Simple_AXI_RAM #(
.NUM_SLOTS(NUM_SLOTS),
.DATA_WIDTH_BYTES(DATA_WIDTH_BYTES)
) DUT (
.clk(clk),
.rst(rst),
.ARVALID(ARVALID),
.ARREADY(ARREADY),
.ARADDR(ARADDR),
.ARPROT(ARPROT),
.RVALID(RVALID),
.RREADY(RREADY),
.RDATA(RDATA),
.RRESP(RRESP),
.AWVALID(AWVALID),
.AWREADY(AWREADY),
.AWADDR(AWADDR),
.AWPROT(AWPROT),
.WVALID(WVALID),
.WREADY(WREADY),
.WDATA(WDATA),
.WSTRB(WSTRB),
.BVALID(BVALID),
.BREADY(BREADY),
.BRESP(BRESP)
);
// Assignments to internal signals
genvar i;
generate
for (i = 0; i < NUM_SLOTS; i = i + 1) begin : RAM_data
assign stored_data[i] = DUT.RAM_unit.memory[i];
end
endgenerate
always #5 clk = ~clk;
initial begin
clk <= 0;
rst <= 0;
ARVALID <= 0;
ARADDR <= 0;
ARPROT <= 0;
RREADY <= 0;
AWVALID <= 0;
AWADDR <= 0;
AWPROT <= 0;
WVALID <= 0;
WDATA <= 0;
WSTRB <= 0;
BREADY <= 0;
#5;
rst <= 1;
#10;
rst <= 0;
#10;
// Write
AWVALID <= 1;
AWADDR <= 4;
#10;
AWVALID <= 0;
AWADDR <= 0;
WDATA <= 'h11223344;
WSTRB <= 'b1101;
#10;
WVALID <= 1;
#10;
WVALID <= 0;
WDATA <= 0;
WSTRB <= 0;
#20;
BREADY <= 1;
#10;
BREADY <= 0;
#20;
// Read
ARVALID <= 1;
ARADDR <= 4;
#10;
ARVALID <= 0;
ARADDR <= 0;
#10;
RREADY <= 1;
#10;
RREADY <= 0;
#20;
// Write
AWVALID <= 1;
AWADDR <= 4;
#10;
AWVALID <= 0;
AWADDR <= 0;
WVALID <= 1;
WDATA <= 'h00003300;
WSTRB <= 'b0010;
#10;
WVALID <= 0;
WDATA <= 0;
WSTRB <= 0;
BREADY <= 1;
#10;
BREADY <= 0;
#10;
// Read
ARVALID <= 1;
ARADDR <= 4;
#10;
ARVALID <= 0;
ARADDR <= 0;
RREADY <= 1;
#10;
RREADY <= 0;
#20;
end
endmodule
| 6.577202 |
module tb_reg_mem;
parameter DATA_WIDTH = 8; //8 bit wide data
parameter ADDR_BITS = 5; //32 Addresses
reg [ ADDR_BITS-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
reg wen, clk;
//Note passing of parameters syntax
reg_mem #(DATA_WIDTH, ADDR_BITS) RM (
addr,
data_in,
wen,
clk,
data_out
);
initial begin
clk = 0;
wen = 1;
//Write 10-42 to addresses 0-31
for (int i = 10; i < 43; i = i + 1) begin
data_in = i;
addr = (i + 2);
$display("Write %d to address %d", data_in, addr);
repeat (2) #1 clk = ~clk;
end
wen = 0;
#1;
//Read 10-42 to addresses 0-31
for (int i = 10; i < 43; i = i + 1) begin
data_in = i;
addr = (i + 2);
$display("Read %d from address %d", data_in, addr);
repeat (2) #1 clk = ~clk;
end
end
endmodule
| 7.502985 |
module tb_simple_CPU;
parameter DATA_WIDTH = 8; //8 bit wide data
parameter ADDR_BITS = 5; //32 Addresses
parameter INSTR_WIDTH = 20; //20b instruction
reg clk, rst;
reg [INSTR_WIDTH-1:0] instruction;
reg [ DATA_WIDTH-1:0] output_reg;
simple_cpu #(DATA_WIDTH, ADDR_BITS, INSTR_WIDTH) SCPU_DUT (
clk,
rst,
instruction
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
clk = 1'b1;
rst = 1'b1;
instruction = 20'd0;
repeat (3) #1 clk = !clk;
rst = 1'b0;
repeat (2) #1 clk = !clk;
/*Info on the simple CPU:
* Reset sets regfile = [0,1,2,3]
* ADD = opcode 0, SUB = opcode 1
*/
//ADD: reg0 = reg1 + reg3 //1+3=4
//In the instruction this is: (instr) (X1) (X2) (X3)
instruction = 20'b01000111000000000000;
repeat (8) #1 clk = !clk; //4 rising edges
//ADD: reg1 = reg0 + reg3 //4+3=7
//In the instruction this is: (instr) (X1) (X2) (X3)
instruction = 20'b01010011000000000000;
repeat (6) #1 clk = !clk;
//SUB: reg3 = reg0 - reg2 //4-2=2
//In the instruction this is: (instr) (X1) (X2) (X3)
instruction = 20'b01110010000000000001;
repeat (6) #1 clk = !clk;
//STORE_R: DATA_MEM(reg2 + 15) = reg1 //DATA_MEM(2+15)=7
//In the instruction this is: (instr) (X2) (X1)
instruction = 20'b11011000000011110000;
repeat (6) #1 clk = !clk;
//STORE_R: DATA_MEM(reg3 + 20) = reg0 //DATA_MEM(2+20)= 4
//In the instruction this is: (instr) (X2) (X1)
instruction = 20'b11001100000101100000;
repeat (6) #1 clk = !clk;
//LOAD_R: DATA_MEM(reg2 + 15) = reg3 //reg3 = DATA_MEM(2+15) -> reg3 becomes 7
//In the instruction this is: (instr) (X2) (X1)
instruction = 20'b10111000000011110000;
repeat (7) #1 clk = !clk;
//LOAD_R: DATA_MEM(reg2 + 15) = reg3 //reg3 = DATA_MEM(2+15) -> reg3 becomes 7
//In the instruction this is: (instr) (X2) (X1)
instruction = 20'b10111000000011110000;
repeat (7) #1 clk = !clk;
end
endmodule
| 7.02698 |
module tb_simple_fsm ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk;
reg sys_rst_n;
reg pi_money;
//wire define
wire po_cola;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50MHz
always #10 sys_clk = ~sys_clk;
//pi_money:产生输入随机数，模拟投币1元的情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) pi_money <= 1'b0;
else pi_money <= {$random} % 2; //取模求余数，产生非负随机数0、1
//------------------------------------------------------------
//将RTL模块中的内部信号引入到Testbench模块中进行观察
wire [2:0] state = simple_fsm_inst.state;
initial begin
$timeformat(-9, 0, "ns", 6);
$monitor("@time %t: pi_money=%b state=%b po_cola=%b", $time, pi_money, state, po_cola);
end
//------------------------------------------------------------
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------------------simple_fsm_inst------------------------
simple_fsm simple_fsm_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.pi_money (pi_money), //input pi_money
.po_cola(po_cola) //output po_cola
);
endmodule
| 8.263991 |
module tb_simple_hash;
// Inputs
reg [ `HASH_WORD_WIDTH-1:0] data_in;
// Outputs
wire [`HASH_RESULT_WIDTH-1:0] data_out;
// Instantiate the Unit Under Test (UUT)
simple_hash uut (
.data_in (data_in),
.data_out(data_out)
);
initial begin
data_in = 0;
#20;
data_in = 1;
#20;
data_in = 12;
#20;
data_in = 45;
#20;
data_in = 75;
#20;
data_in = 836727523;
end
endmodule
| 6.534743 |
module tb_Simple_RAM;
parameter DATA_WIDTH_BYTES = 4;
parameter DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
parameter NUM_SLOTS = 5;
parameter ADDR_WIDTH_BITS = $clog2(NUM_SLOTS);
// Interface signals
reg clk;
reg rst;
reg r_en;
reg [ ADDR_WIDTH_BITS-1:0] r_addr;
wire [ DATA_WIDTH_BITS-1:0] r_data;
reg w_en;
reg [ ADDR_WIDTH_BITS-1:0] w_addr;
reg [ DATA_WIDTH_BITS-1:0] w_data;
reg [DATA_WIDTH_BYTES-1:0] w_strb;
// Other signals
wire [ DATA_WIDTH_BITS-1:0] stored_data[NUM_SLOTS-1:0];
// DUT
Simple_RAM #(
.NUM_SLOTS(NUM_SLOTS),
.DATA_WIDTH_BYTES(DATA_WIDTH_BYTES)
) DUT (
.clk(clk),
.rst(rst),
.r_en(r_en),
.r_addr(r_addr),
.r_data(r_data),
.w_en(w_en),
.w_addr(w_addr),
.w_data(w_data),
.w_strb(w_strb)
);
// Assignments to internal signals
genvar i;
generate
for (i = 0; i < NUM_SLOTS; i = i + 1) begin : RAM_data
assign stored_data[i] = DUT.memory[i];
end
endgenerate
always #5 clk = ~clk;
initial begin
clk <= 0;
rst <= 0;
r_en <= 0;
r_addr <= 0;
w_en <= 0;
w_addr <= 0;
w_data <= 0;
w_strb <= 0;
#5;
rst <= 1;
#10;
rst <= 0;
#10;
w_en <= 1;
w_addr <= 0;
w_data <= 'h11223344;
w_strb <= 'b1101;
#10;
w_en <= 0;
w_addr <= 1;
w_data <= 'hffffffff;
w_strb <= 'b1111;
#10;
r_en <= 1;
r_addr <= 0;
#10;
r_en <= 1;
r_addr <= 1;
#10;
r_en <= 0;
#10;
w_en <= 1;
w_addr <= 0;
w_data <= 'h00003300;
w_strb <= 'b0010;
#10;
w_en <= 0;
w_addr <= 0;
w_data <= 0;
w_strb <= 0;
#10;
end
endmodule
| 6.980752 |
module TestBench ();
reg clk;
reg reset;
reg [31:0] addr;
reg [3:0] mask;
reg enable;
reg cmd;
reg [31:0] write_data;
wire [31:0] load_data;
wire valid;
mem memory (
clk,
reset,
addr,
mask,
enable,
cmd,
write_data,
load_data,
valid
);
always begin
clk <= 0;
#10;
clk <= 1;
#10;
end
initial begin
reset <= 1;
addr <= 0;
mask <= 4'b1111;
enable <= 0;
#50 reset <= 0;
#30 write_data <= 32'b00000000000000001111111111111111;
cmd = `MEM_CMD_WRITE;
#10 enable = 1;
#100 enable = 0;
#10 cmd = `MEM_CMD_READ;
#10 enable = 1;
end
endmodule
| 7.747207 |
module tb_SingleCycle ();
reg clk, rst;
// 產生時脈，週期：10ns
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
rst = 1'b1;
/*
指令資料記憶體，檔名"instr_mem.txt, data_mem.txt"可自行修改
每一行為1 Byte資料，以兩個十六進位數字表示
且為Little Endian編碼
*/
$readmemh("instr_mem.txt", CPU.InstrMem.mem_array);
$readmemh("data_mem.txt", CPU.DatMem.mem_array);
// 設定暫存器初始值，每一行為一筆暫存器資料
$readmemh("reg.txt", CPU.RegFile.file_array);
#10;
rst = 1'b0;
end
always @(posedge clk) begin
$display("%d, PC:", $time / 10 - 1, CPU.pc_src);
if (CPU.instr == 32'b0) $display("%d, NOP\n", $time / 10 - 1);
else if (CPU.opcode == 6'd0) begin
$display("%d, wd: %d", $time / 10 - 1, CPU.rfile_wd);
if (CPU.funct_src == 6'd32) $display("%d, ADD\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd34) $display("%d, SUB\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd36) $display("%d, AND\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd37) $display("%d, OR\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd42) $display("%d, SLT\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd16) $display("%d, MFHI\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd18) $display("%d, MFLO\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd00) $display("%d, SLL\n", $time / 10 - 1);
else if (CPU.funct_src == 6'd27) $display("%d, DIV\n", $time / 10 - 1);
else $display("%d, ERROR FUNCTION (R-TYPE)\n", $time / 10 - 1); // debug
end else if (CPU.opcode == 6'd35) $display("%d, LW\n", $time / 10 - 1);
else if (CPU.opcode == 6'd43) $display("%d, SW\n", $time / 10 - 1);
else if (CPU.opcode == 6'd4) $display("%d, BEQ\n", $time / 10 - 1);
else if (CPU.opcode == 6'd2) $display("%d, J\n", $time / 10 - 1);
else if (CPU.opcode == 6'd3) $display("%d, JAL\n", $time / 10 - 1);
else if (CPU.opcode == 6'd10) $display("%d, SLTI\n", $time / 10 - 1);
else $display("%d, ERROR FUNCTION\n", $time / 10 - 1); // debug
end
mips_single CPU (
clk,
rst
);
endmodule
| 7.196278 |
module TB_SingleDP ();
//2- Delcaracion de señales.
//Registers
reg CLK;
//3- Module Structure
//Instances
SingleDP Finish (CLK);
always #100 CLK = ~CLK; //Always
initial begin
//Evalue
$dumpfile("Phase 1");
$dumpvars(0, TB_SingleDP);
CLK <= 0;
#1200 $stop;
end
endmodule
| 6.687279 |
module : tb_single_cycle_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_factorial();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/factorial6140.vmh";
parameter TEST_NAME = "Factorial";
parameter LOG_FILE = "factorial_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00009d80) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module : tb_single_cycle_cache_top_fibonacci
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_fibonacci();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/fibonacci1536.vmh";
parameter TEST_NAME = "Fibonacci";
parameter LOG_FILE = "fibonacci_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000015) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module : tb_single_cycle_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_gcd();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/gcd1536.vmh";
parameter TEST_NAME = "Greatest Common Denominator";
parameter LOG_FILE = "gcd_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000010) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module : tb_single_cycle_cache_top_hanoi
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_hanoi();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/hanoi1536.vmh";
parameter TEST_NAME = "Hanoi";
parameter LOG_FILE = "hanoi_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h0000000f) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module : tb_single_cycle_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_mandelbrot();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/short_mandelbrot6140.vmh";
parameter TEST_NAME = "Mandelbrot";
parameter LOG_FILE = "mandelbrot_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000002) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module : tb_single_cycle_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define REGISTER_FILE dut.core.ID.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
module tb_single_cycle_cache_top_primes();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/prime_number_counter6140.vmh";
parameter TEST_NAME = "Prime Number Counter";
parameter LOG_FILE = "primes_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
single_cycle_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
#1
if(`CURRENT_PC == 32'h000000a8 || `CURRENT_PC == 32'h000000ac) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h0000000f) begin
$display("\ntb_single_cycle_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_single_cycle_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.223153 |
module tb_single_MIPS;
reg clk;
reg reset;
mips_single MIPS (
clk,
reset
);
initial begin
forever #2 clk <= ~clk;
end
initial begin
clk <= 1'b0;
reset <= 1'b0;
#2 reset <= 1'b1;
#2 reset <= 1'b0;
#222 $stop;
end
endmodule
| 6.694941 |
module tb_single_port_ram;
reg clk;
reg we;
reg [15:0] addr;
reg [15:0] din;
wire [15:0] dout;
initial begin
$from_myhdl(clk, we, addr, din);
$to_myhdl(dout);
end
single_port_ram dut (
clk,
we,
addr,
din,
dout
);
endmodule
| 6.842034 |
module tb_sin_3phase_tbl ();
localparam RATE = 1000.0 / 125.0;
initial begin
$dumpfile("tb_sin_3phase_tbl.vcd");
$dumpvars(0, tb_sin_3phase_tbl);
#100000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
wire cke = 1;
reg [ 9:0] in_phase = 0;
wire [11:0] out_x;
wire [11:0] out_y;
wire [11:0] out_z;
sin_3phase_tbl i_sin_3phase_tbl (
.reset(reset),
.clk (clk),
.cke (cke),
.in_phase(in_phase),
.out_x(out_x),
.out_y(out_y),
.out_z(out_z)
);
always @(posedge clk) begin
if (reset) begin
in_phase <= 0;
end else if (cke) begin
in_phase <= in_phase + 1;
end
end
endmodule
| 7.032748 |
module siso_left_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg LSHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_left_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.LSHIFT(LSHIFT),
.IN(IN),
.OUT(OUT)
);
initial begin
RST = 1;
#100 RST = 0;
fork
begin
CLK = 1;
forever begin
#5 CLK = ~CLK;
end
end
begin
@(negedge CLK);
repeat ((2 ** (SW + 1)) + 16) begin
@(posedge CLK);
#1;
$display("IN : %d, LSHIFT : %0d == OUT : %d", IN, LSHIFT, OUT);
LSHIFT = 1;
IN = $urandom;
@(negedge CLK);
end
$finish;
end
join
end
endmodule
| 7.062855 |
module siso_left_right_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg [1:0] SHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_left_right_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.SHIFT(SHIFT),
.IN(IN),
.OUT(OUT)
);
initial begin
RST = 1;
#100 RST = 0;
fork
begin
CLK = 1;
forever begin
#5 CLK = ~CLK;
end
end
begin
@(negedge CLK);
repeat ((2 ** (SW + 3)) + 16) begin
@(posedge CLK);
#1;
$display(" A --- IN : %d, SHIFT : %0d == OUT : %d", IN, SHIFT, OUT);
SHIFT = 1;
IN = $urandom;
@(negedge CLK);
end
@(negedge CLK);
repeat ((2 ** (SW + 3)) + 16) begin
@(posedge CLK);
#1;
$display(" B --- IN : %d, SHIFT : %0d == OUT : %d", IN, SHIFT, OUT);
SHIFT = 0;
IN = $urandom;
@(negedge CLK);
end
@(negedge CLK);
repeat ((2 ** (SW + 3)) + 16) begin
@(posedge CLK);
#1;
$display(" C --- IN : %d, SHIFT : %0d == OUT : %d", IN, SHIFT, OUT);
SHIFT = 2;
IN = $urandom;
@(negedge CLK);
end
@(negedge CLK);
repeat ((2 ** (SW + 3)) + 16) begin
@(posedge CLK);
#1;
$display(" D --- IN : %d, SHIFT : %0d == OUT : %d", IN, SHIFT, OUT);
SHIFT = 3;
IN = $urandom;
@(negedge CLK);
end
$finish;
end
join
end
endmodule
| 7.027217 |
module siso_right_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg RSHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_right_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.RSHIFT(RSHIFT),
.IN(IN),
.OUT(OUT)
);
initial begin
RST = 1;
#100 RST = 0;
fork
begin
CLK = 1;
forever begin
#5 CLK = ~CLK;
end
end
begin
@(negedge CLK);
repeat ((2 ** (SW + 1)) + 16) begin
@(posedge CLK);
#1;
$display("IN : %d, RSHIFT : %0d == OUT : %d", IN, RSHIFT, OUT);
RSHIFT = 1;
IN = $urandom;
@(negedge CLK);
end
$finish;
end
join
end
endmodule
| 6.96141 |
module tb_site (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [ 3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// IRQ
output [2:0] irq
);
initial begin
$dumpfile("test_site.vcd");
$dumpvars;
#1;
end
toysram_site site (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
// Logic Analyzer Signals
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb(la_oenb),
// IOs
.io_in (io_in),
.io_out(io_out),
.io_oeb(io_oeb),
// IRQ
.irq(irq)
);
endmodule
| 7.655482 |
module tb_sm ();
reg n;
reg d;
reg clk;
reg rst;
wire op;
wire [1:0] state;
wire [1:0] nstate;
sm UUT (
.n ( n ),
.d ( d ),
.clk ( clk ),
.rst ( rst ),
.op ( op ),
.state ( state ),
.nstate ( nstate )
);
initial begin
clk = 0;
rst = 1;
forever #5 clk = ~clk;
end
initial begin
#10 n = 0; // next state s0
d = 0;
rst = 0;
#15 n = 1; // state s0
d = 0; // next state s1
#10 n = 1; // state s1
// next state s2
#10 n = 1; // next state s3 output
#10 n = 0; // state s3. output
// next state s0
#10 d = 1; // state s0
// next state s2
#10 n = 1; // state s2
d = 0; // next state s3 output
// If this reset is activated here then
// the previous output will not be displayed
// this is because the output is NOT seen until the next
// clock cycle.
// Any input or changes of states are registered until
// the next clock cycle.
// #10 rst = 1; //
#10 n = 0; // state s3. output
d = 1; // next state s2
#10 rst = 1; // state s0 reset
end
endmodule
| 6.602217 |
module tb_sm4_core ();
reg r_clk;
reg r_rst;
reg r_flag;
reg r_key_en;
reg [127:0] r_key;
reg r_din_en;
reg [127:0] r_din;
reg [ 31:0] r_err;
reg [ 2:0] r_count;
reg r_test;
wire s_dout_en;
wire [127:0] s_dout;
wire s_key_ok;
reg [ 1:0] r_state;
localparam DLY = 1;
reg [127:0] KEY1 = {32'h76543210, 32'hfedcba98, 32'h89abcdef, 32'h01234567};
reg [127:0] PT1 = {32'h76543210, 32'hfedcba98, 32'h89abcdef, 32'h01234567};
reg [127:0] CT1 = {32'h536e4246, 32'h86b3e94f, 32'hd206965e, 32'h681edf34};
sm4_core uut (
.i_clk(r_clk),
.i_rst(r_rst),
.i_flag(r_flag), //1-encrypt,0-decrypt
.i_key(r_key),
.i_key_en(r_key_en),
.i_din(r_din),
.i_din_en(r_din_en),
.o_dout(s_dout),
.o_dout_en(s_dout_en),
.o_key_ok(s_key_ok)
);
initial begin
r_clk = 0;
forever #5 r_clk = ~r_clk;
end
always @(posedge r_clk or posedge r_rst) begin
if (r_rst) begin
r_count <= #DLY 3'd0;
r_flag <= #DLY 1'b0;
r_din_en <= #DLY 1'b0;
r_din <= #DLY 'b0;
r_key_en <= #DLY 1'b0;
r_key <= #DLY 'b0;
r_err <= #DLY 'b0;
r_state <= #DLY 2'b0;
end else begin
case (r_state)
2'd0: begin
if (r_test) begin
r_key_en <= #DLY 1'b1;
r_key <= #DLY KEY1;
r_state <= #DLY 2'd1;
end
end
2'd1: begin
r_key_en <= #DLY 1'b0;
if (s_key_ok) begin
r_din_en <= #DLY 1'b1;
r_flag <= #DLY 1'b1;
r_din <= #DLY PT1;
r_state <= #DLY 2'd2;
end
end
2'd2: begin
r_din_en <= #DLY 1'b0;
if (s_dout_en) begin
if (s_dout != CT1) r_err <= #DLY r_err + 1'b1;
r_din_en <= #DLY 1'b1;
r_din <= #DLY CT1;
r_flag <= #DLY 1'b0;
r_state <= #DLY 2'd3;
end
end
2'd3: begin
r_din_en <= #DLY 1'b0;
if (s_dout_en) begin
if (s_dout != PT1) r_err <= #DLY r_err + 1'b1;
r_count <= #DLY r_count + 1'b1;
if (r_count == 'd7) r_state <= #DLY 2'd0;
else r_state <= #DLY 2'd1;
end
end
endcase
end
end
initial begin
r_rst = 1'b1;
r_test = 1'b0;
repeat (50) @(negedge r_clk);
r_rst = 1'b0;
repeat (10) @(negedge r_clk);
r_test = 1'b1;
repeat (5000) @(negedge r_clk);
end
endmodule
| 6.516363 |
module tb_CountEvenOneZero;
// Inputs
reg data_in, clk, reset;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
CountEvenOneZero uut (
.data_in(data_in),
.clk(clk),
.reset(reset),
.out(out)
);
initial begin
$dumpfile("tb_CountEvenOneZero.vcd");
$dumpvars(0, tb_CountEvenOneZero);
// Initialize Inputs
data_in = 1;
clk = 0;
reset = 1;
#4 reset = 0;
#40 $finish;
end
always #2 clk = ~clk;
always @(posedge clk) begin
data_in = $random;
end
endmodule
| 6.869616 |
module tb_snif #(
parameter ADR_WIDTH = 6
) ();
reg clk;
reg rst;
reg [ADR_WIDTH-1:0] adr_i;
reg we_i;
wire detect_o;
integer j;
snif #(
.ADR_WIDTH(ADR_WIDTH)
) i_snif (
.clk_i(clk),
.rst_i(rst),
.adr_i(adr_i),
.we_i (we_i),
.detect_o(detect_o)
);
initial begin
$dumpfile("tb_snif.vcd");
// $dumpvars(level, list_of_variables_or_modules)
// level = 1 -> only variables in list_of_variables_or_modules
$dumpvars(0, tb_snif);
//$readmemb("tb/egse.stim", stim);
//$monitor("%b%b LED:%b RS232TX:%b", clk, rst_n, led, rs232_tx);
clk = 0;
rst = 1;
adr_i = 6'b000_000;
we_i = 1'b0;
#10 rst = 0;
@(posedge clk)
/* Traverse through all addresses without write enable */
for (
j = 0; j < 64; j = j + 1
) begin
@(posedge clk) adr_i = j;
if (detect_o != 1'b0) begin
$display("Detect without write: j=%d", j);
end
end
@(posedge clk);
/* Traverse through false addresses with write enable */
we_i = 1'b1;
for (j = 0; j < 63; j = j + 1) begin
adr_i = j;
@(posedge clk)
if (detect_o != 1'b0) begin
$display("Detect false address: j=%d", j);
end
end
@(posedge clk);
/* Detect last address write */
adr_i = 63;
we_i = 1'b1;
@(posedge clk);
we_i = 1'b0;
@(posedge clk);
if (detect_o != 1'b1) begin
$display("No detect!");
end
@(posedge clk);
$finish;
end
always #1 clk = !clk;
endmodule
| 7.47311 |
module tb_snurisc;
reg reset, clk;
initial clk = 0;
always #50 clk = !clk;
initial begin
$vcdplusfile;
$vcdpluson;
end
initial begin
reset = 1;
#200 reset = 0;
#2000 $finish;
end
snurisc dut (
.reset(reset),
.clk (clk)
);
endmodule
| 6.609914 |
module tb_sobel;
reg clock;
reg reset_n;
reg readdatavalid;
reg [15:0] readdata;
reg waitrequest;
reg ready;
reg cont = 1;
reg [9:0] counter = 0;
reg [15:0] memory[0:131072];
wire [31:0] address;
reg [31:0] rdadr;
reg isread = 0;
initial begin
isread <= 0;
clock <= 0;
ready <= 0;
reset_n <= 0;
readdatavalid <= 0;
readdata <= 16'h0001;
waitrequest <= 0;
#20;
reset_n <= 1;
ready <= 1;
$readmemh("testvector", memory);
end
sobel DUT (
.clk(clock),
.reset_n(reset_n),
.waitrequest(waitrequest),
.readdatavalid(readdatavalid),
.readdata(readdata),
.read_n(read_n),
.write_n(write_n),
.chipselect(chipselect),
.address(address),
.byteenable(byteenable),
.writedata(writedata),
.ready(ready),
.done(done),
.cont(cont)
);
always begin
#10 clock = ~clock;
if (read_n == 0 && counter > 8) begin
counter = 0;
isread = 1;
end
if ((write_n == 0) && counter > 6) begin
counter = 0;
end
if (counter == 4) begin
waitrequest <= 0;
rdadr <= ~read_n ? address : 0;
end else begin
waitrequest <= 1;
end
if ((counter == 6) && isread == 1) begin
readdatavalid = 1;
//readdata = memory[rdadr] || 0;
end else begin
readdatavalid = 0;
end
if (counter == 8) begin
isread = 0;
end
counter = counter + clock;
readdata <= $random;
//readdata <= 0;
end
endmodule
| 7.497741 |
module tb_sobel ();
//wire define
wire tx;
wire hsync;
wire vsync;
wire [7:0] rgb;
//reg define
reg clk;
reg rst_n;
reg rx;
reg [7:0] data_mem[9999:0]; //data_mem是一个存储器，相当于一个ram
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial $readmemh("E:/GitLib/Altera/EP4CE10/base_code/9_sobel/matlab/data_test.txt", data_mem);
//时钟、复位信号
initial begin
clk = 1'b1;
rst_n <= 1'b0;
#200 rst_n <= 1'b1;
end
always #10 clk = ~clk;
initial begin
rx <= 1'b1;
#200 rx_byte();
end
task rx_byte();
integer j;
for (j = 0; j < 10000; j = j + 1) rx_bit(data_mem[j]);
endtask
task rx_bit(input [7:0] data); //data是data_mem[j]的值。
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0; //起始位
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7]; //上面8个发送的是数据位
9: rx <= 1'b1; //停止位
endcase
#1040; //一个波特时间=sclk周期*波特计数器
end
endtask
//重定义defparam,用于修改参数,缩短仿真时间
defparam sobel_inst.uart_rx_inst.CLK_FREQ = 500000;
defparam sobel_inst.uart_tx_inst.CLK_FREQ = 500000;
//-------------sobel_inst-------------
sobel sobel_inst (
.sys_clk (clk), //input sys_clk
.sys_rst_n(rst_n), //input sys_rst_n
.rx (rx), //input rx
.hsync(hsync), //output hsync
.vsync(vsync), //output vsync
.rgb (rgb), //output [7:0] rgb
.tx (tx) //output tx
);
endmodule
| 8.05892 |
module tb_soc ();
reg cpu_en;
reg clk;
reg rst_n;
reg io_rtcToggle;
wire rd_insn_en;
wire [ `PC_WIDTH - 1 : 0] pc;
reg [`WORD_WIDTH - 1 : 0] insn;
soc_top u_soc_top (
.cpu_en (cpu_en),
.clk (clk),
.rst_n (rst_n),
.io_rtcToggle(io_rtcToggle),
.rd_insn_en (rd_insn_en),
.pc (pc),
.insn (insn)
);
reg [7 : 0] counter;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 8'b0;
end else begin
counter <= counter + 1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
io_rtcToggle <= 1'b0;
end else if (counter == 8'h11) begin
io_rtcToggle <= 1'b1;
end else begin
io_rtcToggle <= 1'b0;
end
end
parameter TIME_CLK = 10;
always #(TIME_CLK / 2) clk = ~clk;
reg [31:0] itcm[0:1023];
initial begin
$readmemh("itcm.hex", itcm);
end
always @(*) begin
if (rd_insn_en) begin
insn = itcm[pc[11:2]];
end else begin
insn = 0;
end
end
initial begin
#0 begin
clk = 0;
cpu_en = 0;
rst_n = 0;
end
#22 begin
rst_n = 1;
end
// after itcm has insn
#20 begin
cpu_en = 1;
end
#10000 $finish;
end
initial begin
$dumpfile("soc.vcd");
$dumpvars(0, tb_soc);
end
endmodule
| 6.85777 |
module: soc_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_soc_block;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
reg clk_mem;
// Outputs
wire tx;
wire interrupt_ack;
wire [22:0] addr_mem_mem_interface;
wire [6:0] control_mem;
wire [2:0] zero;
// Bidirs
wire [15:0] data_mem_mem_interface;
// Instantiate the Unit Under Test (UUT)
soc_block uut (
.clk(clk),
.reset(reset),
.tx(tx),
.rx(rx),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.addr_mem_mem_interface(addr_mem_mem_interface),
.data_mem_mem_interface(data_mem_mem_interface),
.control_mem(control_mem),
.clk_mem(clk_mem),
.zero(zero)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk_mem = 0;
clk = 0;
reset = 0;
rx = 1;
interrupt = 0;
bit8 = 1;
parity_en = 1;
odd_n_even = 1;
baud_val = 1011;
#20;
reset=1;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
end
endmodule
| 6.636792 |
module tb_soc_bram_ctl ();
parameter PERIOD = 2;
reg clk = 0; // Posedge = 0
wire [31:0] dread;
wire done;
reg [31:0] dwrite;
reg [7:0] addr;
reg rw, valid;
`ifdef SIM
always #(PERIOD / 2) clk = ~clk;
`endif
initial begin
`ifdef SIM
$dumpfile("tb_bram_ctl.vcd");
$dumpvars(0, bram_ctl, f_state);
rw <= 1;
addr <= 32;
dwrite <= 32'h1122_3344;
#(PERIOD * 3) rw <= 1;
addr <= 36;
dwrite <= 32'h5566_7788;
#(PERIOD * 3) rw <= 0;
addr <= 36;
#(PERIOD * 3) $finish;
`endif
end
initial valid = 1;
reg [ 7:0] f_addr = 128;
reg [31:0] f_data = 32'h1122_3344;
reg [ 2:0] f_state;
initial f_state = 0;
/*always @(posedge clk)
case(f_state)
// First, write to address
0: begin
rw <= 1;
addr <= f_addr;
dwrite <= f_data;
f_state <= 1;
end
// Second, read from same address
1: if(done) begin
addr <= f_addr+1;
rw <= 0;
f_state <= 2;
end
2: if(done) f_state <= 3;
3: f_state <= 0;
endcase*/
soc_bram_ctl #(
.addr_width(8)
) bram_ctl (
.clk(clk),
.addr(addr),
.rw(rw),
.dread(dread),
.dwrite(dwrite),
.valid(valid),
.ready(done)
);
endmodule
| 6.681025 |
module tb_soc_j68 (
input UART0_RX, // RX load port
output UART0_TX, // TX load port
input UART1_RX, // RX terminal
output UART1_TX // TX terminal
);
// ========================================================================
// Reset and clock generation
// ========================================================================
wire rst;
wire clk;
tb_clock U_tb_clock (
.rst_100(rst),
.clk_100(clk)
);
// ========================================================================
// 68000-based system-on-a-chip
// ========================================================================
soc_j68 DUT_soc_j68 (
.rst (rst),
.clk (clk),
.clk_ena (1'b1),
// UART #0
.uart0_rxd (UART0_RX),
.uart0_cts_n(1'b0),
.uart0_dcd_n(1'b0),
.uart0_txd (UART0_TX),
.uart0_rts_n( /* open */),
// UART #1
.uart1_rxd (UART1_RX),
.uart1_cts_n(1'b0),
.uart1_dcd_n(1'b0),
.uart1_txd (UART1_TX),
.uart1_rts_n( /* open */)
);
endmodule
| 7.002042 |
module tb_softusb ();
reg sys_clk;
reg sys_rst;
reg usb_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 50MHz USB clock (should be 48) */
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
wire usba_vp;
wire usba_vm;
softusb dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di),
.irq(irq),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i (wb_we_i),
.wb_sel_i(4'hf),
.wb_ack_o(wb_ack_o),
.usba_spd (),
.usba_oe_n(),
.usba_rcv (usba_vp),
.usba_vp (usba_vp),
.usba_vm (usba_vm),
.usbb_spd (),
.usbb_oe_n(),
.usbb_rcv (),
.usbb_vp (),
.usbb_vm ()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
always begin
$dumpfile("softusb.vcd");
$dumpvars(0, dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
csrwrite(32'h00, 32'h00);
#7000;
wbread(32'h00020000);
wbread(32'h00020004);
$finish;
end
/* transmitter */
reg usb_clk_tx;
initial usb_clk_tx = 1'b0;
always #10 usb_clk_tx = ~usb_clk_tx;
reg usb_rst_tx;
reg [7:0] tx_data;
reg tx_valid;
wire txp;
wire txm;
wire txoe;
softusb_tx tx (
.usb_clk(usb_clk_tx),
.usb_rst(usb_rst_tx),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(),
.txp (txp),
.txm (txm),
.txoe(txoe),
.low_speed(1'b0),
.generate_eop(1'b0)
);
pullup (usba_vp);
pulldown (usba_vm);
assign usba_vp = txoe ? txp : 1'bz;
assign usba_vm = txoe ? txm : 1'bz;
initial begin
$dumpvars(0, tx);
usb_rst_tx = 1'b1;
tx_valid = 1'b0;
#20;
usb_rst_tx = 1'b0;
#4000;
tx_data = 8'h80;
tx_valid = 1'b1;
#400;
tx_data = 8'h56;
#400;
tx_valid = 1'b0;
end
endmodule
| 6.540109 |
module tb_sort;
reg clk, rst_n;
reg vaild_i;
reg [ 15:0] v_in;
reg [127:0] x_in;
wire [ 15:0] v_out;
wire [127:0] x_out;
wire datavaild_o;
top top_sort_u0 (
.clk(clk),
.rst_n(rst_n),
.vaild_i(vaild_i),
.v_in(v_in),
.x_in(x_in),
.v_out(v_out),
.datavaild_o(datavaild_o),
.x_out(x_out)
);
initial begin
$fsdbDumpfile("./build/simtop.fsdb");
$fsdbDumpvars("+all");
end
initial begin
rst_n = 0;
clk = 0;
v_in = 16'b0110_0101_1111_0000;
x_in = 128'h01_12_23_34_45_56_67_78_89_9A_AB_BC_CD_DE_EF_F0;
vaild_i = 0;
#5 rst_n = 1;
#10 vaild_i = 1;
#2 vaild_i = 0;
#10 $finish;
end
always #1 clk = ~clk;
endmodule
| 6.600177 |
module sort2_tb ();
// Signal Declarations
reg [3:0] in0, in1; // Inputs
wire [3:0] out0, out1; // Outputs
// Unit Under Test Instantiation
sort2 UUT (
.in0 (in0),
.in1 (in1),
.out0(out0),
.out1(out1)
);
initial begin
in1 = 4'b0000;
in0 = 4'b1111;
#10
// Print Current
$display(
"in0 = %4b in1 = %4b | out0 = %4b out1 = %4b", in0, in1, out0, out1
);
// Automatically stop testbench execution
$stop;
end
endmodule
| 6.65339 |
module tb_sort2values;
/*test the three cases A=B, A<B, A>B and verify the control signal start and
and the push signal*/
reg clock;
reg reset;
reg start;
reg [7:0] A, B;
wire [7:0] data_out;
wire push;
initial //following block executed only once
begin
clock = 0;
reset = 0;
#10 reset = 1;
start = 1;
A = 5;
B = 5;
#20 start = 0;
#10 start = 1;
A = 10;
B = 20;
#20 start = 0;
#10 start = 1;
A = 200;
B = 100;
#10 start = 0;
end
always #5 clock = ~clock; //10ns clock
sort_2_values u1 (
clock,
reset,
start,
A,
B,
data_out,
push
);
endmodule
| 6.666778 |
module sort4_tb ();
// Signal Declarations
reg [3:0] in0, in1, in2, in3; // Inputs
wire [3:0] out0, out1, out2, out3; // Outputs
// Unit Under Test Instantiation
sort4 UUT (
.in0 (in0),
.in1 (in1),
.in2 (in2),
.in3 (in3),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
);
initial begin
in3 = 4'b0000;
in2 = 4'b0001;
in1 = 4'b0010;
in0 = 4'b1111;
#10
// Print Current
$display(
"in0 = %4b in1 = %4b in2 = %4b in3 = %4b", in0, in1, in2, in3
);
$display("out0 = %4b out1 = %4b out2 = %4b out3 = %4b", out0, out1, out2, out3);
// Automatically stop testbench execution
$stop;
end
endmodule
| 6.672724 |
module TB_Sorter #(
parameter N = 16,
W = 16
);
// Inputs
reg clk;
reg [W-1:0] DATA_IN[N-1:0];
reg start;
// Outputs
wire [N*W-1:0] keyIn, keyOut;
//wire [N*W:0] keyIn_tmp [0:1];
wire [W-1:0] DATA_OUT[N-1:0];
wire ready;
integer f, i;
SorterMain #(4, W) sorter (
//INPUT
.clk (clk),
.start(start),
.keyIn(keyIn),
//OUTPUT
.keyOut(keyOut),
.ready (ready)
);
//assign key = (wr_en) ? keyIn_tmp[address] : ((rst)? 0: {N*16{1'bz}}); // To drive the inout net
//assign keyOut = key ; // To drive the inout net
////////////////////////////
/// convert input and output
`PACK_ARRAY(16, N, DATA_IN, keyIn);
//`UNPACK_ARRAY2 (512, 2, keyIn_tmp , keyIn );
`UNPACK_ARRAY(16, N, DATA_OUT, keyOut);
///
////////////////////////////
// 500MHz frequency
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
f = $fopen("D:/output.hex", "w");
$readmemh("D:/input.hex", DATA_IN); //hex
start <= 1'b1;
#2 start <= 1'b0;
////////////////////////////////////////
@(posedge ready);
////////////////////////////////////////
//read data from sorter
//@(posedge clk)
@(posedge clk)
for (i = 0; i < N; i = i + 1) begin
$fwrite(f, "%h\n", DATA_OUT[i]); //1
end
$fclose(f);
end
endmodule
| 6.837896 |
module tb_sort_4sequence ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 96000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
reg ini;
reg writeoutput;
reg [1:0] count;
reg [1:0] countout;
integer outfile;
integer infile;
initial count = 2'b0;
initial countout = 2'b0;
initial ini = 1'b0;
initial writeoutput = 1'b0;
initial begin
outfile = $fopen("output.txt", "w");
infile = $fopen("input.txt", "w");
if (0 == outfile) begin
$display("ERROR: could not open output.txt");
$finish();
end
if (0 == infile) begin
$display("ERROR: could not open input.txt");
$finish();
end
end
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / 2) tb_clk = ~tb_clk;
// DUT
wire [ (`NUM_ELEMS * `DATA_WIDTH)-1 : 0] outp;
wire [(`NUM_ELEMS * `DATA_WIDTH) - 1 : 0] inps;
wire [(`NUM_ELEMS * `DATA_WIDTH) - 1 : 0] max;
sort4_sequence_test #(
.data_width(`DATA_WIDTH)
) my_inner_product_test (
.clk(tb_clk),
.outp(outp),
.max(max),
.outp_inps(inps) // the count
);
// display inputs and output on each clock cycle
always @(posedge tb_clk) begin
ini <= 1'b1;
count <= count + 1'b1;
if (ini == 1'b0) begin
count <= 2'b0;
end
if (count == 2'b11) begin
$fwrite(infile, "\n");
end
if (count == 2'b10) begin
writeoutput <= 1'b1;
end
if (writeoutput == 1'b1) begin
countout <= countout + 1'b1;
$fwrite(outfile, "%d ", outp);
end
if (countout == 2'b11) begin
$fwrite(outfile, "\n");
end
$display("inps = ", inps, " => outp = ", outp, " max = ", max);
$fwrite(infile, "%d ", inps);
end
endmodule
| 7.411279 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.
// If not, see <https://www.gnu.org/licenses/>
////////////////////////////////////////////////////////////////////////////////
module tb_SOS;
parameter WIX = 3, // integer part bitwidth for input sample
WFX = 7, // fractional part bitwidth for input sample
WIC = 3, // integer part bitwidth for Coefficient
WFC = 8, // fractional part bitwidth for Coefficient
WIS = 5, // integer part bitwidth for Scaling
WFS = 11, // fractional part bitwidth for Scaling
WIO =8, // integer part bitwidth for addition output (user input)
WFO =18, // integer part bitwidth for addition outout (user input)
N = 2 ; // order
// Inputs
reg [(WIO+WFO-1):0] X;
reg [(WIS+WFS-1):0] S;
reg CLK;
reg RESET;
// Outputs
wire [(WIO+WFO-1):0] Y;
wire OF_add;
wire OF_mult;
real in1_real,out_real;
function real fixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx<WI+WF-1;idx = idx+1)begin
if(in[idx] == 1'b1)begin
retVal = retVal + (2.0**(idx-WF));
end
end
fixedToFloat = retVal -(in[WI+WF-1]*(2.0**(WI-1)));
end
endfunction
// Instantiate the Unit Under Test (UUT)
SOS #(.WIX(WIX),.WFX(WFX),.WIC(WIC),. WFC( WFC),.WIS(WIS),.WFS(WFS),.WIO(WIO),.WFO(WFO),.N(N)) uut (
.X(X),
.S(S),
.CLK(CLK),
.RESET(RESET),
.Y(Y),
.OF_add1(OF_add1),
.OF_mult1(OF_mult1)
);
parameter clockperiod = 20;
initial CLK = 0;
always #(clockperiod/2) CLK = ~ CLK;
parameter data_width = 26;
parameter addr_width = 50;
reg [(data_width-1):0] rom [addr_width-1:0];
initial begin
$readmemb ("input.txt",rom);
end
integer i;
initial begin
X = 0;
RESET = 0;
@(posedge CLK) RESET = 1;
for (i = 0; i <= 49 ; i = i + 1 )begin
@(posedge CLK) X = rom[i]; S = 16'b00001_00000000000;
$display (fixedToFloat(Y,WIO,WFO));
end
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
$finish;
end
always @ X in1_real = fixedToFloat(X,WIX+WIS,WFX+WFS);
always @ Y out_real = fixedToFloat(Y,WIO,WFO);
endmodule
| 7.743492 |
module tb_SpecialPcUnit;
localparam ADDRESS_BITS = 20;
localparam DATA_WIDTH = 32;
reg clk;
reg rst;
reg en;
reg [ADDRESS_BITS-1:0] curr_pc;
wire done;
wire valid;
wire [ADDRESS_BITS-1:0] out_pc;
SpecialPcUnit uut (
.clk (clk),
.en (en),
.rst (rst),
.curr_pc(curr_pc),
.done (done),
.valid (valid),
.out_pc (out_pc)
);
always #1 clk = !clk;
always #2 curr_pc = curr_pc + 4;
initial begin
$dumpfile("specialunit.vcd");
$dumpvars();
clk = 1;
rst = 1;
en = 0;
curr_pc = 20'hb000f;
#10;
rst = 0;
#10 en = 1;
#2 en = 0; // en has to be asserted only for one cycle to trigger
#10 en = 1;
#4 en = 0;
#100;
$finish;
end
endmodule
| 6.905456 |
module: spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_spi;
// Inputs
reg clk;
reg enviar_dato;
reg recibir_dato;
reg [7:0] din;
reg spi_do;
// Outputs
wire [7:0] dout;
wire oe_n;
wire spi_clk;
wire spi_di;
// Instantiate the Unit Under Test (UUT)
spi uut (
.clk(clk),
.enviar_dato(enviar_dato),
.recibir_dato(recibir_dato),
.din(din),
.dout(dout),
.oe_n(oe_n),
.spi_clk(spi_clk),
.spi_di(spi_di),
.spi_do(spi_do)
);
initial begin
// Initialize Inputs
clk = 0;
enviar_dato = 0;
recibir_dato = 0;
din = 0;
spi_do = 0;
// Wait 100 ns for global reset to finish
#300;
din = 8'b11001011;
enviar_dato = 1;
#700;
enviar_dato = 0;
#2000;
recibir_dato = 1;
spi_do = 1;
@(negedge spi_clk);
spi_do = 0;
@(negedge spi_clk);
spi_do = 1;
@(negedge spi_clk);
spi_do = 1;
@(negedge spi_clk);
spi_do = 0;
@(negedge spi_clk);
spi_do = 0;
@(negedge spi_clk);
spi_do = 1;
@(negedge spi_clk);
spi_do = 1;
@(negedge spi_clk);
#200;
recibir_dato = 0;
#100;
$finish;
end
always begin
clk = #71.428571428571428571428571428571 ~clk;
end
endmodule
| 6.909089 |
module testbench;
reg clk = 0;
reg cs;
reg sr_in;
reg [7:0] data;
wire sr_out;
wire [7:0] gpioout;
integer i;
spigpio testbe (
.clk(clk),
.cs(cs),
.sr_in(sr_in),
.gpioout(gpioout),
.sr_out(sr_out)
);
initial begin
i = 0;
data = 8'hAA;
cs = 1'b0;
for (i = 0; i < 9; i = i + 1) begin
#10 clk = 1;
#10 clk = 0;
end
cs = 1'b1;
for (i = 0; i < 4; i = i + 1) begin
#10 clk = 1;
#10 clk = 0;
end
end
always @(negedge clk) begin
sr_in = data[7];
data = data << 1;
end
initial begin
$dumpfile("spigpio.vcd");
$dumpvars(0, clk, cs, sr_in, gpioout, sr_out);
end
endmodule
| 7.015571 |
module tb_spi_flash_be ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 clk <= ~clk;
defparam memory.mem_access.initfile = "initmemory.txt";
//-------------spi_flash_erase-------------
spi_flash_be spi_flash_be_inst (
.sys_clk (clk), //系统时钟，频率50MHz
.sys_rst_n(rst_n), //复位信号,低电平有效
.pi_key (key), //按键输入信号
.sck (sck), //串行时钟
.cs_n(cs_n), //片选信号
.mosi(mosi) //主输出从输入数据
);
m25p16 memory (
.c (sck), //输入串行时钟,频率12.5Mhz,1bit
.data_in(mosi), //输入串行指令或数据,1bit
.s (cs_n), //输入片选信号,1bit
.w (1'b1), //输入写保护信号,低有效,1bit
.hold (1'b1), //输入hold信号,低有效,1bit
.data_out() //输出串行数据
);
endmodule
| 6.979364 |
module tb_spi_flash_pp ();
//wire define
wire cs_n;
wire sck;
wire mosi;
wire [7:0] cmd_data;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
initial begin
$timeformat(-9, 0, "ns", 16);
$monitor("@time %t: key=%b ", $time, key);
$monitor("@time %t: cs_n=%b", $time, cs_n);
$monitor("@time %t: cmd_data=%d", $time, cmd_data);
end
always #10 clk <= ~clk;
defparam memory.mem_access.initfile = "initmemory.txt";
//-------------spi_flash_pp-------------
spi_flash_pp spi_flash_pp_inst (
.sys_clk (clk), //input sys_clk
.sys_rst_n(rst_n), //input sys_rst
.pi_key (key), //input key
.sck (sck), //output sck
.cs_n(cs_n), //output cs_n
.mosi(mosi) //output mosi
);
m25p16 memory (
.c (sck),
.data_in (mosi),
.s (cs_n),
.w (1'b1),
.hold (1'b1),
.data_out()
);
endmodule
| 6.979364 |
module tb_spi_flash_read ();
//wire define
wire cs_n;
wire sck;
wire mosi;
wire miso;
wire tx;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 clk <= ~clk;
defparam memory.mem_access.initfile = "initM25P16_test.txt";
defparam spi_flash_read_inst.flash_read_ctrl_inst.CNT_WAIT_MAX = 1000;
defparam spi_flash_read_inst.uart_tx_inst.CLK_FREQ = 100000;
//------------- spi_flash_read -------------
spi_flash_read spi_flash_read_inst (
.sys_clk (clk), //input sys_clk
.sys_rst_n(rst_n), //input sys_rst
.pi_key (key), //input key
.miso (miso),
.sck (sck), //output sck
.cs_n(cs_n), //output cs_n
.mosi(mosi), //output mosi
.tx (tx)
);
//------------- memory -------------
m25p16 memory (
.c (sck),
.data_in (mosi),
.s (cs_n),
.w (1'b1),
.hold (1'b1),
.data_out(miso)
);
endmodule
| 6.979364 |
module tb_spi_flash_se ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 clk <= ~clk;
defparam memory.mem_access.initfile = "initmemory.txt";
//-------------spi_flash_se-------------
spi_flash_se spi_flash_se_inst (
.sys_clk (clk), //系统时钟，频率50MHz
.sys_rst_n(rst_n), //复位信号,低电平有效
.pi_key (key), //按键输入信号
.sck (sck), //串行时钟
.cs_n(cs_n), //片选信号
.mosi(mosi) //主输出从输入数据
);
m25p16 memory (
.c (sck), //输入串行时钟,频率12.5Mhz,1bit
.data_in(mosi), //输入串行指令或数据,1bit
.s (cs_n), //输入片选信号,1bit
.w (1'b1), //输入写保护信号,低有效,1bit
.hold (1'b1), //输入hold信号,低有效,1bit
.data_out() //输出串行数据
);
endmodule
| 6.979364 |
module tb_spi_flash_seq_wr ();
//wire define
wire tx;
wire cs_n;
wire sck;
wire mosi;
wire miso;
//reg define
reg clk;
reg rst_n;
reg rx;
reg [7:0] data_mem[299:0]; //data_mem是一个存储器，相当于一个ram
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial
$readmemh(
"E:/base_code/10_spi_flash/spi_flash_write/spi_flash_seq_wr/sim/spi_flash.txt", data_mem
);
//时钟、复位信号
initial begin
clk = 1'b1;
rst_n <= 1'b0;
#200 rst_n <= 1'b1;
end
always #10 clk = ~clk;
initial begin
rx <= 1'b1;
#200 rx_byte();
end
task rx_byte();
integer j;
for (j = 0; j < 300; j = j + 1) rx_bit(data_mem[j]);
endtask
task rx_bit(input [7:0] data); //data是data_mem[j]的值。
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0; //起始位
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7]; //上面8个发送的是数据位
9: rx <= 1'b1; //停止位
endcase
#1040; //一个波特时间=sclk周期*波特计数器
end
endtask
//重定义defparam,用于修改参数,缩短仿真时间
defparam spi_flash_seq_wr_inst.uart_rx_inst.CLK_FREQ = 500000;
defparam spi_flash_seq_wr_inst.uart_tx_inst.CLK_FREQ = 500000;
defparam memory.mem_access.initfile = "initmemory.txt";
//-------------spi_flash_seq_wr_inst-------------
spi_flash_seq_wr spi_flash_seq_wr_inst (
.sys_clk (clk), //input sys_clk
.sys_rst_n(rst_n), //input sys_rst_n
.rx (rx), //input rx
.cs_n(cs_n), //output cs_n
.sck (sck), //output sck
.mosi(mosi), //output mosi
.tx (tx) //output tx
);
m25p16 memory (
.c (sck),
.data_in (mosi),
.s (cs_n),
.w (1'b1),
.hold (1'b1),
.data_out(miso)
);
endmodule
| 6.979364 |
module TB_SPI_MasSlv;
reg rstb;
reg clk = 1'b0;
reg mlb = 1'b0;
reg start = 1'b0;
reg [7:0] m_tdat = 8'b00000000;
reg [1:0] cdiv = 0;
wire din;
wire ss;
wire sck;
wire dout;
wire Mdone;
wire [7:0] Mrdata;
reg ten = 1'b0;
reg [7:0] s_tdata = 8'b00000000;
wire SLVdone;
wire [7:0] SLVrdata;
parameter PERIOD = 50;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 100;
initial begin // Clock process for clk
#OFFSET;
forever begin
clk = 1'b0;
#(PERIOD - (PERIOD * DUTY_CYCLE)) clk = 1'b1;
#(PERIOD * DUTY_CYCLE);
end
end
// to end simulation
initial #10000 $stop;
//uut MASTER instantiation
spi_master MAS (
.rstb(rstb),
.clk(clk),
.mlb(mlb),
.start(start),
.tdat(m_tdat),
.cdiv(cdiv),
.din(din),
.ss(ss),
.sck(sck),
.dout(dout),
.done(Mdone),
.rdata(Mrdata)
);
//uut SLAVE instantiation
spi_slave SLV (
.rstb(rstb),
.ten(ten),
.tdata(s_tdata),
.mlb(mlb),
.ss(ss),
.sck(sck),
.sdin(dout),
.sdout(din),
.done(SLVdone),
.rdata(SLVrdata)
);
// timed contrl signals
initial begin
#10 rstb = 1'b0;
#100;
rstb = 1'b1;
start = 1'b0;
m_tdat = 8'b01111100;
cdiv = 2'b00;
#100 start = 1'b1;
ten = 1; //s_tdata=8'hAC;
#100 start = 1'b0;
#1800 mlb = 1'b1;
cdiv = 2'b01;
m_tdat = 8'b00011100; //s_tdata=8'h64;
#100 start = 1'b1;
#100 start = 1'b0;
#2202;
#100 start = 1'b1;
#100 start = 1'b0;
#2000;
m_tdat = ~m_tdat;
#100 start = 1'b1;
#100 start = 1'b0;
#2000;
end
always @(rstb or Mrdata) begin
if (rstb == 0) s_tdata = 8'hAA;
else begin
#10 s_tdata = Mrdata;
end
end
endmodule
| 7.040552 |
module tb_SPI_Master ();
reg clk;
reg rst;
wire SPI_MOSI;
wire SPI_SCLK;
wire SPI_CS;
wire SPI_MISO;
reg [31:0] sendData;
wire [31:0] recvData;
reg sendStart;
SPI_Master spimaster (
.clk(clk),
.rst(rst),
.sendStart(sendStart),
.SPI_MOSI(SPI_MOSI),
.SPI_SCLK(SPI_SCLK),
.SPI_CS(SPI_CS),
.SPI_MISO(SPI_MISO),
.sendData(sendData),
.recvData(recvData)
);
//pseud slave device
reg [31:0] slaveData;
reg [31:0] MOSIReg;
assign SPI_MISO = slaveData[31];
// pseud slave device
always @(posedge SPI_SCLK or negedge rst) begin
if (rst == 1'b0) begin
slaveData <= 32'hFEDCBA98;
MOSIReg <= 32'h00000000;
end else begin
slaveData <= {slaveData[30:0], 1'b0};
MOSIReg <= {MOSIReg[30:0], SPI_MOSI};
end
end
always #10
if (rst == 1'b0) clk <= 1'b0;
else clk <= ~clk;
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, spimaster);
#0 rst <= 1'b0;
sendData <= 32'h12345678;
sendStart <= 1'b0;
#30 rst <= 1'b0;
#50 rst <= 1'b1;
#50 sendStart <= 1'b1;
#2500 $finish;
end
endmodule
| 6.949372 |
module prescaler (
Q,
CLK
);
output [0:0] Q;
input CLK;
wire CLK;
wire [0:0] Q;
wire [4:0] plusOp;
wire \w_counter_reg_n_0_[0] ;
wire \w_counter_reg_n_0_[1] ;
wire \w_counter_reg_n_0_[2] ;
wire \w_counter_reg_n_0_[3] ;
LUT1 #(
.INIT(2'h1)
) \w_counter[0]_i_1 (
.I0(\w_counter_reg_n_0_[0] ),
.O (plusOp[0])
);
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6)
) \w_counter[1]_i_1 (
.I0(\w_counter_reg_n_0_[0] ),
.I1(\w_counter_reg_n_0_[1] ),
.O (plusOp[1])
);
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78)
) \w_counter[2]_i_1 (
.I0(\w_counter_reg_n_0_[1] ),
.I1(\w_counter_reg_n_0_[0] ),
.I2(\w_counter_reg_n_0_[2] ),
.O (plusOp[2])
);
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80)
) \w_counter[3]_i_1 (
.I0(\w_counter_reg_n_0_[2] ),
.I1(\w_counter_reg_n_0_[0] ),
.I2(\w_counter_reg_n_0_[1] ),
.I3(\w_counter_reg_n_0_[3] ),
.O (plusOp[3])
);
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \w_counter[4]_i_1 (
.I0(\w_counter_reg_n_0_[3] ),
.I1(\w_counter_reg_n_0_[1] ),
.I2(\w_counter_reg_n_0_[0] ),
.I3(\w_counter_reg_n_0_[2] ),
.I4(Q),
.O (plusOp[4])
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[0] (
.C (CLK),
.CE(1'b1),
.D (plusOp[0]),
.Q (\w_counter_reg_n_0_[0] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[1] (
.C (CLK),
.CE(1'b1),
.D (plusOp[1]),
.Q (\w_counter_reg_n_0_[1] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[2] (
.C (CLK),
.CE(1'b1),
.D (plusOp[2]),
.Q (\w_counter_reg_n_0_[2] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[3] (
.C (CLK),
.CE(1'b1),
.D (plusOp[3]),
.Q (\w_counter_reg_n_0_[3] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[4] (
.C (CLK),
.CE(1'b1),
.D (plusOp[4]),
.Q (Q),
.R (1'b0)
);
endmodule
| 7.858126 |
module tb_SPI_Transmitter ();
reg clk;
reg rst;
wire sendComplete;
wire MOSI;
wire SCLK;
wire CS;
wire MISO;
reg [31:0] sendData;
wire [31:0] recvData;
SPI_Transmitter transmitter (
.clk(clk),
.rst(rst),
.sendComplete(sendComplete),
.MOSI(MOSI),
.SCLK(SCLK),
.CS(CS),
.MISO(MISO),
.sendData(sendData),
.recvData(recvData)
);
reg [31:0] slaveData;
reg [31:0] MOSIReg;
assign MISO = slaveData[31];
// pseud slave device
always @(posedge SCLK or negedge rst) begin
if (rst == 1'b0) begin
slaveData <= 32'hFEDCBA98;
MOSIReg <= 32'h00000000;
end else begin
slaveData <= {slaveData[30:0], 1'b0};
MOSIReg <= {MOSIReg[30:0], MOSI};
end
end
always #10
if (rst == 1'b0) clk <= 1'b0;
else clk <= ~clk;
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, transmitter);
#0 rst <= 1'b1;
sendData <= 32'h12345678;
#30 rst <= 1'b0;
#50 rst <= 1'b1;
#2500 $finish;
end
endmodule
| 7.051019 |
module tb_SpongentHash;
wire [87:0] hash;
reg [87:0] reference_hash;
reg clk;
reg rst;
reg en;
wire rdy;
SpongentHash uut (
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy),
.hash_out(hash)
);
initial begin
clk = 0;
rst = 1;
en = 0;
// Set reference Hash value, to test if the result is right.
// Hash for "Hello WorldHello World ZY"
// reference_hash = 88'ha9b5344ec2f458323a1acc;
// Hash for "Spongent is a lightweight Hashfunction"
reference_hash = 88'h06846ff7186c0cfa5dfd32;
#100;
rst = 0;
en = 1;
end
always begin
#5;
clk = !clk;
end
always @rdy begin
if (rdy == 1) begin
$display("hash %h", hash);
if (hash === reference_hash) begin
$display("SUCCESS");
end
end
end
endmodule
| 6.627228 |
module: SPSLmnCE
//
// Dependencies:
//
// Revision:
//
// 0.01 13G20 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_SPSLmnCE;
parameter pDataWidth = 8;
parameter pAddrWidth = 4;
parameter pDepth = (2**pAddrWidth);
// UUT Port List Declarations
reg Rst;
reg Clk;
reg En;
reg Psh;
reg Pop;
reg [7:0] DI;
wire [7:0] DO;
wire Err;
// Simulation Variables
integer i = 0;
// Instantiate the Unit Under Test (UUT)
SPSLmnCE #(
.pDataWidth(8),
.pAddrWidth(4)
) uut (
.Rst(Rst),
.Clk(Clk),
.En(En),
.Psh(Psh),
.Pop(Pop),
.DI(DI),
.DO(DO),
.Err(Err)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
En = 0;
Psh = 0;
Pop = 0;
DI = 0;
// Wait 100 ns for global reset to finish
#101 Rst = 0;
// Add stimulus here
for(i = 1; i < 17; i = i + 1) begin
LIFO_Psh({i[3:0], i[3:0]});
end
LIFO_Pop;
LIFO_Psh(8'h01);
for(i = 1; i < 17; i = i + 1) begin
LIFO_Pop();
end
LIFO_Psh(8'h01);
LIFO_Psh(8'h02);
LIFO_Psh(8'h04);
LIFO_Psh(8'h08);
LIFO_Psh(8'h10);
LIFO_Psh(8'h20);
LIFO_Psh(8'h40);
LIFO_Psh(8'h80);
LIFO_Psh(8'h7F);
LIFO_Psh(8'hBF);
LIFO_Psh(8'hDF);
LIFO_Psh(8'hEF);
LIFO_Psh(8'hF7);
LIFO_Psh(8'hFB);
LIFO_Psh(8'hFD);
LIFO_Psh(8'hFE);
LIFO_Psh(8'h00);
LIFO_Psh(8'h00);
for(i = 1; i < 17; i = i + 1) begin
LIFO_Pop();
end
LIFO_Pop();
LIFO_Pop();
end
////////////////////////////////////////////////////////////////////////////////
//
// Clocks and Enables
//
always #5 Clk = ~Clk;
always @(posedge Clk)
begin
if(Rst)
En <= #1 0;
else
En <= #1 ~En;
end
////////////////////////////////////////////////////////////////////////////////
//
// Tasks and Functions
//
// LIFO Write Task
task LIFO_Psh;
input [(pDataWidth - 1):0] Data;
begin
@(posedge En) Psh = 1; DI = Data;
@(posedge Clk) #1 Psh = 0;
end
endtask
// LIFO Read Task
task LIFO_Pop;
begin
@(posedge En) Pop = 1;
@(posedge Clk) #1 Pop = 0;
end
endtask
endmodule
| 7.139502 |
module tb_sp_mash111;
// mash111 Parameters
parameter PERIOD = 10;
parameter WIDTH = 9;
parameter OUT_REG = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] y_o;
wire [WIDTH-1:0] e_o;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
integer dout_file;
initial begin
dout_file = $fopen("mash111-spefm-i0.5-reg-new.txt", "w"); //打开所创建的文件
if (dout_file == 0) begin
$display("can not open the file!"); //创建文件失败，显示can not open the file!
$stop;
end
end
always @(posedge clk) begin
$fdisplay(dout_file, "%d", $signed(y_o)); //保存有符号数据
end
sp_mash111 #(
.OUT_REG(OUT_REG)
) u_sp_mash111 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i[WIDTH-1:0]),
.y_o(y_o[3:0]),
.e_o(e_o[WIDTH-1:0])
);
initial begin
// x_i = 'd8388608; // 2^23 (0.5)
x_i = 'd16; // 2^4 (0.5)
#(PERIOD * 10000);
$finish;
end
endmodule
| 6.650396 |
module tb_squareroot ();
reg [15:0] num = 'b0;
wire [7:0] sqr;
wire sqr_flag;
reg CLK = 0;
reg RST = 1;
square_root dut (
.num(num),
.CLK(CLK),
.RST(RST),
.sqr(sqr),
.sqr_flag(sqr_flag)
);
always #2.5 CLK = ~CLK;
initial begin
#2 RST = 0;
#5 num = 16'd4;
#5;
num = 16'd25;
#5;
num = 16'd33;
#5;
num = 16'd49;
#8;
num = 16'd6536;
#8;
num = 16'd121;
#7;
end
initial begin
$monitor("Square Root of number %d is %d", num, sqr);
end
endmodule
| 6.599975 |
module TB_SRAM_Controller ();
reg clk = 1'b0, rst = 1'b0;
// Input from Memory Stage
reg write_enable = 1'b0, read_enable = 1'b0;
reg [ `ADDRESS_LEN - 1 : 0] address;
reg [ `REGISTER_LEN - 1 : 0] write_data;
// To WB Stage
wire [ `REGISTER_LEN - 1 : 0] read_data;
// To Freeze other Stages
wire ready;
//////////////////////// SRAM Interface ////////////////////////
wire [ `SRAM_DATA_BUS - 1 : 0] SRAM_DQ; // SRAM Data bus 16 Bits
wire [`SRAM_ADDRESS_BUS - 1 : 0] SRAM_ADDR; // SRAM Address bus 18 Bits
// Active Low Signals
wire SRAM_UB_N; // SRAM High-byte Data Mask
wire SRAM_LB_N; // SRAM Low-byte Data Mask
wire SRAM_WE_N; // SRAM Write Enable
wire SRAM_CE_N; // SRAM Chip Enable
wire SRAM_OE_N; // SRAM Output Enable
SRAM_Controller SRAM_Controller (
.clk(clk),
.rst(rst),
// Input from Memory .Stage(Stag)
.write_enable(write_enable),
.read_enable(read_enable),
.address(address),
.write_data(write_data),
// To WB Stage
.read_data(read_data),
// To Freeze other Stages
.ready(ready),
//////////////////////// SRAM Interface ////////////////////////
.SRAM_DQ (SRAM_DQ), // SRAM Data bus 16 Bits
.SRAM_ADDR(SRAM_ADDR), // SRAM Address bus 18 Bits
// Active Low Signals
.SRAM_UB_N(SRAM_UB_N), // SRAM High-byte Data Mask
.SRAM_LB_N(SRAM_LB_N), // SRAM Low-byte Data Mask
.SRAM_WE_N(SRAM_WE_N), // SRAM Write Enable
.SRAM_CE_N(SRAM_CE_N), // SRAM Chip Enable
.SRAM_OE_N(SRAM_OE_N) // SRAM Output Enable
);
initial repeat (1000) #100 clk = ~clk;
initial begin
#200 rst = 1'b1;
#100 rst = 1'b0;
#2000 write_enable = 1'b1;
read_enable = 1'b0;
address = `ADDRESS_LEN'd12;
write_data = `REGISTER_LEN'd31;
#200 write_enable = 1'b0;
#200 #2000 read_enable = 1'b1;
address = `ADDRESS_LEN'd15;
#200 read_enable = 1'b0;
end
endmodule
| 6.606895 |
module emulates the external SRAM device during simulation
module tb_SRAM_Emulator (
input logic Clock_50,
input logic Resetn,
inout wire [15:0] SRAM_data_io,
input logic [17:0] SRAM_address,
input logic SRAM_UB_N,
input logic SRAM_LB_N,
input logic SRAM_WE_N,
input logic SRAM_CE_N,
input logic SRAM_OE_N
);
parameter SRAM_SIZE = 262144;
logic Clock_100;
// 512 KB SRAM
logic [15:0] SRAM_data [SRAM_SIZE-1:0];
logic [15:0] SRAM_read_data;
// Generate the 100 MHz clock
always begin
#5;
Clock_100 = ~Clock_100;
end
initial begin
// This makes sure the clocks are in-phase
@ (negedge Clock_50);
Clock_100 = 1'b0;
end
// For writing into the SRAM
always_ff @ (posedge Clock_100 or negedge Resetn) begin : SRAM
integer i;
if (Resetn == 1'b0) begin
for (i = 0; i < SRAM_SIZE; i++)
SRAM_data[i] <= 16'd0;
end else begin
if (SRAM_OE_N == 1'b0 && SRAM_CE_N == 1'b0) begin
if (SRAM_UB_N == 1'b0) begin
if (SRAM_WE_N == 1'b0) begin
SRAM_data[SRAM_address] <= SRAM_data_io;
end
end
end
end
end
// For reading the SRAM
always_ff @ (negedge Clock_100 or negedge Resetn) begin
if (Resetn == 1'b0) begin
SRAM_read_data <= 16'd0;
end else begin
if (SRAM_OE_N == 1'b0 && SRAM_CE_N == 1'b0) begin
if (SRAM_UB_N == 1'b0) begin
if (SRAM_WE_N == 1'b1) begin
SRAM_read_data <= SRAM_data[SRAM_address];
end
end
end
end
end
// The bidirectional pin
assign SRAM_data_io = (SRAM_OE_N == 1'b0 && SRAM_CE_N == 1'b0 && SRAM_WE_N == 1'b0) ? 16'hzzzz : SRAM_read_data;
endmodule
| 7.334367 |
module tb_src_a_mux ();
localparam STEP = 10;
reg [31 : 0] pc;
reg [31 : 0] rs1_data;
reg [31 : 0] imm;
reg [`SEL_SRC_A_WIDTH - 1 : 0] select;
wire [31 : 0] alu_src_a;
src_a_mux src_a_mux (
.pc(pc),
.rs1_data(rs1_data),
.imm(imm),
.select(select),
.alu_src_a(alu_src_a)
);
initial begin
pc = 32'b100000;
rs1_data = 32'b1010;
imm = 32'b100;
#(STEP * 10)
for (integer i = 0; i <= 3; i = i + 1) begin
select = i;
#(STEP) $display("alu_src_a: %b", alu_src_a);
end
#(STEP * 100) $stop;
end
endmodule
| 6.886737 |
module tb_src_b_mux ();
localparam STEP = 10;
reg [31 : 0] rs2_data;
reg [31 : 0] imm;
reg [`SEL_SRC_B_WIDTH - 1 : 0] select;
wire [31 : 0] alu_src_b;
src_b_mux src_b_mux (
.rs2_data(rs2_data),
.imm(imm),
.select(select),
.alu_src_b(alu_src_b)
);
initial begin
rs2_data = 32'b1010;
imm = 32'b100;
#(STEP * 10)
for (integer i = 0; i <= 4; i = i + 1) begin
select = i;
#(STEP) $display("alu_src_b: %b", alu_src_b);
end
#(STEP * 100) $stop;
end
endmodule
| 7.118669 |
module tb_srlatch; //testbench of SR-Latch
reg tb_r, tb_s; // 2 inputs
wire tb_q, tb_q_bar; // use 2wires
_srlatch U0_srlatch (
.r(tb_r),
.s(tb_s),
.q(tb_q),
.q_bar(tb_q_bar)
); // instance by using _srlatch
initial begin
tb_r = 1'b0;
tb_s = 1'b0; //input (tb_r,tb_s)=(0,0)
#10;
tb_r = 1'b1; //after 10ns,input(tb_r)=1
#10;
tb_s = 1'b1; //after 10ns,input(tb_s)=1
#10;
tb_r = 1'b0; //after 10ns,input(tb_r)=0
#10;
tb_s = 1'b0; //after 10ns,input(tb_s)=0
#10;
tb_r = 1'b1; //after 10ns,input(tb_r)=1
#10;
$stop; //after 10ns, stop
end
endmodule
| 6.552543 |
module: SSP_UART
//
// Dependencies: SSP_UART
//
// Revision History:
//
// 0.01 08F13 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_SSP_UART_v;
// UUT Interface
reg Rst;
reg Clk;
reg SSP_SSEL;
reg SSP_SCK;
reg [2:0] SSP_RA;
reg SSP_WnR;
reg SSP_EOC;
reg [11:0] SSP_DI;
wire [11:0] SSP_DO;
wire TxD_232;
reg RxD_232;
wire xRTS;
reg xCTS;
wire TxD_485;
reg RxD_485;
wire xDE;
wire IRQ;
wire TxIdle;
wire RxIdle;
// Instantiate the Unit Under Test (UUT)
SSP_UART uut (
.Rst(Rst),
.Clk(Clk),
.SSP_SSEL(SSP_SSEL),
.SSP_SCK(SSP_SCK),
.SSP_RA(SSP_RA),
.SSP_WnR(SSP_WnR),
.SSP_EOC(SSP_EOC),
.SSP_DI(SSP_DI),
.SSP_DO(SSP_DO),
.TxD_232(TxD_232),
.RxD_232(RxD_232),
.xRTS(xRTS),
.xCTS(xCTS),
.TxD_485(TxD_485),
.RxD_485(RxD_485),
.xDE(xDE),
.IRQ(IRQ),
.TxIdle(TxIdle),
.RxIdle(RxIdle)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
SSP_SSEL = 0;
SSP_SCK = 1;
SSP_RA = 0;
SSP_WnR = 0;
SSP_EOC = 0;
SSP_DI = 0;
RxD_232 = 1;
xCTS = 0;
RxD_485 = 1;
// Wait 100 ns for global reset to finish
#101 Rst = 0;
// Add stimulus here
end
///////////////////////////////////////////////////////////////////////////////
//
// Simulation Clocks
//
always #5 Clk = ~Clk;
endmodule
| 7.30643 |
module tb_stage #(
parameter STAGE = 0, //valid: 0-4
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter KEY_LEN = 48 * 2 + 32 * 2 + 16 * 2 + 5,
parameter ACT_LEN = 25,
parameter KEY_OFF = 3 * 6
) ();
reg clk;
reg rst_n;
reg [PHV_LEN-1:0] phv_in;
reg phv_in_valid;
wire [PHV_LEN-1:0] phv_out;
wire phv_out_valid;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
set up the key extract table
*/
/*
give it a random phv to see what we can get
*/
phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
#CYCLE
phv_in <= {
48'hffffffffffff,
48'heeeeeeeeeeee,
288'h0,
32'hcccccccc,
32'hbbbbbbbb,
192'b0,
16'hffff,
16'heeee,
96'h0,
356'b0
};
phv_in_valid <= 1'b1;
#CYCLE phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
#(4 * CYCLE)
/*
switch the value in container 7 and 6
*/
phv_in <= {
48'hffffffffffff,
48'heeeeeeeeeeee,
288'h0,
32'hcccccccc,
32'hbbbbbbbb,
192'b0,
16'hffff,
16'heeee,
96'h0,
356'b0
};
phv_in_valid <= 1'b1;
#CYCLE phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
#(4 * CYCLE);
end
stage #(
.STAGE (STAGE),
.PHV_LEN(),
.KEY_LEN(),
.ACT_LEN(),
.KEY_OFF()
) stage (
.axis_clk(clk),
.aresetn (rst_n),
.phv_in(phv_in),
.phv_in_valid(phv_in_valid),
.phv_out(phv_out),
.phv_out_valid(phv_out_valid)
);
endmodule
| 7.268105 |
module tb_state ();
reg sclk;
reg s_rst_n;
reg catcher;
reg jockey_r;
reg jockey_l;
reg key;
wire direct;
wire stepenable;
initial begin
sclk = 1'b1;
s_rst_n <= 1'b0;
catcher <= 1'b1;
jockey_l <= 1'b1;
jockey_r <= 1'b1;
key <= 1'b0;
#100 s_rst_n <= 1'b1;
#100 key <= 1'b1;
#20 key <= 1'b0;
#100 catcher <= 1'b0;
jockey_l <= 1'b0;
#100 key <= 1'b1;
#20 key <= 1'b0;
end
always #10 sclk = ~sclk;
state state_inst (
.sclk (sclk),
.s_rst_n (s_rst_n),
.catcher (catcher),
.jockey_r (jockey_r),
.jockey_l (jockey_l),
.key (key),
.direct (direct),
.stepenable(stepenable)
);
endmodule
| 7.588164 |
module tb_state_cola_1 ();
reg sys_clk;
reg sys_rst_n;
reg pi_money;
wire po_cola;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
pi_money <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//pi_money 随机数模拟投币情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) pi_money <= 1'b0;
else pi_money <= {$random} % 2;
state_cola_1 state_cola_inst1 (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.pi_money (pi_money),
.po_cola(po_cola)
);
endmodule
| 6.556409 |
module tb_state_cola_2 ();
reg sys_clk;
reg sys_rst_n;
reg pi_money_one;
reg pi_money_half;
wire po_cola;
wire po_money;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
pi_money_half <= 1'b0;
pi_money_one <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//pi_money 随机数模拟投币情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) begin
pi_money_half <= 1'b0;
pi_money_one <= 1'b0;
end else begin
pi_money_half <= {$random} % 2;
pi_money_one <= {$random} % 2;
end
state_cola_2 state_cola_inst2 (
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.pi_money_half(pi_money_half),
.pi_money_one(pi_money_one),
.po_cola (po_cola),
.po_money(po_money)
);
endmodule
| 6.556409 |
module tb_stimulus_gen;
parameter PERIOD = 10; // 100MHz clock
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
// Inputs
// Internal Signals
reg clk;
wire [INPUT_PORTS-1:0] stm_value;
wire rsb;
wire gnt;
reg rst;
reg req;
// Stimulus generation
stimulus_gen #(
.INPUT_PORTS(INPUT_PORTS),
.RESET_PORT (RESET_PORT),
.RESET_SENS (RESET_SENS)
) stimulus_gen (
.clk(clk),
.rst(rst),
.req(req),
.stm_value(stm_value),
.rsb(rsb),
.gnt(gnt)
);
// Clock for signal generation
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
initial begin
// Initialize Inputs
rst = 1;
req = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
req = 0;
// Add stimulus here
#100;
req = 1;
$display("<< Starting the Simulation >>");
#100;
req = 0;
//$monitor(" %0d %b", $time, gnt);
end
endmodule
| 7.691737 |
module tb_stream_joint ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_stream_joint.vcd");
$dumpvars(0, tb_stream_joint);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter ID_WIDTH = 4;
parameter DATA_WIDTH = 32;
parameter S_REGS = 1;
parameter M_REGS = 1;
parameter ALGORITHM = "TOKEN_RING";
parameter USE_M_READY = 1;
reg cke = 1;
reg [ NUM-1:0] s_last;
reg [NUM*DATA_WIDTH-1:0] s_data;
reg [ NUM-1:0] s_valid = 0;
wire [ NUM-1:0] s_ready;
wire [ ID_WIDTH-1:0] m_id;
wire m_last;
wire [ DATA_WIDTH-1:0] m_data;
wire m_valid;
reg m_ready = 1;
integer i;
always @(posedge clk) begin
if (reset) begin
s_last <= {NUM{1'b0}};
s_data <= {(NUM * DATA_WIDTH) {1'b0}};
s_valid <= {NUM{1'b0}};
end else if (cke) begin
for (i = 0; i < NUM; i = i + 1) begin
if (s_valid[i] && s_ready[i]) begin
s_data[i*DATA_WIDTH+:DATA_WIDTH] <= s_data[i*DATA_WIDTH+:DATA_WIDTH] + 1;
s_last[i] <= (s_data[i*DATA_WIDTH+:4] == 15 - 1);
end
if (!s_valid[i] || s_ready[i]) begin
s_valid[i] <= {$random()};
end
end
if (m_valid && m_ready) begin
$display("%d %h %b", m_id, m_data, m_last);
end
end
end
jelly_stream_joint #(
.NUM (NUM),
.ID_WIDTH (ID_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.S_REGS (S_REGS),
.M_REGS (M_REGS),
.ALGORITHM (ALGORITHM),
.USE_M_READY(USE_M_READY)
) i_stream_joint (
.reset(reset),
.clk (clk),
.cke (cke),
.s_last (s_last),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_id (m_id),
.m_last (m_last),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
endmodule
| 7.268285 |
module tb_subbyte ();
reg clk;
reg rst_n;
reg [127:0] data_in;
reg start_in;
reg en_de;
// internal wires
wire [127:0] data_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("AC");
$dumpfile(DUMP_FILE);
$shm_open("tb.shm");
$shm_probe("AC");
end
initial begin
start_in = 0;
en_de = 1;
clk = 0;
rst_n = 1;
forever #5 clk = ~clk;
end
initial begin
#5 rst_n = 0;
#5 rst_n = 1;
#5 data_in = 127'h11223344_00000000_00000000_12345678;
#10 start_in = 1;
#10 start_in = 0;
#1000 $finish;
end
top_subbyte overall_sub (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.start_in(start_in),
.en_de(en_de),
.data_out(data_out),
.ready_out(ready_out)
);
endmodule
| 6.642068 |
module simulates the top-level module for the Sudoku Master
// game.
`timescale 1ns/1ns
module tb_sudokuMasterTop ();
reg CLK, RST;
reg [3:0] userNum;
reg upButton, downButton, leftButton, rightButton;
reg writeSwitch;
wire [6:0] userNumDisp;
wire wpInd;
wire [27:0] rowDisp;
wire winInd;
wire [6:0] time_onesDisp,time_tensDisp;
wire [15:0] rowNums;
wire [3:0] currentNum,time_ones,time_tens;
sudokuMasterTop DUT_sudokuMasterTop(userNum,upButton,downButton,leftButton,rightButton,writeSwitch,userNumDisp,wpInd,rowDisp,winInd,time_onesDisp,time_tensDisp,rowNums,currentNum,time_ones,time_tens,CLK,RST);
initial
begin
CLK<=0;
RST<=1;
userNum<=4'b0000;
upButton<=1'b0;
downButton<=1'b0;
leftButton<=1'b0;
rightButton<=1'b0;
writeSwitch<=1'b0;
end
always
begin
#10 CLK<=0;
#10 CLK<=1;
end
initial
begin
#25 RST<=0;
#40
#20 userNum<=4'b0100;
#20 writeSwitch<=1'b1;
#20 writeSwitch<=1'b0;
#40
#20 downButton<=1;
#20 downButton<=0;
#40
#20 userNum<=4'b0011;
#20 writeSwitch<=1'b1;
#20 writeSwitch<=1'b0;
#40
#20 leftButton<=1;
#20 leftButton<=0;
#40
#20 userNum<=4'b0010;
#20 writeSwitch<=1'b1;
#20 writeSwitch<=1'b0;
#40
#20 leftButton<=1;
#20 leftButton<=0;
#40
#20 userNum<=4'b0001;
#20 writeSwitch<=1'b1;
#20 writeSwitch<=1'b0;
#40
#20 upButton<=1;
#20 upButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0010;
#20 writeSwitch<=1'b0;
#40
#20 leftButton<=1;
#20 leftButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0011;
#20 writeSwitch<=1'b0;
#40
#20 downButton<=1;
#20 downButton<=0;
#40
#20 downButton<=1;
#20 downButton<=0;
#40
#20 userNum<=4'b0001;
#20 writeSwitch<=1'b1;
#20 writeSwitch<=1'b0;
#40
#20 downButton<=1;
#20 downButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0010;
#20 writeSwitch<=1'b0;
#40
#20 rightButton<=1;
#20 rightButton<=0;
#40
#20 rightButton<=1;
#20 rightButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0100;
#20 writeSwitch<=1'b0;
#40
#20 rightButton<=1;
#20 rightButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0001;
#20 writeSwitch<=1'b0;
#40
#20 upButton<=1;
#20 upButton<=0;
#40
#20 leftButton<=1;
#20 leftButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0011;
#20 writeSwitch<=1'b0;
#40
#20 leftButton<=1;
#20 leftButton<=0;
#40
#20 writeSwitch<=1'b1;
#20 userNum<=4'b0100;
#20 writeSwitch<=1'b0;
end
endmodule
| 6.687085 |
module: Sumador4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Sumador4;
// Inputs
reg [63:0] inputPC;
// Outputs
wire [63:0] Nextinst;
// Instantiate the Unit Under Test (UUT)
Sumador4 uut (
.inputPC(inputPC),
.Nextinst(Nextinst)
);
initial begin
// Initialize Inputs
inputPC = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.729994 |
module tb_super ();
localparam BITS = 8;
localparam T = 4;
localparam DATA_BITS = 64;
localparam PIPELINE_STAGES = 0;
localparam N = 127;
reg [BITS-1:0] data_in;
reg clk;
reg pre_start;
wire start;
reg ce;
wire ready;
wire [BITS-1:0] data_out;
wire first;
wire last;
wire data_bits;
wire ecc_bits;
wire [BITS-1:0] err_out;
wire first_out;
reg [DATA_BITS-1:0] error;
reg [BITS-1:0] corrected;
reg [DATA_BITS-1:0] data;
wire [DATA_BITS-1:0] errored = error ^ data;
reg [3:0] state;
parameter IDLE = 0, STARTS = 1;
reg [ 2:0] counter;
reg [N-1:0] codeword;
initial begin
clk = 0;
pre_start = 0;
data = 64'hCAFECAFECAFECAFE;
error = 64'h0000050000001000;
ce = 1;
#23 pre_start = 1;
#10 pre_start = 0;
end
always #5 clk = !clk;
always @(posedge clk) begin
if (first) begin
corrected <= errored;
end else if (first_out) begin
corrected <= corrected ^ err_out;
end else corrected <= corrected;
end
buff #(DATA_BITS, BITS) B1 (
.clk(clk),
.start_in(pre_start),
.b_in(data),
.b_out(data_in),
.start_out(start)
);
xilinx_encode #(T, DATA_BITS, BITS, PIPELINE_STAGES) encoder (
.data_in(data_in),
.clk_in(clk),
.start(start),
.ce(ce),
.ready(ready),
.data_out(data_out),
.first(first),
.last(last),
.data_bits(data_bits),
.ecc_bits(ecc_bits)
);
/*
buffer B2 #(DATA_BITS,BITS)(
.clk(clk),
.start_in(pre_start),
.b_in(data),
.b_out(data_in),
.start_out(start)
);
*/
xilinx_decoder #(T, DATA_BITS, BITS, 1, 1, 0, 0, 1) decoder (
.data_in(errored),
.clk_in(clk),
.start_in(first),
.err_out(err_out),
.first_out(first_out)
);
endmodule
| 6.67692 |
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