code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_tx;
reg clk;
reg rst_n;
reg we;
reg stb;
reg cyc;
reg [2:0] addr;
reg [7:0] data_o;
wire [7:0] data_i;
wire ack;
wire irq;
wire uart_pin;
reg [7:0] rx_data;
reg [7:0] irq_data;
nexi_uart_16550a_wb uart1 (
.clk_i (clk),
.rst_ni(rst_n),
.we_i (we),
.stb_i (stb),
.cyc_i (cyc),
.addr_i(addr),
.data_i(data_o),
.data_o(data_i),
.ack_o (ack),
.irq_o (irq),
.rx_pin(uart_pin), //loopback
.tx_pin(uart_pin)
);
initial begin
clk = 1'b0;
forever #1 clk = ~clk;
end
`define WB_WRITE(_addr, _data) \
addr <= _addr; \
data_o <= _data; \
stb <= 1'b1; \
cyc <= 1'b1; \
we <= 1'b1; \
wait ( ack == 1'b1) #1; \
addr <= 2'b00; \
data_o <= 8'h00; \
stb <= 1'b0; \
cyc <= 1'b0; \
we <= 1'b0; \
wait ( ack == 1'b0) #1;
`define WB_READ(_addr, _reg) \
addr <= _addr; \
stb <= 1'b1; \
cyc <= 1'b1; \
we <= 1'b0; \
wait ( ack == 1'b1) #1; \
addr <= 2'b00; \
_reg <= data_i;\
stb <= 1'b0; \
cyc <= 1'b0; \
wait ( ack == 1'b0) #1;
initial begin
$dumpfile("tb_uart_wb.vcd");
$dumpvars;
rst_n <= 1'b0;
we <= 1'b0;
stb <= 1'b0;
cyc <= 1'b0;
addr <= 2'b00;
data_o <= 8'h00;
#30; // wait for tx to init
rst_n <= 1'b1;
#1;
/* enable rx interrupt */
`WB_WRITE(3'b010, 8'h02)
/* send data */
`WB_WRITE(3'b001, 8'h55)
/* wait for rx */
wait (irq == 1'b1);
`WB_READ(3'b000, rx_data)
$display("Read data is %0x\n", rx_data);
$finish;
end
endmodule
| 6.681822 |
module tb_picosoc;
reg clk;
wire [7:0] test_led;
reg [7:0] test_button = 0;
reg [7:0] test_switch = 0;
wire ser_tx;
reg ser_rx = 1'b1;
localparam ser_half_period = 217;
event ser_sample;
reg [7:0] buffer = {(8) {1'bz}};
reg [7:0] rx_buffer = {(8) {1'bz}};
tri1 test_scl, test_sda;
reg i2c_slave_rst;
wire test_spi_miso;
wire [7:0] test_spi_ss;
wire test_spi_mosi;
wire test_spi_sck;
wire test_spi_cpol;
wire test_spi_cpha;
// clock parameters
parameter HALF_CLOCK_PERIOD_50M = 10;
parameter HALF_CLOCK_PERIOD_32M = 15625;
parameter HALF_CLOCK_PERIOD_10M = 50000;
parameter HALF_CLOCK_PERIOD_1M = 500000;
parameter HALF_CLOCK_PERIOD_100K = 5000000;
parameter HALF_CLOCK_PERIOD_4608 = 108506944;
// clock generation
always begin
clk = 1;
#HALF_CLOCK_PERIOD_50M;
clk = 0;
#HALF_CLOCK_PERIOD_50M;
end
task PRESS_KEY;
input [7:0] KEY;
begin
buffer = 0;
ser_rx = 1'b0;
rx_buffer = KEY;
repeat (ser_half_period) @(posedge clk);
->ser_sample; // start bit
repeat (8) begin
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
ser_rx = rx_buffer[0];
buffer = {ser_rx, buffer[7:1]};
rx_buffer = {1'b0, rx_buffer[6:1]};
->ser_sample; // data bit
end
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
->ser_sample; // stop bit
ser_rx = 1'b1;
end
endtask
task PRESS_ENTER;
parameter KEY_ENTER = 8'h0D; // 8'b 0000_1101
begin
PRESS_KEY(KEY_ENTER);
if (buffer == KEY_ENTER) $display("ENTER PRESSED");
else $display("INCORRECT KEY");
end
endtask
initial begin
#10;
i2c_slave_rst = 1;
#100;
i2c_slave_rst = 0;
repeat (50) #100000;
PRESS_ENTER;
repeat (30) #100000; //265 regular 30 nodebug
PRESS_KEY(8'h34); //PRESS "2"
repeat (150) #100000; //290 regular 60 nodebug
#10;
i2c_slave_rst = 1;
#100;
i2c_slave_rst = 0;
PRESS_KEY(8'h31); //PRESS "3"
repeat (150) #100000; //290 regular 60 nodebug
#10;
i2c_slave_rst = 1;
#100;
i2c_slave_rst = 0;
PRESS_KEY(8'h34); //PRESS "4"
//$finish;
end
ubsoc_debug uut (
.clk_i(clk),
.suart_tx_o(ser_tx),
.suart_rx_i(ser_rx),
.gpio_led_o (test_led),
.gpio_switch_i(test_switch),
.gpio_button_i(test_button),
.i2c_scl_mst_o (test_scl),
.i2c_sda_mst_io(test_sda),
.i2c_scl_slv_i (test_scl),
.i2c_sda_slv_io(test_sda)
/*
.spi_sck (test_spi_sck ),
.spi_ss (test_spi_ss ),
.spi_mosi (test_spi_mosi ),
.spi_miso (test_spi_miso )*/
);
/*
i2c_slave_model #(7'b001_0000) i2c_slave (
.scl (test_scl ),
.sda (test_sda )
);*/
/*
spi_slave_model_2 spi_slave (
.clock (clk ),
.csn (test_spi_ss[0] ),
.sck (test_spi_sck ),
.di (test_spi_mosi ),
.do (test_spi_miso ),
.cpol_i (test_spi_cpol ),
.cpha_i (test_spi_cpha )
);*/
/*i2cSlaveTop i2c_slave_full (
.clk(clk),
.rst(i2c_slave_rst),
.sda(test_sda),
.scl(test_scl),
.myReg0()
);*/
//assign test_spi_cpol = uut.spi_top.MSTR_CTRL.CPol;
//assign test_spi_cpha = uut.spi_top.MSTR_CTRL.CPha;
always begin
@(negedge ser_tx);
repeat (ser_half_period) @(posedge clk);
->ser_sample; // start bit
repeat (8) begin
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
buffer = {ser_tx, buffer[7:1]};
->ser_sample; // data bit
end
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
->ser_sample; // stop bit
if (buffer < 32 || buffer >= 127) begin
if (buffer == 13) $display("");
else
if (buffer == 10);
else $write("%d", buffer);
end else $write("%c", buffer);
end
endmodule
| 6.809553 |
module tb_uC_8Bit ();
//define inputs
reg _clk, _reset;
//define outputs
wire [5:0] _cycle;
wire [7:0] _romAddress;
wire [7:0] _instructionReg, _programCounter;
wire [7:0] _R0, _R1, _R2, _R3;
wire [7:0] _Rhi, _Rlo, _Rquotient, _Rremainder;
wire _ramWrite;
wire [7:0] _ramAddress;
wire [7:0] _romOut, _ramOut;
uC_8Bit DUT (
//define inputs
._clk (_clk),
._reset(_reset),
//define outputs
._cycle(_cycle),
._romAddress(_romAddress),
._instructionReg(_instructionReg),
._programCounter(_programCounter),
._R0(_R0),
._R1(_R1),
._R2(_R2),
._R3(_R3),
._Rhi(_Rhi),
._Rlo(_Rlo),
._Rquotient(_Rquotient),
._Rremainder(_Rremainder),
._ramWrite(_ramWrite),
._ramAddress(_ramAddress),
._romOut(_romOut),
._ramOut(_ramOut)
);
initial begin
_clk = 1'b0;
_reset = 1'b1;
end
always #5 _clk = ~_clk;
initial begin
_reset = #5 1'b0;
end
endmodule
| 6.632825 |
module tb_umi_data_aggregator #(
parameter TARGET = "DEFAULT", // pass through variable for hard macro
parameter TIMEOUT = 5000, // timeout value (cycles)
parameter PERIOD_CLK = 10 // clock period
) ();
// Local parameters
localparam STIMDEPTH = 1024;
localparam TCW = 8;
localparam CW = 32; // UMI width
localparam AW = 64; // UMI width
localparam DW = 512;
// Clock
reg clk;
always #(PERIOD_CLK / 2) clk = ~clk;
// SIM Ctrl signals
reg nreset;
reg [128*8-1:0] memhfile;
reg load;
reg go;
integer r;
// Reset initialization
initial begin
#(1) nreset = 1'b0;
clk = 1'b0;
load = 1'b0;
go = 1'b0;
#(PERIOD_CLK * 10) nreset = 1'b1;
#(PERIOD_CLK * 10) go = 1'b1;
end // initial begin
// control block
initial begin
r = $value$plusargs("MEMHFILE=%s", memhfile);
$readmemh(memhfile, umi_stimulus.ram);
$timeformat(-9, 0, " ns", 20);
$dumpfile("waveform.vcd");
$dumpvars();
#(TIMEOUT) $finish;
end
// DUT signals
wire umi_stim2dut_valid;
wire [CW-1:0] umi_stim2dut_cmd;
wire [AW-1:0] umi_stim2dut_dstaddr;
wire [AW-1:0] umi_stim2dut_srcaddr;
wire [DW-1:0] umi_stim2dut_data;
wire umi_stim2dut_ready;
wire umi_dut2check_valid;
wire [CW-1:0] umi_dut2check_cmd;
wire [AW-1:0] umi_dut2check_dstaddr;
wire [AW-1:0] umi_dut2check_srcaddr;
wire [DW-1:0] umi_dut2check_data;
reg umi_dut2check_ready;
always @(posedge clk) begin
if (~nreset) umi_dut2check_ready <= 1'b0;
else umi_dut2check_ready <= ~umi_dut2check_ready;
end
umi_data_aggregator #(
.CW(CW),
.AW(AW),
.DW(DW)
) dut (
.clk (clk),
.nreset(nreset),
.umi_in_valid (umi_stim2dut_valid),
.umi_in_cmd (umi_stim2dut_cmd),
.umi_in_dstaddr(umi_stim2dut_dstaddr),
.umi_in_srcaddr(umi_stim2dut_srcaddr),
.umi_in_data (umi_stim2dut_data),
.umi_in_ready (umi_stim2dut_ready),
.umi_out_valid (umi_dut2check_valid),
.umi_out_cmd (umi_dut2check_cmd),
.umi_out_dstaddr(umi_dut2check_dstaddr),
.umi_out_srcaddr(umi_dut2check_srcaddr),
.umi_out_data (umi_dut2check_data),
.umi_out_ready (umi_dut2check_ready)
);
umi_stimulus #(
.DEPTH (STIMDEPTH),
.TARGET(TARGET),
.CW (CW),
.AW (AW),
.DW (DW),
.TCW (TCW)
) umi_stimulus (
// Inputs
.nreset (nreset),
.load (load),
.go (go),
.ext_clk (clk),
.ext_valid (1'b0),
.ext_packet({(DW + AW + AW + CW + TCW) {1'b0}}),
.dut_clk (clk),
.dut_ready (umi_stim2dut_ready),
// Outputs
.stim_valid (umi_stim2dut_valid),
.stim_cmd (umi_stim2dut_cmd[CW-1:0]),
.stim_dstaddr(umi_stim2dut_dstaddr[AW-1:0]),
.stim_srcaddr(umi_stim2dut_srcaddr[AW-1:0]),
.stim_data (umi_stim2dut_data[DW-1:0]),
.stim_done (umi_stim2dut_done)
);
endmodule
| 6.502342 |
module tb_unsigned_divide_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_divide_multicycle.vcd");
$dumpvars(0, tb_unsigned_divide_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter DATA_WIDTH = 32;
reg cke = 1'b1;
reg [DATA_WIDTH-1:0] s_data0 = 7;
reg [DATA_WIDTH-1:0] s_data1 = 2;
reg s_valid = 1;
wire s_ready;
wire [DATA_WIDTH-1:0] m_quotient;
wire [DATA_WIDTH-1:0] m_remainder;
wire m_valid;
wire m_ready = 1'b1;
wire [DATA_WIDTH-1:0] exp_quotient;
wire [DATA_WIDTH-1:0] exp_remainder;
always @(posedge clk) begin
if (s_valid & s_ready) begin
s_data0 <= {$random()};
s_data1 <= {$random()} + 1;
end
if (m_valid & m_ready) begin
// $display("%d %d", exp_quotient, exp_remainder);
// $display("%d %d", m_quotient, m_remainder);
end
end
jelly_unsigned_divide_multicycle #(
.DATA_WIDTH(DATA_WIDTH)
) i_unsigned_divide_multicycle (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data0(s_data0),
.s_data1(s_data1),
.s_valid(s_valid),
.s_ready(s_ready),
.m_quotient (m_quotient),
.m_remainder(m_remainder),
.m_valid (m_valid),
.m_ready (m_ready)
);
jelly_cpu_divider #(
.DATA_WIDTH(DATA_WIDTH)
) i_cpu_divider (
.reset(reset),
.clk (clk),
.op_div (s_valid & s_ready),
.op_signed (1'b0),
.op_set_remainder(1'b0),
.op_set_quotient (1'b0),
.in_data0(s_data0),
.in_data1(s_data1),
.out_en (),
.out_quotient (exp_quotient),
.out_remainder(exp_remainder),
.busy()
);
wire quotient_ng = m_valid & (exp_quotient != m_quotient);
wire remainder_ng = m_valid & (exp_remainder != m_remainder);
endmodule
| 7.569862 |
module tb_unsigned_multiply_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_multiply_multicycle.vcd");
$dumpvars(0, tb_unsigned_multiply_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter DATA_WIDTH = 32;
wire cke = 1'b1;
reg [ DATA_WIDTH-1:0] s_data0 = 7;
reg [ DATA_WIDTH-1:0] s_data1 = 2;
reg s_valid = 1;
wire s_ready;
wire [2*DATA_WIDTH-1:0] m_data;
wire m_valid;
wire m_ready = 1'b1;
wire [2*DATA_WIDTH-1:0] exp_data = s_data0 * s_data1;
always @(posedge clk) begin
if (s_valid & s_ready) begin
s_data0 <= {$random()};
s_data1 <= {$random()} + 1;
end
if (m_valid & m_ready) begin
// $display("%d", m_data);
end
end
jelly_unsigned_multiply_multicycle #(
.DATA_WIDTH0(DATA_WIDTH),
.DATA_WIDTH1(DATA_WIDTH)
) i_unsigned_multiply_multicycle (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data0(s_data0),
.s_data1(s_data1),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
endmodule
| 6.56698 |
module tb_unsigned_sqrt_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_sqrt_multicycle.vcd");
$dumpvars(0, tb_unsigned_sqrt_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter DATA_WIDTH = 32;
wire cke = 1'b1;
reg [2*DATA_WIDTH-1:0] s_data = 0;
reg s_valid = 1;
wire s_ready;
wire [ DATA_WIDTH-1:0] m_data;
wire m_valid;
wire m_ready = 1'b1;
integer n = 0;
always @(posedge clk) begin
if (s_valid & s_ready) begin
s_data <= n * n;
n <= n + 1;
end
if (m_valid & m_ready) begin
$display("%d", m_data);
end
end
// }`TCN
jelly_unsigned_sqrt_multicycle #(
.DATA_WIDTH(DATA_WIDTH)
) i_unsigned_sqrt_multicycle (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
endmodule
| 7.192979 |
module tb_upcntr;
// Inputs
reg clk, reset;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
upcntr uut (
.clk (clk),
.reset(reset),
.cnt (cnt)
);
initial begin
$dumpfile("tb_upcntr.vcd");
$dumpvars(0, tb_upcntr);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #123 reset = 0;
endmodule
| 7.679218 |
module tb_updown ();
reg [3:0] IN;
reg Up, Down, Load;
reg CLK = 0;
wire [3:0] OUT;
updown DUT (
OUT,
Up,
Down,
Load,
IN,
CLK
);
always #10 CLK = ~CLK;
initial begin
IN = 4'b1111;
Load = 1'b1;
Up = 1'b0;
Down = 1'b0;
#15 Load = 1'b0;
Up = 1'b1;
Down = 1'b0;
#100 Load = 1'b0;
Up = 1'b0;
Down = 1'b1;
end
endmodule
| 6.734584 |
module tb_up_dn_cntr;
// Inputs
reg clk, reset, up_dnb;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr uut (
.clk(clk),
.reset(reset),
.up_dnb(up_dnb),
.cnt(cnt)
);
initial begin
$dumpfile("tb_up_dn_cntr.vcd");
$dumpvars(0, tb_up_dn_cntr);
// Initialize Inputs
clk = 0;
reset = 1;
up_dnb = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #501 up_dnb = ~up_dnb;
always #123 reset = 0;
endmodule
| 7.483354 |
module tb_up_dn_cntr_with_load;
// Inputs
reg clk, reset, load_en, up_dnb;
reg [3:0] load_data;
reg load_en_1, load_en_2;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr_with_load uut (
.clk(clk),
.reset(reset),
.load_en(load_en),
.load_data(load_data),
.up_dnb(up_dnb),
.cnt(cnt)
);
initial begin
$dumpfile("tb_up_dn_cntr_with_load.vcd");
$dumpvars(0, tb_up_dn_cntr_with_load);
// Initialize Inputs
clk = 0;
reset = 1;
up_dnb = 1;
load_en_1 = 0;
load_en_2 = 0;
load_data = 4'b0000;
#3000 $finish;
end
always #5 clk = ~clk;
always #123 reset = 0;
always #130 load_data = load_data + 1;
always #540 load_en_1 = ~load_en_1;
always #1340 up_dnb = ~up_dnb;
always #1 load_en = load_en_1 ^ load_en_2;
always @(posedge clk, posedge reset) begin
if (reset) load_en_2 = 1'b0;
else load_en_2 = load_en_1;
end
endmodule
| 7.483354 |
module tb_up_dn_cntr_with_load_with_start_stop;
// Inputs
reg clk, reset, load_en, up_dnb, start_stop_b;
reg [3:0] load_data;
reg load_en_1, load_en_2;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr_with_load_with_start_stop uut (
.clk(clk),
.reset(reset),
.load_en(load_en),
.load_data(load_data),
.up_dnb(up_dnb),
.start_stop_b(start_stop_b),
.cnt(cnt)
);
initial begin
$dumpfile("tb_up_dn_cntr_with_load_with_start_stop.vcd");
$dumpvars(0, tb_up_dn_cntr_with_load_with_start_stop);
// Initialize Inputs
clk = 0;
reset = 1;
up_dnb = 1;
load_en_1 = 0;
load_en_2 = 0;
load_data = 4'b0000;
start_stop_b = 1'b0;
#7000 $finish;
end
always #5 clk = ~clk;
always #123 reset = 0;
always #130 load_data = load_data + 1;
always #540 load_en_1 = ~load_en_1;
always #1340 up_dnb = ~up_dnb;
always #880 start_stop_b = ~start_stop_b;
always #1 load_en = load_en_1 ^ load_en_2;
always @(posedge clk, posedge reset) begin
if (reset) load_en_2 = 1'b0;
else load_en_2 = load_en_1;
end
endmodule
| 7.483354 |
module XORSHIFT #(
parameter WIDTH = 32,
parameter SEED = 1
) (
input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL
);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x ^ (x << 11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w ^ (w >> 19)) ^ (t ^ (t >> 8));
end
end
end
endmodule
| 6.534691 |
module tb_util ();
task assert_equals;
input [31:0] expected;
input [31:0] actual;
begin
if (actual === expected) $display("OK!");
else begin
$display("ERRO! @ %t , Esperado: %d, Obteve %d", $time, expected, actual);
$stop;
end
end
endtask
// Gera numeros aleatorios de 32 bit entre 0 e max
task rand_zero_max;
input [31:0] max;
output [31:0] result;
begin
result = $unsigned($random) % max;
end
endtask
endmodule
| 7.867543 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // asynchronous
reg [31:0] s_data_fill; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // valid asynchronous && ready asynchronous
wire valid_var;
master m0 (
.clk(clk_tb),
.reset(reset_tb),
.trans_data(data_tb),
.ready(ready),
.data(data),
.valid(valid),
.valid_var(valid_var)
);
slave s0 (
.clk(clk_tb),
.reset(reset_tb),
.data(data),
.valid(valid),
.ready(ready),
.valid_var(valid_var),
.s_data_fill(s_data_fill)
);
// clock generation
initial begin
clk_tb = 0;
forever begin
#halfperiod clk_tb = ~clk_tb;
end
end
// reset generation
initial begin
reset_tb = 1;
#reset_delay reset_tb = 0;
end
// transmit data generation
initial begin
data_tb = 32'b0;
#193; // set valid&&trans_data asynchronous
data_tb = 32'h20220503;
#10;
data_tb = 32'b0;
#200;
data_tb = 32'h10000006;
end
initial begin
s_data_fill = 32'h10000006;
#192; // set s_data&&ready asynchronous
s_data_fill = 32'b0;
end
endmodule
| 7.015571 |
module at each clock negative edge assuming the DFF is posedge triggered
*/
// TB clock generator
module CLK_GEN #(
parameter CLK_PERIOD = 10
)
(
output reg clk
);
initial begin
clk<=0;
forever #(CLK_PERIOD/2) clk<=~clk;
end
endmodule
| 6.819689 |
module TB;
// TB settings and local args
localparam CLK_PERIOD = 10;
integer idx = 0;
// signals driven by us
reg reset; // sequence detector reset signal
reg seq; // sequence detector 1-bit seq. input
// signals driven by duts and bus drivers/generators
wire out, clk;
// student ID
reg [0:11] tprtn = 12'b0;
seq_23735 dut (
out,
seq,
clk,
reset
);
CLK_GEN #(.CLK_PERIOD(CLK_PERIOD)) clk_generator (.clk(clk));
task bus_driver;
input [0:11] pattern;
input is_correct;
input rst_init;
begin
#(CLK_PERIOD * 2) reset <= rst_init;
#(CLK_PERIOD * 2) reset <= 0;
for (idx = 0; idx < 12; idx = idx + 1) begin
@(negedge clk) seq <= pattern[idx]; //giving the input
@(posedge clk) begin
if (idx <= 11 && out === 1) begin //testing for out=1 before the 12th cycle
$display("FAIL: expected output==0 before 12 cycles");
end
end
end
@(negedge clk) begin
if ((is_correct === 1'b1 & out === 1'b1) || (is_correct === 1'b0 & out === 1'b0))
$display("PASS"); //testing for right out after 12 cycles
else if (is_correct === 1'b1 & out !== 1'b1)
$display("FAIL: expected out==1 @correct sequence");
else if (is_correct === 1'b0 & out !== 1'b0)
$display("FAIL: expected out==0 @wrong sequence");
end
end
endtask
initial begin
//$dumpfile("dump.vcd"); $dumpvars;
//$display("Testing: %d", `SEQ_BCD_NUM);
bus_driver(`SEQ_BCD_NUM << 1, 0, 1);
bus_driver(`SEQ_BCD_NUM, 1, 0);
bus_driver(`SEQ_BCD_NUM >> 1, 0, 0);
$finish;
end
endmodule
| 7.89986 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // synchronous
wire valid_var; // asynchronous
master m0 (
.clk(clk_tb),
.reset(reset_tb),
.trans_data(data_tb),
.ready(ready),
.data(data),
.valid(valid),
.valid_var(valid_var)
);
slave s0 (
.clk(clk_tb),
.reset(reset_tb),
.data(data),
.valid(valid),
.ready(ready),
.valid_var(valid_var)
);
// clock generation
initial begin
clk_tb = 0;
forever begin
#halfperiod clk_tb = ~clk_tb;
end
end
// reset generation
initial begin
reset_tb = 1;
#reset_delay reset_tb = 0;
end
// transmit data generation
initial begin
data_tb = 32'b0;
#192; // set asynchronous
data_tb = 32'h20220503;
#10;
data_tb = 32'b0;
#200;
data_tb = 32'h10000006;
end
endmodule
| 7.015571 |
module tb_vct ();
parameter H_Active = 1920;
parameter H_FrontPorch = 88;
parameter H_SyncWidth = 44;
parameter H_BackPorch = 148;
parameter V_Active = 1080;
parameter V_FrontPorch = 4;
parameter V_SyncWidth = 5;
parameter V_BackPorch = 36;
reg vtc_rst_n;
reg vtc_pix_clk;
wire vtc_vs_o;
wire vtc_hs_o;
wire vtc_de_o;
initial begin
vtc_pix_clk = 0;
forever #(3) vtc_pix_clk = ~vtc_pix_clk;
end
initial begin
vtc_rst_n = 0;
repeat (1000) @(posedge vtc_pix_clk);
vtc_rst_n = 1;
end
vct #(
.H_Active(H_Active),
.H_FrontPorch(H_FrontPorch),
.H_SyncWidth(H_SyncWidth),
.H_BackPorch(H_BackPorch),
.V_Active(V_Active),
.V_FrontPorch(V_FrontPorch),
.V_SyncWidth(V_SyncWidth),
.V_BackPorch(V_BackPorch)
) inst_vct (
.vtc_rst_n (vtc_rst_n),
.vtc_pix_clk(vtc_pix_clk),
.vtc_vs_o (vtc_vs_o),
.vtc_hs_o (vtc_hs_o),
.vtc_de_o (vtc_de_o)
);
endmodule
| 6.96521 |
module: vector_mac
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_vector_mac;
parameter VECTOR_LEN = 5, // number of elements in the vectors
A_CELL_WIDTH = 8, // width of elements in the vector a
B_CELL_WIDTH = 8, // width of elements in the vector b
RESULT_CELL_WIDTH = 10, // width of elements in the output vector
TILING = 5; // number of mults generated for dot product
// Inputs
reg clk;
reg rst;
reg [VECTOR_LEN*A_CELL_WIDTH-1:0] a;
reg a_valid;
wire a_ready;
reg [VECTOR_LEN*B_CELL_WIDTH-1:0] b;
reg b_valid;
wire b_ready;
// Outputs
wire [RESULT_CELL_WIDTH-1:0] result;
wire result_valid;
reg result_ready;
wire error;
// Instantiate the Unit Under Test (UUT)
vector_mac #(
.VECTOR_LEN (VECTOR_LEN ),
.A_CELL_WIDTH (A_CELL_WIDTH ),
.B_CELL_WIDTH (B_CELL_WIDTH ),
.RESULT_CELL_WIDTH(RESULT_CELL_WIDTH),
.TILING (TILING )
) uut (
.clk(clk),
.rst(rst),
.a(a),
.a_valid(a_valid),
.a_ready(a_ready),
.b(b),
.b_valid(b_valid),
.b_ready(b_ready),
.result(result),
.result_valid(result_valid),
.result_ready(result_ready),
.error(error)
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
a <= 0;
a_valid <= 0;
b <= 0;
b_valid <= 0;
result_ready <= 0;
#10 rst <= 0;
#20
a <= {8'd10, -8'd20, 8'd1, 8'd100, 8'd0};
a_valid <= 1;
#10
b <= {8'd5, 8'd4, 8'd3, 8'd2, 8'd1};
b_valid <= 1;
#20 result_ready <= 1;
#10
a_valid <= 0;
b_valid <= 0;
a <= {8'd10, -8'd200, 8'd100, 8'd100, 8'd0};
b <= {8'd50, 8'd4, 8'd30, 8'd2, 8'd1};
#20 a_valid <= 1;
b_valid <= 1;
#20 $stop;
end
endmodule
| 6.80325 |
module tb_vedic3bit;
reg [2:0]A,B; //ports declared
wire [5:0]mul;
vedic3bit M(A,B,mul);// module instantiation
initial //various test inputs
begin
A=3'b001;
B=3'b010;
#1 A=3'b010;
B=3'b100;
#1A=3'b100;
B=3'b101;
#1 A=3'b101;
B=3'b110;
#1A=3'b110;
B=3'b111;
end
endmodule
| 7.285089 |
module tb_VGATest ();
reg clk;
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
wire hsync;
wire vsync;
wire blankN;
wire vgaClk;
wrapper_VGATest uut (
.clk(clk),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.blankN(blankN),
.vgaClk(vgaClk)
);
initial begin
clk = 0;
#1;
end
always #1 clk = ~clk;
endmodule
| 6.826965 |
module tb_vga_char ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire vsync;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk：产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- vga_char_inst -------------
vga_char vga_char_inst (
.sys_clk (sys_clk), //输入晶振时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.hsync(hsync), //输出行同步信号,1bit
.vsync(vsync), //输出场同步信号,1bit
.rgb (rgb) //输出RGB图像信息,16bit
);
endmodule
| 8.141251 |
module tb_vga_colorbar ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire vsync;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk：产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- vga_colorbar_inst -------------
vga_colorbar vga_colorbar_inst (
.sys_clk (sys_clk), //输入晶振时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.hsync(hsync), //输出行同步信号,1bit
.vsync(vsync), //输出场同步信号,1bit
.rgb (rgb) //输出RGB图像信息,16bit
);
endmodule
| 8.73909 |
module tb_vga_ctrl ();
reg clk;
reg rst_n;
reg [15:0] in_rgb;
vga_ctrl component (
.clk(clk),
.rst_n(rst_n),
.in_rgb(in_rgb)
);
initial begin
clk = 1'b1;
rst_n = 1'b0;
in_rgb = 15'b0;
#10 rst_n = 1'b1;
#5000000 $finish;
end
always #1 clk = ~clk;
always #16 in_rgb = in_rgb + 1'b1;
initial begin
$dumpfile("tb_vga_ctrl.vcd");
$dumpvars(0, component);
end
endmodule
| 6.69603 |
module tb_vga_main ();
reg clk;
wire hsync, vsync;
wire [3:0] red;
wire [3:0] blue;
wire [3:0] green;
vga_main vga0 (
.clk(clk),
.io ({red, green, blue, vsync, hsync})
);
// 50 Mhz clock (20 ns period, so 10 ns between state changes)
// NOTE: adjust as required based on your dev board's own clock
always #10 clk = ~clk;
initial begin
clk <= 0;
end
endmodule
| 7.12936 |
module tb_vga_rom_pic ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire vsync;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk:产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- vga_rom_pic_inst -------------
vga_rom_pic vga_rom_pic_inst (
.sys_clk (sys_clk), //输入晶振时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.hsync(hsync), //输出行同步信号,1bit
.vsync(vsync), //输出场同步信号,1bit
.rgb (rgb) //输出RGB图像信息,16bit
);
endmodule
| 8.690512 |
module tb_vga_rom_pic_jump ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire vsync;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk:产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- vga_rom_pic_jump_inst -------------
vga_rom_pic_jump vga_rom_pic_jump_inst (
.sys_clk (sys_clk), //输入晶振时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.hsync(hsync), //输出行同步信号,1bit
.vsync(vsync), //输出场同步信号,1bit
.rgb (rgb) //输出RGB图像信息,16bit
);
endmodule
| 8.690512 |
module tb_vga_uart_pic ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire vsync;
wire [7:0] rgb;
//reg define
reg sys_clk;
reg sys_rst_n;
reg rx;
reg [7:0] data_mem [9999:0]; //data_mem是一个存储器，相当于一个ram
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial
$readmemh(
"F:/GitLib/Altera/EP4CE10F17C8/ZT_Pro/A/4_base_code/30_vga_uart_pic/matlab/data_test.txt",
data_mem
);
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//rx
initial begin
rx <= 1'b1;
#200 rx_byte();
end
//rx_byte
task rx_byte();
integer j;
for (j = 0; j < 10000; j = j + 1) rx_bit(data_mem[j]);
endtask
//rx_bit
task rx_bit(input [7:0] data); //data是data_mem[j]的值。
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0; //起始位
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7]; //上面8个发送的是数据位
9: rx <= 1'b1; //停止位
endcase
#1040; //一个波特时间=sys_clk周期*波特计数器
end
endtask
//重定义defparam,用于修改参数,缩短仿真时间
defparam vga_uart_pic_inst.uart_rx_inst.BAUD_CNT_END = 52;
defparam vga_uart_pic_inst.uart_rx_inst.BAUD_CNT_END_HALF = 26;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- vga_uart_pic_jump -------------
vga_uart_pic vga_uart_pic_inst (
.sys_clk (sys_clk), //输入工作时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.rx (rx), //输入串口的图片数据,1bit
.hsync(hsync), //输出行同步信号,1bit
.vsync(vsync), //输出场同步信号,1bit
.rgb (rgb) //输出像素信息,8bit
);
endmodule
| 7.201704 |
module tb_video_gate ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_video_gate.vcd");
$dumpvars(0, tb_video_gate);
#10000000 $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter TUSER_WIDTH = 1;
parameter TDATA_WIDTH = 4;
wire aresetn = ~reset;
wire aclk = clk;
wire aclken = 1'b1;
reg enable;
wire busy;
reg param_skip;
wire [TUSER_WIDTH-1:0] s_axi4s_tuser;
wire s_axi4s_tlast;
reg [TDATA_WIDTH-1:0] s_axi4s_tdata;
reg s_axi4s_tvalid;
wire s_axi4s_tready;
wire [TUSER_WIDTH-1:0] m_axi4s_tuser;
wire m_axi4s_tlast;
wire [TDATA_WIDTH-1:0] m_axi4s_tdata;
wire m_axi4s_tvalid;
reg m_axi4s_tready = 1'b1;
jelly_video_gate_core #(
.TUSER_WIDTH(TUSER_WIDTH),
.TDATA_WIDTH(TDATA_WIDTH)
) i_video_gate_core (
.aresetn(aresetn),
.aclk (aclk),
.aclken (aclken),
.enable(enable),
.busy (busy),
.param_skip(param_skip),
.s_axi4s_tuser (s_axi4s_tuser),
.s_axi4s_tlast (s_axi4s_tlast),
.s_axi4s_tdata (s_axi4s_tdata),
.s_axi4s_tvalid(s_axi4s_tvalid),
.s_axi4s_tready(s_axi4s_tready),
.m_axi4s_tuser (m_axi4s_tuser),
.m_axi4s_tlast (m_axi4s_tlast),
.m_axi4s_tdata (m_axi4s_tdata),
.m_axi4s_tvalid(m_axi4s_tvalid),
.m_axi4s_tready(m_axi4s_tready)
);
always @(posedge clk) begin
if (reset) begin
enable <= 0;
param_skip <= 0;
m_axi4s_tready <= 1;
end else if (aclken) begin
enable <= {$random()};
param_skip <= {$random()};
m_axi4s_tready <= {$random()};
end
end
always @(posedge clk) begin
if (reset) begin
s_axi4s_tdata <= 5;
s_axi4s_tvalid <= 0;
end else if (aclken) begin
if (s_axi4s_tvalid && s_axi4s_tready) begin
s_axi4s_tdata <= s_axi4s_tdata + 1;
end
s_axi4s_tvalid <= {$random()};
end
end
assign s_axi4s_tuser = (s_axi4s_tdata == 0);
assign s_axi4s_tlast = (s_axi4s_tdata[1:0] == 2'b11);
integer fp;
initial fp = $fopen("out.txt", "w");
always @(posedge clk) begin
if (!reset && aclken && m_axi4s_tvalid && m_axi4s_tready) begin
$fdisplay(fp, "%b %b %h", m_axi4s_tuser, m_axi4s_tlast, m_axi4s_tdata);
end
end
endmodule
| 7.511809 |
module tb_vmicro16_core;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
vmicro16_core uut (
.clk (clk),
.reset(reset)
);
always #10 clk = ~clk;
// Nanosecond time format
initial $timeformat(-9, 0, " ns", 10);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
#30;
reset = 1;
@(posedge clk);
reset = 0;
end
endmodule
| 7.204079 |
module tb_vmicro16_soc;
// Inputs
reg clk;
reg reset;
// Create clock signal
always #10 clk = ~clk;
// Instantiate the Unit Under Test (UUT)
vmicro16_soc uut (
.clk (clk),
.reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
// Assert reset for n clocks minumum
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset = 0;
end
endmodule
| 7.365637 |
module tb_vmicro16_soc_prog;
// Inputs
reg clk;
reg reset;
reg uart_rx;
// Create clock signal
always #10 clk = ~clk;
///////////////////////////////////////////////
// task from https://www.edaplayground.com/x/4Lyz
//////////////////////////////////////////////
// Testbench uses a 25 MHz clock (same as Go Board)
// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.
parameter c_BIT_PERIOD = 8600;
parameter c_WAIT = 85_000;
reg r_RX_Serial = 1;
wire [7:0] w_RX_Byte;
// Takes in input byte and serializes it
task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
// Send Start Bit
r_RX_Serial <= 1'b0;
#(c_BIT_PERIOD);
#1000;
// Send Data Byte
for (ii = 0; ii < 8; ii = ii + 1) begin
r_RX_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
// Send Stop Bit
r_RX_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask // UART_WRITE_BYTE
// Instantiate the Unit Under Test (UUT)
vmicro16_soc uut (
.clk (clk),
.reset (reset),
.uart_rx(r_RX_Serial)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
uart_rx = 0;
// Assert reset for n clocks minumum
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset = 0;
@(posedge clk);
#(c_WAIT);
@(posedge clk);
UART_WRITE_BYTE(8'h80);
@(posedge clk);
UART_WRITE_BYTE(8'h28);
@(posedge clk);
UART_WRITE_BYTE(8'h00);
@(posedge clk);
UART_WRITE_BYTE(8'h08);
@(posedge clk);
UART_WRITE_BYTE(8'hff);
@(posedge clk);
UART_WRITE_BYTE(8'hff);
#(c_WAIT);
@(posedge clk);
UART_WRITE_BYTE(8'h80);
@(posedge clk);
UART_WRITE_BYTE(8'h28);
@(posedge clk);
UART_WRITE_BYTE(8'h00);
@(posedge clk);
UART_WRITE_BYTE(8'h08);
@(posedge clk);
UART_WRITE_BYTE(8'hff);
@(posedge clk);
UART_WRITE_BYTE(8'hff);
end
endmodule
| 7.365637 |
module tb_vmicro16_soc;
// Inputs
reg clk;
reg reset;
wire halt;
wire [`APB_GPIO1_PINS-1:0] gpio1;
// Create clock signal
always #10 clk = ~clk;
// Instantiate the Unit Under Test (UUT)
vmicro16_soc uut (
.clk (clk),
.halt (halt),
.gpio1(gpio1),
.reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
// Assert reset for n clocks minumum
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset = 0;
// Verify correct summation result
@(halt);
`rassert(gpio1 == 16'h7008);
$display("");
$display("SUCCESS!");
end
endmodule
| 7.365637 |
module tb_voting_machine ();
reg t_clk;
reg t_rst;
reg t_candidate_1;
reg t_candidate_2;
reg t_candidate_3;
reg t_vote_over;
wire [5:0] t_result_1;
wire [5:0] t_result_2;
wire [5:0] t_result_3;
//instansiate component unit under test
voting_machine uut (
.clk(t_clk),
.rst(t_rst),
.i_candidate_1(t_candidate_1),
.i_candidate_2(t_candidate_2),
.i_candidate_3(t_candidate_3),
.i_voting_over(t_vote_over),
.o_count1(t_result_1),
.o_count2(t_result_2),
.o_count3(t_result_3)
);
//initial value of clock at 0 time
initial t_clk = 1'b1;
// clock generation
always begin
#5 t_clk = ~t_clk;
end
//stimulus to design
initial begin
$monitor(
"time = %d, rst = %b, candidate_1 = %b, candidate_2 = %b, candidate_3 = %b, vote_over = %b, result_1 = %3d, result_2 = %3d, result_3 = %3d,\n",
$time, t_rst, t_candidate_1, t_candidate_2, t_candidate_3, t_vote_over, t_result_1,
t_result_2, t_result_3,);
t_rst = 1'b1;
t_candidate_1 = 1'b0;
t_candidate_2 = 1'b0;
t_candidate_3 = 1'b0;
t_vote_over = 1'b0;
#20 t_rst = 1'b0;
#10 t_candidate_1 = 1'b1; //when button for candidate 1 is pressed
#10 t_candidate_1 = 1'b0; //button for candidate 1 is released
#20 t_candidate_2 = 1'b1; //when button for candidate 2 is pressed
#10 t_candidate_2 = 1'b0; //button for candidate 2 is released
#20 t_candidate_1 = 1'b1; //when button for candidate 1 is pressed
#10 t_candidate_1 = 1'b0; //button for candidate 1 is released
#20 t_candidate_3 = 1'b1; //when button for candidate 3 is pressed
#10 t_candidate_3 = 1'b0; //button for candidate 3 is released
#20 t_candidate_2 = 1'b1;
#10 t_candidate_2 = 1'b0;
#20 t_candidate_2 = 1'b1;
#10 t_candidate_2 = 1'b0;
#20 t_candidate_1 = 1'b1;
#10 t_candidate_1 = 1'b0;
#20 t_candidate_3 = 1'b1; //when button for candidate 3 is pressed
#10 t_candidate_3 = 1'b0; //button for candidate 3 is released
#30 t_vote_over = 1'b1;
#50 t_rst = 1'b1; //reset when the voting process is over
//use $finish for simulators other than modelsim
#60 $stop; // use $stop instead of $finish to keep modelsim simulator open
end
//.vcd file for gtk wave plot
initial begin
$dumpfile("voting_dumpfile.vcd");
$dumpvars(0, tb_voting_machine);
end
endmodule
| 7.006023 |
module simulates the generation of the video timing signals. It
// generates the hsync and vsync and blank timing signals.
//
module timing_gen #(
parameter DLY = 1,
parameter INTERLACE = 0
)
(
input wire clk,
input wire rst,
input wire ce,
input wire [13:0] active_lines,
input wire [13:0] total_lines,
input wire [13:0] vsync_start,
input wire [13:0] vsync_end,
input wire [13:0] active_pixels,
input wire [13:0] total_pixels,
input wire [13:0] hsync_start,
input wire [13:0] hsync_end,
output wire hsync,
output wire vsync,
output wire hblank,
output wire vblank,
output wire de,
output reg field_id,
output wire [23:0] video_data
);
// variable declarations
reg [13:0] pixel_count;
reg [13:0] line_count;
integer frame_count;
//
// pixel counter
//
// Cleared to 0 on reset. Rolls over when it reaches total_pixels-1. Otherwise
// increments every clock cycle.
//
always @ (posedge clk)
if (ce)
begin
if (rst)
# DLY pixel_count <= 0;
else
begin
if (pixel_count == total_pixels-1)
# DLY pixel_count <= 0;
else
# DLY pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset. Increments coincident with pixel 0.
//
always @ (posedge clk)
if (ce)
begin
if (rst) begin
line_count <= # DLY 0;
frame_count <= # DLY 0;
field_id <= # DLY 0;
end
else if (frame_count >= 7)
begin
$display ("Frame counter timed out. Test error.");
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
end
else if (pixel_count == total_pixels - 1)
if (line_count == total_lines - 1) begin
line_count <= 0;
frame_count <= frame_count +1;
if (INTERLACE)
field_id <= ~field_id;
else
field_id <= 0;
end
else
line_count <= # DLY line_count + 1;
end
//
// Generate the hasync, vsync and data enable timing signals at the appropriate place on each line
// by examining the pixel counter.
//
assign hsync = pixel_count >= hsync_start && pixel_count <= hsync_end;
assign vsync = line_count >= vsync_start && line_count <= vsync_end;
assign hblank = !(pixel_count <= (active_pixels-1));
assign vblank = !(line_count <= (active_lines -1));
assign de = line_count <= (active_lines -1) && pixel_count <= (active_pixels - 1);
// Generate the video outputs. The video is generated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign video_data = {line_count[1:0] , pixel_count[5:0]};
endmodule
| 6.687085 |
module simulates the AXI-4 streaming interface to the video bridge
// it generates handshaking, and regenerates the x,y pixel location based on eol and
// sof. From the pixel location, it creates an expected data value and compares
// this to the incoming video data.
//
module axis_emulation #(
parameter DLY = 1
)
(
input wire aclk,
input wire rst,
output wire axis_tready,
input wire axis_tvalid,
input wire [23:0] axis_tdata_video,
input wire axis_tlast,
input wire axis_tuser_sof,
input wire fid,
input wire [13:0] total_lines,
output reg error_out,
output reg frame_complete
);
// variable declarations
reg [13:0] pixel_count;
reg[13:0] line_count;
reg [23:0] tdata_video_1;
wire [23:0] expected_video_data;
reg eol_1 = 0;
wire sof ;
reg count_valid = 0;
reg [10:0] cycle_counter;
wire data_valid;
wire compare_is_valid;
assign axis_tready = (cycle_counter[3:1] != 0); //Disable ready occasionally
assign sof = axis_tuser_sof;
assign data_valid = axis_tvalid && axis_tready;
// Delay data and eol to match with pixel and line numbers
always @ (posedge aclk) begin
if (data_valid) begin
tdata_video_1 <= axis_tdata_video;
eol_1 <= axis_tlast;
end
end
//
// cycle counter
always @ (posedge aclk) begin
if (rst)
cycle_counter <= 0;
else
cycle_counter <= cycle_counter + 1;
end
// pixel counter
//
// Cleared to 0 on reset and eol. Rolls over when it reaches total_pixels-1. Otherwise
// increments every clock cycle.
//
always @ (posedge aclk) begin
if (rst || eol_1 || sof)
pixel_count <= 0;
else if (data_valid)
pixel_count <= pixel_count + 1;
end
//
// Line counter
//
// Set to line 0 on reset or sof. Increments coincident with pixel 0.
//
always @ (posedge aclk) begin
if (rst )begin
line_count <= 0;
count_valid <= 0;
frame_complete <= 0;
end
if (data_valid) begin
if (sof ) begin // count is valid after 1st sof
line_count <= 0;
count_valid <= 1;
// if count_valid is already asserted and fid=0, the frame is complete
if (count_valid && !fid)
frame_complete <= 1;
end
else if (&line_count)
begin
$display ("Line counter reached maximum value. Test error.");
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
// $finish;
end
else if (eol_1)
line_count <= line_count + 1;
end
end
// Generate the video outputs. The video is gengerated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign expected_video_data = {line_count[1:0], pixel_count[5:0]};
assign compare_is_valid = data_valid && count_valid & !frame_complete;
always @ (posedge aclk) begin
error_out <= 0;
if (compare_is_valid) begin
# DLY if (tdata_video_1 != expected_video_data) begin
$display ("Data Mismatch. Expected: %h, received: %h. Test error.",
expected_video_data, tdata_video_1);
error_out <= 1;
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
// $finish;
end
end
end
endmodule
| 6.687085 |
module tb ();
reg [31:0] A;
reg [31:0] B;
wire [63:0] out;
initial begin
A = 32'hffffffff;
B = 32'hffffffff;
#10 A = 32'd4;
B = 32'd9;
#10 A = 32'h666;
B = 32'h44321;
#10 A = 32'h90012345;
B = 32'h54321;
#10 A = 32'h88888888;
B = 32'h55735;
#10 A = 32'hff431234;
B = 32'hfff44444;
#10 A = 32'h2333;
B = 32'hfff44444;
end
mul32 mul (
.A(A),
.B(B),
.product(out)
);
endmodule
| 7.195167 |
module tb_warmup2_mpadder();
// Define internal regs and wires
reg clk;
reg reset;
reg instart;
reg [127:0] inA;
reg [127:0] inB;
wire [128:0] outC;
wire outdone;
warmup2_mpadder dut(
clk,
reset,
instart,
inA,
inB,
outC,
outdone);
// Generate Clock
initial begin
clk = 0;
forever #`CLK_HALF clk = ~clk;
end
initial begin
reset <= 1'b1;
inA <= 128'h0;
inB <= 128'h0;
#`RESET_TIME
reset <= 1'b0;
#`CLK_PERIOD;
inA <= 128'hcbc87cf0da4497687834fad762e4fa0d;
inB <= 128'h88f32f2f5b948a6ccf335529fa86ee6c;
instart <= 1'b1;
#`CLK_PERIOD;
instart <= 1'b0;
end
endmodule
| 7.099165 |
module tb_warpv ();
reg clock;
reg rst;
wire led;
cpu warpv (
.clk (clock),
.reset(rst),
.led (led)
);
initial begin
$dumpfile("./../Simulation/out.vcd");
$dumpvars(0, tb_warpv);
rst = 1;
clock = 0;
#200 rst = 0;
end
// generate clock
always #(5) clock = ~clock;
initial begin
#20000 $finish; // 18 ms (one frame is 16.7 ms)]
end
endmodule
| 7.226376 |
module tb_water_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [3:0] led_out;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------------- water_led_inst --------------------
water_led #(
.CNT_MAX(25'd24)
) water_led_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.led_out(led_out) //output [3:0] led_out
);
endmodule
| 7.609034 |
module tb_waveform_from_pipe_bram ();
reg reset;
reg pipe_clk;
reg pipe_in_write;
reg [15:0] pipe_in_data;
reg pop_clk;
wire [31:0] wave;
wire [10:0] pipe_addr;
wire [10:1] pop_addr;
initial begin
reset = 0;
pipe_clk = 0;
pipe_in_write = 0;
pipe_in_data = 16'd0;
pop_clk = 0;
#2 reset = 1;
#4 reset = 0;
#4 pipe_in_write = 1;
pipe_in_data = 16'd0;
#2 pipe_in_data = 16'd1;
#2 pipe_in_data = 16'd0;
#2 pipe_in_data = 16'd2;
#2 pipe_in_data = 16'd0;
#2 pipe_in_data = 16'd3;
#1 pipe_in_write = 0;
#1 reset = 1;
#2 reset = 0;
end
always #1 pipe_clk = ~pipe_clk;
always #1 pop_clk = ~pop_clk;
waveform_from_pipe_bram generator (
.reset(reset),
.pipe_clk(pipe_clk),
.pipe_in_write(pipe_in_write),
.pipe_in_data(pipe_in_data),
.pop_clk(pop_clk),
.wave(wave),
.pipe_addr(pipe_addr),
.pop_addr (pop_addr)
);
endmodule
| 6.512514 |
module: weight_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_controller;
parameter NEURON_NUM = 4, // number of cells in the vectors a and delta
NEURON_OUTPUT_WIDTH = 10, // size of the output of the neuron (z signal)
ACTIVATION_WIDTH = 9, // size of the neurons activation
DELTA_CELL_WIDTH = 10, // width of each delta cell
WEIGHT_CELL_WIDTH = 16, // width of individual weights
LEARNING_RATE_SHIFT = 0,
LAYER_ADDR_WIDTH = 2,
FRACTION_WIDTH = 8,
WEIGHT_INIT_FILE = "weights4x4.list";
// Inputs
reg clk;
reg rst;
// layer
reg [LAYER_ADDR_WIDTH-1:0] layer;
reg layer_valid;
wire layer_ready;
// z
reg [NEURON_NUM*NEURON_OUTPUT_WIDTH-1:0] z;
reg z_valid;
wire z_ready;
// delta
reg [NEURON_NUM*DELTA_CELL_WIDTH-1:0] delta;
reg delta_valid;
wire delta_ready;
// Outputs
wire [NEURON_NUM*NEURON_NUM*WEIGHT_CELL_WIDTH-1:0] w;
wire w_valid;
reg w_ready;
// overflow
wire error;
// memories
wire [WEIGHT_CELL_WIDTH-1:0] weights_mem [0:NEURON_NUM*NEURON_NUM-1];
wire [NEURON_OUTPUT_WIDTH-1:0] z_mem [0:NEURON_NUM-1];
wire [DELTA_CELL_WIDTH-1:0] delta_mem [0:NEURON_NUM-1];
genvar i;
generate
for (i=0; i<NEURON_NUM*NEURON_NUM; i=i+1) begin: MEM
assign weights_mem[i] = w[i*WEIGHT_CELL_WIDTH+:WEIGHT_CELL_WIDTH];
end
for (i=0; i<NEURON_NUM; i=i+1) begin: MEM2
assign z_mem[i] = z[i*NEURON_OUTPUT_WIDTH+:NEURON_OUTPUT_WIDTH];
assign delta_mem[i] = delta[i*DELTA_CELL_WIDTH+:DELTA_CELL_WIDTH];
end
endgenerate
// Instantiate the Unit Under Test (UUT)
weight_controller
#(
.NEURON_NUM (NEURON_NUM ),
.NEURON_OUTPUT_WIDTH (NEURON_OUTPUT_WIDTH ),
.ACTIVATION_WIDTH (ACTIVATION_WIDTH ),
.DELTA_CELL_WIDTH (DELTA_CELL_WIDTH ),
.WEIGHT_CELL_WIDTH (WEIGHT_CELL_WIDTH ),
.LEARNING_RATE_SHIFT (LEARNING_RATE_SHIFT ),
.LAYER_ADDR_WIDTH (LAYER_ADDR_WIDTH ),
.FRACTION_WIDTH (FRACTION_WIDTH ),
.WEIGHT_INIT_FILE (WEIGHT_INIT_FILE )
) weight_controller
(
.clk (clk ),
.rst (rst ),
.layer (layer ),
.layer_valid(layer_valid),
.layer_ready(layer_ready),
.z (z ),
.z_valid (z_valid ),
.z_ready (z_ready ),
.delta (delta ),
.delta_valid(delta_valid),
.delta_ready(delta_ready),
.w (w ),
.w_valid (w_valid ),
.w_ready (w_ready ),
.error (error )
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
layer <= 0;
layer_valid <= 0;
z <= {10'd800, 10'd700, 10'd600, 10'd500}; // 10, 20, 30, 40, 50
z_valid <= 0;
delta <= {10'd100, 10'd200, 10'd300, 10'd400}; // 5, 4, 3, 2, 1
delta_valid <= 0;
w_ready <= 0;
#10 rst <= 0;
#20 z_valid <= 1;
#2 z_valid <= 0;
#20 delta_valid <= 1;
#2 delta_valid <= 0;
#20 layer_valid <= 1;
#2 layer_valid <= 0;
#50 w_ready <= 1;
#2 w_ready <= 0;
end
endmodule
| 7.420654 |
module: weight_updater
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_updater;
parameter NEURON_NUM = 5, // size of the vectors a and delta
ACTIVATION_WIDTH = 9, // width of each signal from the neurons
DELTA_CELL_WIDTH = 12, // width of each delta cell
WEIGHT_CELL_WIDTH = 16, // width of individual weights
FRACTION_WIDTH = 0;
// Inputs
reg clk;
reg rst;
// a
reg [NEURON_NUM*ACTIVATION_WIDTH-1:0] a;
reg a_valid;
wire a_ready;
// delta
reg [NEURON_NUM*DELTA_CELL_WIDTH-1:0] delta;
reg delta_valid;
wire delta_ready;
// w
reg [NEURON_NUM*NEURON_NUM*WEIGHT_CELL_WIDTH-1:0] w;
reg w_valid;
wire w_ready;
// result
wire [NEURON_NUM*NEURON_NUM*WEIGHT_CELL_WIDTH-1:0] result;
wire result_valid;
reg result_ready;
// overflow
wire error;
// Instantiate the Unit Under Test (UUT)
weight_updater #(
.NEURON_NUM (NEURON_NUM ),
.ACTIVATION_WIDTH (ACTIVATION_WIDTH ),
.DELTA_CELL_WIDTH (DELTA_CELL_WIDTH ),
.WEIGHT_CELL_WIDTH(WEIGHT_CELL_WIDTH),
.FRACTION_WIDTH (FRACTION_WIDTH )
) updater (
.clk (clk ),
.rst (rst ),
.a (a ),
.a_valid (a_valid ),
.a_ready (a_ready ),
.delta (delta ),
.delta_valid (delta_valid ),
.delta_ready (delta_ready ),
.w (w ),
.w_valid (w_valid ),
.w_ready (w_ready ),
.result (result ),
.result_valid(result_valid),
.result_ready(result_ready),
.error (error )
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
a <= {9'd50, 9'd40, 9'd30, 9'd20, 9'd10}; // 10, 20, 30, 40, 50
a_valid <= 0;
delta <= {12'd5, 12'd4, 12'd3, 12'd2, 12'd1}; // 5, 4, 3, 2, 1
delta_valid <= 0;
w <= {16'd0, 16'd1, 16'd2, 16'd3, 16'd4, 16'd5, 16'd6, 16'd7, 16'd8, 16'd9, 16'd10, 16'd11, 16'd12, 16'd13, 16'd14, 16'd15, 16'd16, 16'd17, 16'd18, 16'd19, 16'd20, 16'd21, 16'd22, 16'd23, 16'd24};
w_valid <= 0;
result_ready <= 0;
#10 rst <= 0;
#20 a_valid <= 1;
#20 delta_valid <= 1;
#20 w_valid <= 1;
#30 result_ready <= 1;
end
endmodule
| 6.92769 |
module: weight_updater
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_updater_error;
parameter NEURON_NUM = 5, // size of the vectors a and delta
ACTIVATION_WIDTH = 9, // width of each signal from the neurons
DELTA_CELL_WIDTH = 12, // width of each delta cell
WEIGHT_CELL_WIDTH = 16, // width of individual weights
FRACTION_WIDTH = 0;
// Inputs
reg clk;
reg rst;
reg start;
reg [NEURON_NUM*ACTIVATION_WIDTH-1:0] a;
reg [NEURON_NUM*DELTA_CELL_WIDTH-1:0] delta;
reg [NEURON_NUM*NEURON_NUM*WEIGHT_CELL_WIDTH-1:0] w;
// Outputs
wire [NEURON_NUM*NEURON_NUM*WEIGHT_CELL_WIDTH-1:0] result;
wire valid, error;
// Instantiate the Unit Under Test (UUT)
weight_updater #(
.NEURON_NUM (NEURON_NUM ),
.ACTIVATION_WIDTH (ACTIVATION_WIDTH ),
.DELTA_CELL_WIDTH (DELTA_CELL_WIDTH ),
.WEIGHT_CELL_WIDTH(WEIGHT_CELL_WIDTH),
.FRACTION_WIDTH (FRACTION_WIDTH )
) updater (
.clk (clk ),
.rst (rst ),
.start (start ),
.a (a ),
.delta (delta ),
.w (w ),
.result(result),
.valid (valid ),
.error (error )
);
always
#1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
start = 0;
a = {9'd50, 9'd40, 9'd30, 9'd20, 9'd10}; // 10, 20, 30, 40, 50
delta = {12'd1000, 12'd4, 12'd3, 12'd2, 12'd1}; // 5, 4, 3, 2, 1
w = {16'd0, 16'd1, 16'd2, 16'd3, 16'd4, 16'd5, 16'd6, 16'd7, 16'd8, 16'd9, 16'd10, 16'd11, 16'd12, 16'd13, 16'd14, 16'd15, 16'd16, 16'd17, 16'd18, 16'd19, 16'd20, 16'd21, 16'd22, 16'd23, 16'd24};
#20 rst = 1;
#2 rst = 0;
#20 start = 1;
#2 start = 0;
end
endmodule
| 6.92769 |
module: mem_test_with_soc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_whole_system_mem_and_soc;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
// Outputs
wire tx;
wire interrupt_ack;
//variables
reg [10:0] shifter;
reg [4:0] j;
reg [7:0] i;
reg [11:0] char;
// Instantiate the Unit Under Test (UUT)
mem_test_with_soc uut (
.clk(clk),
.reset(reset),
.tx(tx),
.rx(rx),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val)
);
always #5
clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
rx = 1;
interrupt = 0;
bit8 = 1;
parity_en = 1;
odd_n_even = 1;
baud_val = 4'b0100;
char = 11'b 11_01000001_01;
#20;
reset = 1;
for(j=0; j<4; j=j+1) begin
for(i=0; i<11; i=i+1) begin
rx=char[i];
#104110;
end
for(i=0; i<8; i=i+1) begin
#104110;
end
char = char + 11'b00_00000001_00;
end
// Wait 100 ns for global reset to finish
#100;
$finish;
// Add stimulus here
end
endmodule
| 7.727194 |
module tb_window ();
reg clk;
reg [11:0] in1, in2;
wire [11:0] out1, out2;
wire next;
wire [2:0] state;
integer i;
initial clk = 0;
always #400 clk = ~clk;
windowing windowing_inst (
.clk (clk),
.in1 (in1),
.in2 (in2),
.out1 (out1),
.out2 (out2),
.next (next),
.state(state)
);
initial begin
in1 <= 12'b010000000000;
in2 <= 12'b010000000000;
//$monitor("state = %h", state);
@(posedge next);
for (i = 0; i < 2048; i = i + 2) begin
@(posedge clk);
@(posedge clk);
#100;
$display("i = %d, out = %d", i, out1);
$display("i = %d, out = %d", i + 1, out2);
end
#1000;
$finish;
end
always @(posedge clk) begin
//$display("state = %h", state);
end
endmodule
| 6.756002 |
module: window_on_background
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_window_on_background;
// Inputs
reg clk;
reg mode;
// Outputs
wire [2:0] r;
wire [2:0] g;
wire [2:0] b;
wire hsync;
wire vsync;
wire csync;
// Instantiate the Unit Under Test (UUT)
window_on_background uut (
.clk(clk),
.mode(mode),
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.vsync(vsync),
.csync(csync)
);
initial begin
// Initialize Inputs
clk = 0;
mode = 0;
@(negedge vsync);
$finish;
end
always begin
clk = #5 ~clk;
end
endmodule
| 7.550897 |
module tb_wire_assign;
reg in;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
wire_assign UUT (
.in (in),
.out(out)
);
initial // initial block executes only once
begin
// values for inputs
in = 0;
#period; // wait for period
if (out !== 0) begin
$display("test 1 failed");
$finish;
end else $display("in = %b , out = %b", in, out);
in = 1;
#period; // wait for period
if (out !== 1) begin
$display("test 2 failed");
$finish;
end else $display("in = %b , out = %b", in, out);
in = 0;
#period; // wait for period
if (out !== 0) begin
$display("test 3 failed");
$finish;
end else $display("in = %b , out = %b", in, out);
$display("all tests passed");
$finish;
end
endmodule
| 6.855927 |
module tb_wm8978_cfg ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire i2c_scl;
wire i2c_sda;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//对sys_clk,sys_rst_n赋初始值
initial begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;
#100 sys_rst_n <= 1'b1;
end
//clk:产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- wm89078_cfg_inst -------------
wm8978_cfg wm8978_cfg_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //系统复位，低有效
.i2c_scl(i2c_scl), //输出至WM8978的串行时钟信号scl
.i2c_sda(i2c_sda) //输出至WM8978的串行数据信号sda
);
endmodule
| 7.503996 |
module tb_writeback ();
localparam STEP = 10;
parameter OP_LOAD = 7'b0000011;
parameter OP_STORE = 7'b0100011;
parameter OP_BRANCH = 7'b1100011;
parameter OP_IMM = 7'b0010011;
parameter OP_OP = 7'b0110011;
parameter OP_JUMP = 7'b1101111;
reg [6 : 0] opcode;
reg [31 : 0] alu_out;
reg wb_reg;
reg [31 : 0] dcache_out;
reg done;
wire [31 : 0] wb_rd_data;
wire wb_enable;
writeback writeback (
.opcode(opcode),
.alu_out(alu_out),
.wb_reg(wb_reg),
.dcache_out(dcache_out),
.done(done),
.wb_rd_data(wb_rd_data),
.wb_enable(wb_enable)
);
initial begin
alu_out = 32'h10000;
dcache_out = 32'h101;
done = 1;
#(STEP * 10) opcode = OP_LOAD;
wb_reg = 1;
#(STEP) $display("[LOAD] data:%h, en:%b", wb_rd_data, wb_enable);
opcode = OP_STORE;
wb_reg = 0;
#(STEP) $display("[STORE] data:%h, en:%b", wb_rd_data, wb_enable);
opcode = OP_BRANCH;
wb_reg = 0;
#(STEP) $display("[BRANCH] data:%h, en:%b", wb_rd_data, wb_enable);
opcode = OP_IMM;
wb_reg = 1;
#(STEP) $display("[IMM] data:%h, en:%b", wb_rd_data, wb_enable);
opcode = OP_OP;
wb_reg = 1;
#(STEP) $display("[OP] data:%h, en:%b", wb_rd_data, wb_enable);
opcode = OP_JUMP;
wb_reg = 1;
#(STEP) $display("[JUPM] data:%h, en:%b", wb_rd_data, wb_enable);
#(STEP * 100) $stop;
end
endmodule
| 6.713494 |
module : tb_writeback_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_writeback_unit ();
reg clock;
reg reset;
reg opWrite;
reg opSel;
reg [4:0] opReg;
reg [31:0] ALU_result;
reg [31:0] memory_data;
wire write;
wire [4:0] write_reg;
wire [31:0] write_data;
reg scan;
writeback_unit #(
.CORE(0),
.DATA_WIDTH(32)
) writeback (
.clock(clock),
.reset(reset),
.opWrite(opWrite),
.opSel(opSel),
.opReg(opReg),
.ALU_result(ALU_result),
.memory_data(memory_data),
.write(write),
.write_reg(write_reg),
.write_data(write_data),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
opWrite = 0;
opSel = 0;
opReg = 0;
ALU_result = 0;
memory_data = 0;
scan = 0;
#10 reset = 0;
repeat (1) @ (posedge clock);
opWrite = 1;
opSel = 0;
opReg = 3;
ALU_result = 5;
memory_data = 9;
repeat (1) @ (posedge clock);
if( write != 1 |
write_reg != 3 |
write_data != 5 ) begin
scan = 1'b1;
repeat (1) @ (posedge clock);
$display("\nError: ALU Writeback failed!");
$display("\ntb_writeback_unit --> Test Failed!\n\n");
$stop();
end
opWrite = 0;
opSel = 1;
opReg = 0;
ALU_result = 4;
memory_data = 8;
repeat (1) @ (posedge clock);
if( write != 0 |
write_reg != 0 |
write_data != 8 ) begin
scan = 1'b1;
repeat (1) @ (posedge clock);
$display("\nError: Memory Writeback failed!");
$display("\ntb_writeback_unit --> Test Failed!\n\n");
$stop();
end
$display("\ntb_writeback_unit --> Test Passed!\n\n");
$stop();
end
endmodule
| 7.713825 |
module : tb_writeback_unit_CSR
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_writeback_unit_CSR();
reg clock;
reg reset;
reg opWrite;
reg opSel;
reg CSR_read_data_valid;
reg [4:0] opReg;
reg [31:0] ALU_result;
reg [31:0] CSR_read_data;
reg [31:0] memory_data;
wire write;
wire [4:0] write_reg;
wire [31:0] write_data;
reg scan;
writeback_unit_CSR #(
.CORE(0),
.DATA_WIDTH(32)
) writeback (
.clock(clock),
.reset(reset),
.opWrite(opWrite),
.opSel(opSel),
.CSR_read_data_valid(CSR_read_data_valid),
.opReg(opReg),
.ALU_result(ALU_result),
.CSR_read_data(CSR_read_data),
.memory_data(memory_data),
.write(write),
.write_reg(write_reg),
.write_data(write_data),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
opWrite = 1;
opSel = 0;
opReg = 0;
ALU_result = 2;
CSR_read_data = 1;
CSR_read_data_valid = 1'b0;
memory_data = 0;
scan = 0;
repeat (3) @ (posedge clock);
reset = 0;
repeat (1) @ (posedge clock);
if( write != 1 |
write_data != 2 ) begin
scan = 1'b1;
repeat (1) @ (posedge clock);
$display("\nError: ALU Writeback failed!");
$display("\ntb_writeback_unit_CSR --> Test Failed!\n\n");
$stop();
end
CSR_read_data_valid = 1'b1;
repeat (1) @ (posedge clock);
if( write != 1 |
write_data != 1 ) begin
scan = 1'b1;
repeat (1) @ (posedge clock);
$display("\nError: CSR Writeback failed!");
$display("\ntb_writeback_unit_CSR --> Test Failed!\n\n");
$stop();
end
$display("\ntb_writeback_unit_CSR --> Test Passed!\n\n");
$stop();
end
endmodule
| 7.713825 |
module tb_writer (
clk,
resetn,
data_in,
// data_valid_in, // Edit here
done,
image_class,
fifo_rdreq, // Edit here
// fifo_data,
fifo_empty // Edit here
);
parameter DWIDTH = 32;
parameter output_file = "";
//
parameter WIDTH = 56;
parameter HEIGHT = 56;
parameter NUM_IMG = 1;
localparam num_data = WIDTH * HEIGHT;
input clk;
input resetn;
input [DWIDTH-1:0] data_in;
// input data_valid_in; // Edit here
output reg done;
input image_class;
integer file_out;
initial begin
file_out = $fopen(output_file, "w");
end
// input [7:0] num_data;
output reg fifo_rdreq;
// input [DWIDTH-1:0] fifo_data;
input fifo_empty;
// reg data_valid;
reg [15:0] data_cnt;
// wire sof; // start of frame
// assign sof = (data_cnt == 1) && (data_valid==1);
// // generate ready signal
// reg[15:0]a;
// always @(posedge clk) begin
// a <=$urandom%10;
// end
// //
// wire ready;
// // assign ready = a[4] | a[0];
// assign ready = 1;
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
fifo_rdreq <= 0;
end else begin
// data_valid <= fifo_rdreq; // delay 1clk after read fifo
if (fifo_empty == 1'b0 /*&& ready == 1*/) begin
// // ly tuong ()
fifo_rdreq <= 1'b1;
// //
end else begin
fifo_rdreq <= 1'b0;
end
end
end
// delay data valid 1 clk
// wire data to text
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
data_cnt <= 0;
done <= 1'b0;
end else begin
// if(data_valid_in) begin
if (fifo_rdreq && fifo_empty == 1'b1) begin
// for write data to text
data_cnt <= data_cnt + 1;
//
// if (data_cnt== 0) begin
// // add header file
// $fwrite(file_out, "%d\n", num_data);
// end
$display("%t \tIMAGE PROCEED %d", $time, data_cnt);
if (data_cnt < NUM_IMG * num_data-1) // Edit here
begin
$fwrite(file_out, "%h, %h\n", image_class, data_in); // Edit here
done <= 1'b0;
end else
// if(data_cnt == num_data-1)
begin
$fwrite(file_out, "%h, %h\n", image_class, data_in); // Edit here
// $fwrite(file_out, "%h\n", data_in);
done <= 1'b1;
#5 $fclose(file_out);
$display("writed file done");
#5 $finish;
end
// else
// // if(data_cnt == num_data)
// begin
// $fclose(file_out);
// $display("writed file done");
// $finish;
// end
end else begin
data_cnt <= data_cnt;
done <= 1'b0;
end
end
end
endmodule
| 7.571256 |
module tb_write_axi_buffer ();
reg clk;
reg rst;
localparam LINE_SIZE = 8;
reg en;
reg addr;
reg [32*LINE_SIZE-1:0] data;
wire empty;
initial begin
repeat (300) begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
end
wire [3 : 0] awid;
wire [ 31:0] awaddr;
wire [7 : 0] awlen;
wire [2 : 0] awsize;
wire [1 : 0] awburst;
wire awvalid;
wire awready;
wire [ 31:0] wdata;
wire [3 : 0] wstrb;
wire wlast;
wire wvalid;
wire wready;
wire [3 : 0] arid;
reg [ 31:0] araddr;
reg [7 : 0] arlen;
reg [2 : 0] arsize;
reg [1 : 0] arburst;
reg arvalid;
wire arready;
wire [3 : 0] rid;
wire [ 31:0] rdata;
wire [1 : 0] rresp;
wire rlast;
wire rvalid;
reg rready;
wire [3 : 0] bid;
wire [1 : 0] bresp;
wire bvalid;
wire bready;
write_axi_buffer #(LINE_SIZE) write_axi_buffer0 (
.clk(clk),
.rst(rst),
.en (en),
.addr (addr),
.data (data),
.empty(empty),
.axi_awaddr (awaddr),
.axi_awlen (awlen),
.axi_awsize (awsize),
.axi_awvalid(awvalid),
.axi_awready(awready),
.axi_wdata (wdata),
.axi_wstrb (wstrb),
.axi_wlast (wlast),
.axi_wvalid (wvalid),
.axi_wready (wready),
.axi_bvalid (bvalid),
.axi_bready (bready)
);
inst_ram axi_i_ram (
.rsta_busy(),
.rstb_busy(),
.s_aclk (clk),
.s_aresetn(~rst),
.s_axi_awid (4'h0),
.s_axi_awaddr (awaddr),
.s_axi_awlen (awlen),
.s_axi_awsize (awsize),
.s_axi_awburst(2'b01),
.s_axi_awvalid(awvalid),
.s_axi_awready(awready),
.s_axi_wdata (wdata),
.s_axi_wstrb (wstrb),
.s_axi_wlast (wlast),
.s_axi_wvalid(wvalid),
.s_axi_wready(wready),
.s_axi_bid (),
.s_axi_bresp (bresp),
.s_axi_bvalid(bvalid),
.s_axi_bready(bready),
.s_axi_arid (),
.s_axi_araddr (araddr),
.s_axi_arlen (arlen),
.s_axi_arsize (arsize),
.s_axi_arburst(arburst),
.s_axi_arvalid(arvalid),
.s_axi_arready(arready),
.s_axi_rid (),
.s_axi_rdata (rdata),
.s_axi_rresp (rresp),
.s_axi_rlast (rlast),
.s_axi_rvalid(rvalid),
.s_axi_rready(rready)
);
initial begin
rst = 1'b1;
araddr = 32'h0;
arlen = 8'h0;
arsize = 3'h0;
arburst = 2'h0;
arvalid = 0;
rready = 0;
#100 rst = 1'b0;
#100 begin
en = 1'b1;
addr = 32'hbfc0_0000;
data = {8'h1, 8'h2, 8'h3, 8'h4, 8'h5, 8'h6, 8'h7, 8'h8};
end
#10 begin
en = 1'b0;
end
#200 begin
araddr = 32'hbfc0_0000;
arlen = LINE_SIZE / 4 - 1;
arsize = 3'b010;
arburst = 2'b01;
arvalid = 1'b1;
rready = 1'b1;
end
end
endmodule
| 7.029376 |
module tb_write_full ();
reg w_en;
reg w_clk;
reg w_rst;
reg [4:0] read_addr_gray_sync, temp, write_addr_gray;
wire [3:0] write_addr;
wire flag_full;
integer i;
initial begin
w_clk = 0;
w_rst = 0;
#20 w_rst = 1;
#40 w_rst = 0;
end
initial begin
for (i = 0; i <= 100; i = i + 1) #20 w_clk = ~w_clk;
end
initial begin
w_en = 0;
#60 w_en = 1;
temp = 3;
read_addr_gray_sync = 0;
if (w_en) begin
for (i = 0; i <= 100; i = i + 1) begin
temp = temp + 1;
read_addr_gray_sync = (temp >> 1) ^ temp;
#45;
end
end else;
end
write_full #(
.FIFO_DEPTH_BIT(10'd4)
) inst_write_full (
.w_clk (w_clk),
.w_rst (w_rst),
.w_en (w_en),
.read_addr_gray_sync(read_addr_gray_sync),
.flag_full (flag_full),
.write_addr (write_addr),
.write_addr_gray(write_addr_gray)
);
initial begin
$vcdpluson;
end
endmodule
| 6.884622 |
module TB_x64_adc()
/* Inputs from ADC */
output adc_clk_n,
output adc_clk_p,
output [7:0] in_0_n,
output [7:0] in_0_p,
output fc_0_n,
output fc_0_p,
output [7:0] in_1_n,
output [7:0] in_1_p,
output fc_1_n,
output fc_1_p,
output [7:0] in_2_n,
output [7:0] in_2_p,
output fc_2_n,
output fc_2_p,
output [7:0] in_3_n,
output [7:0] in_3_p,
output fc_3_n,
output fc_3_p,
output [7:0] in_4_n,
output [7:0] in_4_p,
output fc_4_n,
output fc_4_p,
output [7:0] in_5_n,
output [7:0] in_5_p,
output fc_5_n,
output fc_5_p,
output [7:0] in_6_n,
output [7:0] in_6_p,
output fc_6_n,
output fc_6_p,
output [7:0] in_7_n,
output [7:0] in_7_p,
output fc_7_n,
output fc_7_p,
// /* Application outputs */
// output adc_clk0,
// output adc_clk90,
// output adc_clk180,
// output adc_clk270,
// output [12*8-1:0] adc_data0,
// output adc_dvld0,
// output [12*8-1:0] adc_data1,
// output adc_dvld1,
// output [12*8-1:0] adc_data2,
// output adc_dvld2,
// output [12*8-1:0] adc_data3,
// output adc_dvld3,
// output [12*8-1:0] adc_data4,
// output adc_dvld4,
// output [12*8-1:0] adc_data5,
// output adc_dvld5,
// output [12*8-1:0] adc_data6,
// output adc_dvld6,
// output [12*8-1:0] adc_data7,
// output adc_dvld7,
// /* Software input/outputs */
// output [12*8-1:0] fc_sampled,
output dly_clk,
output [7:0] dly_rst,
output [7:0] dly_en,
output [7:0] dly_inc_dec_n,
output dcm_reset,
// output dcm_locked
);
initial begin
$display("PASSED");
end
endmodule
| 6.963298 |
module tb_xdom_pulse_sender;
reg grst_i;
reg odom_clk_i;
reg odom_pulse_i;
reg xdom_clk_i;
wire xdom_pulse_o;
wire busy_o;
wire err_o;
xdom_pulse_sender uut (
.grst_i(grst_i),
.odom_clk_i(odom_clk_i),
.odom_pulse_i(odom_pulse_i),
.xdom_clk_i(xdom_clk_i),
.xdom_pulse_o(xdom_pulse_o),
.busy_o(busy_o),
.err_o(err_o)
);
parameter ODOM_PERIOD = 10;
parameter XDOM_PERIOD = 100;
initial begin
$dumpfile("db_tb_xdom_pulse_sender.vcd");
$dumpvars(0, tb_xdom_pulse_sender);
end
initial begin
odom_clk_i = 1'b0;
#(ODOM_PERIOD / 2);
forever #(ODOM_PERIOD / 2) odom_clk_i = ~odom_clk_i;
end
initial begin
xdom_clk_i = 1'b0;
#(XDOM_PERIOD / 2);
forever #(XDOM_PERIOD / 2) xdom_clk_i = ~xdom_clk_i;
end
initial begin
#10;
odom_pulse_i = 1'b0;
grst_i = 1'b1;
#5;
grst_i = 1'b0;
/* generate a pulse */
@(posedge odom_clk_i);
odom_pulse_i = 1'b1;
@(posedge odom_clk_i);
odom_pulse_i = 1'b0;
repeat (1000) @(posedge odom_clk_i);
$finish(0);
end
endmodule
| 7.311821 |
module xnor_gate_top;
reg I0, I1;
wire Out;
xnor_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
end
endmodule
| 6.65772 |
module.
`timescale 1ns/1ns
`include "my_xor.v"
module tb_xor;
reg [1:0]bus;
wire out;
my_xor test_xor(bus, out);
initial begin
$dumpfile("tb_xor.vcd");
$dumpvars(0, tb_xor);
bus = 2'b11;
#10;
bus = 2'b00;
#10;
bus = 2'b10;
#10;
bus = 2'b01;
#10;
$display("success.");
end // initial begin
endmodule
| 6.603418 |
module tb_xpsr_reg ();
reg [31:0] inst;
reg clk;
reg rst;
reg en_apsr;
reg en_ipsr;
reg en_epsr;
reg en_carry;
reg inst_valid;
wire [4:0] apsr;
wire [8:0] ipsr;
wire [9:0] epsr;
integer fd;
xpsr_reg u0 (
inst,
clk,
rst,
en_apsr,
en_ipsr,
en_epsr,
en_carry,
inst_valid,
apsr,
ipsr,
epsr
);
reg [31:0] inst_mem[256*6*2*2+1000:0];
initial begin
clk = 0;
rst = 1;
#6 rst = 0;
$readmemh("./inst_it.dat", inst_mem);
fd = $fopen("./xpsr_reg.log", "w");
$fdisplay(fd, "inst\ten_apsr\ten_ipsr\ten_epsr\ten_carry\tinst_valid\tapsr\tipsr\tepsr\ttime");
end
always #5 begin
$fdisplay(fd, "%h\t%b\t%b\t%b\t%b\t%b\t%b\t%h\t%b @%d", inst, en_apsr, en_ipsr, en_epsr,
en_carry, inst_valid, apsr, ipsr, epsr, $time);
{over_flag, inst[9:5]} = {over_flag, inst[9:5]} + 1;
if (over_flag) begin
$fclose(fd);
$finish;
end
end
endmodule
| 6.56803 |
module: tv80n_wrapper
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_z80_y_spi;
// Inputs
reg reset_n;
reg sysclk;
reg [7:0] cpudin;
// Outputs
wire m1_n;
wire mreq_n;
wire iorq_n;
wire rd_n;
wire wr_n;
wire rfsh_n;
wire halt_n;
wire busak_n;
wire [15:0] cpuaddr;
wire [7:0] cpudout;
// Instantiate the Unit Under Test (UUT)
tv80n_wrapper cpu (
.m1_n(m1_n),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.halt_n(halt_n),
.busak_n(busak_n),
.A(cpuaddr),
.dout(cpudout),
.reset_n(reset_n),
.clk(sysclk),
.clk_enable(wait_spi_n),
.wait_n(1'b1),
.int_n(1'b1),
.nmi_n(1'b1),
.busrq_n(1'b1),
.di(cpudin)
);
wire [7:0] spi_dout;
reg [7:0] memory_dout;
wire oe_spi, oe_romyram;
wire [7:0] zxuno_addr_to_cpu; // al bus de datos de entrada del Z80
wire [7:0] zxuno_addr; // direccion de registro actual
wire regaddr_changed; // indica que se ha escrito un nuevo valor en el registro de direcciones
wire oe_zxunoaddr; // el dato en el bus de entrada del Z80 es vlido
wire zxuno_regrd; // Acceso de lectura en el puerto de datos de ZX-Uno
wire zxuno_regwr; // Acceso de escritura en el puerto de datos del ZX-Uno
wire flash_cs_n, flash_clk, flash_di;
wire flash_do;
wire sd_cs_n, sd_clk, sd_mosi;
reg sd_miso;
wire wait_spi_n;
always @* begin
case (1'b1)
oe_zxunoaddr : cpudin = zxuno_addr_to_cpu;
oe_spi : cpudin = spi_dout;
oe_romyram : cpudin = memory_dout;
default : cpudin = 8'hFF;
endcase
end
zxunoregs addr_reg_zxuno (
.clk(sysclk),
.rst_n(reset_n),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(cpudout),
.dout(zxuno_addr_to_cpu),
.oe(oe_zxunoaddr),
.addr(zxuno_addr),
.read_from_reg(zxuno_regrd),
.write_to_reg(zxuno_regwr),
.regaddr_changed(regaddr_changed)
);
flash_and_sd cacharros_con_spi (
.clk(sysclk),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.addr(zxuno_addr),
.ior(zxuno_regrd),
.iow(zxuno_regwr),
.din(cpudout),
.dout(spi_dout),
.oe(oe_spi),
.wait_n(wait_spi_n),
.in_boot_mode(1'b1),
.flash_cs_n(flash_cs_n),
.flash_clk(flash_clk),
.flash_di(flash_di),
.flash_do(flash_do),
.disable_spisd(1'b0),
.sd_cs_n(sd_cs_n),
.sd_clk(sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso)
);
initial begin
// Initialize Inputs
reset_n = 0;
sysclk = 0;
repeat (4)
@(posedge sysclk);
reset_n = 1;
@(negedge halt_n);
$finish;
end
//////////////////////////////////////////
reg [7:0] spimem[0:3];
reg [1:0] indxspi = 2'b00;
reg [7:0] regspi;
assign flash_do = regspi[7];
reg data_from_mosi;
initial begin
spimem[0] = 8'b10101010;
spimem[1] = 8'b11100111;
spimem[2] = 8'b00110011;
spimem[3] = 8'b00001111;
end
always begin
regspi = spimem[indxspi];
if (flash_cs_n == 1'b0) begin
repeat(8) begin
@(posedge flash_clk);
data_from_mosi = flash_di;
@(negedge flash_clk);
regspi = {regspi[6:0], data_from_mosi};
end
indxspi = indxspi + 2'b01;
end
else
@(posedge sysclk);
end
///////////////////////////////////////////
///////////////////////////////////////////
assign oe_romyram = (mreq_n == 1'b0 && rd_n == 1'b0);
reg [7:0] rom[0:255];
initial $readmemh ("testspi.hex", rom);
reg [7:0] ram[0:255];
always @* begin
if (cpuaddr >= 256 && mreq_n == 1'b0 && wr_n == 1'b0)
ram[cpuaddr[7:0]] = cpudout;
memory_dout = (cpuaddr < 256)? rom[cpuaddr[7:0]] : ram[cpuaddr[7:0]];
end
///////////////////////////////////////////
always begin
sysclk = #5 ~sysclk;
end
endmodule
| 6.539653 |
module tb_ZF;
// Input testcase spec:
parameter BID_WIDTH = 32;
parameter TEST_NUM = 1000;
//////////////////////////////////////////////////////////////////////
parameter H_width = BID_WIDTH * 16;
parameter y_width = BID_WIDTH * 8;
parameter link_to_H_binary = "C:/Users/ROG STRIX/Desktop/projecy/memfile/H_binary.txt";
parameter link_to_y_binary = "C:/Users/ROG STRIX/Desktop/projecy/memfile/y_binary.txt";
parameter link_to_n_binary = "C:/Users/ROG STRIX/Desktop/projecy/memfile/n_binary.txt";
parameter link_to_x_binary_hardware = "C:/Users/ROG STRIX/Desktop/projecy/memfile/x_binary_hardware.txt";
reg enable, clk, reset_n, accept_in;
wire accept_out, ready_out;
reg [H_width-1:0] H_matrix;
reg [y_width-1:0] y, n;
wire [y_width-1:0] X;
ZF uut (
enable,
clk,
reset_n,
accept_in,
accept_out,
ready_out,
H_matrix,
y,
n,
X
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset_n = 0;
@(negedge clk);
reset_n = 1;
end
initial begin
enable = 0;
@(posedge clk);
enable = 1;
accept_in = 1;
end
reg [H_width-1:0] H_matrix_data[0:TEST_NUM - 1];
reg [y_width-1:0] y_data[0:TEST_NUM - 1];
reg [y_width-1:0] n_data[0:TEST_NUM - 1];
reg [y_width-1:0] x_data[0:TEST_NUM - 1];
initial $readmemb(link_to_H_binary, H_matrix_data);
initial $readmemb(link_to_y_binary, y_data);
initial $readmemb(link_to_n_binary, n_data);
integer i = 0, j = 0;
always @(accept_out, ready_out) begin
if (accept_out) begin
H_matrix = H_matrix_data[i];
y = y_data[i];
n = n_data[i];
i = i + 1;
end
if (ready_out) begin
x_data[j] = X;
j = j + 1;
end
if (j == TEST_NUM) begin
$writememb(link_to_x_binary_hardware, x_data);
$stop;
end
end
endmodule
| 8.455647 |
module tb_zigzag ();
reg clk_i;
reg rstn_i;
reg [ `RUN_BIT-1:0] hd_run_i;
reg [ `CAT_BIT-1:0] hd_cat_i;
reg hd_gecerli_i;
wire hd_hazir_o;
wire [`PIXEL_BIT-1:0] ct_veri_o;
wire [`BLOCK_BIT-1:0] ct_row_o;
wire [`BLOCK_BIT-1:0] ct_col_o;
wire ct_gecerli_o;
wire ct_blok_son_o;
reg ct_hazir_i;
zigzag_normalizer zn (
.clk_i (clk_i),
.rstn_i (rstn_i),
.hd_run_i (hd_run_i),
.hd_cat_i (hd_cat_i),
.hd_gecerli_i (hd_gecerli_i),
.hd_hazir_o (hd_hazir_o),
.ct_veri_o (ct_veri_o),
.ct_row_o (ct_row_o),
.ct_col_o (ct_col_o),
.ct_gecerli_o (ct_gecerli_o),
.ct_blok_son_o(ct_blok_son_o),
.ct_hazir_i (ct_hazir_i)
);
always begin
clk_i = 1'b0;
#5;
clk_i = 1'b1;
#5;
end
integer i;
localparam TEST_LEN = 8;
reg [`RUN_BIT-1:0] test_runs[0:TEST_LEN-1];
reg [`RUN_BIT-1:0] test_cats[0:TEST_LEN-1];
reg handshake;
initial begin
test_runs['d0] = 0;
test_runs['d1] = 3;
test_runs['d2] = 1;
test_runs['d3] = 0;
test_runs['d4] = 10;
test_runs['d5] = 5;
test_runs['d6] = 5;
test_cats['d0] = 1;
test_cats['d1] = 2;
test_cats['d2] = 3;
test_cats['d3] = 4;
test_cats['d4] = 5;
test_cats['d5] = 6;
test_cats['d6] = 7;
test_runs[TEST_LEN-1] = 0;
test_cats[TEST_LEN-1] = 0;
rstn_i = 1'b0;
handshake = `LOW;
ct_hazir_i = `HIGH;
repeat (20) @(posedge clk_i) #2;
rstn_i = 1'b1;
for (i = 0; i < TEST_LEN;) begin
hd_run_i = test_runs[i];
hd_cat_i = test_cats[i];
hd_gecerli_i = `HIGH;
handshake = hd_hazir_o && hd_gecerli_i;
@(posedge clk_i) #2;
if (handshake) begin
i = i + 1;
end
end
hd_gecerli_i = `LOW;
end
endmodule
| 7.533416 |
module: zxuno
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_zxuno;
// Inputs
reg clk;
reg wssclk;
reg ramclk;
reg power_on_reset_n;
reg clkps2;
reg dataps2;
reg ear;
// Outputs
wire [2:0] r;
wire [2:0] g;
wire [2:0] b;
wire csync;
wire audio_out;
wire [13:0] addr_rom_16k;
wire [18:0] sram_addr;
wire sram_we_n;
// Bidirs
wire [7:0] sram_data;
// Instanciacin del sistema
wire [7:0] rom_dout;
// Instantiate the Unit Under Test (UUT)
zxuno uut (
.clk(clk),
.wssclk(wssclk),
.power_on_reset_n(power_on_reset_n),
.r(r),
.g(g),
.b(b),
.csync(csync),
.clkps2(clkps2),
.dataps2(dataps2),
.ear(ear),
.audio_out(audio_out),
.addr_rom_16k(addr_rom_16k),
.rom_dout(rom_dout),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
);
rom rom_inicial (
.clk(clk),
.a(addr_rom_16k),
.dout(rom_dout)
);
ram512kb ram_simulada (
.a(sram_addr),
.d(sram_data),
.we_n(sram_we_n)
);
initial begin
// Initialize Inputs
clk = 0;
wssclk = 0;
ramclk = 0;
clkps2 = 0;
dataps2 = 0;
ear = 0;
power_on_reset_n = 0;
// Wait 500 ns for global reset to finish
#500 power_on_reset_n = 1;
// Add stimulus here
end
always begin // reloj de 28MHz para todo el sistema
clk = #17.857142857142857142857142857143 ~clk;
end
always begin // reloj de 5MHz para el WSS
wssclk = #100 ~wssclk;
end
always begin // reloj de 20MHz, para la SRAM
ramclk = #25 ~ramclk;
end
endmodule
| 7.354907 |
module ram512kb (
input wire [18:0] a,
inout wire [7:0] d,
input wire we_n
);
reg [7:0] ram[0:524287];
integer i;
initial begin
for (i = 0; i < 524288; i = i + 1) ram[i] = 0;
end
reg [7:0] dout;
assign d = (we_n == 1'b0) ? 8'hZZ : dout;
always @* begin
if (we_n == 1'b0) ram[a] = d;
else dout = ram[a];
end
endmodule
| 7.071599 |
module tb__ghash_core_vs_ghash_core_koa ();
// PARAMETERS.
localparam NB_BLOCK = 128;
localparam N_BLOCKS = 2;
localparam NB_DATA = NB_BLOCK * N_BLOCKS;
// OUTPUTS.
wire [ NB_BLOCK-1:0] tb_o_data_y_KOA;
wire [ NB_BLOCK-1:0] tb_o_data_y_N_BLK;
// INPUTS.
reg [ NB_DATA-1:0] tb_i_data_x_bus;
reg [ NB_BLOCK-1:0] tb_i_data_key; // subkey "H"
wire [NB_DATA-1 : 0] tb_o_h_key_powers;
wire [ N_BLOCKS-1:0] tb_i_skip_bus;
wire tb_i_valid;
wire tb_i_reset;
wire tb_i_sop;
reg tb_i_clock;
wire [ NB_BLOCK-1:0] data_length;
integer count = 0;
reg [ NB_BLOCK-1:0] tb_o_data_y_N_BLK_reg;
reg [ NB_BLOCK-1:0] tb_o_data_y_N_BLK_reg0;
initial begin
tb_i_clock <= 1'b0;
end
always #(5) tb_i_clock = ~tb_i_clock;
always @(posedge tb_i_clock) begin
count <= count + 1;
end
assign tb_i_reset = (count == 0) || (count == 1);
assign tb_i_valid = 1'b1;
always @(posedge tb_i_clock) begin
if ((count % 3)) begin
tb_i_data_x_bus = {
{$random, $random, $random, $random}, {$random, $random, $random, $random}
};
tb_i_data_key = {$random, $random, $random, $random};
end
end
assign tb_i_sop = ((count % 300) == 0) || (count == 2);
assign tb_i_skip_bus = ((count % 305) == 1) ? 2'b10 : 2'b00;
// MODULE INSTANTIATION.
h_key_power_table #(
.NB_BLOCK(NB_BLOCK),
.N_BLOCKS(N_BLOCKS),
.NB_DATA (NB_DATA)
) u_h_key_power_table (
// OUTPUTS.
.o_h_key_powers(tb_o_h_key_powers),
// INPUTS
.i_h_key (tb_i_data_key),
.i_clock (tb_i_clock)
);
ghash_core_koa_pipe_parallel #(
// PARAMETERS.
.NB_BLOCK(NB_BLOCK), // [HINT] Any value different to 128 is not valid
.N_BLOCKS(N_BLOCKS),
.NB_DATA (NB_DATA)
) u_ghash_core_koa_pipe_parallel (
// OUTPUTS.
.o_data_y (tb_o_data_y_KOA),
// INPUTS.
.i_data_x (tb_i_data_x_bus),
.i_data_x_prev (128'b0),
.i_h_key_powers(tb_o_h_key_powers),
.i_skip_bus (tb_i_skip_bus),
.i_sop (tb_i_sop),
.i_valid (tb_i_valid),
.i_reset ({tb_i_reset, tb_i_reset}),
.i_clock (tb_i_clock)
);
ghash_n_blocks #(
.NB_BLOCK(NB_BLOCK),
.N_BLOCKS(N_BLOCKS),
.NB_DATA (NB_DATA)
) u_ghash_n_blocks (
.o_data_y (tb_o_data_y_N_BLK),
.i_data_x_bus (tb_i_data_x_bus),
.i_data_x_initial(128'b0),
.i_hash_subkey_h (tb_i_data_key),
.i_sop (tb_i_sop),
.i_valid (tb_i_valid),
.i_skip_bus (tb_i_skip_bus),
.i_reset (tb_i_reset),
.i_clock (tb_i_clock)
);
always @(posedge tb_i_clock) begin
tb_o_data_y_N_BLK_reg0 <= tb_o_data_y_N_BLK;
tb_o_data_y_N_BLK_reg <= tb_o_data_y_N_BLK_reg0;
end
wire comp;
assign comp = tb_o_data_y_N_BLK_reg == tb_o_data_y_KOA;
endmodule
| 6.994495 |
module tc16a (
input [15:0] D,
input CMP,
output [15:0] Y
);
// internal signals
assign Y = (CMP ? ~D : D) + CMP;
endmodule
| 7.954677 |
module tc18a (
input [17:0] D,
input CMP,
output [17:0] Y
);
// internal signals
assign Y = (CMP ? ~D : D) + CMP;
endmodule
| 6.677291 |
module: TC1_traffic_light_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TC1_traffic_light_controller_test;
// Inputs
reg clk;
reg sync_reset;
// Outputs
//wire start_timer, Ored_start,tMG,tMY,tSG,tSY;
wire MR;
wire MG;
wire MY;
wire SR;
wire SG;
wire SY;
// Instantiate the Unit Under Test (UUT)
TC1_traffic_light_controller uut (
.clk(clk),
.sync_reset(sync_reset),
//.start_timer(start_timer), .Ored_start(Ored_start), .tMG(tMG), .tMY(tMY), .tSG(tSG), .tSY(tSY),
.MR(MR),
.MG(MG),
.MY(MY),
.SR(SR),
.SG(SG),
.SY(SY)
);
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
// Initialize Inputs
sync_reset = 1;
$monitor("time: %d, reset:%b. RGY- M: %b %b %b| S: %b %b %b",$time, sync_reset, MR,MG,MY, SR,SG,SY);
//$monitor("time: %d, reset:%b. RGY- M: %b %b %b| S: %b %b %b| \t start_timer:%b,Ored:%b tMG tMY: %b %b| tSG tSY: %b %b",$time, sync_reset, MR,MG,MY, SR,SG,SY, start_timer, Ored_start, tMG, tMY, tSG, tSY);
// Wait 100 ns for global reset to finish
#40;
sync_reset = 0;
// Add stimulus here
#840;
sync_reset = 1;
#20
sync_reset = 0;
#300;
$finish;
end
endmodule
| 7.203423 |
module: TC1_traffic_timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TC1_traffic_timer_test;
// Inputs
reg start;
reg clk;
// Outputs
wire tMG;
wire tMY;
wire tSG;
wire tSY;
// Instantiate the Unit Under Test (UUT)
TC1_traffic_timer uut (
.start(start),
.clk(clk),
.tMG(tMG),
.tMY(tMY),
.tSG(tSG),
.tSY(tSY)
);
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
// Initialize Inputs
start = 1;
$monitor("time %d..start: %b....MG %b| MY:%b| SG %b| SY %b",$time, start, tMG, tMY,tSG,tSY);
// Wait 100 ns for global reset to finish
#100;
start = 0;
// Add stimulus here
#120; start = 1;
#20; start = 0;
#340; start = 1;
$finish;
end
endmodule
| 7.203423 |
module tc8s (
input [7:0] D,
input CMP,
output [7:0] Q,
input CE,
input CLK,
input SCLR
);
// internal signals
reg [7:0] s;
always @(posedge CLK) begin
if (SCLR) s <= 0;
else if (CE) s <= (CMP ? ~D : D) + CMP;
end
assign Q = s;
endmodule
| 6.77376 |
module TCAM_Adapter (
// inputs
clk,
rst,
i_Key,
i_Set_String,
i_Set_ID,
i_Set_Enable,
// outputs
o_RuleID,
o_Valid,
o_SetDone
);
// ==========================================================================
// == Parameters
// ==========================================================================
parameter KWID = 104; //Key width
parameter MASKWID = KWID / 8; //13
parameter IDWID = 8;
parameter PRIOR = 8; // 8-bit priority
parameter TOTALWID = KWID + MASKWID + PRIOR;
// ==========================================================================
// == Signal Declarations
// ==========================================================================
wire [KWID-1:0] Key;
wire [TOTALWID-1:0] String;
wire [IDWID-1:0] ID;
// ==========================================================================
// == Port Declarations
// ==========================================================================
input rst;
input clk;
// inputs
input i_Key;
input i_Set_String;
input i_Set_ID;
// outputs
output o_RuleID;
output o_Valid;
output o_SetDone;
// ==========================================================================
// == Architecture: Structural
// ==========================================================================
// -- Serial to Parallel Connection
Serial_to_Parallel #(KWID) Key_Inst (
clk,
rst,
i_Key,
Key
);
Serial_to_Parallel #(TOTALWID) String_Inst (
clk,
rst,
i_Set_String,
String
);
Serial_to_Parallel #(IDWID) Set_ID_Inst (
clk,
rst,
i_Set_ID,
ID
);
// -- TCAM
tcam(
.clk(clk),
.rst(rst),
.i_Key(Key),
.o_RuleID(o_RuleID),
.o_Valid(o_Valid),
.o_SetDone(o_SetDone),
.i_Set_ID(ID),
.i_Set_String(String),
.i_Set_Enable(i_Set_Enable)
);
endmodule
| 8.038288 |
module tcam_bl (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [10 : 0] wr_addr;
output busy;
output match;
output [2047 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(2),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(2048),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(2048),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("tcam_bl.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(2),
.c_width(32),
.c_wr_addr_width(11)
) inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
endmodule
| 6.538496 |
module upb_tcam_entry #(
parameter SRL_SIZE = 32, // use 32 here to generate SRLC32E instances
parameter TCAM_WIDTH = 49, // number of SRLs in parallel, so total width is log2(SRL_SIZE) * TCAM_WIDTH
parameter INPUT_WIDTH = 32, // input width for feeding data in
parameter FORCE_MUXCY = 0 // force usage of carry chain on current Xilinx devices
) (
input wire CLK,
input wire RST,
input wire [$clog2(SRL_SIZE)*TCAM_WIDTH-1:0] content,
input wire [INPUT_WIDTH-1:0] wdata,
input wire [$clog2(TCAM_WIDTH/INPUT_WIDTH)-1:0] waddr,
input wire wen,
output logic match
);
logic [SRL_SIZE-1:0] srl[TCAM_WIDTH-1:0] /* synthesis syn_srlstyle = "select_srl" */;
generate
for (genvar i = 0; i < TCAM_WIDTH; i++) begin // write data into SRLs
always_ff @(posedge CLK) begin
if (wen == 1 && i < INPUT_WIDTH * (waddr + 1) && i >= INPUT_WIDTH * waddr) begin
srl[i] <= {srl[i][SRL_SIZE-2:0], wdata[i-(waddr*INPUT_WIDTH)]};
end
end
end
endgenerate
/* We want to use the MUXCYs in the carry chain to generate our match signal if they
are available. If the necessary MUXCYs are not inferred automatically we have to
do this on our own. */
generate
if (FORCE_MUXCY) begin
logic [TCAM_WIDTH-1:0] mux_o;
assign match = mux_o[TCAM_WIDTH-1];
MUXCY muxcy0 (
.O (mux_o[0]),
.CI(1),
.DI(0),
.S (srl[0][content[$clog2(SRL_SIZE)-1-:$clog2(SRL_SIZE)]])
);
for (genvar i = 1; i < TCAM_WIDTH; i++) begin
MUXCY muxcys (
.O (mux_o[i]),
.CI(mux_o[i-1]),
.DI(0),
.S (srl[i][content[(i+1)*$clog2(SRL_SIZE)-1-:$clog2(SRL_SIZE)]])
);
end
end else begin
always_comb begin
match = 1;
for (integer i = 0; i < TCAM_WIDTH; i++) begin
match = match & srl[i][content[(i+1)*$clog2(SRL_SIZE)-1-:$clog2(SRL_SIZE)]];
end
end
end
endgenerate
endmodule
| 8.944739 |
module tcam_entry_tb;
logic CLK;
logic RST;
logic [9:0] content;
logic wdata;
logic waddr;
logic wen;
wire match;
// UUT
upb_tcam_entry #(
.SRL_SIZE(32), // use 32 here to generate SRLC32E instances
.TCAM_WIDTH(2), // number of SRLs in parallel, so total width is log2(SRL_SIZE) * TCAM_WIDTH
.INPUT_WIDTH(1), // input width for feeding data in
.FORCE_MUXCY(0) // force usage of carry chain on current Xilinx devices
) uut (
CLK,
RST,
content,
wdata,
waddr,
wen,
match
);
logic [31:0] srl_data[1:0];
assign srl_data[0] = 32'haffedeaf;
assign srl_data[1] = 32'hdeadbeef;
initial begin
CLK = 1;
RST = 0;
content = 10'b0;
wdata = 0;
waddr = 0;
wen = 0;
#100
// feed data into tcam entry
for (
int i = 1; i >= 0; i--
) begin
for (int j = 31; j >= 0; j--) begin
waddr = i;
wen = 1;
wdata = srl_data[i][j];
#2;
end
end
wen = 0;
#10;
// look up contents
for (int i = 0; i < 1024; i++) begin
content = i;
#2
if (match != (srl_data[0][i] && srl_data[1][i>>5])) begin
$display("Error!");
$display(" Content: ", content);
$display(" Match: ", match);
$stop();
end
end
$display("All fine :)");
#100 $stop();
end
always begin
#1 CLK <= ~CLK;
end
endmodule
| 7.322655 |
module tcam_line_array #(
parameter ADDR_WIDTH = 8,
parameter KEY_WIDTH = 8,
parameter MASK_DISABLE = 0
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] set_addr,
input wire [KEY_WIDTH-1:0] set_key,
input wire [KEY_WIDTH-1:0] set_xmask,
input wire set_clr,
input wire set_valid,
input wire [KEY_WIDTH-1:0] req_key,
input wire req_valid,
output wire [2**ADDR_WIDTH-1:0] line_match
);
localparam MEM_WIDTH = (MASK_DISABLE) ? KEY_WIDTH : KEY_WIDTH * 2;
reg [MEM_WIDTH-1:0] mem[2**ADDR_WIDTH-1:0];
reg [2**ADDR_WIDTH-1:0] active;
reg [2**ADDR_WIDTH-1:0] match;
wire [KEY_WIDTH-1:0] key[2**ADDR_WIDTH-1:0];
wire [KEY_WIDTH-1:0] xmask[2**ADDR_WIDTH-1:0];
integer i;
genvar g;
generate
for (g = 0; g < 2 ** ADDR_WIDTH; g = g + 1) begin
wire [MEM_WIDTH-1:0] mem_tmp;
assign mem_tmp = mem[g];
if (MASK_DISABLE) begin
assign key[g] = mem_tmp;
assign xmask[g] = {KEY_WIDTH{1'b0}};
end else begin
assign key[g] = mem_tmp[KEY_WIDTH-1-:KEY_WIDTH];
assign xmask[g] = mem_tmp[KEY_WIDTH*2-1-:KEY_WIDTH];
end
end
endgenerate
assign line_match = match;
/* Initial */
initial begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
mem[i] = 0;
end
end
/* Set */
always @(posedge clk) begin
if (rst == 1'b1) begin
active = {KEY_WIDTH{1'b0}};
end else begin
if (set_valid == 1'b1) begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
if (set_addr == i) begin
if (MASK_DISABLE) begin
mem[i] <= set_key;
end else begin
mem[i] <= {set_xmask, set_key};
end
active[i] <= ~set_clr;
end
end
end
end
end
/* Request */
always @(posedge clk) begin
if (rst == 1'b1) begin
match <= {2 ** ADDR_WIDTH{1'b0}};
end else begin
if (req_valid == 1'b1) begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
if (MASK_DISABLE) begin
match[i] <= ((key[i] ^ req_key) == 0) & active[i];
end else begin
match[i] <= ((key[i] ^ req_key & ~xmask[i]) == 0) & active[i];
end
end
end
end
end
endmodule
| 8.524502 |
module tcam_line_encoder #(
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire rst,
input wire [2**ADDR_WIDTH-1:0] line_match,
input wire line_valid,
output wire [ADDR_WIDTH-1:0] addr,
output wire addr_valid,
output wire addr_null
);
reg encode;
reg [2**ADDR_WIDTH-1:0] line;
reg [ADDR_WIDTH-1:0] addr_out;
reg valid_out;
reg null_out;
integer i;
assign addr = addr_out;
assign addr_valid = valid_out;
assign addr_null = null_out;
always @(posedge clk) begin
if (rst == 1'b1) begin
encode <= 1'b0;
end else begin
if (encode == 1'b0) begin
if (line_valid) begin
line <= line_match;
encode <= 1'b1;
end
end else begin
if (line == 0) begin
encode <= 1'b0;
end else begin
if ((line & ~(2 ** addr_out))) begin
line[addr_out] <= 1'b0;
end else begin
encode <= 1'b0;
end
end
end
end
end
always @(*) begin
addr_out = 0;
valid_out = 1'b0;
null_out = 1'b0;
if (encode == 1'b1) begin
if (line == 0) begin
valid_out = 1'b1;
null_out = 1'b1;
end else begin
for (i = 2 ** ADDR_WIDTH - 1; i >= 0; i = i - 1) begin
if (line[i] == 1'b1) begin
addr_out = i;
valid_out = 1'b1;
end
end
end
end
end
endmodule
| 7.198534 |
module tcam_lpm_bhv #(
parameter CDEP = 512, // CAM depth
parameter PWID = 32, // CAM/pattern width
parameter INOM = 1
) // binary / Initial CAM with no match (has priority over IFILE)
(
input clk, // clock
input rst, // global registers reset
input wEn, // write enable
input [`log2(CDEP)-1:0] wAddr, // write address
input [ PWID -1:0] wPatt, // write pattern
input [`log2(PWID)-1:0] wMask, // pattern mask
input [ PWID -1:0] mPatt, // patern to match
output reg match, // match indicator
output reg [ CDEP -1:0] mIndc, // match one-hot / for testing only
output reg [`log2(CDEP)-1:0] mAddr
); // matched address
// local parameters
localparam AWID = `log2(CDEP); // address width
localparam MWID = `log2(PWID); // mask width
// assign memory arrays
reg [PWID-1:0] patMem[0:CDEP-1]; // patterns memory
reg [PWID-1:0] mskMem[0:CDEP-1]; // masks memory
// local registers
reg [CDEP-1:0] vld; // valid bit
reg [PWID-1:0] wMaskMax; // temporal maximum masks
// initialize memory, with zeros if INOM or file if IFILE.
integer i;
initial
if (INOM)
for (i = 0; i < CDEP; i = i + 1) {vld[i], patMem[i], mskMem[i]} = {(2 * PWID + 1) {1'b0}};
// wMask thermometer decoder
reg [PWID-1:0] wMaskThr;
always @(*) begin
for (i = 0; i < PWID; i = i + 1) wMaskThr[i] = (wMask > i) ? 1'b0 : 1'b1;
end
integer ai, aj;
always @(posedge clk) begin
// write to memory
if (wEn) {vld[wAddr], patMem[wAddr], mskMem[wAddr]} = {1'b1, wPatt, wMaskThr};
// search memory
ai = 0;
match = ((mskMem[0] & patMem[0]) == (mskMem[0] & mPatt)) && vld[0];
// find first match
while ((!match) && (ai < (CDEP - 1))) begin
ai = ai + 1;
match = ((mskMem[ai] & patMem[ai]) == (mskMem[ai] & mPatt)) && vld[ai];
end
mAddr = ai;
wMaskMax = mskMem[ai];
// find a match with longer prefix
for (aj = ai + 1; aj < CDEP; aj = aj + 1) begin
if (((mskMem[aj] & patMem[aj])==(mskMem[aj] & mPatt)) && vld[aj] && (mskMem[aj]>wMaskMax)) begin
match = 1'b1;
mAddr = aj;
wMaskMax = mskMem[aj];
end
end
// for testing only! generate all indicators
for (i = 0; i < CDEP; i = i + 1)
mIndc[i] = ((mskMem[i] & patMem[i]) == (mskMem[i] & mPatt)) && vld[i];
end
endmodule
| 6.669445 |
module tcam_rtl
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 32
)
(
input CLK,
input WR,
input [ADDR_WIDTH-1:0] ADDR_WR,
input [DATA_WIDTH-1:0] DIN,
input [DATA_WIDTH-1:0] DIN_MASK,
`ifdef EN_TCAM_RD
input RD,
input [ADDR_WIDTH-1:0] ADDR_RD,
output [DATA_WIDTH-1:0] DOUT,
`endif
input [DATA_WIDTH-1:0] CAM_IN,
output reg MATCH,
output reg [ADDR_WIDTH-1:0] MATCH_ADDR
);
(* RAM_STYLE = "DISTRIBUTED" *)
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] mask[0:(2**ADDR_WIDTH)-1];
`ifdef EN_TCAM_RD
reg [DATA_WIDTH-1:0] rd_data;
`endif
always @(posedge CLK)
if (WR) begin
mem[ADDR_WR] <= DIN;
mask[ADDR_WR] <= DIN_MASK;
end
`ifdef EN_TCAM_RD
else if (RD) rd_data <= mem[ADDR_RD];
assign DOUT = rd_data;
`endif
reg [ADDR_WIDTH-1:0] rMatchAddr;
reg rMatch;
integer i;
always @(CAM_IN) begin
rMatch = 0;
rMatchAddr = 0;
for (i=0; i<(2**ADDR_WIDTH); i=i+1) begin
if (|((CAM_IN & mask[i]) ^ (mem[i] & mask[i])) == 0) begin rMatch = 1; rMatchAddr = i; end
end
end
always @(posedge CLK) MATCH_ADDR <= rMatchAddr;
always @(posedge CLK) MATCH <= rMatch;
endmodule
| 7.302543 |
module tcam_sdpram #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8,
parameter RAM_STYLE = "block"
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] dina,
input wire [ADDR_WIDTH-1:0] addra,
input wire [ADDR_WIDTH-1:0] addrb,
input wire wea,
output wire [DATA_WIDTH-1:0] doutb
);
(* ram_style = RAM_STYLE *)
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] readb;
integer i;
assign doutb = readb;
initial begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
ram[i] = 0;
end
end
always @(posedge clk) begin
if (wea) begin
ram[addra] <= dina;
end
readb <= ram[addrb];
end
endmodule
| 7.168283 |
module tcam_unit_test_logic #(
parameter TCAM_UNIT_ADDR = 0,
DPL_MATCH_FIELD_WIDTH = 16,
TCAM_ADDR_WIDTH = 10
) (
clk,
reset,
tcam_program_data,
tcam_program_mask,
tcam_program_addr,
tcam_program_enable,
of_match_field_data,
of_matched_addr_out,
of_matched_out
);
input clk;
input reset;
input [DPL_MATCH_FIELD_WIDTH-1:0] tcam_program_data;
input [DPL_MATCH_FIELD_WIDTH-1:0] tcam_program_mask;
input [TCAM_ADDR_WIDTH-1:0] tcam_program_addr;
input tcam_program_enable;
input [DPL_MATCH_FIELD_WIDTH-1:0] of_match_field_data;
output of_matched_addr_out;
reg [DPL_MATCH_FIELD_WIDTH-1:0] tcam_unit_data;
reg [DPL_MATCH_FIELD_WIDTH-1:0] tcam_unit_mask;
integer i;
output reg [DPL_MATCH_FIELD_WIDTH-1:0] of_matched_out;
//assign of_matched_addr_out=
/*integer j;
always@(of_matched_out)begin
for(j=0;j<DPL_MATCH_FIELD_WIDTH:j=j+1)begin
of_matched_addr_out &= of_matched_out[j]& 1'b1;
end
end
*/
assign of_matched_addr_out = &of_matched_out;
initial begin
$monitor("TIME: %g , OF_MATCHED_OUT: %x OF_MATCHED_ADDR_OUT=%b\n", $time, of_matched_out,
of_matched_addr_out);
end
always @(posedge clk) begin
if (!reset) begin
if (tcam_program_enable) begin
if (tcam_program_addr == TCAM_UNIT_ADDR) begin
tcam_unit_data <= tcam_program_data;
tcam_unit_mask <= tcam_program_mask;
end
end else begin
// $display("TCAM_MATCHING\n");
for (i = 0; i < DPL_MATCH_FIELD_WIDTH; i = i + 1) begin
if (tcam_unit_mask[i] == 1'b1) begin
// $display("TCAM_MATCHING: %g %x-TCAM_MASK=1\n",$time,i);
of_matched_out[i] <= (tcam_unit_data[i] ~^ of_match_field_data[i]);
end else begin
//$display("TCAM_MATCHING: %g %x-TCAM_MASK=0\n",$time,i);
of_matched_out[i] <= 1'b1;
end
end
end
end else begin
tcam_unit_data <= 0;
tcam_unit_mask <= 0;
of_matched_out <= 0;
end
end
endmodule
| 7.216543 |
module tcam_wrapper #(
parameter C_TCAM_ADDR_WIDTH = 4,
parameter C_TCAM_DATA_WIDTH = 16,
parameter C_TCAM_ADDR_TYPE = 0,
parameter C_TCAM_MATCH_ADDR_WIDTH = 4
) (
input CLK,
input WE,
input [C_TCAM_ADDR_WIDTH-1:0] WR_ADDR,
input [C_TCAM_DATA_WIDTH-1:0] DIN,
input [C_TCAM_DATA_WIDTH-1:0] DATA_MASK,
output BUSY,
input [ C_TCAM_DATA_WIDTH-1:0] CMP_DIN,
input [ C_TCAM_DATA_WIDTH-1:0] CMP_DATA_MASK,
output MATCH,
output [C_TCAM_MATCH_ADDR_WIDTH-1:0] MATCH_ADDR
);
localparam C_TCAM_DATA_DEPTH = 2 ** C_TCAM_ADDR_WIDTH;
cam_top #(
.C_ADDR_TYPE (C_TCAM_ADDR_TYPE),
.C_DEPTH (C_TCAM_DATA_DEPTH),
.C_FAMILY ("virtex5"),
.C_HAS_CMP_DIN (1),
.C_HAS_EN (0),
.C_HAS_MULTIPLE_MATCH (0),
.C_HAS_READ_WARNING (0),
.C_HAS_SINGLE_MATCH (0),
.C_HAS_WE (1),
.C_MATCH_RESOLUTION_TYPE(0),
.C_MEM_INIT (0),
.C_MEM_TYPE (0),
.C_REG_OUTPUTS (0),
.C_TERNARY_MODE (1),
.C_WIDTH (C_TCAM_DATA_WIDTH)
) cam_top (
.CLK (CLK),
.CMP_DATA_MASK (CMP_DATA_MASK),
.CMP_DIN (CMP_DIN),
.DATA_MASK (DATA_MASK),
.DIN (DIN),
.EN (1'b1),
.WE (WE),
.WR_ADDR (WR_ADDR),
.BUSY (BUSY),
.MATCH (MATCH),
.MATCH_ADDR (MATCH_ADDR),
.MULTIPLE_MATCH(),
.READ_WARNING (),
.SINGLE_MATCH ()
);
endmodule
| 7.224859 |
module GAN2MCOD2BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.522351 |
module GOR2MCOD1BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.517419 |
module GOR2MCOD2BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.54915 |
module MAOI222D4BWP12T30P140 (
A,
B,
C,
ZN
);
input A, B, C;
output ZN;
and (I0_out, A, B);
and (I1_out, B, C);
and (I2_out, A, C);
or (I3_out, I0_out, I1_out, I2_out);
not (ZN, I3_out);
specify
if (B == 1'b1 && C == 1'b0) (A => ZN) = (0, 0);
if (B == 1'b0 && C == 1'b1) (A => ZN) = (0, 0);
if (A == 1'b1 && C == 1'b0) (B => ZN) = (0, 0);
if (A == 1'b0 && C == 1'b1) (B => ZN) = (0, 0);
if (A == 1'b1 && B == 1'b0) (C => ZN) = (0, 0);
if (A == 1'b0 && B == 1'b1) (C => ZN) = (0, 0);
endspecify
endmodule
| 6.533397 |
module BUFFD20BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.587266 |
module GBUFFD2BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.539864 |
module INVD20BWPHVT (
I,
ZN
);
input I;
output ZN;
not (ZN, I);
specify
(I => ZN) = (0, 0);
endspecify
endmodule
| 6.534856 |
module LVLLHD2BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.542499 |
module OR2XD1BWPHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.717048 |
module HCOSCIND1BWP (
A,
CIN,
CS,
S,
CO
);
input A, CIN, CS;
output S, CO;
xor (I0_out, A, CIN);
not (I1_out, I0_out);
tsmc_mux(
S, A, I1_out, CS
);
not (I2_out, CIN);
and (CO, I2_out, A);
specify
if (CIN == 1'b0 && CS == 1'b1) (A => CO) = (0, 0);
if (CIN == 1'b0 && CS == 1'b0) (A => CO) = (0, 0);
if (A == 1'b1 && CS == 1'b1) (CIN => CO) = (0, 0);
if (A == 1'b1 && CS == 1'b0) (CIN => CO) = (0, 0);
if (CIN == 1'b1 && CS == 1'b1) (A => S) = (0, 0);
if (CIN == 1'b1 && CS == 1'b0) (A => S) = (0, 0);
if (CIN == 1'b0 && CS == 1'b0) (A => S) = (0, 0);
if (CIN == 1'b0 && CS == 1'b1) (A => S) = (0, 0);
if (A == 1'b1 && CS == 1'b1) (CIN => S) = (0, 0);
if (A == 1'b0 && CS == 1'b1) (CIN => S) = (0, 0);
if (A == 1'b0 && CIN == 1'b0) (CS => S) = (0, 0);
if (A == 1'b1 && CIN == 1'b0) (CS => S) = (0, 0);
endspecify
endmodule
| 6.678211 |
module HCOSCOND1BWP (
A,
CI,
CS,
S,
CON
);
input A, CI, CS;
output S, CON;
xor (I0_out, A, CI);
tsmc_mux(
S, A, I0_out, CS
);
and (I1_out, A, CI);
not (CON, I1_out);
specify
if (CI == 1'b1 && CS == 1'b1) (A => CON) = (0, 0);
if (CI == 1'b1 && CS == 1'b0) (A => CON) = (0, 0);
if (A == 1'b1 && CS == 1'b1) (CI => CON) = (0, 0);
if (A == 1'b1 && CS == 1'b0) (CI => CON) = (0, 0);
if (CI == 1'b1 && CS == 1'b0) (A => S) = (0, 0);
if (CI == 1'b0 && CS == 1'b1) (A => S) = (0, 0);
if (CI == 1'b0 && CS == 1'b0) (A => S) = (0, 0);
if (CI == 1'b1 && CS == 1'b1) (A => S) = (0, 0);
if (A == 1'b0 && CS == 1'b1) (CI => S) = (0, 0);
if (A == 1'b1 && CS == 1'b1) (CI => S) = (0, 0);
if (A == 1'b0 && CI == 1'b1) (CS => S) = (0, 0);
if (A == 1'b1 && CI == 1'b1) (CS => S) = (0, 0);
endspecify
endmodule
| 6.583092 |
module OR4D4BWP (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.608187 |
module AN2D1GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.512103 |
module AN2D2GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.780109 |
module AN2D4GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.670093 |
module AN2D8GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.501076 |
module AN2XD1GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.58762 |
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