code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_fifo_asyn_sync ();
wire [31:0] data_out_asyn;
wire [31:0] data_out_sync;
wire fifo_full;
wire fifo_empty_asyn;
wire fifo_empty_sync;
reg [31:0] data_in;
reg en_write;
reg en_read_asyn;
reg en_read_sync;
reg w_clk;
reg wrst_n;
reg r_clk;
reg rrst_n;
fifo_asyn_sync U1 (
data_out_asyn,
data_out_sync,
fifo_full,
fifo_empty_asyn,
fifo_empty_sync,
data_in,
en_write,
en_read_asyn,
en_read_sync,
w_clk,
wrst_n,
r_clk,
rrst_n
);
initial #1500 $stop;
initial begin
data_in = 0;
en_write = 0;
en_read_asyn = 0;
en_read_sync = 0;
w_clk = 0;
wrst_n = 0;
r_clk = 0;
rrst_n = 0;
end
initial begin
#11 wrst_n = 1;
rrst_n = 1;
end
always #5 w_clk = ~w_clk;
always #2 r_clk = ~r_clk;
initial begin
#100 en_write = 1;
#500 en_read_asyn = 1;
#200 en_read_sync = 1;
end
always @(posedge w_clk) data_in = data_in + 1;
endmodule
| 6.574519 |
module: fifo_demux2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_demux2;
// Inputs
reg clk;
reg rst;
reg [31:0] in;
reg in_valid;
reg select;
reg select_valid;
reg out0_ready;
reg out1_ready;
// Outputs
wire in_ready;
wire select_ready;
wire [31:0] out0;
wire out0_valid;
wire [31:0] out1;
wire out1_valid;
// Instantiate the Unit Under Test (UUT)
fifo_demux2 uut (
.clk(clk),
.rst(rst),
.in(in),
.in_valid(in_valid),
.in_ready(in_ready),
.select(select),
.select_valid(select_valid),
.select_ready(select_ready),
.out0(out0),
.out0_valid(out0_valid),
.out0_ready(out0_ready),
.out1(out1),
.out1_valid(out1_valid),
.out1_ready(out1_ready)
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
in <= 0;
in_valid <= 0;
select <= 0;
select_valid <= 0;
out0_ready <= 0;
out1_ready <= 0;
// start
#10 rst <= 0;
#10 select <= 1;
select_valid <= 1;
#2 select_valid <= 0;
#10 in <= 66;
in_valid <= 1;
#2 in_valid <= 0;
#10 out0_ready <= 1;
#10 out1_ready <= 1;
end
endmodule
| 6.910751 |
module tb_fifo_gate;
parameter DATA_WIDTH = 32;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data;
reg data_valid;
wire data_ready;
reg pass;
reg pass_valid;
wire pass_ready;
wire [DATA_WIDTH-1:0] result;
wire result_valid;
reg result_ready;
fifo_gate #(
.DATA_WIDTH(DATA_WIDTH)
) uut (
.clk (clk),
.rst (rst),
.data (data),
.data_valid (data_valid),
.data_ready (data_ready),
.pass (pass),
.pass_valid (pass_valid),
.pass_ready (pass_ready),
.result (result),
.result_valid(result_valid),
.result_ready(result_ready)
);
always #1 clk <= ~clk;
initial begin
clk <= 0;
rst <= 1;
data <= 10;
data_valid <= 0;
pass <= 0;
pass_valid <= 0;
result_ready <= 0;
#10 rst <= 0;
#10 data_valid <= 1;
#10 pass_valid <= 1;
#10 result_ready <= 1;
#20 pass <= 1;
#20 pass <= 0;
#20 result_ready <= 0;
end
endmodule
| 6.628012 |
module: fifo_splitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_splitter;
// Inputs
reg clk;
reg rst;
reg [31:0] data_in;
reg data_in_valid;
reg data_out1_ready;
reg data_out2_ready;
// Outputs
wire data_in_ready;
wire [31:0] data_out1;
wire data_out1_valid;
wire [31:0] data_out2;
wire data_out2_valid;
// Instantiate the Unit Under Test (UUT)
fifo_splitter2 #(
.DATA_WIDTH(32)
)
uut (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_in_ready(data_in_ready),
.data_out1(data_out1),
.data_out1_valid(data_out1_valid),
.data_out1_ready(data_out1_ready),
.data_out2(data_out2),
.data_out2_valid(data_out2_valid),
.data_out2_ready(data_out2_ready)
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
data_in <= 32'd666;
data_in_valid <= 0;
data_out1_ready <= 0;
data_out2_ready <= 0;
#10 rst <= 0;
#10 data_in_valid <= 1;
#2 data_in_valid <= 0;
#10 data_out1_ready <= 1;
#10 data_out2_ready <= 1;
#10 data_in_valid <= 1;
end
endmodule
| 6.761017 |
module tb_fifo_sum ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tx;
//reg define
reg clk;
reg rst_n;
reg rx;
reg [7:0] data_men[2499:0];
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//读取数据
initial $readmemh("E:/sources/fifo_sum/matlab/fifo_data.txt", data_men);
//生成时钟和复位信号
initial begin
clk = 1'b1;
rst_n <= 1'b0;
#30 rst_n <= 1'b1;
end
always #10 clk = ~clk;
//rx赋初值,调用rx_byte
initial begin
rx <= 1'b1;
#200 rx_byte();
end
//rx_byte
task rx_byte();
integer j;
for (j = 0; j < 2500; j = j + 1) rx_bit(data_men[j]);
endtask
//rx_bit
task rx_bit(input [7:0] data); //data是data_men[j]的值。
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0; //起始位
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7]; //上面8个发送的是数据位
9: rx <= 1'b1; //停止位
endcase
#1040;
end
endtask
//重定义defparam,用于修改参数
defparam fifo_sum_inst.uart_rx_inst.CLK_FREQ = 500000 ;
defparam fifo_sum_inst.uart_tx_inst.CLK_FREQ = 500000 ;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- fifo_sum_inst --------------
fifo_sum fifo_sum_inst (
.sys_clk (clk),
.sys_rst_n(rst_n),
.rx (rx),
.tx(tx)
);
endmodule
| 6.968116 |
module tb_fifo_width_convert ();
localparam S_RATE = 1000.0 / 100.0;
localparam M_RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_fifo_width_convert.vcd");
$dumpvars(0, tb_fifo_width_convert);
#10000000 $finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(S_RATE / 2.0) m_clk = ~m_clk;
reg reset = 1'b1;
initial #(S_RATE * 100) reset <= 1'b0;
parameter ASYNC = 1;
parameter UNIT_WIDTH = 8;
parameter S_NUM = 4;
parameter M_NUM = 8;
parameter S_DATA_WIDTH = (UNIT_WIDTH * S_NUM);
parameter M_DATA_WIDTH = (UNIT_WIDTH * M_NUM);
parameter FIFO_PTR_WIDTH = 8;
parameter FIFO_RAM_TYPE = "block";
parameter FIFO_LOW_DEALY = 0;
parameter FIFO_DOUT_REGS = 1;
parameter FIFO_S_REGS = 1;
parameter FIFO_M_REGS = 1;
genvar i;
reg [S_DATA_WIDTH-1:0] src_data;
reg src_valid;
wire src_ready;
wire [M_DATA_WIDTH-1:0] dst_data;
wire dst_valid;
reg dst_ready;
always @(posedge s_clk) begin
if (reset) begin
src_data <= 0;
src_valid <= 0;
end else begin
if (src_valid & src_ready) begin
src_data <= src_data + 1;
end
src_valid <= {$random()};
end
end
always @(posedge m_clk) begin
dst_ready <= {$random()};
end
// target
jelly_fifo_width_convert #(
.ASYNC (ASYNC),
.UNIT_WIDTH (UNIT_WIDTH),
.S_NUM (S_NUM),
.M_NUM (M_NUM),
.FIFO_PTR_WIDTH(FIFO_PTR_WIDTH),
.FIFO_RAM_TYPE (FIFO_RAM_TYPE),
.FIFO_LOW_DEALY(FIFO_LOW_DEALY),
.FIFO_DOUT_REGS(FIFO_DOUT_REGS),
.FIFO_S_REGS (FIFO_S_REGS),
.FIFO_M_REGS (FIFO_M_REGS)
) i_fifo_width_convert (
.endian(1'b0),
.s_reset (reset),
.s_clk (s_clk),
.s_data (src_data),
.s_valid (src_valid),
.s_ready (src_ready),
.s_fifo_free_count(),
.s_fifo_wr_signal (),
.m_reset (reset),
.m_clk (m_clk),
.m_data (dst_data),
.m_valid (dst_valid),
.m_ready (dst_ready),
.m_fifo_data_count(),
.m_fifo_rd_signal ()
);
endmodule
| 7.194647 |
module tb_fillEmptyCell ();
parameter STEP = 20;
reg [79:0] cell_all_in;
wire [79:0] cell_all_out;
wire full;
wire calc_done;
reg [3:0] random_pos;
fillEmptyCell filler (
.cell_all_in(cell_all_in),
.cell_all_out(cell_all_out),
.random_prob(6'b1),
.random_pos(random_pos),
.calc_done(calc_done)
);
initial begin
$dumpfile("fillEmptyCell.vcd");
$dumpvars(0, tb_fillEmptyCell);
cell_all_in = {{13{5'd1}}, {3{5'd0}}};
#STEP random_pos = 10;
#STEP random_pos = 12;
#STEP random_pos = 0;
#STEP random_pos = 1;
#STEP random_pos = 2;
#STEP random_pos = 1;
$dumpflush;
$finish;
end
endmodule
| 8.177563 |
module tb_filter ();
localparam T = 20;
parameter N = 8;
reg clk, rst_n, act;
reg [N-1:0] a, b;
wire [2*N-1:0] result;
wire [N-1:0] c_i;
integer i;
filter result_1 (
clk,
rst_n,
act,
a,
b,
result,
c_i
);
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
end
initial begin
rst_n = 1'b0;
@(posedge clk);
rst_n = 1'b1;
//@(posedge clk);
for (i = 0; i < N; i = i + 1) begin
a[i] = $random();
b[i] = $random();
end
@(negedge clk) a = 255;
b = 50;
@(negedge clk) a = 30;
b = 70;
// @(posedge clk)
// a=
end
endmodule
| 6.504595 |
module tb_filter_window;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire [7:0] Data00;
wire [7:0] Data10;
wire [7:0] Data20;
wire [7:0] Data01;
wire [7:0] Data02;
wire [7:0] Data11;
wire [7:0] Data12;
wire [7:0] Data21;
wire [7:0] Data22;
wire dout_flag;
//------------- generate system signals ------------------------------------
initial begin
sclk = 1;
s_rst_n <= 0;
din <= 'd0;
in_line_vaild <= 0;
#100 s_rst_n <= 1;
#100 in_line_vaild <= 1'b1;
data_generate();
end
always #10 sclk = ~sclk;
fliter_window fliter_window_inst (
.din (din),
.data_valuable(in_line_vaild),
.sclk (sclk),
.s_rst_n (s_rst_n),
.Data00 (Data00),
.Data10 (Data10),
.Data20 (Data20),
.Data01 (Data01),
.Data02 (Data02),
.Data11 (Data11),
.Data12 (Data12),
.Data21 (Data21),
.Data22 (Data22),
.dout_flag(dout_flag)
);
task data_generate();
integer i;
begin
for (i = 0; i < 1000; i = i + 1) begin
#20 din <= din + 1;
end
in_line_vaild <= 0;
end
endtask
endmodule
| 6.946433 |
module tb_fir ();
wire CLK_i;
wire RST_n_i;
wire [12:0] DIN_i;
wire VIN_i;
wire [12:0] H0_i;
wire [12:0] H1_i;
wire [12:0] H2_i;
wire [12:0] H3_i;
wire [12:0] H4_i;
wire [12:0] H5_i;
wire [12:0] H6_i;
wire [12:0] H7_i;
wire [12:0] H8_i;
wire [12:0] H9_i;
wire [12:0] H10_i;
wire [12:0] DOUT_i;
wire VOUT_i;
wire END_SIM_i;
clk_gen CG (
.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i)
);
data_maker SM (
.CLK(CLK_i),
.RST_n(RST_n_i),
.VOUT(VIN_i),
.DOUT(DIN_i),
.H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i),
.H4(H4_i),
.H5(H5_i),
.H6(H6_i),
.H7(H7_i),
.H8(H8_i),
.H9(H9_i),
.H10(H10_i),
.END_SIM(END_SIM_i)
);
myfir UUT (
.CLK(CLK_i),
.RST_N(RST_n_i),
.DIN(DIN_i),
.VIN(VIN_i),
.H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i),
.H4(H4_i),
.H5(H5_i),
.H6(H6_i),
.H7(H7_i),
.H8(H8_i),
.H9(H9_i),
.H10(H10_i),
.DOUT(DOUT_i),
.VOUT(VOUT_i)
);
data_sink DS (
.CLK (CLK_i),
.RST_n(RST_n_i),
.VIN (VOUT_i),
.DIN (DOUT_i)
);
endmodule
| 7.402326 |
module: FixedPoint_FIR_Filter_TM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.
// If not, see <https://www.gnu.org/licenses/>
////////////////////////////////////////////////////////////////////////////////
module tb_FIR2;
parameter No_Input = 50;
parameter N = 4; // filter order for the filter
parameter No_coeff = 8; // number of coefficients available in the LUT
parameter WI1 = 4; // Integer bitwidth for input signal samples
parameter WF1 = 5; // Fractional bitwidth for input signal samples
parameter WIC = 4; // Integer bitwidth for input coefficients
parameter WFC = 5; // Fractional bitwidth for input coefficients
// Inputs
reg [WI1+WF1-1:0] X; //input samples
reg RESET;
reg CLK;
reg test;
// Outputs
wire overflow;
wire [(WI1+WIC+N)+(WF1+WFC)-1:0] Filt_Out;
reg [WI1+WF1-1:0] X_array [0:No_Input-1];
real X_real, in2_real;
real Filt_Out_real;
// Instantiate the Unit Under Test (UUT)
FIR2 #(.N(N),
.No_coeff(No_coeff),
.WI1(WI1),
.WF1(WF1),
.WIC(WIC),
.WFC(WFC))
uut00 (.X(X), .RESET(RESET), .CLK(CLK), .test(test), .Filt_Out(Filt_Out), .overflow(overflow));
parameter ClockPeriod = 10;
initial CLK =0;
always #(ClockPeriod/2) CLK = ~CLK;
//===== Function Definition
function real FixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer i;
real retVal;
begin
retVal = 0;
for (i = 0; i < WI+WF-1; i = i+1) begin
if (in[i] == 1'b1) begin
retVal = retVal + (2.0**(i-WF));
end
end
FixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
end
endfunction
integer i;
initial begin
X = 0;
test = 0;
@(posedge CLK)RESET = 1;
$readmemb("input1.txt",X_array);
for(i=0; i<54; i=i+1) begin
@(posedge CLK) RESET = 0; X = X_array[i]; test = 1;
@(posedge CLK) test = 0;
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
$display(FixedToFloat(Filt_Out, WI1, WF1));
end
$finish;
end
always @ X X_real = FixedToFloat(X, WI1, WF1); //convert in1 to real
always @ Filt_Out Filt_Out_real = FixedToFloat(Filt_Out, (WI1+WIC+N), (WF1+WFC));//convert Out2 to real
endmodule
| 7.257827 |
module tb_fir_adv ();
parameter nb = 11, order = 10, tot_bit = (order + 1) * nb;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] DIN1_i;
wire [nb-1:0] DIN2_i;
wire [nb-1:0] DIN3_i;
wire VIN_i;
wire [tot_bit-1:0] H_i;
wire [nb-1:0] DOUT1_i;
wire [nb-1:0] DOUT2_i;
wire [nb-1:0] DOUT3_i;
wire VOUT_i;
wire END_SIM_i;
clk_gen CG (
.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i)
);
data_maker_adv DM (
.CLK(CLK_i),
.RST_n(RST_n_i),
.VOUT(VIN_i),
.DOUT1(DIN1_i),
.DOUT2(DIN2_i),
.DOUT3(DIN3_i),
.H(H_i),
.END_SIM(END_SIM_i)
);
fir_adv UUT (
.CLK(CLK_i),
.RST_n(RST_n_i),
.DIN1(DIN1_i),
.DIN2(DIN2_i),
.DIN3(DIN3_i),
.VIN(VIN_i),
.b(H_i),
.DOUT1(DOUT1_i),
.DOUT2(DOUT2_i),
.DOUT3(DOUT3_i),
.VOUT(VOUT_i)
);
data_sink_adv DS (
.CLK (CLK_i),
.RST_n(RST_n_i),
.VIN (VOUT_i),
.DIN1 (DOUT1_i),
.DIN2 (DOUT2_i),
.DIN3 (DOUT3_i)
);
endmodule
| 7.298441 |
module tb_fir;
parameter N = 8;
parameter STEP = 10;
integer count, fd;
reg [N*5-1:0] inj_data;
// Inputs
reg clk, rst;
reg [N-1:0] Xin;
reg [N-1:0] H0, H1, H2, H3;
// Outputs
wire [15:0] Yout;
// Instantiate the Unit Under Test (UUT)
//fir#(.N(N)) fir(
fir fir (
.clk (clk),
.rst (rst),
.Xin (Xin),
.H0 (H0),
.H1 (H1),
.H2 (H2),
.H3 (H3),
.Yout(Yout)
);
//Generate a clock with 10 ns clock period.
always #(STEP / 2) begin
clk <= ~clk;
end
always #(STEP) begin
count = count + 1; //to stop the simulation
end
//Initialize and apply the inputs.
initial begin
//$dumpvars(0, tb_fir);
#0 clk <= {1'b0};
rst <= {1'b0};
#(STEP) #(STEP / 2) count = 0;
rst <= {1'b1};
#(STEP) rst <= {1'b0};
$write("Start clock %d \n", count);
// Xin = {8'b00000001}; #STEP;
// Xin = {8'b00000011}; #STEP;
// Xin = {8'b00000111}; #STEP;
// Xin = {8'b00001111}; #STEP;
// Xin = {8'b00011111}; #STEP;
// Xin = {8'b00111111}; #STEP;
// Xin = {8'b01111111}; #STEP;
// Xin = {8'b11111111}; #STEP;
// Xin = {8'b11111110}; #STEP;
// Xin = {8'b11111100}; #STEP;
$dumpon;
// H0 <= {8'b00010101};
// H1 <= {8'b10101101};
// H2 <= {8'b00111111};
// H3 <= {8'b10001011};
// H0 <= $urandom%255;
// H1 <= $urandom%255;
// H2 <= $urandom%255;
// H3 <= $urandom%255;
fd = $fopen("/home/20200969/Estimation/rtl/fir_8bit/design/stimuli.txt", "r");
if (!fd) $display("could not read file");
while (!$feof(
fd
)) begin
$fscanf(fd, "%b", inj_data);
#(STEP)
// Xin <= inj_data;
Xin <= inj_data[N-1:0];
H0 <= inj_data[(N*2)-1:N];
H1 <= inj_data[(N*3)-1:(N*2)];
H2 <= inj_data[(N*4)-1:(N*3)];
H3 <= inj_data[(N*5)-1:(N*4)];
end
$dumpoff;
#(STEP) $write("------------------------\n");
$write("Stop clock %d \n", count);
$finish;
end
always #(STEP) begin
//$write("inj_data=%b ", inj_data);
$write("Xin={%b} ", Xin);
$write("Yout={%b} ", Yout);
$write("Coefficients are: H0=%b; H1=%b; H2=%b; H3=%b; \n", H0, H1, H2, H3);
$write("clk period count= %d", count);
$write("\n");
end
endmodule
| 7.064631 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.
// If not, see <https://www.gnu.org/licenses/>
////////////////////////////////////////////////////////////////////////////////
module tb_FIR_type1;
parameter WIX = 4, // integer part bitwidth for integer 1
WFX = 5, // fractional part bitwidth for integer 1
WIC=4,
WFC=5,
WIO =WIX+WIC, // integer part bitwidth for addition output (user input)
WFO =WFX+WFC, // integer part bitwidth for addition outout (user input)
N = 4;
// Inputs
reg [(WIX+WFX-1):0] X;
reg CLK;
reg RESET;
// Outputs
wire [(WIO+WFO+N-1):0] Y;
wire OF_add;
wire OF_mult;
real in1_real,in2_real,out_real;
real floatout;
function real fixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx<WI+WF-1;idx = idx+1)begin
if(in[idx] == 1'b1)begin
retVal = retVal + (2.0**(idx-WF));
end
end
fixedToFloat = retVal -(in[WI+WF-1]*(2.0**(WI-1)));
end
endfunction
// Instantiate the Unit Under Test (UUT)
FIR1 #(.WIX(WIX),.WFX(WFX),.WIC(WIC),. WFC( WFC),.WIO(WIO),.WFO(WFO),.N(N)) uut (
.X(X),
.CLK(CLK),
.RESET(RESET),
.Y(Y),
.OF_add1(OF_add1),
.OF_mult1(OF_mult1)
);
parameter clockperiod = 20;
initial CLK = 0;
always #(clockperiod/2) CLK = ~ CLK;
parameter data_width = 9;
parameter addr_width = 50;
reg [(data_width-1):0] rom [addr_width-1:0];
initial begin
$readmemb ("input1.txt",rom);
end
integer i;
initial begin
X = 0;
RESET = 1;
@(posedge CLK) RESET = 0;
for (i = 0; i <= 49 ; i = i + 1 )begin
@(posedge CLK) X = rom[i];
$display (fixedToFloat(Y,WIO,WFO));
end
$finish;
end
always @ X in1_real = fixedToFloat(X,WIX,WFX);
always @ Y out_real = fixedToFloat(Y,WIO,WFO);
endmodule
| 7.743492 |
module : tb_five_stage_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_five_stage_cache_top_factorial();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/factorial6140.vmh";
parameter TEST_NAME = "Factorial";
parameter LOG_FILE = "factorial_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
five_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00009d80) begin
$display("\ntb_five_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_five_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.648506 |
module : tb_five_stage_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_five_stage_cache_top_gcd();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/gcd1536.vmh";
parameter TEST_NAME = "Greatest Common Denominator";
parameter LOG_FILE = "gcd_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
five_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000010) begin
$display("\ntb_five_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_five_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.648506 |
module : tb_five_stage_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_five_stage_cache_top_mandelbrot();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/short_mandelbrot6140.vmh";
parameter TEST_NAME = "Mandelbrot";
parameter LOG_FILE = "mandelbrot_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
five_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h00000002) begin
$display("\ntb_five_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_five_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.648506 |
module : tb_five_stage_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Undefine macros used in this file
`ifdef REGISTER_FILE
`undef REGISTER_FILE
`endif
`ifdef CURRENT_PC
`undef CURRENT_PC
`endif
`ifdef PROGRAM_BRAM_MEMORY
`undef PROGRAM_BRAM_MEMORY
`endif
// Redefine macros used in this file
`define PROGRAM_BRAM_MEMORY dut.memory.BRAM_inst.ram
`define REGISTER_FILE dut.core.ID.base_decode.registers.register_file
`define CURRENT_PC dut.core.FI.PC_reg
module tb_five_stage_cache_top_primes();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MEM_ADDRESS_BITS = 14;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
parameter PROGRAM = "./binaries/prime_number_counter6140.vmh";
parameter TEST_NAME = "Count Primes";
parameter LOG_FILE = "count_primes_results.txt";
genvar i;
integer x;
reg clock;
reg reset;
reg start;
reg [ADDRESS_BITS-1:0] program_address;
wire [ADDRESS_BITS-1:0] PC;
reg scan;
five_stage_cache_top #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MEM_ADDRESS_BITS(MEM_ADDRESS_BITS),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) dut (
.clock(clock),
.reset(reset),
.start(start),
.program_address(program_address),
.PC(PC),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
// Initialize program memory
initial begin
for(x=0; x<2**MEM_ADDRESS_BITS; x=x+1) begin
dut.memory.BRAM_inst.ram[x] = 32'd0;
end
for(x=0; x<32; x=x+1) begin
`REGISTER_FILE[x] = 32'd0;
end
$readmemh(PROGRAM, dut.memory.BRAM_inst.ram);
end
integer start_time;
integer end_time;
integer total_cycles;
initial begin
clock = 1;
reset = 1;
scan = 0;
start = 0;
program_address = {ADDRESS_BITS{1'b0}};
#10
#1
reset = 0;
start = 1;
start_time = $time();
#1
start = 0;
end
always begin
// Check pass/fail condition every 1000 cycles so that check does not slow
// down simulation to much
#1
if(`CURRENT_PC == 32'h000000b0 || `CURRENT_PC == 32'h000000b4) begin
end_time = $time();
total_cycles = (end_time - start_time)/2;
#100 // Wait for pipeline to empty
$display("\nRun Time (cycles): %d", total_cycles);
if(`REGISTER_FILE[9] == 32'h0000000f) begin
$display("\ntb_five_stage_cache_top (%s) --> Test Passed!\n\n", TEST_NAME);
end else begin
$display("Dumping reg file states:");
$display("Reg Index, Value");
for( x=0; x<32; x=x+1) begin
$display("%d: %h", x, `REGISTER_FILE[x]);
end
$display("");
$display("\ntb_five_stage_cache_top (%s) --> Test Failed!\n\n", TEST_NAME);
end // pass/fail check
$stop();
end // pc check
end // always
endmodule
| 7.648506 |
module: FixedPoint_Adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FixedPoint_Adder;
parameter WI1 = 8; //INPUT-1 integer length
parameter WF1 = 8; //INPUT-1 fraction lengt
parameter WI2 = 8; //INPUT-2 integer length
parameter WF2 = 8; //INPUT-2 fraction length
parameter WIO = 11;//OUTPUT integer length
parameter WFO = 8;
//Inputs
reg [WI1+WF1-1:0] in1;
reg [WI2+WF2-1:0] in2;
// Outputs
wire [WIO+WFO-1:0] Out1;
//wire [6:0] Out2;
//wire [3:0]Out3;
wire overFlow1;
// wire overFlow2;
//wire overFlow3;
//Real Number Presentation
real in1_real, in2_real;
real out1_real, out2_real, out3_real;
real Floatout1, Floatout2, Floatout3;
//===== Function Definition
function real FixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer i;
real retVal;
begin
retVal = 0;
for (i = 0; i < WI+WF-1; i = i+1) begin
if (in[i] == 1'b1) begin
retVal = retVal + (2.0**(i-WF));
end
end
FixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
end
endfunction
// Instantiate the Unit Under Test (UUT)
//WIO>max(WI1,WI2) , WFO>max(WF1,WF2)
FixedPoint_Adder #(.WI1(WI1),
.WF1(WF1),
.WI2(WI2),
.WF2(WF2),
.WIO(WIO),
.WFO(WFO))
uut01 (.in1(in1), .in2(in2), .overFlow(overFlow1), .FixedPoint_Add_Out(Out1));//Output1
/* //WIO=max(WI1,WI2), WFO < max(WF1,WF2)
FixedPoint_Adder #(.WI1(3),
.WF1(4),
.WI2(4),
.WF2(3),
.WIO(4),
.WFO(3))
uut02 (.in1(in1), .in2(in2), .overFlow(overFlow2), .FixedPoint_Add_Out(Out2));
//WIO<min(WI1,WI2), WFO <min(WF1,WF2)
FixedPoint_Adder #(.WI1(3),
.WF1(4),
.WI2(4),
.WF2(3),
.WIO(2),
.WFO(2))
uut03 (.in1(in1), .in2(in2), .overFlow(overFlow3), .FixedPoint_Add_Out(Out3));
*/
initial begin
// Initialize Inputs
// in2 = 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
// in1 = 40'b1111_1111_1000_0000_0000_0000_0000_0000_0000_0000;
// // Wait 100 ns for global reset to finish
// #100;
// in1 = 9'b0111_1111_0;
//// in2 = 9'b1000_0001_0;
// in2 = 9'b0111_1111_0;
in1 = 16'b0000_0001_1000_0000;
in2 = 16'b0000_0001_1000_0000;
#100;
/*
in1 = 7'b111_0000;
in2 = 7'b0110_000;
// Wait 100 ns for global reset to finish
#100;
in1 = 7'b100_0000;
in2 = 7'b0011_000;
// Wait 100 ns for global
#100;*/
$finish;
end
always @ in1 in1_real = FixedToFloat(in1, WI1, WF1); //convert in1 to real
always @ in2 in2_real = FixedToFloat(in2, WI2, WF2); //convert in2 to real
always @ Out1 out1_real = FixedToFloat(Out1, WIO, WFO);//convert Out2 to real
always @ (in1_real or in2_real) Floatout1 = in1_real + in2_real;//Ideal Output
// always @ Out2 out2_real = FixedToFloat(Out2, 4, 3);//convert Out2 to real
// always @ (in1_real or in2_real) Floatout2 = in1_real + in2_real;//Ideal Output
// always @ Out3 out3_real = FixedToFloat(Out3, 2, 2);//convert Out3 to real
// always @ (in1_real or in2_real) Floatout3 = in1_real + in2_real;//Ideal Output
endmodule
| 6.79281 |
module tb_fjmem ();
parameter adr_width = 24;
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
wire [adr_width-1:0] flash_adr;
wire [15:0] flash_d;
wire flash_oe_n;
wire flash_we_n;
reg [15:0] flash_do;
assign flash_d = (flash_oe_n) ? 16'bz : flash_do;
reg jtag_tck;
reg jtag_rst;
reg jtag_update;
reg jtag_shift;
reg jtag_tdi;
wire jtag_tdo;
fjmem_core #(
.adr_width(adr_width)
) core (
.sys_clk(clk),
.sys_rst(rst),
/* jtag */
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
/* flash */
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n)
);
task jtagclock;
input integer n;
begin
repeat (n) begin
jtag_tck = 1'b0;
#50;
jtag_tck = 1'b1;
#50;
jtag_tck = 1'b0;
end
end
endtask
task jtagshift;
input integer sw;
input [63:0] din;
output [63:0] dout;
begin
repeat (sw) begin
jtag_shift = 1'b1;
jtag_tck = 1'b0;
{din[62:0], jtag_tdi} = din;
#50;
jtag_tck = 1'b1;
dout = {dout[61:0], jtag_tdo};
#50;
jtag_tck = 1'b0;
jtag_shift = 1'b0;
end
end
endtask
task jtagupdate;
begin
jtag_update = 1'b0;
jtag_tck = 1'b0;
#50;
jtag_update = 1'b1;
jtag_tck = 1'b1;
#50;
jtag_update = 1'b0;
jtag_tck = 1'b0;
end
endtask
task jtagreset;
begin
jtag_rst = 1'b0;
jtag_tck = 1'b0;
#50;
jtag_rst = 1'b1;
jtag_tck = 1'b1;
#50;
jtag_rst = 1'b0;
jtag_tck = 1'b0;
end
endtask
parameter IDLE = 3'b000;
parameter DETECT = 3'b111;
parameter QUERY = 3'b110;
parameter READ = 3'b001;
parameter WRITE = 3'b010;
task fjmemcommand;
input [2:0] cmd;
input block;
input [23:0] adr;
input data;
reg [44:0] din;
reg [44:0] dout;
begin
din = {data, adr, block, 1'b0, cmd};
$display("din=%x", din);
jtagshift(45, din, dout);
jtagupdate();
$display("dout=%x", dout);
$display("data=%x adr=%x block=%x ack=%x cmd=%x", dout[44:29], dout[28:5], dout[4], dout[3],
dout[2:0]);
end
endtask
always @(negedge flash_oe_n) begin
$display("Flash read access @%x: %x", flash_adr, flash_adr[15:0]);
#110 flash_do = flash_adr[15:0];
end
always @(negedge flash_we_n) begin
$display("Flash write access @%x: %x", flash_adr, flash_d[15:0]);
end
reg [44:0] data_r;
always begin
$dumpfile("fjmem.vcd");
$dumpvars();
/* Reset / Initialize our logic */
rst = 1'b1;
jtag_tck = 1'b0;
jtag_rst = 1'b0;
jtag_update = 1'b0;
jtag_shift = 1'b0;
jtag_tdi = 1'b0;
#10;
rst = 1'b0;
jtagreset();
fjmemcommand(DETECT, 0, 0, 0);
fjmemcommand(IDLE, 0, 0, 0);
$finish;
end
endmodule
| 7.208186 |
module: FlashingLED
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FlashingLED;
// Inputs
reg clk;
reg rst;
// Note: CLK must be defined as a reg when using this method
// Outputs
wire led_out;
// Instantiate the Unit Under Test (UUT)
FlashingLED uut (
.clk(clk),
.rst(rst),
.led_out(led_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 0;
end
// PERIOD = <value>
parameter PERIOD = 20;
// Generate the clock
always begin
clk = 1'b0;
#(PERIOD/2) clk = 1'b1;
#(PERIOD/2);
end
endmodule
| 7.230286 |
module tb_flash_be_ctrl ();
//wire define
wire cs_n; //Flash片选信号
wire sck; //Flash串行时钟
wire mosi; //Flash主输出从输入信号
//reg define
reg sys_clk; //模拟时钟信号
reg sys_rst_n; //模拟复位信号
reg key; //模拟全擦除触发信号
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
key <= 1'b0;
#100 sys_rst_n <= 1'b1;
#1000 key <= 1'b1;
#20 key <= 1'b0;
end
always #10 sys_clk <= ~sys_clk; //模拟时钟,频率50MHz
//写入Flash仿真模型初始值(全F)
defparam memory.mem_access.initfile = "initmemory.txt";
//------------- flash_be_ctrl_inst -------------
flash_be_ctrl flash_be_ctrl_inst (
.sys_clk (sys_clk), //输入系统时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.key (key), //按键输入信号,1bit
.sck (sck), //输出串行时钟,1bit
.cs_n(cs_n), //输出片选信号,1bit
.mosi(mosi) //输出主输出从输入数据,1bit
);
//------------- memory -------------
m25p16 memory (
.c (sck), //输入串行时钟,频率12.5Mhz,1bit
.data_in(mosi), //输入串行指令或数据,1bit
.s (cs_n), //输入片选信号,1bit
.w (1'b1), //输入写保护信号,低有效,1bit
.hold (1'b1), //输入hold信号,低有效,1bit
.data_out() //输出串行数据
);
endmodule
| 7.521548 |
module tb_flash_pp_ctrl ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg sys_clk;
reg sys_rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 0;
sys_rst_n <= 0;
key <= 0;
#100 sys_rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 sys_clk <= ~sys_clk;
//写入Flash仿真模型初始值(全F)
defparam memory.mem_access.initfile = "initmemory.txt";
//------------- flash_pp_ctrl_inst -------------
flash_pp_ctrl flash_pp_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (key), //按键输入信号
.sck (sck), //串行时钟
.cs_n(cs_n), //片选信号
.mosi(mosi) //主输出从输入数据
);
//------------- memory -------------
m25p16 memory (
.c (sck), //输入串行时钟,频率12.5Mhz,1bit
.data_in(mosi), //输入串行指令或数据,1bit
.s (cs_n), //输入片选信号,1bit
.w (1'b1), //输入写保护信号,低有效,1bit
.hold (1'b1), //输入hold信号,低有效,1bit
.data_out() //输出串行数据
);
endmodule
| 7.767329 |
module tb_flash_se_ctrl ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg sys_clk;
reg sys_rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 0;
sys_rst_n <= 0;
key <= 0;
#100 sys_rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 sys_clk <= ~sys_clk;
//写入Flash仿真模型初始值(全F)
defparam memory.mem_access.initfile = "initmemory.txt";
//------------- flash_se_ctrl_inst -------------
flash_se_ctrl flash_se_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (key), //按键输入信号
.sck (sck), //串行时钟
.cs_n(cs_n), //片选信号
.mosi(mosi) //主输出从输入数据
);
//------------- memory -------------
m25p16 memory (
.c (sck), //输入串行时钟,频率12.5Mhz,1bit
.data_in(mosi), //输入串行指令或数据,1bit
.s (cs_n), //输入片选信号,1bit
.w (1'b1), //输入写保护信号,低有效,1bit
.hold (1'b1), //输入hold信号,低有效,1bit
.data_out() //输出串行数据
);
endmodule
| 8.149322 |
module tb_flip_flop;
reg clk, rst_n, d;
wire q;
// Instantiate counter
flip_flop ff0 (
.clk(clk),
.rst_n(rst_n),
.d(d),
.q(q)
);
// set up the clock period
always #5 clk = ~clk;
initial begin
// initialize clock and reset
clk <= 0;
rst_n <= 0;
#20 rst_n <= 1;
d <= 0; // disable reset and initialize d to zero
#20 d <= 1; // put value in
#20 d <= 0; // reset value
#20 d <= 1; // put value in
#20 rst_n <= 0; // reset flip-flop
#20 $finish;
end
endmodule
| 8.404567 |
module tb_float_step ();
localparam RATE = 1000.0 / 200.0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
initial begin
$dumpfile("tb_top.vcd");
$dumpvars(0, tb_float_step);
#10000 $finish;
end
function [31:0] double_to_float(input [63:0] in_double);
begin
double_to_float[31] = in_double[63];
double_to_float[30:23] = in_double[63:52] - 1023 + 127;
double_to_float[22:0] = in_double[51:29];
end
endfunction
function [63:0] float_to_double(input [31:0] in_float);
begin
float_to_double = 0;
float_to_double[63] = in_float[31];
float_to_double[62:52] = in_float[30:23] - 127 + 1023;
float_to_double[51:29] = in_float[22:0];
end
endfunction
reg [31:0] param_init;
reg [31:0] param_step;
reg set_param = 1'b0;
reg increment = 1'b0;
reg valid = 1'b0;
wire [31:0] out_data;
wire out_valid;
jelly_float_step i_float_step (
.clk (clk),
.stage_cke ({6{1'b1}}),
.param_init(param_init),
.param_step(param_step),
.set_param(valid & set_param),
.increment(valid & increment),
.out_data(out_data)
);
initial begin
// $display("%f %f", 1.0, $bitstoreal(float_to_double(double_to_float($realtobits(1.0)))) );
// $display("%f %f", 1.2, $bitstoreal(float_to_double(double_to_float($realtobits(1.2)))) );
// $display("%f %f", 1.3, $bitstoreal(float_to_double(double_to_float($realtobits(1.3)))) );
// $display("%f %f", -1.4, $bitstoreal(float_to_double(double_to_float($realtobits(-1.4)))) );
#200 @(negedge clk) param_init = double_to_float($realtobits(1.25));
param_step = double_to_float($realtobits(-0.25));
set_param = 1'b1;
increment = 1'b1;
valid = 1'b1;
@(negedge clk) param_init = 32'hxxxx_xxxx;
param_step = 32'hxxxx_xxxx;
set_param = 1'b0;
increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk) increment = 1'b1;
valid = 1'b1;
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
@(negedge clk)
increment = 1'b0;
valid = 1'b0;
@(negedge clk) @(negedge clk) #1000 $finish;
end
always @(posedge clk) begin
if (out_valid) begin
$display("%f", $bitstoreal(float_to_double(out_data)));
end
end
endmodule
| 6.810774 |
module.
//------------------------------------------------------------------
module tb_fltcpu();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
parameter DEBUG_CORE = 0;
parameter DEBUG_TOP = 0;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
wire tb_mem_cs;
wire [3 : 0] tb_mem_we;
wire [31 : 0] tb_mem_address;
reg [31 : 0] tb_mem_rd_data;
wire [31 : 0] tb_mem_wr_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
fltcpu dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.mem_cs(tb_mem_cs),
.mem_we(tb_mem_we),
.mem_address(tb_mem_address),
.mem_rd_data(tb_mem_rd_data),
.mem_wr_data(tb_mem_wr_data)
);
//----------------------------------------------------------------
// clk_gen
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// dump_dut_state()
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 32'h0;
error_ctr = 32'h0;
tc_ctr = 32'h0;
tb_clk = 0;
tb_reset_n = 0;
end
endtask // init_dut
//----------------------------------------------------------------
// display_test_result()
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully.", tc_ctr);
end
else
begin
$display("*** %02d test cases completed.", tc_ctr);
$display("*** %02d errors detected during testing.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// cpu_test
//----------------------------------------------------------------
initial
begin : cpu_test
$display(" -- Testbench for CPU started --");
init_sim();
reset_dut();
display_test_result();
$display(" -- Testbench for cpu done. --");
$finish;
end // cpu_test
endmodule
| 6.659433 |
module tb_forth1;
reg sys_clk_i;
reg sys_rst_i;
reg io_rd;
reg io_wr;
reg [15:0] io_din;
reg [15:0] io_addr;
reg [15:0] io_dout;
initial begin
$dumpfile("vcd/forth1.vcd");
$dumpvars(0, tb_forth1);
end
initial begin
$from_myhdl(io_din, sys_clk_i, sys_rst_i);
$to_myhdl(io_dout, io_addr, io_rd, io_wr);
end
//wire sys_rst_i;
j1 dut_j1 (
sys_clk_i,
sys_rst_i,
io_din,
io_addr,
io_dout,
io_rd,
io_wr
);
endmodule
| 6.55735 |
module tb_forwarder ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
wire of_lookup_req;
wire [242:0] of_lookup_data;
wire of_lookup_ack;
wire of_lookup_err;
wire [3:0] of_lookup_fwd_port;
lookupflow #(
.NPORT(4'h4)
) lookupflow_tb (
.sys_clk(sys_clk)
, .sys_rst(sys_rst)
, .of_lookup_req(of_lookup_req)
, .of_lookup_data(of_lookup_data)
, .of_lookup_ack(of_lookup_ack)
, .of_lookup_err(of_lookup_err)
, .of_lookup_fwd_port(of_lookup_fwd_port)
);
reg [8:0] rx_dout;
reg rx_empty;
wire rx_rd_en;
wire [7:0] port0tx_din, port1tx_din, port2tx_din, port3tx_din, nic_din;
reg port0tx_full, port1tx_full, port2tx_full, port3tx_full, nic_full;
wire port0tx_wr_en, port1tx_wr_en, port2tx_wr_en, port3tx_wr_en, nic_wr_en;
forwarder #(
.NPORT(4'h4)
, .PORT_NUM(4'h0)
) forwarder_tb (
.sys_rst(sys_rst)
, .sys_clk(sys_clk)
, .rx_dout (rx_dout)
, .rx_empty(rx_empty)
, .rx_rd_en(rx_rd_en)
, .port0tx_din (port0tx_din)
, .port0tx_full (port0tx_full)
, .port0tx_wr_en(port0tx_wr_en)
, .port1tx_din (port1tx_din)
, .port1tx_full (port1tx_full)
, .port1tx_wr_en(port1tx_wr_en)
, .port2tx_din (port2tx_din)
, .port2tx_full (port2tx_full)
, .port2tx_wr_en(port2tx_wr_en)
, .port3tx_din (port3tx_din)
, .port3tx_full (port3tx_full)
, .port3tx_wr_en(port3tx_wr_en)
, .nic_din (nic_din)
, .nic_full (nic_full)
, .nic_wr_en(nic_wr_en)
, .of_lookup_req(of_lookup_req)
, .of_lookup_data(of_lookup_data)
, .of_lookup_ack(of_lookup_ack)
, .of_lookup_err(of_lookup_err)
, .of_lookup_fwd_port(of_lookup_fwd_port)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge sys_clk) begin
if (rx_rd_en == 1'b1) $display("empty: %x dout: %x", rx_empty, rx_dout);
end
reg [11:0] counter;
reg [8:0] rom[0:511];
always #1{rx_empty, rx_dout} <= rom[counter];
always @(posedge phy_tx_clk) begin
if (rx_rd_en == 1'b1) counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_forwarder);
$readmemh("./phy_pingto5hosts.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#10000;
$finish;
end
endmodule
| 7.249102 |
module: FPadder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.
// If not, see <https://www.gnu.org/licenses/>
////////////////////////////////////////////////////////////////////////////////
module tb_FPadder;
parameter WI1 = 8, WF1 = 32, WI2 = 8, WF2 = 32, WIO = 8, WFO = 32;
// Inputs
reg [WI1+WF1-1 : 0] A;
reg [WI2+WF2-1 : 0] B;
// Outputs
wire [WIO+WFO-1 : 0] out;
wire overflow;
//real number Presentation
real in1_real,in2_real,out_real;
real floatout;
//------------------------Function Definition to convert fixed point to floating point number------------//
function real fixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx<WI+WF-1;idx = idx+1)begin
if(in[idx] == 1'b1)begin
retVal = retVal + (2.0**(idx-WF));
end
end
fixedToFloat = retVal -(in[WI+WF-1]*(2.0**(WI-1)));
end
endfunction
// Instantiate the Unit Under Test (UUT)
FPadder #(.WI1(WI1),.WF1(WF1),.WI2(WI2),.WF2(WF2),.WFO(WFO),.WIO(WIO)) uut (
.A(A),
.B(B),
.out(out),
.overflow(overflow)
);
initial begin
// Initialize Inputs
A = 40'b11111111_10000000000000000000000000000000;
B = 40'b00000000_00000000000000000000000000000000;
#100;
A = 40'b00000000_00000000000000000000000000000000;
B = 40'b11111111_10000000000000000000000000000000;
#100;
$finish;
// Add stimulus here
end
always @ A in1_real = fixedToFloat(A,WI1,WF1);
always @ B in2_real = fixedToFloat(B,WI2,WF2);
always @ out out_real = fixedToFloat(out,WIO,WFO);
always @ (in1_real or in2_real) floatout=in1_real + in2_real;
endmodule
| 7.372755 |
module tb_fpmul ();
wire CLK_i;
wire [31:0] DATA_i;
wire [31:0] RES_i;
clk_gen CG (.CLK(CLK_i));
data_maker SM (
.CLK (CLK_i),
.DATA(DATA_i)
);
FPmul UUT (
.CLK (CLK_i),
.FP_A(DATA_i),
.FP_B(DATA_i),
.FP_Z(RES_i)
);
endmodule
| 6.907347 |
module FPMult_tb;
// Inputs
reg clk;
reg rst;
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] result;
wire [4:0] flags;
integer i;
// Instantiate the Unit Under Test (UUT)
FPMult_reduced uut (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.result(result),
.flags(flags)
);
always begin
#5 clk = ~clk;
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
a = 0;
a = 0;
// Wait 10 ns for global reset to finish
#10;
// Add stimulus here
// TEST #1
// -6.55504723008 + 0.156205364091 = -1.02393353921
// Expected Z = 10111111100000110001000001000001
// 10111111100000110001000001000010
#10 a = 32'b11000000110100011100001011110010;
b = 32'b00111110000111111111010001001101;
$display("%b", result);
// TEST #2
// 3.0960619702 + 8.77542136981 = 27.1692483755
// Expected Z = 01000001110110010101101010011111
// 01000001110110010101101010011111
#10 a = 32'b0_1000_0000_10001100010010111100001;
b = 32'b0_1000_0010_00011000110100000100000;
$display("%b", result);
// TEST #3
// 8.72801516902 + 8.66712318573 = 75.6467826368
// Expected Z = 01000010100101110100101100100111
// 01000010100101110100101100100111
#10 a = 32'b01000001000010111010010111110011;
b = 32'b01000001000010101010110010001001;
$display("%b", result);
// TEST #4
// -3.92298069694 - 1.38250350354 = -5.42353455784
// Expected Z = 11000000101011011000110110011000
#10 a = 32'b11000000011110110001001000011110;
b = 32'b00111111101100001111010111100000;
$display("%b", result);
// TEST #5
// 3.92420946435 - 0.852892795309 = 3.34692997943
// Expected Z = 01000000010101100011010000011010
#10 a = 32'b01000000011110110010011000111111;
b = 32'b00111111010110100101011100101111;
$display("%b", result);
// TEST #6
// -3.65982412483 + 1.64573535265 = -6.02310194671
// Expected Z = 11000000110000001011110101000000
#10 a = 32'b11000000011010100011101010001111;
b = 32'b00111111110100101010011101110101;
$display("%b", result);
// TEST #7
// 4.37288448465 + 4.75615002457 = 20.7980946491
// Expected Z = 01000001101001100110001001111111
#10 a = 32'b01000000100010111110111010101011;
b = 32'b01000000100110000011001001100010;
$display("%b", result);
// TEST #8
// 6.6687684133 - -4.80960037793 = -32.074111081
// Expected Z = 01000010000000000100101111100100
#10 a = 32'b01000000110101010110011010001101;
b = 32'b11000000100110011110100000111111;
$display("%b", result);
// TEST #9
// 2.1624545611 - 1.72175603989 = 3.72321920156
// Expected Z = 01000000011011100100100100111001
#10 a = 32'b01000000000010100110010110101000;
b = 32'b00111111110111000110001010000000;
$display("%b", result);
// TEST #10
// 1.21525685799 - -1.69553124072 = -2.06050596822
// Expected Z = 01000000000000111101111101010100
#10 a = 32'b00111111100110111000110110001001;
b = 32'b10111111110110010000011100101011;
$display("%b", result);
for (i = 0; i <= 20; i = i + 1) begin
#10 $display("%b", result);
end
#100 #10 $finish;
end
endmodule
| 7.463027 |
module tb_fpmul ();
wire CLK_i;
wire RST_n_i;
wire [31:0] DIN_i;
wire [31:0] DOUT_i;
clk_gen CG (
.CLK (CLK_i),
.RST_N(RST_n_i)
);
data_maker SM (
.CLK (CLK_i),
.RST_N(RST_n_i),
.DATA (DIN_i)
);
FPmul UUT (
.clk (CLK_i),
.rst_n(RST_n_i),
.FP_A (DIN_i),
.FP_B (DIN_i),
.FP_Z (DOUT_i)
);
data_sink DS (
.CLK (CLK_i),
.RST_N(RST_n_i),
.DIN (DOUT_i)
);
endmodule
| 6.907347 |
module tb_fpu;
reg clk;
reg [1:0] rmode;
reg [2:0] fpu_op;
reg [31:0] opa, opb;
wire [31:0] out;
wire inf, snan, qnan;
wire ine;
wire overflow, underflow;
wire zero;
wire div_by_zero;
fpu dut_fpu_0
(
.clk (clk),
.rmode(rmode),
.fpu_op(fpu_op),
.opa(opa),
.opb(opb),
.out(out),
.inf(inf),
.snan(snan),
.qnan(qnan),
.ine(ine),
.overflow(overflow),
.underflow(underflow),
.zero(zero),
.div_by_zero(div_by_zero)
);
localparam CLK_PERIOD = 50;
always #(CLK_PERIOD/2) clk=~clk;
initial begin
dumpfile("tb_fpu.vcd");
dumpvars(0, tb_fpu);
end
initial begin
clk = 1;
#100;
opa = 'd55;
opb = 'd55;
rmode = 'd0;
fpu_op = 'd0;
end
endmodule
| 6.534917 |
module tb_fpu_normalizer ();
// Testbench for fpu_normalizer
reg [23:0] mantissa;
reg [7:0] exponent;
reg [22:0] normalized_mantissa;
reg [7:0] normalized_exponent;
wire overflow;
wire underflow;
fpu_normalizer fpu_normalizer_inst (
.mantissa(mantissa),
.exponent(exponent),
.normalized_mantissa(normalized_mantissa),
.normalized_exponent(normalized_exponent),
.overflow(overflow),
.underflow(underflow)
);
initial begin
// Test 1
mantissa = 24'b000000000000000000000001;
exponent = 0;
#100;
// Test 2
mantissa = 24'b000000000000000000000001;
exponent = 1;
#100;
// Test 3
mantissa = 24'b000000000000000000000010;
exponent = 2;
#100;
// Test 4
mantissa = 24'b000100000000000000000000;
exponent = 3;
#100;
// Test 5
mantissa = 24'b010000000000000000000000;
exponent = 4;
#100;
// Test 6
mantissa = 24'b100000000000000000000000;
exponent = 5;
#100;
$finish;
end
endmodule
| 6.875816 |
module tb_fpu_sp_comparator ();
// Inputs
reg signed [7:0] a;
reg signed [7:0] b;
// Outputs
wire unsigned [7:0] difference;
wire sign;
wire overflow;
// Instantiate the Unit Under Test (UUT)
fpu_comparator #(
.size(8)
) uut (
.a(a),
.b(b),
.difference(difference),
.sign(sign),
.overflow(overflow)
);
initial begin
$display("\ta \t b \t diff \t exp_d \t sign \t exp_s \t of \t exp_of");
$display("---------------------------------------------------------------------");
a = 0;
b = 0;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 0, sign, 0, overflow, 0
);
a = 0;
b = 1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 1, sign, 1, overflow, 0
);
a = 1;
b = 0;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 1, sign, 0, overflow, 0
);
a = 1;
b = 1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 0, sign, 0, overflow, 0
);
a = 0;
b = 2;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 2, sign, 1, overflow, 0
);
a = 2;
b = 0;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 2, sign, 0, overflow, 0
);
a = -1;
b = 0;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 1, sign, 1, overflow, 0
);
a = 0;
b = -1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 1, sign, 0, overflow, 0
);
a = -1;
b = 1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 2, sign, 1, overflow, 0
);
a = 1;
b = -1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 2, sign, 0, overflow, 0
);
a = 0;
b = 127;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 127, sign, 1, overflow, 0
);
a = 127;
b = 0;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 127, sign, 0, overflow, 0
);
a = -127;
b = 1;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 128, sign, 1, overflow, 1
);
a = 2;
b = -127;
#10
$display(
"%d \t %d \t %d \t %d \t %d \t %d \t %d \t %d", a, b, difference, 128, sign, 0, overflow, 1
);
$stop;
end
endmodule
| 6.663318 |
module tb_fractionaln;
// fractionaln Parameters
parameter PERIOD = 10;
parameter P_WIDTH = 5;
parameter S_WIDTH = 3;
parameter INT_WIDTH = 8;
parameter FRAC_WIDTH = 24;
// fractionaln Inputs
reg Fin = 0;
reg rst_n = 0;
reg [ INT_WIDTH-1:0] Integer = 0;
reg [FRAC_WIDTH-1:0] Fraction = 0;
reg clk = 0;
reg clk_div = 0;
// fractionaln Outputs
wire Fout;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
forever #(PERIOD * 120.5 / 2) clk_div = ~clk_div;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
fractionaln #(
.P_WIDTH (P_WIDTH),
.S_WIDTH (S_WIDTH),
.INT_WIDTH (INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) u_fractionaln (
.Fin (clk),
.rst_n (rst_n),
.Integer (Integer[INT_WIDTH-1:0]),
.Fraction(Fraction[FRAC_WIDTH-1:0]),
.Fout(Fout)
);
initial begin
Integer = 8'd120;
Fraction = 24'd8388607; // 2^23 - 1 (0.5)
#(PERIOD * 120 * 10000);
$finish;
end
integer dout_file;
initial begin
dout_file = $fopen(
"/home/EDA/vsim/Fractional-N-DIV/delta-sigma/tb/data.txt"); //打开所创建的文件
if (dout_file == 0) begin
$display("can not open the file!"); //创建文件失败，显示can not open the file!
$stop;
end
end
always @(posedge u_fractionaln.u_mash111.clk) begin
$fdisplay(dout_file, "%d", $signed(u_fractionaln.u_mash111.y_o)); //保存有符号数据
end
// always @(posedge u_fractionaln.u_mash111.clk) begin
// $fdisplay(dout_file,"%b",Fout); //使能信号有效，每来一个时钟，写入到所创建的文件中
// end
// /tb_fractionaln/u_fractionaln/u_mash111/y_o
endmodule
| 7.695816 |
module tb_frameGenerator;
localparam LEN_TX_DATA = 64;
localparam LEN_TX_CTRL = 8;
reg tb_clock;
reg tb_reset;
wire [LEN_TX_DATA-1 : 0] tb_o_tx_data;
wire [LEN_TX_CTRL-1 : 0] tb_o_tx_ctrl;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
#1 tb_reset = 1'b1;
#1 tb_reset = 1'b0;
#1000000 $finish;
end
always #1 tb_clock = ~tb_clock;
frameGenerator #() test_frameGenerator (
.i_clock (tb_clock),
.i_reset (tb_reset),
.o_tx_data(tb_o_tx_data),
.o_tx_ctrl(tb_o_tx_ctrl)
);
endmodule
| 6.714946 |
module tb_frame_sync_generator;
reg clk;
reg clk_lp;
wire frame_sync_output;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
frame_sync_generator ins1 (
.lp_clk_i(clk_lp),
.out_clk_i(clk),
.frame_sync_o(frame_sync_output)
);
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk;
end
task send_frame;
reg [16:0] i;
begin
for (i = 0; i < 2000; i = i + 1) begin
if (i > 1000) begin
clk_lp = 1;
end
#2;
end
end
endtask
initial begin
clk_lp = 0;
send_frame();
clk_lp = 0;
#1000;
send_frame();
clk_lp = 0;
#1000;
send_frame();
end
endmodule
| 6.736331 |
module tb_freq ();
/*
reg sclk;
reg rst_n;
reg pulse;
wire [31:0] cnt_clk;
wire [31:0] cnt_squ;
wire [31:0] cnt_pulse;
initial sclk = 1;
always #5 sclk = ~sclk;
initial begin
rst_n = 0;
#100
rst_n = 1;
end
reg [31:0] cnt = 0;
always @(posedge sclk or negedge rst_n) begin
if(!rst_n) cnt <= 0;
else if(cnt == 35) cnt <= 0;
else cnt <= cnt + 1;
end
always@(posedge sclk or negedge rst_n) begin
if(!rst_n) pulse <= 0;
else if(cnt == 19) pulse <= 0;
else if(cnt == 34) pulse <= 1;
end
//--------------------------------//
Freq_measure Freq_measure_inst0(
.clk_100M (sclk),
.square (pulse),
.cnt_clk (cnt_clk),
.cnt_squ (cnt_squ),
.cnt_pulse (cnt_pulse)
);
//--------------------------------//
*/
reg sclk;
reg rst_n;
reg pulse_r0;
reg pulse_r1;
wire [31:0] cnt_time;
initial sclk = 1;
always #5 sclk = ~sclk;
initial begin
rst_n = 0;
pulse_r0 = 0;
pulse_r1 = 0;
#100 rst_n = 1;
#500 pulse_r0 <= 1;
#1500 pulse_r1 <= 1;
end
//---------------------//
Time_measure Time_measure_inst0 (
.clk(sclk),
.rst_n(rst_n),
.squ_r0(pulse_r0),
.squ_r1(pulse_r1),
.cnt_time(cnt_time)
);
endmodule
| 7.246341 |
module testbench;
reg inpClk, reset;
wire S;
FreqDiv FD1 (
inpClk,
reset,
S
);
initial begin
inpClk = 1'b1; // 1
reset = 1'b0; // 0
#20 reset = 1'b1; // 1
#10 reset = 1'b0; // 0
end
always begin
#10 inpClk = ~inpClk;
end
endmodule
| 7.015571 |
module tb_freq_div ();
reg rst, inclk;
wire sec_clk, min_clk, hour_clk;
freq_div test_feq (
rst,
inclk,
sec_clk,
min_clk,
hour_clk
);
initial begin
inclk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 inclk = ~inclk;
end
endmodule
| 7.159323 |
module tb_freq_meter ();
//********************************************************************//
//****************** Parameter And Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的时钟输入
wire ds; //串行数据输入
wire oe;
//reg define
reg sys_clk;
reg sys_rst_n;
reg clk_test;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//时钟、复位、待检测时钟的生成
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
#500 clk_test = 1'b1;
end
always #10 sys_clk = ~sys_clk; //50MHz系统时钟
always #100 clk_test = ~clk_test; //5MHz待检测时钟
//重定义软件闸门计数时间,缩短仿真时间
defparam freq_meter_inst.freq_meter_calc_inst.CNT_GATE_S_MAX = 240 ;
defparam freq_meter_inst.freq_meter_calc_inst.CNT_RISE_MAX = 40 ;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- freq_meter_inst -------------
freq_meter freq_meter_inst (
.sys_clk (sys_clk), //系统时钟,频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.clk_test (clk_test), //待检测时钟
.clk_out(clk_out), //生成的待检测时钟
.stcp (stcp), //输出数据存储寄时钟
.shcp (shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe)
);
endmodule
| 8.138754 |
module TB_from_controller ();
wire clk;
reg reset;
wire [7:0] from_data;
wire [6:0] from_addr;
wire from_clk;
reg wb_cyc_i, wb_stb_i, wb_we_i;
reg [15:0] wb_adr_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
wire wb_ack_o;
from_controller from_controller (
.wb_clk_i (clk),
.wb_rst_i (reset),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_we_i (wb_we_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.from_clk (from_clk),
.from_addr(from_addr),
.from_data(from_data)
);
reg [7:0] clk_counter;
initial begin
$dumpvars();
clk_counter <= 8'b0;
reset <= 1'b1;
`ifdef DEBUG
$display("sim: starting sim");
`endif
#5 reset <= 1'b0;
`ifdef DEBUG
$display("sim: clearing reset");
`endif
#80000 $display("FAILED: simulation timed out");
$finish;
end
assign clk = clk_counter < ((`CLK_PERIOD) / 2);
always begin
#1 clk_counter <= (clk_counter == `CLK_PERIOD - 1 ? 32'b0 : clk_counter + 1);
end
/*from goodies*/
`ifdef MODELSIM
UFROM #(
.MEMORYFILE("include/from.mem")
) UFROM_inst (
.ADDR6(from_addr[6]),
.ADDR5(from_addr[5]),
.ADDR4(from_addr[4]),
.ADDR3(from_addr[3]),
.ADDR2(from_addr[2]),
.ADDR1(from_addr[1]),
.ADDR0(from_addr[0]),
.CLK (from_clk),
.DO7 (from_data[7]),
.DO6 (from_data[6]),
.DO5 (from_data[5]),
.DO4 (from_data[4]),
.DO3 (from_data[3]),
.DO2 (from_data[2]),
.DO1 (from_data[1]),
.DO0 (from_data[0])
);
`else
reg [7:0] from_data_reg;
assign from_data = from_data_reg;
always @(posedge from_clk) begin
from_data_reg <= {1'b0, from_addr};
end
`endif
reg state;
`define STATE_SEND 1'b0
`define STATE_WAIT 1'b1
reg [6:0] counter;
always @(posedge clk) begin
wb_cyc_i <= 1'b0;
wb_stb_i <= 1'b0;
if (reset) begin
counter <= 7'b0;
state <= `STATE_SEND;
end else begin
case (state)
`STATE_SEND: begin
wb_cyc_i <= 1'b1;
wb_stb_i <= 1'b1;
wb_we_i <= 1'b0;
wb_adr_i <= {9'b0, counter};
state <= `STATE_WAIT;
`ifdef DEBUG
$display("wbm: read command, adr = %x", {9'b0, counter});
`endif
end
`STATE_WAIT: begin
if (wb_ack_o) begin
`ifdef DEBUG
$display("wbm: read reply, data = %x", wb_dat_o);
`endif
if (wb_dat_o[6:0] !== counter) begin
$display("FAILED: invalid data");
$finish;
end else if (counter == 7'b111_1111) begin
$display("PASSED");
$finish;
end
counter <= counter + 1;
state <= `STATE_SEND;
end
end
endcase
end
end
endmodule
| 6.605472 |
module tb_fsm ();
reg clk;
reg rst_n;
reg key_in;
wire [1:0] state;
initial begin
clk = 1'b1;
rst_n = 1'b0;
key_in = 1'b1;
#100 rst_n = 1'b1;
#100 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 $finish;
end
always #10 clk = ~clk;
fsm component (
.clk(clk),
.rst_n(rst_n),
.key_in(key_in),
.out(state)
);
initial begin
$dumpfile("tb_fsm.vcd");
$dumpvars(0, component);
end
endmodule
| 7.134834 |
module tb_FSM_ex_control;
parameter s_IDLE = 2'b00; //States for the main FSM
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000; //States for the sub-FSM
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100;
parameter s_ADC_2 = 3'b101;
parameter s_END = 3'b110;
reg r_Init = 1'b0;
reg r_Clock = 1'b0;
reg r_Reset = 1'b0;
reg [4:0] r_count_time = 5'd30;
reg [2:0] r_RD_FSM = s_INIT;
wire w_NRE_1;
wire w_NRE_2;
wire w_ADC;
wire w_Expose;
wire w_Erase;
wire [1:0] w_Main_FSM;
//Instantiation of FSM_ex_control, called UUT (Unit Under Test)
FSM_ex_control UUT (
.i_Init(r_Init),
.i_Clock(r_Clock),
.i_Reset(r_Reset),
.i_count_time(r_count_time),
.i_RD_FSM(r_RD_FSM),
.o_NRE_1(w_NRE_1),
.o_NRE_2(w_NRE_2),
.o_ADC(w_ADC),
.o_Expose(w_Expose),
.o_Erase(w_Erase),
.o_Main_FSM(w_Main_FSM)
);
always #2.5 r_Clock <= !r_Clock;
initial begin //Function calls to create a *.vcd file
$dumpfile("dump.vcd"); //NECESSARY JUST TO SIMULATE IN edaplayground.com
$dumpvars(1); //WITH EITHER VERILOG OR SYSTEMVERILOG
end
initial begin //Initial block
r_Reset <= 1'b1;
#10 //20us seconds
r_Reset <= 1'b0;
#10 r_Init <= 1'b1;
#5 r_Init <= 1'b0;
#40 r_count_time <= 5'd0;
r_RD_FSM <= s_INIT;
#10 r_RD_FSM <= s_NRE_1;
#10 r_RD_FSM <= s_ADC_1;
#10 r_RD_FSM <= s_NRE_1;
#10 r_RD_FSM <= s_NOTHING;
#10 r_RD_FSM <= s_NRE_2;
#10 r_RD_FSM <= s_ADC_2;
#10 r_RD_FSM <= s_NRE_2;
#10 r_RD_FSM <= s_END;
#10 $display("Test Complete");
end
endmodule
| 7.792768 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire clk, reset;
wire [15:0] bus_data_in_TB;
wire [3:0] nxt_state_BTB;
wire [3:0] nxt_state_STB;
wire error_BTB;
wire error_STB;
wire [3:0] state_control_BTB;
wire [3:0] state_control_STB;
wire nxt_error_BTB;
wire nxt_error_STB;
wire [15:0] bus_data_out_BTB;
wire [15:0] bus_data_out_STB;
///////////////////////////////////////////////////////////////////////////////////////////
//////////// FSM MUX BEHAVIORAL
////////////
///////////////////////////////////////////////////////////////////////////////////////////
fsm_par_mux fsm_mux_TB ( /*AUTOINST*/
// Outputs
.bus_data_out(bus_data_out_BTB),
.nxt_state(nxt_state_BTB),
.state_control(state_control_BTB),
.nxt_error(nxt_error_BTB),
.error(error_BTB),
// Inputs
.clk(clk),
.bus_data_in(bus_data_in_TB),
.reset(reset)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// FSM MUX SYN
////////////
///////////////////////////////////////////////////////////////////////////////////////////
fsm_par_mux_syn fsm_mux_syn_TB ( /*AUTOINST*/
// Outputs
.bus_data_out(bus_data_out_STB),
.nxt_state(nxt_state_STB),
.state_control(state_control_STB),
.nxt_error(nxt_error_STB),
.error(error_STB),
// Inputs
.clk(clk),
.bus_data_in(bus_data_in_TB),
.reset(reset)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// TESTER FSM MUX
////////////
///////////////////////////////////////////////////////////////////////////////////////////
t_fsm_par_mux t_fsm_parame_mux_TB ( /*AUTOINST*/
// Outputs
.bus_data_out(bus_data_out_BTB),
.nxt_state(nxt_state_BTB),
.state_control(state_control_BTB),
.nxt_error(nxt_error_BTB),
.error(error_BTB),
// Syn
.bus_data_out_s(bus_data_out_STB),
.nxt_state_s(nxt_state_BTB),
.state_control_s(state_control_BTB),
.nxt_error_s(nxt_error_BTB),
.error_s(error_BTB),
// Inputs
.clk(clk),
.bus_data_in(bus_data_in_TB),
.reset(reset)
);
endmodule
| 7.554736 |
module tb_ftdi_chip_model #(
parameter CHIP_EW = 0 // FTDI USB chip data width, 0=8bit, 1=16bit, 2=32bit. for FT232H is 0, for FT600 is 1, for FT601 is 2.
) (
output reg ftdi_clk,
output reg ftdi_rxf_n,
output reg ftdi_txe_n,
input wire ftdi_oe_n,
input wire ftdi_rd_n,
input wire ftdi_wr_n,
inout [(8<<CHIP_EW)-1:0] ftdi_data,
inout [(1<<CHIP_EW)-1:0] ftdi_be
);
//---------------------------------------------------------------------------------------------------------------------------------------------------------------
// function : generate random unsigned integer
//---------------------------------------------------------------------------------------------------------------------------------------------------------------
function [31:0] randuint;
input [31:0] min;
input [31:0] max;
begin
randuint = $random;
if (min != 0 || max != 'hFFFFFFFF) randuint = (randuint % (1 + max - min)) + min;
end
endfunction
wire [(8<<CHIP_EW)-1:0] DATA_HIGHZ = {(8 << CHIP_EW) {1'bz}};
localparam [(8<<CHIP_EW)-1:0] DATA_ZERO = {(8 << CHIP_EW) {1'b0}};
wire [(1<<CHIP_EW)-1:0] BE_HIGHZ = {(1 << CHIP_EW) {1'bz}};
localparam [(1<<CHIP_EW)-1:0] BE_ZERO = {(1 << CHIP_EW) {1'b0}};
localparam [(1<<CHIP_EW)-1:0] BE_ALL_ONE = ~BE_ZERO;
initial ftdi_clk = 1'b0; // generate FTDI chip clock
always #8333 ftdi_clk = ~ftdi_clk; // approximately 60MHz.
reg [(8<<CHIP_EW)-1:0] ftdi_r_data = DATA_ZERO;
reg [(1<<CHIP_EW)-1:0] ftdi_r_be = BE_ZERO;
reg [(8<<CHIP_EW)-1:0] tmp_data = DATA_ZERO;
reg [(8<<CHIP_EW)-1:0] tmp_be = (CHIP_EW == 0) ? 1 : BE_ZERO;
reg [ 7:0] rxbyte = (CHIP_EW == 0) ? 8'h01 : 8'h00;
integer i;
always @(posedge ftdi_clk) // data from FTDI-Chip to FPGA (read from FTDI-Chip)
if (~ftdi_rd_n & ~ftdi_rxf_n) begin
tmp_data = ftdi_r_data;
tmp_be = (CHIP_EW == 0) ? BE_ALL_ONE : randuint(0, 'hFFFFFFFF);
for (i = 0; i < (1 << CHIP_EW); i = i + 1) begin
if (tmp_be[i]) begin
//$write(" %02X", rxbyte);
tmp_data[8*i+:8] = rxbyte;
rxbyte = rxbyte + 1;
end
end
ftdi_r_data <= tmp_data;
ftdi_r_be <= tmp_be;
end
reg [7:0] txbyte = 8'h00;
always @(posedge ftdi_clk) // data from FPGA to FTDI-Chip (write to FTDI-Chip)
if (~ftdi_wr_n & ~ftdi_txe_n) begin
for (i = 0; i < (1 << CHIP_EW); i = i + 1) begin
if (ftdi_be[i]) begin
$write(" %02X", ftdi_data[8*i+:8]);
if (txbyte !== ftdi_data[8*i+:8]) begin
$display("*** error : data incorrect");
$stop;
end
txbyte = txbyte + 1;
end
end
end
assign ftdi_data = ftdi_oe_n ? DATA_HIGHZ : ftdi_r_data;
assign ftdi_be = ftdi_oe_n ? BE_HIGHZ : ftdi_r_be;
initial begin
ftdi_rxf_n <= 1'b1;
while (1) begin
repeat (randuint(1, 100)) @(posedge ftdi_clk);
ftdi_rxf_n <= 1'b0;
repeat (randuint(1, 100)) @(posedge ftdi_clk);
ftdi_rxf_n <= 1'b1;
end
end
initial begin
ftdi_txe_n <= 1'b1;
while (1) begin
repeat (randuint(1, 100)) @(posedge ftdi_clk);
ftdi_txe_n <= 1'b0;
repeat (randuint(1, 100)) @(posedge ftdi_clk);
ftdi_txe_n <= 1'b1;
end
end
endmodule
| 7.23555 |
module tb_full_adder_cout;
// Inputs
reg a, b, c;
// Outputs
wire cout;
// Instantiate the Unit Under Test (UUT)
fa_cout uut (
.a(a),
.b(b),
.c(c),
.cout(cout)
);
initial begin
$dumpfile("tb_full_adder_cout.vcd");
$dumpvars(0, tb_full_adder_cout);
// Initialize Inputs
a = 0;
b = 0;
c = 0;
#30 $finish;
end
always #4 a = ~a;
always #2 b = ~b;
always #1 c = ~c;
endmodule
| 7.161246 |
module tb_full_adder_sum;
// Inputs
reg a, b, c;
// Outputs
wire sum;
// Instantiate the Unit Under Test (UUT)
fa_sum uut (
.a (a),
.b (b),
.c (c),
.sum(sum)
);
initial begin
$dumpfile("tb_full_adder_sum.vcd");
$dumpvars(0, tb_full_adder_sum);
// Initialize Inputs
a = 0;
b = 0;
c = 0;
#30 $finish;
end
always #4 a = ~a;
always #2 b = ~b;
always #1 c = ~c;
endmodule
| 7.161246 |
module tb_fusion #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
) ();
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'd1; // reset
#25 gpio_o_data_tri_o = 32'd0;
//Etapa carga, 5 datos, subida/bajada valid
#500 gpio_o_data_tri_o = 32'b00000000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000001000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000001000000010;
//Carga img length/size
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000000000;
//Cargo 1024
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000001110;
//Cambio a instruccion de carga de img length;
#500 gpio_o_data_tri_o = 32'b00100000000000000000000000001110;
//Ya cargue tamano, pasamos a etapa de carga
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011000010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01010000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01000000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01010000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
//Data request
#500 gpio_o_data_tri_o = 32'b01100000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000111100011111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
//Paso a estado de RUN, vamos FSM
#500 gpio_o_data_tri_o = 32'b10000000000111111111111111111110;
#2500 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim u_micro_sim (
.o_led(o_led),
.i_CLK(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule
| 6.522731 |
module tb_fw ();
reg exmem_regwr, memwb_regwr;
reg [4:0] exmem_rd, memwb_rd, idex_rs1, idex_rs2;
wire [1:0] forwardA, forwardB;
forwarding_unit fw (
exmem_regwr,
exmem_rd,
memwb_regwr,
memwb_rd,
idex_rs1,
idex_rs2,
forwardA,
forwardB
);
initial begin
exmem_regwr = 1'b1;
memwb_regwr = 1'b0;
exmem_rd = 4'h0;
memwb_rd = 4'h1;
idex_rs1 = 4'h0;
idex_rs2 = 4'h1;
#10 exmem_regwr = 1'b1;
memwb_regwr = 1'b0;
exmem_rd = 4'h1;
memwb_rd = 4'h2;
idex_rs1 = 4'h1;
idex_rs2 = 4'h0;
#10 exmem_regwr = 1'b1;
memwb_regwr = 1'b1;
exmem_rd = 4'h3;
memwb_rd = 4'h3;
idex_rs1 = 4'h3;
idex_rs2 = 4'h1;
#40 $finish;
end
initial begin
$dumpfile("fw.vcd");
$dumpvars(0, tb_fw);
end
endmodule
| 6.724096 |
module tb_f_word_set ();
reg sys_clk;
reg sys_rst_n;
reg key_add;
reg key_sub;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#10000;
key_add <= 1'b1;
#50;
end
always #10 sys_clk = ~sys_clk;
f_word_set f_word_set_inst (
.sys_clk (),
.sys_rst_n(),
.key_add (),
.key_sub (),
.FREQ_CTRL()
);
endmodule
| 6.697354 |
module tb_gameChecker ();
wire [1:0] RamAddr;
wire [23:0] RamDat;
wire gameComplete;
reg CLK, RST = 1'b0;
reg [31:0] cycleCounter = 0;
// Testbench memory manipulation I/O
reg [23:0] ramInA = 24'h000000;
wire [23:0] ramOutA;
reg ramWrenA = 1'b1;
reg [1:0] ramAddrA = 2'b00;
gameChecker DUT_gameChecker (
.RamAddr(RamAddr),
.RamDat(RamDat),
.gameComplete(gameComplete),
.CLK(CLK),
.RST(RST)
);
sudokuRAM RAM (
.clock(CLK),
// Memory port used by game checker (read-only)
.address_b(RamAddr),
.q_b(RamDat),
.wren_b(1'b0),
.data_b(),
// Mock out memory port used by interface controller
// Use to alter memory during testing
.address_a(ramAddrA),
.data_a(ramInA),
.wren_a(ramWrenA),
.q_a(ramOutA)
);
// Test logic
initial begin
CLK = 0;
// Note: RAM starts in state determined by sudoku4x4.mif
// Delay start to let checker load game state from RAM
repeat (10) @(posedge CLK);
// Expect gameComplete == 0 after loading
// Write new game state to RAM (not a valid complete state, but close)
// Format isn't technically correct but only the lowest 16 bits matter for the checker
// 1 _ 3 4
// 4 3 2 1
// 3 4 1 2
// 2 1 4 3
@(posedge CLK) ramAddrA = 2'b00;
@(posedge CLK) ramInA = 24'h001034;
@(posedge CLK) ramAddrA = 2'b01;
@(posedge CLK) ramInA = 24'h004321;
@(posedge CLK) ramAddrA = 2'b10;
@(posedge CLK) ramInA = 24'h003412;
@(posedge CLK) ramAddrA = 2'b11;
@(posedge CLK) ramInA = 24'h002143;
// Delay to let checker read game state, at end expect gameComplete == 0
repeat (10) @(posedge CLK);
// Fill in the last blank in row 00, completing the game
@(posedge CLK) ramAddrA = 2'b00;
@(posedge CLK) ramInA = 24'h001234;
// Delay for game checker, at end expect gameComplete == 1
repeat (10) @(posedge CLK);
// Mess up a couple of numbers
@(posedge CLK) ramAddrA = 2'b01;
@(posedge CLK) ramInA = 24'h004322;
@(posedge CLK) ramAddrA = 2'b11;
@(posedge CLK) ramInA = 24'h001143;
// Delay for game checker, at end expect gameComplete == 0
repeat (10) @(posedge CLK);
// Test a second, different correct game state
// This time it's a solution of the state from the MIF file
// 3 2 1 4
// 4 1 2 3
// 1 4 3 2
// 2 3 4 1
@(posedge CLK) ramAddrA = 2'b00;
@(posedge CLK) ramInA = 24'h003214;
@(posedge CLK) ramAddrA = 2'b01;
@(posedge CLK) ramInA = 24'h004123;
@(posedge CLK) ramAddrA = 2'b10;
@(posedge CLK) ramInA = 24'h001432;
@(posedge CLK) ramAddrA = 2'b11;
@(posedge CLK) ramInA = 24'h002341;
// Delay for game checker, at end expect gameComplete == 1
repeat (10) @(posedge CLK);
// Assert game checker reset
RST = 1;
repeat (2) @(posedge CLK);
RST = 0;
repeat (10) @(posedge CLK);
end
// Test clock (50 MHz)
always begin
if (cycleCounter < 170) begin
#10;
CLK <= !CLK;
cycleCounter <= cycleCounter + 1;
end
end
endmodule
| 6.665633 |
module tb_gates ();
reg a_in;
reg b_in;
wire o_and;
wire o_nand;
wire o_or;
wire o_nor;
wire o_xor;
wire o_xnor;
wire o_inv;
wire o_buf;
integer i;
and_gate AND_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_and)
);
nand_gate NAND_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_nand)
);
or_gate OR_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_or)
);
nor_gate NOR_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_nor)
);
xor_gate XOR_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_xor)
);
xnor_gate XNOR_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_xnor)
);
inverter INVERTER (
.a_in (a_in),
.y_out(o_inv)
);
buffer BUFFER (
.a_in (a_in),
.y_out(o_buf)
);
initial begin
$dumpfile("tb_gates.vcd");
$dumpvars(0);
end
initial begin
a_in = 1'b0;
b_in = 1'b0;
end
initial begin
for (i = 0; i < 4; i = i + 1) begin
#10{a_in, b_in} = i;
end
end
initial begin
$display("a_in\tb_in\to_and\to_nand\to_or\to_nor\to_xor\to_xnor\to_inv\to_buf");
$monitor(a_in, "\t", b_in, "\t", o_and, "\t", o_nand, "\t", o_or, "\t", o_nor, "\t", o_xor,
"\t", o_xnor, "\t", o_inv, "\t", o_buf);
#40 $finish;
end
endmodule
| 7.322367 |
module: gate_and
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_gate_and #(
parameter INPUT_COUNT = 8,
parameter INPUT_RANGE = 2**8
);
// Inputs
reg [INPUT_COUNT - 1:0] in = 0;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
gate_and #(
.INPUT_COUNT(INPUT_COUNT)
)
uut (
.in(in),
.out(out)
);
initial
begin
for(in = 0; in < (INPUT_RANGE - 1); in = in + 1)
begin
if(out) $stop;
#1;
end
#1;
if(~out) $stop;
$stop;
end
endmodule
| 7.54105 |
module
// Module Name: /home/lsriw/SR/KonradAdasiewicz/lab2/gate_module/tb_gate_module.v
// Project Name: gate_module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: gate_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_gate_module;
// Inputs
wire [7:0] x;
wire [7:0] y;
// Outputs
wire out;
gate_module_gen_test generator (
.x(x),
.y(y)
);
// Instantiate the Unit Under Test (UUT)
gate_module uut (
.x(x),
.y(y),
.out(out)
);
gate_module_check_test checker (
.in(out)
);
endmodule
| 6.999332 |
module tb_genDone;
reg clk, rst, gen_en, sobel_en2;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen ADDGEN (
clk,
rst,
gen_en,
sobel_en2,
addr,
done
);
reg gen_done, sobel_done;
wire gray_en, sobel_en;
wire [5:0] state;
FSM fsm (
clk,
rst,
gen_done,
sobel_done,
gray_en,
sobel_en,
state
);
initial begin
rst = 1'b1;
#300;
rst = 1'b0;
#200;
#2000;
#50000;
#1000;
#50000;
#50000; // gets to 10000_00000
#50000; // 1111110111
#2000;
#200;
#600 $stop;
end
always @(*) begin
sobel_en2 = sobel_en;
gen_done = done;
gen_en = gray_en;
end
always begin
if (rst == 1'b1) begin
clk = 1'b0;
#1;
end else begin
#100;
clk = ~clk;
end
end
endmodule
| 7.571897 |
module tb_generate1;
reg sysclk;
reg reset;
reg status;
parameter bus_width = 15;
reg [bus_width:0] din;
reg [bus_width:0] rdout;
initial begin
$dumpfile("vcd/generate1.vcd");
$dumpvars(0, tb_generate1);
end
initial begin
$from_myhdl(sysclk, reset, wrb, din);
$to_myhdl(rdout);
end
//wire rstn;
gen dut_gen (
sysclk,
reset,
wrb,
din,
rdout
);
endmodule
| 7.1758 |
module tb_generator (
clk,
resetn,
// num_data,
// fifo write bus
// fifo_full,
fifo_data,
fifo_wrreq,
ack
);
// paramenters
parameter DWIDTH = 8;
parameter input_file = "";
//
parameter WIDTH = 56;
parameter HEIGHT = 56;
localparam num_data = WIDTH * HEIGHT;
//portmap
input clk;
input resetn;
// input fifo_full;
output [DWIDTH-1:0] fifo_data;
output reg fifo_wrreq;
// output reg [7:0] num_data;
output reg ack;
integer file_in;
integer s_data;
initial begin
file_in <= $fopen(input_file, "r"); // Read image file
end
// parameter READ_CFG_STATE = 0;
// parameter WR_DATA_STATE = 1;
//
reg [ 11:0] data_cnt;
reg [DWIDTH-1:0] data; // dung de doc gia tri pixel tu file
reg [DWIDTH-1:0] data_read; // dung de lay data tren cac channel
// reg [1:0] state;
//
assign fifo_data = data_read;
// // generate random value
// reg[15:0]a;
// always @(posedge clk)
// begin
// a <=$urandom%10;
// end
// wire data_valid_in;
// // assign data_valid_in = a[3] | a[1];
assign data_valid_in = 1'b1;
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
data_cnt <= 1;
data_read <= 0;
fifo_wrreq <= 0;
end else begin
if (data_valid_in == 1 /* && fifo_full == 0 */) begin
data_cnt <= data_cnt + 1;
s_data = $fscanf(file_in, "%h", data);
// if (s_data)
// begin
// data_read <= data;
// fifo_wrreq <= 1;
// if(data_cnt == num_data)
// begin
// $display("end read data");
// end
// end
// else
// begin
// // data_cnt <= data_cnt;
// data_read <= data_read;
// fifo_wrreq <= 0;
// end
if (s_data) begin
// if (data_cnt == num_data+)
if(data_cnt < num_data * 2) // Edit here
begin
data_read <= data;
fifo_wrreq <= 1;
end
else
if(data_cnt == num_data * 2) // Edit here
begin
data_read <= data;
fifo_wrreq <= 1;
$display("end read data");
end else
// if (data_cnt < num_data+WIDTH+2) // Edit here
// begin
// fifo_wrreq <= 1;
// data_read <= 32'bz;
// end
// else
begin
fifo_wrreq <= 0;
data_read <= 32'bz;
end
end else begin
// data_cnt <= data_cnt;
data_read <= data_read;
fifo_wrreq <= 0;
end
end else begin
data_cnt <= data_cnt;
data_read <= data_read;
fifo_wrreq <= 0;
end
end
end
endmodule
| 7.35437 |
module tb_generic_sync_ram;
reg clk;
reg [7:0] address;
reg [7:0] data_in;
wire [7:0] data_out;
reg [7:0] data_out_r;
reg cs;
reg we;
reg oe;
generic_sync_mem mem (
.clk(clk),
.address(address),
.data_in(data_in),
.data_out(data_out),
.cs(cs),
.we(we),
.oe(oe)
);
initial begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("tb_generic_sync_ram.vcd");
$dumpvars;
#10;
cs = 1'b1;
we = 1'b1;
oe = 1'b0;
data_in = 8'hff;
address = 8'h00;
#10;
cs = 1'b1;
we = 1'b1;
oe = 1'b0;
data_in = 8'hbb;
address = 8'h01;
#10;
cs = 1'b1;
we = 1'b1;
oe = 1'b0;
data_in = 8'hcc;
address = 8'h02;
#10;
cs = 1'b1;
we = 1'b1;
oe = 1'b0;
data_in = 8'hdd;
address = 8'h03;
#10;
cs = 1'b1;
we = 1'b0;
oe = 1'b1;
address = 8'h00;
#10;
cs = 1'b1;
we = 1'b0;
oe = 1'b1;
address = 8'h01;
#10;
cs = 1'b1;
we = 1'b0;
oe = 1'b1;
address = 8'h02;
#10;
cs = 1'b1;
we = 1'b0;
oe = 1'b1;
address = 8'h03;
#10;
$finish;
end
endmodule
| 6.666288 |
module: game_engin
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_gameengine;
// Inputs
reg clk;
reg collision_detected;
reg [1:0] player_choice;
reg [1:0] enemy_choice;
reg player_turn;
reg attacker_turn;
// Outputs
wire [7:0] player_HP;
wire [7:0] enemy_HP;
wire [4:0] player_remained_sword;
wire [4:0] player_remained_baseballbat;
wire [4:0] enemy_remained_sword;
wire [4:0] enemy_remained_baseballbat;
wire player_win;
wire enemy_win;
// Instantiate the Unit Under Test (UUT)
new_game uut (
.clk(clk),
.collision_detected(collision_detected),
.player_choice(player_choice),
.enemy_choice(enemy_choice),
.player_turn(player_turn),
.attacker_turn(attacker_turn),
.player_HP(player_HP),
.enemy_HP(enemy_HP),
.player_remained_sword(player_remained_sword),
.player_remained_baseballbat(player_remained_baseballbat),
.enemy_remained_sword(enemy_remained_sword),
.enemy_remained_baseballbat(enemy_remained_baseballbat),
.player_win(player_win),
.enemy_win(enemy_win)
);
initial begin
// Initialize Inputs
clk = 0;
collision_detected = 0;
player_choice = 0;
enemy_choice = 0;
player_turn = 0;
attacker_turn = 0;
// Wait 100 ns for global reset to finish
#5;
player_choice = 2'b11;
collision_detected = 1;
#2;
player_turn = 1;
// Add stimulus here
#5;
player_turn = 0;
attacker_turn = 1;
enemy_choice = 2'b10;
#7;
player_turn = 1;
attacker_turn = 0;
player_choice = 2'b01;
#2;
player_turn = 0;
attacker_turn = 1;
enemy_choice = 2'b00;
#4;
collision_detected = 0;
attacker_turn = 0;
#2;
collision_detected = 1;
#2;
player_turn = 1;
#4;
player_turn = 0;
attacker_turn = 1;
#6;
$finish;
end
always
#1 clk = !clk;
endmodule
| 7.016196 |
module tb_gige_tx ();
reg srst;
reg clk;
wire tx_c_90, tx_dv;
wire [3:0] tx_d;
// clock
initial begin
clk = 0;
forever #(4) clk = ~clk;
end
// reset
initial begin
srst <= 1;
repeat (15) @(posedge clk);
srst <= 0;
end
top_gige #(
.SIM_FLAG(1)
) inst_top_gige (
.tx_clk(clk),
.rst(srst),
.tx_c_90(tx_c_90),
.tx_d(tx_d),
.tx_dv(tx_dv)
);
endmodule
| 7.264755 |
module tb_gmii2fifo18 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [17:0] data_din, len_din;
reg data_full, len_full;
wire data_wr_en, len_wr_en;
wire wr_clk;
reg [63:0] global_counter;
gmii2fifo18 #(
.Gap(4'h4)
) gmii2fifo18_tb (
.sys_rst(sys_rst),
.global_counter(global_counter),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.data_din (data_din),
.data_full (data_full),
.data_wr_en(data_wr_en),
.len_din (len_din),
.len_full (len_full),
.len_wr_en(len_wr_en),
.wr_clk()
);
task waitclock;
begin
@(posedge phy_rx_clk);
#1;
end
endtask
always @(posedge phy_rx_clk) begin
if (data_wr_en == 1'b1) $display("din: %05x", data_din);
end
reg [8:0] rom[0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv, phy_rxd} <= rom[counter];
counter <= counter + 1;
global_counter <= global_counter + 64'h1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo18);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
data_full = 1'b0;
global_counter <= 64'h0;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
| 6.655554 |
module tb_gmii2fifo72 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [71:0] din;
wire full;
wire wr_en;
wire wr_clk;
gmii2fifo72 #(
.Gap(4'h2)
) gmii2fifo72_tb (
.sys_rst(sys_rst),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge wr_clk) begin
if (wr_en == 1'b1) $display("din: %x", din);
end
reg [11:0] rom[0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv, phy_rxd} <= rom[counter];
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo72);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
| 6.743546 |
module tb_gmii2fifo9 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [8:0] din;
reg full;
wire wr_en;
wire wr_clk;
gmii2fifo9 #(
.Gap(4'h2)
) gmii2fifo9_tb (
.sys_rst(sys_rst),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge wr_clk) begin
if (wr_en == 1'b1) $display("din: %x", din);
end
reg [8:0] rom[0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv, phy_rxd} <= rom[counter];
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo9);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
full = 1'b0;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
| 6.740253 |
module tb_gmiisend ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
reg gmii_tx_clk;
initial gmii_tx_clk = 1'b0;
always #8 gmii_tx_clk = ~gmii_tx_clk;
reg fifo_clk;
initial fifo_clk = 1'b0;
always #13.468 fifo_clk = ~fifo_clk;
//
// Test Bench
//
reg sys_rst;
//reg rx_dv;
reg empty;
reg full;
wire rd_en;
wire TXEN;
wire [7:0] TXD;
reg [23:0] tx_data;
gmii_tx gmiisend (
/*** FIFO ***/
.fifo_clk(fifo_clk),
.sys_rst(sys_rst),
.dout(tx_data), //24bit
.empty(empty),
.full(full),
.rd_en(rd_en),
//.rd_clk(fifo_clk),
/*** Ethernet PHY GMII ****/
.tx_clk(gmii_tx_clk),
.tx_en(TXEN),
.txd(TXD)
);
//
// a clock
//
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
//
// Scinario
//
reg [25:0] rom[0:2024];
reg [11:0] counter = 12'd0;
always @(posedge sys_clk) begin
{full, empty, tx_data} <= rom[counter];
counter <= counter + 12'd1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmiisend);
$readmemh("request.mem", rom);
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#100000;
$finish;
end
endmodule
| 7.834436 |
module tb_gng;
reg tb_clock;
reg tb_reset;
reg tb_clockEnable;
wire tb_valid_out;
wire [15:0] tb_data_out;
wire [2:0] nterm;
wire [7:0] ndata;
wire [7:0] nidle;
assign nterm = tb_data_out[(15-7)-:3];
assign ndata = tb_data_out[(15-4)-:8];
assign nidle = tb_data_out[(15-8)-:6];
initial begin
tb_clock = 1'b0;
tb_clockEnable = 1'b0;
tb_reset = 1'b1;
#1 tb_reset = 1'b0;
#1 tb_reset = 1'b1;
#1 tb_clockEnable = 1'b1;
#10000000 $finish;
end
always #1 tb_clock = ~tb_clock;
gng #() test_gng (
.clk(tb_clock),
.rstn(tb_reset),
.ce(tb_clockEnable),
.valid_out(tb_valid_out),
.data_out(tb_data_out)
);
endmodule
| 7.097798 |
module tb_good_latch;
// Inputs
reg clk, reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
good_latch uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_good_latch.vcd");
$dumpvars(0, tb_good_latch);
// Initialize Inputs
clk = 0;
reset = 1;
d = 0;
#300 $finish;
end
always #20 clk = ~clk;
always #23 d = ~d;
always #15 reset = 0;
endmodule
| 6.676618 |
module tb_good_mux;
// Inputs
reg i0, i1, sel;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
good_mux uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.y (y)
);
initial begin
$dumpfile("tb_good_mux.vcd");
$dumpvars(0, tb_good_mux);
// Initialize Inputs
sel = 0;
i0 = 0;
i1 = 0;
#300 $finish;
end
always #75 sel = ~sel;
always #10 i0 = ~i0;
always #55 i1 = ~i1;
endmodule
| 7.020985 |
module tb_good_shift_reg;
// Inputs
reg clk, reset, d;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
good_shift_reg uut (
.clk(clk),
.reset(reset),
.d(d),
.dout(dout)
);
initial begin
$dumpfile("tb_good_shift_reg.vcd");
$dumpvars(0, tb_good_shift_reg);
// Initialize Inputs
clk = 0;
reset = 1;
d = 0;
#3000 $finish;
end
always #20 clk = ~clk;
always #223 d = ~d;
always #147 reset = 0;
endmodule
| 7.276209 |
module tb_good_shift_reg;
// Inputs
reg clk, reset, d;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
good_shift_reg uut (
.clk(clk),
.reset(reset),
.d(d),
.dout(dout)
);
initial begin
$dumpfile("tb_good_shift_reg.vcd");
$dumpvars(0, tb_good_shift_reg);
// Initialize Inputs
clk = 0;
reset = 1;
d = 0;
#3000 $finish;
end
always #20 clk = ~clk;
always #223 d = ~d;
always #147 reset = 0;
endmodule
| 7.276209 |
module tb_Gray ();
wire [2:0] code;
reg up;
reg down;
reg reset;
Gray_counter uut (
.clk_up(up),
.clk_down(down),
.code(code),
.reset(reset)
);
integer i;
initial begin
reset = 1;
#5;
reset = 0;
$display("%b", code);
up = 1;
#5;
up = 0;
#5; /*1*/
$display("%b", code);
up = 1;
#5;
up = 0;
#5; /*2*/
$display("%b", code);
up = 1;
#5;
up = 0;
#5; /*3*/
$display("%b", code);
down = 1;
#5;
down = 0;
#5; /*2*/
$display("%b", code);
up = 1;
#5;
up = 0;
#5; /*3*/
$display("%b", code);
up = 1;
#5;
up = 0;
#5; /*4*/
$display("%b", code);
reset = 1;
#5;
reset = 0;
$display("do it again");
$display("%b", code);
for (i = 0; i < 10; i = i + 1) begin
up = 1;
#5;
up = 0;
#5;
$display("%b", code);
end
end
endmodule
| 6.513005 |
module tb_GRAY2MEM;
reg clk, rst;
reg gen_done, sobel_done;
wire gray_en, sobel_en;
wire [5:0] state;
FSM fsm (
clk,
rst,
gen_done,
sobel_done,
gray_en,
sobel_en,
state
);
reg gen_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen ADDGEN (
clk,
rst,
gen_en,
sobel_en,
addr,
done
);
wire [11:0] mem;
wire [ 3:0] red;
wire [ 3:0] green;
wire [ 3:0] blue;
ROM rom (
addr,
red,
green,
blue,
mem
);
reg wr_en, rd_en;
reg [ 9:0] wr_addr;
reg [11:0] wr_data;
reg [ 9:0] rd_addr;
wire [11:0] data_out;
wire [ 3:0] wr_gx;
wire [ 3:0] wr_gy;
memOp Gray (
clk,
gray_en,
rd_en,
sobel_en,
addr,
wr_data,
addr - 1'b1,
data_out,
wr_gx,
wr_gy
);
reg [11:0] rgb_in;
wire [ 3:0] gray_out;
grayScale grayscale (
clk,
rgb_in,
gray_out
);
initial begin
rst = 1'b1;
#300;
rst = 1'b0;
#200;
#2000;
#50000;
#1000;
#50000;
#50000; // gets to 10000_00000
#50000; // 1111110111
#2000;
#200;
#600 $stop;
end
always @(*) begin
rd_en = 1'b1;
gen_en = gray_en;
gen_done = done;
rgb_in = mem;
wr_data = {gray_out, gray_out, gray_out};
end
always begin
if (rst == 1'b1) begin
clk = 1'b0;
#1;
end else begin
#100;
clk = ~clk;
end
end
endmodule
| 7.189963 |
module tb_graycode;
reg clk;
reg rstn;
reg [3:0] xin;
wire [3:0] out;
graycode r0 (
clk,
xin,
rstn,
out
);
always #5 clk = ~clk;
initial begin
$dumpfile("graycode.vcd");
$dumpvars(0, tb_graycode);
$monitor($time, " %b", out);
rstn <= 0;
clk <= 0;
repeat (1) @(posedge clk);
repeat (16) begin
#10 rstn <= 1;
#10 xin <= out;
end
$finish;
end
endmodule
| 6.781936 |
module.
`timescale 1ns/1ns
`include "greater.v"
module tb_greater;
reg [1:0] a;
reg [1:0] b;
wire out;
greater test_greater(a, b, out);
initial begin
$dumpfile("tb_greater.vcd");
$dumpvars(0, tb_greater);
// vector assignment like pattern matching
// in functional programming languages.
{a, b} = 4'b0000; #1;
{a, b} = 4'b0001; #1;
{a, b} = 4'b0010; #1;
{a, b} = 4'b0011; #1;
{a, b} = 4'b0100; #1;
{a, b} = 4'b0101; #1;
{a, b} = 4'b0110; #1;
{a, b} = 4'b0111; #1;
{a, b} = 4'b1000; #1;
{a, b} = 4'b1001; #1;
{a, b} = 4'b1010; #1;
{a, b} = 4'b1011; #1;
{a, b} = 4'b1100; #1;
{a, b} = 4'b1101; #1;
{a, b} = 4'b1110; #1;
{a, b} = 4'b1111; #1;
$display("success");
end // initial begin
endmodule
| 6.603418 |
module tb_handshakee (); /* this is automatically generated */
// clock
reg clk;
initial begin
clk = 0;
forever #(1) clk = ~clk;
end
reg rst_n;
initial begin
rst_n <= 0;
#10 rst_n <= 1;
end
// (*NOTE*) replace reset, clock, others
reg valid_i;
reg data_i;
reg ready_i;
wire ready_o;
wire valid_o;
wire data_o;
handshakee inst_handshakee (
.clk (clk),
.rst_n (rst_n),
.valid_i(valid_i),
.data_i (data_i),
.ready_i(ready_i),
.ready_o(ready_o),
.valid_o(valid_o),
.data_o (data_o)
);
initial begin
valid_i <= 0;
data_i <= 0;
ready_i <= 0;
repeat (10) @(posedge clk);
data_i <= 1;
repeat (2) @(posedge clk);
valid_i <= 1;
repeat (2) @(posedge clk);
valid_i <= 0;
ready_i <= 1;
repeat (2) @(posedge clk);
ready_i <= 0;
repeat (2) @(posedge clk);
valid_i <= 1;
repeat (2) @(posedge clk);
ready_i <= 1;
repeat (2) @(posedge clk);
valid_i <= 0;
repeat (2) @(posedge clk);
ready_i <= 0;
repeat (10) @(posedge clk);
$finish;
end
// dump wave
endmodule
| 6.542843 |
module tb_hardtanh_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam NUM = {DATA_WIDTH{1'b1}};
// interface
reg clk;
reg rst_n;
reg [ NUM_INPUT_DATA-1:0] i_valid;
reg [ WIDTH_INPUT_DATA-1:0] i_data_bus;
wire [ NUM_OUTPUT_DATA-1:0] o_valid;
wire [WIDTH_OUTPUT_DATA-1:0] o_data_bus; //{o_data_a, o_data_b}
reg i_en;
initial begin
clk = 1'b0;
rst_n = 1'b1;
i_data_bus = ZERO_POINT;
i_valid = 1'b0;
i_en = 1'b1;
// reset
#10 rst_n = 1'b0;
// input activate below zero (negative)
#10 rst_n = 1'b1;
i_data_bus = {1'b1, {(DATA_WIDTH - 1) {1'b0}}};
i_valid = 1'b1;
// input activate larger than zero
#10
// i_data_bus = {1'b0, {(DATA_WIDTH-1){1'b1}}};
i_data_bus = ZERO_POINT;
i_valid = 1'b1;
#2600 $stop;
end
integer i;
always begin
@(posedge clk)
for (i = 0; i < NUM; i = i + 1) begin
i_data_bus = i_data_bus + 2'sb01;
end
end
always #5 clk = ~clk;
hardtanh_seq #(
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.rst_n(rst_n),
.i_data_bus(i_data_bus),
.i_valid(i_valid),
.o_data_bus(o_data_bus),
.o_valid(o_valid),
.i_en(i_en)
);
endmodule
| 7.132403 |
module tb_hard_png ();
initial $dumpvars(1, tb_hard_png);
reg rstn = 1'b0;
reg clk = 1'b1;
always #10000 clk = ~clk; // 50MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg istart = 1'b0;
reg ivalid = 1'b0;
wire iready;
reg [ 7:0] ibyte = 0;
wire ostart;
wire [ 2:0] colortype;
wire [13:0] width;
wire [31:0] height;
wire ovalid;
wire [7:0] opixelr, opixelg, opixelb, opixela;
hard_png hard_png_i (
.rstn (rstn),
.clk (clk),
// data input
.istart (istart),
.ivalid (ivalid),
.iready (iready),
.ibyte (ibyte),
// image size output
.ostart (ostart),
.colortype(colortype),
.width (width),
.height (height),
// data output
.ovalid (ovalid),
.opixelr (opixelr),
.opixelg (opixelg),
.opixelb (opixelb),
.opixela (opixela)
);
integer fptxt = 0, fppng = 0;
reg [256*8:1] fname_png;
reg [256*8:1] fname_txt;
integer png_no = 0;
integer txt_no = 0;
integer ii;
integer cyccnt = 0;
integer bytecnt = 0;
initial begin
while (~rstn) @(posedge clk);
fork
// thread: input png file
for (png_no = `START_NO; png_no <= `FINAL_NO; png_no = png_no + 1) begin
istart <= 1'b1;
@(posedge clk);
istart <= 1'b0;
$sformat(fname_png, `IN_PNG_FILE_FOMRAT, png_no);
fppng = $fopen(fname_png, "rb");
if (fppng == 0) begin
$error("input file %s open failed", fname_png);
$finish;
end
cyccnt = 0;
bytecnt = 0;
$display("\nstart to decode %30s", fname_png);
ibyte <= $fgetc(fppng);
while (!$feof(
fppng
))
@(posedge clk) begin
if (~ivalid | iready) begin
ivalid <= 1'b1; // A. use this to always try to input a byte to hard_png (no bubble, will get maximum throughput)
//ivalid <= ($random % 3) == 0; // B. use this to add random bubbles to the input stream of hard_png. (Although the maximum throughput cannot be achieved, it allows input with mismatched rate, which is more common in the actual engineering scenarios)
end
if (ivalid & iready) begin
ibyte <= $fgetc(fppng);
bytecnt = bytecnt + 1;
end
cyccnt = cyccnt + 1;
end
ivalid <= 1'b0;
$fclose(fppng);
$display("image %30s decode done, input %d bytes in %d cycles, throughput=%f byte/cycle",
fname_png, bytecnt, cyccnt, (1.0 * bytecnt) / cyccnt);
end
// thread: output txt file
for (txt_no = `START_NO; txt_no <= `FINAL_NO; txt_no = txt_no + 1) begin
$sformat(fname_txt, `OUT_TXT_FILE_FORMAT, txt_no);
while (~ostart) @(posedge clk);
$display("decode result: colortype:%1d width:%1d height:%1d", colortype, width, height);
fptxt = $fopen(fname_txt, "w");
if (fptxt != 0)
$fwrite(
fptxt,
"decode result: colortype:%1d width:%1d height:%1d\n",
colortype,
width,
height
);
else begin
$error("output txt file %30s open failed", fname_txt);
$finish;
end
for (ii = 0; ii < width * height; ii = ii + 1) begin
@(posedge clk);
while (~ovalid) @(posedge clk);
$fwrite(fptxt, "%02x%02x%02x%02x ", opixelr, opixelg, opixelb, opixela);
if ((ii % (width * height / 10)) == 0) $display("%d/%d", ii, width * height);
end
$fclose(fptxt);
end
join
repeat (100) @(posedge clk);
$finish;
end
endmodule
| 6.682756 |
module tb_ha_1b;
reg IN0, IN1;
wire SUM, CO;
ha_1b ha (
.IN0(IN0),
.IN1(IN1),
.SUM(SUM),
.CARRY_OUT(CO)
);
initial begin
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
IN0 = 0;
IN1 = 0;
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
IN0 = 0;
IN1 = 1;
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
IN0 = 1;
IN1 = 0;
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
IN0 = 1;
IN1 = 1;
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
end
endmodule
| 6.524754 |
module tb_hk_mash111;
// mash111 Parameters
parameter PERIOD = 10;
// parameter WIDTH = 24;
parameter WIDTH = 9;
parameter A_GAIN = 2;
parameter OUT_REG = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] y_o;
wire [WIDTH-1:0] e_o;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
integer dout_file;
initial begin
dout_file = $fopen("mash111-hkefm-data-9bit-a2-reg-new.txt", "w"); //打开所创建的文件
if (dout_file == 0) begin
$display("can not open the file!"); //创建文件失败，显示can not open the file!
$stop;
end
end
always @(posedge clk) begin
$fdisplay(dout_file, "%d", $signed(y_o)); //保存有符号数据
end
hk_mash111 #(
.WIDTH (WIDTH),
.A_GAIN (A_GAIN),
.OUT_REG(OUT_REG)
) u_hk_mash111 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i[WIDTH-1:0]),
.y_o(y_o[3:0]),
.e_o(e_o[WIDTH-1:0])
);
initial begin
// x_i = 'd8388608; // 2^23 (0.5)
x_i = 'd16; // 2^4 (0.5)
#(PERIOD * 10000);
$finish;
end
endmodule
| 6.799648 |
module hsc_vlg_tst ();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg ext_clk;
reg ext_rst_n;
reg [0:0] treg_mem_clk;
reg [0:0] treg_mem_clk_n;
reg [15:0] treg_mem_dq;
reg [1:0] treg_mem_dqs;
// wires
wire led;
wire [12:0] mem_addr;
wire [1:0] mem_ba;
wire mem_cas_n;
wire [0:0] mem_cke;
wire [0:0] mem_clk;
wire [0:0] mem_clk_n;
wire [0:0] mem_cs_n;
wire [1:0] mem_dm;
wire [15:0] mem_dq;
wire [1:0] mem_dqs;
wire [0:0] mem_odt;
wire mem_ras_n;
wire mem_we_n;
// assign statements (if any)
assign mem_clk = treg_mem_clk;
assign mem_clk_n = treg_mem_clk_n;
assign mem_dq = treg_mem_dq;
assign mem_dqs = treg_mem_dqs;
hsc i1 (
// port map - connection between master ports and signals/registers
.ext_clk(ext_clk),
.ext_rst_n(ext_rst_n),
.led(led),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_we_n(mem_we_n)
);
initial begin
ext_clk = 0;
ext_rst_n = 0;
#1000;
@(posedge ext_clk);
#5;
ext_rst_n = 1;
#10000;
$stop;
$display("Running testbench");
end
always #20 ext_clk = ~ext_clk;
always // optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
| 7.177094 |
module tb_hsync ();
reg clk;
wire hsync;
wire h264;
wire hblank_n;
always #50 clk = ~clk;
hsync hsync0 (
.clk(clk),
.hsync(hsync),
.h264(h264),
.hblank_n(hblank_n)
);
initial begin
clk <= 0;
#100000 $finish;
end
endmodule
| 6.516932 |
module: i2c_fsm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_i2c_fsm;
// Inputs
reg clk;
reg rst;
reg arst;
reg start;
reg scl_pad_i;
reg sda_pad_i;
// Outputs
wire done;
wire [7:0] msb;
wire [7:0] lsb;
wire scl_pad_o;
wire scl_padoen_o;
wire sda_pad_o;
wire sda_padoen_o;
wire scl, sda;
delay m_scl(scl_padoen_o ? 1'bz : scl_pad_o, scl);
delay m_sda(sda_padoen_o ? 1'bz : sda_pad_o, sda);
pullup (scl);
pullup (sda);
// Instantiate the Unit Under Test (UUT)
i2c_fsm uut (
.clk(clk),
.rst(rst),
.arst(arst),
.start(start),
.done(done),
.msb(msb),
.lsb(lsb),
.scl_pad_i(scl),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_padoen_o)
);
i2c_slave_model i2c_slave (
.scl(scl),
.sda(sda)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
arst = 1;
start = 0;
scl_pad_i = 0;
sda_pad_i = 0;
// Wait 100 ns for global reset to finish
#100;
#10 arst = 0;
#50 arst = 1;
#10 start = 1;
while(!done) @(posedge clk);
#100 $finish;
// Add stimulus here
end
always
#10 clk = !clk;
endmodule
| 7.65446 |
module tb_i2c_master;
// Inputs
reg [7:0] i_addr_data;
reg i_cmd;
reg i_strobe;
reg i_clk;
// Outputs
wire io_scl;
wire [7:0] o_data;
wire [2:0] o_status;
// Bidirs
wire io_sda_w;
reg io_sda;
reg en = 0;
assign io_sda_w = en ? io_sda : 1'bZ;
/*
initial
$monitor($time, ": i_clk=%b i_addr_data=%b i_cmd=%b d_neg_count=%d d_state=%d d_pos_state=%d d_neg_state=%d d_wr_sda_pos=%b d_wr_sda_neg=%b d_reg_sda_pos=%b d_reg_sda_neg=%b o_data=%b o_status=%b io_sda_w=%b d_in_data=%b",
i_clk,
i_addr_data,
i_cmd,
d_neg_count,
d_state,
d_pos_state,
d_neg_state,
d_wr_sda_pos,
d_wr_sda_neg,
d_reg_sda_pos,
d_reg_sda_neg,
o_data,
o_status,
io_sda_w,
d_in_data);
*/
// Instantiate the Unit Under Test (UUT)
i2c_master uut (
.i_addr_data(i_addr_data),
.i_cmd(i_cmd),
.i_strobe(i_strobe),
.i_clk(i_clk),
.io_sda(io_sda_w),
.io_scl(io_scl),
.o_data(o_data),
.o_status(o_status)
);
initial begin
#10 forever #10 i_clk = !i_clk;
end
initial begin
// Initialize Inputs
i_addr_data = 0;
i_cmd = 0;
i_strobe = 0;
i_clk = 0;
// Wait 10 ns for global reset to finish
// Write data 0xAB at address 0x65
#10;
i_addr_data = 8'h65;
i_strobe = 1;
i_cmd = 0; // write
#20;
i_addr_data = 8'hAB;
i_strobe = 1;
#20; // do nothing, Start condition is done
i_strobe = 0;
#180; // 8 clocks later, provide addr ack on falling edge
io_sda = 0;
en = 1;
#20;
en = 0; // release bus by rising
#160; // 8 data writes
io_sda = 0;
en = 1;
#20;
en = 0;
#60;
// Read data of 11010010 from address 0x65
i_addr_data = 8'h65;
i_strobe = 1;
i_cmd = 1; // read
#20;
i_strobe = 0;
#180; // start + addr bits
io_sda = 0; // Ack
en = 1;
#20;
io_sda = 1; // data 7
#20;
io_sda = 1;
#20;
io_sda = 0;
#20;
io_sda = 1;
#20;
io_sda = 0;
#20;
io_sda = 0;
#20;
io_sda = 1;
#20;
io_sda = 0; // data 0
#20;
en = 0;
#60;
$stop;
end
endmodule
| 7.069776 |
module tb_i2s;
reg clk;
reg reset;
reg signed [15:0] IN_L, IN_R;
wire i2s_sclk;
wire i2s_lrclk;
wire i2s_dout;
wire signed [15:0] OUT_L, OUT_R;
wire i2s_din;
wire i2s_sampled;
// 24 MHz clock source
always #20.8333 clk = ~clk;
// reset
initial begin
`ifdef icarus
$dumpfile("tb_i2s.vcd");
$dumpvars;
`endif
// init regs
clk = 1'b0;
reset = 1'b1;
// release reset
#1000 reset = 1'b0;
`ifdef icarus
// stop after 1 sec
#1000000 $finish;
`endif
end
// I2S master timing
reg [3:0] cnt;
reg [5:0] bits;
always @(posedge clk)
if (reset) begin
cnt <= 4'd0;
bits <= 6'd0;
end else begin
cnt <= cnt + 4'd1;
if (cnt == 4'hf) bits <= bits + 6'd1;
end
assign i2s_sclk = cnt[3];
assign i2s_lrclk = bits[5];
assign i2s_dout = i2s_din;
// I2S TX data
always @(posedge clk)
if (reset) begin
IN_L <= 16'd0;
IN_R <= 16'd0;
end else if (i2s_sampled) begin
IN_L <= IN_L + 16'd1;
IN_R <= IN_R - 16'd1;
end
// UUT
i2s uut (
.CLK(clk),
.IN_L(IN_L),
.IN_R(IN_R),
.i2s_sclk(i2s_sclk),
.i2s_lrclk(i2s_lrclk),
.i2s_dout(i2s_dout),
.OUT_L(OUT_L),
.OUT_R(OUT_R),
.i2s_din(i2s_din),
.i2s_sampled(i2s_sampled)
);
endmodule
| 6.554753 |
module tb_iclarke ();
reg [31:0] valp, vbet;
reg clk;
reg rst_n;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
valp = 32'h46;
vbet = 32'h56;
#500;
rst_n = 1'b1;
#5000;
$finish;
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0, tb_iclarke, "+all");
end
iclarke u_iclarke (
.clk (clk),
.rst_n(rst_n),
.valp (valp),
.vbet (vbet)
);
endmodule
| 6.766365 |
module tb_icnbc;
parameter N = 8;
parameter MIN_LD = 2;
parameter MEM_DEPTH = 256;
reg clk;
reg rst;
reg [N-1:0] n;
reg start;
reg [N-1:0] min_ld;
wire [ 3:0] codes [N-1:0];
initial begin
clk <= 1'b0;
rst = 1'b1;
end
always #5 clk = ~clk;
initial begin
repeat (10) @(negedge clk);
rst = 1'b0; //disable reset
@(negedge clk);
start = 1;
n = N;
min_ld = MIN_LD;
end
/* icnbc AUTO_TEMPLATE
(
);
*/
icnbc #(
.N(N),
.depth(MEM_DEPTH),
.width(N)
) LCBBC_INST ( /*AUTOINST*/
// Outputs
.codes (codes[3:0][N-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.n (n[N-1:0]),
.min_ld(min_ld[N-1:0]),
.start (start)
);
/* -----\/----- EXCLUDED -----\/-----
initial
begin
#15000;
$finish;
end
-----/\----- EXCLUDED -----/\----- */
initial begin
$monitor("codeword = %b\t ", codes);
end
endmodule
| 6.627426 |
module tb_idle_deletion;
localparam CGMII_IDLE = 8'h07;
reg clock;
reg reset;
reg [63:0] data;
reg [63:0] data_aux;
reg [7:0] ctrl;
reg valid;
reg enable;
reg [9:0] counter;
wire [63:0] output_data;
initial begin
clock = 1'b0;
reset = 1'b1;
data = {64{1'b0}};
data_aux = {64{1'b0}};
ctrl = 0;
valid = 0;
enable = 0;
counter = 0;
#5 reset = 0;
end
always #2.5 clock = ~clock;
always @(posedge clock) begin
counter <= counter + 1;
valid <= 1;
enable <= 1;
if (counter < 30) begin
data <= data + 1;
ctrl <= 0;
end else if (counter >= 30 && counter < 80) begin
if ((counter % 2) == 0) begin
data <= {8{CGMII_IDLE}};
ctrl <= 8'hff;
end else begin
data <= data_aux + 1;
ctrl <= 0;
end
end else begin
data <= data + 1;
ctrl <= 0;
end
end
idle_insertion_top #(
.LEN_TX_DATA(64),
.LEN_TX_CTRL(8),
.N_IDLE(20),
.N_BLOCKS(100),
.N_LANES(20)
) u_idle_insertion (
.i_clock (clock),
.i_reset (reset),
.i_enable (enable),
.i_valid (valid),
.i_tx_data(data),
.i_tx_ctrl(ctrl),
.o_tx_data(output_data)
);
endmodule
| 7.498726 |
module tb_idle_insert_file;
localparam NB_DATA = 64;
localparam NB_CTRL = 8;
localparam N_LANES = 20;
localparam N_BLOCKS = 100;
reg clock, reset, enable, in_valid; //control inputs
reg tb_enable_files;
reg [NB_DATA-1 : 0] tb_input_data;
reg [NB_CTRL-1 : 0] tb_input_ctrl;
reg [0 : NB_DATA-1] temp_in_data;
reg [0 : NB_CTRL-1] temp_in_ctrl;
wire [NB_DATA-1 : 0] tb_output_data, tb_insert_data;
wire [NB_CTRL-1 : 0] tb_output_ctrl, tb_insert_ctrl;
wire am_flag, out_valid, out_am_flag;
integer fid_input_data;
integer fid_input_ctrl;
integer fid_output_data;
integer fid_output_ctrl;
integer fid_output_flag;
integer code_error_data;
integer code_error_ctrl;
integer ptr_data;
integer ptr_ctrl;
initial begin
fid_input_data = $fopen(
"/home/diego/fundacion/PPS/src/Python/file_generator/idle-deletion-input-data.txt", "r");
if (fid_input_data == 0) begin
$display("\n\n La entrada de datos no pudo ser abierta");
$stop;
end
fid_input_ctrl = $fopen(
"/home/diego/fundacion/PPS/src/Python/file_generator/idle-deletion-input-ctrl.txt", "r");
if (fid_input_ctrl == 0) begin
$display("\n\n La entrada de control no pudo ser abierta");
$stop;
end
fid_output_data =
$fopen("/home/diego/fundacion/PPS/src/Python/file_generator/verilog-output-data.txt", "w");
if (fid_output_data == 0) begin
$display("\n\n La salida de datos no pudo ser abierta");
$stop;
end
fid_output_ctrl =
$fopen("/home/diego/fundacion/PPS/src/Python/file_generator/verilog-output-ctrl.txt", "w");
if (fid_output_ctrl == 0) begin
$display("\n\n La salida de control no pudo ser abierta");
$stop;
end
fid_output_flag =
$fopen("/home/diego/fundacion/PPS/src/Python/file_generator/verilog-output-flag.txt", "w");
if (fid_output_flag == 0) begin
$display("\n\n La salida de control no pudo ser abierta");
$stop;
end
clock = 0;
reset = 1;
enable = 0;
in_valid = 0;
tb_enable_files = 0;
#3 tb_enable_files = 1;
#2 reset = 0;
enable = 1;
in_valid = 1;
tb_enable_files = 1;
end
always #1 clock = ~clock;
always @(posedge clock) begin
if (tb_enable_files) begin
//LECTURA DE ARCHIVO
for (ptr_data = 0; ptr_data < NB_DATA; ptr_data = ptr_data + 1) begin
code_error_data <= $fscanf(fid_input_data, "%b\n", temp_in_data[ptr_data]);
if (code_error_data != 1) begin
$display("Tx-Data: El caracter leido no es valido..");
$stop;
end
end
for (ptr_ctrl = 0; ptr_ctrl < NB_CTRL; ptr_ctrl = ptr_ctrl + 1) begin
code_error_ctrl <= $fscanf(fid_input_ctrl, "%b\n", temp_in_ctrl[ptr_ctrl]);
if (code_error_ctrl != 1) begin
$display("Tx-Ctrl: El caracter leido no es valido..");
$stop;
end
end
//FIN LECTURA ARCHIVO
//ESCRITURA
$fwrite(fid_output_data, "%b\n", tb_output_data);
$fwrite(fid_output_ctrl, "%b\n", tb_output_ctrl);
$fwrite(fid_output_flag, "%b\n", am_flag);
tb_input_data <= temp_in_data;
tb_input_ctrl <= temp_in_ctrl;
end
end
idle_insertion_top #(
.LEN_TX_DATA(NB_DATA),
.LEN_TX_CTRL(NB_CTRL),
.N_IDLE(N_LANES),
.N_BLOCKS(N_BLOCKS),
.N_LANES(N_LANES)
) u_idle_insertion_top (
.i_clock (clock),
.i_reset (reset),
.i_enable (enable),
.i_valid (in_valid),
.i_tx_data(tb_input_data),
.i_tx_ctrl(tb_input_ctrl),
.o_tx_data(tb_insert_data),
.o_tx_ctrl(tb_insert_ctrl),
.o_am_flag(am_flag),
.o_valid (out_valid)
);
encoder_interface #(
.LEN_TX_DATA(NB_DATA),
.LEN_TX_CTRL(NB_CTRL)
) u_encoder_interface (
.i_valid (out_valid),
.i_am_flag(am_flag),
.i_tx_data(tb_insert_data),
.i_tx_ctrl(tb_insert_ctrl),
.o_am_flag(out_am_flag),
.o_tx_data(tb_output_data),
.o_tx_ctrl(tb_output_ctrl)
);
endmodule
| 6.525598 |
module tb_ifchain1;
reg clk;
reg rstn;
reg status;
reg [3:0] a;
reg [3:0] b;
initial begin
$dumpfile("vcd/ifchain1.vcd");
$dumpvars(0, tb_ifchain1);
end
initial begin
$from_myhdl(a, b, clk, rstn);
$to_myhdl(status);
end
//wire rstn;
test dut_test (
clk,
rstn
);
endmodule
| 6.592245 |
module top ();
wire [31:0] inst;
reg clk;
reg reset;
reg [31:0] wb_newpc;
reg [31:0] wb_newmsr;
reg wb_newpcmsr_valid;
reg exe_annul;
reg wb_annul;
reg [31:0] mem_newpc;
reg [31:0] mem_newmsr;
reg mem_newpc_valid;
reg mem_newmsr_valid;
wire decode_stall;
wire ifetch_valid;
wire [ 3:0] ifetch_fault;
wire [31:0] ifetch_instr;
wire [31:0] ifetch_pc;
wire [31:0] ifetch_msr;
wire done;
// Memory for IF:
reg [63:0] memory [1023:0];
reg [63:0] read_data;
wire read_req;
wire [31:0] read_address;
wire [ 9:0] ram_addr = read_address[12:3];
always @(posedge clk) begin
if (read_req) begin
read_data <= memory[ram_addr];
end
end
////////////////////////////////////////////////////////////////////////////////
// DUT
ifetch IF (
.clk (clk),
.reset(reset),
.IRQ(1'b0),
.wb_newpc(wb_newpc),
.wb_newmsr(wb_newmsr), /* FIXME size */
.wb_newpcmsr_valid(wb_newpcmsr_valid),
.exe_annul(exe_annul),
.wb_annul (wb_annul),
.mem_newpc(mem_newpc),
.mem_newmsr(mem_newmsr), /* FIXME size */
.mem_newpc_valid(mem_newpc_valid),
.mem_newmsr_valid(mem_newmsr_valid),
.decode_stall(decode_stall),
.ifetch_valid(ifetch_valid),
.ifetch_fault(ifetch_fault),
.ifetch_pc(ifetch_pc),
.ifetch_msr(ifetch_msr), /* FIXME can be optimised */
.ifetch_instr(ifetch_instr),
.emi_if_address(read_address),
.emi_if_req(read_req),
.emi_if_rdata(read_data),
.emi_if_valid(1'b1)
);
dummy_DE DDE (
.clk (clk),
.reset(reset),
.instr(ifetch_instr),
.instr_valid(ifetch_valid),
.instr_pc(ifetch_pc),
.instr_fault(ifetch_fault),
.stall_out(decode_stall),
.done(done)
);
////////////////////////////////////////////////////////////////////////////////
always #`CLK_P clk <= ~clk;
reg [11:0] i;
initial begin
$dumpfile("tb_ifetch2.vcd");
$dumpvars(0, top);
clk <= 0;
reset <= 1;
wb_newpc <= 0;
wb_newmsr <= 0;
wb_newpcmsr_valid <= 0;
exe_annul <= 0;
wb_annul <= 0;
mem_newpc <= 0;
mem_newmsr <= 0;
mem_newpc_valid <= 0;
mem_newmsr_valid <= 0;
/* Initialise test memory */
for (i = 0; i < 64; i = i + 1) begin
memory[i] = {magic_number((i * 2) + 1), magic_number(i * 2)};
end
/* -----\/----- EXCLUDED -----\/-----
for (i = 0; i < 64; i = i + 1) begin
$display("mem[%d] = %x", i, memory[i]);
end
-----/\----- EXCLUDED -----/\----- */
#`CLK;
reset <= 0;
//////////////////////////////////////////////////////////////////////
#(`CLK * 200);
if (done) $display("PASS");
else $display("FAIL");
$finish(0);
end
/* Test scenarios:
*
* - Regular sequential fetch of instrs
* - Stall from DE
* - Trigger a stall in fetch
* - New PC/MSR from WB and MEM, annul
* - New PC/MSR whilst stalled on I$!
* - Fault on address, IRQ -> generate fault out
* - Fetch after fault resolved -> correct instruction
* (including where stall was ongoing due to pre-fault fetch!)
*/
function [31:0] magic_number;
input [9:0] addr;
begin
magic_number = {addr[9:0], addr[9:0], addr[9:0]} ^
{{addr[8:0], addr[8:0], addr[8:0]}, 1'b0} ^
{{addr[3:0], addr[3:0], addr[3:0]}, 4'h1};
// $display("addr %x magic %x", addr, magic_number);
end
endfunction // magic_number
endmodule
| 7.326089 |
module tb_IF;
// Parameters
localparam NB_PC_CONSTANT = 3;
localparam NB_PC = 32;
localparam NB_INSTRUCTION = 32;
localparam NB_MEM_WIDTH = 8;
// Ports
reg i_clock;
reg i_IF_branch;
reg i_IF_j_jal;
reg i_IF_jr_jalr;
reg i_IF_pc_enable;
reg i_IF_pc_reset;
reg i_IF_read_enable;
reg i_IF_write_enable; // DEBUG_UNIT control
reg [ NB_MEM_WIDTH-1:0] i_IF_write_data; // DEBUG_UNIT control
reg [ NB_PC-1:0] i_IF_branch_addr;
reg [ NB_PC-1:0] i_IF_jump_addr;
reg [ NB_PC-1:0] i_IF_data_last_register;
wire [ NB_PC-1:0] o_IF_adder_result;
wire [NB_INSTRUCTION-1:0] o_IF_instruction;
FETCH #(
.NB_PC_CONSTANT(NB_PC_CONSTANT),
.NB_PC(NB_PC),
.NB_INSTRUCTION(NB_INSTRUCTION)
) FETCH (
.i_clock(i_clock),
.i_IF_branch(i_IF_branch),
.i_IF_j_jal(i_IF_j_jal),
.i_IF_jr_jalr(i_IF_jr_jalr),
.i_IF_pc_enable(i_IF_pc_enable),
.i_IF_pc_reset(i_IF_pc_reset),
.i_IF_read_enable(i_IF_read_enable),
.i_IF_write_enable(i_IF_write_enable),
.i_IF_write_data(i_IF_write_data),
.i_IF_branch_addr(i_IF_branch_addr),
.i_IF_jump_addr(i_IF_jump_addr),
.i_IF_data_last_register(i_IF_data_last_register),
.o_IF_adder_result(o_IF_adder_result),
.o_IF_instruction(o_IF_instruction)
);
initial begin
begin
i_clock = 0;
i_IF_pc_reset = 1'b1;
i_IF_branch = 1'b0;
i_IF_j_jal = 1'b0;
i_IF_jr_jalr = 1'b0;
i_IF_write_enable = 1'b0;
i_IF_write_data = {NB_MEM_WIDTH{1'b0}}; // DEBUG UNIT
i_IF_branch_addr = 32'h4;
i_IF_jump_addr = 32'h3;
i_IF_data_last_register = 32'h2;
#40 i_IF_read_enable = 1'b1;
// PC + 1
#40 i_IF_pc_reset = 1'b0;
i_IF_pc_enable = 1'b1;
// branch addr
#40 i_IF_branch = 1'b1;
// j/jal addr
#40 i_IF_j_jal = 1'b1;
// jr/jalrl addr
#40 i_IF_jr_jalr = 1'b1;
#1000 $finish;
end
end
always #5 i_clock = !i_clock;
endmodule
| 6.51731 |
module tb_iic_controller;
reg clk;
reg rst_n;
wire scl;
wire sda;
pullup (scl);
pullup (sda);
reg soc;
reg [ 9:0] sclDiv;
//master
wire [ 7:0] iic_rdms;
wire [ 7:0] iic_rdls;
wire iic_ack;
//slaver
reg [15:0] SwriteData;
wire [ 7:0] SreadData;
wire SwriteOK;
wire SreadOK;
wire SnackError;
wire occupt;
iic_controller uut_iic_tem_controller (
.clk(clk),
.rst_n(rst_n),
.en(soc),
.DEVICE_WRADD(8'h80),
.DEVICE_RDADD(8'h81),
.DEVICE_SDCMD(8'he3),
.iic_rdms(iic_rdms),
.iic_rdls(iic_rdls),
.iic_ack(iic_ack),
.scl(scl),
.sda(sda)
);
iic_slaver_controller u_iic_slaver_controller (
.clk (clk),
.rst_n(rst_n),
.addr (7'b1000_000),
.scl(scl),
.sda(sda),
.writeData(SwriteData),
.writeOK (SwriteOK),
.readData(SreadData),
.readOK (SreadOK),
.nackError(SnackError),
.occupt(occupt)
);
parameter clkperiod = 6'd10;
initial begin
// Initialize Inputs
rst_n = 1'b0;
clk = 1'b1;
//master
sclDiv = 10'd512;
soc = 1'b0;
//slaver
SwriteData = 8'h00;
// Wait 100 ns for global reset to finish
#(clkperiod * sclDiv * 2) rst_n = 1'b1;
#(clkperiod * sclDiv * 4) #(clkperiod * sclDiv * 3) soc = 1'b1;
#(clkperiod * sclDiv * 3) SwriteData <= 16'hc2;
#(clkperiod * sclDiv * 10) soc = 1'b0;
#(clkperiod * sclDiv * 20)
// //
// addr = 7'b101_1001;
// MwriteData <= 8'ha1;
// #(clkperiod*sclDiv*3)
// soc = 1'b1;
// #(clkperiod*sclDiv*3)
// MwriteData <= 8'ha2;
// #(clkperiod*sclDiv*20)
// soc = 1'b0;
// #(clkperiod*sclDiv*20)
$finish;
end
always #(clkperiod / 2) clk <= ~clk;
initial begin
$dumpfile("controller_test.vcd");
$dumpvars(0, tb_iic_controller);
end
endmodule
| 6.574125 |
module tb_iic_test ();
reg sys_clk; //100M
reg rst_n;
reg [31:0] i_cfg_dat;
reg i_cfg_start_en;
wire iic_sda;
wire iic_scl;
iic_test u_iic_test (
.sys_clk (sys_clk), //100M
.rst_n (rst_n),
.i_cfg_dat (i_cfg_dat),
.i_cfg_start_en(i_cfg_start_en),
.iic_scl (iic_scl),
.iic_sda (iic_sda),
.o_rd_dat ()
);
initial begin
sys_clk = 'd0;
rst_n = 1'b0;
i_cfg_start_en = 'd0;
i_cfg_dat = 32'b1010_1110_1110_0110_1010_1101_1110_0001;
#100 rst_n = 1'b1;
#10 i_cfg_start_en = 'd1;
#10 i_cfg_start_en = 'd0;
#700000 i_cfg_dat = 32'b1010_1110_1110_0110_0000_0000_1010_0101;
#10 i_cfg_start_en = 'd1;
#10 i_cfg_start_en = 'd0;
#700000 i_cfg_dat = 32'b1010_1110_1110_0110_1010_1101_1110_0001;
#10 i_cfg_start_en = 'd1;
#10 i_cfg_start_en = 'd0;
end
always #5 sys_clk = ~sys_clk;
endmodule
| 6.627936 |
module data_mem_imre #(
parameter DATA_WIDTH = 100,
parameter WORD_WIDTH = 180
) (
clk,
rst_n,
wen,
waddr,
wdata,
ren,
raddr,
rdata
);
parameter ADDR_WIDTH = $clog2(WORD_WIDTH); //9
input wen, ren, clk, rst_n;
input [(ADDR_WIDTH-1):0] waddr, raddr;
input [(DATA_WIDTH-1):0] wdata;
output [(DATA_WIDTH-1):0] rdata;
integer i;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[WORD_WIDTH-1:0];
assign rdata = (ren) ? ram[raddr] : 0;
// Port A
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
ram[i] <= 0;
end
end else begin
if (wen) begin
ram[waddr] <= wdata;
end
end
end
endmodule
| 8.169423 |
module tb_iir;
wire CLK_i;
wire RST_n_i;
wire [8:0] DIN_i;
wire VIN_i;
wire [8:0] B0_i;
wire [8:0] B1_i;
wire [8:0] B2_i;
wire [8:0] A1_i;
wire [8:0] A2_i;
wire VOUT_i;
wire [8:0] DOUT_i;
wire SMPL_END_i;
wire END_SIM_i;
clk_gen CG (
.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i)
);
data_maker DM (
.CLK(CLK_i),
.RST_n(RST_n_i),
.SMPL_END(SMPL_END_i),
.VOUT(VIN_i),
.DOUT(DIN_i),
.B0(B0_i),
.B1(B1_i),
.B2(B2_i),
.A1(A1_i),
.A2(A2_i)
);
IIR_FILTER UUT (
.clk(CLK_i),
.rst_n(RST_n_i),
.din(DIN_i),
.vin(VIN_i),
.b0(B0_i),
.b1(B1_i),
.b2(B2_i),
.a1(A1_i),
.a2(A2_i),
.dout(DOUT_i),
.vout(VOUT_i)
);
data_sink DS (
.CLK(CLK_i),
.RST_n(RST_n_i),
.VIN(VOUT_i),
.SMPL_END(SMPL_END_i),
.DIN(DOUT_i),
.END_SIM(END_SIM_i)
);
endmodule
| 7.404479 |
module tb_iir_adv;
wire CLK_i;
wire RST_n_i;
wire [10:0] DIN_i;
wire VIN_i;
wire [10:0] B0_i;
wire [10:0] B1_i;
wire [10:0] B2_i;
wire [10:0] A1_i;
wire [10:0] A2_i;
wire [10:0] A1_NEG_i;
wire [10:0] A1_2_A2_i;
wire [10:0] A1A2_i;
wire VOUT_i;
wire [10:0] DOUT_i;
wire SMPL_END_i;
wire END_SIM_i;
clk_gen CG (
.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i)
);
data_maker_adv DM (
.CLK(CLK_i),
.RST_n(RST_n_i),
.SMPL_END(SMPL_END_i),
.VOUT(VIN_i),
.DOUT(DIN_i),
.B0(B0_i),
.B1(B1_i),
.B2(B2_i),
.A1_NEG(A1_NEG_i),
.A1_2_A2(A1_2_A2_i),
.A1A2(A1A2_i)
);
IIR_FILTER_ADV UUT (
.clk(CLK_i),
.rst_n(RST_n_i),
.din(DIN_i),
.vin(VIN_i),
.b0(B0_i),
.b1(B1_i),
.b2(B2_i),
.a1_neg(A1_NEG_i),
.a1_2_a2(A1_2_A2_i),
.a1a2(A1A2_i),
.dout(DOUT_i),
.vout(VOUT_i)
);
data_sink_adv DS (
.CLK(CLK_i),
.RST_n(RST_n_i),
.VIN(VOUT_i),
.SMPL_END(SMPL_END_i),
.DIN(DOUT_i),
.END_SIM(END_SIM_i)
);
endmodule
| 7.325604 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.
// If not, see <https://www.gnu.org/licenses/>
////////////////////////////////////////////////////////////////////////////////
module tb_IIR_Mcascaded ;
parameter WIX=3,
WFX=7,
WIS=5,
WFS=11,
WIC=2,
WFC=8,
WIO=14,
WFO=24,
N=8;
// Inputs
//reg [(WIX+WFX+WIS+WFS-1):0] X;
reg [(WIX+WFX-1):0] X;
reg CLK;
reg RESET;
reg CE;
// Outputs
wire [(WIO+WFO-1):0] Y;
wire overflow;
real in1_real,out_real;
function real fixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx<WI+WF-1;idx = idx+1)begin
if(in[idx] == 1'b1)begin
retVal = retVal + (2.0**(idx-WF));
end
end
fixedToFloat = retVal -(in[WI+WF-1]*(2.0**(WI-1)));
end
endfunction
// Instantiate the Unit Under Test (UUT)
IIR_Mcascaded #(.WIX(WIX),.WFX(WFX),.WIC(WIC),. WFC( WFC),.WIS(WIS),.WFS(WFS),.WIO(WIO),.WFO(WFO),.N(N)) uut1 (
.X(X),
.CE(CE),
.CLK(CLK),
.RESET(RESET),
.Y(Y),
.overflow(overflow)
);
parameter clockperiod = 20;
initial CLK = 0;
always #(clockperiod/2) CLK = ~ CLK;
parameter data_width = 10;
parameter addr_width = 50;
reg [(data_width-1):0] rom [addr_width-1:0];
reg [(WIC+WFC)-1 : 0 ] filter_coef [0 : 23];
integer j = 0;
initial begin
$readmemb ("input.txt",rom);
$readmemb ("filtercoeff.txt",filter_coef);
for (j = 0; j <= 5; j = j + 1)
begin
tb_IIR_Mcascaded.uut1.xi[0].SOSi.SOS_filter_coef[j] = filter_coef[j];
end
for (j = 0; j <= 5; j = j + 1)
begin
tb_IIR_Mcascaded.uut1.xi[1].SOSi.SOS_filter_coef[j] = filter_coef[(j+6)];
end
for (j = 0; j <= 5; j = j + 1)
begin
tb_IIR_Mcascaded.uut1.xi[2].SOSi.SOS_filter_coef[j] = filter_coef[(j+12)];
end
for (j = 0; j <= 5; j = j + 1)
begin
tb_IIR_Mcascaded.uut1.xi[3].SOSi.SOS_filter_coef[j] = filter_coef[(j+18)];
end
end
integer i;
initial begin
X = 0;
RESET = 0;
CE = 0;
@(posedge CLK) RESET = 0; CE = 0;
@(posedge CLK) RESET = 0; CE = 0;
@(posedge CLK) RESET = 0; CE = 1;
@(posedge CLK) RESET = 0; CE = 1;
@(posedge CLK) RESET = 0; CE = 1;
@(posedge CLK) RESET = 1;
for (i = 0; i <= 49 ; i = i + 1 )begin
@(posedge CLK) X = rom[i];
$display (fixedToFloat(Y,WIO,WFO));
//$display (fixedToFloat(X,WIX,WFX));
end
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
$finish;
end
always @ X in1_real = fixedToFloat(X,WIX,WFX);
always @ Y out_real = fixedToFloat(Y,WIO,WFO);
endmodule
| 7.743492 |
module tb_image_src ();
parameter H_Active = 1920;
parameter H_FrontPorch = 88;
parameter H_SyncWidth = 44;
parameter H_BackPorch = 148;
parameter V_Active = 1080;
parameter V_FrontPorch = 4;
parameter V_SyncWidth = 5;
parameter V_BackPorch = 36;
parameter Frame_cnt = 10;
parameter Frame_bpp = 24;
parameter Frame_src = "../../../../viewer/txt_i/2.txt";
reg pix_clk;
reg rst_n;
wire vs;
wire hs;
wire de;
wire [Frame_bpp -1:0] image_data;
always #3 pix_clk = ~pix_clk;
initial begin
pix_clk <= 1'b1;
rst_n <= 1'b0;
#100 rst_n <= 1'b1;
end
image_src #(
.H_Active(H_Active),
.H_FrontPorch(H_FrontPorch),
.H_SyncWidth(H_SyncWidth),
.H_BackPorch(H_BackPorch),
.V_Active(V_Active),
.V_FrontPorch(V_FrontPorch),
.V_SyncWidth(V_SyncWidth),
.V_BackPorch(V_BackPorch),
.Frame_cnt(Frame_cnt),
.Frame_bpp(Frame_bpp),
.Frame_src(Frame_src)
) inst_image_src (
.pix_clk (pix_clk),
.rst_n (rst_n),
.vs (vs),
.hs (hs),
.de (de),
.image_data(image_data)
);
endmodule
| 7.435333 |
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