code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_distance_detection;
reg CLK, RST, front, rear;
reg [4:0] distance;
wire [4:0] front_distance, rear_distance;
distance_detection DUT (
.CLK(CLK),
.RST(RST),
.front(front),
.rear(rear),
.distance(distance),
.front_distance(front_distance),
.rear_distance(rear_distance)
);
initial begin
CLK = 1'b0;
RST = 1'b1;
front = 1'b0;
rear = 1'b0;
distance = 5'b00000; // Nothing within range of front or back of car.
#10 CLK = 1'b1;
RST = 1'b0;
front = 1'b1; // Something comes within 20 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01111; // Thing is now within 15 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01010; // Thing is now within 10 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00101; // Thing is now within 5 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00100; // Thing is now within 4 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00101; // Thing is now within 5 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01010; // Thing is now within 10 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01111; // Thing is now within 15 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b10100; // Thing is now within 20 feet of front of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00000; // Thing is now out of range of front of car.
#10 CLK = 1'b0;
RST = 1'b1;
front = 1'b0; // Nothing within range of front of car.
#10 CLK = 1'b1;
RST = 1'b0;
rear = 1'b1; // Something comes within 20 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01111; // Thing is now within 15 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01010; // Thing is now within 10 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00101; // Thing is now within 5 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00100; // Thing is now within 4 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00101; // Thing is now within 5 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01010; // Thing is now within 10 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b01111; // Thing is now within 15 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b10100; // Thing is now within 20 feet of rear of car.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
distance = 5'b00000; // Thing is now out of range of rear of car.
#10 CLK = 1'b0;
RST = 1'b1;
rear = 1'b0; // Nothing within range of rear of car.
#10 CLK = 1'b1;
RST = 1'b0;
#10 CLK = 1'b0;
#5 $finish;
end
endmodule
| 7.024912 |
module tb_divider_4over1;
reg enable, clk, reset_n, accept_in;
wire accept_out, ready_out;
//
reg [63:0] Q;
reg [15:0] M;
wire [63:0] quot;
divider_4over1 uut (
enable,
clk,
reset_n,
accept_in,
accept_out,
ready_out,
Q,
M,
quot
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset_n = 0;
@(negedge clk);
reset_n = 1;
end
initial begin
enable = 1;
accept_in = 1;
end
reg [63:0] inQ[0 : 1];
reg [15:0] inM[0 : 1];
initial begin
inQ[0] = 64'b0000100010100011000001110000101000001000010100010000011001100110;
inQ[1] = 64'b0000011100001010000001100110011000000111110101110000011101011100;
inM[0] = 16'b0011001100110011; //3.2
inM[1] = 16'b0101000000000000; //5
end
reg i = 0;
always @(accept_out) begin
if (accept_out) begin
Q = inQ[i];
M = inM[i];
i = i + 1;
end
end
endmodule
| 6.97433 |
module tb_divider_5 ();
reg sys_clk;
reg sys_rst_n;
wire clk_flag;
//初始化时钟 复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk <= ~sys_clk;
divider_5 divider_5_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.clk_flag(clk_flag) //因为使用always进行赋值，所以使用reg
);
endmodule
| 7.540646 |
module tb_divider_6 ();
reg sys_clk;
reg sys_rst_n;
wire clk_flag;
//初始化时钟 复位
initial begin
sys_clk = 1'b1;
sys_rst_n = 1'b0;
#20 sys_rst_n = 1'b1;
end
always #10 sys_clk <= ~sys_clk;
divider_6 divider_6_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.clk_flag(clk_flag) //因为使用always进行赋值，所以使用reg
);
endmodule
| 7.605545 |
module tb_divider_clock (
tb_status,
referenceCLK,
CLK,
pulseOffset,
pulseWidth,
divisor,
delay1_bits,
delay2_bits,
state1,
state2
);
parameter initialize = 0;
parameter initialReferenceClkState = 1;
input [1:0] tb_status;
input referenceCLK;
output CLK;
input [31:0] pulseOffset;
input [31:0] pulseWidth;
input [31:0] divisor;
input [63:0] delay1_bits;
input [63:0] delay2_bits;
input state1;
input state2;
reg CLK;
integer tb_EdgeCount;
real delay1;
real delay2;
integer secondPulseWidth;
always begin : CLK_process
@(posedge tb_status[0]) delay1 = $bitstoreal(delay1_bits);
delay2 = $bitstoreal(delay2_bits);
secondPulseWidth = (divisor * 2 - pulseWidth);
if (divisor < 1) begin
$display("Error: Divisor for clock %m is invalid (divisor=%d). Clock will not be driven",
divisor);
end
// drive initial value
CLK <= state2;
// wait for reference clock to start
while (referenceCLK !== initialReferenceClkState) @(referenceCLK);
// wait for pulse offset
tb_EdgeCount = 0;
while (tb_EdgeCount < pulseOffset) begin
@(referenceCLK);
if (referenceCLK !== 1'bx) tb_EdgeCount = tb_EdgeCount + 1;
end
while (tb_status[0] === 1'b1) begin
// drive the first half of the cycle
if (delay1 > 0) CLK <= #(delay1) state1;
else CLK <= state1;
tb_EdgeCount = 0;
while (tb_EdgeCount < pulseWidth) begin
@(referenceCLK);
if (referenceCLK !== 1'bx) tb_EdgeCount = tb_EdgeCount + 1;
end
// drive the second half of the cycle
if (delay2 > 0) CLK <= #(delay2) state2;
else CLK <= state2;
tb_EdgeCount = 0;
while (tb_EdgeCount < secondPulseWidth) begin
@(referenceCLK);
if (referenceCLK !== 1'bx) tb_EdgeCount = tb_EdgeCount + 1;
end
end
end
endmodule
| 7.188607 |
module tb_divider_five ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_out;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//**************************** Instantiate ***************************//
//********************************************************************//
//------------- divider_five_inst --------------
divider_five divider_five_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.clk_out(clk_out) //output clk_out
);
endmodule
| 7.680233 |
module tb_divider_for_defog;
reg [7:0] t2;
reg [11:0] dividend;
reg clk;
reg nrst;
wire [7:0] quotient;
initial begin
nrst = 1'b0;
clk = 1'b0;
dividend = 12'd4095;
t2 = 8'd188;
#5 nrst = 1'b1;
#100 t2 = 8'd103;
#100 t2 = 8'd44;
end
always #5 clk = !clk;
divider_for_defog u0 (
.t2(t2),
.dividend(dividend),
.clk(clk),
.nrst(nrst),
.quotient(quotient)
);
endmodule
| 6.676391 |
module tb_divider_six ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_out;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//**************************** Instantiate ***************************//
//********************************************************************//
//------------- divider_six_inst -------------
divider_six divider_six_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.clk_out(clk_out) //output clk_out
);
endmodule
| 7.970112 |
module tb_divrem ();
reg clk, cpurst, diven_p;
initial begin
$fsdbDumpfile("divrem.fsdb");
$fsdbDumpvars;
//
clk = 1'b0;
diven_p = 1'b0;
cpurst = 1'b1;
#1000;
cpurst = 1'b0;
#1000;
@(posedge clk);
#1;
diven_p = 1'b1;
@(posedge clk);
#1;
diven_p = 1'b0;
#100000;
$finish;
end
always #10 clk = ~clk;
divrem_top divrem_top_u (
.clk (clk),
.cpurst (cpurst),
.divider (32'hffffffff),
.dividend (32'h80000000),
.diven_p (diven_p),
.divsigned(1'b1)
);
endmodule
| 7.460354 |
module tb_div_89;
// div_89 Parameters
parameter PERIOD = 10;
// div_89 Inputs
reg clk = 0;
reg rst_n = 0;
reg MC = 0;
// div_89 Outputs
wire f45;
wire f89;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
div_89 u_div_89 (
.clk (clk),
.rst_n(rst_n),
.MC (MC),
.f45(f45),
.f89(f89)
);
initial begin
MC = 0;
#(PERIOD * 100);
MC = 1;
#(PERIOD * 100);
$finish;
end
endmodule
| 6.512217 |
module tb_div_by3 ();
reg clk_in;
reg reset_n;
wire clk_out;
div_by3 div_by3_i (
.clk_in (clk_in),
.reset_n(reset_n),
.clk_out(clk_out)
);
always begin
#5 clk_in = ~clk_in;
end
initial begin
clk_in = 1'b0;
reset_n = 1'b0;
#10;
reset_n = 1'b1;
#200000;
$finish();
end
endmodule
| 6.612358 |
module tb_div_by_two ();
reg clk_in;
reg reset_n;
wire clk_out;
div_by_two div_by_two_i (
.clk_in (clk_in),
.reset_n(reset_n),
.clk_out(clk_out)
);
always begin
#10 clk_in = ~clk_in;
end
initial begin
clk_in = 1'b0;
reset_n = 1'b0;
#10;
reset_n = 1'b1;
#20000;
$finish();
end
endmodule
| 6.860617 |
module tb_dlatch; // TestBench of D-Latch
reg tb_clk, tb_d; // 2 inputs
wire tb_q, tb_q_bar; // use 2 wires
_dlatch U0_dlatch (
.clk(tb_clk),
.d(tb_d),
.q(tb_q),
.q_bar(tb_q_bar)
); //instance by using dlatch
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5;
end
initial begin
tb_d = 1'b1; // input(tb_d)=1
#10;
tb_d = 1'b0; // after 10ns, input(tb_d)=0
#10;
tb_d = 1'b1; // after 10ns, input(tb_d)=1
#10;
tb_d = 1'b0; // after 10ns, input(tb_d)=0
#10;
tb_d = 1'b1; // after 10ns, input(tb_d)=1
#10;
tb_d = 1'b0; // after 10ns, input(tb_d)=0
#10;
tb_d = 1'b1; // after 10ns, input(tb_d)=1
#10;
$stop; // after 10ns, stop
end
endmodule
| 7.181609 |
module dmaer (
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
always @(negedge rst_n) begin
disable main_loop;
req = 1'b0;
rnw = 1'b1;
inprogress = 1'b0;
end
always begin : main_loop
wait (rst_n);
wait (start);
begin : dma_loop
forever begin
inprogress <= 1'b1;
rnw <= rnw_in;
req <= 1'b1;
@(negedge ack);
if (!start) disable dma_loop;
end
end
req <= 1'b0;
wait (done); /*@(posedge done);*/
inprogress <= 1'b0;
end
endmodule
| 7.059175 |
module tb_dmac_1 (); //tb_dmac_1
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] data_count;
wire [2:0] next_state;
wire [31:0] din_src_addr, din_dest_addr, din_data_size;
wire [31:0] dout_src_addr, dout_dest_addr, dout_data_size;
//DMAC instance
DMAC_Top U0_dmac (
Clk,
reset_n,
M_grant,
M_din,
S_sel,
S_wr,
S_address,
S_din,
M_req,
M_wr,
M_address,
M_dout,
S_dout,
Interrupt,
next_state,
wr_en,
rd_en,
data_count,
op_start,
op_done,
op_clear,
op_mode,
din_src_addr,
din_dest_addr,
din_data_size,
dout_src_addr,
dout_dest_addr,
dout_data_size
);
parameter STEP = 1; //clk parameter
always #(STEP) Clk = ~Clk; // clock period
initial begin
Clk = 1;
reset_n = 0;
M_grant = 0;
M_din = 0;
S_din = 0;
S_sel = 0;
S_wr = 0;
S_address = 8'h00;
#2 reset_n = 1;
#3 S_sel = 1;
S_address = 8'h00;
#2 S_wr = 1;
S_address = 8'h02;
S_din = 32'h00000001; //interrupt_en
#2 S_address = 8'h03;
S_din = 32'h0000000a; //source address
#2 S_address = 8'h04;
S_din = 32'h00000014; //destination address
#2 S_address = 8'h07;
S_din = 32'h00000004; //data size
#2 S_address = 8'h05;
S_din = 32'h00000001; //fifo push
#2 S_address = 8'h08;
S_din = 32'h00000003; //op_mode
#2 S_address = 8'h01;
S_din = 32'h00000001; //op_start
#2 S_sel = 0;
S_wr = 0;
#10 M_grant = 1; //Bus request
#3 M_din = 32'd100; //M_din write
#4 M_din = 32'd200; //..
#4 M_din = 32'd300; //..
#4 M_din = 32'd400; //..
#5 S_sel = 1;
S_wr = 1;
S_address = 8'h00;
S_din = 32'h00000001; //op_clear
#3 S_wr = 0;
S_address = 8'h08; //op_mode read
#2 S_address = 8'h07; //data size read
#2 S_address = 8'h06; //descriptor size read
#2 S_address = 8'h03; //source address read
#4 $stop;
end
endmodule
| 6.711455 |
module tb_dmac_2 (); //tb_dmac_2
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] data_count;
wire [2:0] next_state;
wire [31:0] din_src_addr, din_dest_addr, din_data_size;
wire [31:0] dout_src_addr, dout_dest_addr, dout_data_size;
//DMAC_TOP instance
DMAC_Top U0_dmac (
Clk,
reset_n,
M_grant,
M_din,
S_sel,
S_wr,
S_address,
S_din,
M_req,
M_wr,
M_address,
M_dout,
S_dout,
Interrupt,
next_state,
wr_en,
rd_en,
data_count,
op_start,
op_done,
op_clear,
op_mode,
din_src_addr,
din_dest_addr,
din_data_size,
dout_src_addr,
dout_dest_addr,
dout_data_size
);
parameter STEP = 1; //clk parameter
always #(STEP) Clk = ~Clk; // clock period
initial begin
Clk = 1;
reset_n = 0;
M_grant = 0;
M_din = 0;
S_din = 0;
S_sel = 0;
S_wr = 0;
S_address = 8'h00; //reset all
#2 reset_n = 1; //reset inactive
#3 S_sel = 1;
S_address = 8'h00;
#2 S_wr = 1;
S_address = 8'h02;
S_din = 32'h00000001; //interrupt_en
#2 S_address = 8'h03;
S_din = 32'h0000000a; //source address
#2 S_address = 8'h04;
S_din = 32'h00000014; //destination address
#2 S_address = 8'h07;
S_din = 32'h00000004; //data size
#2 S_address = 8'h05;
S_din = 32'h00000001; //fifo push
#2 S_address = 8'h08;
S_din = 32'h00000007; //op_mode zero initialize
#2 S_address = 8'h01;
S_din = 32'h00000001; //op_start
#2 S_sel = 0;
S_wr = 0;
#10 M_grant = 1; //bus request
#3 M_din = 32'd100; //M_din write
#4 M_din = 32'd200; //..
#4 M_din = 32'd300; //..
#4 M_din = 32'd400; //..
#5 S_sel = 1;
S_wr = 1;
S_address = 8'h00;
S_din = 32'h00000001; //op_cleaer
#3 S_wr = 0;
S_address = 8'h08; //op_mode read
#2 S_address = 8'h07; //data size read
#2 S_address = 8'h06; //descriptor size read
#2 S_address = 8'h03; //source address read
#4 $stop;
end
endmodule
| 6.679944 |
module tb_dmac_3 (); //tb_dmac_3
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] data_count;
wire [2:0] next_state;
wire [31:0] din_src_addr, din_dest_addr, din_data_size;
wire [31:0] dout_src_addr, dout_dest_addr, dout_data_size;
//DMAC_Top instance
DMAC_Top U0_dmac (
Clk,
reset_n,
M_grant,
M_din,
S_sel,
S_wr,
S_address,
S_din,
M_req,
M_wr,
M_address,
M_dout,
S_dout,
Interrupt,
next_state,
wr_en,
rd_en,
data_count,
op_start,
op_done,
op_clear,
op_mode,
din_src_addr,
din_dest_addr,
din_data_size,
dout_src_addr,
dout_dest_addr,
dout_data_size
);
parameter STEP = 1; //clk parameter
always #(STEP) Clk = ~Clk; // clock period
initial begin
Clk = 1;
reset_n = 0;
M_grant = 0;
M_din = 0;
S_din = 0;
S_sel = 0;
S_wr = 0;
S_address = 8'h00; //reset all
#2 reset_n = 1; //reset inactive
#3 S_sel = 1;
S_address = 8'h00;
#2 S_wr = 1;
S_address = 8'h02;
S_din = 32'h00000001; //interrupt_en
#2 S_address = 8'h03;
S_din = 32'h0000000a; //src addr
#2 S_address = 8'h04;
S_din = 32'h00000014; //dest addr
#2 S_address = 8'h07;
S_din = 32'h00000004; //data size
#2 S_address = 8'h05;
S_din = 32'h00000001; //fifo push
#2 S_address = 8'h03;
S_din = 32'h0000001e; //src addr
#2 S_address = 8'h04;
S_din = 32'h00000028; //dest addr
#2 S_address = 8'h07;
S_din = 32'h00000004; //data size
#2 S_address = 8'h05;
S_din = 32'h00000001; //fifo push
#2 S_address = 8'h03;
S_din = 32'h00000028; //src addr
#2 S_address = 8'h04;
S_din = 32'h00000032; //dest addr
#2 S_address = 8'h07;
S_din = 32'h00000000; //data size
#2 S_address = 8'h05;
S_din = 32'h00000001; //fifo push
#2 S_address = 8'h08;
S_din = 32'h00000007; //op_mode
#2 S_address = 8'h01;
S_din = 32'h00000001; //op_start
#2 S_sel = 0;
S_wr = 0;
#10 M_grant = 1;
#80 S_sel = 1;
S_wr = 1;
S_address = 8'h00;
S_din = 32'h00000001; //op_clear
#3 S_wr = 0;
S_address = 8'h08; //op_mode read
#2 S_address = 8'h07; //data size read
#2 S_address = 8'h06; //descriptor size read
#2 S_address = 8'h03; //src addr read
#4 $stop;
end
endmodule
| 6.716693 |
module tb_DMAC_SLAVE;
reg clk, reset_n, opdone, s_sel, s_wr;
reg [15:0] s_addr;
reg [31:0] s_din;
wire [ 1:0] wr_en;
wire op_start, opdone_clear, s_interrupt;
wire [31:0] data_size;
wire [31:0] dest_addr, src_addr;
wire [ 1:0] opmode;
wire [31:0] s_dout;
DMAC_SLAVE U0_SLAVE (
clk,
reset_n,
opdone,
opdone_clear,
s_sel,
s_wr,
s_addr,
s_din,
wr_en,
data_size,
dest_addr,
src_addr,
s_interrupt,
s_dout,
op_start,
opmode
);
always #5 clk = ~clk;
initial begin
#0;
clk = 1;
reset_n = 0;
opdone = 0;
s_sel = 1;
s_wr = 0;
s_addr = 0;
s_din = 0;
#7;
reset_n = 1;
s_wr = 1;
s_din = 1; // op_start = 1;
#10;
s_addr = 1;
s_din = 1; // s_interrupt = 0;
#10;
s_addr = 2;
s_din = 1; // s_interrupt = 1;
#10;
s_addr = 3;
s_din = 32'h0001; // src_addr = 32'h0001;
#10;
s_addr = 4;
s_din = 32'h0002;
#10;
s_addr = 5;
s_din = 32'h0001;
#10;
s_addr = 6;
s_din = 32'h0001; // DEFAULT
#10;
s_addr = 7;
s_din = 32'h0001;
#10;
s_addr = 8;
s_din = 32'h0001; // DEFAULT
#10;
s_addr = 0;
s_wr = 0;
#10;
s_addr = 1;
#10;
s_addr = 2;
#10;
s_addr = 3;
#10;
s_addr = 4;
#10;
s_addr = 5;
#10;
s_addr = 6;
#10;
s_addr = 7;
#10;
s_addr = 8;
#10;
$stop;
end
endmodule
| 6.815496 |
module tb_dmx ();
reg sys_clk;
reg sys_rst;
/* 83.333MHz system clock */
initial sys_clk = 1'b0;
always #6 sys_clk = ~sys_clk;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do_tx;
wire [31:0] csr_do_rx;
wire dmx_signal;
dmx_tx #(
.csr_addr(4'h0),
.clk_freq(83333333)
) tx_dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_do(csr_do_tx),
.csr_di(csr_di),
.thru(1'b0),
.tx (dmx_signal)
);
dmx_rx #(
.csr_addr(4'h1),
.clk_freq(83333333)
) rx_dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_do(csr_do_rx),
.csr_di(csr_di),
.rx(dmx_signal)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do_tx | csr_do_rx);
end
endtask
always begin
$dumpfile("dmx.vcd");
$dumpvars(0, tx_dut);
$dumpvars(0, rx_dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
waitclock;
sys_rst = 1'b0;
waitclock;
csrread(32'h0000);
csrwrite(32'h0000, 32'hff);
csrread(32'h0000);
#1000000;
csrread(32'h1000);
csrread(32'h1004);
#50000000;
$finish;
end
endmodule
| 7.504928 |
module tb_DPD ();
localparam M = 3;
localparam MEMORY_DEPTH = 32768; // 激励数据的深度
localparam DATA_WIDTH = 32; // 包含实部与虚部
localparam LUT_DEPTH = 4096;
reg JESD_clk = 0;
reg AXI_clk = 0;
reg reset = 0;
reg [ 31:0] coeff = 32'hAAAAAAAA;
reg [$clog2(LUT_DEPTH*(M+1))-1:0] coeff_addr = 'd0;
reg coeff_en = 1'b1;
reg [ 127:0] dac; // 包含4个DAC数据
wire [ 127:0] dpd;
reg [ 31:0] lut;
reg [ $clog2(MEMORY_DEPTH/4)-1:0] counter_dac = 'd0;
reg [ 127:0] dac_data [ 0:MEMORY_DEPTH-1];
reg [ 31:0] dpd_data [ 0:MEMORY_DEPTH-1];
reg [ 31:0] lut_data [0:LUT_DEPTH*(M+1)-1];
wire [ 15:0] dpd_i_sample0;
wire [ 15:0] dpd_i_sample1;
wire [ 15:0] dpd_i_sample2;
wire [ 15:0] dpd_i_sample3;
wire [ 15:0] dpd_q_sample0;
wire [ 15:0] dpd_q_sample1;
wire [ 15:0] dpd_q_sample2;
wire [ 15:0] dpd_q_sample3;
always #2.035 JESD_clk = ~JESD_clk;
always #2 AXI_clk = ~AXI_clk;
assign dpd_i_sample0 = {dpd[0+:8], dpd[32+:8]};
assign dpd_q_sample0 = {dpd[64+:8], dpd[96+:8]};
assign dpd_i_sample1 = {dpd[8+:8], dpd[40+:8]};
assign dpd_q_sample1 = {dpd[72+:8], dpd[104+:8]};
assign dpd_i_sample2 = {dpd[16+:8], dpd[48+:8]};
assign dpd_q_sample2 = {dpd[80+:8], dpd[112+:8]};
assign dpd_i_sample3 = {dpd[24+:8], dpd[56+:8]};
assign dpd_q_sample3 = {dpd[88+:8], dpd[120+:8]};
integer outfile;
integer number = 0;
// 读取输入数据
initial begin
// 修改下面文件的命名
// 需要将dat或txt文件用vivado添加为simulation source，就无需指定相对路径，否则会在.sim\sim_1\behav\xsim下
// 实测时发现每次还是要从xsim复制走，所以用绝对路径最好
outfile = $fopen("D:/Documents/Matlab/for_FPGA/TB_DPD.dat", "w");
if (outfile == 0) begin
$display("Error: File, output file could not be opened.\nExiting Simulation.");
$finish;
end
// 读取输入文件的值，16进制或2进制
// $readmemh("input.dat", input_data, 0, MEMORY_DEPTH-1);
// 用绝对路径最好，相对路径添加source后就会被复制到xsim文件夹下，后面在matlab里修改没用
$readmemb("D:/Documents/Matlab/for_FPGA/TB_DAC.dat", dac_data, 0, MEMORY_DEPTH / 4 - 1);
$readmemb("D:/Documents/Matlab/for_FPGA/TB_LUT.dat", lut_data, 0, LUT_DEPTH * (M + 1) - 1);
// 将Data_out写入文件
@(coeff_addr == LUT_DEPTH * (M + 1) - 1);
#100
while (number != MEMORY_DEPTH / 4) begin
@(posedge JESD_clk) begin
// 注意是fdisplay不是display
$fdisplay(outfile, "%b", dpd);
number = number + 1;
end
end
// 等待1ms
#1000 $display("Simulation Ended Normally at Time: %t", $realtime);
$fclose(outfile);
$finish;
end
initial begin
@(coeff_addr == LUT_DEPTH * (M + 1) - 1);
while (1)
@(posedge JESD_clk) begin
dac <= dac_data[counter_dac];
counter_dac <= counter_dac + 1;
end
end
initial begin
lut = lut_data[0];
#100
while (coeff_addr != LUT_DEPTH * (M + 1) - 1) begin
@(posedge AXI_clk) begin
lut = lut_data[coeff_addr];
coeff_addr = coeff_addr + 1'b1;
coeff_en = 1'b1;
end
end
end
MP_LUT_wrapper #(
.M (M),
.RESOLUTION(LUT_DEPTH)
) DUT (
.JESD_clk_i (JESD_clk),
.AXI_clk_i (AXI_clk),
.reset_i (reset),
.coeff_i (lut),
.coeff_addr_i ({coeff_addr, 2'b0}),
.coeff_en_i (coeff_en),
.dac_i (dac),
.vio_wdpd_i (1'b1),
.LED_OVF (),
.data_o (dpd),
.sample0_i_ila(),
.sample0_r_ila()
);
endmodule
| 7.732496 |
module instantiation.
//
// Verilog Test Fixture created by ISE for module: DPSFnmCE
//
// Dependencies: None
//
// Revision:
//
// 0.01 07L22 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_DPSFmnCE_v;
// Inputs
reg Rst;
reg Clk;
reg WE;
reg RE;
reg [15:0] DI;
// Outputs
wire [15:0] DO;
wire FF;
wire EF;
wire HF;
wire [4:0] Cnt;
// Instantiate the Unit Under Test (UUT)
DPSFnmCE uut (
.Rst(Rst),
.Clk(Clk),
.WE(WE),
.RE(RE),
.DI(DI),
.DO(DO),
.FF(FF),
.EF(EF),
.HF(HF),
.Cnt(Cnt)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
WE = 0;
RE = 0;
DI = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Rst = 0;
FIFO_Wr(16'h1111);
FIFO_Wr(16'h2222);
FIFO_Wr(16'h3333);
FIFO_Wr(16'h4444);
FIFO_Wr(16'h5555);
FIFO_Wr(16'h6666);
FIFO_Wr(16'h7777);
FIFO_Wr(16'h8888);
FIFO_Wr(16'h9999);
FIFO_Wr(16'hAAAA);
FIFO_Wr(16'hBBBB);
FIFO_Wr(16'hCCCC);
FIFO_Wr(16'hDDDD);
FIFO_Wr(16'hEEEE);
FIFO_Wr(16'hFFFF);
FIFO_Wr(16'h0000);
FIFO_Rd;
FIFO_Wr(16'h0001);
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Wr(16'h0001);
FIFO_Wr(16'h0002);
FIFO_Wr(16'h0004);
FIFO_Wr(16'h0008);
FIFO_Wr(16'h0010);
FIFO_Wr(16'h0020);
FIFO_Wr(16'h0040);
FIFO_Wr(16'h0080);
FIFO_Wr(16'h0100);
FIFO_Wr(16'h0200);
FIFO_Wr(16'h0400);
FIFO_Wr(16'h0800);
FIFO_Wr(16'h1000);
FIFO_Wr(16'h2000);
FIFO_Wr(16'h4000);
FIFO_Wr(16'h8000);
FIFO_Wr(16'h8001);
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_RW(16'h8001);
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
FIFO_Rd;
end
always #5 Clk = ~Clk;
// FIFO Write Task
task FIFO_Wr;
input [15:0] Data;
begin
@(posedge Clk);
#1 WE = 1; DI = Data;
@(posedge Clk);
#1 WE = 0;
end
endtask
// FIFO Read Task
task FIFO_Rd;
begin
@(posedge Clk);
#1 RE = 1;
@(posedge Clk);
#1 RE = 0;
end
endtask
// FIFO Simultaneous Read/Write Task
task FIFO_RW;
input [15:0] Data;
begin
@(posedge Clk);
#1 WE = 1; RE = 1; DI = Data;
@(posedge Clk);
#1 WE = 0; RE = 0;
end
endtask
endmodule
| 6.950232 |
module tb_ds18b20 ();
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//wire define
wire stcp;
wire shcp;
wire ds;
wire oe;
wire dq;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//对sys_clk,sys_rst_n赋初始值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#100 sys_rst_n <= 1'b1;
end
//clk:产生时钟
always #10 sys_clk <= ~sys_clk;
//重新定义参数值，缩短仿真时间
defparam ds18b20_inst.ds18b20_ctrl_inst.S_WAIT_MAX = 750;
//-------------ds18b20_inst-------------
ds18b20 ds18b20_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低电平有效
.dq(dq), //数据总线
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //输出使能信号
);
endmodule
| 8.094535 |
module tb_DS192_sel;
wire write_en;
reg clk;
reg rst_n;
reg [16:0] pixel_counter;
wire [15:0] BRAMDATA;
wire [23:0] RGB_sep, RGB_com;
wire [15:0] RGB;
bufferram bufferram_i (
.addra(pixel_counter),
.douta(BRAMDATA)
);
RGB_separate RGB_separate_module (
.RGB_in(BRAMDATA),
.R (RGB_sep[23:16]),
.G (RGB_sep[15:8]),
.B (RGB_sep[7 : 0])
);
RGB_compress RGB_compress_module (
.R (RGB_com[23:16]),
.G (RGB_com[15:8]),
.B (RGB_com[7 : 0]),
.RGB_out(RGB)
);
genvar i;
generate
for (i = 23; i > 0; i = i - 8) begin : DS192_
DS192_sel DS192_module (
.clk(clk),
.rst_n(rst_n),
.din(RGB_sep[i:i-7]),
.dout(RGB_com[i:i-7]),
.write_en(write_en)
);
end
endgenerate
initial begin
rst_n = 0;
#30 rst_n = 1;
end
initial begin
clk = 0;
forever #40 clk = ~clk;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pixel_counter <= 0;
end else if (pixel_counter == 17'h1_0000) begin
$fclose(fd);
end else begin
pixel_counter <= pixel_counter + 1;
end
end
integer fd;
initial fd = $fopen("output 192.txt", "w");
always @(posedge clk) begin
if (pixel_counter != 17'h1_0000 && write_en) begin
$fwrite(fd, "%h\n", RGB);
end
end
endmodule
| 6.60598 |
module tb_DS64_sel;
wire write_en;
reg clk;
reg rst_n;
reg [16:0] pixel_counter;
wire [15:0] BRAMDATA;
wire [23:0] RGB_sep, RGB_com;
wire [15:0] RGB;
bufferram bufferram_i (
.addra(pixel_counter),
.douta(BRAMDATA)
);
RGB_separate RGB_separate_module (
.RGB_in(BRAMDATA),
.R (RGB_sep[23:16]),
.G (RGB_sep[15:8]),
.B (RGB_sep[7 : 0])
);
RGB_compress RGB_compress_module (
.R (RGB_com[23:16]),
.G (RGB_com[15:8]),
.B (RGB_com[7 : 0]),
.RGB_out(RGB)
);
genvar i;
generate
for (i = 23; i > 0; i = i - 8) begin : DS64_
DS64_sel DS64_module (
.clk(clk),
.rst_n(rst_n),
.din(RGB_sep[i:i-7]),
.dout(RGB_com[i:i-7]),
.write_en(write_en)
);
end
endgenerate
initial begin
rst_n = 0;
#30 rst_n = 1;
end
initial begin
clk = 0;
forever #40 clk = ~clk;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pixel_counter <= 0;
end else if (pixel_counter == 17'h1_0000) begin
$fclose(fd);
end else begin
pixel_counter <= pixel_counter + 1;
end
end
integer fd;
initial fd = $fopen("output 64.txt", "w");
always @(posedge clk) begin
if (pixel_counter != 17'h1_0000 && write_en) begin
$fwrite(fd, "%h\n", RGB);
end
end
endmodule
| 6.660945 |
module tb_dsu_tx(clk, rst, TxD_start, TxD_data, TxD, TxD_busy);
input clk, rst, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter Baud = 115200;
//parameter Baud = 9600;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef FPGA_50MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h00097; //for 115200 BPS at 50MHz.
`endif
`ifdef FPGA_32MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h000ec; //for 115200 BPS at 32MHZ
`endif
`ifdef FPGA_64MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h00076; //for 115200 BPS at 64MHZ
`endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
BaudGeneratorAcc <= 16'h0000;
else if(TxD_busy)
BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
end
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
TxD_dataReg <= 8'h00;
else if(TxD_ready & TxD_start)
TxD_dataReg <= TxD_data;
end
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
state <= 4'h0;
else
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
end
// Output mux
reg muxbit;
always @ ( * )
begin
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
end
// Put together the start, data and stop bits
reg TxD;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
TxD <= 1'b1;
else
TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
end
endmodule
| 7.481741 |
module tb_dual_div;
// dual_div Parameters
parameter PERIOD = 10;
parameter P_WIDTH = 5;
parameter S_WIDTH = 3;
// dual_div Inputs
reg clk = 0;
reg rst_n = 0;
reg [S_WIDTH-1:0] Si = 0;
reg [P_WIDTH-1:0] Pi = 0;
// dual_div Outputs
wire Fdiv;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
dual_div #(
.P_WIDTH(P_WIDTH),
.S_WIDTH(S_WIDTH)
) u_dual_div (
.clk (clk),
.rst_n(rst_n),
.Si (Si[S_WIDTH-1:0]),
.Pi (Pi[P_WIDTH-1:0]),
.Fdiv(Fdiv)
);
initial begin
Pi = 6'd16;
Si = 3'd4;
#(PERIOD * 1000);
$finish;
end
endmodule
| 7.047055 |
module : tb_dual_port_BRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_dual_port_BRAM();
parameter CORE = 0;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter SCAN_CYCLES_MIN = 0;
parameter SCAN_CYCLES_MAX = 1000;
reg clock;
reg reset;
// Port
reg readEnable_1;
reg writeEnable_1;
reg [ADDR_WIDTH-1:0] address_1;
reg [DATA_WIDTH-1:0] writeData_1;
wire [DATA_WIDTH-1:0] readData_1;
// Port 2
reg readEnable_2;
reg writeEnable_2;
reg [ADDR_WIDTH-1:0] address_2;
reg [DATA_WIDTH-1:0] writeData_2;
wire [DATA_WIDTH-1:0] readData_2;
reg scan;
dual_port_BRAM #(
.CORE(CORE),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) uut (
.clock(clock),
.reset(reset),
// Port
.readEnable_1(readEnable_1),
.writeEnable_1(writeEnable_1),
.address_1(address_1),
.writeData_1(writeData_1),
.readData_1(readData_1),
// Port 2
.readEnable_2(readEnable_2),
.writeEnable_2(writeEnable_2),
.address_2(address_2),
.writeData_2(writeData_2),
.readData_2(readData_2),
.scan(scan)
);
always #5 clock = ~clock;
initial begin
clock = 1'b1;
reset = 1'b1;
readEnable_1 = 1'b0;
writeEnable_1 = 1'b0;
address_1 = 0;
writeData_1 = 0;
readEnable_2 = 1'b0;
writeEnable_2 = 1'b0;
address_2 = 0;
writeData_2 = 0;
scan = 0;
repeat (1) @ (posedge clock);
reset = 1'b0;
repeat (1) @ (posedge clock);
writeEnable_1 = 1'b1;
address_1 = 0;
writeData_1 = 10;
writeEnable_2 = 1'b1;
address_2 = 1;
writeData_2 = 11;
repeat (1) @ (posedge clock);
#1 // Delay to ensure readData is checked after it is latched on the posedge clock
if( readData_1 != 0 |
readData_2 != 0 ) begin
$display("\nError: Unexpected read data during write!");
$display("\ntb_dual_port_BRAM --> Test Failed!\n\n");
$stop();
end
writeEnable_1 = 1'b0;
readEnable_1 = 1'b1;
writeEnable_2 = 1'b0;
readEnable_2 = 1'b1;
repeat (1) @ (posedge clock);
#1 // Delay to ensure readData is checked after it is latched on the posedge clock
if( readData_1 != 10 |
readData_2 != 11 ) begin
$display("\nError: Unexpected read data during read!");
$display("\ntb_dual_port_BRAM --> Test Failed!\n\n");
$stop();
end
$display("\ntb_dual_port_BRAM --> Test Passed!\n\n");
$stop();
end
endmodule
| 6.955551 |
module : tb_dual_port_RAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_dual_port_RAM();
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
INDEX_BITS = 4;
reg clock;
reg writeEnable_0, writeEnable_1;
reg [DATA_WIDTH-1:0] writeData_0;
reg [DATA_WIDTH-1:0] writeData_1;
reg [ADDRESS_WIDTH-1:0] address_0;
reg [ADDRESS_WIDTH-1:0] address_1;
wire [DATA_WIDTH-1:0] data_out0_old, data_out0_new;
wire [DATA_WIDTH-1:0] data_out1_old, data_out1_new;
//instantiate DUT
dual_port_RAM #(
DATA_WIDTH,
ADDRESS_WIDTH,
INDEX_BITS,
"OLD_DATA"
) DUT_OLD (
.clock(clock),
.writeEnable_0(writeEnable_0), .writeEnable_1(writeEnable_1),
.writeData_0(writeData_0),
.writeData_1(writeData_1),
.address_0(address_0),
.address_1(address_1),
.readData_0(data_out0_old),
.readData_1(data_out1_old)
);
dual_port_RAM #(
DATA_WIDTH,
ADDRESS_WIDTH,
INDEX_BITS,
"NEW_DATA"
) DUT_NEW (
.clock(clock),
.writeEnable_0(writeEnable_0), .writeEnable_1(writeEnable_1),
.writeData_0(writeData_0),
.writeData_1(writeData_1),
.address_0(address_0),
.address_1(address_1),
.readData_0(data_out0_new),
.readData_1(data_out1_new)
);
//generate clock
always #1 clock = ~clock;
//cycle counter
reg [31:0] cycles;
always @(posedge clock)begin
cycles <= cycles + 1;
end
//Test patterns
initial begin
clock = 0;
cycles = 0;
writeEnable_0 = 0;
writeEnable_1 = 0;
writeData_0 = 0;
writeData_1 = 0;
address_0 = 0;
address_1 = 0;
//write value
repeat(1) @(posedge clock);
@(posedge clock)begin
writeEnable_0 <= 1;
writeData_0 <= 8'h49;
address_0 <= 14;
end
//pass through behavior
@(posedge clock)begin
writeEnable_0 <= 0;
writeData_0 <= 0;
address_0 <= 14;
writeEnable_1 <= 1;
writeData_1 <= 8'h53;
address_1 <= 14;
end
@(posedge clock)begin
writeEnable_0 <= 0;
writeEnable_1 <= 0;
writeData_0 <= 0;
writeData_1 <= 0;
end
end
// Automatic checking code
initial begin
repeat(4) @(posedge clock);
if(data_out0_old != 8'h49 || data_out0_new != 8'h49)begin
$display("Cycle count = %d", cycles);
$display("\ntb_dual_port_RAM --> Test Failed!\n\n");
$stop;
end
repeat(1) @(posedge clock);
if(data_out0_old != 8'h49 || data_out0_new != 8'h53 || data_out1_old != 8'h53 ||
data_out1_new != 8'h53)begin
$display("Cycle count = %d", cycles);
$display("\ntb_dual_port_RAM --> Test Failed!\n\n");
$stop;
end
repeat(1) @(posedge clock);
if(data_out0_old != 8'h53 || data_out0_new != 8'h53 || data_out1_old != 8'h53 ||
data_out1_new != 8'h53)begin
$display("Cycle count = %d", cycles);
$display("\ntb_dual_port_RAM --> Test Failed!\n\n");
$stop;
end
repeat(1) @(posedge clock);
$display("\ntb_dual_port_RAM --> Test Passed!\n\n");
$stop;
end
endmodule
| 6.955551 |
module tb_dut_uart_txrx;
parameter c_CLOCK_PERIOD_NS = 10;
//parameter c_CLKS_PER_BIT = 868;
//The parameter c_BIT_PERIOD = 8600;
//not required
//parameter c_BIT_PERIOD = 8600;
//Used to generate 100MHz clock
//using the parameter c_CLOCK_PERIOD_NS = 10;
reg r_Clock = 0;
//Signal to start to the transfer on o_uart_tx
//During the transfer the o_TX_Active is hi
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
//Signal to map to o_uart_tx
wire w_TX_Serial;
//Signal to map to i_TX_Byte
reg [7:0] r_TX_Byte = 0;
//Signal to map to o_RX_Byte
wire [7:0] w_RX_Byte;
//for loop reg that allows
//clocks pass the detection of
//w_RX_Byte to see that the r_TX_Done
reg [7:0] r_loop = 0;
uart_rx dut_rx (
.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);
uart_tx dut_tx (
.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when
// UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;
//Used to generate 100MHz clock
//which drives the simulation
always #(c_CLOCK_PERIOD_NS / 2) r_Clock <= !r_Clock;
// Main Testing:
initial begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
// Check that the correct command was received
@(posedge w_RX_DV);
if (w_RX_Byte == 8'h3F) $display("Test Passed - Correct Byte Received");
else $display("Test Failed - Incorrect Byte Received");
//for loop reg that allows
//clocks pass the detection of
//w_RX_Byte to see that the r_TX_Done
//for (r_loop = 0; r_loop <= 1023 ; r_loop = r_loop + 1) begin
//@(posedge r_Clock);
//end
$finish();
end
initial begin
// Required to dump signals to EPWave
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
| 6.830521 |
module tb_dvi_demo ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #4 sys_clk = ~sys_clk;
//
// Ethernet Clock 125MHz
//
reg phy_clk;
initial phy_clk = 1'b0;
always #4 phy_clk = ~phy_clk;
//
// TMDS CLOCK 74.2MHz
//
reg tmds_clk;
initial tmds_clk = 1'b0;
always #6.734 tmds_clk = ~tmds_clk;
//
// Test Bench
//
reg sys_rst;
wire TXEN;
wire [7:0] TXD;
wire gtxclk;
wire phy_rst;
//-----------------------------------------------------------
// FIFO(48bit) to GMII
// Depth --> 4096
//-----------------------------------------------------------
wire full;
wire empty;
wire [47:0] tx_data;
wire rd_en;
reg [3:0] hsync, vsync;
wire hsyn = hsync[0];
wire vsyn = vsync[0];
reg [7:0] red, green, blue;
wire [47:0] din_fifo = {in_vcnt, in_hcnt, red, green, blue};
wire fifo_wr_en = (in_hcnt < 12'd1280 & in_vcnt < 12'd720) & video_en;
afifo48 asfifo (
.Data(din_fifo),
.WrClock(tmds_clk),
.RdClock(phy_clk),
.WrEn(fifo_wr_en),
.RdEn(rd_en),
.Reset(sys_rst),
.RPReset(),
.Q(tx_data),
.Empty(empty),
.Full(full)
);
// TMDS HSYNC VSYNC COUNTER ()
// (1280x720 progressive
// HSYNC: 45khz VSYNC : 60Hz)
//-----------------------------------------------------
wire [11:0] in_hcnt = {1'b0, video_hcnt[10:0]};
wire [11:0] in_vcnt = {1'b0, video_vcnt[10:0]};
wire [10:0] video_hcnt;
wire [10:0] video_vcnt;
wire video_en;
tmds_timing timing (
.rx0_pclk (tmds_clk),
.rstbtn_n (sys_rst),
.rx0_hsync (hsyn),
.rx0_vsync (vsyn),
.video_en (video_en),
.video_hcnt(video_hcnt),
.video_vcnt(video_vcnt)
);
gmii_tx gmii_tx (
/*** FIFO ***/
.fifo_clk(tmds_clk),
.sys_rst(sys_rst),
.dout(tx_data), //48bit
.empty(empty),
.full(full),
.rd_en(rd_en),
.wr_en(video_en),
/*** Ethernet PHY GMII ***/
.tx_clk(phy_clk),
.tx_en(TXEN),
.txd(TXD)
);
//
// a clock
//
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
//
// Scinario
//
reg [31:0] rom[0:2475000];
reg [21:0] counter = 22'd0;
always @(posedge tmds_clk) begin
{vsync, hsync, red, green, blue} <= rom[counter];
counter <= counter + 22'd1;
end
reg [11:0] hcnt;
always @(posedge tmds_clk) begin
if (in_hcnt == 0) hcnt <= hcnt + 1;
else hcnt <= in_hcnt;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_dvi_demo);
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
$readmemh("request.mem", rom);
counter = 0;
$readmemh("request.mem", rom);
counter = 0;
$readmemh("request.mem", rom);
#20000000;
$finish;
end
endmodule
| 8.210692 |
module tb ();
reg clk, nreset;
always begin
#5 clk = !clk;
end
// Declare dynamic array
reg [7:0] mem[];
initial begin
#10;
// Allocate array for 4 locations
$display("Setting array size to 4");
mem = new[4];
$display("Initial the array with default values");
for (int i = 0; i < 4; i++) begin
mem[i] = i;
end
// Doubling the size of array, with old content still valid
mem = new[8] (mem);
// Print current size
$display("Current array size is %d", mem.size());
//for (int i = 0; i < 4; i ++) begin
for (int i = 0; i < 8; i++) begin
$display("Value at location %g is %d ", i, mem[i]);
end
// Delete array
$display("Deleting the array");
mem.delete();
$display("Current array size is %d", mem.size());
#1 $finish;
end
endmodule
| 7.195167 |
module tb;
parameter BITS = 8;
reg clk, rst, valid, in;
reg [BITS-1 : 0] pattern;
wire out;
dyn_pattern_imp #(
.BITS(BITS)
) u0 (
.clk(clk),
.rst(rst),
.valid(valid),
.in(in),
.out(out),
.pattern(pattern)
);
always #1 clk = ~clk;
initial begin
clk = 0;
valid = 0;
in = 0;
pattern = 0;
rst = 1;
repeat (5) @(posedge clk);
rst = 0;
pattern = $random;
valid = 1;
repeat (300) begin
in = $random;
@(posedge clk);
end
valid = 0;
rst = 1;
repeat (10) @(posedge clk);
rst = 0;
repeat (5) @(posedge clk);
$finish;
end
endmodule
| 6.746419 |
module: D_FF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_D_FF;
// Inputs
reg arst;
reg clk;
reg en;
reg data;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
D_FF uut (
.arst(arst),
.clk(clk),
.en(en),
.data(data),
.out(out)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
arst = 1;
clk = 0;
en = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
arst = 0;
data = 1;
#100
en = 1;
#100
arst = 1;
#20
arst = 0;
#20
en = 0;
#80
data = 0;
// Add stimulus here
end
endmodule
| 7.281187 |
module tb_e213.v
Test bench for (2,1,3) efficient backward label Viterbi Decoder.
John O'Shea, joshea@emc.com
===========================================================================*/
`timescale 1 ns/1 ns
module tb_e213;
`include "params_e213.inc.v"
reg [`n-1:0] Rx_data [0:22];
reg [`n-1:0] Rx;
reg seq_ready;
reg clock;
reg reset;
wire [`k-1:0] Dx;
wire [63:0] HD;
wire sync_error;
wire oe;
integer i;
/*=== Instantiate efficient (2,1,3) decoder ===*/
eVITERBI_213 TB_U2 (.Dx(Dx), .oe(oe), .sync_error(sync_error), .Rx(Rx), .seq_ready(seq_ready), .clock(clock), .reset(reset));
/*=== Create Free Running Clock ===*/
always
begin
#(0.5*`CLOCK_PERIOD);
clock=~clock;
end
/*=== Load Test Vectors ===*/
initial
begin
Rx_data[0] = 2'b00;
Rx_data[1] = 2'b11;
Rx_data[2] = 2'b10;
Rx_data[3] = 2'b10;
Rx_data[4] = 2'b11;
Rx_data[5] = 2'b01;
Rx_data[6] = 2'b10;
Rx_data[7] = 2'b00;
Rx_data[8] = 2'b00;
Rx_data[9] = 2'b01;
Rx_data[10] = 2'b00;
Rx_data[11] = 2'b10;
Rx_data[12] = 2'b11;
Rx_data[13] = 2'b11;
Rx_data[14] = 2'b11;
Rx_data[15] = 2'b10;
Rx_data[16] = 2'b10;
Rx_data[17] = 2'b00;
Rx_data[18] = 2'b00;
Rx_data[19] = 2'b01;
Rx_data[20] = 2'b11;
Rx_data[21] = 2'b11;
Rx_data[22] = 2'b00;
end
/*=== Clock data into the decoder ===*/
initial
begin
clock = 0;
reset = 1; //Apply reset
#`CLOCK_PERIOD reset =0; //Disable reset after one clock period
seq_ready =1;
for (i=0; i<12; i=i+1)
begin
Rx=Rx_data[i];
#(`CLOCK_PERIOD*3);
end
// After 1st Traceback, clock in remaining bits after each traceback
for (i=12; i<30; i=i+1)
begin
Rx=Rx_data[i];
#(`CLOCK_PERIOD*15);
end
seq_ready =0;
end
/*=== Create Simulation Waveforms ===*/
initial
begin
$fsdbDumpfile("verilog.fsdb");// debussy dump format
$fsdbDumpStrength;
$fsdbDumpvars;
end
initial
#13000 $finish;
/*=== Monitor Viterbi Decoder Responses ===*/
initial
$monitor("time=%4g, clock=%b, Rx=%b, we=%b, te=%b, oe=%b, wptr=%h, tptr=%h, min_state=%b, tb_reg=%b,A_in=%h,P_in=%b,plabels=%b,Dx=%b, ns=%b",
$time,
clock,
Rx,
TB_U2.U3.we,
TB_U2.U3.te,
TB_U2.U3.oe,
TB_U2.U3.write_ptr,
TB_U2.U3.trace_ptr,
TB_U2.U3.min_state,
TB_U2.U3.tb_reg,
{TB_U2.U3.A0_in,
TB_U2.U3.A1_in,
TB_U2.U3.A2_in,
TB_U2.U3.A3_in,
TB_U2.U3.A4_in,
TB_U2.U3.A5_in,
TB_U2.U3.A6_in,
TB_U2.U3.A7_in},
{TB_U2.U3.P0_in,
TB_U2.U3.P1_in,
TB_U2.U3.P2_in,
TB_U2.U3.P3_in,
TB_U2.U3.P4_in,
TB_U2.U3.P5_in,
TB_U2.U3.P6_in,
TB_U2.U3.P7_in},
{TB_U2.U3.P0[`T-1],
TB_U2.U3.P1[`T-1],
TB_U2.U3.P2[`T-1],
TB_U2.U3.P3[`T-1],
TB_U2.U3.P4[`T-1],
TB_U2.U3.P5[`T-1],
TB_U2.U3.P6[`T-1],
TB_U2.U3.P7[`T-1]},
TB_U2.U3.Dx,
TB_U2.U3.NEXT_STATE
);
endmodule
| 7.003508 |
module tb_edge_det;
reg clk, rst_n, data;
wire rise_edge;
wire fall_edge;
wire data_edge;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(posedge clk) data = {$random};
end
$finish;
end
initial begin
$dumpfile("seq101_tb.vcd");
$dumpvars();
end
edge_det edge_det (
.clk (clk),
.rst_n (rst_n),
.data (data),
.rise_edge(rise_edge),
.fall_edge(fall_edge),
.data_edge(data_edge)
);
endmodule
| 6.661764 |
module tb_eeprom_byte_rd_wr ();
//wire define
wire scl;
wire sda;
wire stcp;
wire shcp;
wire ds;
wire oe;
//reg define
reg clk;
reg rst_n;
reg key_wr;
reg key_rd;
//时钟、复位信号
initial begin
clk = 1'b1;
rst_n <= 1'b0;
key_wr <= 1'b1;
key_rd <= 1'b1;
#200 rst_n <= 1'b1;
#1000 key_wr <= 1'b0;
key_rd <= 1'b1;
#400 key_wr <= 1'b1;
key_rd <= 1'b1;
#20000000 key_wr <= 1'b1;
key_rd <= 1'b0;
#400 key_wr <= 1'b1;
key_rd <= 1'b1;
#40000000 $stop;
end
always #10 clk = ~clk;
defparam eeprom_byte_rd_wr_inst.key_wr_inst.CNT_MAX = 5;
defparam eeprom_byte_rd_wr_inst.key_rd_inst.CNT_MAX = 5;
defparam eeprom_byte_rd_wr_inst.i2c_rw_data_inst.CNT_WAIT_MAX = 1000;
//-------------eeprom_byte_rd_wr_inst-------------
eeprom_byte_rd_wr eeprom_byte_rd_wr_inst (
.sys_clk (clk), //输入工作时钟,频率50MHz
.sys_rst_n(rst_n), //输入复位信号,低电平有效
.key_wr (key_wr), //按键写
.key_rd (key_rd), //按键读
.sda (sda), //串行数据
.scl (scl), //串行时钟
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe)
);
//-------------eeprom_inst-------------
M24LC64 M24lc64_inst (
.A0 (1'b0), //器件地址
.A1 (1'b0), //器件地址
.A2 (1'b0), //器件地址
.WP (1'b0), //写保护信号,高电平有效
.RESET(~rst_n), //复位信号,高电平有效
.SDA(sda), //串行数据
.SCL(scl) //串行时钟
);
endmodule
| 7.919131 |
module tb_efm;
// efm Parameters
parameter PERIOD = 10;
parameter WIDTH = 9;
// efm Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// efm Outputs
wire y_o;
wire [WIDTH-1:0] e_o;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
hk_efm #(
.WIDTH(WIDTH)
) u_efm (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i[WIDTH-1:0]),
.y_o(y_o),
.e_o(e_o[WIDTH-1:0])
);
initial begin
x_i = 'd254;
#(PERIOD * 100);
$finish;
end
endmodule
| 7.049262 |
module tb_EightxOneMux;
reg [2:0] Read;
reg [3:0] Din0, Din1, Din2, Din3, Din4, Din5, Din6, Din7; //4 registers of size 8 bits
wire [3:0] Output;
EightxOneMux show (
.Din0(Din0),
.Din1(Din1),
.Din2(Din2),
.Din3(Din3),
.Din4(Din4),
.Din5(Din5),
.Din6(Din6),
.Din7(Din7),
.RA(Read),
.RDout(Output)
);
initial begin
Din0 = 10;
Din1 = 9;
Din2 = 8;
Din3 = 7;
Din4 = 6;
Din5 = 5;
Din6 = 4;
Din7 = 3;
#20;
Read = 0;
#20;
Read = 1;
#20;
Read = 2;
#20;
Read = 3;
#20;
Read = 4;
end
endmodule
| 7.10896 |
module tb_elements; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
wire in1_AND_testbench, in2_AND_testbench, out_AND_testbench;
wire in1_OR_testbench, in2_OR_testbench, out_OR_testbench;
wire d_FF_testbench, q_FF_testbench, clk_testbench;
wire in_NOT_testbench, out_NOT_testbench;
wire out_mux_1bit, in1_mux_1bit, in2_mux_1bit, select_mux_1bit;
wire [1:0] out_mux_2bit, in1_mux_2bit, in2_mux_2bit;
wire select_mux_2bit;
// Since there are 6 elements and two files per element we have 12 modules to import ...
// 1. AND GATE
// connecting module and gate
and_two_input_gate and_two_input_gate_testbench (
.out_and_gate(out_AND_testbench),
.in1_and_gate(in1_AND_testbench),
.in2_and_gate(in2_AND_testbench)
);
// 2. AND GATE TESTER
// Signal generator and monitor
and_two_input_gate_tester and_two_input_gate_tester_testbench (
.out_and_gate_tester(out_AND_testbench),
.in1_and_gate_tester(in1_AND_testbench),
.in2_and_gate_tester(in2_AND_testbench)
);
// 3. OR GATE
// connecting module and gate
or_two_input_gate or_two_input_gate_testbench (
.out_or(out_OR_testbench),
.in_or1(in1_OR_testbench),
.in_or2(in2_OR_testbench)
);
// 4. OR GATE TESTER
// Signal generator and monitor
or_two_input_gate_tester or_two_input_gate_tester_testbench (
.out_or_tester(out_OR_testbench),
.in_or1_tester(in1_OR_testbench),
.in_or2_tester(in2_OR_testbench)
);
// 5. FLIP-FLOP
// Connecting the Flip Flop module
flip_flop_single_type_D flip_flop_testbench (
.Q (q_FF_testbench),
.D (d_FF_testbench),
.clk(clk_testbench)
);
// 6. FLIP-FLOP TESTER
// Making the tester connections
flip_flop_single_type_D_tester flip_flop_tester_testbench (
.Q_tester (q_FF_testbench),
.D_tester (d_FF_testbench),
.clk_tester(clk_testbench)
);
// 7. NOT GATE
// Connecting NOT gate module
inversor_as_not_gate inversor_as_not_gate_testbench (
.out_not(out_NOT_testbench),
.in_not (in_NOT_testbench)
);
// 8. NOT GATE TESTER
inversor_as_not_gate_tester inversor_as_not_gate_tester_testbench (
.tester_out_not(out_NOT_testbench),
.tester_in_not (in_NOT_testbench)
);
// 9. MUX 2:1 1 BIT
mux2_1_1bit mux2_1_1bit_testbench (
.out_mux1bit(out_mux_1bit),
.in1_mux2_1_1bit(in1_mux_1bit),
.in2_mux2_1_1bit(in2_mux_1bit),
.selec_1bit(select_mux_1bit)
);
// 10. MUX 2:1 1 BIT TESTER
mux2_1_1bit_tester mux2_1_1bit_tester_testbench (
.out_mux1bits_tester (out_mux_1bit),
.in1_mux1bits_tester (in1_mux_1bit),
.in2_mux1bits_tester (in2_mux_1bit),
.selec_mux1bits_tester(select_mux_1bit)
);
// 11. MUX 2:1 2 BIT
mux2_1_2bit mux2_1_2bit_testbench (
.out_mux2bit(out_mux_2bit),
.in1_mux2_1_2bit(in1_mux_2bit),
.in2_mux2_1_2bit(in2_mux_2bit),
.selec_2bit(select_mux_2bit)
);
// 12. MUX 2:1 2 BIT TESTER
mux2_1_2bit_tester mux2_1_2bit_tester_testbench (
.out_mux2bits_tester (out_mux_2bit),
.in1_mux2bits_tester (in1_mux_2bit),
.in2_mux2bits_tester (in2_mux_2bit),
.selec_mux2bits_tester(select_mux_2bit)
);
endmodule
| 8.15573 |
module tb_elevator;
reg clk;
reg reset;
reg en;
reg [3:0] F;
wire [3:0] D;
wire [3:0] Q;
wire A;
wire B;
wire A_latch;
wire B_latch;
wire [3:0] LED;
initial begin
$from_myhdl(clk, reset, en, F);
$to_myhdl(D, Q, A, B, A_latch, B_latch, LED);
end
elevator dut (
clk,
reset,
en,
F,
D,
Q,
A,
B,
A_latch,
B_latch,
LED
);
endmodule
| 7.448055 |
module: ENC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_ENC;
// Inputs
reg [31:0] D_IN;
reg [7:0] K_IN;
reg CLK;
// Outputs
wire [31:0] D_OUT;
// Instantiate the Unit Under Test (UUT)
ENC uut (
.D_IN(D_IN),
.K_IN(K_IN),
.CLK(CLK),
.D_OUT(D_OUT)
);
initial begin
// Initialize Inputs
D_IN = 0;
K_IN = 0;
CLK = 0;
// Wait 100 ns for global reset to finish
#2;
D_IN = 1;
K_IN = 1;
#2;
D_IN = 2;
K_IN = 2;
#2;
D_IN = 3;
K_IN = 3;
#2;
D_IN = 4;
K_IN = 4;
#2;
D_IN = 5;
K_IN = 5;
#2;
D_IN = 6;
K_IN = 6;
#2;
D_IN = 7;
K_IN = 7;
#2;
D_IN = 8;
K_IN = 8;
#2;
D_IN = 9;
K_IN = 9;
#2;
D_IN = 10;
K_IN = 10;
#2;
D_IN = 11;
K_IN = 11;
// Add stimulus here
end
always #1 CLK = !CLK;
endmodule
| 7.176694 |
module tb_Encoder8x3;
reg [7:0] data;
wire [2:0] code;
Encoder8x3 encoder8x3 (
.code(code),
.data(data)
);
initial begin
#0 data = 8'b0000_0001;
#5 data = 8'b0000_0010;
#5 data = 8'b0000_0100;
#5 data = 8'b0000_1000;
#5 data = 8'b0001_0000;
#5 data = 8'b0010_0000;
#5 data = 8'b0100_0000;
#5 data = 8'b1000_0000;
#5 $stop;
end
endmodule
| 6.757371 |
module tb_Encoders;
reg [15:0] in = 0;
reg [ 3:0] out4;
reg [ 2:0] out3;
reg [ 1:0] out2;
Encoder_16 enc (
in,
out4
);
Encoder_8 enc8 (
in[7:0],
out3
);
Encoder_4 enc4 (
in[3:0],
out2
);
initial begin
in = 16'b0000000000000000;
#20;
in = 16'b0000000000000001;
#20;
in = 16'b0000000000000010;
#20;
in = 16'b0000000000000100;
#20;
in = 16'b0000000000001000;
#20;
in = 16'b0000000000010000;
#20;
in = 16'b0000000000100000;
#20;
in = 16'b0000000001000000;
#20;
in = 16'b0000000010000000;
#20;
in = 16'b0000000100000000;
#20;
in = 16'b0000001000000000;
#20;
in = 16'b0000010000000000;
#20;
in = 16'b0000100000000000;
#20;
in = 16'b0001000000000000;
#20;
in = 16'b0010000000000000;
#20;
in = 16'b0100000000000000;
#20;
in = 16'b1000000000000000;
#20;
in = 16'b1000000000000001;
#20;
in = 16'b0000000100000001;
#20;
in = 16'b0000000000000011;
#20;
in = 16'b0000000000000000;
#20;
end
initial begin
$dumpfile("vcd/encoders.vcd");
$dumpvars(0, tb_Encoders);
end
endmodule
| 6.841873 |
module encoder_2pNxN_top;
parameter N = 5;
reg [(2**N)-1:0] IN;
wire [N-1:0] OUT;
integer i = 0;
encoder_2pNxN #(
.N(N)
) encoder (
IN,
OUT
);
initial begin
for (i = 0; i < 2 ** N; i = i + 1) begin
IN = 1 << i;
#1;
$display("IN = %b, OUT = %0d", IN, OUT);
end
$display("");
for (i = 0; i < 2 ** N; i = i + 1) begin
IN = ~(32'd0) << i;
#1;
$display("IN = %b, OUT = %0d", IN, OUT);
end
end
endmodule
| 6.936903 |
module tb_encoder_comparator;
parameter LEN_TX_CTRL = 8;
parameter LEN_TX_DATA = 64;
parameter LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [ 9:0] counter;
reg [ LEN_TX_CTRL-1:0] tb_tx_ctrl;
reg [ LEN_TX_DATA-1:0] tb_tx_data;
wire [ 3:0] tb_o_type;
wire [LEN_CODED_BLOCK-1:0] tb_tx_coded;
initial begin
tb_reset = 1'b0;
tb_clock = 1'b0;
tb_enable = 1'b0;
counter = 0;
end
always @(posedge tb_clock) begin
counter = counter + 1;
case (counter)
10'D2: tb_reset = 1'b1;
10'D3: tb_reset = 1'b0;
10'D5: begin
tb_tx_ctrl = 8'h00;
tb_tx_data = 64'h0001020304050607;
tb_enable = 1'b1;
end
10'D6: begin
tb_enable = 1'b0;
end
10'D10: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'h0707070707070707;
tb_enable = 1'b1;
end
10'D11: begin
tb_enable = 1'b0;
end
10'D15: begin
tb_tx_ctrl = 8'h80;
tb_tx_data = 64'hFB01020304050607;
tb_enable = 1'b1;
end
10'D16: begin
tb_enable = 1'b0;
end
10'D20: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D21: begin
tb_enable = 1'b0;
end
/*corregir de ahora en adelante
sgsdgsgaasdgsagasdgas */
10'D25: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D26: begin
tb_enable = 1'b0;
end
10'D30: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D31: begin
tb_enable = 1'b0;
end
10'D35: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D36: begin
tb_enable = 1'b0;
end
10'D40: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D41: begin
tb_enable = 1'b0;
end
10'D45: begin
tb_tx_ctrl = 8'hff;
tb_tx_data = 64'hFDFE07FE07FE07FE;
tb_enable = 1'b1;
end
10'D46: begin
tb_enable = 1'b0;
end
endcase
end
comparator_test #(
.LEN_TX_CTRL (LEN_TX_CTRL),
.LEN_CODED_BLOCK(LEN_CODED_BLOCK),
.LEN_TX_DATA (LEN_TX_DATA)
) u_comparator (
.i_clock (tb_clock),
.i_reset (tb_reset),
.i_enable (tb_enable),
.i_tx_ctrl (tb_tx_ctrl),
.i_tx_data (tb_tx_data),
.o_t_type (tb_o_type),
.o_tx_coded(tb_tx_coded)
);
always #2.5 tb_clock = ~tb_clock;
endmodule
| 6.520722 |
module tb_encoder_comparator ;
parameter LEN_TX_CTRL = 8 ;
parameter LEN_TX_DATA = 64 ;
parameter LEN_CODED_BLOCK = 66 ;
reg tb_clock ;
reg tb_reset ;
reg tb_enable ;
reg [9:0] counter ;
reg [LEN_TX_CTRL-1:0] tb_tx_ctrl ;
reg [LEN_TX_DATA-1:0] tb_tx_data ;
reg [LEN_CODED_BLOCK-1:0] tb_tx_coded ;
reg [LEN_TX_CTRL-1:0] temp_tx_ctrl ;
reg [LEN_TX_DATA-1:0] temp_tx_data ;
reg [LEN_CODED_BLOCK-1:0] temp_tx_coded ;
wire [3:0] tb_o_type ;
integer fid_tx_data ;
integer fid_tx_ctrl ;
integer fid_tx_coded;
integer code_error_data ;
integer code_error_ctrl ;
integer code_error_coded ;
integer ptr_data ;
integer ptr_ctrl ;
integer ptr_error ;
initial
begin
tb_reset = 1'b0 ;
tb_clock = 1'b0 ;
tb_enable = 1'b0 ;
counter = 0 ;
end
always @ (posedge tb_clock)
begin
for(ptr_data = 0 ; )
code_error_data <= $fscanf(fid_tx_data, "%b", temp_tx_data);
end
comparator_test
#(
.LEN_TX_CTRL (LEN_TX_CTRL) ,
.LEN_CODED_BLOCK(LEN_CODED_BLOCK) ,
.LEN_TX_DATA (LEN_TX_DATA)
)
u_comparator
(
.i_clock (tb_clock) ,
.i_reset (tb_reset) ,
.i_enable (tb_enable) ,
.i_tx_ctrl (tb_tx_ctrl) ,
.i_tx_data (tb_tx_data) ,
.o_t_type (tb_o_type) ,
.o_tx_coded(tb_tx_coded)
);
always #2.5 tb_clock = ~tb_clock;
endmodule
| 6.520722 |
module tb_enhanced_prio ();
wire [3:0] fst, snd;
reg [9:0] r;
// Instantiation of enhanced_prio module
enhanced_prio UUT (
.fst(fst),
.snd(snd),
.r (r)
);
// Test vector generator
initial begin
// test vector 1
r <= 10'b0000000000;
#200;
// test vector 2
r <= 10'b0000000100;
#200;
// test vector 3
r <= 10'b0000001001;
#200;
// test vector 4
r <= 10'b0000101001;
#200;
// test vector 5
r <= 10'b0001101001;
#200;
// test vector 6
r <= 10'b1101101001;
#200;
// test vector 7
r <= 10'b1111111111;
#200;
// test vector 8
r <= 10'b1000000000;
#200 $stop;
// terminate simulation
end
endmodule
| 6.993576 |
module TB_epb_wb_bridge ();
initial begin
$display("PASSED");
$finish;
end
endmodule
| 6.550148 |
module: error_propagator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_error_propagator_error;
parameter MATRIX_WIDTH = 4, // width of the weight matrix aka the number of columns
MATRIX_HEIGHT = 5, // height of the weight matrix aka the number of rows and size of vector
DELTA_CELL_WIDTH = 8, // width of each delta cell in bits
WEIGHTS_CELL_WIDTH = 8, // widht of each matrix cell in bits
NEURON_ADDR_WIDTH = 10, // width of activations from neurons before the sigmoid
ACTIVATION_WIDTH = 9, // cell width after sigmoid
FRACTION_WIDTH = 0,
TILING_ROW = 3, // number of vector_mac units to create
TILING_COL = 3; // number of multipliers per vector_mac unit
`include "log2.v"
localparam DW = DELTA_CELL_WIDTH;
// Inputs
reg clk;
reg rst;
reg start;
reg [MATRIX_HEIGHT*DELTA_CELL_WIDTH-1:0] delta_input;
reg [MATRIX_WIDTH *NEURON_ADDR_WIDTH-1:0] z;
reg [MATRIX_WIDTH*MATRIX_HEIGHT*WEIGHTS_CELL_WIDTH-1:0] w;
// Outputs
wire [MATRIX_WIDTH*DELTA_CELL_WIDTH-1:0] delta_output;
wire valid, error;
// Memory
wire [DELTA_CELL_WIDTH-1:0] delta_output_mem [MATRIX_WIDTH-1:0];
genvar i;
for (i=0; i<MATRIX_WIDTH; i=i+1) begin: MEM
assign delta_output_mem[i] = delta_output[i*DELTA_CELL_WIDTH+:DELTA_CELL_WIDTH];
end
// Instantiate the Unit Under Test (UUT)
error_propagator #(
.MATRIX_WIDTH (MATRIX_WIDTH ),
.MATRIX_HEIGHT (MATRIX_HEIGHT ),
.DELTA_CELL_WIDTH (DELTA_CELL_WIDTH ),
.WEIGHTS_CELL_WIDTH(WEIGHTS_CELL_WIDTH),
.NEURON_ADDR_WIDTH (NEURON_ADDR_WIDTH ),
.ACTIVATION_WIDTH (ACTIVATION_WIDTH ),
.FRACTION_WIDTH (FRACTION_WIDTH ),
.TILING_ROW (TILING_ROW ),
.TILING_COL (TILING_COL )
) uut (
.clk (clk ),
.rst (rst ),
.start (start ),
.delta_input (delta_input ),
.z (z ),
.w (w ),
.delta_output(delta_output),
.valid (valid ),
.error (error )
);
always
#1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
start = 0;
delta_input = {12'd1, 12'd1, 12'd1, 12'd1, 12'd1}; // 10, 20, 30, 40, 50
z = {10'd250, 10'd220, 10'd190, 10'd120}; // 4, 3, 2, 1
w = {8'd20, 8'd19, 8'd18, 8'd17, 8'd16, 8'd15, 8'd14, 8'd13, 8'd12, 8'd11, 8'd10, 8'd9, 8'd8, 8'd7, 8'd6, 8'd5, 8'd4, 8'd3, 8'd2, 8'd1};
// [ 45., 100., 165., 240.]
#20 rst = 1;
#20 rst = 0;
#20 start = 1;
#2 start = 0;
end
endmodule
| 6.768408 |
module: tft_color
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_etc_lcd;
// Inputs
reg sclk;
reg srst;
// Outputs
wire hsync;
wire vsync;
wire [15:0] rgb;
wire tft_bl;
wire tft_clk;
wire tft_de;
initial begin
// Initialize Inputs
sclk = 1'b1;
srst <= 1'b0;
// Wait 100 ns for global reset to finish
#40;
srst <= 1'b1;
end
always #10 sclk = ~sclk;
// Instantiate the Unit Under Test (UUT)
tft_color uut (
.sclk(sclk),
.srst(srst),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb),
.tft_bl(tft_bl),
.tft_clk(tft_clk),
.tft_de(tft_de)
);
endmodule
| 8.17593 |
module tb_ethernet_udp_rmii ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk; //PHY芯片接收数据时钟信号
reg sys_rst_n; //系统复位,低电平有效
reg eth_rxdv; //PHY芯片输入数据有效信号
reg [655:0] data_mem; //data_mem是一个存储器,相当于一个ram
reg [ 11:0] cnt_data; //数据包字节计数器
reg start_flag; //数据输入开始标志信号
//wire define
wire eth_tx_en_r; //PHY芯片输出数据有效信号
wire [ 1:0] eth_tx_data_r; //PHY芯片输出数据
wire eth_rst_n; //PHY芯片复位信号,低电平有效
wire [ 1:0] eth_rx_data; //PHY芯片输入数据
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
start_flag <= 1'b0;
#200 sys_rst_n <= 1'b1;
#100 start_flag <= 1'b1;
#50 start_flag <= 1'b0;
end
//sys_clk
always #10 sys_clk = ~sys_clk;
//data_mem
always @(negedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0)
data_mem <= 'hFE_DC_BA_98_76_54_32_10_FE_DC_BA_98_76_54_32_10_FE_DC_BA_98_76_54_32_10_FE_DC_BA_98_76_54_32_10_00_00_28_00_D2_04_D2_04_17_01_FE_A9_1F_BF_FE_A9_00_00_11_80_00_00_00_5F_3C_00_00_45_00_08_2D_DB_4A_5E_D5_E0_BC_9A_78_56_34_12_D5_55_55_55_55_55_55_55;
else if (eth_rxdv == 1'b1) data_mem <= data_mem >> 2;
else data_mem <= data_mem;
//eth_rxdv:PHY芯片输入数据有效信号
always @(negedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) eth_rxdv <= 1'b0;
else if (cnt_data == 327) eth_rxdv <= 1'b0;
else if (start_flag == 1'b1) eth_rxdv <= 1'b1;
else eth_rxdv <= eth_rxdv;
//cnt_data:数据包字节计数器
always @(negedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_data <= 12'd0;
else if (eth_rxdv == 1'b1) cnt_data <= cnt_data + 1'b1;
else cnt_data <= cnt_data;
//eth_rx_data:PHY芯片输入数据
assign eth_rx_data = (eth_rxdv == 1'b1) ? data_mem[1:0] : 2'b0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- ethernet_udp_rmii_inst -------------
ethernet_udp_rmii ethernet_udp_rmii_inst (
.eth_clk (sys_clk), //PHY芯片时钟
.sys_rst_n (sys_rst_n), //系统复位,低电平有效
.eth_rxdv_r (eth_rxdv), //PHY芯片输入数据有效信号
.eth_rx_data_r(eth_rx_data), //PHY芯片输入数据
.eth_tx_en_r (eth_tx_en_r), //PHY芯片输出数据有效信号
.eth_tx_data_r(eth_tx_data_r), //PHY芯片输出数据
.eth_rst_n(eth_rst_n) //PHY芯片复位信号,低电平有效
);
endmodule
| 7.473692 |
module tb_Euclid_GCD #(
parameter W = 16
) ();
reg clk;
// Data signals
reg [W-1:0] operand_A;
reg [W-1:0] operand_B;
wire [W-1:0] result_data;
// Control signals
wire input_available;
reg reset;
wire result_taken;
wire result_rdy;
wire [1:0] state;
wire [1:0] nstate;
Euclid_GCD UUT (
.clk (clk),
.reset (reset),
.operand_A (operand_A),
.operand_B (operand_B),
.result_data (result_data),
.input_available(input_available),
.result_rdy (result_rdy),
.result_taken (result_taken),
.state (state),
.nstate (nstate)
);
// if A < B, swap A and B
// else if B does not equal zero, A = A - B;
initial begin
// GCD of 270 and 192 is 6 = 16'h0006;
operand_A = 16'h010E;
operand_B = 16'h00C0;
reset = 1;
clk = 0;
forever #5 clk = ~clk;
end
// operation seen in simulation waveform
// A = 270, B = 192 result_data = A
// A = 270 - 192
// A = 78, B = 192 result_data = A
// A = 192, B = 78 result_data = A
// A = 192 - 78
// A = 114, B = 78 result_data = A
// A = 114 - 78
// A = 36, B = 78 result_data = A
// A = 78, B = 36 result_data = A
// A = 78 - 36
// A = 42, B = 36 result_data = A
// A = 42 - 36
// A = 6, B = 36 result_data = A
// A = 36, B = 6 result_data = A
// A = 30, B = 6 result_data = A
// A = 24, B = 6 result_data = A
// A = 24 - 6
// A = 18, B = 6 result_data = A
// A = 12, B = 6 result_data = A
// A = 12 - 6
// A = 6, B = 6 result_data = A
// A = 6 - 6
// A = 0, B = 6 result_data = A
// A = 6, B = 0 result_data = A
initial begin
#10 reset = 0;
#200 reset = 1;
end
endmodule
| 6.938021 |
module tb_execute ();
localparam STEP = 10;
parameter NOP = 32'b00000000_00000000_00000000_00010011;
reg [31 : 0] pc;
reg [31 : 0] imm;
reg [`ALU_OP_WIDTH - 1 : 0] alu_op_sel;
reg [`SEL_SRC_A_WIDTH - 1 : 0] src_a_sel;
reg [`SEL_SRC_B_WIDTH - 1 : 0] src_b_sel;
reg [31 : 0] rs1_data;
reg [31 : 0] rs2_data;
wire [31 : 0] alu_out;
execute execute (
.pc(pc),
.imm(imm),
.alu_op_sel(alu_op_sel),
.src_a_sel(src_a_sel),
.src_b_sel(src_b_sel),
.rs1_data(rs1_data),
.rs2_data(rs2_data),
.alu_out(alu_out)
);
initial begin
pc = 32'b10000;
imm = 32'b10;
alu_op_sel = `ALU_OP_NONE;
src_a_sel = `SEL_SRC_A_NONE;
src_b_sel = `SEL_SRC_B_NONE;
rs1_data = 32'b100000000;
rs2_data = 32'b0101;
#(STEP * 10) alu_op_sel = `ALU_OP_ADD;
for (integer i = 1; i <= 3; i = i + 1) begin
for (integer j = 1; j <= 4; j = j + 1) begin
src_a_sel = i;
src_b_sel = j;
#(STEP) $display("[ADD] alu_out: %b", alu_out);
end
end
#(STEP * 100) $stop;
end
endmodule
| 6.655532 |
module : tb_execution_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_execution_unit();
reg clock;
reg reset;
reg [5:0] ALU_operation;
reg [19:0] PC;
reg [1:0] operand_A_sel;
reg operand_B_sel;
reg branch_op;
reg [31:0] rs1_data;
reg [31:0] rs2_data;
reg [31:0] extend;
wire branch;
wire [31:0] ALU_result;
wire [19:0] JALR_target;
reg scan;
execution_unit #(
.CORE(0),
.DATA_WIDTH(32),
.ADDRESS_BITS(20)
) execute (
.clock(clock),
.reset(reset),
.ALU_operation(ALU_operation),
.PC(PC),
.operand_A_sel(operand_A_sel),
.operand_B_sel(operand_B_sel),
.branch_op(branch_op),
.rs1_data(rs1_data),
.rs2_data(rs2_data),
.extend(extend),
.branch(branch),
.ALU_result(ALU_result),
.JALR_target(JALR_target),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
ALU_operation = 0;
PC = 0;
operand_A_sel = 0;
operand_B_sel = 0;
branch_op = 0;
rs1_data = 0;
rs2_data = 0;
extend = 0;
scan = 0;
#10 reset = 0;
repeat (1) @ (posedge clock);
// Logical Shift Right
ALU_operation <= 6'd12;
rs1_data <= 15;
rs2_data <= 2;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'h00000003) begin
$display("\nError: Logical Shift Right operation failed!");
$display("\ntb_execution_unit--> Test Failed!\n\n");
$stop();
end
// Subtraction
ALU_operation <= 6'd14;
rs1_data <= 5;
rs2_data <= 7;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'hfffffffe) begin
$display("\nError: Subtraction operation failed!");
$display("\ntb_execution_unit--> Test Failed!\n\n");
$stop();
end
// Immediate And
ALU_operation <= 6'd10;
rs1_data <= 4;
rs2_data <= 7;
extend <= 4;
operand_B_sel <= 1'b1;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'h00000004) begin
$display("\nError: Immediate AND operation failed!");
$display("\ntb_execution_unit--> Test Failed!\n\n");
$stop();
end
$display("\ntb_execution_unit--> Test Passed!\n\n");
$stop();
end
endmodule
| 8.059788 |
module : tb_execution_unit_multi_cycle
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_execution_unit_multi_cycle();
reg clock;
reg reset;
reg [5:0] ALU_operation;
reg [19:0] PC;
reg [1:0] operand_A_sel;
reg operand_B_sel;
reg branch_op;
reg [31:0] rs1_data;
reg [31:0] rs2_data;
reg [31:0] extend;
wire branch;
wire [31:0] ALU_result;
wire [19:0] JALR_target;
reg scan;
execution_unit_multi_cycle #(
.CORE(0),
.DATA_WIDTH(32),
.ADDRESS_BITS(20),
.M_EXTENSION("True")
) EXECUTE (
.clock(clock),
.reset(reset),
.ALU_operation(ALU_operation),
.PC(PC),
.operand_A_sel(operand_A_sel),
.operand_B_sel(operand_B_sel),
.branch_op(branch_op),
.rs1_data(rs1_data),
.rs2_data(rs2_data),
.extend(extend),
.ready_i(ready_i),
.ready_o(ready_o),
.valid_result(valid_result),
.branch(branch),
.ALU_result(ALU_result),
.JALR_target(JALR_target),
.scan(scan)
);
// Clock generator
always #1 clock = ~clock;
initial begin
clock = 0;
reset = 1;
ALU_operation = 0;
PC = 0;
operand_A_sel = 0;
operand_B_sel = 0;
branch_op = 0;
rs1_data = 0;
rs2_data = 0;
extend = 0;
scan = 1;
#10 reset = 0;
repeat (1) @ (posedge clock);
// Logical Shift Right
ALU_operation <= 6'd12;
rs1_data <= 15;
rs2_data <= 2;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'h00000003) begin
$display("\nError: Logical Shift Right operation failed!");
$display("\ntb_execution_unit_multi_cycle --> Test Failed!\n\n");
$stop();
end
// Subtraction
ALU_operation <= 6'd14;
rs1_data <= 5;
rs2_data <= 7;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'hfffffffe) begin
$display("\nError: Subtraction operation failed!");
$display("\ntb_execution_unit_multi_cycle --> Test Failed!\n\n");
$stop();
end
// Immediate And
ALU_operation <= 6'd10;
rs1_data <= 4;
rs2_data <= 7;
extend <= 4;
operand_B_sel <= 1'b1;
repeat (1) @ (posedge clock);
if( ALU_result !== 32'h00000004) begin
$display("\nError: Immediate AND operation failed!");
$display("\ntb_execution_unit_multi_cycle --> Test Failed!\n\n");
$stop();
end
// MUL
ALU_operation <= 6'd20;
rs1_data <= 4;
rs2_data <= 7;
extend <= 0;
operand_B_sel <= 1'b0;
repeat (1) @ (posedge clock);
#1
if( ALU_result !== 32'd28) begin
$display("\nError: MUL operation failed!");
$display("\ntb_execution_unit_multi_cycle --> Test Failed!\n\n");
$stop();
end
$display("\ntb_execution_unit_multi_cycle --> Test Passed!\n\n");
$stop();
end
endmodule
| 8.059788 |
module tb_exe_pulse_lighting ();
//ϵͳź
reg clk200M; //200Mʱ
reg rst_n; //λ͵ƽЧ
//
reg [ 7:0] mode; //ģʽ
reg [15:0] distance; //ֵ(m)
reg [31:0] phase_diff; //λƫ(5ns)
reg [31:0] expose_time; //̽عʱ
reg [15:0] laser_width; //
reg flag_en; //Ч־,ߵƽЧ
//ź
wire laser_ttl; //ź
wire SWIR_ttl; //SWIRعź
//ʵexe_pusle_lighting
exe_pusle_lighting exe_pusle_lighting_inst (
//ϵͳź
.clk200M (clk200M), //200Mʱ
.rst_n (rst_n), //λ͵ƽЧ
//
.mode (mode), //ģʽ
.distance (distance), //ֵ(m)
.phase_diff (phase_diff), //λƫ(5ns)
.expose_time(expose_time), //̽عʱ
.laser_width(laser_width), //
.flag_en (flag_en), //Ч־,ߵƽЧ
//ź
.laser_ttl (laser_ttl), //ź
.SWIR_ttl (SWIR_ttl) //SWIRعź
);
always #2.5 clk200M <= ~clk200M; //ʱ5ns200MHz
initial begin
clk200M = 0;
rst_n = 0;
mode = 8'h00;
distance = 16'h0000;
phase_diff = 32'h0000_0000;
expose_time = 32'h0000_0000;
laser_width = 16'h0000;
flag_en = 'b0;
#100; //λӳ100ns
rst_n = 1;
cmd_debug_once_100us_10ms_20ms(); //ģʽ£ЧΣ100usλƫ10ms عʱ20ms
#12_000_000; //12msδ
cmd_debug_once_100us_10ms_20ms(); //ģʽ£ЧΣ100usλƫ10ms عʱ20ms
#19_000_000;
cmd_real_10Hz_10us_50us_100us(); //ʵģʽ£/cλ10Hz10usλƫ50us عʱ100us
#201_000_000;
cmd_cycle_stop(); //stop
cmd_debug_once_10us_10us_100us(); //ģʽ£ЧΣ10usλƫ10us عʱ100us
end
//õģʽ£ЧΣ100usλƫ10ms عʱ20ms
task cmd_debug_once_100us_10ms_20ms();
begin
mode = 8'h18; //,Ƶʣ
distance = 16'd3000; //룺3000 Ч
laser_width = 16'd20_000; //:100us
phase_diff = 32'd2_000_000; //λƫ:10ms
expose_time = 32'd4_000_000; //عʱ:20ms
cmd_enable(); //д
end
endtask
//õģʽ£ЧΣ10usλƫ10us عʱ100us
task cmd_debug_once_10us_10us_100us();
begin
mode = 8'h18; //,Ƶʣ
distance = 16'd3000; //룺3000 Ч
laser_width = 16'd2_000; //:10us
phase_diff = 32'd2_000; //λƫ:10us
expose_time = 32'd20_000; //عʱ:100us
cmd_enable(); //д
end
endtask
//ʵģʽ£/cλ10Hz10usλƫ50us عʱ100us
task cmd_real_10Hz_10us_50us_100us();
begin
mode = 8'h13; //ʵ,Ƶʣ
distance = 16'd3000; //룺3000
laser_width = 16'd2000; //2000 * 5ns = 10us
phase_diff = 32'd6000; //λƫ: 6000 * 5ns = 30us ʵλ = 30us + (distance*20/3)ns = 50us
expose_time = 32'd20000; //20000 * 5ns = 100us
cmd_enable(); //д
end
endtask
//ģʽֹͣ
task cmd_cycle_stop();
begin
mode = 8'h1f;
cmd_enable(); //д
end
endtask
//д
task cmd_enable();
begin
flag_en = 'b1;
#20; //20nsߵƽflag_enuart_rx_cmdģṩʱclk50M
flag_en = 'b0;
end
endtask
endmodule
| 6.593836 |
module of testbench
`include "define_state.h"
module tb_experiment1;
logic Clock_50;
logic [17:0] Switches;
logic [3:0] Push_buttons;
logic [8:0] LED_Green;
wire [15:0] SRAM_data_io;
logic [15:0] SRAM_write_data, SRAM_read_data;
logic [19:0] SRAM_address;
logic SRAM_UB_N;
logic SRAM_LB_N;
logic SRAM_WE_N;
logic SRAM_CE_N;
logic SRAM_OE_N;
logic SRAM_resetn;
logic mismatch;
// Instantiate the unit under test
experiment1 uut (
.CLOCK_50_I(Clock_50),
.SWITCH_I(Switches),
.PUSH_BUTTON_I(Push_buttons),
.LED_GREEN_O(LED_Green),
.SRAM_DATA_IO(SRAM_data_io),
.SRAM_ADDRESS_O(SRAM_address),
.SRAM_UB_N_O(SRAM_UB_N),
.SRAM_LB_N_O(SRAM_LB_N),
.SRAM_WE_N_O(SRAM_WE_N),
.SRAM_CE_N_O(SRAM_CE_N),
.SRAM_OE_N_O(SRAM_OE_N)
);
// The emulator for the external SRAM during simulation
tb_SRAM_Emulator SRAM_component (
.Clock_50(Clock_50),
.Resetn(SRAM_resetn),
.SRAM_data_io(SRAM_data_io),
.SRAM_address(SRAM_address[17:0]),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_WE_N(SRAM_WE_N),
.SRAM_CE_N(SRAM_CE_N),
.SRAM_OE_N(SRAM_OE_N)
);
// Generate a 50 MHz clock
always begin
# 10;
Clock_50 = ~Clock_50;
end
// Task for generating master reset
task master_reset;
begin
wait (Clock_50 !== 1'bx);
@ (posedge Clock_50);
$write("Applying global reset...\n\n");
Switches[17] = 1'b1;
// Activate reset for 2 clock cycles
@ (posedge Clock_50);
@ (posedge Clock_50);
Switches[17] = 1'b0;
$write("Removing global reset...\n\n");
end
endtask
// Initialize signals
initial begin
// This is for setting the time format
$timeformat(-6, 2, " us", 10);
Clock_50 = 1'b0;
Switches = 18'd0;
SRAM_resetn = 1'b1;
Push_buttons = 4'hF;
// Switches[0] = 1'b1; // Stuck at address
// Switches[1] = 1'b1; // Stuck at write data
// Switches[2] = 1'b1; // Stuck at write enable
// Switches[3] = 1'b1; // Stuck at read data
// Apply master reset
master_reset;
@ (posedge Clock_50);
// Clear SRAM
SRAM_resetn = 1'b0;
@ (posedge Clock_50);
SRAM_resetn = 1'b1;
@ (posedge Clock_50);
@ (posedge Clock_50);
// Activate Push button 0
$write("Start signal issued for PB0...\n\n");
Push_buttons[0] = 1'b0;
@ (posedge uut.PB_pushed[0]);
$write("Pulse generated for PB0...\n\n");
Push_buttons[0] = 1'b1;
# 200;
// run simulation until BIST is done
@ (posedge uut.BIST_finish);
$write("\nBIST finish at %t...\n", $realtime);
$write("No mismatch found...\n\n");
#20;
$stop;
end
// Self-checking testbench
always @ (posedge uut.BIST_unit.BIST_mismatch) begin
// Display error message
$write("///////////////////////////\n");
$write("Mismatch found at %t\n", $realtime);
$write("///////////////////////////\n");
$stop;
end
// This shows the progress of the SRAM BIST engine
always @ (posedge Clock_50) begin
// Only display data in the Read cycle
if (uut.BIST_unit.BIST_address[13:0] == 14'h3FFF) begin
// Note: the data from the current address will be available two clock cycles later
$write("State = %s, Current address = %d (%h), Read data = %h, Write data = %h\n",
uut.BIST_unit.BIST_state,
uut.BIST_unit.BIST_address,
uut.BIST_unit.BIST_address,
uut.BIST_unit.BIST_read_data,
uut.BIST_unit.BIST_write_data
);
end
end
/*
logic [15:0] expected_data;
// This is for probing the internal signals during simulation for debugging
always @ (posedge Clock_50) begin
// Only display data in the Read cycle
if (uut.BIST_unit.BIST_state == S_READ_CYCLE) begin
// Expected data is computed based on the state transitions in the BIST engine
expected_data = uut.BIST_unit.BIST_write_data - 16'd1;
// Note: the data from the current address will be available two clock cycles later
$write("State = %s, Current address = %d (%h), Read data = %h, Expected data = %h\n",
uut.BIST_unit.BIST_state,
uut.BIST_unit.BIST_address,
uut.BIST_unit.BIST_address,
uut.BIST_unit.BIST_read_data,
expected_data
);
end
end
*/
endmodule
| 7.998111 |
module tb_experiment1a;
logic Clock_50;
logic [17:0] switch;
logic VGA_clock;
logic VGA_Hsync;
logic VGA_Vsync;
logic VGA_blank;
logic VGA_sync;
logic [7:0] VGA_red;
logic [7:0] VGA_green;
logic [7:0] VGA_blue;
// Instantiate the unit under test
experiment1a uut (
.CLOCK_50_I(Clock_50),
.SWITCH_I(switch),
.VGA_CLOCK_O(VGA_clock),
.VGA_HSYNC_O(VGA_Hsync),
.VGA_VSYNC_O(VGA_Vsync),
.VGA_BLANK_O(VGA_blank),
.VGA_SYNC_O(VGA_sync),
.VGA_RED_O(VGA_red),
.VGA_GREEN_O(VGA_green),
.VGA_BLUE_O(VGA_blue)
);
// Generate a 50 MHz clock
always begin
#10;
Clock_50 = ~Clock_50;
end
task master_reset;
begin
wait (Clock_50 !== 1'bx);
@(posedge Clock_50);
switch[17] = 1'b1;
// Activate reset for 2 clock cycles
@(posedge Clock_50);
@(posedge Clock_50);
switch[17] = 1'b0;
end
endtask
// Initialize signals
initial begin
Clock_50 = 1'b0;
switch = 18'd0;
// Apply master reset
master_reset;
// run simulation for 1.5 ms
#1500000;
$stop;
end
endmodule
| 7.004582 |
module tb_experiment1b;
logic Clock_50;
logic [17:0] switch;
logic VGA_clock;
logic VGA_Hsync;
logic VGA_Vsync;
logic VGA_blank;
logic VGA_sync;
logic [7:0] VGA_red;
logic [7:0] VGA_green;
logic [7:0] VGA_blue;
// Instantiate the unit under test
experiment1b uut (
.CLOCK_50_I(Clock_50),
.SWITCH_I(switch),
.VGA_CLOCK_O(VGA_clock),
.VGA_HSYNC_O(VGA_Hsync),
.VGA_VSYNC_O(VGA_Vsync),
.VGA_BLANK_O(VGA_blank),
.VGA_SYNC_O(VGA_sync),
.VGA_RED_O(VGA_red),
.VGA_GREEN_O(VGA_green),
.VGA_BLUE_O(VGA_blue)
);
// Generate a 50 MHz clock
always begin
#10;
Clock_50 = ~Clock_50;
end
task master_reset;
begin
wait (Clock_50 !== 1'bx);
@(posedge Clock_50);
switch[17] = 1'b1;
// Activate reset for 2 clock cycles
@(posedge Clock_50);
@(posedge Clock_50);
switch[17] = 1'b0;
end
endtask
// Initialize signals
initial begin
Clock_50 = 1'b0;
switch = 18'd0;
// Apply master reset
master_reset;
// run simulation for 1.5 ms
#1500000;
$stop;
end
endmodule
| 7.004582 |
module tb_experiment3a;
logic CLOCK;
logic RESETN;
experiment3a uut (
.CLOCK_I(CLOCK),
.RESETN_I(RESETN),
.BCD_COUNT_O()
);
initial begin
CLOCK = 1'b0;
RESETN = 1'b0;
#10 RESETN = 1'b1;
end
always begin
CLOCK = #5 ~CLOCK;
end
endmodule
| 7.004582 |
module tb_experiment3b;
logic CLOCK;
logic RESETN;
logic LOAD;
logic [3:0] LOAD_VALUE[1:0];
assign LOAD_VALUE = {4'h0, 4'h0};
experiment3b uut (
.CLOCK_I(CLOCK),
.RESETN_I(RESETN),
.LOAD_I(LOAD),
.LOAD_VALUE_I(LOAD_VALUE),
.BCD_COUNT_O()
);
initial begin
// Initialize all signals
CLOCK = 1'b0;
RESETN = 1'b0;
LOAD = 1'b0;
#10
// After 10ns, turn off global reset
RESETN = 1'b1;
#210
// At time 220ns, simulate a load operation
// by asserting the LOAD signal for 1cc
LOAD = 1'b1;
#10 LOAD = 1'b0;
end
always begin
CLOCK = #5 ~CLOCK;
end
endmodule
| 7.004582 |
module tb_experiment4;
logic Clock_50;
logic [17:0] Switches;
logic [8:0] LED_Green;
wire [15:0] SRAM_data_io;
logic [15:0] SRAM_write_data, SRAM_read_data;
logic [19:0] SRAM_address;
logic SRAM_UB_N;
logic SRAM_LB_N;
logic SRAM_WE_N;
logic SRAM_CE_N;
logic SRAM_OE_N;
logic SRAM_resetn;
// Instantiate the unit under test
experiment4 uut (
.CLOCK_50_I(Clock_50),
.SWITCH_I(Switches),
.LED_GREEN_O(LED_Green),
.SRAM_DATA_IO(SRAM_data_io),
.SRAM_ADDRESS_O(SRAM_address),
.SRAM_UB_N_O(SRAM_UB_N),
.SRAM_LB_N_O(SRAM_LB_N),
.SRAM_WE_N_O(SRAM_WE_N),
.SRAM_CE_N_O(SRAM_CE_N),
.SRAM_OE_N_O(SRAM_OE_N)
);
// The emulator for the external SRAM during simulation
tb_SRAM_Emulator SRAM_component (
.Clock_50(Clock_50),
.Resetn (SRAM_resetn),
.SRAM_data_io(SRAM_data_io),
.SRAM_address(SRAM_address[17:0]),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_WE_N(SRAM_WE_N),
.SRAM_CE_N(SRAM_CE_N),
.SRAM_OE_N(SRAM_OE_N)
);
// Generate a 50 MHz clock
always begin
#10;
Clock_50 = ~Clock_50;
end
task master_reset;
begin
wait (Clock_50 !== 1'bx);
@(posedge Clock_50);
Switches[17] = 1'b1;
// Activate reset for 2 clock cycles
@(posedge Clock_50);
@(posedge Clock_50);
Switches[17] = 1'b0;
end
endtask
// Initialize signals
initial begin
Clock_50 = 1'b0;
Switches = 18'd0;
SRAM_resetn = 1'b1;
// Switches[1] = 1'b1; // Stuck at address
// Switches[2] = 1'b1; // Stuck at write data
// Switches[3] = 1'b1; // Stuck at write enable
// Switches[4] = 1'b1; // Stuck at read data
// Apply master reset
master_reset;
@(posedge Clock_50);
// Clear SRAM
SRAM_resetn = 1'b0;
@(posedge Clock_50);
SRAM_resetn = 1'b1;
@(posedge Clock_50);
@(posedge Clock_50);
// Start the BIST
Switches[0] = 1'b1;
@(posedge Clock_50);
Switches[0] = 1'b0;
#200;
// run simulation until BIST is done
@(posedge uut.BIST_finish);
#20;
$stop;
end
endmodule
| 7.004582 |
module tb_exploremips ();
reg clk;
reg rst;
wire [31:0] W_debug_wb_pc;
wire [ 3:0] W_debug_wb_rf_wen;
wire [ 4:0] W_debug_wb_rf_wnum;
wire [31:0] W_debug_wb_rf_wdata;
Top mips (
clk,
rst,
// debug
W_debug_wb_pc,
W_debug_wb_rf_wen,
W_debug_wb_rf_wnum,
W_debug_wb_rf_wdata
);
initial begin
clk = 1'b0;
forever begin
#50 clk = ~clk;
end
end
initial begin
#10 rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
end
endmodule
| 6.562994 |
module tb_exp_iteration_2bit_int_angle_16bit ();
localparam LEN = 16;
wire [LEN-1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = -32768;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 16'sb00000000_00000001;
end
$write("Simulation has finished");
$stop;
end
exp_iteration_2bit_int_angle_16bit #(
.LEN(LEN)
) exp0 (
.angle(angle),
.exp (exp)
);
always #5 clk = ~clk;
endmodule
| 7.424702 |
module TBExtendedTest ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/extendedtest.dat", cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
rst = 0;
#5 rst = 1;
#5 rst = 0;
end
always begin
#5 clk = ~clk;
if (clk) begin
$display("PC = 0x%8h, instruction = 0x%8h", cpu.PC, cpu.AnInstruction);
$display("");
cnt = cnt + 1;
end
if (cnt == 45) begin
ShowRegFile;
ShowDataMem;
end
end
task ShowRegFile;
begin
$display("R[00-07]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", 0, cpu.rf.rf[1],
cpu.rf.rf[2], cpu.rf.rf[3], cpu.rf.rf[4], cpu.rf.rf[5], cpu.rf.rf[6], cpu.rf.rf[7]);
$display("R[08-15]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[8],
cpu.rf.rf[9], cpu.rf.rf[10], cpu.rf.rf[11], cpu.rf.rf[12], cpu.rf.rf[13],
cpu.rf.rf[14], cpu.rf.rf[15]);
$display("R[16-23]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[16],
cpu.rf.rf[17], cpu.rf.rf[18], cpu.rf.rf[19], cpu.rf.rf[20], cpu.rf.rf[21],
cpu.rf.rf[22], cpu.rf.rf[23]);
$display("R[24-31]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[24],
cpu.rf.rf[25], cpu.rf.rf[26], cpu.rf.rf[27], cpu.rf.rf[28], cpu.rf.rf[29],
cpu.rf.rf[30], cpu.rf.rf[31]);
end
endtask
task ShowDataMem;
begin
$display("m[0x0] = 0x%8h", cpu.dm.dataMem[0/4]);
$display("m[0x4] = 0x%8h", cpu.dm.dataMem[4/4]);
$display("m[0x8] = 0x%8h", cpu.dm.dataMem[8/4]);
$display("m[0xc] = 0x%8h", cpu.dm.dataMem[32'hc/4]);
$display("m[0x10] = 0x%8h", cpu.dm.dataMem[32'h10/4]);
$display("m[0x14] = 0x%8h", cpu.dm.dataMem[32'h14/4]);
$display("m[0x18] = 0x%8h", cpu.dm.dataMem[32'h18/4]);
$display("m[0x1c] = 0x%8h", cpu.dm.dataMem[32'h1c/4]);
$display("m[0x20] = 0x%8h", cpu.dm.dataMem[32'h20/4]);
$stop();
end
endtask
endmodule
| 7.023844 |
module tb_ext_crc;
reg rx_clk, rx_enable;
reg [7:0] rx_data;
wire [7:0] rawdata;
wire raw_en;
ext_crc uut (
.rx_clk(rx_clk),
.rx_data(rx_data),
.rx_enable(rx_enable),
.sfd_wait(1'b0), // 0
.rawdata(rawdata),
.raw_en (raw_en)
);
localparam CYCLE = 16;
localparam packetsize = 50;
localparam whereis_segment = 5;
task onepacket;
input [15:0] segment_number;
input [7:0] id;
input [7:0] aux;
integer i;
begin
rx_enable = 1;
for (i = 0; i < packetsize; i = i + 1) begin
if (i == whereis_segment) rx_data = segment_number[15:8];
else if (i == whereis_segment + 1) rx_data = segment_number[7:0];
else if (i == whereis_segment + 2) rx_data = id;
else if (i == whereis_segment + 5) rx_data = aux;
else if (i >= packetsize - 5) rx_data = (i * 15) % 16;
else rx_data = 8'h55;
#CYCLE;
end
rx_enable = 0;
rx_data = 8'hxx;
end
endtask
initial begin
rx_clk = 0;
rx_enable = 0;
rx_data = 0;
$dumpfile("tb_ext_crc.vcd");
$dumpvars(0, tb_ext_crc);
#(CYCLE * 10);
onepacket(2, 1, 3);
#(CYCLE * 7);
onepacket(4, 5, 6);
#(CYCLE * 44);
$finish;
end
always begin
#2 rx_clk = !rx_clk;
#6;
end
endmodule
| 7.050573 |
module tb_ex_cnt ();
reg tb_sclk, tb_rst_n;
wire [9:0] tb_cnt;
initial begin
tb_sclk <= 1'b0;
tb_rst_n <= 1'b0;
#200.1
tb_rst_n <= 1'b1;
end
always #10 tb_sclk <= ~tb_sclk;
ex_cnt ex_cnt_inst (
.sclk (tb_sclk),
.rst_n(tb_rst_n),
.cnt (tb_cnt)
);
endmodule
| 6.679251 |
module tb_ex_ipcore ();
reg tb_clk;
wire tb_oclk1;
wire tb_oclk2;
wire tb_locked;
wire [1:0] tb_cnt;
wire [7:0] tb_odata;
initial begin
tb_clk <= 1'b0;
end
always #10 tb_clk = ~tb_clk;
ex_ipcore ex_ipcore_instance (
.clk(tb_clk),
.oclk1(tb_oclk1),
.oclk2(tb_oclk2),
.cnt(tb_cnt),
.odata(tb_odata),
.locked(tb_locked)
);
endmodule
| 6.548534 |
module tb_ex_shift_reg ();
reg tb_lvds_clk;
reg tb_rst_n;
reg tb_lvds_d;
wire [7:0] tb_o_lvds_d;
reg [3:0] i_30;
reg [0:0] mem1x16[15:0];
initial begin
tb_lvds_clk <= 1'b0;
tb_rst_n <= 1'b0;
tb_lvds_d <= 1'b0;
#90.1
tb_rst_n <= 1'b1;
end
always #10 tb_lvds_clk <= ~tb_lvds_clk;
initial begin
$readmemb("./data.txt", mem1x16);
end
initial begin
#100 lvds_send_d();
end
ex_shift_reg ex_shift_reg_inst (
.lvds_clk(tb_lvds_clk),
.rst_n (tb_rst_n),
.lvds_d (tb_lvds_d),
.o_lvds_d(tb_o_lvds_d)
);
task lvds_send_d();
integer i;
begin
for (i = 0; i < 256; i = i + 1) begin
@(posedge tb_lvds_clk);
tb_lvds_d <= mem1x16[i[3:0]];
i_30 <= i[3:0];
end
end
endtask
endmodule
| 6.506087 |
module tb_ex_spi ();
reg tb_sclk;
reg tb_rst_n;
reg tb_work_en;
reg tb_spi_sdo;
wire tb_spi_clk;
wire tb_spi_sdi;
wire tb_spi_csn;
wire tb_conf_end;
reg [15:0] send_mem[31:0];
reg [15:0] shift_buf;
initial begin
tb_sclk <= 1'b0;
tb_rst_n <= 1'b0;
#100;
tb_rst_n <= 1'b1;
end
always #10 tb_sclk <= ~tb_sclk;
initial begin
tb_work_en <= 1'b0;
#150;
tb_work_en <= 1'b1;
end
spi_ctrl spi_ctrl_instance (
.sclk(tb_sclk),
.rst_n(tb_rst_n),
.work_en(tb_work_en),
.spi_clk(tb_spi_clk),
.spi_sdi(tb_spi_sdi),
.spi_csn(tb_spi_csn),
.spi_sdo(tb_spi_sdo),
.conf_end(tb_conf_end)
);
initial begin
$readmemb("data.mif", send_mem);
end
initial begin
rec_spi();
end
task rec_spi();
integer i, j;
begin
for (i = 0; i < 32; i = i + 1) begin
for (j = 0; j < 16; j = j + 1) begin
@(posedge tb_spi_clk);
shift_buf = {shift_buf[14:0], tb_spi_sdi};
if ((shift_buf == send_mem[i]) && (j == 15))
$display("Right word index was %d, rec_d=%d, send_d=%d", i, shift_buf, send_mem[i]);
else if (j == 15)
$display("Error word index was %d, rec_d=%d, send_d=%d", i, shift_buf, send_mem[i]);
end
end
end
endtask
endmodule
| 7.056943 |
module tb_fa ();
reg a;
reg b;
reg cin;
wire sum;
wire cout;
full_adder UUT (
.a (a),
.b (b),
.cin (cin),
.sum (sum),
.cout(cout)
);
initial begin
#10 a = 0;
b = 0;
cin = 0;
#10 a = 0;
b = 1;
#10 a = 1;
b = 0;
#10 a = 1;
b = 1;
#10 a = 0;
b = 0;
cin = 1;
#10 a = 1;
b = 1;
end
endmodule
| 6.785935 |
module tb_fadder_1bit ();
wire sum, cout;
reg a, b, cin;
fadder_1bit fadd (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
a = 0;
b = 0;
cin = 0;
#5 a = 0;
b = 0;
cin = 1;
#5 a = 0;
b = 1;
cin = 0;
#5 a = 0;
b = 1;
cin = 1;
#5 a = 1;
b = 0;
cin = 0;
#5 a = 1;
b = 0;
cin = 1;
#5 a = 1;
b = 1;
cin = 0;
#5 a = 1;
b = 1;
cin = 1;
end
initial $monitor("a = %b, b = %b, cin = %b, cout = %b, sum = %b", a, b, cin, cout, sum);
initial begin
$dumpfile("tb_fadder_1bit.vcd");
$dumpvars;
end
endmodule
| 6.554951 |
module tb_fadder_4bit ();
wire [3:0] sum;
wire cout;
reg [3:0] a, b;
reg cin;
fadder_4bit faddr (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
$dumpfile("tb_fadder_4bit.vcd");
$dumpvars;
end
initial begin
a = 4'b0101;
b = 4'b1000;
cin = 0;
#5 a = 4'b0101;
b = 4'b1000;
cin = 1;
#5 a = 4'b1101;
b = 4'b1001;
cin = 0;
#5 a = 4'b1101;
b = 4'b1001;
cin = 1;
end
endmodule
| 6.593624 |
module tb_fadder_dec ();
reg a, b, cin;
wire sum, cout;
fadder_dec addr (
.cout(cout),
.sum(sum),
.cin(cin),
.a(a),
.b(b)
);
initial begin
$dumpfile("tb_fadder_dec.vcd");
$dumpvars;
end
initial $monitor(" a = %b, b = %b, cin = %b, sum = %b, cout = %b", a, b, cin, sum, cout);
initial begin
a = 0;
b = 0;
cin = 0;
#5 a = 0;
b = 0;
cin = 1;
#5 a = 0;
b = 1;
cin = 0;
#5 a = 0;
b = 1;
cin = 1;
#5 a = 1;
b = 0;
cin = 0;
#5 a = 1;
b = 0;
cin = 1;
#5 a = 1;
b = 1;
cin = 0;
#5 a = 1;
b = 1;
cin = 1;
end
endmodule
| 7.094135 |
module: FanSpeed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FanSpeed;
// Inputs
reg arst;
reg clk;
reg [7:0] speed;
// Outputs
wire pwm_data;
// Instantiate the Unit Under Test (UUT)
FanSpeed uut (
.arst(arst),
.clk(clk),
.speed(speed),
.pwm_data(pwm_data)
);
initial begin
arst = 1;
clk = 0;
#40 arst=0;
repeat (1100)
#40 clk = ~clk;
end
initial begin
// Initialize Inputs
//clk = 0;
speed = 8'b10001001;
end
/*always #10 clk = ~clk;
initial begin
// Initialize Inputs
arst = 1;
clk = 0;
speed = 8'b1001000;
// Wait 100 ns for global reset to finish
#100;
arst = 0;
#107;
arst = 1;
#103
arst = 0;
// Add stimulus here
end*/
endmodule
| 8.365707 |
module TB_fan_controller ();
reg clk;
reg rst;
wire f0, f1, f2;
fan_controller fan_controller_inst (
.wb_clk_i(clk),
.wb_rst_i(rst),
.fan_control({f2, f1, f0})
);
initial begin
$dumpvars;
clk <= 1'b0;
rst <= 1'b1;
#40 rst <= 1'b0;
#400000 $display("PASSED");
$finish;
end
initial begin
end
always begin
#1 clk <= ~clk;
end
endmodule
| 6.620747 |
module tb_Fast_median_filter;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire dout_flag;
wire [7:0] median;
reg [7:0] mem_a[130559:0]; //480*272=130560-----13bit
//------------- generate system signals ------------------------------------
initial begin
sclk = 1;
s_rst_n <= 0;
din <= 'd0;
in_line_vaild <= 0;
#100 s_rst_n <= 1;
#100 data_generate();
end
always #10 sclk = ~sclk;
initial $readmemh("./1.txt", mem_a);
//initial $readmemh("./test.txt", mem_a);
//initial $readmemh("./1.txt", mem_a);
//modelsim仿真wave中数据变量导出到txt文档
reg [17:0] i = 0;
always @(posedge sclk) begin
if (!s_rst_n) i <= 0;
else if (i < 130559 && dout_flag == 1)
//else if (i<47 && dout_flag==1)
i <= i + 1;
else i <= 0;
end
integer w_file;
initial w_file = $fopen("data_out_1.txt");
always @(i) begin
$fdisplay(w_file, "%d", median);
if (i == 17'd130559) //
//if (i == 17'd47)
$stop;
end
//modelsim仿真wave中数据变量导出到txt文档
Fast_median_filter Fast_median_filter_inst (
.din (din ),
.data_valuable (in_line_vaild),
.sclk (sclk ),
.s_rst_n (s_rst_n ),
.vsync (vsync ),
.median (median),
.dout_flag(dout_flag)
);
task data_generate();
integer i;
begin
for (i = 0; i < 130560; i = i + 1) begin
//for(i=0; i<50; i=i+1) begin
#20 in_line_vaild <= 1'b1;
din <= mem_a[i];
//#20 din<=din+1;
end
in_line_vaild <= 0;
end
endtask
endmodule
| 7.20021 |
module fa_Nb_top;
parameter W = 2;
reg [W-1:0] IN0, IN1;
reg CIN;
wire [W-1:0] SUM;
wire CO;
fa_Nb #(
.WIDTH(W)
) fa (
.CARRY_IN(CIN),
.IN0(IN0),
.IN1(IN1),
.SUM(SUM),
.CARRY_OUT(CO)
);
integer i = 0;
initial begin
for (i = 0; i <= 2 ** (2 * W + 1); i = i + 1) begin
$display("CIN : %0b, IN0 : %0d, IN1 : %0d == {CO,SUM} : %0d", CIN, IN0, IN1, {CO, SUM});
{CIN, IN0, IN1} = i;
#1;
if ((CIN + IN0 + IN1) != ({CO, SUM})) begin
$display("Error Information Mismatch");
$display("CIN : %0b, IN0 : %0d, IN1 : %0d == {CO,SUM} : %0d", CIN, IN0, IN1, {CO, SUM});
$finish;
end
end
end
endmodule
| 7.030295 |
module fdc(
output PIN_nSHIFT, // serial clock
output PIN_nOUT,
output PIN_nDI,
input PIN_nDO,
input PIN_nRUN,
input PIN_nSET,
output PIN_nERR,
output PIN_nDONE,
output PIN_nTR
);
reg CLK;
reg nSH;
reg nOUT;
reg nDI;
wire nDO;
wire nRUN;
wire nSET;
reg nERR;
reg nDONE;
reg nTR;
reg [2:0] stat;
reg [3:0] cnt;
reg [8:0] cmd;
reg [7:0] dat;
assign PIN_nSHIFT = nSH;
assign PIN_nOUT = nOUT;
assign PIN_nDI = nDI;
assign PIN_nERR = nERR;
assign PIN_nDONE = nDONE;
assign PIN_nTR = nTR;
assign nDO = PIN_nDO;
assign nRUN = PIN_nRUN;
assign nSET = PIN_nSET;
//_____________________________________________________________________________
//
// Clock generator
//
initial
begin
CLK = 1'b0;
#`SIM_HDELAY
forever #`SIM_DELAY CLK = ~CLK;
end
initial
begin
nSH = 1'b1;
nOUT = 1'b1;
nDI = 1'b1;
nERR = 1'b1;
nDONE = 1'b1;
nTR = 1'b1;
stat = 3'b000;
end
always @(negedge nSET or posedge CLK)
begin
if (~nSET)
begin
nSH = 1'b1;
nOUT = 1'b1;
nDI = 1'b1;
nERR = 1'b1;
nDONE = 1'b1;
nTR = 1'b1;
stat = 3'b000;
end
else
case(stat)
3'b000: // wait command
begin
nDONE = 1'b0;
if (~nRUN)
begin
nDONE = 1'b1;
cnt = 4'h8;
cmd = {8'b0, ~nDO};
stat = 3'b001;
end
end
3'b001: // get command
begin
if (nSH)
begin
cmd = {cmd[7:0], ~nDO};
nSH = 1'b0;
end
else
begin
nSH = 1'b1;
cnt = cnt - 4'h1;
if (cnt == 4'h0)
begin
$display("FDC cmd: %03O", cmd);
stat = 3'b010;
end
end
end
3'b010: // analyze command
case(cmd[4:1])
3'b000: // write buffer
begin
nTR = 1'b0;
stat = 3'b011;
end
3'b001: // read buffer
begin
nOUT = 1'b0;
stat = 3'b101;
dat = 8'o054;
cnt = 7;
nDI = ~dat[7];
end
default: // unrecognized
begin
stat = 3'b000;
nDONE = 1'b0;
nERR = 1'b0;
end
endcase
3'b011:
if (~nRUN)
begin
nTR = 1'b1;
dat = {7'b0, ~nDO};
cnt = 4'h8;
stat = 4'b100;
end
3'b100: // write buffer data
begin
if (nSH)
begin
dat = {dat[6:0], ~nDO};
nSH = 1'b0;
end
else
begin
nSH = 1'b1;
cnt = cnt - 4'h1;
if (cnt == 4'h0)
begin
$display("FDC dat: %03O", dat);
stat = 3'b000;
nDONE = 1'b0;
nERR = 1'b1;
end
end
end
3'b101: // read buffer data
begin
if (nSH)
begin
dat = {dat[6:0], ~nDO};
nSH = 1'b0;
nDI = ~dat[7];
end
else
begin
nSH = 1'b1;
cnt = cnt - 4'h1;
if (cnt == 4'h0)
begin
$display("FDC dat: %03O", dat);
stat = 3'b110;
nTR = 1'b0;
end
end
end
3'b110: // read buffer data
begin
if (~nRUN)
begin
stat = 3'b000;
nDONE = 1'b0;
nERR = 1'b1;
nOUT = 1'b1;
nTR = 1'b1;
end
end
endcase
end
endmodule
| 6.757907 |
module tb_fdiv;
reg clk0;
wire clk1;
wire clk2;
parameter Tburst = 100000000, Ton = 1, Toff = 1;
fdiv fd (
clk0,
clk1,
clk2
);
initial begin
repeat (Tburst) begin
#Toff clk0 = 1'b1;
#Ton clk0 = 1'b0;
end
end
endmodule
| 6.617482 |
module tb_fetch ();
localparam STEP = 10;
reg clk;
reg rst;
reg [31 : 0] pc;
reg stall;
reg [31 : 0] rs1;
reg [31 : 0] imm;
reg [31 : 0] pc_sel;
reg taken;
wire [31 : 0] ir_code;
wire [31 : 0] next_pc;
fetch fetch (
.clk(clk),
.rst(rst),
.pc(pc),
.stall(stall),
.rs1(rs1),
.imm(imm),
.pc_sel(pc_sel),
.taken(taken),
.ir_code(ir_code),
.next_pc(next_pc)
);
always begin
clk = 0;
#(STEP / 2);
clk = 1;
#(STEP / 2);
end
initial begin
rst = 0;
#(STEP * 10) rst = 1;
#(STEP * 10) rst = 0;
pc = 32'h0;
rs1 = 32'h100;
imm = 32'h100;
pc_sel = `PC_SEL_ADD4;
taken = 0;
stall = 0;
for (integer i = 0; i < 4; i = i + 1) begin
#(STEP) $display("ir_code: %h next_pc: %h", ir_code, next_pc);
pc = next_pc;
end
pc_sel = `PC_SEL_JAL;
#(STEP);
$display("ir_code: %h next_pc: %h", ir_code, next_pc);
pc = next_pc;
pc_sel = `PC_SEL_JALR;
#(STEP);
$display("ir_code: %h next_pc: %h", ir_code, next_pc);
pc = next_pc;
pc_sel = `PC_SEL_ADD4;
taken = 1;
#(STEP);
$display("ir_code: %h next_pc: %h", ir_code, next_pc);
pc = next_pc;
pc_sel = `PC_SEL_ADD4;
taken = 0;
stall = 1;
for (integer i = 0; i < 4; i = i + 1) begin
#(STEP) $display("ir_code: %h next_pc: %h", ir_code, next_pc);
pc = next_pc;
end
// Cache Miss
pc_sel = `PC_SEL_ADD4;
taken = 0;
stall = 0;
pc = 32'h100000;
#(STEP) $display("ir_code: %h next_pc: %h", ir_code, next_pc); // NOP
#(STEP * 100) $stop;
end
endmodule
| 7.007226 |
module : tb_fetch_issue
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_fetch_issue();
parameter RESET_PC = 0;
parameter ADDRESS_BITS = 32;
reg clock;
reg reset;
reg [1:0] next_PC_select;
reg [ADDRESS_BITS-1:0] target_PC;
wire [ADDRESS_BITS-1:0] issue_PC;
// instruction cache interface
wire [ADDRESS_BITS-1:0] i_mem_read_address;
reg scan;
//instantiate DUT
fetch_issue #(
.RESET_PC(RESET_PC),
.ADDRESS_BITS(ADDRESS_BITS)
) DUT (
.clock(clock),
.reset(reset),
.next_PC_select(next_PC_select),
.target_PC(target_PC),
.issue_PC(issue_PC),
.i_mem_read_address(i_mem_read_address),
.scan(scan)
);
// generate clock signal
always #5 clock = ~clock;
initial begin
clock = 1;
reset = 1;
next_PC_select = 0;
target_PC = 0;
scan = 0;
repeat (3) @ (posedge clock);
reset = 1'b0;
next_PC_select = 0;
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 4)begin
$display("\nTest 1 Error!");
$display("\ntb_fetch_issue --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 8)begin
$display("\nTest 2 Error!");
$display("\ntb_fetch_issue --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 32'd12)begin
$display("\nTest 3 Error!");
$display("\ntb_fetch_issue --> Test Failed!\n\n");
$stop;
end
next_PC_select = 2'b10;
target_PC = 32'h8000;
repeat (1) @ (posedge clock);
#1
if(issue_PC != 32'h8000)begin
$display("\nTest 4 Error!");
$display("\ntb_fetch_issue --> Test Failed!\n\n");
$stop;
end
next_PC_select = 0;
repeat (1) @ (posedge clock);
$display("\ntb_fetch_issue --> Test Passed!\n\n");
$stop;
end
endmodule
| 8.699001 |
module : tb_fetch_issue_intr
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_fetch_issue_intr();
parameter RESET_PC = 0;
parameter ADDRESS_BITS = 32;
reg clock;
reg reset;
reg [1:0] next_PC_select;
reg [ADDRESS_BITS-1:0] target_PC;
reg trap_branch;
reg [ADDRESS_BITS-1:0] trap_target;
wire [ADDRESS_BITS-1:0] next_PC;
wire [ADDRESS_BITS-1:0] issue_PC;
// instruction cache interface
wire [ADDRESS_BITS-1:0] i_mem_read_address;
reg scan;
//instantiate DUT
fetch_issue_intr #(
.RESET_PC(RESET_PC),
.ADDRESS_BITS(ADDRESS_BITS)
) DUT (
.clock(clock),
.reset(reset),
.next_PC_select(next_PC_select),
.target_PC(target_PC),
.trap_branch(trap_branch),
.trap_target(trap_target),
.next_PC(next_PC),
.issue_PC(issue_PC),
.i_mem_read_address(i_mem_read_address),
.scan(scan)
);
// generate clock signal
always #5 clock = ~clock;
initial begin
clock = 1;
reset = 1;
next_PC_select = 0;
target_PC = 0;
trap_target = 0;
trap_branch = 0;
scan = 0;
repeat (3) @ (posedge clock);
reset = 1'b0;
next_PC_select = 0;
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 4)begin
$display("\nTest 1 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 8)begin
$display("\nTest 2 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 32'd12)begin
$display("\nTest 3 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
next_PC_select = 2'b10;
target_PC = 32'h8000;
repeat (1) @ (posedge clock);
#1
if(issue_PC != 32'h8000)begin
$display("\nTest 4 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
next_PC_select = 0;
target_PC = 0;
trap_target = 32'h000000C0;
trap_branch = 1;
#1
if(next_PC !== 32'h00008004 ) begin
$display("\nTest 5 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
#1
if(issue_PC !== 32'h000000C0 ) begin
$display("\nTest 6 Error!");
$display("\ntb_fetch_issue_intr --> Test Failed!\n\n");
$stop;
end
repeat (1) @ (posedge clock);
$display("\ntb_fetch_issue_intr --> Test Passed!\n\n");
$stop;
end
endmodule
| 8.699001 |
module : tb_fetch_receive
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_fetch_receive();
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter NOP = 32'h00000013;
reg [DATA_WIDTH-1 :0] i_mem_data;
reg [ADDRESS_BITS-1:0] issue_PC;
reg flush;
reg scan;
wire [31 :0] instruction;
//instantiate fetch_receive module
fetch_receive #(
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS)
) DUT (
.flush(flush),
.i_mem_data(i_mem_data),
.issue_PC(issue_PC),
.instruction(instruction),
.scan(scan)
);
initial begin
flush <= 0;
i_mem_data <= 32'hFEFEFEFE;
issue_PC <= 32'd0;
scan <= 0;
#1;
if(instruction !== 32'hFEFEFEFE)begin
$display("Test 1 Error!");
$display("\ntb_fetch_receive --> Test Failed!\n\n");
$stop;
end
#5;
i_mem_data <= 32'h55556666;
issue_PC <= 32'd4;
flush <= 1;
#1;
if(instruction !== NOP)begin
$display("Test 2 Error!");
$display("\ntb_fetch_receive --> Test Failed!\n\n");
$stop;
end
#5;
i_mem_data <= 32'h11111111;
issue_PC <= 32'd4;
#1;
if(instruction !== NOP)begin
$display("Test 3 Error!");
$display("\ntb_fetch_receive --> Test Failed!\n\n");
$stop;
end
#5;
flush <= 0;
#1;
if(instruction !== 32'h11111111)begin
$display("Test 4 Error!");
$display("\ntb_fetch_receive --> Test Failed!\n\n");
$stop;
end
$display("\ntb_fetch_receive --> Test Passed!\n\n");
$stop;
end
endmodule
| 8.854399 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
reg clk;
reg reset;
// Control Interface
reg flush;
reg [IADDRW-1:0] load_address;
reg load;
// Code Segment
reg [ 15:0] cs_register;
// Instruction Memory Interface
wire imem_valid;
reg imem_ready;
wire [IADDRW-1:0] imem_address;
wire imem_wr_en;
wire [IDATAW-1:0] imem_wr_data;
wire [ISIZEW-1:0] imem_wr_size;
reg imem_dp_valid;
wire imem_dp_ready;
reg [IDATAW-1:0] imem_dp_read_data;
// Branch Predictor Interface
wire [IADDRW-1:0] bp_pc;
reg [IADDRW-1:0] bp_target;
reg bp_taken;
// Return Address Stack Interface
wire ras_pop;
reg [IADDRW-1:0] ras_target;
// Pipestage Interface
wire f_valid;
reg f_ready;
reg [ 5:0] f_bytes_read;
wire [ 6:0] f_valid_bytes;
wire [ 255:0] f_instruction;
wire [IADDRW-1:0] f_pc;
wire f_branch_taken;
reg [ 127:0] memory_data;
reg memory_valid;
//reg [2047:0] MEMORY[127:0];
fetch_top uut (
clk,
reset,
flush,
load_address,
load,
cs_register,
imem_valid,
imem_ready,
imem_address,
imem_wr_en,
imem_wr_data,
imem_wr_size,
imem_dp_valid,
imem_dp_ready,
imem_dp_read_data,
bp_pc,
bp_target,
bp_taken,
ras_pop,
ras_target,
f_valid,
f_ready,
f_bytes_read,
f_valid_bytes,
f_instruction,
f_pc,
f_branch_taken
);
initial begin
$strobe("============ \n Begin Test \n============");
reset = 1;
clk = 0;
//for ( i = 0; i < 2048; i = i+ 1) begin
// MEMORY[i] = (2048 - i);
//end
flush = 0;
load_address = 0;
load = 0;
// Code Segment
cs_register = 16'hF000;
// Branch Predictor Interface
bp_target = 0;
bp_taken = 0;
// Return Address Stack Interface
ras_target = 0;
// Pipestage Interface
f_ready = 1;
f_bytes_read = 4;
#25 reset = 0;
#10 #10 $display("==========\n End Test \n==========");
end
initial #2000 $finish;
always @(posedge clk or posedge reset) begin
if (reset) begin
memory_data <= 0;
memory_valid <= 0;
end else begin
memory_data <= {32'h78787878, 32'h56565656, 32'h34343434, 32'h12121212};
memory_valid <= (memory_valid) ? ~(imem_dp_ready) : imem_valid;
end
end
always @(*) begin
imem_dp_valid = memory_valid;
imem_dp_read_data = memory_data;
imem_ready = ~memory_valid;
end
always #10 clk = ~clk;
//always #20 f_ready = ($random%2);
reg [3:0] random_int;
always @(f_valid_bytes) begin
random_int = ($random % 15) + 1;
if (random_int > f_valid_bytes) begin
f_ready = 0;
end else begin
f_ready = 1;
end
f_bytes_read = random_int;
end // always @ begin
//always #20 f_bytes_read = ($random%15)+1;
initial begin
$vcdplusfile("fetch_seq.dump.vpd");
$vcdpluson(0, TOP);
end
endmodule
| 6.594167 |
module tb_ffcore ();
parameter NATIVE_ADDR_WDITH = 3;
parameter NATIVE_DATA_WIDTH = 32;
parameter M = 32'd100;
FF_Test_Core #(
.NATIVE_ADDR_WDITH(NATIVE_ADDR_WDITH),
.NATIVE_DATA_WIDTH(NATIVE_DATA_WIDTH),
.M(M)
) inst_FF_Test_Core (
.REFCLK (REFCLK),
.NATIVE_CLK (NATIVE_CLK),
.NATIVE_EN (NATIVE_EN),
.NATIVE_WR (NATIVE_WR),
.NATIVE_ADDR (NATIVE_ADDR),
.NATIVE_DATA_IN (NATIVE_DATA_IN),
.NATIVE_DATA_OUT(NATIVE_DATA_OUT),
.NATIVE_READY (NATIVE_READY),
.proba_signal (proba_signal),
.rst_n (rst_n),
.imp_in (imp_in),
.ps_done (ps_done),
.ps_en (ps_en),
.ps_incdec (ps_incdec),
.ps_clk (ps_clk)
);
reg REFCLK;
reg NATIVE_CLK;
reg NATIVE_EN;
reg NATIVE_WR;
reg [NATIVE_ADDR_WDITH-1:0] NATIVE_ADDR;
reg [NATIVE_DATA_WIDTH-1:0] NATIVE_DATA_IN;
wire [NATIVE_DATA_WIDTH-1:0] NATIVE_DATA_OUT;
wire NATIVE_READY;
wire proba_signal;
reg rst_n;
reg imp_in;
reg ps_done;
wire ps_en;
wire ps_incdec;
wire ps_clk;
always begin
#5 NATIVE_CLK = ~NATIVE_CLK;
end
always begin
#2 imp_in = ~imp_in;
REFCLK = ~REFCLK;
end
initial begin
REFCLK = 0;
NATIVE_CLK = 0;
NATIVE_EN = 0;
NATIVE_WR = 0;
NATIVE_ADDR = 0;
NATIVE_DATA_IN = 0;
rst_n = 1;
imp_in = 0;
ps_done = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#10 NATIVE_EN = 1;
NATIVE_WR = 1;
NATIVE_ADDR = 1;
NATIVE_DATA_IN = 1;
#10 NATIVE_EN = 0;
NATIVE_WR = 1;
NATIVE_ADDR = 1;
NATIVE_DATA_IN = 1;
#10 NATIVE_EN = 0;
NATIVE_WR = 1;
NATIVE_ADDR = 1;
NATIVE_DATA_IN = 1;
#100 #10 NATIVE_EN = 1;
NATIVE_WR = 0;
NATIVE_ADDR = 2;
NATIVE_DATA_IN = 0;
#10 NATIVE_EN = 0;
NATIVE_WR = 0;
NATIVE_ADDR = 2;
NATIVE_DATA_IN = 0;
#1000 $stop;
end
endmodule
| 7.398432 |
module tb_fft ();
reg SCLK;
reg signed [13:0] data_out;
//------------------------------------//
wire signed [13:0] data_out_re;
wire signed [13:0] data_out_im;
//--------------时钟部分----------------//
initial SCLK = 0;
always #10 SCLK = ~SCLK;
//-------------------------------------//
//-------------------------------------//
parameter num = 32'd1024;
reg [7:0] i = 0;
reg signed [13:0] data_men[1:num];
//reg [13:0] data_reg = 0;
initial begin
$readmemb("E:/Workspace/Vivado_16.4/2017_11_5_FFT/TestBeach/sin_data.txt", data_men);
end
always @(posedge SCLK) begin
data_out <= data_men[i];
i <= i + 8'd1;
end
//------------------------------------//
/*
//-------------------------------------//
parameter num = 512;
integer i = 0;
reg [13:0] stimulus[1:num];
initial begin
$readmemh("E:/Workspace/Vivado_16.4/2017_11_8_TestBeach/TestBeach/sin_data.txt",stimulus);
i = 0;
repeat(num) begin
i = i + 1;
data_out = stimulus[i];
#10;
end
end
//-------------------------------------//
*/
//-------------调用fft-----------------//
FFT_Control FFT_Control_inst0 (
.sclk (SCLK),
.data_in (data_out),
.data_out_re(data_out_re),
.data_out_im(data_out_im)
);
endmodule
| 6.502988 |
module tb_fft_2 ();
reg clk; //50mhz
reg rst; //复位
reg [31:0]s_axis_data_tdata;//fft 输入的处理数据,低16位为实部信号，高16位虚部信号，本次matlab才生的信号都是失信号
reg [31:0] data[511:0]; ////数组，将FPGA读取的信号数据寄存在数组中
wire s_axis_config_tready; //fft core 准备好接收配置信号
wire s_axis_data_tready; //fft core 准备好接收处理数据信号
wire [31:0] xk_re; //FFT处理后输出实部信号
wire [31:0] xk_im; //FFT处理后输出虚部信号
wire m_axis_data_tvalid;
//例化fft ip
FFT_Control_2 FFT_Control_2_inst0 (
.clk(clk),
.rst(rst),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_data_tdata(s_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.xk_re(xk_re),
.xk_im(xk_im),
.s_axis_data_tready(s_axis_data_tready)
);
initial clk = 1;
always #(`clk_period / 2) clk = ~clk; //产生50MHZ的系统时钟
integer i;
initial begin
rst = 0;
; //复位
s_axis_data_tdata = 0; //输入初始化为0
#100;
rst = 1; //恢复
$readmemb("E:/Workspace/Vivado_16.4/2017_11_5_FFT/TestBeach/sin_data.txt",
data); //从matlab生成文件中读取数据
for (i = 0; i < 512; i = i + 1) begin
s_axis_data_tdata[15:0]=data[i];//将数组的数据赋值给s_axis_data_tdata作为输入，作为实部信号，没有虚部信号
#(`clk_period); //将输入数据以采样频率50MHZ输入
end
#80000;
$stop;
end
//定义一个文件名，将处理后的实部信号发存放在此文件中
integer fft_file;
initial begin
fft_file = $fopen("fft_file.txt");
if (fft_file == 0) begin
$display("can not open the file!");
$stop;
end
end
wire signed [31:0] fft_dataout;
assign fft_dataout = xk_re; //将输出的实部信号赋值给fft_dataout寄存器
always @(posedge clk)
if (m_axis_data_tvalid == 1'b1) // m_axis_data_tvalid有效时 输出
$fdisplay(fft_file, "%d", fft_dataout);
//定义一个文件名，将处理后的虚部信号发存放在此文件中
integer fft_im_file;
initial begin
fft_im_file = $fopen("fft_im_file.txt");
if (fft_im_file == 0) begin
$display("can not open the file!");
$stop;
end
end
wire signed [31:0] fft_im_dataout;
assign fft_im_dataout = xk_im; //将输出的虚部信号赋值给fft_im_dataout寄存器
always @(posedge clk)
if (m_axis_data_tvalid == 1'b1) // m_axis_data_tvalid有效时 输出
$fdisplay(fft_im_file, "%d", fft_im_dataout);
endmodule
| 6.936962 |
module tb_fft_3 ();
//------------------------------//
reg sclk;
reg [31:0] s_axis_data_tdata;
reg [31:0] data [1023:0];
wire s_axis_config_tready;
wire s_axis_data_tready;
wire [31:0] data_re;
wire [31:0] data_im;
wire m_axis_data_tvalid;
wire [15:0] m_axis_data_tuser;
//------------------------------//
//----------设置时钟信号----------//
initial sclk = 0;
always #5 sclk = ~sclk; //100M
//-------------------------------//
//-----------其他部分-----------//
integer i;
initial begin
s_axis_data_tdata = 0;
#100 $readmemb("E:/Workspace/Vivado_16.4/2017_11_5_FFT/TestBeach/sin_data.txt", data);
for (i = 0; i < 1024; i = i + 1) begin
s_axis_data_tdata[13:0] = data[i];
#10;
end
//#8000;
//$stop;
end
//------------------模拟串口发送部分------------------//
reg rx_ready;
reg rd_clk;
//--------例化-----------//
FFT_Control_3 FFT_Control_3_inst0 (
.clk (sclk),
.s_axis_data_tdata (s_axis_data_tdata),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_data_tready (s_axis_data_tready),
.data_out_re (data_re),
.data_out_im (data_im),
.m_axis_data_tvalid (m_axis_data_tvalid),
.m_axis_data_tuser (m_axis_data_tuser)
);
//-------------------------//
FIFO_Control FIFO_Control_inst1 (
.clk (sclk),
.wr_clk (sclk),
.rd_clk (rd_clk), //读数据速度
.data_valid (m_axis_data_tvalid),
.tx_dong_sig(tx_dong_sig), //发送结束标志
.rx_ready (rx_ready), //单片机接收准备
.data_re (data_re),
.tx_ready (tx_ready) //FFT发送准备
);
endmodule
| 7.483662 |
module tb_FFT_FSM;
reg i_clk;
reg i_rst;
reg i_en;
reg i_new_data;
reg [15:0] i_data;
wire [31:0] o_dout;
wire o_active_write;
wire [7:0] o_addr;
FFT_FSM dut (
i_clk,
i_rst,
i_en,
i_new_data,
i_data,
o_dout,
o_active_write,
o_addr
);
initial begin
i_clk = 0;
i_rst = 1;
i_en = 0;
i_new_data = 0;
i_data = 0;
#100 i_rst <= #20 0;
i_en <= #20 1;
end
always #10 i_clk <= !i_clk;
endmodule
| 6.748723 |
module TB_Fibonacci ();
parameter clock_time = 1000000;
reg next;
reg reset;
wire [6:0] disp1;
wire [6:0] disp2;
wire [6:0] disp3;
wire [6:0] disp4;
Fibonacci fib (
.next (next),
.reset(reset),
.disp1(disp1),
.disp2(disp2),
.disp3(disp3),
.disp4(disp4)
);
initial begin
next = 0;
reset = 1;
#10 reset = 0;
#10 reset = 1;
end
always #clock_time begin
next = ~next;
$display("%x - %x - %x - %x", disp4, disp3, disp2, disp1);
end
endmodule
| 6.692512 |
module: fifo36_to_ll8
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo36_to_ll8;
// Inputs
reg clk;
reg reset;
reg clear;
reg [35:0] f36_data;
reg f36_src_rdy_i;
reg ll_dst_rdy_n;
// Outputs
wire f36_dst_rdy_o;
wire [7:0] ll_data;
wire ll_sof_n;
wire ll_eof_n;
wire ll_src_rdy_n;
wire [31:0] debug;
// Instantiate the Unit Under Test (UUT)
fifo36_to_ll8 uut (
.clk(clk),
.reset(reset),
.clear(clear),
.f36_data(f36_data),
.f36_src_rdy_i(f36_src_rdy_i),
.f36_dst_rdy_o(f36_dst_rdy_o),
.ll_data(ll_data),
.ll_sof_n(ll_sof_n),
.ll_eof_n(ll_eof_n),
.ll_src_rdy_n(ll_src_rdy_n),
.ll_dst_rdy_n(ll_dst_rdy_n),
.debug(debug)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
clear = 0;
f36_data = 0;
f36_src_rdy_i = 1;
ll_dst_rdy_n = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
#10;
f36_data = 36'b0001_00000000_11111111_00000000_11111111;
#10;
f36_data = 36'b0000_11111111_00000000_11111111_00000000;
#10;
f36_data = 36'b0000_00000000_11111111_00000000_11111111;
#10;
f36_data = 36'b0000_11111111_00000000_11111111_00000000;
// Add stimulus here
end
always begin
#5;
clk = ~clk;
end
endmodule
| 6.518526 |
module tb_fifo72togmii ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [71:0] dout;
reg empty;
wire rd_en;
wire rd_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
fifo72togmii fifo72togmii_tb (
.sys_rst(sys_rst),
.dout (dout),
.empty (empty),
.rd_en (rd_en),
.rd_clk(rd_clk),
.gmii_tx_clk(phy_tx_clk),
.gmii_tx_en(gmii_tx_en),
.gmii_txd(gmii_txd)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge rd_clk) begin
if (rd_en == 1'b1) $display("empty: %x dout: %x", empty, dout);
end
reg [11:0] counter;
reg [79:0] rom[0:4091];
always #1{empty, dout} <= rom[counter];
always @(posedge phy_tx_clk) begin
if (rd_en == 1'b1) counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_fifo72togmii);
$readmemh("./fifo72.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
| 7.037264 |
module tb_fifo9togmii ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [8:0] dout;
reg empty;
wire rd_en;
wire rd_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
fifo9togmii fifo9togmii_tb (
.sys_rst(sys_rst),
.dout (dout),
.empty (empty),
.rd_en (rd_en),
.rd_clk(rd_clk),
.gmii_tx_clk(phy_tx_clk),
.gmii_tx_en(gmii_tx_en),
.gmii_txd(gmii_txd)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge rd_clk) begin
if (gmii_tx_en == 1'b1) $display("gmii_tx_out: %x", gmii_txd);
end
reg [11:0] counter;
reg [8:0] rom[0:4091];
always #1{empty, dout} <= rom[counter];
always @(posedge phy_tx_clk) begin
if (rd_en == 1'b1) counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_fifo9togmii);
$readmemh("./fifo9.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
| 7.116518 |
module tb_fifos_interface ();
parameter FIFO_DEPTH = 32;
parameter LOG2_FIFO_DEPTH = 5;
parameter DATA_LINE_WIDTH = 40;
parameter CONTROL_LINE_WIDTH = 0;
reg clk = 0;
reg i_mc_sreq_wen = 0;
wire o_mc_sreq_fifo_empty = 0, o_mc_sreq_fifo_full = 0;
reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq_inbits;
reg i_sc_rreq_ren = 0;
wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_sc_rreq_outbits;
reg i_sc_sresp_wen = 0;
wire o_sc_sresp_fifo_empty = 0, o_sc_sresp_fifo_full = 0;
reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_sc_sresp_inbits;
reg i_mc_rresp_ren = 0;
wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_mc_rresp_outbits;
integer i;
initial begin
$monitor(
"%g i_mc_sreq_wen:%h o_mc_sreq_fifo_empty:%h o_mc_sreq_fifo_full:%h i_mc_sreq_inbits:%h",
$time, i_mc_sreq_wen, o_mc_sreq_fifo_empty, o_mc_sreq_fifo_full, i_mc_sreq_inbits);
$monitor("%g i_sc_rreq_ren:%h o_sc_rreq_outbits:%h", $time, i_sc_rreq_ren, o_sc_rreq_outbits);
$monitor(
"%g i_sc_sresp_wen:%h o_sc_sresp_fifo_empty:%h o_sc_sresp_fifo_full:%h i_sc_sresp_inbits:%h",
$time, i_sc_sresp_wen, o_sc_sresp_fifo_empty, o_sc_sresp_fifo_full, i_sc_sresp_inbits);
$monitor("%g i_mc_rresp_ren:%h o_mc_rresp_outbits:%h", $time, i_mc_rresp_ren,
o_mc_rresp_outbits);
clk = 0;
@(negedge clk);
i_mc_sreq_wen = 1;
// We are causing over flow in master send request fifo
for (i = 0; i < 70; i = i + 1) begin
i_mc_sreq_inbits = i;
@(negedge clk);
end
i_mc_sreq_wen = 0;
@(negedge clk);
i_sc_rreq_ren = 1;
// We are causing over flow in slave recieve request fifo
for (i = 0; i < 70; i = i + 1) begin
@(negedge clk);
end
i_sc_rreq_ren = 0;
@(negedge clk);
i_sc_sresp_wen = 1;
// We are causing over flow in slave send response fifo
for (i = 70; i < 140; i = i + 1) begin
i_sc_sresp_inbits = i;
@(negedge clk);
end
i_sc_sresp_wen = 0;
@(negedge clk);
i_mc_rresp_ren = 1;
// We are causing over flow in slave recieve request fifo
for (i = 70; i < 140; i = i + 1) begin
@(negedge clk);
end
i_mc_rresp_ren = 0;
#100 $finish;
end
// Generate simulation clock
always #1 clk = !clk;
// instantiate fifo system
fifos_interface strawfifo (
.clk(clk),
.i_mc_sreq_inbits(i_mc_sreq_inbits),
.i_mc_sreq_wen(i_mc_sreq_wen),
.o_mc_sreq_fifo_empty(o_mc_sreq_fifo_empty),
.o_mc_sreq_fifo_full(o_mc_sreq_fifo_full),
.i_sc_rreq_ren(i_sc_rreq_ren),
.o_sc_rreq_outbits(o_sc_rreq_outbits),
.i_sc_sresp_inbits(i_sc_sresp_inbits),
.i_sc_sresp_wen(i_sc_sresp_wen),
.o_sc_sresp_fifo_empty(o_sc_sresp_fifo_empty),
.o_sc_sresp_fifo_full(o_sc_sresp_fifo_full),
.i_mc_rresp_ren(i_mc_rresp_ren),
.o_mc_rresp_outbits(o_mc_rresp_outbits)
);
endmodule
| 7.508918 |
module tb_fifo_0 ();
//-----------------接口定义-------------------=//
reg sclk; //系统时钟
reg rd_clk; //读数据时钟
reg data_tvalid = 0; //FFT数据准备完毕
reg [13:0] data; //数据
reg rx_ready; //单片机接收准备
wire tx_ready; //uart发送准备
wire data_out;
//===============产生时钟信号==================//
initial sclk = 1;
always #5 sclk = ~sclk; //系统时钟100M
initial rd_clk = 1; //数据读取时钟
always begin
#100 rd_clk = 1;
#10 rd_clk = 0;
end
//===============产生valid信号=================//
reg [12:0] cnt = 0;
always @(posedge sclk) begin
if (cnt == 13'd8000) begin //计数一个周期
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end
always @(posedge sclk) begin
if (cnt <= 13'd1023) begin
data_tvalid <= 1; //fft数据准备完毕
data <= cnt; //产生数据
end else if (cnt > 13'd1024) begin
data_tvalid <= 0;
data <= data;
end else begin
data_tvalid <= data_tvalid;
data <= data;
end
end
//=================接收方信号=================//
initial begin
rx_ready = 0;
#75000 rx_ready = 1;
#180050 rx_ready = 0;
#44950 rx_ready = 1;
#180000 rx_ready = 0;
end
//-------------------例化---------------------//
FIFO_Control_0 FIFO_Control_0_inst0 (
.clk(sclk),
.wr_clk(sclk),
.rd_clk(rd_clk),
.data_valid(data_tvalid),
.rx_ready(rx_ready),
.data_re(data),
.tx_ready(tx_ready),
.data_out(data_out)
);
endmodule
| 7.434651 |
module tb;
parameter DATA_WIDTH = 4,
FIFO_DEPTH = 4,
PTR_WIDTH = 3;
reg clk, reset, put, get;
wire empty_bar, full_bar;
wire [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] data_in;
integer i=0;
//override parameters via instantiation
<<<<<<< HEAD
FIFO_2clk #(DATA_WIDTH,FIFO_DEPTH) u1(
.clk(clk),
.reset(reset),
.we(put),
.re(get),
.empty_bar(empty_bar),
.full_bar(full_bar),
.data_out(data_out),
.data_in(data_in));
=======
FIFO_2clk #(DATA_WIDTH,FIFO_DEPTH,PTR_WIDTH) u1(.rclk(rclk),
.wclk(wclk),
.reset(reset),
.we(put),
.re(get),
.empty_bar(empty_bar),
.full_bar(full_bar),
.data_out(data_out),
.data_in(data_in));
>>>>>>> 7e87010823ca2b64ac7405466f5008d2734c2363
initial
begin
data_in = 'd0;
clk = 1;
reset = 1;
put = 0;
get = 0;
#50;
reset = 0;
//fill the FIFO
for(i=0; i<FIFO_DEPTH; i=i+1)
begin
put = 1;
data_in = i+1;
get = 0;
<<<<<<< HEAD
#1.6;
put = 0;
=======
#100;
>>>>>>> 7e87010823ca2b64ac7405466f5008d2734c2363
end
//empty the FIFO
put = 0;
#10;
for(i=0; i<FIFO_DEPTH; i=i+1)
begin
get = 1;
<<<<<<< HEAD
#1.6;
put = 0;
get = 0;
end
#1000;
=======
#25;
end
#400;
//read and write simultaneously
for(i=0; i<FIFO_DEPTH; i=i+1)
begin
get = 1;
put = 1;
data_in = 4'hA + i;
#100;
end
#600;
>>>>>>> 7e87010823ca2b64ac7405466f5008d2734c2363
$finish;
end
//rclk (200 MHz: T=5ns)
always
#1.6 clk=~clk;
endmodule
| 7.110249 |
module tb;
parameter DATA_WIDTH = 4, FIFO_DEPTH = 4, PTR_WIDTH = 3;
reg rclk, wclk, reset, put, get;
wire empty_bar, full_bar;
wire [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] data_in;
integer i = 0;
//no parameters for GLS!
FIFO_2clk u1 (
.rclk(rclk),
.wclk(wclk),
.reset(reset),
.we(put),
.re(get),
.empty_bar(empty_bar),
.full_bar(full_bar),
.data_out(data_out),
.data_in(data_in)
);
initial begin
data_in = 'd0;
rclk = 1;
wclk = 1;
reset = 1;
put = 0;
get = 0;
#50;
reset = 0;
//fill the FIFO
for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
put = 1;
data_in = i + 1;
get = 0;
#100;
end
//empty the FIFO
put = 0;
#10;
for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
get = 1;
#25;
end
#400;
//read and write simultaneously
for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
get = 1;
put = 1;
data_in = 4'hA + i;
#100;
end
#600;
$finish;
end
//rclk (200 MHz: T=5ns)
always #2.5 rclk = ~rclk;
//wclk (10 MHz: T=100ns)
always #50 wclk = ~wclk;
initial begin
$sdf_annotate("sdf/FIFO_2clk.sdf", u1,,, "TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
end
endmodule
| 6.746419 |
module: fifo_2clock_cascade
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_2clock_cascade;
// Inputs
reg wclk;
reg [35:0] datain;
reg src_rdy_i;
reg rclk;
reg dst_rdy_i;
reg arst;
// Outputs
wire dst_rdy_o;
wire [15:0] space;
wire [35:0] dataout;
wire src_rdy_o;
wire [15:0] occupied;
// Instantiate the Unit Under Test (UUT)
fifo_2clock_cascade uut (
.wclk(wclk),
.datain(datain),
.src_rdy_i(src_rdy_i),
.dst_rdy_o(dst_rdy_o),
.space(space),
.rclk(rclk),
.dataout(dataout),
.src_rdy_o(src_rdy_o),
.dst_rdy_i(dst_rdy_i),
.occupied(occupied),
.arst(arst)
);
initial begin
// Initialize Inputs
wclk = 0;
datain = 0;
src_rdy_i = 0;
rclk = 0;
dst_rdy_i = 0;
arst = 1;
// Wait 100 ns for global reset to finish
#100;
@(posedge rclk)
dst_rdy_i = 1;
#50;
@(posedge wclk);
arst =0;
src_rdy_i = 1;
end
always begin
@(posedge wclk);
if (dst_rdy_o)
datain = datain + 1'b1;
end
always begin
#4; rclk = ~rclk; // 125 MHz
end
always begin
#3.333; wclk = ~wclk; // 150 MHz
end
endmodule
| 6.93239 |
module tb_fifo_async_fwft ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 201.7;
initial begin
$dumpfile("tb_fifo_async_fwft.vcd");
$dumpvars(0, tb_fifo_async_fwft);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(M_RATE / 2.0) m_clk = ~m_clk;
reg reset = 1'b1;
initial #(S_RATE * 100) reset = 1'b0;
localparam DATA_WIDTH = 16;
localparam PTR_WIDTH = 2;
wire [DATA_WIDTH-1:0] s_data;
wire s_valid;
wire s_ready;
wire [ PTR_WIDTH:0] s_free_count;
wire [DATA_WIDTH-1:0] m_data;
wire m_valid;
wire m_ready;
wire [ PTR_WIDTH:0] m_data_count;
jelly_fifo_async_fwtf #(
.DATA_WIDTH(DATA_WIDTH),
.PTR_WIDTH (PTR_WIDTH),
.DOUT_REGS (1)
) i_fifo_async_fwtf (
.s_reset (reset),
.s_clk (s_clk),
.s_data (s_data),
.s_valid (s_valid),
.s_ready (s_ready),
.s_free_count(s_free_count),
.m_reset (reset),
.m_clk (m_clk),
.m_data (m_data),
.m_valid (m_valid),
.m_ready (m_ready),
.m_data_count(m_data_count)
);
// write
reg [DATA_WIDTH-1:0] reg_data;
reg reg_valid;
always @(posedge s_clk) begin
if (reset) begin
reg_data <= 0;
reg_valid <= 1'b0;
end else begin
if (!(s_valid && !s_ready)) begin
reg_valid <= {$random};
end
if (s_valid && s_ready) begin
reg_data <= reg_data + 1'b1;
end
end
end
assign s_data = reg_data;
assign s_valid = reg_valid;
// read
reg [DATA_WIDTH-1:0] reg_expectation_value;
reg reg_ready;
always @(posedge m_clk) begin
if (reset) begin
reg_expectation_value <= 0;
reg_ready <= 1'b0;
end else begin
reg_ready <= {$random};
if (m_valid && m_ready) begin
if (m_data != reg_expectation_value) begin
$display("error!");
end
reg_expectation_value <= reg_expectation_value + 1'b1;
end
end
end
assign m_ready = reg_ready;
endmodule
| 7.464611 |
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