code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_csi_rx_word_align;
reg RST_N, CLK;
wire [7:0] DIN0, DIN1;
wire FSYNC;
wire VALID;
wire [31:0] DOUT;
always #(10) CLK = ~CLK;
initial begin
#0;
RST_N = 0;
CLK = 0;
#100;
RST_N = 1;
@(posedge CLK);
end
csi_rx_word_align u_csi_rx_word_align (
.RST_N(RST_N),
.CLK (CLK),
.DIN0(DIN0),
.DIN1(DIN1),
.FSYNC(FSYNC),
.VALID(VALID),
.DOUT (DOUT)
);
integer count;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
count <= 0;
end else begin
count <= count + 1;
end
end
function [15:0] DATA(input integer c);
begin
if (c < 12) begin
case (c)
0: DATA = 16'h0000;
1: DATA = 16'h0000;
2: DATA = 16'h0000;
3: DATA = 16'h0000;
4: DATA = 16'hB8AE;
5: DATA = 16'hD00A;
6: DATA = 16'h3CC3;
7: DATA = 16'h1406;
8: DATA = 16'h1407;
9: DATA = 16'h1407;
10: DATA = 16'h1407;
11: DATA = 16'h1407;
12: DATA = 16'h1407;
default: DATA = 16'h0000;
endcase
end else if (c < 1800) begin
DATA = 16'h1407;
end else begin
DATA = 16'h0000;
end
end
endfunction
wire [15:0] preDATA;
assign preDATA = DATA(count);
assign DIN0 = preDATA[7:0];
assign DIN1 = preDATA[15:8];
/*
40001A60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40001A70: 00 00 00 00 00 00 00 00 AE B8 00 00 0A D0 00 00
40001A80: C3 3C 00 00 06 14 00 00 07 14 00 00 07 14 00 00
40001A90: 07 14 00 00 07 14 00 00 47 14 00 00 07 14 00 00
40001AA0: 07 15 00 00 07 15 00 00 47 14 00 00 C7 15 00 00
*/
endmodule
| 6.817039 |
module tb_csi_rx_word_align;
reg RST_N, CLK;
wire [7:0] DIN0, DIN1;
wire FSYNC;
wire VALID;
wire [31:0] DOUT;
wire DETECT;
wire FS;
wire FE;
wire [ 7:0] L0;
wire [ 7:0] L1;
wire [15:0] DET_D0;
wire [15:0] DET_D1;
wire [15:0] PIXEL_NUM;
wire [15:0] LINE_NUM;
always #(10) CLK = ~CLK;
initial begin
#0;
RST_N = 0;
CLK = 0;
#100;
RST_N = 1;
@(posedge CLK);
end
csi_rx_word_align u_csi_rx_word_align (
.RST_N(RST_N),
.CLK (CLK),
.DIN0(DIN0),
.DIN1(DIN1),
.FSYNC(FSYNC),
.VALID(VALID),
.DOUT (DOUT),
.DETECT(DETECT),
.FS(FS),
.FE(FE),
.L0(L0),
.L1(L1),
.DET_D0(DET_D0),
.DET_D1(DET_D1),
.PIXEL_NUM(PIXEL_NUM),
.LINE_NUM(LINE_NUM)
);
integer count;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
count <= 0;
end else begin
count <= count + 1;
end
end
function [15:0] DATA(input integer c);
begin
if (c < 12) begin
case (c)
0: DATA = 16'h0000;
1: DATA = 16'h0000;
2: DATA = 16'h0000;
3: DATA = 16'h0000;
4: DATA = 16'hB8AE;
5: DATA = 16'hD00A;
6: DATA = 16'h3CC3;
7: DATA = 16'h1406;
8: DATA = 16'h1407;
9: DATA = 16'h1407;
10: DATA = 16'h1407;
11: DATA = 16'h1407;
12: DATA = 16'h1407;
default: DATA = 16'h0000;
endcase
end else if (c < 1800) begin
DATA = 16'h1407;
end else begin
DATA = 16'h0000;
end
end
endfunction
wire [15:0] preDATA;
assign preDATA = DATA(count);
assign DIN0 = preDATA[7:0];
assign DIN1 = preDATA[15:8];
/*
40001A60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40001A70: 00 00 00 00 00 00 00 00 AE B8 00 00 0A D0 00 00
40001A80: C3 3C 00 00 06 14 00 00 07 14 00 00 07 14 00 00
40001A90: 07 14 00 00 07 14 00 00 47 14 00 00 07 14 00 00
40001AA0: 07 15 00 00 07 15 00 00 47 14 00 00 C7 15 00 00
*/
endmodule
| 6.817039 |
module tb_csrbrg ();
reg sys_clk;
reg sys_rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [13:0] csr_a;
wire csr_we;
wire [31:0] csr_do;
reg [31:0] csr_di;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
csrbrg dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i (wb_we_i),
.wb_ack_o(wb_ack_o),
/* CSR bus master */
.csr_a (csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
/* Simulate CSR slave */
reg [31:0] csr1;
reg [31:0] csr2;
wire csr_selected = (csr_a[13:10] == 4'ha);
always @(posedge sys_clk) begin
if (csr_selected) begin
if (csr_we) begin
$display("Writing %x to CSR %x", csr_do, csr_a[0]);
case (csr_a[0])
1'b0: csr1 <= csr_do;
1'b1: csr2 <= csr_do;
endcase
end
case (csr_a[0])
1'b0: csr_di <= csr1;
1'b1: csr_di <= csr2;
endcase
end else
/* we must set data to 0 to be able to use a distributed OR topology
* in the slaves->master datapath.
*/
csr_di <= 32'd0;
end
always begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
/* Try some transfers */
wbwrite(32'h0000a000, 32'hcafebabe);
wbwrite(32'h0000a004, 32'habadface);
wbread(32'h0000a000);
wbread(32'h0000a004);
$finish;
end
endmodule
| 7.579757 |
module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CT;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg chip_select;
// Outputs
wire signal_out;
wire [3:0] ciclo_actual;
// Instantiate the Unit Under Test (UUT)
Modificacion_Ciclo_Trabajo uut (
.clk_100MHz(clk_100MHz),
.clk_de_trabajo(clk_de_trabajo),
.rst(rst),
.up(up),
.down(down),
.chip_select(chip_select),
.signal_out(signal_out),
.ciclo_actual(ciclo_actual)
);
initial begin
forever #5 clk_100MHz = ~clk_100MHz;
end
initial begin
forever #10 clk_de_trabajo = ~clk_de_trabajo;
end
initial begin
// Initialize Inputs
clk_100MHz = 0;
clk_de_trabajo = 0;
rst = 1;
up = 0;
down = 0;
chip_select = 1;
// Wait 100 ns for global reset to finish
#10;
rst = 0;
/*
#10
up = 1;
#50
up = 0;
*/
// Add stimulus here
end
endmodule
| 8.169432 |
module tb_ctrl #(
parameter GUI_RUN = 0,
CLK_FREQ_MHZ = 200
) (
// Clock and reset outputs
output reg clk_x2,
output reg clk,
output reg clk_div2,
output reg rst_n,
output [31:0] count_vec,
input [31:0] timeout,
// Simulation status and control inputs
input error,
input do_stop,
input do_finish,
input partial_test,
output failed,
output passed
);
integer count;
wire end_sim;
real clk_x2_period;
initial begin
clk_x2 = 1'b1;
clk = 1'b1;
clk_div2 = 1'b1;
rst_n = 1'b0;
count = 0;
clk_x2_period = 1000000.0 / (CLK_FREQ_MHZ * 2.0);
end
// ---------------------------------------
// Clock and reset generation
// ---------------------------------------
// Clock generation with concurrent procedure call
always #(clk_x2_period / 2.0) clk_x2 <= ~clk_x2;
// Export counter
assign count_vec = count;
// Derive system clock from master clock
always @(posedge clk_x2) begin
clk <= ~clk;
end
always @(posedge clk) begin
clk_div2 <= ~clk_div2;
end
// Generate a reset
always @(posedge clk) begin
count <= count + 1;
rst_n <= (count > 10) ? 1'b1 : 1'b0;
end
// End-of-simulation signals
assign end_sim = (count == timeout || do_stop == 1'b1 || do_finish == 1'b1) ? 1'b1 : 1'b0;
assign failed = (end_sim == 1'b1 && (error == 1'b1 || count == timeout)) ? 1'b1 : 1'b0;
assign passed = (end_sim == 1'b1 && error == 1'b0) ? 1'b1 : 1'b0;
// ---------------------------------------
// Simulation control from VProc over
// CSR bus
// ---------------------------------------
always @(posedge clk) begin
// ---------------------------------------
// End simulation
// ---------------------------------------
// If end of simulation, stop
if (end_sim == 1'b1) begin
if (error == 1'b1) $display("*** FAIL: errors found");
else begin
if (count >= timeout) $display("*** FAIL: timeout");
else if (partial_test == 1'b1) $display("NO FAILURES");
else $display("SUCCESS");
end
if (GUI_RUN != 0 || (do_stop == 1'b1 && do_finish == 1'b0)) $stop;
else $finish;
end
end
endmodule
| 8.371975 |
module tb_CTRL_ex_time;
parameter s_IDLE = 2'b00;
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
reg r_Exp_increase = 1'b0;
reg r_Exp_decrease = 1'b0;
reg r_Clock = 1'b0;
reg r_Reset = 1'b0;
reg [1:0] r_Main_FSM = s_IDLE;
wire [4:0] w_count_time;
//Instantiation of CTRL_ex_time, called UUT (Unit Under Test)
CTRL_ex_time UUT (
.i_Exp_increase(r_Exp_increase),
.i_Exp_decrease(r_Exp_decrease),
.i_Clock(r_Clock),
.i_Reset(r_Reset),
.i_Main_FSM(r_Main_FSM),
.o_count_time(w_count_time)
);
always #2 r_Clock <= !r_Clock;
initial begin //Function calls to create a *.vcd file
$dumpfile("dump.vcd"); //NECESSARY JUST TO SIMULATE IN edaplayground.com
$dumpvars(1); //WITH EITHER VERILOG OR SYSTEMVERILOG
end
initial begin //Initial block
r_Reset <= 1'b1;
#10 //10us seconds
r_Reset <= 1'b0;
r_Main_FSM <= s_IDLE;
r_Exp_increase <= 1'b1;
#10 r_Exp_increase <= 1'b0;
#10 r_Exp_increase <= 1'b1;
#10 r_Exp_increase <= 1'b0;
#10 r_Exp_increase <= 1'b1;
#10 r_Exp_increase <= 1'b0;
#10 r_Exp_increase <= 1'b1;
#10 r_Exp_increase <= 1'b0;
#10 r_Exp_decrease <= 1'b1;
#10 r_Exp_decrease <= 1'b0;
#10 r_Exp_decrease <= 1'b1;
#10 r_Exp_decrease <= 1'b0;
#10 r_Main_FSM <= s_EXPOSURE;
$display("Test Complete");
end
endmodule
| 6.562911 |
module tb_ctrl_fsm ();
parameter INSTR_WIDTH = 16;
parameter ADDR_WIDTH_OP = 4;
parameter ADDR_WIDTH_PC = 12;
parameter OPCODE_LGNT = 8;
parameter JMPR_OPCODE = 4;
parameter SEG_REG_WIDTH = 4;
reg clk_i;
reg a_reset_l;
reg [INSTR_WIDTH-1:0] out_data_pram_i; //output data from the PRAM
reg intr_h_i; //interrupt request
reg ovr_i; //goes to 1 if wish bone already loaded
reg valid_i; //loaded WISHBONE
reg wb_ack_i; //full WISHBONE and ready to be read
reg [INSTR_WIDTH-1:0] data_b_bus_i; //bus from B-reg
reg [INSTR_WIDTH-1:0] data_wb_bus_i; //bus from wishbone
reg mask_i; //bit for masking
reg sync_h_i; //synchronization signal
reg alu_valid_i; //valid signal for mult and div
wire [OPCODE_LGNT-1:0] alu_op_o; // alu operation
wire wb_we_o; //enable wrtie WISHBONE
wire wb_start_o; //start to wrt from WISHBONE
wire regfile_we_o; //register file writes on reg A
wire [ADDR_WIDTH_OP-1:0] adr_a_o; //addr reg A
wire [ADDR_WIDTH_OP-1:0] adr_b_o; //addr reg B
wire seg_reg_we_o; //write enable to write on reg. file
wire [SEG_REG_WIDTH-1:0] seg_reg_o; //segmentation register to load reg. file
wire adr_ld_o; //load addr out to load input address next block
wire [ADDR_WIDTH_PC-1:0] adr_pc_o; //jumping addr from pc to pram
wire init_mode_o; //begin initial mode: copy from WISH BONE to PRAM
wire [1:0] alu_mux_o; //output bus to control MUX ALU instr[3], ALU[2] & data_in[1]
wire [1:0] sp_mux_o; //output bus to control MUX, B_reg[2] & SP[1]
wire [1:0] data_mux_o; //output bus to control PC[2] & data_out[1]
wire inc_o; //increment address of program counter
//wire [INSTR_WIDTH-1:0] data_instr_o; //data from the instruction
ctrl_fsm ctrl_fsm_i (
.clk_i (clk_i ),
.a_reset_l (a_reset_l ),
.out_data_pram_i(out_data_pram_i),
.intr_h_i (intr_h_i ),
.ovr_i (ovr_i ),
.valid_i (valid_i ),
.wb_ack_i (wb_ack_i ),
.data_b_bus_i (data_b_bus_i ),
.data_wb_bus_i (data_wb_bus_i ),
.mask_i (mask_i ),
.sync_h_i (sync_h_i ),
.alu_valid_i (alu_valid_i ),
.alu_op_o (alu_op_o ),
.wb_we_o (wb_we_o ),
.wb_start_o (wb_start_o ),
.regfile_we_o (regfile_we_o ),
.adr_a_o (adr_a_o ),
.adr_b_o (adr_b_o ),
.seg_reg_we_o (seg_reg_we_o ),
.seg_reg_o (seg_reg_o ),
.adr_ld_o (adr_ld_o ),
.adr_pc_o (adr_pc_o ),
.init_mode_o (init_mode_o ),
.alu_mux_o (alu_mux_o ),
.sp_mux_o (sp_mux_o ),
.data_mux_o (data_mux_o ),
.inc_o (inc_o )
//.data_instr_o (data_instr_o )
);
///////////////////////////////////////////////
//// Template for clk and reset generation ////
//// uncomment it when needed ////
///////////////////////////////////////////////
parameter CLKPERIODE = 100;
initial clk_i = 1'b0;
always #(CLKPERIODE / 2) clk_i = !clk_i;
initial begin
a_reset_l = 1'b0;
#33 a_reset_l = 1'b1;
end
///////////////////////////////////////////////
// Template for testcase specific pattern generation
// File has to be situated in simulation/<simulator_name>/[testcase] directory
`include "testcase.v"
endmodule
| 7.612174 |
module: cumsum
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cumsum;
// Inputs
reg clk;
reg ce;
reg rst;
reg [13:0] in;
// Outputs
wire [22:0] out;
// Instantiate the Unit Under Test (UUT)
cumsum uut (
.clk(clk),
.ce(ce),
.rst(rst),
.in(in),
.out(out)
);
integer i;
integer sum;
initial begin
// Initialize Inputs
clk = 0;
ce = 1;
rst = 0;
in = 0;
sum = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in = 2;
for(i = 0; i < 50; i = i + 1)
begin
if(out != sum) $stop;
clk = 0; #1;
sum = sum + 2;
clk = 1; #1;
end
$stop;
end
endmodule
| 7.392478 |
module tb_dac_diff;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg [1:0] tb_data;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_dac_diff #(
.WORD_WIDTH(2),
.BYTE_WIDTH(16),
.ONEZERO_OUT(16'h7FFF),
.ZEROONE_OUT(16'h8000),
.SAME_OUT(0)
) dut (
.clk(tb_data_clk),
.rstn(~tb_rst),
// diff input
.diff_in(tb_data),
// write output
.rd_data(),
.rd_valid(),
.rd_dunf()
);
//reset
initial begin
tb_rst <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_dac_diff.vcd");
$dumpvars(0, tb_dac_diff);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 4);
end
//product data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_data <= 0;
end else begin
tb_data <= $random % 4;
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 8.17104 |
module tb_dac_switch;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg tb_data;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_dac_switch #(
.BYTE_WIDTH(16)
) dut (
// diff input
.fifo_valid(tb_data),
.fifo_data("FIFO_DATA"),
.fifo_dunf(1),
.fifo_wren(),
// dac diff input
.wr_data("DAC_DIFF_DATA"),
.wr_valid(1'b1),
.wr_dunf(1'b1),
// dac output
.dac_data(),
.dac_dunf(),
.dac_valid(1'b1)
);
//reset
initial begin
tb_rst <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_dac_switch.vcd");
$dumpvars(0, tb_dac_switch);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 4);
end
//product data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_data <= 0;
end else begin
tb_data <= $random % 2;
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 9.196998 |
module tb_daq #(
parameter NDAQ = 5
) (
input wire clk,
input wire [31:0] systime,
output wire eth_tx0,
output wire eth_tx1,
output wire eth_tx_en,
input wire eth_rx_clk,
input wire [31:0] daq_data[NDAQ],
input wire [NDAQ-1:0] daq_valid,
input wire [NDAQ-1:0] daq_end,
input wire [NDAQ-1:0] daq_req,
output wire [NDAQ-1:0] daq_grant,
input wire [1:0] enable,
output wire [31:0] sig_data,
output reg sig_end,
output reg sig_valid = 0,
output reg sig_req = 0,
input wire sig_grant,
input wire [31:0] s_arg_data,
output wire s_arg_advance,
input wire [CMD_BITS-1:0] s_cmd,
input wire s_cmd_ready,
output wire s_cmd_done,
output wire [32:0] s_param_data,
output wire s_param_write,
output wire s_invol_req,
input wire s_invol_grant,
input [SIG_WIDTH-1:0] signal
);
localparam CMD_BITS = 8;
localparam MAC_PACKET_BITS = 9; /* 2^9 * 4 bytes > 1500 */
localparam HZ = 48000000;
wire [31:0] daqo_data;
wire daqo_data_rd_en;
wire [MAC_PACKET_BITS-1:0] daqo_len;
wire daqo_len_ready;
wire daqo_len_rd_en;
/* no system verilog: flatten daq_data */
wire [(32 * NDAQ)-1:0] _daq_data;
genvar gi;
generate
for (gi = 0; gi < NDAQ; gi = gi + 1) assign _daq_data[((gi+1)*32)-1:(gi*32)] = daq_data[gi];
endgenerate
daq #(
.NDAQ(NDAQ),
.MAC_PACKET_BITS(MAC_PACKET_BITS)
) u_daq (
.clk(clk),
.systime(systime),
.daq_data_in(_daq_data),
.daq_end(daq_end),
.daq_valid(daq_valid),
.daq_req(daq_req),
.daq_grant(daq_grant),
.daqo_data(daqo_data),
.daqo_data_rd_en(daqo_data_rd_en),
.daqo_len(daqo_len),
.daqo_len_ready(daqo_len_ready),
.daqo_len_rd_en(daqo_len_rd_en),
.debug()
);
reg [15:0] ether_type = 16'h5139;
reg [47:0] src_mac = 48'h123456789abc;
reg [47:0] dst_mac = 48'h665544332211;
mac #(
.HZ(HZ),
.MAC_PACKET_BITS(MAC_PACKET_BITS),
.PACKET_WAIT_FRAC(100),
.ES_QUEUE(0),
.ES_DISCARD(1),
.ES_RUNNING(2)
) u_mac (
.clk(clk),
.tx0(eth_tx0),
.tx1(eth_tx1),
.tx_en(eth_tx_en),
.rx_clk_in(eth_rx_clk),
.daqo_data(daqo_data),
.daqo_data_rd_en(daqo_data_rd_en),
.daqo_len(daqo_len),
.daqo_len_ready(daqo_len_ready),
.daqo_len_rd_en(daqo_len_rd_en),
.ether_type(ether_type),
.src_mac(src_mac),
.dst_mac(dst_mac),
.enable_in(enable),
.debug()
);
localparam SIG_WIDTH = 18;
reg [31:0] s_daq_data;
reg s_daq_end;
reg s_daq_valid = 0;
reg s_daq_req = 0;
wire s_daq_grant;
signal #(
.HZ(HZ),
.SIG_WIDTH(SIG_WIDTH),
.CMD_BITS(CMD_BITS),
.CMD_CONFIG(28),
.SIG_WAIT_FRAC(1000),
.RLE_BITS(12),
.FLUSH_FREQ(10000),
.DAQT_DATA(64)
) u_signal (
.clk(clk),
.systime(systime),
.daq_data (sig_data),
.daq_end (sig_end),
.daq_valid(sig_valid),
.daq_req (sig_req),
.daq_grant(sig_grant),
.arg_data(s_arg_data),
.arg_advance(s_arg_advance),
.cmd(s_cmd),
.cmd_ready(s_cmd_ready),
.cmd_done(s_cmd_done),
.param_data(s_param_data),
.param_write(s_param_write),
.invol_req(s_invol_req),
.invol_grant(s_invol_grant),
.signal(signal)
);
endmodule
| 7.252753 |
module tb_dat #(
parameter DATA_WIDTH = 8
) ();
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_i;
reg [`OP_WIDTH-1:0] ctr_aluop_i;
reg ctr_a_reg_en_i;
reg [`CTR_CARRYMUX_WIDTH-1:0] ctr_carrymux_i;
wire carry_o;
wire [DATA_WIDTH-1:0] data_o;
integer j;
dat #(
.DATA_WIDTH(DATA_WIDTH)
) i_dat (
.clk_i(clk),
.rst_i(rst),
.data_i(data_i),
.ctr_aluop_i(ctr_aluop_i),
.ctr_carrymux_i(ctr_carrymux_i),
.ctr_a_reg_en_i(ctr_a_reg_en_i),
.carry_o(carry_o),
.data_o (data_o)
);
initial begin
$dumpfile("tb_dat.vcd");
// $dumpvars(level, list_of_variables_or_modules)
// level = 1 -> only variables in list_of_variables_or_modules
$dumpvars(0, tb_dat);
//$readmemb("tb/egse.stim", stim);
//$monitor("%b%b LED:%b RS232TX:%b", clk, rst_n, led, rs232_tx);
clk = 0;
rst = 1;
data_i = 8'b00000000;
ctr_aluop_i = `OP_ADD;
ctr_carrymux_i = `CARRY_OP_GEN;
ctr_a_reg_en_i = 1'b0;
#10 rst = 0;
@(posedge clk)
/* Add zero to accumulator */
ctr_a_reg_en_i = 1'b1;
for (j = 0; j < 10; j = j + 1) begin
@(posedge clk)
if (data_o != data_i) begin
$display("Add zero fail: j=%d", j);
end
if (carry_o != 1'b0) begin
$display("Add zero carry fail: j=%d", j);
end
end
/* Keep state */
data_i = 8'b01011001;
ctr_a_reg_en_i = 1'b0;
for (j = 0; j < 10; j = j + 1) begin
@(posedge clk)
if (data_o == data_i) begin
$display("Keep state fail: j=%d", j);
end
end
/* Add one to accumulator */
data_i = 8'b00000001;
@(posedge clk);
ctr_a_reg_en_i = 1'b1;
for (j = 1; j < 2 ** DATA_WIDTH; j = j + 1) begin
@(posedge clk);
if (data_o != j) begin
$display("Add one fail: j=%d", j);
end
end
@(posedge clk);
if (carry_o != 1'b1) begin
$display("Carry generation fail");
end
/* Clear carry */
data_i = 8'b00000000;
ctr_aluop_i = `OP_JCC;
ctr_carrymux_i = `CARRY_OP_CLR;
ctr_a_reg_en_i = 1'b0;
@(posedge clk)
if (carry_o != 1'b0) begin
$display("Carry clear fail");
end
/* NOR zero accumulator content with all zero to get all one */
data_i = 8'b00000000;
ctr_aluop_i = `OP_NOR;
ctr_carrymux_i = `CARRY_OP_CLR;
ctr_a_reg_en_i = 1'b1;
@(posedge clk)
#1
if (data_o != 8'b1111_1111) begin
$display("NOR with zero fail");
end
/* NOR all one accumulator with all one to get all zero */
data_i = 8'b1111_1111;
ctr_aluop_i = `OP_NOR;
ctr_carrymux_i = `CARRY_OP_CLR;
ctr_a_reg_en_i = 1'b1;
@(posedge clk)
#1
if (data_o != 0) begin
$display("NOR with one fail");
end
$finish;
end
always #1 clk = !clk;
endmodule
| 7.067317 |
module tb_data32_to_data16 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire rec_en_out; //输出16位数据使能信号
wire [15:0] rec_data_out; //输出16位数据
//reg define
reg eth_rx_clk; //系统时钟
reg sys_rst_n; //复位信号,低有效
reg rec_en_in; //32位数据使能信号
reg [31:0] rec_data_in; //32位数据
reg [ 2:0] cnt_data; //数据间隔计数器
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//时钟、复位信号
initial begin
eth_rx_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #20 eth_rx_clk = ~eth_rx_clk;
//cnt_data:数据间隔计数器
always @(posedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_data <= 3'd0;
else cnt_data <= cnt_data + 3'd1;
//rec_data_in:32位数据
always @(posedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) rec_data_in <= 32'h12_34_56_78;
else if (cnt_data == 3'd7) rec_data_in <= rec_data_in + 1'b1;
else rec_data_in <= rec_data_in;
//rec_en_in:32位数据使能信号
always @(posedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) rec_en_in <= 1'b0;
else if (cnt_data == 3'd7) rec_en_in <= 1'b1;
else rec_en_in <= 1'b0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------ data32_to_data16_inst -------------
data32_to_data16 data32_to_data16_inst (
.sys_clk (eth_rx_clk), //系统时钟
.sys_rst_n (sys_rst_n), //复位信号,低有效
.rec_en_in (rec_en_in), //输入32位数据使能信号
.rec_data_in(rec_data_in), //输入32位数据
.rec_en_out (rec_en_out), //输出16位数据使能信号
.rec_data_out(rec_data_out) //输出16位数据
);
endmodule
| 7.797857 |
module: dataControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_dataControl;
// Inputs
reg clk;
reg reset_n;
reg [455:0] wenmiao_rx_frame;
reg wenmiao_tx_busy;
reg wenmiao_rx_frame_done;
reg wenmiao_check_sum_error;
reg wenmiao_comNoResponse;
reg feikong_tx_busy;
reg [319:0] feikong_rx_frame;
reg feikong_rx_frame_done;
reg feikong_check_sum_error;
reg feikong_comNoResponse;
reg [71:0] fakong_rx_frame;
reg fakong_tx_busy;
reg fakong_rx_frame_done;
reg fakong_check_sum_error;
reg fakong_comNoResponse;
reg [199:0] adt_rx_frame;
reg adt_rx_frame_done;
reg adt_tx_busy;
reg adt_check_sum_error;
reg adt_comNoResponse;
// Outputs
wire [159:0] wenmiao_tx_frame;
wire wenmiao_tx_start;
wire [79:0] feikong_tx_frame;
wire feikong_tx_frame_start;
wire [255:0] fakong_tx_frame;
wire fakong_tx_start;
wire adt_wr_ram;
wire [15:0] adt_addr_ram;
wire [7:0] adt_data_ram;
wire adt_tx_frame_start;
// Instantiate the Unit Under Test (UUT)
dataControl uut (
.clk(clk),
.reset_n(reset_n),
.wenmiao_tx_frame(wenmiao_tx_frame),
.wenmiao_tx_start(wenmiao_tx_start),
.wenmiao_rx_frame(wenmiao_rx_frame),
.wenmiao_tx_busy(wenmiao_tx_busy),
.wenmiao_rx_frame_done(wenmiao_rx_frame_done),
.wenmiao_check_sum_error(wenmiao_check_sum_error),
.wenmiao_comNoResponse(wenmiao_comNoResponse),
.feikong_tx_frame(feikong_tx_frame),
.feikong_tx_frame_start(feikong_tx_frame_start),
.feikong_tx_busy(feikong_tx_busy),
.feikong_rx_frame(feikong_rx_frame),
.feikong_rx_frame_done(feikong_rx_frame_done),
.feikong_check_sum_error(feikong_check_sum_error),
.feikong_comNoResponse(feikong_comNoResponse),
.fakong_tx_frame(fakong_tx_frame),
.fakong_tx_start(fakong_tx_start),
.fakong_rx_frame(fakong_rx_frame),
.fakong_tx_busy(fakong_tx_busy),
.fakong_rx_frame_done(fakong_rx_frame_done),
.fakong_check_sum_error(fakong_check_sum_error),
.fakong_comNoResponse(fakong_comNoResponse),
.adt_rx_frame(adt_rx_frame),
.adt_rx_frame_done(adt_rx_frame_done),
.adt_tx_busy(adt_tx_busy),
.adt_check_sum_error(adt_check_sum_error),
.adt_comNoResponse(adt_comNoResponse),
.adt_wr_ram(adt_wr_ram),
.adt_addr_ram(adt_addr_ram),
.adt_data_ram(adt_data_ram),
.adt_tx_frame_start(adt_tx_frame_start)
);
initial begin
// Initialize Inputs
clk = 0;
reset_n = 0;
wenmiao_rx_frame = 0;
wenmiao_tx_busy = 0;
wenmiao_rx_frame_done = 0;
wenmiao_check_sum_error = 0;
wenmiao_comNoResponse = 0;
feikong_tx_busy = 0;
feikong_rx_frame = 0;
feikong_rx_frame_done = 0;
feikong_check_sum_error = 0;
feikong_comNoResponse = 0;
fakong_rx_frame = 0;
fakong_tx_busy = 0;
fakong_rx_frame_done = 0;
fakong_check_sum_error = 0;
fakong_comNoResponse = 0;
adt_rx_frame = 0;
adt_rx_frame_done = 0;
adt_tx_busy = 0;
adt_check_sum_error = 0;
adt_comNoResponse = 0;
// Wait 100 ns for global reset to finish
#40
reset_n = 1;
#40
reset_n = 0;
#20
reset_n = 1;
#20
wenmiao_tx_busy = 1;
fakong_tx_busy = 1;
#20
wenmiao_tx_busy = 0;
fakong_tx_busy = 0;
// Add stimulus here
//forever #10 clk = ~clk;
end
always #10 clk = ~clk;
endmodule
| 6.805526 |
module DataMemoryTestbench;
reg clock;
reg [3:0] address;
reg [7:0] writeData;
wire [7:0] dataOut;
reg MemRead;
reg MemWrite;
DataMemory dut (
clock,
address,
writeData,
dataOut,
MemRead,
MemWrite
);
initial begin
clock = 0;
address = 0;
writeData = 0;
MemRead = 0;
MemWrite = 0;
$display("Teste 1: Escrevendo na memoria");
$display("Supondo que $mem contem o valor 22");
$display("Escrevendo no endereco 10 da memoria de dados");
$display("Valor armazenado na posicao 10: %d", dut.data[10]);
MemWrite = 1;
writeData = 22;
address = 10;
#1 clock = 1;
#1 clock = 0;
$display("Valor armazenado na posicao 10: %d", dut.data[10]);
$display("Teste 2: Lendo da memoria");
$display("Lendo da posicao 10 da memoria de dados");
$display("Valor armazenado na posicao 10: %d", dut.data[10]);
MemRead = 1;
MemWrite = 0;
address = 10;
#1 clock = 0;
#1 clock = 1;
$display("Valor da saida do banco de memoria: %d", dataOut);
end
initial begin
$monitor("Time=%0d, Clock=%d, MemRead=%b, MemWrite=%b, address=%d, writeData=%d, dataOut=%d",
$time, clock, MemRead, MemWrite, address, writeData, dataOut);
end
endmodule
| 6.894818 |
module tb_DATAPATH;
parameter n = 16, m = 16;
wire [n+m-1:0] tb_Product;
wire tb_done;
reg tb_clk, tb_rst, tb_start;
reg [15:0] tb_multiplicand, tb_multiplier;
DATAPATH DUT (
.Product(tb_Product),
.done(tb_done),
.clk(tb_clk),
.multiplicand(tb_multiplicand),
.multiplier(tb_multiplier),
.start(tb_start),
.rst(tb_rst)
);
initial tb_clk = 1'b0;
always #10 tb_clk = ~tb_clk;
integer i;
initial begin
tb_rst = 1'b1;
#15 tb_rst = 1'b0;
tb_start = 1'b1;
$monitor($time, "tb_Product=%b", tb_Product);
for (i = 1; i <= 1; i = i + 1) begin
tb_multiplicand = {$random} % 65000;
tb_multiplier = {$random} % 75000;
#400;
end
$finish;
end
endmodule
| 6.540094 |
module tb_data_async ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 21.7;
initial begin
$dumpfile("tb_data_async.vcd");
$dumpvars(0, tb_data_async);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(M_RATE / 2.0) m_clk = ~m_clk;
reg reset = 1'b1;
initial #(S_RATE * 100) reset = 1'b0;
localparam DATA_WIDTH = 16;
wire [DATA_WIDTH-1:0] s_data;
wire s_valid;
wire s_ready;
wire [DATA_WIDTH-1:0] m_data;
wire m_valid;
wire m_ready;
jelly_data_async #(
.DATA_WIDTH(DATA_WIDTH)
) i_data_async (
.s_reset(reset),
.s_clk (s_clk),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_reset(reset),
.m_clk (m_clk),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// write
reg [DATA_WIDTH-1:0] reg_data;
reg reg_valid;
always @(posedge s_clk) begin
if (reset) begin
reg_data <= 0;
reg_valid <= 1'b0;
end else begin
if (!(s_valid && !s_ready)) begin
reg_valid <= {$random};
end
if (s_valid && s_ready) begin
reg_data <= reg_data + 1'b1;
end
end
end
assign s_data = reg_data;
assign s_valid = reg_valid;
// read
reg [DATA_WIDTH-1:0] reg_expectation_value;
reg reg_ready;
always @(posedge m_clk) begin
if (reset) begin
reg_expectation_value <= 0;
reg_ready <= 1'b0;
end else begin
reg_ready <= {$random};
if (m_valid && m_ready) begin
if (m_data != reg_expectation_value) begin
$display("error!");
end
reg_expectation_value <= reg_expectation_value + 1'b1;
end
end
end
assign m_ready = reg_ready;
reg [7:0] reg_puls_count = 0;
always @(posedge s_clk) begin
reg_puls_count <= reg_puls_count + 1;
end
wire pulse_async;
jelly_pulse_async i_pulse_async (
.s_reset(reset),
.s_clk (s_clk),
.s_pulse(1), // reg_puls_count == 0),
.m_reset(reset),
.m_clk (m_clk),
.m_pulse(pulse_async)
);
endmodule
| 7.930142 |
module tb_data_gen ();
reg sys_clk;
reg sys_rst_n;
wire [19:0] data;
wire [ 5:0] point;
wire sign;
wire seg_en;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
data_gen #(
.CNT_MAX (9),
.DATA_MAX(9)
) data_gen_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.data (data),
.point (point),
.sign (sign),
.seg_en(seg_en)
);
endmodule
| 6.938083 |
module tb_data_mem;
// Inputs
reg clk;
reg rst;
reg wea;
reg web;
reg [`DATA_WIDTH*2-1:0] dina;
reg [`DATA_WIDTH*2-1:0] dinb;
reg wben;
reg rden;
reg inst_v;
reg [`INST_WIDTH-1:0] inst;
// Outputs
wire [`DATA_WIDTH*2-1:0] douta;
wire [`DATA_WIDTH*2-1:0] doutb;
// Instantiate the Unit Under Test (UUT)
data_mem DMEM (
.clk(clk),
.rst(rst),
.wea(wea),
.web(web),
.dina(dina),
.dinb(dinb),
.wben(wben),
.rden(rden),
.inst_v(inst_v),
.inst(inst),
.douta(douta),
.doutb(doutb)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
integer cycle;
initial cycle = 0;
always @(posedge clk) cycle = cycle + 1;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
wea = 0;
web = 0;
dina = 0;
dinb = 0;
wben = 0;
rden = 0;
inst_v = 0;
inst = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
// Add stimulus here
#20;
wea = 0;
rst = 0;
#20;
wea = 0;
#20;
wea = 0;
#20;
wea = 0;
// wea or rden is aligned with inst; 1 cycle ahead of wdata
#20;
wea = 0;
#20;
wea = 1;
dina = 32'h0004_0002; // 4 + j*2
#20;
wea = 1;
dina = 32'h0003_0001; // 3 + j*1
#20;
wea = 1;
dina = 32'h0008_0006; // 8 + j*6
#20;
wea = 1;
dina = 32'h0007_0005; // 7 + j*5
#20;
wea = 1;
dina = 32'h000c_000a; // 12 + j*10
#20;
wea = 1;
dina = 32'h000b_0009; // 11 + j*9
#20;
wea = 0;
dina = 32'hxxxx_xxxx;
// Load the instructions (only affects the raddr1, raddr0, and waddr)
#20;
inst_v = 1;
rden = 0;
inst = 32'h60_01_00_10; // CMPLX_MULT
#20;
inst_v = 1;
rden = 1;
inst = 32'h60_03_02_11; // CMPLX_MULT
#20;
inst_v = 1;
rden = 1;
inst = 32'h60_05_04_12; // CMPLX_MULT
#20;
inst_v = 0;
rden = 1;
inst = 32'hxx_xx_xx_xx;
#20;
rden = 0;
// write back the 3 results generated by the ALU
#20;
wben = 1;
#20;
wben = 1;
dina = 32'h000a_000a;
#20;
wben = 1;
dina = 32'h001a_0052;
#20;
wben = 0;
dina = 32'h002a_00da;
#20;
wben = 0;
dina = 32'hxxxx_xxxx;
// #20; inst_v = 1; rden = 0; inst = 32'h60_90_8F_13; // CMPLX_MULT
// #20; inst_v = 1; rden = 1; inst = 32'h60_92_91_14; // CMPLX_MULT
// #20; inst_v = 0; rden = 1; inst = 0;
// #20; rden = 0;
#20;
web = 1;
dinb = 32'h1100_1100;
#20;
web = 1;
dinb = 32'h2200_2200;
#20;
web = 1;
dinb = 32'h3300_3300;
#20;
web = 1;
dinb = 32'h4400_4400;
#20;
web = 0;
dinb = 32'hxxxx_xxxx;
#20;
inst_v = 1;
rden = 0;
inst = 32'hxx_90_8F_xx;
#20;
inst_v = 1;
rden = 1;
inst = 32'hxx_92_91_xx;
#20;
inst_v = 0;
rden = 1;
inst = 32'hxx_xx_xx_xx;
#20;
rden = 0;
#1000;
end
endmodule
| 6.649235 |
module tb_mem_data;
// Parameters
localparam MEMORY_WIDTH = 8;
localparam MEMORY_DEPTH = 128;
localparam NB_ADDR = 7;
localparam NB_DATA = 32;
localparam RAM_PERFORMANCE = "LOW_LATENCY";
localparam INIT_FILE = "";
// Ports
reg i_clock = 0;
reg i_mem_write_flag = 0;
reg i_mem_read_flag = 0;
reg i_word_enable = 0;
reg i_halfword_enable = 0;
reg i_byte_enable = 0;
reg [NB_ADDR-1:0] i_read_addr;
reg [NB_DATA-1:0] i_write_data;
wire [NB_DATA-1:0] o_read_data;
mem_data #(
.MEMORY_WIDTH(MEMORY_WIDTH),
.MEMORY_DEPTH(MEMORY_DEPTH),
.NB_ADDR(NB_ADDR),
.NB_DATA(NB_DATA),
.RAM_PERFORMANCE(RAM_PERFORMANCE),
.INIT_FILE(INIT_FILE)
) mem_data_1 (
.i_clock(i_clock),
.i_mem_write_flag(i_mem_write_flag),
.i_mem_read_flag(i_mem_read_flag),
.i_word_enable(i_word_enable),
.i_halfword_enable(i_halfword_enable),
.i_byte_enable(i_byte_enable),
.i_read_addr(i_read_addr),
.i_write_data(i_write_data),
.o_read_data(o_read_data)
);
initial begin
begin
i_mem_write_flag = 1'b1;
i_mem_read_flag = 1'b0;
i_word_enable = 1'b1;
i_halfword_enable = 1'b0;
i_byte_enable = 1'b0;
i_read_addr = 7'd0;
i_write_data = 32'hffffffff;
#20 i_word_enable = 1'b0;
i_halfword_enable = 1'b0;
i_byte_enable = 1'b1;
i_read_addr = 7'd0;
i_write_data = 32'h0;
#20 i_word_enable = 1'b0;
i_halfword_enable = 1'b1;
i_byte_enable = 1'b0;
i_read_addr = 7'd10;
i_write_data = 32'hffffffff;
#20 i_mem_write_flag = 1'b0;
i_mem_read_flag = 1'b1;
i_word_enable = 1'b0;
i_halfword_enable = 1'b1;
i_byte_enable = 1'b0;
i_read_addr = 7'd0;
#20 i_word_enable = 1'b1;
i_halfword_enable = 1'b0;
i_byte_enable = 1'b0;
i_read_addr = 7'd0;
#20 i_word_enable = 1'b0;
i_halfword_enable = 1'b0;
i_byte_enable = 1'b1;
i_read_addr = 7'd10;
#20 i_word_enable = 1'b1;
i_halfword_enable = 1'b0;
i_byte_enable = 1'b0;
i_read_addr = 7'd10;
$finish;
end
end
always #5 i_clock = !i_clock;
endmodule
| 6.731737 |
module tb_data_multiplexer ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_multiplexer.vcd");
$dumpvars(0, tb_data_multiplexer);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 5;
parameter DATA_WIDTH = 8;
reg [ DATA_WIDTH-1:0] src_data;
reg src_valid;
wire src_ready;
wire [NUM*DATA_WIDTH-1:0] port_data;
wire port_valid;
wire port_ready;
wire [ DATA_WIDTH-1:0] sink_data;
wire sink_valid;
reg sink_ready = 1;
always @(posedge clk) begin
sink_ready <= {$random};
end
jelly_data_demultiplexer #(
.NUM (NUM),
.DATA_WIDTH(DATA_WIDTH)
) i_data_demultiplexer (
.reset(reset),
.clk (clk),
.cke (1),
.endian(0),
.s_data (src_data),
.s_valid(src_valid),
.s_ready(src_ready),
.m_data (port_data),
.m_valid(port_valid),
.m_ready(port_ready)
);
jelly_data_multiplexer #(
.NUM (NUM),
.DATA_WIDTH(DATA_WIDTH)
) i_data_multiplexer (
.reset(reset),
.clk (clk),
.cke (1),
.endian(0),
.s_data (port_data),
.s_valid(port_valid),
.s_ready(port_ready),
.m_data (sink_data),
.m_valid(sink_valid),
.m_ready(sink_ready)
);
always @(posedge clk) begin
if (reset) begin
src_data <= 0;
src_valid <= 0;
end else begin
if (src_valid && src_ready) begin
src_data <= src_data + 1;
end
if (!src_valid || src_ready) begin
src_valid <= {$random};
end
end
end
reg [DATA_WIDTH-1:0] exp_data;
always @(posedge clk) begin
if (reset) begin
exp_data <= 0;
end else begin
if (sink_valid && sink_ready) begin
if (sink_data != exp_data) begin
$display("Error!");
end
// $display("%h", sink_data);
exp_data <= exp_data + 1;
end
end
end
endmodule
| 7.584495 |
module tb_data_packing ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_packing.vcd");
$dumpvars(0, tb_data_packing);
#100000 $finish();
end
parameter BUSY = 0;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg cke = 1;
always @(posedge clk) cke <= BUSY ? {$random} : 1'b1;
parameter UNIT_WIDTH = 8;
parameter S_NUM = 4;
parameter M_NUM = 5;
parameter S_DATA_WIDTH = S_NUM * UNIT_WIDTH;
parameter M_DATA_WIDTH = M_NUM * UNIT_WIDTH;
parameter PADDING_DATA = 32'hxxxx_xxxx; // 32'h55aa5a5a;
parameter FIRST_FORCE_LAST = 1; // firstで前方吐き出し時に残変換があればlastを付与
parameter FIRST_OVERWRITE = 0; // first時前方に残変換があれば吐き出さずに上書き
reg endian = 0;
reg [ 31:0] count;
wire s_first = 0; //(count[0:0] == 1'b0);
wire s_last = 0; //(count[0:0] == 1'b1);
reg [S_DATA_WIDTH-1:0] s_data;
reg s_valid;
wire s_ready;
wire m_first;
wire m_last;
wire [M_DATA_WIDTH-1:0] m_data;
wire m_valid;
reg m_ready = 1;
integer i;
always @(posedge clk) begin
if (reset) begin
count <= 0;
for (i = 0; i < S_NUM; i = i + 1) begin
s_data[i*UNIT_WIDTH+:UNIT_WIDTH] <= endian ? S_NUM - 1 - i : i;
end
s_valid <= 0;
end else if (cke) begin
if (s_valid && s_ready) begin
for (i = 0; i < S_NUM; i = i + 1) begin
s_data[i*UNIT_WIDTH+:UNIT_WIDTH] <= s_data[i*UNIT_WIDTH+:UNIT_WIDTH] + S_NUM;
end
count <= count + 1;
end
if (!s_valid || s_ready) begin
s_valid <= BUSY ? {$random()} : 1'b1;
end
end
end
always @(posedge clk) begin
m_ready <= BUSY ? {$random()} : 1'b1;
end
jelly_data_packing #(
.UNIT_WIDTH (UNIT_WIDTH),
.S_NUM (S_NUM),
.M_NUM (M_NUM),
.S_DATA_WIDTH (S_DATA_WIDTH),
.M_DATA_WIDTH (M_DATA_WIDTH),
.FIRST_FORCE_LAST(FIRST_FORCE_LAST),
.FIRST_OVERWRITE (FIRST_OVERWRITE)
) i_data_unit_converter (
.reset(reset),
.clk (clk),
.cke (cke),
.endian (endian),
.padding_data(PADDING_DATA),
.s_first(s_first),
.s_last (s_last),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_first(m_first),
.m_last (m_last),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
integer fp;
initial begin
fp = $fopen("out.txt", "w");
end
always @(posedge clk) begin
if (reset) begin
end else if (cke) begin
if (m_valid && m_ready) begin
$fdisplay(fp, "%h %b %b", m_data, m_first, m_last);
end
end
end
endmodule
| 7.120757 |
module tb_data_rd_ctrl ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
wire rd_en; //数据读使能信号
wire [31:0] rd_addr; //读数据扇区地址
//reg define
reg sys_clk; //系统时钟
reg sys_rst_n; //复位信号
reg cnt_en; //计数器计数使能
reg [ 8:0] cnt; //计数器
reg rd_busy; //模拟读忙信号
//defparam
//重定义模块中的相关参数
defparam data_rd_ctrl_inst.RD_NUM = 20; //单张图片读取次数
defparam data_rd_ctrl_inst.WAIT_MAX = 3000; //图片切换时间间隔计数最大值
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//cnt_en:计数器计数使能
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_en <= 1'b0;
else if (cnt == 9'd511) cnt_en <= 1'b0;
else if (rd_en == 1'b1) cnt_en <= 1'b1;
else cnt_en <= cnt_en;
//cnt:计数器,约束读忙信号rd_busy
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt <= 9'd0;
else if (cnt_en == 1'b1) cnt <= cnt + 1'b1;
else cnt <= 9'd0;
//rd_busy:模拟读忙信号
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) rd_busy <= 1'b0;
else if (cnt <= 9'd60) rd_busy <= 1'b0;
else rd_busy <= 1'b1;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- data_rd_ctrl_inst -------------
data_rd_ctrl data_rd_ctrl_inst (
.sys_clk (sys_clk), //输入工作时钟,频率50MHz
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效
.rd_busy (rd_busy), //读操作忙信号
.rd_en (rd_en), //数据读使能信号
.rd_addr(rd_addr) //读数据扇区地址
);
endmodule
| 7.376374 |
module tb_data_serializer ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_serializer.vcd");
$dumpvars(0, tb_data_serializer);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter DATA_WIDTH = 4;
wire endian = 0;
reg [NUM*DATA_WIDTH-1:0] src_data;
reg src_valid;
wire src_ready;
wire [ DATA_WIDTH-1:0] port_data;
wire port_valid;
wire port_ready;
wire [NUM*DATA_WIDTH-1:0] sink_data;
wire sink_valid;
reg sink_ready = 1;
always @(posedge clk) begin
sink_ready <= {$random};
end
jelly_data_serializer #(
.NUM (NUM),
.DATA_WIDTH(DATA_WIDTH),
.S_REGS (0)
) i_data_serializer (
.reset(reset),
.clk (clk),
.cke (1),
.endian(endian),
.s_data (src_data),
.s_valid(src_valid),
.s_ready(src_ready),
.m_data (port_data),
.m_valid(port_valid),
.m_ready(port_ready)
);
jelly_data_deserializer #(
.NUM (NUM),
.DATA_WIDTH(DATA_WIDTH)
) i_data_deserializer (
.reset(reset),
.clk (clk),
.cke (1),
.endian(endian),
.s_data (port_data),
.s_valid(port_valid),
.s_ready(port_ready),
.m_data (sink_data),
.m_valid(sink_valid),
.m_ready(sink_ready)
);
always @(posedge clk) begin
if (reset) begin
src_data <= 0;
src_valid <= 0;
end else begin
if (src_valid && src_ready) begin
src_data <= src_data + 1;
end
if (!src_valid || src_ready) begin
src_valid <= {$random};
end
end
end
reg [NUM*DATA_WIDTH-1:0] exp_data;
always @(posedge clk) begin
if (reset) begin
exp_data <= 0;
end else begin
if (sink_valid && sink_ready) begin
if (sink_data != exp_data) begin
$display("Error!");
end
// $display("%h", sink_data);
exp_data <= exp_data + 1;
end
end
end
endmodule
| 7.052546 |
module tb_data_spliter ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_spliter.vcd");
$dumpvars(0, tb_data_spliter);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter DATA_WIDTH = 32;
parameter S_REGS = 1;
parameter M_REGS = 1;
reg cke = 1;
reg [NUM*DATA_WIDTH-1:0] s_data;
reg s_valid;
wire s_ready;
wire [NUM*DATA_WIDTH-1:0] m_data;
wire [ NUM-1:0] m_valid;
reg [ NUM-1:0] m_ready = {NUM{1'b1}};
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < NUM; i = i + 1) begin
s_data[i*DATA_WIDTH+:DATA_WIDTH] <= (i << (DATA_WIDTH / 2));
s_valid <= 1'b0;
end
end else begin
if (s_valid && s_ready) begin
for (i = 0; i < NUM; i = i + 1) begin
s_data[i*DATA_WIDTH+:DATA_WIDTH] <= s_data[i*DATA_WIDTH+:DATA_WIDTH] + 1;
end
end
if (!s_valid || s_ready) begin
s_valid <= {$random()};
end
end
end
always @(posedge clk) begin
for (i = 0; i < NUM; i = i + 1) begin
m_ready[i] <= {$random()};
end
end
integer fp[0:NUM-1];
initial begin
fp[0] = $fopen("out0.txt", "w");
fp[1] = $fopen("out1.txt", "w");
fp[2] = $fopen("out2.txt", "w");
fp[3] = $fopen("out3.txt", "w");
end
always @(posedge clk) begin
for (i = 0; i < NUM; i = i + 1) begin
if (m_valid[i] && m_ready[i]) begin
$fdisplay(fp[i], "%h", m_data[i*DATA_WIDTH+:DATA_WIDTH]);
end
end
end
jelly_data_spliter #(
.NUM (NUM),
.DATA_WIDTH(DATA_WIDTH),
.S_REGS (S_REGS),
.M_REGS (M_REGS)
) i_data_spliter (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
endmodule
| 7.093038 |
module tb_data_split_pack ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_split_pack.vcd");
$dumpvars(0, tb_data_split_pack);
#10000 $finish();
end
parameter RAND_BUSY = 1;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg cke = 1'b1;
always @(posedge clk) cke <= 1; // RAND_BUSY ? {$random} : 1'b1;
parameter NUM = 3;
parameter DATA0_WIDTH = 8;
parameter DATA1_WIDTH = 16;
parameter DATA2_WIDTH = 24;
parameter S_REGS = 0;
parameter M_REGS = 0;
reg [DATA0_WIDTH-1:0] s_data0;
reg [DATA1_WIDTH-1:0] s_data1;
reg [DATA2_WIDTH-1:0] s_data2;
reg s_valid;
wire s_ready;
wire [DATA0_WIDTH-1:0] m0_data;
wire m0_valid;
reg m0_ready;
wire [DATA1_WIDTH-1:0] m1_data;
wire m1_valid;
reg m1_ready;
wire [DATA2_WIDTH-1:0] m2_data;
wire m2_valid;
reg m2_ready;
integer i;
always @(posedge clk) begin
if (reset) begin
s_data0 <= 1;
s_data1 <= 2;
s_data2 <= 3;
s_valid <= 1'b0;
end else if (cke) begin
if (!s_valid || s_ready) begin
s_valid <= RAND_BUSY ? {$random()} : 1'b1;
end
if (s_valid && s_ready) begin
s_data0 <= s_data0 + 1;
s_data1 <= s_data1 + 1;
s_data2 <= s_data2 + 1;
end
end
m0_ready <= RAND_BUSY ? {$random()} : 1'b1;
m1_ready <= RAND_BUSY ? {$random()} : 1'b1;
m2_ready <= RAND_BUSY ? {$random()} : 1'b1;
end
integer fp0, fp1, fp2;
initial begin
fp0 = $fopen("out0.txt", "w");
fp1 = $fopen("out1.txt", "w");
fp2 = $fopen("out2.txt", "w");
end
always @(posedge clk) begin
if (cke) begin
if (m0_valid && m0_ready) $fdisplay(fp0, "%h", m0_data);
if (m1_valid && m1_ready) $fdisplay(fp1, "%h", m1_data);
if (m2_valid && m2_ready) $fdisplay(fp2, "%h", m2_data);
end
end
jelly_data_split_pack #(
.NUM (NUM),
.DATA0_WIDTH(DATA0_WIDTH),
.DATA1_WIDTH(DATA1_WIDTH),
.DATA2_WIDTH(DATA2_WIDTH),
.S_REGS (S_REGS),
.M_REGS (M_REGS)
) i_data_split_pack (
.reset(reset),
.clk (clk),
.cke (cke),
.s_data0(s_data0),
.s_data1(s_data1),
.s_data2(s_data2),
.s_valid(s_valid),
.s_ready(s_ready),
.m0_data (m0_data),
.m0_valid(m0_valid),
.m0_ready(m0_ready),
.m1_data (m1_data),
.m1_valid(m1_valid),
.m1_ready(m1_ready),
.m2_data (m2_data),
.m2_valid(m2_valid),
.m2_ready(m2_ready)
);
endmodule
| 7.093038 |
module tb_data_stream;
reg tx_symbol_clk;
reg tx_align_train;
reg tx_clock_train;
reg tx_link_established;
reg f;
wire [72:0] msa_merged_data;
wire test_signal_ready;
wire [ 2:0] stream_channel_count;
initial begin
tx_symbol_clk = 1'b0;
tx_align_train = 1'b0;
tx_clock_train = 1'b0;
tx_link_established = 1'b1;
end
always begin
#4 // Should be 135MHz, but 125 is close enough for simulation
tx_symbol_clk = ~tx_symbol_clk;
#4 // Should be 135MHz, but 125 is close enough for simulation
tx_symbol_clk = ~tx_symbol_clk;
$display("%b %b", msa_merged_data[8:0], msa_merged_data[26:18]);
$display("%b %b", msa_merged_data[17:9], msa_merged_data[35:27]);
end
///////////////////////////////////////////////////
// Video pipeline
/////////////////////////////////////////%/////////
test_source i_test_source (
.clk (tx_symbol_clk),
.stream_channel_count(stream_channel_count),
.ready (test_signal_ready),
.data (msa_merged_data)
);
wire [79:0] tx_symbols;
main_stream_processing i_main_stream_processing (
.symbol_clk (tx_symbol_clk),
.tx_link_established(tx_link_established),
.source_ready (test_signal_ready),
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
.in_data (msa_merged_data),
.tx_symbols (tx_symbols)
);
endmodule
| 6.691095 |
module prescaler (
w_gated_sclk_reg,
out,
o_slave_select_OBUF,
clk,
CLK
);
output w_gated_sclk_reg;
output [0:0] out;
input o_slave_select_OBUF;
input clk;
input CLK;
wire CLK;
wire clk;
wire o_slave_select_OBUF;
wire [0:0] out;
wire [4:0] plusOp;
wire \w_counter_reg_n_0_[0] ;
wire \w_counter_reg_n_0_[1] ;
wire \w_counter_reg_n_0_[2] ;
wire \w_counter_reg_n_0_[3] ;
wire w_gated_sclk_reg;
LUT1 #(
.INIT(2'h1)
) \w_counter[0]_i_1 (
.I0(\w_counter_reg_n_0_[0] ),
.O (plusOp[0])
);
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6)
) \w_counter[1]_i_1 (
.I0(\w_counter_reg_n_0_[0] ),
.I1(\w_counter_reg_n_0_[1] ),
.O (plusOp[1])
);
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78)
) \w_counter[2]_i_1 (
.I0(\w_counter_reg_n_0_[0] ),
.I1(\w_counter_reg_n_0_[1] ),
.I2(\w_counter_reg_n_0_[2] ),
.O (plusOp[2])
);
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80)
) \w_counter[3]_i_1 (
.I0(\w_counter_reg_n_0_[1] ),
.I1(\w_counter_reg_n_0_[0] ),
.I2(\w_counter_reg_n_0_[2] ),
.I3(\w_counter_reg_n_0_[3] ),
.O (plusOp[3])
);
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \w_counter[4]_i_1 (
.I0(\w_counter_reg_n_0_[2] ),
.I1(\w_counter_reg_n_0_[0] ),
.I2(\w_counter_reg_n_0_[1] ),
.I3(\w_counter_reg_n_0_[3] ),
.I4(out),
.O (plusOp[4])
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[0] (
.C (CLK),
.CE(1'b1),
.D (plusOp[0]),
.Q (\w_counter_reg_n_0_[0] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[1] (
.C (CLK),
.CE(1'b1),
.D (plusOp[1]),
.Q (\w_counter_reg_n_0_[1] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[2] (
.C (CLK),
.CE(1'b1),
.D (plusOp[2]),
.Q (\w_counter_reg_n_0_[2] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[3] (
.C (CLK),
.CE(1'b1),
.D (plusOp[3]),
.Q (\w_counter_reg_n_0_[3] ),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \w_counter_reg[4] (
.C (CLK),
.CE(1'b1),
.D (plusOp[4]),
.Q (out),
.R (1'b0)
);
LUT3 #(
.INIT(8'hE4)
) w_gated_sclk_i_1 (
.I0(o_slave_select_OBUF),
.I1(out),
.I2(clk),
.O (w_gated_sclk_reg)
);
endmodule
| 7.858126 |
module Tb_Data_writer ();
reg clk, Rx_tick;
reg [7:0] Din;
wire fin, Wen;
wire [15:0] addr;
wire [ 7:0] Dout;
Data_Writer DStore (
.clk(clk),
.Din(Din),
.Rx_tick(Rx_tick),
.fin(fin),
.Wen(Wen),
.Addr(addr),
.Dout(Dout)
);
initial begin
clk = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
#60;
Din <= 8'b01101000;
#10;
Rx_tick <= 1;
#20;
Rx_tick <= 0;
#60;
Rx_tick <= 1;
#20;
Rx_tick <= 0;
#60;
Rx_tick <= 1;
#20;
Rx_tick <= 0;
#60;
Rx_tick <= 1;
#20;
Rx_tick <= 0;
#60;
end
endmodule
| 6.839678 |
module tb_DBU ();
localparam WIDTH = 32;
localparam CWKTIME = 10;
reg clk, rst, succ, step;
reg [2:0] sel;
reg m_rf, inc, dec;
wire [15:0] led;
wire [ 7:0] an;
wire [ 7:0] seg;
DBU #(WIDTH) dbu (
.clk (clk),
.rst (rst),
.succ(succ),
.step(step),
.sel (sel),
.m_rf(m_rf),
.inc (inc),
.dec (dec),
.led (led),
.an (an),
.seg (seg)
);
initial begin
clk = 1;
// rst = 1;
// # (CWKTIME) rst = 0;
end
always #(CWKTIME / 2) clk = ~clk;
initial begin
rst = 1;
sel = 0;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 0;
inc = 1;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 0;
inc = 1;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 1;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 2;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 3;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 4;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 5;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 5;
m_rf = 0;
inc = 0;
dec = 0;
succ = 1;
step = 0;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 1;
inc = 0;
dec = 0;
succ = 0;
step = 1;
#(CWKTIME) rst = 0;
sel = 0;
m_rf = 1;
inc = 0;
dec = 0;
succ = 0;
step = 0;
#(CWKTIME) $finish;
end
endmodule
| 6.501632 |
module tb_DCPU16;
// Clock
reg clk;
// Active low reset
reg rst_n;
// RAM interface
wire [15:0] ram_addr;
wire [15:0] ram_dout;
// Instantiate DCPU-16
DCPU16 core0 (
.rst_n (rst_n),
.clk (clk),
.ram_addr (ram_addr),
.ram_dout (ram_dout)
);
// RAM
ram ram0 (
.ram_addr(ram_addr),
.ram_dout(ram_dout)
);
// Clock
initial begin
clk = 1'b0;
forever #50 clk <= ~clk;
end
// Reset
initial begin
rst_n = 1'b1;
#300;
rst_n = 1'b0;
#300;
rst_n = 1'b1;
end
// Terminate
initial begin
#10000;
$finish;
end
// Generate waveforms
initial begin
$dumpfile("tb_DCPU16.vcd");
$dumpvars(0, tb_DCPU16);
end
endmodule
| 7.170894 |
module tb_dct_main #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter COEFF_WIDTH = 9,
parameter FIRST_STAGE_WIDTH = 21,
// parameter SECOND_STAGE_WIDTH = 33,
parameter SECOND_STAGE_WIDTH = 25,
parameter QUANT_STAGE_WIDTH = 14,
parameter RUNL_STAGE_WIDTH = 16
) ();
// input signals
reg clk, data_vld, resetn;
reg [DATA_WIDTH-1 : 0] wdata0, wdata1;
// output signals
wire sync;
wire [RUNL_STAGE_WIDTH-1 : 0] rdata0, rdata1;
// test signals
reg [31:0] tstcase;
reg [ 7:0] num_iter;
reg test_failed, failed, test_start;
localparam NUM_IMG_PIXELS = 65536;
reg [7:0] test_data[0 : NUM_IMG_PIXELS-1];
initial begin
$readmemh("dct_test_block.mem", test_data, 0, NUM_IMG_PIXELS - 1);
end
dct_main #(DATA_WIDTH, COEFF_WIDTH, FIRST_STAGE_WIDTH, SECOND_STAGE_WIDTH, QUANT_STAGE_WIDTH, RUNL_STAGE_WIDTH)
DUT (
.wdata0(wdata0),
.wdata1(wdata1),
.i_clk(clk),
.wen(data_vld),
.i_resetn(resetn),
.rdata0(rdata0),
.rdata1(rdata1),
.rsync(sync)
);
initial begin
clk = 0;
data_vld = 0;
wdata0 = 0;
wdata1 = 0;
tstcase = 0;
failed = 0;
test_failed = 0;
test_start = 0;
num_iter = 0;
end
// generate
always clk = #5 ~clk;
// set resetn high
initial begin
resetn = 0;
repeat (5) @(negedge clk);
forever begin
@(negedge clk) test_start <= 1;
@(negedge clk) resetn <= 1'b1;
end
end
always @(negedge clk) begin
if (test_start && (tstcase <= NUM_IMG_PIXELS - 1)) begin
// we are still reading the image
data_vld <= 1;
end else begin
data_vld <= 0;
end
if (tstcase < NUM_IMG_PIXELS - 1) begin
wdata0 <= test_data[tstcase];
wdata1 <= test_data[tstcase+1];
end
if (sync) begin
$display("%0d\n%0d", rdata0, rdata1);
end
// handle printing errors
#1
if (failed) begin
// would have been the previous testc case
// $display("ERORR: test case %0d failed", tstcase-1);
failed <= 0;
test_failed <= 1;
end
// increment the test case number
if (test_start && resetn) begin
#1 tstcase <= (tstcase + 2);
end
end
endmodule
| 7.687836 |
module tb_dct_stage #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter OUTPUT_WIDTH = 12, // output coefficient width
parameter COEFF_WIDTH = 12 // coefficient bit width
) ();
// input signals
reg clk, data_vld, resetn;
reg [DATA_WIDTH-1 : 0] p0, p1;
// output signals
wire sync;
wire [OUTPUT_WIDTH-1 : 0] c0, c1;
// test signals
reg [7:0] tstcase;
reg test_failed, failed;
dct_stage #(DATA_WIDTH, OUTPUT_WIDTH, COEFF_WIDTH) DUT (
.i_p0(p0),
.i_p1(p1),
.i_clk(clk),
.i_vld(data_vld),
.i_resetn(resetn),
.o_c0(c0),
.o_c1(c1),
.o_sync(sync)
);
initial begin
clk = 0;
data_vld = 0;
resetn = 0;
p0 = 0;
p1 = 0;
tstcase = 0;
failed = 0;
test_failed = 0;
end
// generate
always clk = #5 ~clk;
always @(negedge clk) begin
case (tstcase)
0: begin
resetn <= 0;
end
1: begin
resetn <= 1;
data_vld <= 1;
p0 <= 1;
p1 <= 2;
end
2: begin
p0 <= 3;
p1 <= 4;
end
3: begin
p0 <= 5;
p1 <= 6;
end
4: begin
p0 <= 7;
p1 <= 8;
end
default: begin
$display("waiting ...");
end
endcase
// handle printing errors
#1
if (failed) begin
// would have been the previous testc case
$display("ERORR: test case %0d failed", tstcase - 1);
failed <= 0;
test_failed <= 1;
end
// increment the test case number
#1 tstcase = tstcase + 1;
end
endmodule
| 6.85393 |
module tb_dds ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
//wire define
wire [7:0] data_out;
//reg define
reg sys_clk;
reg sys_rst_n;
reg [3:0] wave_select;
//**************************************************************//
//************************** Main Code *************************//
//**************************************************************//
//sys_rst_n,sys_clk,key
initial begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;
wave_select <= 4'b0000;
#200;
sys_rst_n <= 1'b1;
#10000 wave_select <= 4'b0001;
#8000000;
wave_select <= 4'b0010;
#8000000;
wave_select <= 4'b0100;
#8000000;
wave_select <= 4'b1000;
#8000000;
wave_select <= 4'b0000;
#8000000;
end
always #10 sys_clk = ~sys_clk;
//**************************************************************//
//************************ Instantiation ***********************//
//**************************************************************//
//------------- top_dds_inst -------------
dds dds_inst (
.sys_clk (sys_clk), //系统时钟,50MHz
.sys_rst_n (sys_rst_n), //复位信号,低电平有效
.wave_select(wave_select), //输出波形选择
.data_out(data_out) //波形输出
);
endmodule
| 7.593829 |
module tb_dds_top;
parameter DATA_WIDTH = 12;
parameter ADDR_WIDTH = 12;
reg clk;
reg rst_n;
reg [ 11:0] phase_data;
reg [ 31:0] freq_data;
wire [DATA_WIDTH-1:0] dout;
initial begin
$dumpfile("tb_dds_top.dump");
//$dumpfile("addertb.vcd");
$dumpvars(0, tb_dds_top);
end
dds_top #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) u_dds_top ( /*autoinst*/
// Outputs
.dout (dout[DATA_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst_n (rst_n),
.freq_data (freq_data[31:0]),
.phase_data(phase_data[11:0])
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
phase_data = 0;
freq_data = 32'h1;
#100 rst_n = 1;
#100000000 $finish;
end
endmodule
| 7.091297 |
module TB_debouncer ();
reg clk, reset;
wire [(`SWITCHES-1):0] swout;
reg [(`SWITCHES-1):0] swin;
debouncer #(
.DELAY(`DEBOUNCE_TIMEOUT)
) debouncer[`SWITCHES - 1 : 0] (
.clk(clk),
.rst(reset),
.in_switch(swin),
.out_switch(swout)
);
reg runt_check;
initial begin
$dumpvars;
`ifdef DEBUG
$display("starting sim");
`endif
clk <= 1'b0;
reset <= 1'b1;
runt_check <= 1'b0;
swin <= `SWITCHES'b0;
#9 reset <= 1'b0;
#10 swin <= ~swout;
#2
if (swout != `SWITCHES'b0) begin
$display("FAILED: reacted too soon");
$finish;
end
swin <= swout;
#10 swin <= ~swin;
#7
if (swout != ~(`SWITCHES'b0)) begin
$display("FAILED: did not react");
$finish;
end
swin <= `SWITCHES'b0;
#22
if (swout != (`SWITCHES'b0)) begin
$display("FAILED: did not react");
$finish;
end
runt_check <= 1'b1;
#1 swin <= `SWITCHES'b1;
#3 swin <= `SWITCHES'b0;
#1 $display("PASSED");
$finish;
end
always begin
#1 clk <= ~clk;
end
always @(*) begin
if (runt_check) begin
if (swout != `SWITCHES'b0) begin
$display("FAILED: got a runt pulse");
$finish;
end
end
end
endmodule
| 7.444772 |
module testbench;
reg [2:0] S;
reg reset;
wire [7:0] Q;
Dec Dec_1 (
S,
reset,
Q
);
initial begin
reset = 1'b1;
#10 reset = 1'b0;
#10 S = 3'b110; //6
#10 S = 3'b000; //0
#10 S = 3'b010; //2
#10 S = 3'b111; //7
#10 S = 3'b001; //1
#10 S = 3'b100; //4
#10 S = 3'b110; //6
#10 S = 3'b101; //5
#10 S = 3'b011; //3
#10 S = 3'b010; //2
#10 S = 3'b100; //4
#10 S = 3'b000; //0
end
endmodule
| 7.015571 |
module tb_decimal_splitter;
reg [6:0] dec;
wire [3:0] tens, units;
decimal_splitter tb_decimal_splitter__decimal_splitter (
.dec(dec),
.tens(tens),
.units(units)
);
initial begin
dec = 25;
#100 dec = 56;
#100 dec = 83;
end
endmodule
| 7.848117 |
module tb_decoder;
reg tb_data_clk = 0;
reg tb_rst = 0;
reg [175:0] tb_m_axis_tdata = 0;
reg tb_m_axis_tvalid = 0;
wire tb_m_axis_tready;
wire [ 15:0] tb_s_axis_tdata;
wire [ 7:0] tb_s_axis_tuser;
wire tb_s_axis_tvalid;
reg tb_s_axis_tready;
reg tb_vslave_off;
reg tb_vslave_toggle = 0;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1600;
//1553 to string core
util_axis_1553_string_decoder dut (
//axi streaming clock and reset.
.aclk(tb_data_clk),
.arstn(~tb_rst),
//axis slave interface (input)
.s_axis_tdata(tb_m_axis_tdata),
.s_axis_tvalid(tb_m_axis_tvalid),
.s_axis_tready(tb_m_axis_tready),
//axis master interface (out)
.m_axis_tdata(tb_s_axis_tdata),
.m_axis_tvalid(tb_s_axis_tvalid),
.m_axis_tuser(tb_s_axis_tuser),
.m_axis_tready(tb_s_axis_tready)
);
//reset
initial begin
tb_rst <= 1'b1;
tb_vslave_off <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
#30000;
tb_vslave_off <= 1'b0;
#30500;
tb_vslave_off <= 1'b1;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_decoder.vcd");
$dumpvars(0, tb_decoder);
end
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 2);
end
//valid off/on
always begin
tb_vslave_toggle <= ~tb_vslave_toggle;
#(CLK_PERIOD / 2);
end
//product data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_m_axis_tdata <= {"DATA;D1;P1;I0;HxA5F0", 16'h0A0D};
tb_m_axis_tvalid <= 0;
tb_s_axis_tready <= 0;
end else begin
tb_s_axis_tready <= $random % 2;
tb_m_axis_tvalid <= tb_vslave_off & tb_vslave_toggle;
;
tb_m_axis_tdata <= tb_m_axis_tdata;
if (tb_m_axis_tready == 1'b1) begin
tb_m_axis_tdata <= tb_m_axis_tdata + 20'h10000;
end
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 8.277876 |
module tb_decoder2x4 ();
reg [1:0] in;
reg en;
wire [3:0] dout;
decoder2x4 test_decoder2x4 (
.in (in),
.en (en),
.dout(dout)
);
initial begin
en <= 1'b0;
in <= 2'b00;
#10;
in <= 2'b01;
#10;
in <= 2'b10;
#10;
in <= 2'b11;
#20;
en <= 1'b1;
in <= 2'b00;
#10;
in <= 2'b01;
#10;
in <= 2'b10;
#10;
in <= 2'b11;
#20;
$finish;
end
endmodule
| 6.727177 |
module tb_Decoder3by8;
reg [2:0] tb_usr_input;
reg tb_ENABLE;
wire [7:0] tb_Dout;
reg [2:0] count = 3'd0;
//instantiate module
Decoder3by8 uut (
.usr_input(tb_usr_input),
.Dout(tb_Dout),
.ENABLE(tb_ENABLE)
);
initial begin
$display($time, " << starting simulation >> ");
tb_usr_input = 3'd0;
tb_ENABLE = 1'b1;
#10;
for (count = 0; count < 8; count = 1'b1) begin
$display("\ninput is : %b", tb_usr_input);
tb_usr_input = tb_usr_input + 1'b1;
#20;
end
tb_ENABLE = 1'b0;
end
endmodule
| 7.055777 |
module tb_decoder3to8_gate;
reg [2:0] in;
wire [7:0] out;
decoder3to8_gate dec (
out,
in[2],
in[1],
in[0]
);
initial $monitor($time, " in=%3b, out=%8b", in, out);
initial begin
#0 in = 3'b000;
repeat (7) #10 in = in + 3'b001;
end
endmodule
| 7.257758 |
module tb_decoder3_8 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [7:0] out;
//reg define
reg in1;
reg in2;
reg in3;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化输入信号
initial begin
in1 <= 1'b0;
in2 <= 1'b0;
in3 <= 1'b0;
end
//in1:产生输入随机数，模拟输入端1的输入情况
always #10 in1 <= {$random} % 2;
//in2:产生输入随机数，模拟输入端2的输入情况
always #10 in2 <= {$random} % 2;
//in3:产生输入随机数，模拟输入端3的输入情况
always #10 in3 <= {$random} % 2;
initial begin
$timeformat(-9, 0, "ns", 6);
$monitor("@time %t: in1=%b in2=%b in3=%b out=%b", $time, in1, in2, in3, out);
end
//********************************************************************//
//**************************** Instantiate ***************************//
//********************************************************************//
//------------- decoder3_8_inst -------------
decoder3_8 decoder3_8_inst (
.in1(in1), //input in1
.in2(in2), //input in2
.in3(in3), //input in3
.out(out) //output [7:0] out
);
endmodule
| 7.798816 |
module: Decoder4to16_less
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Decoder4to16_less;
// Inputs
reg [3:0] in;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
Decoder4to16_less uut (
.in(in),
.out(out)
);
initial begin
// Initialize Inputs
in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in = 4'b0001;
#100
in = 4'b0010;
#100
in = 4'b0011;
#100
in = 4'b0100;
#100
in = 4'b0101;
#100
in = 4'b0110;
#100
in = 4'b0111;
#100
in = 4'b1000;
#100
in = 4'b1001;
#100
in = 4'b1010;
#100
in = 4'b1011;
#100
in = 4'b1100;
#100
in = 4'b1101;
#100
in = 4'b1110;
#100
in = 4'b1111;
end
endmodule
| 7.145307 |
module tb_decoder4x16;
wire [15:0] dout;
reg [3:0] in;
reg en;
decoder4x16 test_decoder4x16 (
.dout(dout),
.in (in),
.en (en)
);
initial begin
en <= 1'b0;
in <= 4'b0000;
#10;
in <= 4'b0001;
#10;
in <= 4'b0010;
#10;
in <= 4'b0011;
#20;
en <= 1'b1;
in <= 4'b0000;
#10;
in <= 4'b0001;
#10;
in <= 4'b0010;
#10;
in <= 4'b0011;
#20;
$finish;
end
endmodule
| 6.821244 |
module tb_decoder_assgn ();
wire [15:0] decoder_out;
reg enable;
reg [3:0] binary_in;
decoder_assign uut (
decoder_out,
enable,
binary_in
);
initial begin
binary_in = 4'b0;
enable = 1'b0;
#10;
binary_in = 4'b1;
enable = 1'b1;
#10;
binary_in = 4'b0001;
enable = 1'b0;
#10;
binary_in = 4'b0011;
enable = 1'b1;
#10;
binary_in = 4'b0000;
enable = 1'b1;
#10;
binary_in = 4'b0101;
enable = 1'b0;
#10;
binary_in = 4'b0110;
enable = 1'b1;
#10;
binary_in = 4'b0111;
enable = 1'b1;
#10;
binary_in = 4'b1001;
enable = 1'b0;
#10;
binary_in = 4'b1100;
enable = 1'b1;
#10;
binary_in = 4'b1111;
enable = 1'b1;
#10;
end
endmodule
| 6.873406 |
module decoder_Nx2pN_top;
reg [2:0] IN;
wire [(2**3)-1:0] OUT;
integer i = 0;
decoder_Nx2pN #(
.N(3)
) decoder (
IN,
OUT
);
initial begin
for (i = 0; i <= 2 ** 3; i = i + 1) begin
$display("IN = %0d, OUT = %b", IN, OUT);
IN = i;
#1;
end
end
endmodule
| 7.875318 |
module tb_decode;
parameter PERIOD = 2;
parameter IMUL = 0;
parameter BARREL_SHIFTER = 1;
reg [31:0] instd = 32'h4200_1000;
reg clk = 0;
reg reset = 1;
wire reqe, rdye;
wire [ 3:0] aluop;
wire [ 4:0] shift;
wire [15:0] imm;
wire [ 3:0] rd;
wire [ 3:0] rm;
wire [ 3:0] rn;
wire [15:0] ctlsig;
wire [ 1:0] bank;
wire [31:0] addr, dtw;
reg [31:0] dtr = 32'hCAFEBABE;
wire rw, valid;
reg ready = 1;
always #(PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_exec_decode.vcd");
$dumpvars(0, decode, exec);
// Initialize some registers
exec.regfile_s.regs[0] = 32'h6;
exec.regfile_s.regs[1] = 32'h2;
// Power on reset, no touchy >:[
#PERIOD reset <= 0;
exec.pc_s = 32'h0000_1000;
#(PERIOD * 20);
$finish;
end
hs32_exec #(
.IMUL(IMUL),
.BARREL_SHIFTER(BARREL_SHIFTER)
) exec (
.clk (clk),
.reset(reset),
.req (reqe),
.rdy (rdye),
.flush(),
.newpc(),
.aluop(aluop),
.shift(shift),
.imm(imm),
.rd(rd),
.rm(rm),
.rn(rn),
.ctlsig(ctlsig),
.bank(bank),
.addr (addr),
.dtrm (32'hCAFE),
.dtwm (dtw),
.reqm (valid),
.rdym (ready),
.rw_mem(rw),
.intrq(1'b0),
.isr (0)
);
hs32_decode #(
.IMUL(IMUL)
) decode (
.clk(clk),
.reset(reset),
.instd(instd),
.reqd(),
.rdyd(1'b1),
.aluop(aluop),
.shift(shift),
.imm(imm),
.rd(rd),
.rm(rm),
.rn(rn),
.bank(bank),
.ctlsig(ctlsig),
.reqe(reqe),
.rdye(rdye)
);
/*soc_bram_ctl #(
.addr_width(8)
) bram_ctl(
.clk(clk),
.addr(addr[7:0]), .rw(rw),
.dread(dtr), .dwrite(dtw),
.valid(valid), .ready(ready)
);*/
endmodule
| 6.942186 |
module tb_decode_execute ();
localparam STEP = 10;
reg [31 : 0] ir;
reg [31 : 0] pc;
reg [31 : 0] rs1_data;
reg [31 : 0] rs2_data;
wire [4 : 0] rs1_num;
wire [4 : 0] rs2_num;
wire wb_reg;
wire [4 : 0] rd_num;
wire [31 : 0] rd_data;
wire [6 : 0] opcode;
wire [2 : 0] func3;
wire [31 : 0] imm;
wire br_taken;
wire [`SEL_PC_WIDTH - 1 : 0] pc_sel;
decode_execute decode_execute (
.ir(ir),
.pc(pc),
.rs1_data(rs1_data),
.rs2_data(rs2_data),
.rs1_num(rs1_num),
.rs2_num(rs2_num),
.opcode(opcode),
.func3(func3),
.wb_reg(wb_reg),
.rd_num(rd_num),
.rd_data(rd_data),
.imm(imm),
.pc_sel(pc_sel),
.br_taken(br_taken)
);
initial begin
pc = 32'h100;
rs1_data = 32'b1000;
rs2_data = 32'b0011;
#(STEP * 10)
// ADD r3, r1, r2
ir = 32'b0000000_00010_00001_000_00011_0110011;
#(STEP)
$display(
"[ADD]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// XORI r2, r1, imm
ir = 32'b000000111111_00001_100_00010_0010011;
#(STEP)
$display(
"[XORI]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// LW r2, imm(r1)
ir = 32'b000000101010_00001_010_00010_0000011;
#(STEP)
$display(
"[LW]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// BNE r1, r2, pc + imm
ir = 32'b0_000000_00010_00001_001_1010_0_1100011;
#(STEP)
$display(
"[BNE]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// LUI r1, imm
ir = 32'b10101010101010101010_00001_0110111;
#(STEP)
$display(
"[LUI]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// AUIPC r1, imm
ir = 32'b10101010101010101010_00001_0010111;
#(STEP)
$display(
"[AUIPC]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// JAL r2, imm
ir = 32'b0_1010101010_0_00000000_00010_1101111;
#(STEP)
$display(
"[JAL]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
// JALR rd, rs1, imm
ir = 32'b101010101010_00001_000_00010_1100111;
#(STEP)
$display(
"[JALR]rs1:%h, rs2:%h, wb:%b, rd_num:%h, rd_data:%b",
rs1_num,
rs2_num,
wb_reg,
rd_num,
rd_data
);
#(STEP * 100) $stop;
end
endmodule
| 6.544139 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
// Clock Interface
reg clk;
reg reset;
// Control Interface
reg flush;
reg handle_int;
wire halt;
// Return Address Stack Interface
wire [IADDRW-1:0] ras_address;
wire ras_push;
// Fetch Interface
reg f_valid;
wire f_ready;
wire [ 5:0] f_bytes_read;
reg [ 5:0] f_valid_bytes;
reg [ 255:0] f_instruction;
reg [IADDRW-1:0] f_pc;
reg f_branch_taken;
// Pipestage Interface
wire d_valid;
reg d_ready;
wire d_mmr;
wire [ 2:0] d_rega;
wire [ 2:0] d_regb;
wire [ 31:0] d_imm;
wire [ 31:0] d_disp;
wire [ 5:0] d_seg_ov; // One Hot {CS, SS, DS, ES, FS, GS}
wire [ 7:0] d_sib;
wire [ 3:0] d_op;
wire d_opsize;
wire [ 5:0] d_alu;
wire d_repeat;
wire [ 3:0] d_size_of_txn;
wire d_branch_taken;
//reg [2047:0] MEMORY[127:0];
decode_top uut (
clk,
reset,
flush,
handle_int,
halt,
ras_address,
ras_push,
f_valid,
f_ready,
f_bytes_read,
f_valid_bytes,
f_instruction,
f_pc,
f_branch_taken,
d_valid,
d_ready,
d_mmr,
d_rega,
d_regb,
d_imm,
d_disp,
d_seg_ov,
d_sib,
d_op,
d_opsize,
d_alu,
d_repeat,
d_size_of_txn,
d_branch_taken
);
initial begin
$strobe("============ \n Begin Test \n============");
reset = 1;
clk = 0;
flush = 'h0;
handle_int = 'h0;
f_valid = 'h0;
f_valid_bytes = 'h0;
f_instruction = 'h0;
f_pc = 'h0;
f_branch_taken = 'h0;
d_ready = 'h0;
#25 reset = 0;
#10 $display("==========\n End Test \n==========");
end
initial #2000 $finish;
always #10 clk = ~clk;
initial begin
$vcdplusfile("fetch_seq.dump.vpd");
$vcdpluson(0, TOP);
end
endmodule
| 6.594167 |
module TB_DECONCAT;
localparam ENDCOUNT = 10000;
localparam NUM_PATTERNS = 8;
localparam LEN_ENCODE = $clog2(NUM_PATTERNS);
reg [255+LEN_ENCODE:0] data_i;
reg clk, rst_n, en_i;
wire [255:0] scanned_o;
wire en_o;
DECONCAT #(
.NUM_PATTERNS(NUM_PATTERNS)
) DUT (
.data_i(data_i[255:0]),
.clk (clk),
.rst_n (rst_n),
.en_i (en_i),
.scanned_o(scanned_o),
.en_o (en_o)
);
// clock gen
initial begin
clk = 1'b0;
forever #10 clk = !clk;
end
// reset and en_i gen
initial begin
rst_n = 1'b0;
en_i = 1'b0;
repeat (2) @(posedge clk);
rst_n = 1'b1;
en_i = 1'b1;
end
// input vector gen
reg [255 + LEN_ENCODE:0] data;
reg [255 + LEN_ENCODE:0] data_list [0:ENDCOUNT-1];
integer list_idx;
integer file_data_i;
integer file_stat_i;
initial begin
list_idx = 0;
data = 'd0;
file_data_i = $fopen("../tb/stimulus/stimulus_deconcat/data_i.txt", "r");
if (file_data_i) begin
while (!$feof(
file_data_i
)) begin
repeat (ENDCOUNT)
@(posedge clk) begin
if (rst_n) begin
$fscanf(file_data_i, "%b\n", data);
data_i <= data;
data_list[list_idx] <= data;
list_idx = list_idx + 1;
end
end
end
$fclose(file_data_i);
end else begin
$display("ERROR: Input file is not opened");
$finish;
end
end
// output vector gen [scanned]
integer file_scanned_o;
reg [255:0] scanned_o_stimulus;
initial begin
scanned_o_stimulus = 'd0;
file_scanned_o = $fopen("../tb/stimulus/stimulus_deconcat/scanned_o.txt", "r");
if (file_scanned_o) begin
while (!$feof(
file_scanned_o
)) begin
repeat (ENDCOUNT)
@(posedge clk) begin
if (rst_n && en_o) begin
$fscanf(file_scanned_o, "%b\n", scanned_o_stimulus);
end
end
end
$fclose(file_scanned_o);
end else begin
$display("ERROR: Output file is not opened");
$finish;
end
end
// self-check
integer total, cnt;
initial begin
total = 0;
cnt = 0;
repeat (ENDCOUNT)
@(posedge clk) begin
if (en_o) begin
#(1);
if (scanned_o != scanned_o_stimulus) begin
cnt = cnt + 1;
$display("Failed at %05d => data_i : %0d, %0x", total,
data_list[total][255+LEN_ENCODE:256], data_list[total][255:0]);
$display(" scanned_o : %0x | ref : %0x\n", scanned_o,
scanned_o_stimulus);
end
end
total = total + 1;
end
$display("Total error: %d / %d", cnt, total);
$finish;
end
endmodule
| 6.746632 |
module tb_dec_counter;
reg clk, reset;
wire [3:0] count;
dec_counter counter (
count,
clk,
reset
);
initial begin
#0 clk = 0;
#0 reset = 0;
#75 reset = 1;
#5 reset = 0;
#1000 $stop;
end
always begin
#5 clk = ~clk;
end
endmodule
| 7.290193 |
module tb_DEC_INPUT_KEY;
reg input_key;
reg valid_cmd;
reg reset;
reg clk;
wire active;
wire mode;
DEC_INPUT_KEY DUT (
input_key,
valid_cmd,
reset,
clk,
active,
mode
);
initial begin
$dumpvars(0, tb_DEC_INPUT_KEY);
$dumpfile("my.vcd");
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 1;
valid_cmd = 0;
input_key = 0;
#4 display;
reset = 0;
valid_cmd = 1;
input_key = 1;
#12 display;
valid_cmd = 1;
input_key = 0;
#12 display;
valid_cmd = 1;
input_key = 1;
#12 display;
valid_cmd = 1;
input_key = 0;
#12 display;
valid_cmd = 1;
input_key = 1;
#12 display;
valid_cmd = 1;
input_key = 0;
#12 display;
#300 $finish;
end
task display;
$display("reset = %0h, clk = %0h, valid = %0h, in = %0h, active = %0h, mode = %0h", reset, clk,
valid_cmd, input_key, active, mode);
endtask
endmodule
| 7.268056 |
module stimulate #(
parameter N = 1
) (
output clk,
output [N-1:0] out
);
reg clks = 1'b0;
reg [N-1:0] outs = 0;
initial begin
while (1) begin
#1;
clks <= 1'b0;
#1;
clks <= 1'b1;
end
end
always @(posedge clk) begin
outs <= outs + 1;
end
assign clk = clks;
assign out = outs;
endmodule
| 7.159411 |
module tb_delay ();
localparam N = 3;
localparam DELAY = 4;
wire clk;
wire [N-1:0] in;
wire [N-1:0] out;
stimulate #(
.N(N)
) stim_i (
.clk(clk),
.out(in)
);
delay_line #(
.N(N),
.DELAY(DELAY)
) dut (
.clk (clk),
.idata(in),
.odata(out)
);
endmodule
| 6.930738 |
module tb_delay_fifo ();
parameter DELAY_CYCLES = 1;
parameter BITWIDTH = 32;
parameter ADDRWIDTH = 4;
parameter MEMHEIGHT = 2 ** ADDRWIDTH;
parameter INVALIDHEIGHT = MEMHEIGHT / 4;
parameter VALIDHEIGHT = MEMHEIGHT - INVALIDHEIGHT;
localparam input_file_path = {`path, "tb/data/delay_fifo_input.bin"};
reg aclk;
reg en;
reg [ BITWIDTH - 1 : 0] din;
wire [ BITWIDTH - 1 : 0] dout;
reg valid;
reg valid_d;
wire dvalid;
reg [ BITWIDTH - 1 : 0] mem [MEMHEIGHT - 1 : 0];
reg [MEMHEIGHT - 1 : 0] addr;
reg start;
reg stop;
initial begin
aclk <= 1'b1;
en <= 1'b0;
addr <= 'd0;
$readmemh(input_file_path, mem);
end
integer i;
initial begin
#(`period);
start = 1'b1;
#(2 * `period);
#(DELAY_CYCLES * `period);
for (i = 0; i < VALIDHEIGHT; i = i + 1) begin
if (dout == mem[i] && dvalid) $display("[ TEST CASE #%d ] PASS", i);
else if (dvalid) $display("[ TEST CASE #%d ] FAIL : %x expected(%x)", i, dout, mem[i]);
else $display("[ TEST CASE #%d ] FAIL : INVALID expected(VALID)", i);
#(`period);
end
for (i = 0; i < INVALIDHEIGHT; i = i + 1) begin
if (dvalid) $display("[ TEST CASE #%d ] FAIL : VALID expected(INVALID)", i + VALIDHEIGHT);
else $display("[ TEST CASE #%d ] PASS", i + VALIDHEIGHT);
end
#(5 * `period);
$finish;
end
always #(`period / 2) aclk <= ~aclk;
always @(posedge aclk)
if (start) begin
en <= 1'b1;
valid_d <= 1'b1;
end
always @(posedge aclk)
if (valid_d) valid <= 1'b1;
else valid <= 1'b0;
always @(posedge aclk)
if (stop) begin
valid_d <= 1'b0;
valid <= 1'b0;
end
always @(posedge aclk) if (en) start <= 1'b0;
always @(posedge aclk) if (!en) stop <= 1'b0;
always @(posedge aclk) if (en && addr == VALIDHEIGHT - 1) stop <= 1'b1;
always @(posedge aclk) if (en) addr <= addr + 1;
always @(posedge aclk) if (en) din <= mem[addr];
delay_fifo #(
.DELAY_CYCLES(DELAY_CYCLES),
.BITWIDTH (BITWIDTH)
) u_delay_fifo (
.aclk (aclk),
.en (en),
.din (din),
.valid (valid),
.dout (dout),
.dvalid(dvalid)
);
endmodule
| 7.192433 |
module: delay_line
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delay_line #(
parameter WIDTH = 8,
parameter DELAY = 4
);
wire clk;
wire [WIDTH - 1:0] data_in;
wire [WIDTH - 1:0] data_out;
delay_line_gen_test #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
generator (
.out(data_in),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
delay_line #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
uut (
.ce(1'b1),
.rst(1'b0),
.clk(clk),
.in(data_in),
.out(data_out)
);
delay_line_check_test #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
checker (
.in(data_out)
);
endmodule
| 7.993436 |
module: delta_picker
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delta_picker;
// Inputs
reg clk;
reg rst;
reg [1:0] layer;
reg layer_valid;
reg [31:0] fetcher;
reg fetcher_valid;
reg [31:0] propagator;
reg propagator_valid;
reg result_ready;
// Outputs
wire layer_ready;
wire fetcher_ready;
wire propagator_ready;
wire [31:0] result;
wire result_valid;
// Instantiate the Unit Under Test (UUT)
delta_picker #(
.LAYER_MAX(3)
)uut (
.clk(clk),
.rst(rst),
.layer(layer),
.layer_valid(layer_valid),
.layer_ready(layer_ready),
.fetcher(fetcher),
.fetcher_valid(fetcher_valid),
.fetcher_ready(fetcher_ready),
.propagator(propagator),
.propagator_valid(propagator_valid),
.propagator_ready(propagator_ready),
.result(result),
.result_valid(result_valid),
.result_ready(result_ready)
);
always
#1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
layer = 3;
layer_valid = 0;
fetcher = 100;
fetcher_valid = 0;
propagator = 200;
propagator_valid = 0;
result_ready = 0;
#10 rst = 0;
#10 fetcher_valid = 1;
#2 fetcher_valid = 0;
#10 propagator_valid = 1;
#2 propagator_valid = 0;
#10 layer_valid = 1;
#2 layer_valid = 0;
#10 result_ready = 1;
#2 result_ready = 0;
// layer goes to 2
#30 layer_valid = 1;
layer = 2;
#2 layer_valid = 0;
#10 result_ready = 1;
#2 result_ready = 0;
end
endmodule
| 6.63449 |
module tb_delta_sigma_adc;
// delta_sigma_adc Parameters
parameter PERIOD = 10;
parameter W = 16;
parameter N = 1024; //量化位数
// delta_sigma_adc Inputs
reg clk = 0;
reg rst_n = 0;
reg signed [W-1:0] din = -32768;
// delta_sigma_adc Outputs
wire dout;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
reg [31:0] cnt = 0;
always @(posedge clk) begin
if (cnt == N - 1) cnt <= 'd0;
else cnt <= cnt + 1;
if (cnt == N - 1) din <= din + 1000;
end
delta_sigma_adc #(
.W(W)
) u_delta_sigma_adc (
.clk (clk),
.rst_n(rst_n),
.din (din[W-1:0]),
.dout(dout)
);
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, tb_delta_sigma_adc);
#(PERIOD * 2) rst_n = 1;
#(PERIOD * N * 80) //65536
$finish;
end
endmodule
| 6.606775 |
module tb_demo #(
// parameters declared here.
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h80000000,
// AXI Stream parameters
// Slave
parameter C_S_AXIS_DATA_WIDTH = 512,
parameter C_S_AXIS_TUSER_WIDTH = 128,
// Master
parameter C_M_AXIS_DATA_WIDTH = 256,
// self-defined
parameter PHV_ADDR_WIDTH = 4
) ();
//stimulates (regs) and oputputs(wires) declared here
reg clk;
reg aresetn;
reg [ C_S_AXIS_DATA_WIDTH-1:0] s_axis_tdata;
reg [((C_S_AXIS_DATA_WIDTH/8))-1:0] s_axis_tkeep;
reg [ C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser;
reg s_axis_tvalid;
wire s_axis_tready;
reg s_axis_tlast;
wire [ C_S_AXIS_DATA_WIDTH-1:0] m_axis_tdata;
wire [((C_S_AXIS_DATA_WIDTH/8))-1:0] m_axis_tkeep;
wire [ C_S_AXIS_TUSER_WIDTH-1:0] m_axis_tuser;
wire m_axis_tvalid;
reg m_axis_tready;
wire m_axis_tlast;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
aresetn = 1;
#(10);
aresetn = 0; //reset all the values
#(10);
aresetn = 1;
end
initial begin
#(2 * CYCLE + CYCLE / 2)
/*
here you give values to stimulates per CYCLE
*/
//.....
#(CYCLE)
s_axis_tdata <= 512'b0;
s_axis_tkeep <= 64'h0;
s_axis_tuser <= 128'h0;
s_axis_tvalid <= 1'b0;
s_axis_tlast <= 1'b0;
#(10 * CYCLE);
end
demo #(
.C_S_AXI_DATA_WIDTH(),
.C_S_AXI_ADDR_WIDTH(),
.C_BASEADDR(),
.C_S_AXIS_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_S_AXIS_TUSER_WIDTH(),
.C_M_AXIS_DATA_WIDTH(),
.PHV_ADDR_WIDTH()
) demo (
.clk(clk), // axis clk
.aresetn(aresetn),
// input Slave AXI Stream
.s_axis_tdata (s_axis_tdata),
.s_axis_tkeep (s_axis_tkeep),
.s_axis_tuser (s_axis_tuser),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast (s_axis_tlast),
// output Master AXI Stream
.m_axis_tdata (m_axis_tdata),
.m_axis_tkeep (m_axis_tkeep),
.m_axis_tuser (m_axis_tuser),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast (m_axis_tlast)
);
endmodule
| 7.731347 |
module demux_1x2_top;
reg [3:0] in0;
reg sel;
wire [3:0] out0, out1;
integer i = 0;
demux_1x2 demux (
in0,
sel,
out0,
out1
);
initial begin
for (i = 0; i < 16; i = i + 1) begin
in0 = i + 1;
sel = i[0];
#1;
$display("in0 = %0d, sel = %0d, out0 = %0d, out1 = %0d", in0, sel, out0, out1);
end
end
endmodule
| 6.98808 |
module tb_demux_case;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_case uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),
.o6 (o6),
.o7 (o7),
.i (i)
);
initial begin
$dumpfile("tb_demux_case.vcd");
$dumpvars(0, tb_demux_case);
// Initialize Inputs
i = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3900 $finish;
end
always #17 i = ~i;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 3'b000;
else sel <= sel + 1;
end
endmodule
| 7.797713 |
module tb_demux_case_net;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_case uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),
.o6 (o6),
.o7 (o7),
.i (i)
);
initial begin
$dumpfile("tb_demux_case_net.vcd");
$dumpvars(0, tb_demux_case_net);
// Initialize Inputs
i = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3900 $finish;
end
always #17 i = ~i;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 3'b000;
else sel <= sel + 1;
end
endmodule
| 7.797713 |
module tb_demux_for;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_for uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),
.o6 (o6),
.o7 (o7),
.i (i)
);
initial begin
$dumpfile("tb_demux_for.vcd");
$dumpvars(0, tb_demux_for);
// Initialize Inputs
i = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3900 $finish;
end
always #17 i = ~i;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 3'b000;
else sel <= sel + 1;
end
endmodule
| 7.565734 |
module tb_demux_for_net;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_for uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),
.o6 (o6),
.o7 (o7),
.i (i)
);
initial begin
$dumpfile("tb_demux_for_net.vcd");
$dumpvars(0, tb_demux_for_net);
// Initialize Inputs
i = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3900 $finish;
end
always #17 i = ~i;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 3'b000;
else sel <= sel + 1;
end
endmodule
| 7.873836 |
module tb_demux_generate;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_generate uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),
.o6 (o6),
.o7 (o7),
.i (i)
);
initial begin
$dumpfile("tb_demux_generate.vcd");
$dumpvars(0, tb_demux_generate);
// Initialize Inputs
i = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3900 $finish;
end
always #17 i = ~i;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 3'b000;
else sel <= sel + 1;
end
endmodule
| 8.136728 |
module: deserializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_deserializer;
wire rxd;
wire rst;
wire clk;
wire [7:0] data;
wire received;
deserializer_gen_test generator (
.rxd(rxd),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
deserializer uut (
.rxd(rxd),
.rst(rst),
.clk(clk),
.data(data),
.received(received)
);
deserializer_check_test writer (
.received(received),
.data(data)
);
endmodule
| 7.284927 |
module tb_detect_errors;
parameter CYCLE = 16;
parameter whereis_aux = 0;
parameter packetsize = 33;
parameter segment_number_max = 16'd5;
reg rx_en = 0, clk = 0, rst = 0;
reg [7:0] rx_data = 0;
wire [31:0] count, ok, ng, lostnum;
wire valid;
wire [2:0] state;
reg [15:0] segment_number;
detect_errors2 #(
.whereis_aux(whereis_aux)
) uut (
.clk(clk),
.rst(rst),
.seg(segment_number),
.segment_number_max(segment_number_max),
.rx_en(rx_en),
.rx_data(rx_data),
.count(count),
.ok(ok),
.ng(ng),
.lostnum(lostnum),
.valid(valid),
.state(state)
);
always begin // create clock 125MHz
#3 clk = !clk;
#5;
end
task onepacket;
input [7:0] aux;
integer i;
integer j;
begin
rx_en = 1'b1;
for (i = 0; i < packetsize; i = i + 1) begin
case (i)
whereis_aux: rx_data = aux;
default: rx_data = 8'h12;
endcase
#CYCLE;
end // end for
rx_en = 1'b0;
rx_data = 8'hxx;
end
endtask
integer i;
integer j;
integer k;
integer a;
initial begin
$dumpfile("tb_detect_errors.vcd");
$dumpvars(0, uut);
clk = 0;
rst = 0;
rx_en = 0;
rx_data = 8'hxx;
#(CYCLE * 2);
rst = 1;
#CYCLE;
rst = 0;
#(CYCLE * 3);
a = 0;
#(CYCLE * 30);
for (k = 0; k < 4; k = k + 1) begin
for (i = 0; i <= 255; i = i + 1) begin
for (j = 0; j < segment_number_max; j = j + 1) begin
segment_number = j;
onepacket(a);
a = a + 1;
#(CYCLE * 10);
end
#(CYCLE * 3);
end
#(CYCLE * 9);
end
#(CYCLE * 40);
$finish;
end
endmodule
| 7.67994 |
module tb_devboard;
parameter PERIOD = 2;
reg clk = 1;
reg reset = 1;
always #(PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_devboard.vcd");
$dumpvars(0, tb_devboard);
// Power on reset, no touchy >:[
#(PERIOD * 2) reset <= 0;
#(PERIOD * 200);
$finish;
end
wire ack, stb, rw;
wire [31:0] addr, dtw, dtr;
hs32_cpu #(
.IMUL(1),
.BARREL_SHIFTER(1),
.PREFETCH_SIZE(2)
) cpu (
.i_clk(clk),
.reset(reset),
.addr(addr),
.rw(rw),
.din(dtr),
.dout(dtw),
.stb(stb),
.ack(ack)
);
ext_sram #(
.SRAM_LATCH_LAZY(0)
) sram (
.clk(clk),
.reset(reset),
.ack(ack),
.stb(stb),
.i_rw(rw),
.i_addr(addr),
.i_dtw(dtw),
.dtr(dtr)
);
endmodule
| 7.625449 |
module tb_dff8;
reg clk, reset, en;
reg [7:0] d;
wire [7:0] q;
dff8 tb_dff8 (
.clk(clk),
.reset(reset),
.en(en),
.d(d),
.q(q)
);
integer i;
initial begin
clk = 1'b0;
i = 0;
end // initial
always begin
#10 clk = ~clk;
end // always
always @(posedge clk) begin
if (i < 2) begin
d = 8'b0000_1111;
end // if (clk)
else if (i < 4) begin
d = 8'b1111_0000;
end // else if (~clk)
if (i & 2'b10) begin
en = 1'b0;
end // if (i & 2'b10)
else begin
en = 1'b1;
end // else
if (i >= 5) begin
reset = 1'b1;
end // if (i == 5)
else begin
reset = 1'b0;
end // else
if (i == 7) begin
$stop;
end // if (i == 6)
i = i + 1;
end // always @(posedge clk)
endmodule
| 6.799424 |
module tb_dff_asyncres;
// Inputs
reg clk, async_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_asyncres uut (
.clk(clk),
.async_reset(async_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_asyncres.vcd");
$dumpvars(0, tb_dff_asyncres);
// Initialize Inputs
clk = 0;
async_reset = 1;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #547 async_reset = ~async_reset;
endmodule
| 7.388007 |
module tb_dff_asyncres_syncres;
// Inputs
reg clk, async_reset, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_asyncres_syncres uut (
.clk(clk),
.async_reset(async_reset),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_asyncres_syncres.vcd");
$dumpvars(0, tb_dff_asyncres_syncres);
// Initialize Inputs
clk = 0;
async_reset = 1;
sync_reset = 0;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #113 sync_reset = ~sync_reset;
always #547 async_reset = ~async_reset;
endmodule
| 7.388007 |
module tb_dff_async_reset;
// Inputs
reg clk, async_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_reset uut (
.clk(clk),
.async_reset(async_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_async_reset.vcd");
$dumpvars(0, tb_dff_async_reset);
// Initialize Inputs
clk = 0;
async_reset = 1;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #547 async_reset = ~async_reset;
endmodule
| 6.904937 |
module tb_dff_async_set;
// Inputs
reg clk, async_set, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_set uut (
.clk(clk),
.async_set(async_set),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_async_set.vcd");
$dumpvars(0, tb_dff_async_set);
// Initialize Inputs
clk = 0;
async_set = 1;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #547 async_set = ~async_set;
endmodule
| 6.904937 |
module tb_dff_clear;
reg d, clk, reset;
wire q;
dff_async_clear dff (
q,
d,
reset,
clk
);
always @(posedge clk) begin
$display($time, " d=%b, clk=%b, reset=%b, q=%b\n", d, clk, reset, q);
end
initial begin
forever begin
#0 clk = 0;
#5 clk = 1;
#5 clk = 0;
end
end
initial begin
#0 d = 0;
reset = 1;
#4 d = 0;
reset = 0;
#50 d = 1;
reset = 1;
#20 d = 0;
reset = 0;
#30 $finish;
end
endmodule
| 7.15127 |
module tb_dff_const1;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const1 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const1.vcd");
$dumpvars(0, tb_dff_const1);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #1547 reset = ~reset;
endmodule
| 6.820369 |
module tb_dff_const3;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const3 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const3.vcd");
$dumpvars(0, tb_dff_const3);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #1547 reset = ~reset;
endmodule
| 7.059134 |
module tb_dff_const4;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const4 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const4.vcd");
$dumpvars(0, tb_dff_const4);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #1547 reset = ~reset;
endmodule
| 6.877993 |
module tb_dff_const5;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const5 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const5.vcd");
$dumpvars(0, tb_dff_const5);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #1547 reset = ~reset;
endmodule
| 6.513805 |
module tb_dff_en; //enabled d flip flop test bench
reg tb_clk, tb_en, tb_d; // 3inputs
wire tb_q; // wire tb_q
_dff_en U0_dff_en (
.clk(tb_clk),
.en (tb_en),
.d (tb_d),
.q (tb_q)
); //instance by using _dff_en
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; //every 5ns, invert tb_clk
end
initial begin
tb_en = 1'b1;
tb_d = 1'b1; //input(tb_en,tb_d)=(1,1)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_en = 1'b0;
tb_d = 1'b1; //after 10ns,input(tb_en,tb_d)=(0,1)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
$stop; //after 10ns,stop
end
endmodule
| 7.297135 |
module tb_dff_r; // testbench of Resettable D flipflop
reg tb_clk, tb_reset_n, tb_d; // 3 inputs
wire tb_q; // wire tb_q
_dff_r U0_dff (
.clk(tb_clk),
.reset_n(tb_reset_n),
.d(tb_d),
.q(tb_q)
); //instance by using _dff_r
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; //every 5ns, invert tb_clk
end
initial begin
tb_d=1'b1;
tb_reset_n = 1'b0; //input(tb_d,tb_reset_n)=(1,0)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0;
tb_reset_n = 1'b1; //after 10ns,input(tb_d,tb_reset_n)=(0,1)
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1;
tb_reset_n = 1'b0; //after 10ns,input(tb_d,tb_reset_n)=(1,0)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
$stop; //after 10ns,stop
end
endmodule
| 6.870625 |
module tb_dff_rs; //set, reset d flip flop test bench
reg tb_clk, tb_set_n, tb_reset_n, tb_d; // 4 inputs
wire tb_q; // wire tb_q
_dff_rs U0_dff_rs (
.clk(tb_clk),
.set_n(tb_set_n),
.reset_n(tb_reset_n),
.d(tb_d),
.q(tb_q)
); //instance by using _dff_rs
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; //every 5ns, invert tb_clk
end
initial begin
tb_d = 1'b1;
tb_set_n = 1'b0;
tb_reset_n = 1'b0; //input(tb_d,tb_set_n,tb_reset_n)=(1,0,0)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1;
tb_reset_n = 1'b1; //after 10ns,input(tb_d,tb_reset_n)=(1,1)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1;
tb_set_n = 1'b1; //after 10ns,input(tb_d,tb_set_n)=(1,1)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
$stop; //after 10ns,stop
end
endmodule
| 7.000466 |
module tb_dff_rs_sync_async; //sync async set,reset d flip flop test bench
reg tb_clk, tb_set_n, tb_reset_n, tb_d; // 4 inputs
wire tb_q_sync, tb_q_async; // use 2 wires
_dff_rs_sync_async U0_dff_rs_sync_async (
.clk(tb_clk),
.set_n(tb_set_n),
.reset_n(tb_reset_n), //instance by _dff_rs_sync_async
.d(tb_d),
.q_sync(tb_q_sync),
.q_async(tb_q_async)
);
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; //every 5ns, invert tb_clk
end
initial begin
tb_set_n = 1'b0;
tb_reset_n = 1'b0;
tb_d = 1'b0; //input(tb_set_n,tb_reset_n)=(0,0)
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0;
tb_reset_n = 1'b1; //after 10ns,input(tb_d,tb_reset_n)=(0,1)
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1;
tb_set_n = 1'b1; //after 10ns,input(tb_d,tb_set_n)=(1,1)
#10;
tb_d = 1'b0; //after 10ns,input(tb_d)=0
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
tb_d = 1'b0;
tb_reset_n = 1'b0; //after 10ns,input(tb_d,tb_reset_n)=(0,0)
#10;
tb_d = 1'b1; //after 10ns,input(tb_d)=1
#10;
$stop; //after 10ns,stop
end
endmodule
| 7.205853 |
module
`timescale 1ns/1ps
`include "./include/gscl45nm.v"
module tb_syn;
wire q;
reg d, clk;
dff d1 (clk, d, q);
always #5 clk = ~clk;
initial
begin
$monitor ("Time = %g d=%b, q=%b", $time, d, q);
clk = 0;
d = 0;
#6;
d = 1;
#3;
d = 0;
#14;
d = 1;
#14;
d = 0;
#18;
d = 1;
#6;
d = 0;
$finish;
end
initial
begin
$sdf_annotate("./netlist/dff.sdf", d1,,"sdf.log","MAXIMUM","1.0:1.0:1.0", "FROM_MAXIMUM");
$enable_warnings;
$log("ncsim.log");
end
endmodule
| 6.608387 |
module tb_dff_sync ();
reg clock, d, clear;
wire q;
dff_async_clear dff (
.q(q),
.d(d),
.clear(clear),
.clock(clock)
);
initial begin
$dumpfile("tb_dff.vcd");
$dumpvars;
end
initial clock = 1'b0;
always #5 clock = ~clock;
initial begin
d = 1'b0;
clear = 1'b1;
#10 d = 1'b1;
#10 d = 1'b0;
#10 clear = 1'b0;
#10 d = 1'b1;
#10 d = 1'b0;
#10 $finish;
end
endmodule
| 6.839537 |
module tb_dff_syncasync_reset;
// Inputs
reg clk, async_reset, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_syncasync_reset uut (
.clk(clk),
.async_reset(async_reset),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_syncasync_reset.vcd");
$dumpvars(0, tb_dff_syncasync_reset);
// Initialize Inputs
clk = 0;
async_reset = 1;
sync_reset = 0;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #113 sync_reset = ~sync_reset;
always #547 async_reset = ~async_reset;
endmodule
| 7.531848 |
module tb_dff_syncres;
// Inputs
reg clk, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_syncres uut (
.clk(clk),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_syncres.vcd");
$dumpvars(0, tb_dff_syncres);
// Initialize Inputs
clk = 0;
sync_reset = 0;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #113 sync_reset = ~sync_reset;
endmodule
| 7.198298 |
module tb_dff_sync_reset;
// Inputs
reg clk, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_sync_reset uut (
.clk(clk),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_sync_reset.vcd");
$dumpvars(0, tb_dff_sync_reset);
// Initialize Inputs
clk = 0;
sync_reset = 0;
d = 0;
#3000 $finish;
end
always #10 clk = ~clk;
always #23 d = ~d;
always #113 sync_reset = ~sync_reset;
endmodule
| 7.368056 |
module tb_DFlipFlop;
//Inputs
reg d, clk;
//Output
wire q, q1;
integer i;
//Instancia a unidade a ser testada
DFlipFlop uut (
.d (d),
.clk(clk),
.q (q),
.q1 (q1)
);
//Pulso do clock
always begin
clk = 1'b0;
#10;
clk = 1'b1;
#10;
end
initial begin
for (
i = 0; i < 2; i = i + 1
) //Testa d = 0 e d = 1
begin
d = i;
#20;
end
$finish;
end
endmodule
| 7.353168 |
module: Dflop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Dflop;
// Inputs
reg rst;
reg clk;
reg din;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
Dflop uut (
.rst(rst),
.clk(clk),
.din(din),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
rst = 1'b0;
clk = 1'b0;
#40;
din = 1'b0;
#40;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b0;
rst = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
$finish;
// Add stimulus here
end
endmodule
| 7.468095 |
module
//-------------------------------------------------------------------
module tb_dft();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_IN_W = 12;
localparam DUT_DATA_OUT_W = 15;
reg signed [DUT_DATA_IN_W-1:0] data_in = 0;
reg valid_in = 0;
wire ready;
wire [DUT_DATA_OUT_W-1:0] data_out;
wire valid_out;
dft
#(
.DATA_W (DUT_DATA_IN_W) // Data input width
)
dut
(
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // System reset
// Input data from ADC
.data_in (data_in), // Data input
.valid_in (valid_in), // Data input is valid
.ready (ready), // DFT is ready to receive more data
// Output data
.data_out (data_out), // Data output
.valid_out (valid_out) // Output data is valid
);
//-------------------------------------------------------------------
// Testbench body
//------------------------------------------------------------------
localparam DATA_CHUNKS_N = 256;
localparam DATA_IN_N = 32*DATA_CHUNKS_N;
localparam DATA_OUT_N = DATA_CHUNKS_N;
integer err_cnt = 0;
// Test memory array
reg [DUT_DATA_IN_W-1:0] test_mem_in [DATA_IN_N-1:0];
reg [DUT_DATA_OUT_W-1:0] test_mem_out [DATA_CHUNKS_N-1:0];
reg [DUT_DATA_OUT_W-1:0] golden_mem_out [DATA_CHUNKS_N-1:0];
initial
begin
$readmemh("../tb/tb_dft_in.mem", test_mem_in);
$readmemh("../tb/tb_dft_out.mem", golden_mem_out);
end
task send_data();
begin : task_send_data
integer i;
for (i = 0; i < DATA_IN_N; i = i + 1) begin
@(posedge tb_clk);
if (!ready) begin
//valid_in = 1'b0;
wait(ready);
@(posedge tb_clk);
end
#0;
data_in = test_mem_in[i];
valid_in = 1'b1;
end
@(posedge tb_clk);
#0;
valid_in = 1'b0;
end
endtask
task result_read();
begin : task_result_read
integer i;
for (i = 0; i < DATA_OUT_N; i = i + 1) begin
@(posedge valid_out);
@(posedge tb_clk);
test_mem_out[i] = data_out;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_OUT_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
wait(!tb_rst);
#20;
fork
send_data();
result_read();
join
check();
#1000;
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
`ifdef __ICARUS__
$finish;
`else
$stop;
`endif
end
`ifdef __ICARUS__
initial begin
$dumpfile("work.vcd");
$dumpvars(0, tb_dft);
end
`endif
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_complex_abs();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_W = 16;
reg signed [DUT_DATA_W-1:0] data_re = 0;
reg signed [DUT_DATA_W-1:0] data_im = 0;
reg valid = 0;
wire [DUT_DATA_W-1:0] result;
wire done;
dft_complex_abs
#(
.DATA_W (DUT_DATA_W)
)
dut
(
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // System reset
// Input data
.data_re (data_re), // Data real part
.data_im (data_im), // Data imaginary part
.valid (valid), // Data valid
// Output data
.result (result), // Result
.done (done) // Calculations were done
);
//-------------------------------------------------------------------
// Testbench body
//-------------------------------------------------------------------
integer err_cnt = 0;
localparam BATCH_N = 3;
localparam DATA_N = 256*BATCH_N;
// Test memory array
reg [DUT_DATA_W-1:0] test_mem_re_in [DATA_N-1:0];
reg [DUT_DATA_W-1:0] test_mem_im_in [DATA_N-1:0];
reg [DUT_DATA_W-1:0] test_mem_out [DATA_N-1:0];
reg [DUT_DATA_W-1:0] golden_mem_out [DATA_N-1:0];
initial
begin
$readmemh("../tb/tb_dft_complex_abs_in_re.mem", test_mem_re_in);
$readmemh("../tb/tb_dft_complex_abs_in_im.mem", test_mem_im_in);
$readmemh("../tb/tb_dft_complex_abs_out.mem", golden_mem_out);
end
task send_data;
begin : task_send_data
integer i, j;
for (i=0; i<DATA_N/BATCH_N; i=i+1) begin
for (j=0; j<BATCH_N; j=j+1) begin
@(posedge tb_clk);
data_re = test_mem_re_in[i*BATCH_N + j];
data_im = test_mem_im_in[i*BATCH_N + j];
valid = 1'b1;
end
@(posedge tb_clk);
valid = 1'b0;
repeat(109) @(posedge tb_clk);
end
end
endtask
task get_result();
begin : task_get_result
integer i;
for (i=0; i<DATA_N; i=i+1) begin
@(posedge done);
@(posedge tb_clk);
test_mem_out[i] = result;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
fork
send_data();
get_result();
join
check();
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_fifo();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_ADDR_W = 8;
localparam DUT_DATA_W = 12;
reg [DUT_DATA_W-1:0] wdata = 0;
reg wr = 0;
wire full;
wire [DUT_DATA_W-1:0] rdata;
reg rd = 0;
wire empty;
dft_fifo
#(
.ADDR_W (DUT_ADDR_W), // Memory depth
.DATA_W (DUT_DATA_W) // Data width
)
dut
(
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // System reset
// Write interface
.wdata (wdata), // Write data
.wr (wr), // Write operation
.full (full), // FIFO is full
// Read interface
.rdata (rdata), // Read data
.rd (rd), // Read operation
.empty (empty) // FIFO is empty
);
//-------------------------------------------------------------------
// Testbench body
//------------------------------------------------------------------
integer err_cnt = 0;
// Test memory array
reg [DUT_DATA_W-1:0] test_mem_in [2**DUT_ADDR_W-1:0];
reg [DUT_DATA_W-1:0] test_mem_out [2**DUT_ADDR_W-1:0];
initial
begin : test_mem_init
integer i;
for (i = 0; i < 2**DUT_ADDR_W; i = i + 1) begin
test_mem_in[i] = $random();
end
end
task fifo_write();
begin : task_fifo_write
integer i;
for (i = 0; i < 2**DUT_ADDR_W; i = i + 1) begin
@(posedge tb_clk);
wdata = test_mem_in[i];
wr = 1'b1;
@(posedge tb_clk);
wr = 1'b0;
end
end
endtask
task fifo_read();
begin : task_fifo_read
integer i;
wait(!empty);
@(posedge tb_clk);
for (i = 0; i < 2**DUT_ADDR_W; i = i + 1) begin
@(posedge tb_clk);
rd = 1'b1;
@(posedge tb_clk);
rd = 1'b0;
@(posedge tb_clk);
@(posedge tb_clk);
@(posedge tb_clk);
test_mem_out[i] = rdata;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < 2**DUT_ADDR_W; i = i + 1) begin
if (test_mem_out[i] != test_mem_in[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Memory: Addr=%d, expected 0x%04x, got 0x%04x!", i, test_mem_in[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
wait(!tb_rst);
#20;
fork
fifo_write();
fifo_read();
join
check();
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_postproc();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_W = 16;
reg signed [DUT_DATA_W-1:0] data_re_in = 0;
reg signed [DUT_DATA_W-1:0] data_im_in = 0;
reg valid_in = 0;
wire [DUT_DATA_W-2:0] data_out;
wire valid_out;
dft_postproc
#(
.DATA_W (DUT_DATA_W) // Data width
)
dut
(
// System
.clk (tb_clk),
.rst (tb_rst),
// Input data
.data_re_in (data_re_in), // Data real part
.data_im_in (data_im_in), // Data imaginary part
.valid_in (valid_in), // Data input valid
// Output data
.data_out (data_out), // Data output
.valid_out (valid_out) // Data output is valid
);
//-------------------------------------------------------------------
// Testbench body
//-------------------------------------------------------------------
integer err_cnt = 0;
localparam BATCH_N = 3;
localparam DATA_N = 256*BATCH_N;
// Test memory array
reg [DUT_DATA_W-1:0] test_mem_re_in [DATA_N-1:0];
reg [DUT_DATA_W-1:0] test_mem_im_in [DATA_N-1:0];
reg [DUT_DATA_W-2:0] test_mem_out [DATA_N-1:0];
reg [DUT_DATA_W-2:0] golden_mem_out [DATA_N-1:0];
initial
begin
$readmemh("../tb/tb_dft_postproc_in_re.mem", test_mem_re_in);
$readmemh("../tb/tb_dft_postproc_in_im.mem", test_mem_im_in);
$readmemh("../tb/tb_dft_postproc_out.mem", golden_mem_out);
end
task send_data;
begin : task_send_data
integer i, j;
for (i=0; i<DATA_N/BATCH_N; i=i+1) begin
for (j=0; j<BATCH_N; j=j+1) begin
@(posedge tb_clk);
data_re_in = test_mem_re_in[i*BATCH_N + j];
data_im_in = test_mem_im_in[i*BATCH_N + j];
valid_in = 1'b1;
end
@(posedge tb_clk);
valid_in = 1'b0;
repeat(109) @(posedge tb_clk);
end
end
endtask
task get_result();
begin : task_get_result
integer i;
for (i=0; i<DATA_N/BATCH_N; i=i+1) begin
@(posedge valid_out);
@(posedge tb_clk);
test_mem_out[i] = data_out;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
fork
send_data();
get_result();
join
check();
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_preproc();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_W = 12;
reg signed [DUT_DATA_W-1:0] data_in;
reg valid_in;
wire signed [DUT_DATA_W-1:0] data_out;
wire valid_out;
dft_preproc
#(
.DATA_W (DUT_DATA_W)
)
dut
(
// System
.clk (tb_clk),
.rst (tb_rst),
// Input data
.data_in (data_in),
.valid_in (valid_in),
// Output data
.data_out (data_out),
.valid_out (valid_out),
.ready_out (1'b1)
);
//-------------------------------------------------------------------
// Testbench body
//-------------------------------------------------------------------
integer err_cnt = 0;
reg signed [DUT_DATA_W:0] golden_result;
task set_rand_data_var1;
begin
@(posedge tb_clk);
data_in = $random();
golden_result = data_in;
valid_in = 1'b1;
@(posedge tb_clk);
valid_in = 1'b0;
@(posedge tb_clk);
data_in = $random();
golden_result = golden_result + data_in;
valid_in = 1'b1;
@(posedge tb_clk);
valid_in = 1'b0;
golden_result = golden_result/2;
end
endtask
task set_rand_data_var2;
begin
data_in = $random();
golden_result = data_in;
valid_in = 1'b1;
@(posedge tb_clk);
data_in = $random();
golden_result = golden_result + data_in;
golden_result = golden_result/2;
end
endtask
task check_result;
begin
if (golden_result != data_out) begin
err_cnt = err_cnt + 1;
$display("Error! expected %0d, got %0d!", golden_result, data_out);
end
end
endtask
// Main test
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
set_rand_data_var1();
wait(valid_out);
check_result();
set_rand_data_var1();
wait(valid_out);
check_result();
@(posedge tb_clk);
set_rand_data_var2();
@(posedge tb_clk); #1;
check_result();
set_rand_data_var2();
@(posedge tb_clk); #1;
check_result();
set_rand_data_var2();
@(posedge tb_clk); #1;
check_result();
valid_in = 1'b0;
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_sqrsum();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_IN_W = 16;
localparam DUT_SUM_PIPELINE_STAGES = 2;
localparam DUT_DATA_OUT_W = DUT_DATA_IN_W * 2;
reg signed [DUT_DATA_IN_W-1:0] data_re = 0;
reg signed [DUT_DATA_IN_W-1:0] data_im = 0;
wire [DUT_DATA_OUT_W-1:0] result;
dft_sqrsum
#(
.DATA_W (DUT_DATA_IN_W),
.SUM_PIPELINE_STAGES (DUT_SUM_PIPELINE_STAGES)
) dut (
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // MAC clear
// Input data
.data_re (data_re), // Data real part
.data_im (data_im), // Data imaginary part
// Output data
.result (result) // Result
);
reg valid_in = 0;
wire valid_out;
dft_dline
#(
.STAGES_N (DUT_SUM_PIPELINE_STAGES + 2)
) dline (
.clk (tb_clk),
.rst (tb_rst),
.din (valid_in),
.dout (valid_out)
);
//-------------------------------------------------------------------
// Testbench body
//-------------------------------------------------------------------
integer err_cnt = 0;
localparam DATA_N = 64;
// Test memory array
reg [DUT_DATA_IN_W-1:0] test_mem_re_in [DATA_N-1:0];
reg [DUT_DATA_IN_W-1:0] test_mem_im_in [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] test_mem_out [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] golden_mem_out [DATA_N-1:0];
initial
begin : test_mem_init
integer i;
reg [DUT_DATA_OUT_W-1:0] temp1;
reg [DUT_DATA_OUT_W-1:0] temp2;
for (i=0; i<DATA_N; i=i+1) begin
test_mem_re_in[i] = $random();
test_mem_im_in[i] = $random();
end
for (i=0; i<DATA_N; i=i+1) begin
temp1 = $signed(test_mem_re_in[i])*$signed(test_mem_re_in[i]);
temp2 = $signed(test_mem_im_in[i])*$signed(test_mem_im_in[i]);
golden_mem_out[i] = temp1 + temp2;
end
end
task send_data;
begin : task_send_data
integer i;
for (i=0; i<DATA_N; i=i+1) begin
@(posedge tb_clk);
data_re = test_mem_re_in[i];
data_im = test_mem_im_in[i];
valid_in = 1'b1;
@(posedge tb_clk);
valid_in = 1'b0;
end
end
endtask
task recv_data();
begin : task_recv_data
integer i;
for (i=0; i<DATA_N; i=i+1) begin
@(posedge valid_out);
@(posedge tb_clk);
test_mem_out[i] = result;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
fork
send_data();
recv_data();
join
check();
#100;
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_sqrt();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_IN_W = 32;
localparam DUT_DATA_OUT_W = DUT_DATA_IN_W/2;
reg [DUT_DATA_IN_W-1:0] data;
reg valid;
wire [DUT_DATA_OUT_W-1:0] result;
wire done;
dft_sqrt
#(
.DATA_W (DUT_DATA_IN_W)
)
dut
(
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // System reset
// Input data
.data (data), // Data input
.valid (valid), // Data valid
// Output data
.result (result), // Result
.done (done) // Calculations were done
);
//-------------------------------------------------------------------
// Testbench body
//-------------------------------------------------------------------
integer err_cnt = 0;
localparam DATA_N = 256;
// Test memory array
reg [DUT_DATA_IN_W-1:0] test_mem_in [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] test_mem_out [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] golden_mem_out [DATA_N-1:0];
initial
begin
$readmemh("../tb/tb_dft_sqrt_in.mem", test_mem_in);
$readmemh("../tb/tb_dft_sqrt_out.mem", golden_mem_out);
end
task send_data;
begin : task_send_data
integer i;
for (i=0; i<DATA_N; i=i+1) begin
@(posedge tb_clk);
data = test_mem_in[i];
valid = 1'b1;
@(posedge tb_clk);
valid = 1'b0;
wait(done);
end
end
endtask
task get_result();
begin : task_get_result
integer i;
for (i=0; i<DATA_N; i=i+1) begin
@(posedge done);
@(posedge tb_clk);
test_mem_out[i] = result;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
fork
send_data();
get_result();
join
check();
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_twiddle_rom();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_ADDR_W = 2;
localparam DUT_DATA_W = 16;
localparam DUT_MEM_FILE_RE = "../rtl/mem_files/dft_twiddle_re_16.mem";
localparam DUT_MEM_FILE_IM = "../rtl/mem_files/dft_twiddle_im_16.mem";
wire [DUT_DATA_W-1:0] rdata_re;
wire [DUT_DATA_W-1:0] rdata_im;
reg [DUT_ADDR_W-1:0] raddr;
reg rd;
dft_twiddle_rom
#(
.ADDR_W (DUT_ADDR_W),
.DATA_W (DUT_DATA_W)
) dut (
// System
.clk (tb_clk),
.rst (tb_rst),
// Read interface
.rdata_re (rdata_re),
.rdata_im (rdata_im),
.raddr (raddr),
.rd (rd)
);
//-------------------------------------------------------------------
// Testbench body
//------------------------------------------------------------------
// Test memory array
reg [DUT_DATA_W-1:0] test_mem_re [2**DUT_ADDR_W-1:0];
reg [DUT_DATA_W-1:0] test_mem_im [2**DUT_ADDR_W-1:0];
// ROM init
initial begin
$readmemh(DUT_MEM_FILE_RE, test_mem_re);
$readmemh(DUT_MEM_FILE_IM, test_mem_im);
end
// Main test
integer err_cnt = 0;
initial begin : tb_main
integer i;
wait(!tb_rst);
#20;
@(posedge tb_clk);
for (i = 0; i <= 2**DUT_ADDR_W; i=i+1) begin
@(posedge tb_clk);
raddr = i;
rd = 1'b1;
#1;
if (i>0) begin
if (rdata_re != test_mem_re[i-1]) begin
err_cnt = err_cnt + 1;
$display("Error! Memory RE: Addr=%d, expected 0x%04x, got 0x%04x!", i, test_mem_re[i-1], rdata_re);
end
if (rdata_im != test_mem_im[i-1]) begin
err_cnt = err_cnt + 1;
$display("Error! Memory IM: Addr=%d, expected 0x%04x, got 0x%04x!", i, test_mem_im[i-1], rdata_im);
end
end
end
rd = 1'b0;
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
$stop;
end
endmodule
| 8.13663 |
module tb_digitization;
reg clk;
reg [7:0] input_bit;
wire [7:0] freq;
digitization UUT (
.clk(clk),
.input_bit(input_bit),
.freq(freq)
);
initial begin
$display("******************************************************");
$display("BEGIN TESTBENCH");
$display("******************************************************");
end
initial begin
clk = 0;
forever begin
clk = #5 ~clk;
end
end
initial begin
// 0
input_bit[7:4] = 4'b0000;
input_bit[3:0] = 4'b0000;
#1000;
// 25
input_bit[7:4] = 4'b0010;
input_bit[3:0] = 4'b0101;
#1000;
//37
input_bit[7:4] = 4'b0011;
input_bit[3:0] = 4'b0111;
#1000;
// 50
input_bit[7:4] = 4'b0101;
input_bit[3:0] = 4'b0000;
#1000;
// 55
input_bit[7:4] = 4'b0101;
input_bit[3:0] = 4'b0101;
#1000;
// 99
input_bit[7:4] = 4'b1001;
input_bit[3:0] = 4'b1001;
#1000;
$finish;
end
endmodule
| 6.693934 |
module tb_display_clock;
// display_clock Parameters
parameter PERIOD = 10;
// display_clock Inputs
reg load = 0;
reg set = 0;
reg [3:0] set_id = 0;
reg [3:0] set_num = 0;
reg [3:0] seconds_ones = 1;
reg [3:0] minutes_ones = 3;
reg [3:0] load_minutes_ones = 5;
reg [2:0] seconds_tens = 2;
reg [2:0] minutes_tens = 4;
reg [2:0] load_minutes_tens = 6;
// display_clock Outputs
wire [3:0] out_seconds_ones;
wire [3:0] out_minutes_ones;
wire [2:0] out_seconds_tens;
wire [2:0] out_minutes_tens;
initial begin
#(PERIOD * 10) set = 1;
#(PERIOD * 5) set = 0;
end
initial begin
#(PERIOD * 11) set_id = 'b01;
set_num = 5;
#(PERIOD) set_id = 0;
set_num = 0;
end
initial begin
#(PERIOD * 20) load = 1;
#(PERIOD * 10) load = 0;
end
display_clock u_display_clock (
.load (load),
.set (set),
.set_id (set_id[3:0]),
.set_num (set_num[3:0]),
.seconds_ones (seconds_ones[3:0]),
.minutes_ones (minutes_ones[3:0]),
.load_minutes_ones(load_minutes_ones[3:0]),
.seconds_tens (seconds_tens[2:0]),
.minutes_tens (minutes_tens[2:0]),
.load_minutes_tens(load_minutes_tens[2:0]),
.out_seconds_ones(out_seconds_ones[3:0]),
.out_minutes_ones(out_minutes_ones[3:0]),
.out_seconds_tens(out_seconds_tens[2:0]),
.out_minutes_tens(out_minutes_tens[2:0])
);
initial begin
$finish;
end
endmodule
| 7.856061 |
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