code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
/*
`ifdef MOD_OSRAM
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base = 32'h2000_0000;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base = 32'h2000_0000;
`endif
*/
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
/*
`ifdef MOD_OSRAM
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base;
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base;
`endif
*/
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M / 2) CLK <= ~CLK;
end
reg [31:0] rslt;
/*
always @(posedge CLK) begin
if((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wdata;
end
end
*/
// Sinario
initial begin
wait (CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
/*
wait((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF));
*/
#(2000000);
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait (led == 4'hF);
repeat (10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait (sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
ArtyA7 #(
.MEM_FILE("../../../../src/imem.hex")
) u_ArtyA7 (
.CLK100MHZ(CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out(uart_rxd_out),
.led(led)
);
/*
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
*/
task_uart u_task_uart (
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule
| 6.574589 |
module tb_ascon_vanilla ();
reg [319:0] in;
wire [319:0] out;
reg clk;
reg reset, start_dut;
wire done;
localparam Tclk = 10;
localparam Tclkd = (Tclk / 2.0);
always @(*) #(Tclk / 2.0) clk <= ~clk;
Ascon_FSM #(d) dut (
start_dut,
clk,
reset,
in,
done,
out
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb_ascon_vanilla);
clk = 0;
reset = 1;
#40 reset = 0;
start_dut = 1;
in = 320'h80400c0600000000000102030405060708090a0b0c0d0e0f000102030405060708090a0b0c0d0e0f;
#10 start_dut = 0;
in = 320'hX;
end
always @(done) begin
if (done) begin
#20 $finish();
end
end
endmodule
| 7.102892 |
module: asic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_asic;
// Inputs
reg clk;
reg rst;
// Outputs
wire [1:0] r;
wire [1:0] g;
wire [1:0] b;
wire bright;
wire csync;
wire int_n;
// Instantiate the Unit Under Test (UUT)
asic uut (
.clk(clk),
.rst_n(1'b1),
// CPU interface
.mreq_n(1'b1),
.iorq_n(1'b1),
.rd_n(1'b1),
.wr_n(1'b1),
.cpuaddr(16'h1234),
.data_from_cpu(8'h88),
.data_to_cpu(),
.data_enable_n(),
.wait_n(),
// RAM/ROM interface
.vramaddr(),
.cpuramaddr(),
.data_from_ram(8'hAA),
.ramwr_n(),
.romcs_n(),
.ramcs_n(),
.asic_is_using_ram(),
// audio I/O
.ear(1'b0),
.mic(),
.beep(),
// keyboard I/O
.keyboard(8'hFF),
.rdmsel(),
// disk I/O
.disc1_n(),
.disc2_n(),
// video output
.r(r),
.g(g),
.b(b),
.bright(bright),
.csync(csync),
.int_n(int_n)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
clk = #(1000.0/24.0) ~clk;
end
endmodule
| 6.618777 |
module tb_async_micron_controller (
input clk50MHz,
output mwe_L,
output moe_L,
output madv_L,
output mclk,
output mub_L,
output mlb_L,
output mce_L,
output mcre,
input mwait,
output [22:0] maddr,
output [7:0] debug_out,
inout [15:0] mem_data,
input rx,
output tx
);
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [7:0] req;
assign req[6:0] = 0;
wire [7:0] ack;
wire [BUS_WIDTH-1:0] master_out;
wire [CTRL_WIDTH-1:0] master_ctrl_out;
wire [BUS_WIDTH-1:0] bus_data_out;
wire [CTRL_WIDTH-1:0] bus_ctrl_out;
wire [BUS_WIDTH-1:0] slave_out;
wire [CTRL_WIDTH-1:0] slave_ctrl_out;
micron_controller_async sramctrl (
.clk50MHz(clk50MHz),
.bus_data_in(bus),
.bus_data_out(slave_out),
.bus_ctrl_in(ctrl),
.bus_ctrl_out(slave_ctrl_out),
.bus_ack(ack[0]),
.mem_data(mem_data),
.maddr(maddr),
.moe_L(moe_L),
.mwe_L(mwe_L),
.madv_L(madv_L),
.mclk(mclk),
.mub_L(mub_L),
.mlb_L(mlb_L),
.mce_L(mce_L),
.mcre(mcre),
.mwait(mwait),
.debug_out(debug_out)
);
uartInterface master (
.bus_in(bus),
.bus_ack(ack[7]),
.clk50MHz(clk50MHz),
.bus_req(req[7]),
.bus_out(master_out),
.ctrl_in(ctrl),
.ctrl_out(master_ctrl_out),
.rx(rx),
.tx(tx)
);
BusController controller (
.req(req),
.clk(clk50MHz),
.ack(ack),
.bus_in_0(slave_out),
.bus_in_7(master_out),
.bus_out(bus),
.ctrl_in_0(slave_ctrl_out),
.ctrl_in_7(master_ctrl_out),
.ctrl_out(ctrl)
);
endmodule
| 7.725085 |
module tb_asyn_bridge;
localparam ADDR_WD = 8, DATA_WD = 6, STRB_WD = 2, PROT_WD = 4;
reg a_pclk;
reg a_prst_n;
reg b_pclk;
reg b_prst_n;
reg a_psel;
reg a_penable;
reg a_pwrite;
reg [ADDR_WD-1 : 0] a_paddr;
reg [DATA_WD-1 : 0] a_pwdata;
reg [PROT_WD-1 : 0] a_pprot;
reg [STRB_WD-1 : 0] a_pstrb;
wire [DATA_WD-1 : 0] a_prdata;
wire a_pready;
wire b_psel;
wire b_penable;
wire b_pwrite;
wire [ADDR_WD-1 : 0] b_paddr;
wire [DATA_WD-1 : 0] b_pwdata;
wire [PROT_WD-1 : 0] b_pprot;
wire [STRB_WD-1 : 0] b_pstrb;
wire [DATA_WD-1 : 0] b_prdata;
wire b_pready;
reg [ADDR_WD-1 : 0] cnt;
initial begin
$dumpfile("asyn_bridge.vcd");
$dumpvars;
end
initial begin
a_pclk = 1'b0;
forever begin
#7;
a_pclk = ~a_pclk;
end
end
initial begin
b_pclk = 1'b0;
forever begin
#11;
b_pclk = ~b_pclk;
end
end
initial begin
a_prst_n = 1'b1;
b_prst_n = 1'b1;
#1;
a_prst_n = 1'b0;
b_prst_n = 1'b0;
#1;
a_prst_n = 1'b1;
b_prst_n = 1'b1;
#100000;
$finish;
end
always @(posedge a_pclk or negedge a_prst_n) begin
if (!a_prst_n) begin
a_psel <= 1'b0;
end else begin
if (!a_psel) begin
a_psel <= $random;
end else if (a_penable && a_pready) begin
a_psel <= $random;
end
end
end
always @(posedge a_pclk or negedge a_prst_n) begin
if (!a_prst_n) begin
a_penable <= 1'b0;
end else begin
if (a_psel) begin
a_penable <= 1'b1;
end
if (a_penable && a_pready) begin
a_penable <= 1'b0;
end
end
end
always @(posedge a_pclk or negedge a_prst_n) begin
if (!a_prst_n) begin
cnt <= 'b0;
end else if (a_penable && a_pready) begin
cnt <= cnt + 1'b1;
end
end
always @(posedge a_pclk or negedge a_prst_n) begin
if (!a_prst_n) begin
a_pwrite <= 1'b1;
end else if (cnt == {ADDR_WD{1'b1}}) begin
a_pwrite <= 1'b0;
end
end
always @(posedge a_pclk) begin
a_paddr <= cnt;
a_pwdata <= cnt[DATA_WD-1 : 0];
end
initial begin
a_pprot = 3'b0;
a_pstrb = 4'b1111;
end
asyn_bridge_top #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) asyn_bridge_top (
.a_pclk(a_pclk),
.a_prst_n(a_prst_n),
.a_psel(a_psel),
.a_penable(a_penable),
.a_pwrite(a_pwrite),
.a_paddr(a_paddr),
.a_pwdata(a_pwdata),
.a_pprot(a_pprot),
.a_pstrb(a_pstrb),
.a_prdata(a_prdata),
.a_pready(a_pready),
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(b_psel),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(b_prdata),
.b_pready(b_pready)
);
slave_mux #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) slave_mux (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(b_psel),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(b_prdata),
.b_pready(b_pready)
);
endmodule
| 6.989125 |
module tb;
parameter DEPTH = 16;
parameter WIDTH = 8;
parameter PTR_WDITH = 4;
parameter WR_DELAY = 13;
parameter RD_DELAY = 12;
parameter WR_TP = 15;
parameter RD_TP = 15;
reg wr_en_i, rd_en_i;
reg [WIDTH-1:0] wdata_i;
wire full_o;
wire [WIDTH-1:0] rdata_o;
wire empty_o;
reg wr_clk_i, rd_clk_i, rst_i;
wire error_o;
integer i;
integer wr_delay, rd_delay;
reg [30*8:1] testname;
async_fifo dut (
wr_en_i,
wdata_i,
full_o,
rd_en_i,
rdata_o,
empty_o,
wr_clk_i,
rd_clk_i,
rst_i,
error_o
);
initial begin
wr_clk_i = 0;
forever #(WR_TP / 2.0) wr_clk_i = ~wr_clk_i;
end
initial begin
rd_clk_i = 0;
forever #(RD_TP / 2.0) rd_clk_i = ~rd_clk_i;
end
initial begin
$value$plusargs("testname=%s", testname);
rst_i = 1;
repeat (2) @(posedge wr_clk_i);
rst_i = 0;
case (testname)
"test_full": begin
//make FIFO full
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge wr_clk_i);
wdata_i = $random;
wr_en_i = 1;
end
@(posedge wr_clk_i);
wdata_i = 0;
wr_en_i = 0;
end
"test_empty": begin
//make FIFO full
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge wr_clk_i);
wdata_i = $random;
wr_en_i = 1;
end
@(posedge wr_clk_i);
wdata_i = 0;
wr_en_i = 0;
//make FIFO empty
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge rd_clk_i);
rd_en_i = 1;
end
@(posedge rd_clk_i);
rd_en_i = 0;
end
"test_full_error": begin
for (i = 0; i < DEPTH + 1; i = i + 1) begin
@(posedge wr_clk_i);
wdata_i = $random;
wr_en_i = 1;
end
@(posedge wr_clk_i);
wdata_i = 0;
wr_en_i = 0;
end
"test_empty_error": begin
//make FIFO full
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge wr_clk_i);
wdata_i = $random;
wr_en_i = 1;
end
@(posedge wr_clk_i);
wdata_i = 0;
wr_en_i = 0;
//make FIFO empty
for (i = 0; i < DEPTH + 1; i = i + 1) begin
@(posedge rd_clk_i);
rd_en_i = 1;
end
@(posedge rd_clk_i);
rd_en_i = 0;
end
"test_concurrent_wr_rd": begin
fork
begin //write process
for (i = 0; i < 500; i = i + 1) begin
@(posedge wr_clk_i);
wdata_i = $random;
wr_en_i = 1;
wr_delay = $urandom_range(1, WR_DELAY);
@(posedge wr_clk_i);
wr_en_i = 0;
repeat (wr_delay - 1) @(posedge wr_clk_i);
end
end
begin //read process
for (i = 0; i < 500 + 1; i = i + 1) begin
@(posedge rd_clk_i);
rd_en_i = 1;
rd_delay = $urandom_range(1, RD_DELAY);
@(posedge rd_clk_i);
rd_en_i = 0;
repeat (rd_delay - 1) @(posedge rd_clk_i);
end
end
join
end
endcase
#100;
$finish;
end
endmodule
| 6.612288 |
module tb_asyn_fifo_v2;
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 4 ;
reg reset_l;
reg wr_clk;
reg wr_en;
wire full;
reg [15:0] write_data;
reg rd_clk;
reg rd_en;
wire empty;
wire [15:0] read_data;
reg [15:0] wr_cnt;
reg [15:0] q;
initial begin
reset_l <= 1'b0;
#200 reset_l <= 1'b1;
end
initial begin
wr_clk <= 1'b0;
forever #10 wr_clk <= ~wr_clk;
end
initial begin
rd_clk <= 1'b1;
forever #10 rd_clk <= ~rd_clk;
end
always(posedge wr_clk or negedge reset_l)begin
if(reset_l == 1'b0)begin
wr_en <= 1'b0;
end
else begin
if(full != 1'b0)begin
wr_en <= 1'b1;
end
end
end
always(posedge wr_clk or negedge reset_l)begin
if(reset_l == 1'b0)begin
wr_cnt <= 15'b0;
end
else begin
if(wr_en == 1'b1)begin
wr_cnt <= wr_cnt + 1;
end
end
end
assign write_data = (wr_en == 1) ? wr_cnt : 0;
always(posedge rd_clk or negedge reset_l)begin
if(reset_l == 1'b0)begin
rd_data <= 15'b0;
end
else begin
if(full == 1'b0)begin
rd_en <= 1'b1;
end
end
end
assign q = (rd_en == 1'b1) ? read_data : 0;
asyn_fifo_v2
#(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH)
)
U_asyn_fifo_v2(
.reset_l (reset_l),
.wr_clk (wr_clk),//дʱ
.wr_en (wr_en),//дʹ
.full (full),//asyn_full == 0 ʾ 1ʾ
.write_data (write_data),//д
.rd_clk (rd_clk),//ʱ
.rd_en (rd_en),//ʹ
.empty (empty),//͵ƽʹasyn_empty == 0 ʾգ1ʾǿ
.read_data (read_data) // w_req
)
endmodule
| 6.997609 |
module tb_avg_inst (
output wire [63:0] avmm_0_rw_address, // avmm_0_rw.address
output wire [ 7:0] avmm_0_rw_byteenable, // .byteenable
output wire avmm_0_rw_read, // .read
input wire [63:0] avmm_0_rw_readdata, // .readdata
output wire avmm_0_rw_write, // .write
output wire [63:0] avmm_0_rw_writedata, // .writedata
input wire start, // call.valid
output wire busy, // .stall
input wire clock, // clock.clk
input wire resetn, // reset.reset_n
output wire done, // return.valid
input wire stall, // .stall
input wire [63:0] x, // x.data
input wire [63:0] y // y.data
);
avg_internal avg_internal_inst (
.clock (clock), // clock.clk
.resetn (resetn), // reset.reset_n
.start (start), // call.valid
.busy (busy), // .stall
.done (done), // return.valid
.stall (stall), // .stall
.x (x), // x.data
.y (y), // y.data
.avmm_0_rw_address (avmm_0_rw_address), // avmm_0_rw.address
.avmm_0_rw_byteenable(avmm_0_rw_byteenable), // .byteenable
.avmm_0_rw_read (avmm_0_rw_read), // .read
.avmm_0_rw_readdata (avmm_0_rw_readdata), // .readdata
.avmm_0_rw_write (avmm_0_rw_write), // .write
.avmm_0_rw_writedata (avmm_0_rw_writedata) // .writedata
);
endmodule
| 6.843297 |
module tb_axi ();
parameter DATA_WIDTH_SLAVE = 32;
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8;
parameter ADDRESS_WIDTH_SLAVE = 8;
parameter DATA_WIDTH_MASTER = 32;
parameter STROBE_WIDTH_MASTER = DATA_WIDTH_MASTER / 8;
parameter ADDRESS_WIDTH_MASTER = 8;
reg clk_tb;
reg rst_tb;
reg read_tb;
reg write_tb;
integer i = 0;
//generated clk signal
always #5 clk_tb = ~clk_tb;
//test
initial begin
clk_tb = 0;
rst_tb = 1;
//rst
repeat (2) @(posedge clk_tb);
rst_tb = 0;
//10 read -> only if addr%3!=0
repeat (2) @(posedge clk_tb);
repeat (10) begin
if (i % 2 != 0) begin
#50 read_tb = 1;
#20 read_tb = 0;
#50 read_tb = 1;
#20 read_tb = 0;
#50 write_tb = 1;
#20 write_tb = 0;
#50 read_tb = 1;
#20 read_tb = 0;
end else begin
#50 write_tb = 1;
#20 write_tb = 0;
#50 read_tb = 1;
#20 read_tb = 0;
#50 write_tb = 1;
#20 write_tb = 0;
#50 read_tb = 1;
#20 read_tb = 0;
end
i = i + 1;
end
//rst
repeat (2) @(posedge clk_tb);
rst_tb = 1;
repeat (2) @(posedge clk_tb);
rst_tb = 0;
$finish;
end
AxiModule AM0 (
.aclk_axi(clk_tb),
.aresetn_axi(rst_tb),
.read(read_tb),
.write(write_tb)
);
endmodule
| 6.998862 |
module tb_axi4s_add_control_signal ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_axi4s_add_control_signal.vcd");
$dumpvars(0, tb_axi4s_add_control_signal);
#10000000;
$finish;
end
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
parameter RAND_BUSY = 1;
parameter X_WIDTH = 10;
parameter Y_WIDTH = 10;
parameter TUSER_WIDTH = 2;
parameter TDATA_WIDTH = 24;
wire aresetn = ~reset;
wire aclk = clk;
reg aclken = 1;
// reg [X_WIDTH-1:0] param_width = 640;
// reg [Y_WIDTH-1:0] param_height = 480;
reg [ X_WIDTH-1:0] param_width = 64;
reg [ Y_WIDTH-1:0] param_height = 48;
reg [TDATA_WIDTH-1:0] s_axi4s_tdata;
reg s_axi4s_tvalid;
wire s_axi4s_tready;
wire [TUSER_WIDTH-1:0] m_axi4s_tuser;
wire m_axi4s_tlast;
wire [TDATA_WIDTH-1:0] m_axi4s_tdata;
wire m_axi4s_tvalid;
reg m_axi4s_tready = 1;
jelly_axi4s_add_control_signal #(
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH),
.TUSER_WIDTH(TUSER_WIDTH),
.TDATA_WIDTH(TDATA_WIDTH)
) i_axi4s_add_control_signal (
.aresetn(aresetn),
.aclk (aclk),
.aclken (aclken),
.param_width (param_width),
.param_height(param_height),
.s_axi4s_tdata (s_axi4s_tdata),
.s_axi4s_tvalid(s_axi4s_tvalid),
.s_axi4s_tready(s_axi4s_tready),
.m_axi4s_tuser (m_axi4s_tuser),
.m_axi4s_tlast (m_axi4s_tlast),
.m_axi4s_tdata (m_axi4s_tdata),
.m_axi4s_tvalid(m_axi4s_tvalid),
.m_axi4s_tready(m_axi4s_tready)
);
always @(posedge aclk) begin
aclken <= RAND_BUSY ? {$random()} : 1;
end
integer fp;
initial fp = $fopen("out.txt", "w");
always @(posedge aclk) begin
if (~aresetn) begin
s_axi4s_tdata <= 0;
s_axi4s_tvalid <= 0;
end else if (aclken) begin
if (s_axi4s_tvalid && s_axi4s_tready) begin
s_axi4s_tdata <= s_axi4s_tdata + 1;
end
if (!s_axi4s_tvalid || s_axi4s_tready) begin
s_axi4s_tvalid <= RAND_BUSY ? {$random()} : 1;
end
if (m_axi4s_tvalid && m_axi4s_tready) begin
$display("%h %b %b", m_axi4s_tdata, m_axi4s_tuser, m_axi4s_tlast);
$fdisplay(fp, "%h %b %b", m_axi4s_tdata, m_axi4s_tuser, m_axi4s_tlast);
if (m_axi4s_tdata == param_width * param_height * 3) begin
$finish;
end
end
m_axi4s_tready <= RAND_BUSY ? {$random()} : 1;
end
end
endmodule
| 7.743347 |
module tb_AXI4_Lite_Slave_FSM;
// Interface Signals
reg clk;
reg rst; // reset on high
// AXI4-Lite Interface Signals
// Read address channel
reg ARVALID;
wire ARREADY;
// Read data channel
wire RVALID;
reg RREADY;
// Write address channel
reg AWVALID;
wire AWREADY;
// Write data channel
reg WVALID;
wire WREADY;
// Write response channel
wire BVALID;
reg BREADY;
wire [3:0] state_out;
// DUT
AXI4_Lite_Slave_FSM DUT (
.clk(clk),
.rst(rst),
.ARVALID(ARVALID),
.ARREADY(ARREADY),
.RVALID(RVALID),
.RREADY(RREADY),
.AWVALID(AWVALID),
.AWREADY(AWREADY),
.WVALID(WVALID),
.WREADY(WREADY),
.BVALID(BVALID),
.BREADY(BREADY)
);
// Assignments to internal signals
assign state_out = DUT.state;
always #5 clk = ~clk;
initial begin
clk <= 0;
rst <= 0;
ARVALID <= 0;
RREADY <= 0;
AWVALID <= 0;
WVALID <= 0;
BREADY <= 0;
#5;
rst <= 1;
#10;
rst <= 0;
#10;
AWVALID <= 1;
#10;
AWVALID <= 0;
#20;
WVALID <= 1;
#10;
WVALID <= 0;
#20;
BREADY <= 1;
#10;
BREADY <= 0;
#10;
end
endmodule
| 6.611181 |
module tb_axil_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [31:0] M_AXI_AWADDR,
input [ 3:0] M_AXI_AWCACHE,
input [ 2:0] M_AXI_AWPROT,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [1:0] M_AXI_BRESP,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [31:0] M_AXI_ARADDR,
input [ 3:0] M_AXI_ARCACHE,
input [ 2:0] M_AXI_ARPROT,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output [31:0] M_AXI_RDATA,
output reg [ 1:0] M_AXI_RRESP,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BRESP = 0;
M_AXI_RRESP = 0;
M_AXI_ARREADY = 1;
end
// AXI Read
reg axi_rena;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_rena <= 0;
axi_length <= 0;
end else begin
if (M_AXI_RVALID & M_AXI_RREADY) begin
axi_rena <= 0;
end else if (M_AXI_ARVALID) begin
axi_rena <= 1;
end
end
end
assign M_AXI_RDATA = M_AXI_ARADDR;
assign M_AXI_RVALID = axi_rena & M_AXI_RREADY;
// AXI BResponse
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_wvalid <= 0;
end else begin
if (M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
| 8.453533 |
module tb_axi_addr_range ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_axi_addr_range.vcd");
$dumpvars(0, tb_axi_addr_range);
#1000000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
parameter RAND_BUSY = 1;
parameter BYPASS = 0;
parameter USER_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter DATA_SIZE = 3; // 0:8bit, 1:16bit, 2:32bit, 3:64bit, ...
parameter LEN_WIDTH = 24;
parameter S_SLAVE_REGS = 1;
parameter S_MASTER_REGS = 1;
parameter M_SLAVE_REGS = 1;
parameter M_MASTER_REGS = 1;
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
wire aresetn = ~reset;
wire aclk = clk;
reg aclken = 1'b1;
reg [ USER_BITS-1:0] s_user;
reg [ADDR_WIDTH-1:0] s_addr;
reg [ LEN_WIDTH-1:0] s_len;
reg s_valid;
wire s_ready;
wire [ USER_BITS-1:0] m_user;
wire [ADDR_WIDTH-1:0] m_addr;
wire [ LEN_WIDTH-1:0] m_len;
wire m_valid;
reg m_ready = 1'b1;
jelly_axi_addr_range #(
.BYPASS (BYPASS),
.USER_WIDTH (USER_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_SIZE (DATA_SIZE),
.LEN_WIDTH (LEN_WIDTH),
.S_SLAVE_REGS (S_SLAVE_REGS),
.S_MASTER_REGS(S_MASTER_REGS),
.M_SLAVE_REGS (M_SLAVE_REGS),
.M_MASTER_REGS(M_MASTER_REGS)
) i_axi_addr_range (
.aresetn(aresetn),
.aclk (aclk),
.aclken (aclken),
.param_range_start(32'h0001_0000),
.param_range_end (32'h0001_0f30),
.s_user (s_valid ? s_user : {USER_WIDTH{1'bx}}),
.s_addr (s_valid ? s_addr : {ADDR_WIDTH{1'bx}}),
.s_len (s_valid ? s_len : {LEN_WIDTH{1'bx}}),
.s_valid(s_valid),
.s_ready(s_ready),
.m_user (m_user),
.m_addr (m_addr),
.m_len (m_len),
.m_valid(m_valid),
.m_ready(m_ready)
);
always @(posedge aclk) begin
aclken <= RAND_BUSY ? {$random()} : 1;
end
integer fp;
initial fp = $fopen("out.txt", "w");
always @(posedge aclk) begin
if (~aresetn) begin
s_user <= 0;
s_addr <= 32'h0001_0000;
s_len <= 8'hff;
s_valid <= 1'b0;
end else if (aclken) begin
if (s_valid && s_ready) begin
s_user <= s_user + 1;
s_addr <= s_addr + (1 << DATA_SIZE);
end
if (!s_valid || s_ready) begin
s_valid = RAND_BUSY ? {$random()} : 1;
end
if (m_valid && m_ready) begin
$display("%d %h %h", m_user, m_addr, m_len);
$fdisplay(fp, "%d %h %h", m_user, m_addr, m_len);
if (m_user == 4096) begin
$finish;
end
end
m_ready <= RAND_BUSY ? {$random()} : 1;
end
end
endmodule
| 8.14275 |
module tb_axi_lite ();
reg M_AXI_ACLK;
reg M_AXI_ARESETN;
wire [31:0] M_AXI_AWADDR;
wire [ 2:0] M_AXI_AWPROT;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
// Master Interface Write Data
wire [31:0] M_AXI_WDATA;
wire [ 3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
// Master Interface Write Response
wire [ 1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
// Master Interface Read Address
wire [31:0] M_AXI_ARADDR;
wire [ 2:0] M_AXI_ARPROT;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
// Master Interface Read Data
wire [31:0] M_AXI_RDATA;
wire [ 1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
reg start_input_gpio;
axi_lite_master #(
.C_M_AXI_ADDR_WIDTH(32),
.C_M_AXI_DATA_WIDTH(32),
.C_NUM_COMMANDS (16),
.READ_WRITE_ADDR (32'h88000000)
) MASTER (
// System Signals
.M_AXI_ACLK (M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
// Master Interface Write Address
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
// Master Interface Write Data
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
// Master Interface Write Response
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
// Master Interface Read Address
.M_AXI_ARADDR (M_AXI_ARADDR),
.M_AXI_ARPROT (M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
// Master Interface Read Data
.M_AXI_RDATA (M_AXI_RDATA),
.M_AXI_RRESP (M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
//Example Output
.DONE_SUCCESS (),
.start_input_gpio (start_input_gpio),
//Test Ports
.test_awvalid(),
.test_awaddr (),
.test_wdata (),
.test_wvalid (),
.test_bready (),
.test_bvalid (),
.test_rready (),
.test_araddr (),
.test_arvalid(),
.test_rdata (),
.test_rvalid ()
);
axi_lite_final #(
.C_BASEADDR (32'h88000000),
.C_HIGHADDR (32'h880001FF),
.C_S_AXI_MIN_SIZE (32'h000001ff),
.C_S_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_NUM_REG (4)
) SLAVE (
// System Signals
.ACLK (M_AXI_ACLK),
.ARESETN (M_AXI_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (M_AXI_AWADDR),
.S_AXI_AWPROT (M_AXI_AWPROT),
.S_AXI_AWVALID(M_AXI_AWVALID),
.S_AXI_AWREADY(M_AXI_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WDATA (M_AXI_WDATA),
.S_AXI_WSTRB (M_AXI_WSTRB),
.S_AXI_WVALID(M_AXI_WVALID),
.S_AXI_WREADY(M_AXI_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BRESP (M_AXI_BRESP),
.S_AXI_BVALID(M_AXI_BVALID),
.S_AXI_BREADY(M_AXI_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARADDR (M_AXI_ARADDR),
.S_AXI_ARPROT (M_AXI_ARPROT),
.S_AXI_ARVALID(M_AXI_ARVALID),
.S_AXI_ARREADY(M_AXI_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RDATA (M_AXI_RDATA),
.S_AXI_RRESP (M_AXI_RRESP),
.S_AXI_RVALID(M_AXI_RVALID),
.S_AXI_RREADY(M_AXI_RREADY)
);
initial begin
M_AXI_ACLK = 1'b0;
M_AXI_ARESETN = 1'b0;
start_input_gpio = 1'b0;
#500 M_AXI_ARESETN = 1'b1;
start_input_gpio = 1'b1;
#30000 $stop;
end
always #50 M_AXI_ACLK = ~M_AXI_ACLK;
endmodule
| 6.690306 |
module tb_axi_ls_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data Channel
output reg [31:0] S_AXI_WDATA,
output reg [ 3:0] S_AXI_WSTRB,
output reg S_AXI_WVALID,
input S_AXI_WREADY,
// Write Response Channel
input S_AXI_BVALID,
output reg S_AXI_BREADY,
input [1:0] S_AXI_BRESP,
// Read Address Channe
output reg [31:0] S_AXI_ARADDR,
output reg [ 3:0] S_AXI_ARCACHE,
output reg [ 2:0] S_AXI_ARPROT,
output reg S_AXI_ARVALID,
input S_AXI_ARREADY,
// Read Data Channel
input [31:0] S_AXI_RDATA,
input [ 1:0] S_AXI_RRESP,
input S_AXI_RVALID,
output reg S_AXI_RREADY
);
initial begin
S_AXI_AWADDR = 32'h0000_0000;
S_AXI_AWCACHE = 3'd0;
S_AXI_AWPROT = 2'd0;
S_AXI_AWVALID = 1'b0;
S_AXI_WDATA = 32'h0000_0000;
S_AXI_WSTRB = 4'H0;
S_AXI_WVALID = 1'b0;
S_AXI_BREADY = 1'b0;
S_AXI_ARADDR = 32'h0000_0000;
S_AXI_ARCACHE = 3'd0;
S_AXI_ARPROT = 2'd0;
S_AXI_ARVALID = 1'b0;
S_AXI_RREADY = 1'b0;
end
// Write Data
task wrdata;
input [31:0] adrs;
input [31:0] data;
begin
@(negedge ACLK);
S_AXI_AWADDR <= adrs;
S_AXI_AWVALID <= 1'b1;
@(negedge ACLK);
wait (S_AXI_AWREADY);
S_AXI_AWVALID <= 1'b0;
@(negedge ACLK);
S_AXI_WDATA <= data;
S_AXI_WSTRB <= 4'HF;
S_AXI_WVALID <= 1'b1;
wait (S_AXI_WREADY);
@(negedge ACLK);
S_AXI_WVALID <= 1'b0;
@(negedge ACLK);
wait (S_AXI_BVALID);
@(negedge ACLK);
S_AXI_BREADY <= 1'b1;
@(negedge ACLK);
wait (!S_AXI_BVALID);
S_AXI_BREADY <= 1'b0;
@(negedge ACLK);
end
endtask
// Read Data
task rddata;
input [31:0] adrs;
output [31:0] data;
begin
@(negedge ACLK);
S_AXI_ARADDR <= adrs;
S_AXI_ARVALID <= 1'b1;
@(negedge ACLK);
wait (S_AXI_ARREADY);
S_AXI_ARVALID <= 1'b0;
@(negedge ACLK);
S_AXI_RREADY <= 1'b1;
wait (S_AXI_RVALID);
data = S_AXI_RDATA;
$display("AXI Lite Master Read[%08X]: %08X", adrs, S_AXI_RDATA);
@(negedge ACLK);
S_AXI_RREADY <= 1'b0;
wait (!S_AXI_RVALID);
@(negedge ACLK);
end
endtask
endmodule
| 7.834581 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input [ 1:0] M_AXI_AWBURST, // Burst Type: Fixed 2'b01(Incremental Burst)
input M_AXI_AWLOCK, // Lock: Fixed 2'b00
input [ 3:0] M_AXI_AWCACHE, // Cache: Fiex 2'b0011
input [ 2:0] M_AXI_AWPROT, // Protect: Fixed 2'b000
input [ 3:0] M_AXI_AWQOS, // QoS: Fixed 2'b0000
input [ 0:0] M_AXI_AWUSER, // User: Fixed 32'd0
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WLAST,
input [ 0:0] M_AXI_WUSER,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [0:0] M_AXI_BID,
output reg [1:0] M_AXI_BRESP,
output reg [0:0] M_AXI_BUSER,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [ 0:0] M_AXI_ARID,
input [31:0] M_AXI_ARADDR,
input [ 7:0] M_AXI_ARLEN,
input [ 2:0] M_AXI_ARSIZE,
input [ 1:0] M_AXI_ARBURST,
// input [1:0] M_AXI_ARLOCK,
input [ 0:0] M_AXI_ARLOCK,
input [ 3:0] M_AXI_ARCACHE,
input [ 2:0] M_AXI_ARPROT,
input [ 3:0] M_AXI_ARQOS,
input [ 0:0] M_AXI_ARUSER,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output reg [ 0:0] M_AXI_RID,
output [63:0] M_AXI_RDATA,
output reg [ 1:0] M_AXI_RRESP,
output M_AXI_RLAST,
output reg [ 0:0] M_AXI_RUSER,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BID = 0;
M_AXI_BRESP = 0;
M_AXI_BUSER = 0;
//M_AXI_BVALID = 0;
M_AXI_ARREADY = 1;
M_AXI_RID = 0;
//M_AXI_RDATA = 0;
M_AXI_RRESP = 0;
//M_AXI_RLAST = 0;
M_AXI_RUSER = 0;
//M_AXI_RVALID = 0;
end
// AXI Read
reg axi_rena;
reg [31:0] count, rcount;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
count <= 32'd0;
rcount <= 32'd0;
axi_rena <= 0;
axi_length <= 0;
// M_AXI_RVALID<=1'b0;
end else begin
if (M_AXI_RLAST) begin
axi_rena <= 0;
end else if (M_AXI_ARVALID) begin
axi_rena <= 1;
axi_length <= M_AXI_ARLEN;
end
if (axi_rena) begin
count <= count + 32'd1;
end else begin
count <= 0;
end
if (M_AXI_RVALID & M_AXI_RREADY) begin
rcount <= rcount + 32'd1;
end
end
end
assign M_AXI_RDATA = {rcount, rcount};
assign M_AXI_RLAST = (axi_rena & (axi_length == count)) ? 1 : 0;
assign M_AXI_RVALID = axi_rena;
// AXI BResponse
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_wvalid <= 0;
end else begin
if (M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID & M_AXI_WLAST) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
| 7.908944 |
module axis_master_model (
input W_AXIS_TCLK,
output reg [63:0] W_AXIS_TDATA,
output reg W_AXIS_TVALID,
input W_AXIS_TREADY,
output reg [ 7:0] W_AXIS_TSTRB,
output reg W_AXIS_TKEEP,
output reg W_AXIS_TLAST
);
initial begin
W_AXIS_TDATA = 64'd0;
W_AXIS_TVALID = 1'b0;
W_AXIS_TSTRB = 8'd0;
W_AXIS_TKEEP = 1'b0;
W_AXIS_TLAST = 1'b0;
end
task wrdata;
input [63:0] wdata;
input last;
begin
@(posedge W_AXIS_TCLK);
wait (W_AXIS_TREADY);
W_AXIS_TVALID <= 1'b1;
W_AXIS_TDATA <= wdata;
W_AXIS_TLAST <= last;
@(posedge W_AXIS_TCLK);
W_AXIS_TVALID <= 1'b0;
W_AXIS_TDATA <= 64'd0;
W_AXIS_TLAST <= 1'b0;
@(posedge W_AXIS_TCLK);
end
endtask
endmodule
| 7.491749 |
module axis_slave_model (
input R_AXIS_TCLK,
input [63:0] R_AXIS_TDATA,
input R_AXIS_TVALID,
output reg R_AXIS_TREADY,
input [ 7:0] R_AXIS_TSTRB,
input R_AXIS_TKEEP,
input R_AXIS_TLAST
);
initial begin
R_AXIS_TREADY = 1'b0;
end
task rdenable;
begin
@(posedge R_AXIS_TCLK);
R_AXIS_TREADY <= 1'b1;
@(posedge R_AXIS_TCLK);
end
endtask
task rddisable;
begin
@(posedge R_AXIS_TCLK);
R_AXIS_TREADY <= 1'b1;
@(posedge R_AXIS_TCLK);
end
endtask
endmodule
| 7.490526 |
module tb_axi_ls_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data Channel
output reg [31:0] S_AXI_WDATA,
output reg [ 3:0] S_AXI_WSTRB,
output reg S_AXI_WVALID,
input S_AXI_WREADY,
// Write Response Channel
input S_AXI_BVALID,
output reg S_AXI_BREADY,
input [1:0] S_AXI_BRESP,
// Read Address Channe
output reg [31:0] S_AXI_ARADDR,
output reg [ 3:0] S_AXI_ARCACHE,
output reg [ 2:0] S_AXI_ARPROT,
output reg S_AXI_ARVALID,
input S_AXI_ARREADY,
// Read Data Channel
input [31:0] S_AXI_RDATA,
input [ 1:0] S_AXI_RRESP,
input S_AXI_RVALID,
output reg S_AXI_RREADY
);
initial begin
S_AXI_AWADDR = 32'h0000_0000;
S_AXI_AWCACHE = 3'd0;
S_AXI_AWPROT = 2'd0;
S_AXI_AWVALID = 1'b0;
S_AXI_WDATA = 32'h0000_0000;
S_AXI_WSTRB = 4'H0;
S_AXI_WVALID = 1'b0;
S_AXI_BREADY = 1'b0;
S_AXI_ARADDR = 32'h0000_0000;
S_AXI_ARCACHE = 3'd0;
S_AXI_ARPROT = 2'd0;
S_AXI_ARVALID = 1'b0;
S_AXI_RREADY = 1'b0;
end
// Write Data
task wrdata;
input [31:0] adrs;
input [31:0] data;
begin
@(negedge ACLK);
S_AXI_AWADDR <= adrs;
S_AXI_AWVALID <= 1'b1;
@(negedge ACLK);
wait (S_AXI_AWREADY);
S_AXI_AWVALID <= 1'b0;
@(negedge ACLK);
S_AXI_WDATA <= data;
S_AXI_WSTRB <= 4'HF;
S_AXI_WVALID <= 1'b1;
wait (S_AXI_WREADY);
@(negedge ACLK);
S_AXI_WVALID <= 1'b0;
@(negedge ACLK);
wait (S_AXI_BVALID);
@(negedge ACLK);
S_AXI_BREADY <= 1'b1;
@(negedge ACLK);
wait (!S_AXI_BVALID);
S_AXI_BREADY <= 1'b0;
@(negedge ACLK);
end
endtask
// Read Data
task rddata;
input [31:0] adrs;
output [31:0] data;
begin
@(negedge ACLK);
S_AXI_ARADDR <= adrs;
S_AXI_ARVALID <= 1'b1;
@(negedge ACLK);
wait (S_AXI_ARREADY);
S_AXI_ARVALID <= 1'b0;
@(negedge ACLK);
S_AXI_RREADY <= 1'b1;
wait (S_AXI_RVALID);
data = S_AXI_RDATA;
$display("AXI Lite Master Read[%08X]: %08X", adrs, S_AXI_RDATA);
@(negedge ACLK);
S_AXI_RREADY <= 1'b0;
wait (!S_AXI_RVALID);
@(negedge ACLK);
end
endtask
endmodule
| 7.834581 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input [ 1:0] M_AXI_AWBURST, // Burst Type: Fixed 2'b01(Incremental Burst)
input M_AXI_AWLOCK, // Lock: Fixed 2'b00
input [ 3:0] M_AXI_AWCACHE, // Cache: Fiex 2'b0011
input [ 2:0] M_AXI_AWPROT, // Protect: Fixed 2'b000
input [ 3:0] M_AXI_AWQOS, // QoS: Fixed 2'b0000
input [ 0:0] M_AXI_AWUSER, // User: Fixed 32'd0
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WLAST,
input [ 0:0] M_AXI_WUSER,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [0:0] M_AXI_BID,
output reg [1:0] M_AXI_BRESP,
output reg [0:0] M_AXI_BUSER,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [ 0:0] M_AXI_ARID,
input [31:0] M_AXI_ARADDR,
input [ 7:0] M_AXI_ARLEN,
input [ 2:0] M_AXI_ARSIZE,
input [ 1:0] M_AXI_ARBURST,
// input [1:0] M_AXI_ARLOCK,
input [ 0:0] M_AXI_ARLOCK,
input [ 3:0] M_AXI_ARCACHE,
input [ 2:0] M_AXI_ARPROT,
input [ 3:0] M_AXI_ARQOS,
input [ 0:0] M_AXI_ARUSER,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output reg [ 0:0] M_AXI_RID,
output [63:0] M_AXI_RDATA,
output reg [ 1:0] M_AXI_RRESP,
output M_AXI_RLAST,
output reg [ 0:0] M_AXI_RUSER,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BID = 0;
M_AXI_BRESP = 0;
M_AXI_BUSER = 0;
//M_AXI_BVALID = 0;
M_AXI_ARREADY = 1;
M_AXI_RID = 0;
//M_AXI_RDATA = 0;
M_AXI_RRESP = 0;
//M_AXI_RLAST = 0;
M_AXI_RUSER = 0;
//M_AXI_RVALID = 0;
end
// AXI Read
reg axi_rena;
reg [31:0] count, rcount;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
count <= 32'd0;
rcount <= 32'd0;
axi_rena <= 0;
axi_length <= 0;
// M_AXI_RVALID<=1'b0;
end else begin
if (M_AXI_RLAST) begin
axi_rena <= 0;
end else if (M_AXI_ARVALID) begin
axi_rena <= 1;
axi_length <= M_AXI_ARLEN;
end
if (axi_rena) begin
count <= count + 32'd1;
end else begin
count <= 0;
end
if (M_AXI_RVALID & M_AXI_RREADY) begin
rcount <= rcount + 32'd1;
end
end
end
assign M_AXI_RDATA = {rcount, rcount};
assign M_AXI_RLAST = (axi_rena & (axi_length == count)) ? 1 : 0;
assign M_AXI_RVALID = axi_rena;
// AXI BResponse
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_wvalid <= 0;
end else begin
if (M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID & M_AXI_WLAST) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
| 7.908944 |
module axis_master_model (
input W_AXIS_TCLK,
output reg [63:0] W_AXIS_TDATA,
output reg W_AXIS_TVALID,
input W_AXIS_TREADY,
output reg [ 7:0] W_AXIS_TSTRB,
output reg W_AXIS_TKEEP,
output reg W_AXIS_TLAST
);
initial begin
W_AXIS_TDATA = 64'd0;
W_AXIS_TVALID = 1'b0;
W_AXIS_TSTRB = 8'd0;
W_AXIS_TKEEP = 1'b0;
W_AXIS_TLAST = 1'b0;
end
task wrdata;
input [63:0] wdata;
input last;
begin
@(posedge W_AXIS_TCLK);
wait (W_AXIS_TREADY);
W_AXIS_TVALID <= 1'b1;
W_AXIS_TDATA <= wdata;
W_AXIS_TLAST <= last;
@(posedge W_AXIS_TCLK);
W_AXIS_TVALID <= 1'b0;
W_AXIS_TDATA <= 64'd0;
W_AXIS_TLAST <= 1'b0;
@(posedge W_AXIS_TCLK);
end
endtask
endmodule
| 7.491749 |
module axis_slave_model (
input R_AXIS_TCLK,
input [63:0] R_AXIS_TDATA,
input R_AXIS_TVALID,
output reg R_AXIS_TREADY,
input [ 7:0] R_AXIS_TSTRB,
input R_AXIS_TKEEP,
input R_AXIS_TLAST
);
initial begin
R_AXIS_TREADY = 1'b0;
end
task rdenable;
begin
@(posedge R_AXIS_TCLK);
R_AXIS_TREADY <= 1'b1;
@(posedge R_AXIS_TCLK);
end
endtask
task rddisable;
begin
@(posedge R_AXIS_TCLK);
R_AXIS_TREADY <= 1'b1;
@(posedge R_AXIS_TCLK);
end
endtask
endmodule
| 7.490526 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN,
input [ 2:0] M_AXI_AWSIZE,
input [ 1:0] M_AXI_AWBURST,
input M_AXI_AWLOCK,
input [ 3:0] M_AXI_AWCACHE,
input [ 2:0] M_AXI_AWPROT,
input [ 3:0] M_AXI_AWQOS,
input [ 0:0] M_AXI_AWUSER,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WLAST,
input [ 0:0] M_AXI_WUSER,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [0:0] M_AXI_BID,
output reg [1:0] M_AXI_BRESP,
output reg [0:0] M_AXI_BUSER,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [ 0:0] M_AXI_ARID,
input [31:0] M_AXI_ARADDR,
input [ 7:0] M_AXI_ARLEN,
input [ 2:0] M_AXI_ARSIZE,
input [ 1:0] M_AXI_ARBURST,
// input [1:0] M_AXI_ARLOCK,
input [ 0:0] M_AXI_ARLOCK,
input [ 3:0] M_AXI_ARCACHE,
input [ 2:0] M_AXI_ARPROT,
input [ 3:0] M_AXI_ARQOS,
input [ 0:0] M_AXI_ARUSER,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output reg [ 0:0] M_AXI_RID,
output [31:0] M_AXI_RDATA,
output reg [ 1:0] M_AXI_RRESP,
output M_AXI_RLAST,
output reg [ 0:0] M_AXI_RUSER,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BID = 0;
M_AXI_BRESP = 0;
M_AXI_BUSER = 0;
//M_AXI_BVALID = 0;
M_AXI_ARREADY = 1;
M_AXI_RID = 0;
//M_AXI_RDATA = 0;
M_AXI_RRESP = 0;
//M_AXI_RLAST = 0;
M_AXI_RUSER = 0;
//M_AXI_RVALID = 0;
end
// AXI Read
reg axi_rena;
reg [31:0] count, rcount;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
count <= 32'd0;
rcount <= 32'd0;
axi_rena <= 0;
axi_length <= 0;
// M_AXI_RVALID<=1'b0;
end else begin
if (M_AXI_RLAST) begin
axi_rena <= 0;
end else if (M_AXI_ARVALID) begin
axi_rena <= 1;
axi_length <= M_AXI_ARLEN;
end
if (axi_rena) begin
if (M_AXI_RREADY) begin
count <= count + 32'd1;
end
end else begin
count <= 0;
end
if (M_AXI_RVALID & M_AXI_RREADY) begin
rcount <= rcount + 32'd1;
end
end
end
assign M_AXI_RDATA = {rcount};
assign M_AXI_RLAST = (axi_rena & (axi_length == count)) ? 1 : 0;
assign M_AXI_RVALID = axi_rena & M_AXI_RREADY;
// AXI BResponse
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_wvalid <= 0;
end else begin
if (M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID & M_AXI_WLAST) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
| 7.908944 |
module tb_axi_vip ();
// SIZE value for WRITE/READ_BURST transaction
xil_axi_size_t mtestDataSize;
// Burst Type value for WRITE/READ_BURST transaction
xil_axi_burst_t mtestBurstType;
// LOCK value for WRITE/READ_BURST transaction
xil_axi_lock_t mtestLOCK;
bit [31:0] mtestWData1;
bit [31:0] mtestRData;
axi_sim_axi_vip_0_0_mst_t mst_agent;
// xil_axi_resp_t mtestRresp;
// xil_axi_resp_t mtestBresp;
assign mtestDataSize = XIL_AXI_SIZE_4BYTE;
assign mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
assign mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
task WriteReg;
input [31:0] WrAddr;
input [31:0] WrData;
xil_axi_resp_t mtestBresp;
begin
mst_agent.AXI3_WRITE_BURST(2, WrAddr, 0, mtestDataSize, mtestBurstType, mtestLOCK, 3, 0,
WrData, mtestBresp);
end
endtask
task ReadReg;
input [31:0] RdAddr;
output [31:0] RdData;
xil_axi_resp_t [3:0] mtestRresp;
begin
mst_agent.AXI3_READ_BURST(3, RdAddr, 0, mtestDataSize, mtestBurstType, mtestLOCK, 3, 0,
RdData, mtestRresp);
end
endtask
axi_sim DUT ();
initial begin
mst_agent = new("master vip agent", DUT.axi_vip_0.inst.IF);
mst_agent.start_master();
WriteReg(32'hC000_0004, 32'haabb33dd);
WriteReg(32'hC000_0008, 32'haabb44dd);
WriteReg(32'hC000_0010, 32'haabb55dd);
ReadReg(32'hC000_0004, mtestRData);
ReadReg(32'hC000_0008, mtestRData);
ReadReg(32'hC000_0010, mtestRData);
end
axi_sim axi_sim_i ();
endmodule
| 7.92703 |
module tb_b213.v
Test bench for (2,1,3) backward label Viterbi Decoder.
===========================================================================*/
`timescale 1 ns/1 ns
module tb_b213;
`include "params_b213.inc.v"
reg [`n-1:0] Rx_data [0:22];
reg [`n-1:0] Rx;
reg seq_ready;
reg clock;
reg reset;
wire [`k-1:0] Dx;
wire [63:0] HD;
wire sync_error;
wire oe;
integer i;
/*=== Instantiate efficient (2,1,3) decoder ===*/
bVITERBI_213 TB_U2 (.Dx(Dx), .oe(oe), .sync_error(sync_error), .Rx(Rx), .seq_ready(seq_ready), .clock(clock), .reset(reset));
/*=== Create Free Running Clock ===*/
always
begin
#(0.5*`CLOCK_PERIOD);
clock=~clock;
end
/*=== Load Test Vectors ===*/
initial
begin
Rx_data[0] = 2'b00;
Rx_data[1] = 2'b11;
Rx_data[2] = 2'b10;
Rx_data[3] = 2'b10;
Rx_data[4] = 2'b11;
Rx_data[5] = 2'b01;
Rx_data[6] = 2'b10;
Rx_data[7] = 2'b00;
Rx_data[8] = 2'b00;
Rx_data[9] = 2'b01;
Rx_data[10] = 2'b00;
Rx_data[11] = 2'b10;
Rx_data[12] = 2'b11;
Rx_data[13] = 2'b11;
Rx_data[14] = 2'b11;
Rx_data[15] = 2'b10;
Rx_data[16] = 2'b10;
Rx_data[17] = 2'b00;
Rx_data[18] = 2'b00;
Rx_data[19] = 2'b01;
Rx_data[20] = 2'b11;
Rx_data[21] = 2'b11;
Rx_data[22] = 2'b00;
end
/*=== Clock data into the decoder ===*/
initial
begin
clock = 0;
reset = 1; //Apply reset
#`CLOCK_PERIOD reset =0; //Disable reset after one clock period
seq_ready =1;
for (i=0; i<15; i=i+1)
begin
Rx=Rx_data[i];
#(`CLOCK_PERIOD*3);
end
// After 1st Traceback, clock in remaining bits after each traceback
for (i=15; i<33; i=i+1)
begin
Rx=Rx_data[i];
#(`CLOCK_PERIOD*19);
end
seq_ready =0;
end
/*=== Create Simulation Waveforms ===*/
initial
begin
$fsdbDumpfile("verilog.fsdb");// debussy dump format
$fsdbDumpStrength;
$fsdbDumpvars;
end
initial
#17000 $finish;
/*=== Monitor Viterbi Decoder Responses ===*/
initial
$monitor("time=%4g, clock=%b, Rx=%b, we=%b, te=%b, oe=%b, wptr=%h, tptr=%h, min_state=%b, tb_reg=%b,A_in=%h,P_in=%b,plabels=%b,Dx=%b, ns=%b",
$time,
clock,
Rx,
TB_U2.U3.we,
TB_U2.U3.te,
TB_U2.U3.oe,
TB_U2.U3.write_ptr,
TB_U2.U3.trace_ptr,
TB_U2.U3.min_state,
TB_U2.U3.tb_reg,
{TB_U2.U3.A0_in,
TB_U2.U3.A1_in,
TB_U2.U3.A2_in,
TB_U2.U3.A3_in,
TB_U2.U3.A4_in,
TB_U2.U3.A5_in,
TB_U2.U3.A6_in,
TB_U2.U3.A7_in},
{TB_U2.U3.P0_in,
TB_U2.U3.P1_in,
TB_U2.U3.P2_in,
TB_U2.U3.P3_in,
TB_U2.U3.P4_in,
TB_U2.U3.P5_in,
TB_U2.U3.P6_in,
TB_U2.U3.P7_in},
{TB_U2.U3.P0[`T-1],
TB_U2.U3.P1[`T-1],
TB_U2.U3.P2[`T-1],
TB_U2.U3.P3[`T-1],
TB_U2.U3.P4[`T-1],
TB_U2.U3.P5[`T-1],
TB_U2.U3.P6[`T-1],
TB_U2.U3.P7[`T-1]},
TB_U2.U3.Dx,
TB_U2.U3.NEXT_STATE
);
endmodule
| 6.764531 |
module tb_barrel;
reg [15:0] op;
reg [ 3:0] shift_mag;
wire [15:0] result;
BarrelShifter shifter_instance (
op,
shift_mag,
result
);
initial begin
shift_mag = 4'b0001;
op = 16'b0000000000000001;
#10;
shift_mag = 4'b0101;
op = 16'b0000000000000101;
#10;
$stop;
end
endmodule
| 6.923881 |
module tb_barrel_shift_16bit;
reg [15:0] in;
reg [ 3:0] ctrl;
wire [15:0] out;
initial begin
$dumpfile("tb_barrel_shifter.vcd");
$dumpvars(0, tb_barrel_shift_16bit);
end
barrel_shift_16bit bs (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
in = 16'd16385;
ctrl = 4'd0;
#5 in = 16'd16385;
ctrl = 4'd1;
#5 in = 16'd16385;
ctrl = 4'd2;
#5 in = 16'd16385;
ctrl = 4'd3;
#5 in = 16'd16385;
ctrl = 4'd4;
#5 in = 16'd16385;
ctrl = 4'd5;
#5 in = 16'd16385;
ctrl = 4'd6;
#5 in = 16'd16385;
ctrl = 4'd7;
#5 in = 16'd16385;
ctrl = 4'd8;
#5 in = 16'd16385;
ctrl = 4'd9;
#5 in = 16'd16385;
ctrl = 4'd10;
#5 in = 16'd16385;
ctrl = 4'd11;
#5 in = 16'd16385;
ctrl = 4'd12;
#5 in = 16'd16385;
ctrl = 4'd13;
#5 in = 16'd16385;
ctrl = 4'd14;
#5 in = 16'd16385;
ctrl = 4'd15;
end
initial begin
$monitor("Input=%d, Control=%d, Output=%d", in, ctrl, out);
end
endmodule
| 8.352919 |
module tb_barrel_shift_16bit;
reg [15:0] in;
reg [ 3:0] ctrl;
wire [15:0] out;
initial begin
$dumpfile("tb_project.vcd");
$dumpvars(0, tb_barrel_shift_16bit);
end
barrel_shift_16bit bs (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
$display($time, " << Starting the Simulation >>"); //Monitor display
/* in=16'd000; ctrl=4'd0; //no shift
#10 in=16'd128; ctrl=4'd1; //shift by 1 bit
#10 in=16'd128; ctrl=4'd2; //shift 2 bits
#10 in=16'd128; ctrl=4'd4; //shift 4 bits
#10 in=16'd255; ctrl=4'd7; //shift by 7 bits
#10 in=16'd255; ctrl=4'd8; //shift by 8 bits
#10 in=16'd511; ctrl=4'd15;//shift by 15 bits*/
#10 in = 16'd32768;
ctrl = 4'd0; //shift 1 bits;
#10 in = 16'd32768;
ctrl = 4'd1; //shift 2 bits;
#10 in = 16'd32768;
ctrl = 4'd2; //shift 3 bits;
#10 in = 16'd32768;
ctrl = 4'd3; //shift 4 bits;
#10 in = 16'd32768;
ctrl = 4'd4; //shift 5 bits;
#10 in = 16'd32768;
ctrl = 4'd5; //shift 6 bits;
#10 in = 16'd32768;
ctrl = 4'd6; //shift 7 bits;
#10 in = 16'd32768;
ctrl = 4'd7; //shift 8 bits;
#10 in = 16'd32768;
ctrl = 4'd8; //shift 9 bits;
#10 in = 16'd32768;
ctrl = 4'd9; //shift 10 bits;
#10 in = 16'd32768;
ctrl = 4'd10; //shift 11 bits;
#10 in = 16'd32768;
ctrl = 4'd11; //shift 12 bits;
#10 in = 16'd32768;
ctrl = 4'd12; //shift 13 bits;
#10 in = 16'd32768;
ctrl = 4'd13; //shift 14 bits;
#10 in = 16'd32768;
ctrl = 4'd14; //shift 15 bits;
#10 in = 16'd32768;
ctrl = 4'd15; //shift 16 bits;
end
initial begin
$monitor("Input=%d, Control=%d, Output=%d", in, ctrl,
out); // this stament is used for direct display
end
endmodule
| 8.352919 |
module tb_basic ();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD / 2) clk = ~clk;
z1top #(
.IMEM_HEX("firmware.hex")
) DUT (
.CLK100MHZ(clk),
.ck_rst(rst),
.sw ('b0101),
.led(),
.btn('b1010)
);
initial begin
#0;
rst = 0;
$display("[TEST]\tRESET pulled LOW.");
repeat (2) @(posedge clk);
@(negedge clk);
rst = 1;
$display("[TEST]\tRESET pulled HIGH.");
repeat (2000) @(posedge clk);
#1;
$finish();
end
endmodule
| 7.381782 |
module tb_BasicHalfDuplexUart;
// Inputs
reg [7:0] txData;
reg [12:0] clocksPerBit;
reg stopBit2;
reg startTx;
reg ackFlags;
reg clk;
reg nReset;
// Outputs
wire [7:0] rxData;
wire overrunErrorFlag;
wire dataOutReadyFlag;
wire frameErrorFlag;
wire run;
wire rxStartBit;
wire txFull;
wire isTx;
// Bidirs
wire serialLine;
// Instantiate the Unit Under Test (UUT)
BasicHalfDuplexUart uut (
.rxData(rxData),
.overrunErrorFlag(overrunErrorFlag),
.dataOutReadyFlag(dataOutReadyFlag),
.frameErrorFlag(frameErrorFlag),
.run(run),
.rxStartBit(rxStartBit),
.txFull(txFull),
.isTx(isTx),
.serialLine(serialLine),
.txData(txData),
.clocksPerBit(clocksPerBit),
.stopBit2(stopBit2),
.startTx(startTx),
.ackFlags(ackFlags),
.clk(clk),
.nReset(nReset)
);
initial begin
// Initialize Inputs
txData = 0;
clocksPerBit = 0;
stopBit2 = 0;
startTx = 0;
ackFlags = 0;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.8835 |
module tb_basic_gates; // Defining a module
reg A, B; // Defining input ports
wire o_and, o_or, o_nand; // Defining output ports
wire o_nor, o_xor, o_xnor; // Defining output ports
basic_gates basic_gates (
A,
B
); // Calling the main function
initial begin
$dumpfile("basic_gates.vcd");
$dumpvars(0, tb_basic_gates);
#20 // 20ns delay
{A, B} = 2'b00;
#20; // A = 0, B = 0
{A, B} = 2'b01;
#20; // A = 0, B = 1
{A, B} = 2'b10;
#20; // A = 1, B = 0
{A, B} = 2'b11;
#20; // A = 1, B = 1
$display("Test complete");
end
endmodule
| 6.908519 |
module tb_basis ();
genvar i;
generate
for (i = 2; i <= `MAX_M; i = i + 1) begin : FOO
tb_basis_m #(i) test ();
end
endgenerate
endmodule
| 7.49876 |
module tb_baudrate_gen ();
reg clk;
reg rst_n;
reg bps_tx_clk_en;
reg bps_rx_clk_en;
wire bps_tx_clk;
wire bps_rx_clk;
initial begin
clk = 0;
rst_n = 0;
bps_tx_clk_en = 0;
bps_rx_clk_en = 0;
#10 rst_n = 1;
bps_tx_clk_en = 1;
#900 bps_tx_clk_en = 0;
bps_rx_clk_en = 1;
#900 bps_tx_clk_en = 1;
bps_rx_clk_en = 0;
#900 bps_tx_clk_en = 0;
bps_rx_clk_en = 1;
#900 bps_tx_clk_en = 1;
bps_rx_clk_en = 1;
$stop;
end
always #1 clk = ~clk;
baudrate_gen bg (
.I_clk(clk),
.I_rst_n(rst_n),
.I_bps_tx_clk_en(bps_tx_clk_en),
.I_bps_rx_clk_en(bps_rx_clk_en),
.O_bps_tx_clk(bps_tx_clk),
.O_bps_rx_clk(bps_rx_clk)
);
endmodule
| 6.769593 |
module tb_baud_controller;
reg clk, reset;
reg [2:0] reg_baud_select;
wire sample_ENABLE;
initial begin
clk = 1'b1;
#200 reset = 1'b1;
#100 reset = 1'b0;
#1200 reset = 1'b1;
#100 reset = 1'b0;
reg_baud_select = 3'b111;
#5000 reg_baud_select = 3'b110;
#5000 reg_baud_select = 3'b101;
#5000 reg_baud_select = 3'b100;
#10000 reg_baud_select = 3'b011;
#15000 reg_baud_select = 3'b010;
#30000 reg_baud_select = 3'b001;
#60000 reg_baud_select = 3'b000;
end
always #10 clk = ~clk;
baud_controller baud_controllerINSTANCE (
.reset(reset),
.clk(clk),
.baud_select(reg_baud_select),
.sample_ENABLE(sample_ENABLE)
);
endmodule
| 6.663799 |
module tb_bcdToGray_gate;
reg [3:0] In;
wire [3:0] Out;
bcdToGray_df mod (
Out,
In
);
initial begin
$monitor($time, " In=%4b, Out=%4b.", In, Out);
#0 In = 4'b0000;
repeat (9) #10 In = In + 4'b0001;
end
endmodule
| 6.927902 |
module tb_beep ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk; //时钟
reg sys_rst_n; //复位
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//对时钟，复位信号赋初值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#100 sys_rst_n <= 1'b1;
end
//产生时钟信号
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
beep #(
.TIME_500MS(25'd24999), //0.5s计数值
.DO (18'd190), //"哆"音调分频计数值（频率262）
.RE (18'd170), //"来"音调分频计数值（频率294）
.MI (18'd151), //"咪"音调分频计数值（频率330）
.FA (18'd143), //"发"音调分频计数值（频率349）
.SO (18'd127), //"梭"音调分频计数值（频率392）
.LA (18'd113), //"拉"音调分频计数值（频率440）
.XI (18'd101) //"西"音调分频计数值（频率494）
) beep_inst (
.sys_clk (sys_clk), //系统时钟,频率50MHz
.sys_rst_n(sys_rst_n), //系统复位，低有效
.beep(beep) //输出蜂鸣器控制信号
);
endmodule
| 7.32315 |
module pass (
input grant_in,
output grant_out
);
assign grant_out = grant_in;
endmodule
| 9.16988 |
module block (
input grant_in,
output grant_out
);
assign grant_out = 0;
endmodule
| 8.703735 |
module tb_bip_calc_alone;
localparam LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [LEN_CODED_BLOCK-1 : 0] tb_data;
initial begin
tb_clock = 0;
tb_reset = 1;
tb_enable = 0;
#6 tb_reset = 0;
tb_enable = 1;
#1000000 $finish;
end
always #1 tb_clock = ~tb_clock;
bip_calculator #(
.LEN_CODED_BLOCK(LEN_CODED_BLOCK)
) u_bip_calculator (
.i_clock (tb_clock),
.i_reset (tb_reset),
.i_data (tb_data), // data from internal reg. [FIX]
.i_enable (tb_enable),
.i_am_insert(tb_insert),
.o_bip3 (tb_bip3),
.o_bip7 (tb_bip7),
.i_bip (tb_br)
);
endmodule
| 6.758818 |
module tb_bit8_2to1mux;
wire [31:0] out;
reg [31:0] in1, in2;
reg sel;
bit32_2to1mux m1 (
out,
sel,
in1,
in2
);
initial $monitor($time, " in1=%b in2=%b sel=%b out=%b", in1, in2, sel, out);
initial begin
in1 = 32'b10101010_10101010_10101010_10101010;
in2 = 32'b01010101_01010101_01010101_01010101;
sel = 1'b0;
#100 sel = 1'b1;
#1000 $finish;
end
endmodule
| 6.834395 |
module tb_bit32_4to1mux;
wire [31:0] out;
reg [31:0] in1, in2, in3, in4;
reg [1:0] sel;
bit32_4to1mux m1 (
out,
in1,
in2,
in3,
in4,
sel
);
initial
$monitor($time, " in1=%h in2=%h in3=%h in4=%h sel=%b out=%h", in1, in2, in3, in4, sel, out);
initial begin
in1 = 32'b10101010_10101010_10101010_10101010;
in2 = 32'b01010101_01010101_01010101_01010101;
in3 = 32'b10011001_10011001_10011001_10011001;
in4 = 32'b01100110_01100110_01100110_01100110;
sel = 2'b00;
#100 sel = 2'b01;
#100 sel = 2'b10;
#100 sel = 2'b11;
end
endmodule
| 7.162276 |
module tb_bit32_reg;
reg [31:0] d;
reg clk, reset;
wire [31:0] q;
bit32_reg R (
q,
d,
clk,
reset
);
always @(clk) #5 clk <= ~clk;
initial begin
clk = 1'b1;
reset = 1'b0; //reset the register
#20 reset = 1'b1;
#20 d = 32'hAFAFAFAF;
#200 $finish;
end
initial $monitor($time, " d=%h q=%h reset=%b", d, q, reset);
endmodule
| 6.907715 |
module tb_bit8_2to1mux;
wire [7:0] out;
reg [7:0] in1, in2;
reg sel;
bit8_2to1mux m1 (
out,
sel,
in1,
in2
);
initial $monitor($time, " in1=%b in2=%b sel=%b out=%b", in1, in2, sel, out);
initial begin
in1 = 8'b10101010;
in2 = 8'b01010101;
sel = 1'b0;
#100 sel = 1'b1;
#1000 $finish;
end
endmodule
| 6.834395 |
module TB_BitonicNetwork #(
parameter NUM = 16,
W = 16
);
// Inputs
reg [NUM*W-1:0] IN;
// Output
wire [NUM*W-1:0] OUT;
// Instantiate the Bitonic Network
BitonicNetwork #(NUM, W) BN (
.direction(1'b0),
.IN(IN),
.OUT(OUT)
);
// 500MHz frequency
//initial begin
// clk <= 1'b1;
// forever #1 clk <= ~clk;
//end
initial begin
forever begin
IN = {8{$random}};
#10;
end
end
endmodule
| 6.589523 |
module tb_bitserial ();
reg [7:0] A, W;
reg clk, rstn, en;
reg [ 1:0] Precision;
wire [ 2:0] count;
wire [15:0] PRODUCT;
wire [19:0] ACCUM;
wire [15:4] PRODUCT4b = PRODUCT[15:4];
wire [19:4] ACC4b = ACCUM[19:4];
wire [15:6] PRODUCT2b = PRODUCT[15:6];
wire [19:6] ACC2b = ACCUM[19:6];
MAC_Unit MAC (
A,
W,
clk,
rstn,
en,
Precision,
count,
PRODUCT,
ACCUM
);
initial begin
#0 clk = 0;
rstn = 0;
en = 0;
Precision = 2'b00;
A = 0;
W = 0;
#10 rstn = 1;
#5 A = 8'b01100111;
W = 8'b00001010;
#5 en = 1;
#75 A = 8'b00111111;
W = 8'b11100001;
#80 A = 8'b10110100;
W = 8'b01000000;
#80 A = 8'b10101001;
W = 8'b10110101;
#80 A = 8'b10000000;
W = 8'b10000000;
#95 en = 0;
rstn = 0;
Precision = 2'b01;
A = 0;
W = 0;
#10 rstn = 1;
A = 8'b01111011;
W = 8'b0100_1000;
#10 en = 1;
#75 A = 8'b10011000;
W = 8'b01111011;
#95 en = 0;
rstn = 0;
Precision = 2'b10;
A = 0;
W = 0;
#10 rstn = 1;
A = 8'b01011100;
W = 8'b01_00_11_10;
#10 en = 1;
#75 A = 8'b11010001;
W = 8'b10_00_11_01;
#95 en = 0;
end
always #5 clk = ~clk;
endmodule
| 6.6439 |
module tb_bit_encoder ();
localparam RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_bit_encoder.vcd");
$dumpvars(1, tb_bit_encoder);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
parameter DATA_WIDTH = 24;
parameter SEL_WIDTH = DATA_WIDTH < 2 ? 1 :
DATA_WIDTH < 4 ? 2 :
DATA_WIDTH < 8 ? 3 :
DATA_WIDTH < 16 ? 4 :
DATA_WIDTH < 32 ? 5 :
DATA_WIDTH < 64 ? 6 :
DATA_WIDTH < 128 ? 7 :
DATA_WIDTH < 256 ? 8 :
DATA_WIDTH < 512 ? 9 :
DATA_WIDTH < 1024 ? 10 :
DATA_WIDTH < 2048 ? 11 :
DATA_WIDTH < 4096 ? 12 :
DATA_WIDTH < 8192 ? 13 :
DATA_WIDTH < 16384 ? 14 :
DATA_WIDTH < 32768 ? 15 : 16;
reg [DATA_WIDTH-1:0] in_data = 1;
wire [ SEL_WIDTH-1:0] out_sel_onehot;
wire [ SEL_WIDTH-1:0] out_sel_msb;
wire [ SEL_WIDTH-1:0] out_sel_lsb;
always @(posedge clk) begin
in_data <= {in_data[DATA_WIDTH-2:0], in_data[DATA_WIDTH-1]};
end
jelly_bit_encoder #(
.DATA_WIDTH(DATA_WIDTH),
.PRIORITYT (0),
.LSB_FIRST (0)
) i_bit_encoder_onehot (
.in_data(in_data),
.out_sel(out_sel_onehot)
);
jelly_bit_encoder #(
.DATA_WIDTH(DATA_WIDTH),
.PRIORITYT (1),
.LSB_FIRST (0)
) i_bit_encoder_msb (
.in_data(in_data),
.out_sel(out_sel_msb)
);
jelly_bit_encoder #(
.DATA_WIDTH(DATA_WIDTH),
.PRIORITYT (1),
.LSB_FIRST (1)
) i_bit_encoder_lsb (
.in_data(in_data),
.out_sel(out_sel_lsb)
);
endmodule
| 6.766054 |
module tb_blink ();
reg clk, reset;
reg en;
wire blink;
blink #(
.DVSR(5)
) tb_blink (
.clk(clk),
.reset(reset),
.en(en),
.blink(blink)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
end
initial begin
reset = 1'b1;
en = 1'b0;
#(1.3 * T);
reset = 1'b0;
#(T);
en = 1'b1;
end
endmodule
| 6.517853 |
module tb_blocking ();
wire [1:0] out;
reg sys_clk;
reg sys_rst_n;
reg [1:0] in;
//初始化系统时钟、全局复位和输入信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//in:产生输入随机数，模拟按键的输入情况
always #20
in <= {$random} % 4; //取模求余数，产生非负随机数0、1，每隔20ns产生一次随机数
//------------------------ blocking_inst ------------------------
blocking blocking_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.in (in), //input [1:0] in
.out(out) //output [1:0] out
);
endmodule
| 7.795335 |
module tb_blocking_caveat;
// Inputs
reg a, b, c;
// Output
wire d;
// Instantiate the Unit Under Test (UUT)
blocking_caveat uut (
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
$dumpfile("tb_blocking_caveat.vcd");
$dumpvars(0, tb_blocking_caveat);
// Initialize Inputs
a = 0;
b = 0;
c = 0;
#3000 $finish;
end
always #10 a = ~a;
always #100 c = ~c;
always #50 b = ~b;
endmodule
| 6.934426 |
module tb_blocking_caveat_net;
// Inputs
reg a, b, c;
// Output
wire d;
// Instantiate the Unit Under Test (UUT)
blocking_caveat uut (
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
$dumpfile("tb_blocking_caveat_net.vcd");
$dumpvars(0, tb_blocking_caveat_net);
// Initialize Inputs
a = 0;
b = 0;
c = 0;
#3000 $finish;
end
always #10 a = ~a;
always #100 c = ~c;
always #50 b = ~b;
endmodule
| 6.934426 |
module tb_block_value ();
reg sys_clock;
reg sys_rst_n;
reg [1:0] in;
wire [1:0] out;
initial begin
sys_clock <= 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
always #10 sys_clock = ~sys_clock;
always #20 in <= {$random} % 4;
block_value block_value_inst (
.sys_clock(sys_clock),
.sys_rst_n(sys_rst_n),
.in (in),
.out (out)
);
endmodule
| 6.631346 |
module tb_BMPTST_3FRM ();
reg clk, rst;
wire VSYNC, HSYNC;
reg SYNC_HLD;
wire [31:0] READ_DATA;
reg FRM1, FRM2, FRM3;
parameter STEP = 10;
parameter DLY = 0.1;
COMM_VH #(
.FRM(3),
.H_WIDTH(2448),
.V_WIDTH(2048)
) COMM_VH (
.clk(clk),
.rst(rst),
.enable(~rst),
.VSYNC(VSYNC),
.HSYNC(HSYNC)
);
/* FRM */
BMP_MOD_SEQCNT_FRM3 #(
.BMP_RD_FILE ("in.bmp"),
.BMP_WR_FILE_FRM1("out_frm1.bmp"),
.BMP_WR_FILE_FRM2("out_frm2.bmp"),
.BMP_WR_FILE_FRM3("out_frm3.bmp")
) BMP_MOD_SEQCNT_FRM3 (
.CLK(clk),
.RE(VSYNC & HSYNC),
.RDATA(READ_DATA[31:0]),
.WE(SYNC_HLD),
.WDATA(READ_DATA[31:0])
);
initial begin
clk = 1;
forever #(STEP / 2) clk = ~clk;
end
initial begin
rst = 1;
#0.1 //psd dly
#(STEP * 20);
rst = 0;
#(STEP * 2500 * 2170 * 3);
$finish();
end
always @(posedge clk) begin
if (rst == 1) begin
SYNC_HLD <= #DLY 1'd0;
end else begin
SYNC_HLD <= #DLY VSYNC & HSYNC;
end
end
endmodule
| 6.854431 |
module tb_booth8x8;
reg clk, start;
reg [7:0] a, b;
wire [15:0] ab;
wire busy;
booth_8x8 multiplier1 (
ab,
busy,
a,
b,
clk,
start
);
initial begin
clk = 0;
$display("first example: a = 3 b = 17");
a = 3;
b = 17;
start = 1;
#50 start = 0;
#80 $display("first example done");
$display("second example: a = 7 b = 7");
a = 7;
b = 7;
start = 1;
#50 start = 0;
#80 $display("second example done");
$finish;
end
always #5 clk = !clk;
always @(posedge clk) $strobe("ab: %d busy: %d at time=%t", ab, busy, $stime);
endmodule
| 6.591773 |
module vp_tty (
input PIN_nIN,
input PIN_nOUT,
input PIN_nSET,
output PIN_ERR,
output PIN_DONE,
output PIN_TR,
output PIN_nAO_A,
output PIN_nAC_A,
output PIN_nSC_S,
output PIN_nSO_S,
input PIN_nAC_S,
input PIN_nSC_A
);
wire nIN, nOUT, nSET;
reg ERR, DONE, TR;
wire nAC_S, nSC_A;
reg nAO_A, nAC_A, nSC_S, nSO_S;
assign nIN = PIN_nIN;
assign nOUT = PIN_nOUT;
assign nSET = PIN_nSET;
assign PIN_ERR = ERR;
assign PIN_DONE = DONE;
assign PIN_TR = TR;
assign nAC_S = PIN_nAC_S;
assign nSC_A = PIN_nSC_A;
assign PIN_nAO_A = nAO_A;
assign PIN_nAC_A = nAC_A;
assign PIN_nSC_S = nSC_S;
assign PIN_nSO_S = nSO_S;
initial begin
ERR = 1'b1;
DONE = 1'b1;
TR = 1'b1;
nAO_A = 1'b1;
nAC_A = 1'b1;
nSC_S = 1'b1;
nSO_S = 1'b1;
end
always @(negedge nSET) begin
nAO_A = 1'b0;
nAC_A = 1'b0;
nSO_S = 1'b0;
ERR = 1'b0;
DONE = 1'b0;
end
always @(negedge nSC_A) begin
#`SIM_HDELAY nAC_A = 1'b1;
TR = 0;
end
always @(posedge nSC_A) begin
#`SIM_HDELAY nAC_A = 1'b0;
TR = 1;
end
always @(negedge nAC_S) begin
#`SIM_HDELAY nSC_S = 1'b0;
end
always @(posedge nAC_S) begin
#`SIM_HDELAY nSC_S = 1'b1;
end
endmodule
| 6.598851 |
module tb_bram;
parameter RAM_WIDTH = 32;
parameter RAM_ADDR_BITS = 9;
reg clk;
reg ram_enable;
reg write_enable;
reg [RAM_ADDR_BITS-1:0] address;
reg [ RAM_WIDTH-1:0] input_data;
wire [ RAM_WIDTH-1:0] output_data;
bram #(
.RAM_WIDTH (RAM_WIDTH),
.RAM_ADDR_BITS (RAM_ADDR_BITS),
.INIT_START_ADDR(0),
.INIT_END_ADDR (10)
) bram_inst (
.clock (clk),
.ram_enable (ram_enable),
.write_enable(write_enable),
.address (address),
.input_data (input_data),
.output_data (output_data)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, tb_bram);
ram_enable = 1;
write_enable = 0;
address = 0;
input_data = 0;
repeat (2) @(posedge clk);
$display("Writing data in BRAM");
#1 write_enable = 1;
for (address = 0; address < 20; address = address + 1) begin
input_data = address * 10;
@(posedge clk);
#1;
end
write_enable = 0;
begin
#50;
end
$display("Reading data from BRAM");
repeat (2) @(posedge clk);
for (address = 0; address < 20; address = address + 1) begin
@(posedge clk);
#1 $display("ADDR: %d, DATA: %d", address, output_data);
end
repeat (2) @(posedge clk);
$finish;
end
endmodule
| 6.894833 |
module tb_breath_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************/
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------------- breath_led_inst --------------------
breath_led #(
.CNT_1US_MAX(6'd4),
.CNT_1MS_MAX(10'd9),
.CNT_1S_MAX (10'd9)
) breath_led_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.led_out(led_out) //output led_out
);
endmodule
| 6.872678 |
module : tb_BSRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_BSRAM ();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
task print_signal_values;
begin
$display("Simulation time: %0t", $time);
$display("Read: %b", readEnable);
$display("Read address: %h", readAddress);
$display("Read data: %h", readData);
$display("Write: %h", writeEnable);
$display("Write address: %b", writeAddress);
$display("Write data: %b", writeData);
end
endtask
reg clock;
reg reset;
reg readEnable;
reg [ADDR_WIDTH-1:0] readAddress;
wire [DATA_WIDTH-1:0] readData;
reg [ADDR_WIDTH-1:0] writeAddress;
reg [DATA_WIDTH-1:0] writeData;
reg writeEnable;
reg scan;
integer i;
BSRAM #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) DUT (
.clock(clock),
.reset(reset),
.readEnable(readEnable),
.readAddress(readAddress),
.readData(readData),
.writeEnable(writeEnable),
.writeAddress(writeAddress),
.writeData(writeData),
.scan(scan)
);
always
#1 clock = ~clock;
initial begin
clock <= 0;
reset <= 1;
scan <= 0;
@(posedge clock)begin
readAddress <= 0;
readEnable <= 0;
end
@(posedge clock)begin
writeAddress = 0;
writeData = 0;
writeEnable = 0;
end
@(posedge clock)begin
reset = 0;
DUT.sram[2] = 32'hAAAA8888;
DUT.sram[4] = 32'h11110000;
end
repeat (1) @ (posedge clock);
@(posedge clock)begin
readAddress = 2;
readEnable = 1;
end
wait(readData == 32'hAAAA8888);
@(posedge clock)begin
writeAddress = 2;
writeData = 100;
writeEnable = 1;
end
@(posedge clock)begin
writeEnable = 0;
readAddress = 2;
readEnable = 1;
readEnable = 0;
end
wait(readData == 32'd100);
@(posedge clock)begin
readAddress = 4;
readEnable = 1;
end
wait(readData == 32'h11110000);
$display("\ntb_BSRAM --> Test Passed!\n\n");
$stop;
end
initial begin
#100;
$display("TEST FAILED.");
$display("\ntb_BSRAM --> Test Failed!\n\n");
$stop;
end
endmodule
| 7.084562 |
module : tb_BSRAM_byte_en
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_BSRAM_byte_en();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
task print_signal_values;
begin
$display("Simulation time: %0t", $time);
$display("Read: %b", readEnable);
$display("Read address: %h", readAddress);
$display("Read data: %h", readData);
$display("Write: %h", writeEnable);
$display("Write Byte: %h", writeByteEnable);
$display("Write address: %b", writeAddress);
$display("Write data: %b", writeData);
end
endtask
reg clock;
reg reset;
reg readEnable;
reg [ADDR_WIDTH-1:0] readAddress;
wire [DATA_WIDTH-1:0] readData;
reg [ADDR_WIDTH-1:0] writeAddress;
reg [DATA_WIDTH-1:0] writeData;
reg writeEnable;
reg [DATA_WIDTH/8-1:0] writeByteEnable;
reg scan;
integer i;
BSRAM_byte_en #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) DUT (
.clock(clock),
.reset(reset),
.readEnable(readEnable),
.readAddress(readAddress),
.readData(readData),
.writeEnable(writeEnable),
.writeByteEnable(writeByteEnable),
.writeAddress(writeAddress),
.writeData(writeData),
.scan(scan)
);
always #5 clock = ~clock;
initial begin
clock <= 0;
reset <= 1;
scan <= 0;
@(posedge clock)begin
readAddress <= 0;
readEnable <= 0;
end
@(posedge clock)begin
writeAddress = 2;
writeData = 32'hAAAA8888;
writeEnable = 1;
writeByteEnable = 4'b1111;
end
@(posedge clock)begin
writeAddress = 4;
writeData = 32'h11110000;
writeEnable = 1;
writeByteEnable = 4'b1111;
end
@(posedge clock)begin
writeAddress = 0;
writeData = 0;
writeEnable = 0;
writeByteEnable = 4'b0000;
end
repeat (1) @ (posedge clock);
@(posedge clock)begin
readAddress = 2;
readEnable = 1;
end
wait(readData == 32'hAAAA8888);
@(posedge clock)begin
writeAddress = 2;
writeData = 100;
writeEnable = 1;
writeByteEnable = 4'b0011;
end
@(posedge clock)begin
writeEnable = 0;
readAddress = 2;
readEnable = 1;
end
wait(readData == 32'hAAAA0064);
@(posedge clock)begin
readAddress = 4;
readEnable = 1;
end
wait(readData == 32'h11110000);
$display("\ntb_BSRAM_byte_en --> Test Passed!\n\n");
$stop;
end
initial begin
#100;
$display("\ntb_BSRAM_byte_en --> Test Failed!\n\n");
$stop;
end
endmodule
| 7.336435 |
module bubble4_tb ();
// Signal Declarations
reg [3:0] in0, in1, in2, in3; // Inputs
wire [3:0] out0, out1, out2, out3; // Outputs
// Unit Under Test Instantiation
bubble4 UUT (
.in0 (in0),
.in1 (in1),
.in2 (in2),
.in3 (in3),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
);
initial begin
in3 = 4'b0000;
in2 = 4'b0001;
in1 = 4'b0010;
in0 = 4'b1111;
#10
// Print Current
$display(
"in0 = %4b in1 = %4b in2 = %4b in3 = %4b", in0, in1, in2, in3
);
$display("out0 = %4b out1 = %4b out2 = %4b out3 = %4b", out0, out1, out2, out3);
// Automatically stop testbench execution
$stop;
end
endmodule
| 6.767651 |
module tb_bus;
reg clk, reset_n, tb_M0_req, tb_M1_req, tb_M0_wr, tb_M1_wr; // 6 reg
reg [7:0] tb_M0_address, tb_M1_address; // 8bits 2 reg
reg [31:0] tb_M0_dout, tb_M1_dout, tb_S0_dout, tb_S1_dout; // 32bits 4 reg
wire tb_M0_grant, tb_M1_grant, tb_S0_sel, tb_S1_sel, tb_S_wr; // 5 wire
wire [7:0] tb_S_address; // 8bits wire
wire [31:0] tb_S_din, tb_M_din; // 32bits 2 wire
// instance by using bus
bus U0_bus (
.clk(clk),
.reset_n(reset_n),
.M0_req(tb_M0_req),
.M1_req(tb_M1_req),
.M0_wr(tb_M0_wr),
.M1_wr(tb_M1_wr),
.M0_address(tb_M0_address),
.M1_address(tb_M1_address),
.M0_dout(tb_M0_dout),
.M1_dout(tb_M1_dout),
.S0_dout(tb_S0_dout),
.S1_dout(tb_S1_dout),
.M0_grant(tb_M0_grant),
.M1_grant(tb_M1_grant),
.M_din(tb_M_din),
.S0_sel(tb_S0_sel),
.S1_sel(tb_S1_sel),
.S_wr(tb_S_wr),
.S_address(tb_S_address),
.S_din(tb_S_din)
);
// values in bus module put testbench values by one to one
always begin
clk = 0;
#5;
clk = 1;
#5; // every 5ns, invert clk
end
initial begin
reset_n = 0;
tb_M0_req = 0;
tb_M1_req = 0;
tb_M0_wr = 0;
tb_M1_wr = 0; // initialization
tb_M0_address = 8'b0;
tb_M1_address = 8'b0;
tb_M0_dout = 32'b0;
tb_M1_dout = 32'b0;
tb_S0_dout = 32'b0;
tb_S1_dout = 32'b0;
#10;
reset_n = 1;
tb_M0_req = 1;
tb_M0_wr = 1;
tb_M0_address = 8'h01;
tb_M0_dout = 32'h11111111; // then, every 10 ns, input values and check output
tb_S0_dout = 32'h01;
tb_S1_dout = 32'h02;
#10;
tb_M0_address = 8'h10;
tb_M0_dout = 32'h22222222;
#10;
tb_M0_address = 8'h25;
tb_M0_dout = 32'h33333333;
#10;
tb_M0_address = 8'h41;
tb_M0_dout = 32'h44444444;
#10;
tb_M0_req = 0;
tb_M1_req = 1;
tb_M1_wr = 1;
#10; // order from m1 grant
tb_M1_address = 8'h8;
tb_M1_dout = 32'h55555555;
#10;
tb_M1_address = 8'h21;
tb_M1_dout = 32'h66666666;
#10;
tb_M0_req = 1;
tb_M1_req = 0;
#10; // order from m0 grant
tb_M0_address = 8'h31;
tb_M0_dout = 32'h77777777;
#10;
tb_M0_address = 8'h43;
tb_M0_dout = 32'h88888888;
#10;
tb_M0_req = 0;
tb_M1_req = 1;
tb_M1_address = 8'h30;
tb_M1_dout = 32'h99999999;
#10; // otder from m1 grant
$stop;
end
endmodule
| 6.699324 |
module tb_busAddressTranslator ();
reg [31:0] virtual_addr;
wire [31:0] phys_addr;
wire [ 7:0] device_en;
BusAddressTranslator bat (
.virtual_addr(virtual_addr),
.phys_addr(phys_addr),
.device_en(device_en)
);
always begin
virtual_addr <= 32'h00000020;
#5 virtual_addr <= 32'h008000A0;
#5 virtual_addr <= 32'h01000009;
#5 virtual_addr <= 32'h0100001C;
#5 virtual_addr <= 32'h00000027;
end
endmodule
| 7.143223 |
module tb_busmux (
sel,
din,
dout
);
parameter BUS_COUNT = 2; // Number of input buses.
parameter MUX_WIDTH = 3; // Bit width of data buses.
parameter SEL_WIDTH = 1; // Width of select line.
input [SEL_WIDTH-1:0] sel; // Select signal.
input [MUX_WIDTH*BUS_COUNT-1:0] din; // Concatenated input buses.
wire [MUX_WIDTH*BUS_COUNT-1:0] din;
output [MUX_WIDTH-1:0] dout; // Output data bus.
reg [MUX_WIDTH-1:0] dout;
reg [BUS_COUNT-1:0] sel_oh; // One-hot select signals.
// Create one hot version of sel input.
// Used as select line for the mux.
always @(sel) begin : sel_oh_PROC
integer busnum;
sel_oh = {BUS_COUNT{1'b0}};
for (busnum = 0; busnum <= (BUS_COUNT - 1); busnum = busnum + 1) begin
if (sel == busnum) sel_oh[busnum] = 1'b1;
end
end
// One of the subtleties that might not be obvious that makes
// this work so well is the use of the blocking assignment (=)
// that allows dout to be built up incrementally.
// The one-hot select builds up into the wide "or" function
// you'd code by hand.
always @(sel_oh or din) begin : mux_logic
integer i, j;
dout = {MUX_WIDTH{1'b0}};
for (i = 0; i <= (BUS_COUNT - 1); i = i + 1) begin
for (j = 0; j <= (MUX_WIDTH - 1); j = j + 1) begin
dout[j] = dout[j] | din[MUX_WIDTH*i+j] & sel_oh[i];
end
end
end // always
`ifdef PARAM_VARS_PROC
// -------------------------------------------------------
// Initial block added to declare and connect variables
// to hold all parameters in this module for easy viewing
// during debug in a wave viewer.
// -------------------------------------------------------
// synopsys translate_off
// VCS coverage off
initial begin : param_vars_PROC
integer BUS_COUNT_param;
integer MUX_WIDTH_param;
integer SEL_WIDTH_param;
BUS_COUNT_param = BUS_COUNT;
MUX_WIDTH_param = MUX_WIDTH;
SEL_WIDTH_param = SEL_WIDTH;
end // param_vars_PROC
// VCS coverage on
// synopsys translate_on
`endif // PARAM_VARS_PROC
endmodule
| 7.97646 |
module would be able to mux three 12-bit buses, or
// seven 5-bit buses, or any other combination,
// depending on the parameter values used when the
// module is instantiated.
//
*/
module tb_busmux_ohsel ( sel, din, dout );
parameter bus_count = 2; // number of input buses
parameter mux_width = 3; // bit width of data buses
input [bus_count-1:0] sel; // one-hot select signals
input [mux_width*bus_count-1:0] din; // concatenated input buses
output [mux_width-1:0] dout; // output data bus
wire [bus_count-1:0] sel; // one-hot select signals
wire [mux_width*bus_count-1:0] din; // concatenated input buses
reg [mux_width-1:0] dout; // output data bus
// One of the subtleties that might not be obvious that makes this work so well
// is the use of the blocking assignment (=) that allows dout to be built up
// incrementally. The one-hot select builds up into the wide "or" function
// you'd code by hand.
always @ (sel or din) begin : mux_logic
integer i, j;
dout = {mux_width{1'b0}};
for (i = 0; i <= (bus_count-1); i = i + 1) begin
for (j = 0; j <= (mux_width-1); j = j + 1) begin
dout[j] = dout[j] | din[mux_width*i +j]&sel[i];
end
end
end // always
endmodule
| 8.634706 |
module tb_button_debounce;
parameter CLK_FREQ = 1_000;
parameter DEBOUNCE_HZ = 40;
reg clk;
reg rst_n;
reg btn_in;
wire btn_out;
button_debounce #(
.CLK_FREQ(CLK_FREQ),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
) _button_debounce (
.clk (clk),
.rst_n (rst_n),
.btn_in (btn_in),
.btn_out(btn_out)
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_button_debounce.vcd");
$dumpvars(0, tb_button_debounce);
#1 rst_n = 1'bx;
clk = 1'bx;
btn_in = 1'bx;
#(CLK_PERIOD) rst_n = 1;
#(CLK_PERIOD) rst_n = 0;
clk = 0;
#(CLK_PERIOD) rst_n = 1;
#(CLK_PERIOD) btn_in = 0;
#(CLK_PERIOD * 50);
$finish(2);
end
always begin
#(CLK_PERIOD * 10) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
#(CLK_PERIOD / 100) btn_in = ~btn_in;
end
endmodule
| 7.63017 |
module
`timescale 1ns/1ns
module tb_button_shaper();
reg clk,rst,Btt_in;
wire Btt_out;
button_shaper DUT_button_shaper_1(clk,rst,Btt_in,Btt_out);
initial begin
clk=0;
rst=1;
Btt_in=0;
end
always begin
#10 clk=1;
#10 clk=0;
end
initial begin
//Begins in Initial State
#15 Btt_in=1;//Pushes to the Pulse State
#40 // Pushes to Wait State
#40 Btt_in=0;//Pushes to Initial State
#80 Btt_in=1;//Pushes to the Pulse State
#120 Btt_in=0;
end
endmodule
| 6.608387 |
module tb_bu_ndiag ();
reg [31:0] data_b_accum;
reg [31:0] dataa_mul;
reg clk, clk_en, aclr;
reg data_in_flag;
wire data_available;
wire zero, overflow, underflow;
wire [31:0] result;
localparam dly = 20000;
bu_ndiag a0 (
.data_available(data_available),
.zero(zero),
.overflow(overflow),
.underflow(underflow),
.result(result),
.data_b_accum(data_b_accum),
.dataa_mul(dataa_mul),
.clock(clk),
.clk_en(clk_en),
.aclr(aclr),
.data_in_flag(data_in_flag)
);
initial begin
clk = 0;
forever begin
#10000 clk = ~clk;
end
end
initial begin
$display("reset high");
aclr <= 1'b1;
#50000;
data_b_accum <= 32'b0;
dataa_mul <= 32'b0;
clk_en <= 1'b0;
data_in_flag <= 1'b0;
$display("reset low");
aclr <= 1'b0;
clk_en <= 1'b0;
#55000;
write_data(32'h40000000);
write_data_noflag(32'h00000000);
#150000 write_data(32'h40000000);
write_data(32'h40400000);
write_data(32'h40800000);
write_data(32'h40a00000);
write_data_noflag(32'h40c00000);
write_data_noflag(32'h40e00000);
write_data(32'h41000000);
write_data(32'h41100000);
#100000 write_data(32'h00000000);
/*
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
write_data_acumm(32'h40000000);
#100000*/
aclr <= 1'b0;
#500000;
$display("Successful completion. All transfers passed");
//$finish;
$stop;
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
task write_data;
input [31:0] data;
begin
#dly;
data_b_accum <= 32'b0;
dataa_mul <= data;
clk_en <= 1'b1;
data_in_flag <= 1'b1;
end
endtask
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
task write_data_noflag;
input [31:0] data;
begin
#dly data_b_accum <= 32'b0;
clk_en <= 1'b1;
dataa_mul <= data;
data_in_flag <= 1'b0;
end
endtask
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
task write_data_acumm;
input [31:0] data;
begin
#dly data_b_accum <= result;
dataa_mul <= data;
data_in_flag <= 1'b0;
end
endtask
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
localparam CLK_SPEED = 2; // IF clk = 122.88Mhz = 8.14nS, For half of clock, CLK_SPEED = 8.14nS/2 = 4.07nS
/*
always
#5 clk= ~clk; */
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule
| 6.520445 |
module tb_b_reg;
reg Rst;
reg Clk;
reg [5:0] b_sel;
reg LE_sel;
reg [7:0] Selector;
wire [7:0] Rx;
wire [7:0] Ry;
b_reg uut (
.Rst(Rst),
.Clk(Clk),
.b_sel(b_sel),
.LE_sel(LE_sel),
.Selector(Selector),
.Rx(Rx),
.Ry(Ry)
);
initial begin
Rst = 1;
Clk = 0;
b_sel = 0;
LE_sel = 0;
Selector = 0;
#2 Rst = 0;
b_sel = 6'b000_000;
LE_sel = 0;
LE_sel = 8'b00000000;
#2 b_sel = 6'b000000;
LE_sel = 1;
Selector = 8'b00000001;
#2 b_sel = 6'b000001;
LE_sel = 1;
Selector = 8'b00000010;
#2 b_sel = 6'b000010;
LE_sel = 1;
Selector = 8'b00000011;
#2 b_sel = 6'b000011;
LE_sel = 1;
Selector = 8'b00000100;
#2 b_sel = 6'b000100;
LE_sel = 1;
Selector = 8'b00000101;
#2 b_sel = 6'b000101;
LE_sel = 1;
Selector = 8'b00000110;
#2 b_sel = 6'b000110;
LE_sel = 1;
Selector = 8'b00000111;
#2 b_sel = 6'b000111;
LE_sel = 1;
Selector = 8'b00001000;
#2 b_sel = 6'b001000;
LE_sel = 0;
#2 b_sel = 6'b011010;
LE_sel = 0;
#2 b_sel = 6'b101100;
LE_sel = 0;
#2 b_sel = 6'b111110;
LE_sel = 0;
end
always #1 Clk = !Clk;
endmodule
| 6.53187 |
module tb_cache_tag_full ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_cache_tag_full.vcd");
$dumpvars(0, tb_cache_tag_full);
#1000000;
$display("!!!!TIME OUT!!!!");
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter ADDR_WIDTH = 12;
parameter TAG_WIDTH = 2;
reg cke = 1;
reg [ADDR_WIDTH-1:0] s_addr;
reg s_valid;
wire [ADDR_WIDTH-1:0] m_addr;
wire [ TAG_WIDTH-1:0] m_tag;
wire m_hit;
wire m_valid;
always @(posedge clk) begin
if (reset) begin
s_addr <= {ADDR_WIDTH{1'b0}};
s_valid <= 1'b0;
end else if (cke) begin
s_addr[TAG_WIDTH:0] <= {$random()}; // s_addr[TAG_WIDTH:0] + 1;
s_valid <= 1'b1;
end
end
jelly_cache_tag_full #(
.USER_WIDTH(0),
.ADDR_WIDTH(ADDR_WIDTH),
.TAG_WIDTH (TAG_WIDTH)
) i_cache_tag_full (
.reset(reset),
.clk (clk),
.cke (cke),
.s_user (),
.s_addr (s_addr),
.s_valid(s_valid),
.m_user (),
.m_addr (m_addr),
.m_tag (m_tag),
.m_hit (m_hit),
.m_valid(m_valid)
);
endmodule
| 7.962894 |
module tb_capacity_async ();
localparam S_RATE = 1000.0 / 200.0;
// localparam M_RATE = 1000.0/150.1;
localparam M_RATE = 1000.0 / 1500.1;
initial begin
$dumpfile("tb_capacity_async.vcd");
$dumpvars(0, tb_capacity_async);
// #100000;
// $finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(M_RATE / 2.0) m_clk = ~m_clk;
reg reset = 1'b1;
initial #(S_RATE * 100) reset = 1'b0;
parameter ASYNC = 1;
parameter CAPACITY_WIDTH = 32;
parameter REQUEST_WIDTH = CAPACITY_WIDTH;
parameter ISSUE_WIDTH = CAPACITY_WIDTH;
parameter REQUEST_SIZE_OFFSET = 1'b0;
parameter ISSUE_SIZE_OFFSET = 1'b0;
parameter INIT_REQUEST = {CAPACITY_WIDTH{1'b0}};
reg [ REQUEST_WIDTH-1:0] s_request_size = 0;
reg s_request_valid = 0;
wire [CAPACITY_WIDTH-1:0] s_queued_request;
wire [ ISSUE_WIDTH-1:0] m_issue_size;
wire m_issue_valid;
reg m_issue_ready = 1;
wire [CAPACITY_WIDTH-1:0] m_queued_request;
jelly_capacity_async #(
.ASYNC (ASYNC),
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.REQUEST_WIDTH (REQUEST_WIDTH),
.ISSUE_WIDTH (ISSUE_WIDTH),
.REQUEST_SIZE_OFFSET(REQUEST_SIZE_OFFSET),
.ISSUE_SIZE_OFFSET (ISSUE_SIZE_OFFSET),
.INIT_REQUEST (INIT_REQUEST)
) i_capacity_async (
.s_reset (reset),
.s_clk (s_clk),
.s_request_size (s_request_size),
.s_request_valid (s_request_valid),
.s_queued_request(s_queued_request),
.m_reset (reset),
.m_clk (m_clk),
.m_issue_size (m_issue_size),
.m_issue_valid (m_issue_valid),
.m_issue_ready (m_issue_ready),
.m_queued_request(m_queued_request)
);
integer i = 0;
integer request_count = 0;
integer issue_count = 0;
always @(posedge s_clk) begin
if (reset) begin
s_request_size <= 0;
s_request_valid <= 0;
end else begin
i = i + 1;
if (i < 2000) begin
s_request_size <= {$random()} & 32'hff;
s_request_valid <= ({$random()} % 2 == 0);
end else begin
s_request_valid <= 1'b0;
end
if (s_request_valid) begin
request_count = request_count + s_request_size + REQUEST_SIZE_OFFSET;
end
if (i > 3000) begin
$display("request_count = %d, issue_count=%d", request_count, issue_count);
if (request_count == issue_count) begin
$display("OK");
end else begin
$display("NG");
end
$finish();
end
end
end
always @(posedge m_clk) begin
if (reset) begin
m_issue_ready <= 0;
end else begin
m_issue_ready <= {$random()};
if (m_issue_valid && m_issue_ready) begin
issue_count = issue_count + m_issue_size + ISSUE_SIZE_OFFSET;
end
end
end
endmodule
| 7.989831 |
module tb_capacity_buffer ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_buffer.vcd");
$dumpvars(0, tb_capacity_buffer);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
parameter CAPACITY_WIDTH = 32;
parameter REQUEST_WIDTH = CAPACITY_WIDTH;
parameter ISSUE_WIDTH = CAPACITY_WIDTH;
parameter REQUEST_SIZE_OFFSET = 1'b0;
parameter ISSUE_SIZE_OFFSET = 1'b1;
parameter INIT_REQUEST = {CAPACITY_WIDTH{1'b0}};
wire [CAPACITY_WIDTH-1:0] queued_request;
reg [ REQUEST_WIDTH-1:0] s_request_size = 0;
reg s_request_valid = 0;
wire [ ISSUE_WIDTH-1:0] m_issue_size;
wire m_issue_valid;
reg m_issue_ready = 1;
jelly_capacity_buffer #(
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.REQUEST_WIDTH (REQUEST_WIDTH),
.ISSUE_WIDTH (ISSUE_WIDTH),
.REQUEST_SIZE_OFFSET(REQUEST_SIZE_OFFSET),
.ISSUE_SIZE_OFFSET (ISSUE_SIZE_OFFSET),
.INIT_REQUEST (INIT_REQUEST)
) i_capacity_buffer (
.reset(reset),
.clk (clk),
.cke (cke),
.queued_request(queued_request),
.s_request_size (s_request_size),
.s_request_valid(s_request_valid),
.m_issue_size (m_issue_size),
.m_issue_valid(m_issue_valid),
.m_issue_ready(m_issue_ready)
);
integer i = 0;
integer count_request = 0;
integer count_issue = 0;
always @(posedge clk) begin
if (reset) begin
s_request_size <= 0;
s_request_valid <= 0;
m_issue_ready <= 0;
end else if (cke) begin
i = i + 1;
if (i < 2000) begin
s_request_size <= {$random()} & 32'hff;
s_request_valid <= ({$random()} % 10 == 0);
m_issue_ready <= {$random()};
end else begin
s_request_valid <= 1'b0;
m_issue_ready <= 1'b1;
end
if (s_request_valid) begin
count_request = count_request + s_request_size + REQUEST_SIZE_OFFSET;
end
if (m_issue_valid && m_issue_ready) begin
count_issue = count_issue + m_issue_size + ISSUE_SIZE_OFFSET;
end
if (i > 5000) begin
$display("count_request = %d, count_issue=%d", count_request, count_issue);
if (count_request == count_issue) begin
$display("OK");
end else begin
$display("NG");
end
$finish();
end
end
end
endmodule
| 6.873313 |
module tb_capacity_size_limitter ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_size_limitter.vcd");
$dumpvars(0, tb_capacity_size_limitter);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
parameter CAPACITY_WIDTH = 32;
parameter REQUEST_WIDTH = CAPACITY_WIDTH;
parameter ISSUE_WIDTH = 8;
parameter REQUEST_SIZE_OFFSET = 1'b1;
parameter ISSUE_SIZE_OFFSET = 1'b1;
reg [ ISSUE_WIDTH-1:0] max_issue_size = 8'hff;
wire [CAPACITY_WIDTH-1:0] queued_request;
reg [ REQUEST_WIDTH-1:0] s_request_size = 0;
reg s_request_valid = 0;
wire [ ISSUE_WIDTH-1:0] m_issue_size;
wire m_issue_valid;
reg m_issue_ready = 1;
jelly_capacity_size_limitter #(
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.REQUEST_WIDTH (REQUEST_WIDTH),
.ISSUE_WIDTH (ISSUE_WIDTH),
.REQUEST_SIZE_OFFSET(REQUEST_SIZE_OFFSET),
.ISSUE_SIZE_OFFSET (ISSUE_SIZE_OFFSET)
) i_capacity_size_limitter (
.reset(reset),
.clk (clk),
.cke (cke),
.max_issue_size(max_issue_size),
.queued_request(queued_request),
.s_request_size (s_request_size),
.s_request_valid(s_request_valid),
.m_issue_size (m_issue_size),
.m_issue_valid(m_issue_valid),
.m_issue_ready(m_issue_ready)
);
integer i = 0;
integer request_count = 0;
integer issue_count = 0;
always @(posedge clk) begin
if (reset) begin
s_request_size <= 0;
s_request_valid <= 0;
m_issue_ready <= 0;
end else if (cke) begin
i = i + 1;
if (i < 1000) begin
s_request_size <= {$random()} & 32'h1ff;
s_request_valid <= ({$random()} % 3 == 0);
m_issue_ready <= {$random()};
end else begin
s_request_valid <= 1'b0;
m_issue_ready <= 1'b1;
end
if (s_request_valid) begin
request_count = request_count + s_request_size + REQUEST_SIZE_OFFSET;
end
if (m_issue_valid && m_issue_ready) begin
issue_count = issue_count + m_issue_size + ISSUE_SIZE_OFFSET;
end
if (i > 2000) begin
$display("request_count = %d, issue_count=%d", request_count, issue_count);
if (request_count == issue_count) begin
$display("OK");
end else begin
$display("NG");
end
$finish();
end
end
end
endmodule
| 7.615417 |
module tb_capacity_timeout ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_timeout.vcd");
$dumpvars(0, tb_capacity_timeout);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
parameter TIMER_WIDTH = 8;
parameter CAPACITY_WIDTH = 32;
parameter REQUEST_WIDTH = CAPACITY_WIDTH;
parameter ISSUE_WIDTH = 8;
parameter REQUEST_SIZE_OFFSET = 1'b0;
parameter ISSUE_SIZE_OFFSET = 1'b1;
parameter INIT_REQUEST = {CAPACITY_WIDTH{1'b0}};
reg [ ISSUE_WIDTH-1:0] max_issue_size = 8'h7f;
wire [ TIMER_WIDTH-1:0] timeout = 8'h0f;
wire [CAPACITY_WIDTH-1:0] queued_request;
wire [ TIMER_WIDTH-1:0] current_timer;
reg [ REQUEST_WIDTH-1:0] s_request_size = 0;
reg s_request_valid = 0;
wire [ ISSUE_WIDTH-1:0] m_issue_size;
wire m_issue_valid;
reg m_issue_ready = 1;
jelly_capacity_timeout #(
.TIMER_WIDTH (TIMER_WIDTH),
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.REQUEST_WIDTH (REQUEST_WIDTH),
.ISSUE_WIDTH (ISSUE_WIDTH),
.REQUEST_SIZE_OFFSET(REQUEST_SIZE_OFFSET),
.ISSUE_SIZE_OFFSET (ISSUE_SIZE_OFFSET),
.INIT_REQUEST (INIT_REQUEST)
) i_capacity_timeout (
.reset(reset),
.clk (clk),
.cke (cke),
.max_issue_size(max_issue_size),
.timeout (timeout),
.queued_request(queued_request),
.current_timer (current_timer),
.s_request_size (s_request_size),
.s_request_valid(s_request_valid),
.m_issue_size (m_issue_size),
.m_issue_valid(m_issue_valid),
.m_issue_ready(m_issue_ready)
);
integer i = 0;
integer request_count = 0;
integer issue_count = 0;
always @(posedge clk) begin
if (reset) begin
s_request_size <= 0;
s_request_valid <= 0;
m_issue_ready <= 0;
end else if (cke) begin
i = i + 1;
if (i < 2000) begin
s_request_size <= {$random()} & 32'hff;
s_request_valid <= ({$random()} % 10 == 0);
m_issue_ready <= {$random()};
end else begin
s_request_valid <= 1'b0;
m_issue_ready <= 1'b1;
end
if (s_request_valid) begin
request_count = request_count + s_request_size + REQUEST_SIZE_OFFSET;
end
if (m_issue_valid && m_issue_ready) begin
issue_count = issue_count + m_issue_size + ISSUE_SIZE_OFFSET;
end
if (i > 5000) begin
$display("request_count = %d, issue_count=%d", request_count, issue_count);
if (request_count == issue_count) begin
$display("OK");
end else begin
$display("NG");
end
$finish();
end
end
end
endmodule
| 7.17141 |
module tb_cascade ();
localparam NUM = 4;
localparam DECIMAL_POINT = 14;
localparam WIDTH = 16;
reg clk;
reg rst;
reg [NUM*WIDTH-1:0] in_signal_pack;
reg [ WIDTH-1:0] in_signal [NUM-1:0];
integer i, j;
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
for (j = 0; j < WIDTH; j = j + 1) begin
#100
for (i = 0; i < NUM; i = i + 1) begin
in_signal[i] = i + 1 << j;
end
for (i = 0; i < NUM; i = i + 1) begin
in_signal_pack = {in_signal_pack, in_signal[i]};
end
end
end
always #10 clk = ~clk;
cascade_activation #(
.NUM(NUM),
.WIDTH(WIDTH),
.DECIMAL_POINT(DECIMAL_POINT)
) test (
.clk(clk),
.rst(rst),
.in_signal(in_signal_pack)
);
endmodule
| 6.736914 |
module tb_cast5_core ();
reg r_clk;
reg r_rst;
reg r_flag;
reg r_key_en;
reg [127:0] r_key;
reg r_din_en;
reg [ 63:0] r_din;
reg [ 31:0] r_err;
reg [ 2:0] r_count;
reg r_test;
wire s_dout_en;
wire [ 63:0] s_dout;
wire s_key_ok;
reg [ 1:0] r_state;
localparam DLY = 1;
reg [127:0] KEY1 = {
8'h01,
8'h23,
8'h45,
8'h67,
8'h12,
8'h34,
8'h56,
8'h78,
8'h23,
8'h45,
8'h67,
8'h89,
8'h34,
8'h56,
8'h78,
8'h9A
};
reg [127:0] PT1 = {8'h01, 8'h23, 8'h45, 8'h67, 8'h89, 8'hAB, 8'hCD, 8'hEF};
reg [127:0] CT1 = {8'h23, 8'h8B, 8'h4F, 8'hE5, 8'h84, 8'h7E, 8'h44, 8'hB2};
cast5_core uut (
.i_clk(r_clk),
.i_rst(r_rst),
.i_flag(r_flag), //1-encrypt,0-decrypt
.i_key(r_key),
.i_key_en(r_key_en),
.i_din(r_din),
.i_din_en(r_din_en),
.o_dout(s_dout),
.o_dout_en(s_dout_en),
.o_key_ok(s_key_ok)
);
initial begin
r_clk = 0;
forever #5 r_clk = ~r_clk;
end
always @(posedge r_clk or posedge r_rst) begin
if (r_rst) begin
r_count <= #DLY 3'd0;
r_flag <= #DLY 1'b0;
r_din_en <= #DLY 1'b0;
r_din <= #DLY 'b0;
r_key_en <= #DLY 1'b0;
r_key <= #DLY 'b0;
r_err <= #DLY 'b0;
r_state <= #DLY 2'b0;
end else begin
case (r_state)
2'd0: begin
if (r_test) begin
r_key_en <= #DLY 1'b1;
r_key <= #DLY KEY1;
r_state <= #DLY 2'd1;
end
end
2'd1: begin
r_key_en <= #DLY 1'b0;
if (s_key_ok) begin
r_din_en <= #DLY 1'b1;
r_flag <= #DLY 1'b1;
r_din <= #DLY PT1;
r_state <= #DLY 2'd2;
end
end
2'd2: begin
r_din_en <= #DLY 1'b0;
if (s_dout_en) begin
if (s_dout != CT1) r_err <= #DLY r_err + 1'b1;
r_din_en <= #DLY 1'b1;
r_din <= #DLY CT1;
r_flag <= #DLY 1'b0;
r_state <= #DLY 2'd3;
end
end
2'd3: begin
r_din_en <= #DLY 1'b0;
if (s_dout_en) begin
if (s_dout != PT1) r_err <= #DLY r_err + 1'b1;
r_count <= #DLY r_count + 1'b1;
if (r_count == 'd7) r_state <= #DLY 2'd0;
else r_state <= #DLY 2'd1;
end
end
endcase
end
end
initial begin
r_rst = 1'b1;
r_test = 1'b0;
repeat (50) @(negedge r_clk);
r_rst = 1'b0;
repeat (10) @(negedge r_clk);
r_test = 1'b1;
repeat (5000) @(negedge r_clk);
$stop;
end
endmodule
| 6.66467 |
module tb_decoder;
reg [31:0] inst;
reg inst_16;
reg clk;
wire arith;
wire dp;
wire sdibe;
wire llp;
wire lssd;
wire gpca;
wire gspa;
wire misc;
wire smr;
wire lmr;
wire cbsc;
wire ucb;
reg of;
integer file;
decoder top (
inst,
inst_16,
clk,
arith,
dp,
sdibe,
llp,
lssd,
gpca,
gspa,
misc,
smr,
lmr,
cbsc,
ucb
);
initial begin
inst = 0;
inst_16 = 1;
clk = 0;
of = 0;
end
always #5 clk = ~clk;
initial begin
#10
forever
@(posedge clk) begin
#5{of, inst[31:26]} <= {of, inst[31:26]} + 1;
end
end
initial begin
file = $fopen("./decoder.log", "w");
$fdisplay(
file,
"inst[31:26] inst_16 [arith,dp,sdibe,llp,lssd,gpca,gspa,misc,smr,lmr,cbsc,ucb] time");
forever
@(posedge clk) begin
#1
$fdisplay(
file,
"%b\t\t%b\t\t%b\t\t\t\t@%d",
inst[31:26],
inst_16,
{
arith, dp, sdibe, llp, lssd, gpca, gspa, misc, smr, lmr, cbsc, ucb
},
$time
);
end
end
always @(posedge clk) begin
if (of == 1'b1) begin
$fclose(file);
$finish;
end
end
endmodule
| 8.277876 |
module tb_catboard_blinky_host;
reg clock;
wire [7:0] led;
wire uart_tx;
reg uart_rx;
initial begin
$from_myhdl(clock, uart_rx);
$to_myhdl(led, uart_tx);
end
catboard_blinky_host dut (
clock,
led,
uart_tx,
uart_rx
);
endmodule
| 7.51189 |
module: CF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CF;
// Inputs
reg [15:0] gyroData;
reg [15:0] y_accel_data;
reg [15:0] z_accel_data;
reg clk;
// Outputs
wire [15:0] x_temp;
wire [15:0] x_final;
// Instantiate the Unit Under Test (UUT)
CF uut (
.gyroData(gyroData),
.y_accel_data(y_accel_data),
.z_accel_data(z_accel_data),
.clk(clk),
.x_temp(x_temp),
.x_final(x_final)
);
initial begin
// Initialize Inputs
clk = 0;
#100 gyroData = 16'h0001;y_accel_data = 16'h2800;z_accel_data = 16'h2000;
#100 gyroData = 16'h0004;y_accel_data = 16'h2800;z_accel_data = 16'h2000;
#100 gyroData = 16'h0008;y_accel_data = 16'h2800;z_accel_data = 16'h2000;
#100 gyroData = 16'h0010;y_accel_data = 16'h2800;z_accel_data = 16'h2000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
#20000 clk = ~clk;
end
endmodule
| 7.014675 |
module tb_cgmii;
//Registro
reg tb_clock;
reg tb_reset;
reg [3:0] tb_debug_pulse;
wire [7:0] tb_tx_ctrl;
wire [63:0] tb_tx_data;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
tb_debug_pulse = 4'b0000;
#1 tb_reset = 1'b1;
#1 tb_reset = 1'b0;
#10 tb_debug_pulse = 4'b0000;
#10000000 $finish;
end
//always @ (posedge tb_clock)
//begin
// counter = counter + 1 ;
// case(counter)
// 10'D2: tb_reset = 1'b1 ;
// 10'D3: tb_reset = 1'b0 ;
// 10'D10: tb_debug_pulse = 4'b0000 ;
// 10'D200: tb_debug_pulse = 4'b0001 ;
// 10'D400: tb_debug_pulse = 4'b0010 ;
// 10'D500: tb_debug_pulse = 4'b1000 ;
// 10'D600: tb_debug_pulse = 4'b1111 ;
// endcase
//end
always #1 tb_clock = ~tb_clock;
cgmii #() test_cgmii (
.i_clock(tb_clock),
.i_reset(tb_reset),
.i_debug_pulse(tb_debug_pulse),
.o_tx_ctrl(tb_tx_ctrl),
.o_tx_data(tb_tx_data)
);
endmodule
| 7.085932 |
module tb_cgmiiandenco;
parameter LEN_TX_CTRL = 8;
parameter LEN_TX_DATA = 64;
parameter LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [ 9:0] counter;
reg [ 3:0] tb_debug_pulse;
wire [ LEN_TX_CTRL-1:0] tb_tx_ctrl;
wire [ LEN_TX_DATA-1:0] tb_tx_data;
wire [ 3:0] tb_o_type;
wire [LEN_CODED_BLOCK-1:0] tb_tx_coded;
initial begin
tb_reset = 1'b0;
tb_clock = 1'b0;
tb_enable = 1'b0;
counter = 0;
end
always @(posedge tb_clock) begin
counter = counter + 1;
case (counter)
10'D2: tb_reset = 1'b1;
10'D3: begin
tb_reset = 1'b0;
tb_enable = 1'b1;
end
10'D4: tb_debug_pulse = 4'b000;
endcase
end
cgmii #() test_cgmii (
.i_clock(tb_clock),
.i_reset(tb_reset),
.i_debug_pulse(tb_debug_pulse),
.o_tx_ctrl(tb_tx_ctrl),
.o_tx_data(tb_tx_data)
);
encoder_comparator #(
.LEN_TX_CTRL (LEN_TX_CTRL),
.LEN_CODED_BLOCK(LEN_CODED_BLOCK),
.LEN_TX_DATA (LEN_TX_DATA)
) u_comparator (
.i_clock (tb_clock),
.i_reset (tb_reset),
.i_enable (tb_enable),
.i_tx_ctrl (tb_tx_ctrl),
.i_tx_data (tb_tx_data),
.o_t_type (tb_o_type),
.o_tx_coded(tb_tx_coded)
);
always #2.5 tb_clock = ~tb_clock;
endmodule
| 6.917279 |
module. This TB verifies
// that the chacha20 core can be used as specified in RFC 7539.
// Testvectors are taken from the RFC.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_chacha20_qr();
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] tb_a;
reg [31 : 0] tb_b;
reg [31 : 0] tb_c;
reg [31 : 0] tb_d;
wire [31 : 0] tb_a_prim;
wire [31 : 0] tb_b_prim;
wire [31 : 0] tb_c_prim;
wire [31 : 0] tb_d_prim;
//----------------------------------------------------------------
// chacha_core device under test.
//----------------------------------------------------------------
chacha_qr dut(
.a(tb_a),
.b(tb_b),
.c(tb_c),
.d(tb_d),
.a_prim(tb_a_prim),
.b_prim(tb_b_prim),
.c_prim(tb_c_prim),
.d_prim(tb_d_prim)
);
//----------------------------------------------------------------
// chacha_qr_test
//----------------------------------------------------------------
initial
begin : chacha20_qr_test
$display(" -- Testbench for chacha20 qr module started --");
$display("");
// Testvectors from RFC 7539, chapter 2.1.1.
$display("*** Applying test vector to qr module.");
tb_a = 32'h11111111;
tb_b = 32'h01020304;
tb_c = 32'h9b8d6f43;
tb_d = 32'h01234567;
#1;
$display("a = 0x%08x, b = 0x%08x, c = 0x%08x, d = 0x%08x",
tb_a, tb_b, tb_c, tb_d);
$display("a_prim = 0x%08x, b_prim = 0x%08x, c_prim = 0x%08x, d_prim = 0x%08x",
tb_a_prim, tb_b_prim, tb_c_prim, tb_d_prim);
$display("");
if ((tb_a_prim != 32'hea2a92f4) || (tb_b_prim != 32'hcb1cf8ce) ||
(tb_c_prim != 32'h4581472e) || (tb_d_prim != 32'h5881c4bb))
$display("*** Error: Incorrect result generated by the qr module.");
else
$display("*** Correct result generated by the qr module.");
$display("");
$display(" -- Testbench for chacha20 qr module done --");
$finish;
end // chacha20_qr_test
endmodule
| 6.733226 |
module tb_channel_management;
reg clk100;
wire [7:0] debug;
wire hpd;
wire auxch_in;
wire auxch_out;
wire auxch_tri;
// Datapath requirements
reg [2:0] stream_channel_count;
reg [2:0] source_channel_count;
// Datapath control
wire tx_clock_train;
wire tx_align_train;
// Transceiver management
wire [3:0] tx_powerup_channel;
wire tx_preemp_0p0;
wire tx_preemp_3p5;
wire tx_preemp_6p0;
wire tx_swing_0p4;
wire tx_swing_0p6;
wire tx_swing_0p8;
reg [3:0] tx_running;
wire tx_link_established;
reg [31:0] i, j;
initial begin
clk100 = 1'b0;
// Datapath requirements
stream_channel_count = 3'b001;
source_channel_count = 3'b001;
tx_running = 4'b0000;
end
always begin
#5 clk100 = ~clk100; // generate a clock
end
wire dp_tx_hp_detect;
tb_dummy_sink i_tb_dummy_sink (
.clk100 (clk100),
.auxch_data (auxch_in),
.hotplug_detect(hpd)
);
channel_management i_channel_management (
.clk100(clk100),
.debug (debug),
.hpd (hpd),
.auxch_in (auxch_in),
.auxch_out(auxch_out),
.auxch_tri(auxch_tri),
// Datapath requirements
.stream_channel_count(stream_channel_count),
.source_channel_count(source_channel_count),
// Datapath control
.tx_clock_train(tx_clock_train),
.tx_align_train(tx_align_train),
// Transceiver management
.tx_powerup_channel(tx_powerup_channel),
.tx_preemp_0p0(tx_preemp_0p0),
.tx_preemp_3p5(tx_preemp_3p5),
.tx_preemp_6p0(tx_preemp_6p0),
.tx_swing_0p4(tx_swing_0p4),
.tx_swing_0p6(tx_swing_0p6),
.tx_swing_0p8(tx_swing_0p8),
.tx_running (tx_running),
.tx_link_established(tx_link_established)
);
endmodule
| 6.597603 |
module tb_check_idle_resp (
// Inputs - System.
hclk_i,
hresetn_i,
// Inputs - AHB bus.
htrans_i,
hsel_i,
hready_i,
hrdata_bus_i,
hrdata_i
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
parameter NUM_SLVS = 0;
parameter RDATA_W = 0;
parameter RDATA_BUS_W = NUM_SLVS * RDATA_W;
//----------------------------------------------------------------------
// LOCAL MACROS
`define HTRANS_W 2
`define HTRANS_IDLE 2'b0
//----------------------------------------------------------------------
// PORT DECLARATIONS
// Inputs - System.
input hclk_i;
input hresetn_i;
// Inputs - slaves
input [`HTRANS_W-1:0] htrans_i;
input [NUM_SLVS-1:0] hsel_i;
input [RDATA_BUS_W-1:0] hrdata_bus_i;
// Inputs - ahb bus.
input hready_i;
input [RDATA_W-1:0] hrdata_i;
//----------------------------------------------------------------------
// INTERNAL SIGNALS
// hsel controlled to decode which slave owns the data bus.
reg [NUM_SLVS-1:0] hsel_data_r;
// rdata of the slave that owns the data bus.
wire [RDATA_W-1:0] hrdata_selected;
// Which slave owns the data bus.
integer data_own_slave;
// Asserted when check condition occurs.
reg check_done;
//--------------------------------------------------------------------
// Generate a version of hsel that decodes which slave owns the data
// bus. Due to pipelined nature of AHB bus, a master can own the
// command signals, while another master owns the data signals. This
// means that we cannot use hsel directly to decode which slave owns
// the data busses, since hsel is a command signal.
// Here we capture a new version of hsel when ever a new value of hsel
// is detected (compared with previous captured version) and hready is
// asserted. By waiting for hready we know that the previous slave has
// finished and control of data busses is now handed over to the new
// slave.
always @(posedge hclk_i or negedge hresetn_i) begin : hsel_data_r_PROC
if (~hresetn_i) begin
hsel_data_r <= 0;
end else begin
if ((hsel_data_r != hsel_i) & hready_i) hsel_data_r <= hsel_i;
end
end // hsel_data_r_PROC
// Select the read data bus of the slave that should own the
// data bus.
tb_busmux_ohsel #(NUM_SLVS, // Number of buses to mux between.
RDATA_W // Width of each bus input to the mux.
) U_tb_busmux_ohsel (
.sel (hsel_data_r),
.din (hrdata_bus_i),
.dout(hrdata_selected)
);
// Decode integer value of slave index that owns data bus.
always @(*) begin : data_own_slave_PROC
integer i;
data_own_slave = 0;
for (i = 0; i <= NUM_SLVS; i = i + 1) begin
if (hsel_data_r[i]) data_own_slave = i;
end
end // data_own_slave_PROC
// Perform the check.
always @(posedge hclk_i) begin : check_PROC
check_done = 1'b0;
// This is the case we need to do the check, a slave is
// selected, and the master is sending IDLE transactions.
if (|hsel_i & (htrans_i == `HTRANS_IDLE)) begin
check_done = 1'b1;
if (hrdata_i != hrdata_selected) begin
$display("ERROR: %0d - IDLE RESP CHECKER FAILED.", $time);
$display("ERROR: %0d - Bus hrdata (0x%0h) != selcted slave (%0d) hrdata (0x%0h)", $time,
hrdata_i, data_own_slave, hrdata_selected);
end
end
end // check_PROC
//----------------------------------------------------------------------
// LOCAL MACROS UNDEF
`undef HTRANS_W
`undef HTRANS_IDLE
endmodule
| 7.744873 |
module tb_Chi;
localparam DataLength = 20;
reg [1599:0] in_data;
reg [1599:0] out_ans;
wire [1599:0] out_data;
reg [1599:0] in_mem [0:DataLength-1];
reg [1599:0] golden_mem[0:DataLength-1];
integer i, err_num;
Chi chi0 (
.in (in_data),
.out(out_data)
);
initial $readmemh(`IN_DATA, in_mem);
initial $readmemh(`GOLDEN, golden_mem);
initial begin
$fsdbDumpfile("chi.fsdb");
$fsdbDumpvars;
end
initial begin
in_data = 0;
out_ans = 0;
i = 0;
err_num = 0;
$display("Testing Chi Stage...");
// $display("test mod %d mod %d = %d", -1, 64, -1%64);
for (i = 0; i < DataLength; i = i + 1) begin
#(`CYCLE);
in_data = in_mem[i];
out_ans = golden_mem[i];
#(`HCYCLE);
if (out_data !== out_ans) begin
$display("Error at %d:\nin=%h\noutput=%h\nexpect=%h", i, in_data, out_data, out_ans);
err_num = err_num + 1;
end
#(`HCYCLE);
end
if (err_num == 0) begin
$display("---------------------------------------------\n");
$display("All data have been generated successfully!\n");
$display("--------------------PASS--------------------\n");
$display("---------------------------------------------\n");
end else begin
$display("---------------------------------------------\n");
$display("There are %d errors!\n", err_num);
$display("--------------------FAIL--------------------\n");
$display("---------------------------------------------\n");
end
// finish tb
#(`CYCLE) $finish;
end
endmodule
| 6.697827 |
module testRSS ();
//constants
parameter N = 16;
parameter len_data_test = 1000;
//set counter for FOR LOOP
integer count;
integer i;
integer cout_for_dec = 10;
integer f;
//memory for test
reg data_for_test[len_data_test-1:0];
// ====== ports initialization begin ====== //
reg clk, rst;
reg data_in, data;
reg [10:0] idx;
reg bit;
wire ce, mclk, ce_pcm;
wire signed [6:0] data_out1;
wire signed [11:0] data_out2;
reg [7:0] prescaler;
wire signed [15:0] fir_out;
reg signed [15:0] b0;
reg signed [15:0] b1;
wire signed [15:0] fir_in;
cic DUT(clk,rst,ce,data_in, data_out2);
micclk clockgen(clk, rst, mclk, ce);
pcm_clk pcmclkgen(clk, rst, prescaler, ce_pcm);
FIR_Filter fir(clk, rst, ce_pcm, fir_in, b0, b1, fir_out);
assign fir_in = {{4{data_out2[11]}},data_out2};
// ================== TEST BEGING ==================== //
initial begin
f = $fopen("./output.csv","w");
end
// ---initial values begin --- //
initial begin
clk = 0;
rst = 0;
data_in = 0;
prescaler = 49;
b0 = 16'h0FFF;
b1 = 16'h7FFF;
//read memory data
$readmemh("sin_for_tb.txt", data_for_test);
end
// ---initial values end --- //
always@(posedge clk) begin
if(rst) begin
data_in<=0;
idx <=0;
bit <=1;
end
else if (ce) begin
bit <= bit ^ 1;
data_in <= bit;
//data_in <= data_for_test[idx];
idx <= idx+1;
end
end
//clock
always # 20833 clk = ~clk;
//--------- stimulus start! ---------- //
initial begin
//put rst
rst = 1; //set rst
@(negedge clk); //wait for negedge clk
rst = 0; //set rst = 0
// --- Using test_data_input for stimulus DUT --- //
for(count = 0; count < len_data_test; count = count + 1) begin
data = data_for_test[count];
if(count == 0) begin
$display("data_in,data_out_L1,data_out_cic");
$fwrite(f,"data_in,data_out_L1,data_out_cic,fir_in,fir_out\n");
end
if(count!=0 || count == 0) begin
$display ("%d,%d,%d",data_for_test[count], DUT.sum1, data_out2);
$fwrite(f,"%d,%d,%d,%d,%d\n",data_for_test[count], DUT.sum1, data_out2, fir.X1, fir_out);
end
//wait for negedge clk for change the values
@(negedge clk);
end
$fclose(f);
$finish;
end
//--------- stimulus END! ---------- //
//--------- dump to file! ---------- //
initial begin
$dumpfile ("rss.vcd");
$dumpvars;
end
endmodule
| 6.529798 |
module tb_cilantro_rv_top;
reg clk;
reg rst;
reg [31:0] instruction_in;
wire [31:0] data_out;
reg [32:0] memory[1023:0];
// Instantiate DUT here
cilantro_rv_top DUT (
.clk(clk),
.rst(rst),
.instr_in(instruction_in),
.data_out(data_out)
);
// Testbench clock generation (for example, a 10ns clock period)
always #5 clk = ~clk;
initial begin
clk = 0;
rst = 1; // Reset active high
#10 rst = 0; // De-assert reset after 10 time units
// Load a test program into memory (for example)
memory[0] = 32'h00100013; // ADDI x0, x1, 1 (x0 = 0 + 1)
memory[4] = 32'h00008067; // JALR x0, x1, 0 (jump to x1 + 0)
memory[8] = 32'h00000013; // NOP (no operation)
// Stimulus: Set instruction_in to the address of the first instruction
instruction_in = 32'd0;
#20 instruction_in = 32'd4;
// Continue with other instructions as needed for testing
#100;
$finish;
end
initial begin
$dumpfile("tb_cilantro_rv_top.vcd");
$dumpvars(0, tb_cilantro_rv_top);
end
initial begin
$display("rst\tinstr\tout");
$monitor(rst, "\t", instruction_in, "\t", data_out);
end
endmodule
| 6.578052 |
module tb_cisc ();
reg clk, reset, clkreset;
wire clk1, clk2;
wire [20:0] cword;
wire [7:0] ird, eab, edb, dout;
wire [2:0] ib, sb, state;
wire [7:0] di, t1, t2, b, pc, irf, ire, aluout, abus, bbus;
cisc CPU (
clk1,
clk2,
cword,
ird,
eab,
edb,
dout,
ib,
sb,
state,
di,
t1,
t2,
b,
pc,
irf,
ire,
aluout,
abus,
bbus,
clk,
reset,
clkreset
);
initial begin
reset = 1'd1;
clkreset = 1'd1;
clk = 1'd0;
#11 clkreset = 1'd0;
#30 reset = 1'd0;
end
always #10 clk = ~clk;
endmodule
| 7.458522 |
module tb_cla4;
reg [3:0] tb_a, tb_b; // 4bits 2 input
reg tb_ci; // 1bit 1 input
wire [3:0] tb_s; // 4bits output
wire tb_co; // 1bit output
wire [4:0] tb_result; // 5bits output
assign tb_result = {tb_co, tb_s};
cla4 U0_cla4 (
.a (tb_a),
.b (tb_b),
.ci(tb_ci),
.s (tb_s),
.co(tb_co)
); //express by instance
initial begin
tb_a = 0;
tb_b = 0;
tb_ci = 0; //at first, input(a,b,ci)=(0,0,0)
#10;
tb_a = 4'h3;
tb_b = 4'h5;
tb_ci = 0; //after 10ns, input(a,b,ci)=(3,5,0)
#10;
tb_a = 4'h7;
tb_b = 4'h9;
tb_ci = 0; //after 10ns, input(a,b,ci)=(7,9,0)
#10;
tb_a = 4'h5;
tb_b = 4'h5;
tb_ci = 1; //after 10ns, input(a,b,ci)=(5,5,1)
#10;
tb_a = 4'h8;
tb_b = 4'h7;
tb_ci = 1; //after 10ns, input(a,b,ci)=(8,7,1)
#10;
tb_a = 4'hf;
tb_b = 4'hf;
tb_ci = 0; //after 10ns, input(a,b,ci)=(16,16,0)
#10;
tb_a = 4'hf;
tb_b = 4'hf;
tb_ci = 1; //after 10ns, input(a,b,ci)=(16,16,1)
#10;
$stop; //after 10ns, stop
end
endmodule
| 6.757753 |
module tb_clark_park_tr ();
initial $dumpvars(1, tb_clark_park_tr);
reg rstn = 1'b0;
reg clk = 1'b1;
always #(13563) clk = ~clk; // 36.864MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg en_theta = 0;
reg [11:0] theta = 0; // 当前电角度（简记为 ψ）。取值范围0~4095。0对应0°；1024对应90°；2048对应180°；3072对应270°。
localparam [11:0] PI_M2_D3 = (2 * 4096 / 3); // (2/3)*π
localparam [11:0] PI_D3 = (4096 / 3); // (1/3)*π
wire en_iabc;
wire signed [15:0] ia, ib, ic;
wire en_ialphabeta;
wire signed [15:0] ialpha, ibeta;
wire en_idq;
wire signed [15:0] id;
wire signed [15:0] iq;
// 这里只是刚好借助了 sincos 模块来生成正弦波给 clark_tr ，只是为了仿真。在 FOC 设计中 sincos 模块并不是用来给 clark_tr 提供输入数据的，而是被 park_tr 调用。
sincos u1_sincos (
.rstn(rstn),
.clk(clk),
.i_en(en_theta),
.i_theta(theta + PI_M2_D3), // input : θ + (2/3)*π
.o_en(en_iabc),
.o_sin(ia), // output: Ia, 振幅为±16384，初相位为 (4/3)*π 的正弦波
.o_cos()
);
sincos u2_sincos (
.rstn (rstn),
.clk (clk),
.i_en (en_theta),
.i_theta(theta + PI_D3), // input : θ + (1/3)*π
.o_en (),
.o_sin (ib), // output: Ib, 振幅为±16384，初相位为 (2/3)*π 的正弦波
.o_cos ()
);
sincos u3_sincos (
.rstn (rstn),
.clk (clk),
.i_en (en_theta),
.i_theta(theta), // input : θ
.o_en (),
.o_sin (ic), // output: Ic, 振幅为±16384，初相位为 0 的正弦波
.o_cos ()
);
// clark 变换
clark_tr u_clark_tr (
.rstn(rstn),
.clk(clk),
.i_en(en_iabc),
.i_ia(ia / 16'sd2), // input : 振幅为±8192，初相位为 (4/3)*π 的正弦波
.i_ib(ib / 16'sd2), // input : 振幅为±8192，初相位为 (2/3)*π 的正弦波
.i_ic(ic / 16'sd2), // input : 振幅为±8192，初相位为 0 的正弦波
.o_en(en_ialphabeta),
.o_ialpha(ialpha), // output: Iα ，应该为初相位为 (4/3)*π 的正弦波
.o_ibeta ( ibeta ) // output: Iβ ，相位应该比 Iα 滞后 (1/2)*π ，也就是与 Iα 正交
);
// park 变换
park_tr u_park_tr (
.rstn(rstn),
.clk(clk),
.psi(theta + 12'd512), // input : θ + (1/4)*π
.i_en(en_ialphabeta),
.i_ialpha(ialpha), // input : Iα
.i_ibeta(ibeta), // input : Iβ
.o_en(en_idq),
.o_id ( id ), // output: Id ，应该变为一个定值，因为 park 变换把转子又变回定子了
.o_iq ( iq ) // output: Iq ，应该变为一个定值，因为 park 变换把转子又变回定子了
);
integer i;
initial begin
while (~rstn) @(posedge clk);
for (i = 0; i < 1000; i = i + 1)
@(posedge clk) begin
en_theta <= 1'b1;
theta <= theta + 12'd10;
@(posedge clk);
en_theta <= 1'b0;
repeat (9) @(posedge clk);
end
$finish;
end
endmodule
| 6.933763 |
module tb_cla_clk;
reg clock; //input clock
reg [31:0] tb_a, tb_b; //32bits 2 input
reg tb_ci; //carry in
wire [31:0] tb_s_cla; //32bits sum(output)
wire tb_co_cla; //carry out
parameter STEP = 10; //define STEP=10ns
cla_clk U0_cla_clk (
.clock(clock),
.a(tb_a),
.b(tb_b),
.ci(tb_ci),
.s_cla(tb_s_cla),
.co_cla(tb_co_cla)
); //express by instance
always #(STEP / 2) clock = ~clock; //every 5ns, invert clock
initial begin
clock = 1'b1;
tb_a = 32'h0;
tb_b = 32'h0;
tb_ci = 1'b0; //at first, input(a,b,ci)=(0,0,0)
#(STEP - 2);
tb_a = 32'hFFFF_FFFF;
tb_b = 32'h0;
tb_ci = 1'b0; //after 8ns, input(a,b,ci)=(hFFFF_FFFF,0,0)
#(STEP);
tb_a = 32'h0;
tb_b = 32'hFFFF_FFFF;
tb_ci = 1'b1; //after 10ns, input(a,b,ci)=(0,hFFFF_FFFF,1)
#(STEP);
tb_a = 32'h0000_FFFF;
tb_b = 32'hFFFF_0000;
tb_ci = 1'b0; //after 10ns, input(a,b,ci)=(h0000_FFFF,hFFFF_0000,0)
#(STEP);
tb_a = 32'h0000_FFFF;
tb_b = 32'hFFFF_0000;
tb_ci = 1'b1; //after 10ns, input(a,b,ci)=(h0000_FFFF,hFFFF_0000,1)
#(STEP);
tb_a = 32'h135f_a562;
tb_b = 32'h3561_4642;
tb_ci = 1'b0; //after 10ns, input(a,b,ci)=(h135f_a562,h3561_4642,0)
#(STEP * 2);
$stop; //after 20ns, stop
end
endmodule
| 6.728434 |
module tb_clk ();
reg clk = 0;
reg reset = 1;
wire [15:0] out;
top top0 (
clk,
reset,
out
);
always #5 clk = ~clk;
initial begin
#5820000 reset = 0;
#112 reset = 1;
end
endmodule
| 7.317761 |
module wb_clkrst (
// Clk & Rst Interface
clk_o,
rst_o
);
//
// Clock and Reset Interface
//
output clk_o;
output rst_o;
//
// Internal registers
//
reg clk_o;
reg rst_o;
initial begin
clk_o = 0;
rst_o = 0;
#1;
rst_o = 1;
#`Trst;
rst_o = 0;
end
//
// Clock generator
//
always clk_o = #`Thper ~clk_o;
endmodule
| 7.197419 |
module tb_clk_div ();
reg clk_in;
reg rst_n;
wire clk_2;
wire clk_5;
ClkDiv #(
.DIV_NUM(2)
) clk2 (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk_2)
);
ClkDiv #(
.DIV_NUM(5)
) clk5 (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk_5)
);
initial begin
rst_n = 0;
clk_in = 0;
#10 rst_n = 1;
forever begin
#5 clk_in = ~clk_in;
end
end
endmodule
| 6.770648 |
module tb_clk_divider ();
reg clk;
reg rst;
wire clk2;
wire clk4;
wire clk8;
initial begin
clk = 1'b1;
rst = 1'b1;
#100 rst = 1'b0;
end
always #10 clk = ~clk;
clk_divider ins (
.clk (clk),
.rst (rst),
.clk2(clk2),
.clk4(clk4),
.clk8(clk8)
);
endmodule
| 6.740558 |
module tb_clk_gen (
clk
);
output clk;
reg clk;
integer period_hi;
integer period_lo;
reg en;
initial begin
period_hi = 20_000; // 20ns 25MHz
period_lo = 20_000; // 20ns
en = 1'b0;
clk = 1'b0;
end
always @(en) begin
while (en == 1'b1) begin
clk = 1'b1;
#(period_hi);
clk = 1'b0;
#(period_lo);
end
end
endmodule
| 6.651295 |
module tb_clk_pll ();
reg clk;
reg rst_n;
wire pll_clk;
wire locked;
clk_pll clk_pll_inst (
.areset(~rst_n),
.inclk0(clk),
.c0(pll_clk),
.locked(locked)
);
initial begin
clk = 1'b1;
rst_n = 1'b0;
#10 rst_n = 1'b1;
#5000 $finish;
end
always #1 clk = ~clk;
endmodule
| 7.050562 |
module: clocking
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_clock;
// Inputs
reg clk_50M;
reg rst_n;
reg clk_main_out;
reg clk_ddr_p;
reg clk_ddr_n;
// Outputs
wire clk_main;
wire clk_sdr_p;
wire clk_sdr_n;
wire rst_sys_n;
wire clk_sys;
wire clk_col;
wire clk_rxg;
wire clk_rxio;
wire clk_txg;
wire clk_txio;
wire tx_strobe;
// Instantiate the Unit Under Test (UUT)
clocking uut (
.clk_50M(clk_50M),
.rst_n(rst_n),
.clk_main(clk_main),
.clk_sdr_p(clk_sdr_p),
.clk_sdr_n(clk_sdr_n),
.clk_main_out(clk_main_out),
.clk_ddr_p(clk_ddr_p),
.clk_ddr_n(clk_ddr_n),
.rst_sys_n(rst_sys_n),
.clk_sys(clk_sys),
.clk_col(clk_col),
.clk_rxg(clk_rxg),
.clk_rxio(clk_rxio),
.clk_txg(clk_txg),
.clk_txio(clk_txio),
.tx_strobe(tx_strobe)
);
initial begin
// Initialize Inputs
clk_50M = 0;
rst_n = 0;
clk_main_out = 0;
clk_ddr_p = 0;
clk_ddr_n = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #10 clk_50M=~clk_50M;
endmodule
| 7.048701 |
module tb_clock1;
parameter TF = 2;
parameter TH = TF / 2;
wire clk1;
initial begin
$dumpfile("tb_clock1.vcd");
$dumpvars(0);
end
initial begin
$monitor("%0d\tclk1=", $time, clk1);
#10 $finish;
end
clock1 CLK1GEN (.clk1(clk1));
endmodule
| 6.524111 |
module: clocking
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_clocking;
// Inputs
reg clk_25M;
reg rst_n;
reg clk_main_out;
reg clk_ddr_p;
reg clk_ddr_n;
// Outputs
wire clk_main;
wire clk_sdr_p;
wire clk_sdr_n;
wire rst_sys_n;
wire clk_sys;
wire clk_col;
wire clk_rxg;
wire clk_rxio;
wire clk_rxg_x2;
wire rx_strobe;
wire clk_txg;
wire clk_txio;
wire tx_strobe;
// Instantiate the Unit Under Test (UUT)
clocking uut (
.clk_25M(clk_25M),
.rst_n(rst_n),
.clk_main(clk_main),
.clk_sdr_p(clk_sdr_p),
.clk_sdr_n(clk_sdr_n),
.clk_main_out(clk_main_out),
.clk_ddr_p(clk_ddr_p),
.clk_ddr_n(clk_ddr_n),
.rst_sys_n(rst_sys_n),
.clk_sys(clk_sys),
.clk_col(clk_col),
.clk_rxg(clk_rxg),
.clk_rxio(clk_rxio),
.clk_rxg_x2(clk_rxg_x2),
.rx_strobe(rx_strobe),
.clk_txg(clk_txg),
.clk_txio(clk_txio),
.tx_strobe(tx_strobe)
);
initial begin
// Initialize Inputs
clk_25M = 0;
rst_n = 0;
clk_main_out = 0;
clk_ddr_p = 0;
clk_ddr_n = 0;
// Wait 100 ns for global reset to finish
#100;
#100 rst_n = 1;
// Add stimulus here
end
always # 20 clk_25M = ~clk_25M;
always # 20 clk_main_out = ~clk_main_out;
endmodule
| 7.048701 |
module ******************* */
/* ********** 1) Main clock and test clock set to 50MHz ** */
/* ********** 2) Auto stop time is 10Us ** */
/* ********** ** */
/* ********** ** */
/* ********** ** */
/* ***************************************** GS Core ******************************* */
// Create by Mr. Liqinghua
// rev.0.1 2006.07.17
// rev.0.2 2006.07.24
module tb_clock_div (clk_in, rst, clk_out);
parameter cfactor= 2;
input clk_in;
input rst;
output clk_out;
reg clk_loc=0;
// reg [15:0] cnt;//allowed maximum clock division factor is 65536
reg [10:0] cnt;//allowed maximum clock division factor is 2048
// assign clk_out = ((rst==1) || (cfactor==1))? clk_in : clk_loc;
assign clk_out = (cfactor==1)? clk_in : clk_loc;
always@(posedge clk_in)
begin: cdiv
if(rst==1)
begin
cnt <= 'd0;
clk_loc = 1;
end
else
begin
cnt <= cnt + 1'b1;
if(cnt==cfactor/2-1)
clk_loc = 0;
else if(cnt==cfactor-1)
begin
cnt <= 'd0;
clk_loc = 1;
end
end
end
endmodule
| 7.793578 |
module tb_clock_divider;
// Inputs
reg clock_in;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog
Clock_divider uut (
.clock_in (clock_in),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock_in = 0;
// create input clock 50MHz
forever #10 clock_in = ~clock_in;
end
endmodule
| 7.862983 |
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