code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TbNeokeonGammafun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [127:0] inDataState = 128'b0;
wire [127:0] outDataState;
NeokeonGammafun neokeonGammafun (
.inDataState (inDataState),
.outDataState(outDataState)
);
always begin
#(inClkp);
inDataState = 128'h6954e6d2e262a1f43b1b8df3491b3773;
$stop;
end
endmodule
| 6.525215 |
module TbNeokeonROTL32by1fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTL32by1fun neokeonROTL32by1fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h1111aaaa;
$stop;
end
endmodule
| 6.587286 |
module TbNeokeonROTL32by2fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTL32by2fun neokeonROTL32by2fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h11111111;
$stop;
end
endmodule
| 6.587286 |
module TbNeokeonROTL32by5fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTL32by5fun neokeonROTL32by5fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h00800080;
$stop;
end
endmodule
| 6.587286 |
module TbNeokeonROTL32by8fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTL32by8fun neokeonROTL32by8fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h00800080;
$stop;
end
endmodule
| 6.587286 |
module TbNeokeonROTR32by1fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTR32by1fun neokeonROTL32by1fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h1111aaaa;
$stop;
end
endmodule
| 6.758934 |
module TbNeokeonROTR32by2fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTR32by2fun neokeonROTR32by2fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h1111aaaa;
$stop;
end
endmodule
| 6.758934 |
module TbNeokeonROTR32by5fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outputData;
NeokeonROTR32by5fun neokeonROTR32by5fun (
.inDataWord(inDataWord),
.outputData(outputData)
);
always begin
#(inClkp);
inDataWord = 32'h00800080;
$stop;
end
endmodule
| 6.758934 |
module TBreg ();
reg [31:0] A, B;
reg clk, rst = 1, en = 1;
wire [31:0] AA;
genvar j;
generate
for (j = 0; j <= 31; j = j + 8) begin : row
regmaster Num1 (
A[j+7:j],
clk,
rst,
en,
AA[j+7:j]
);
end
endgenerate
initial begin
#800 clk = 0;
rst = 0;
A = 32'b01101100;
#2000 clk = 1;
#1500 clk = 0;
#2000 clk = 1;
#1500 clk = 0;
#2000 clk = 1;
#1500 clk = 0;
#450 $stop;
end
endmodule
| 6.756139 |
module tbriscv;
reg rst_n;
reg clk;
riscv_top DUT (
.rst_n(rst_n),
.clk (clk)
);
initial begin
clk = 1'b0;
#50;
repeat (79) begin
clk = 1'b1;
#50 clk = 1'b0;
#50;
end
clk = 1'b1;
#50;
// dumped values till 2 us
end
// "Constant Pattern"
// Start Time = 0 ns, End Time = 2 us, Period = 0 ns
initial begin
rst_n = 1'b0;
#100;
rst_n = 1'b1;
#9000;
// dumped values till 2 us
end
initial #10000 $stop;
endmodule
| 6.813861 |
module TBT (
clk,
rst,
start,
data,
en,
addr,
fin,
result
);
input clk, rst, start;
input [4 : 0] data;
output en, fin;
output [4 : 0] addr, result;
endmodule
| 6.843925 |
module Top(
clk,
rst_n,
);
input clk , rst_n;
wire clk_out;
time_change u1(clk,rst_n,clk_out);
endmodule
| 7.232326 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureAbnormalityDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBtemperatureAbnormalityDetector;
// Inputs
reg [4:0] factotyBaseTemp;
reg [3:0] factotyTempCoef;
reg [3:0] tempSensorValue;
// Outputs
wire lowTempAbnormality;
wire highTempAbnormality;
// Instantiate the Unit Under Test (UUT)
temperatureAbnormalityDetector uut (
.factotyBaseTemp(factotyBaseTemp),
.factotyTempCoef(factotyTempCoef),
.tempSensorValue(tempSensorValue),
.lowTempAbnormality(lowTempAbnormality),
.highTempAbnormality(highTempAbnormality)
);
initial begin
factotyBaseTemp = 5'b10101;
factotyTempCoef = 4'b1111;
tempSensorValue = 4'b1100;
#10
factotyBaseTemp = 5'b10011;
factotyTempCoef = 4'b1011;
tempSensorValue = 4'b1010;
#10
$finish;
end
endmodule
| 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBtemperatureAnalyzer;
// Inputs
reg [7:0] temperature;
// Outputs
wire lowTempAbnormality;
wire highTempAbnormality;
// Instantiate the Unit Under Test (UUT)
temperatureAnalyzer uut (
.temperature(temperature),
.lowTempAbnormality(lowTempAbnormality),
.highTempAbnormality(highTempAbnormality)
);
initial begin
temperature = 8'b00100000; //32
#10
temperature = 8'b00100101; //37
#10
temperature = 8'b00101000; //40
#10
$finish;
end
endmodule
| 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBtemperatureCalculator;
// Inputs
reg [4:0] factotyBaseTemp;
reg [3:0] factotyTempCoef;
reg [3:0] tempSensorValue;
// Outputs
wire [7:0] temperature;
// Instantiate the Unit Under Test (UUT)
temperatureCalculator uut (
.factotyBaseTemp(factotyBaseTemp),
.factotyTempCoef(factotyTempCoef),
.tempSensorValue(tempSensorValue),
.temperature(temperature)
);
initial begin
factotyBaseTemp = 5'b10101;
factotyTempCoef = 4'b1111;
tempSensorValue = 4'b1100;
#10
factotyBaseTemp = 5'b10011;
factotyTempCoef = 4'b1011;
tempSensorValue = 4'b1010;
#10
$finish;
end
endmodule
| 8.163945 |
module TBT_tb;
//Clock period
parameter cyc = 30;
parameter dataWidth = 5;
parameter memWidth = 5;
parameter SEQ = 33;
reg [dataWidth - 1 : 0] dataROM [0 : SEQ - 1];
reg [ memWidth - 1 : 0] maxSize;
reg clk, rst, start;
reg [dataWidth - 1 : 0] data;
wire fin, en;
wire [dataWidth - 1 : 0] result;
wire [ memWidth - 1 : 0] addr;
//TBT module
TBT tbt (
.clk(clk),
.rst(rst),
.start(start),
.data(data),
.en(en),
.addr(addr),
.fin(fin),
.result(result)
);
always #(cyc / 2) clk = ~clk;
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, tbt);
$fsdbDumpfile("TBT_syn.fsdb");
`else
$fsdbDumpfile("TBT.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
$display(" ");
//Init ROM
$readmemb("info.dat", dataROM);
maxSize = 5'd31;
rst = 1'b0;
clk = 1'b0;
start = 1'b0;
data = 'hz;
@(negedge clk) rst = 1'b1;
#(cyc);
rst = 1'b0;
#(cyc);
@(negedge clk) start = 1'b1;
while (fin == 0) begin
if (en && addr <= maxSize) begin
data = dataROM[addr];
#(cyc / 2);
end else begin
data = 'hz;
end
@(negedge clk);
end
$display(" ");
$display("Result = %d , Answer = %d", $signed(result), $signed(dataROM[32]));
if (result == dataROM[32]) begin
$display("!!!!! ACCEPTED !!!!!");
end else begin
$display("WRONG ANSWER QAQ");
end
$display(" ");
$finish;
end
initial begin
#`End_CYCLE;
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
endmodule
| 8.294132 |
module tbuart (
input ser_rx
);
reg [3:0] recv_state;
reg [2:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [8*50-1:0] recv_buf_data; // 50 characters. Increase as needed for tests.
reg clk;
initial begin
clk <= 1'b0;
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
end
// NOTE: Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
// bit ~= 64 kbaud. Not tuned to any particular UART. Most run at
// 9600 baud default and will bounce up to higher baud rates when
// passed specific command words.
always #1500 clk <= (clk === 1'b0);
always @(posedge clk) begin
recv_divcnt <= recv_divcnt + 1;
case (recv_state)
0: begin
if (!ser_rx) recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2 * recv_divcnt > 3'd3) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > 3'd3) begin
// 0x0a = '\n'
if (recv_pattern == 8'h0a) begin
$display("output: %s", recv_buf_data);
end else begin
recv_buf_data <= {recv_buf_data, recv_pattern};
end
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > 3'd3) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
endmodule
| 8.711715 |
module TbUartRx();
localparam clockRate = 76_800_000;
localparam uartRate = 12_000_000;
localparam real clockDt = 1_000_000_000.0 / clockRate;
localparam real uartDt = 1_000_000_000.0 / uartRate;
reg clk = 0;
reg uartClk = 0;
reg uart = 1;
wire available;
wire [7 : 0] data;
integer nIteration = 100_000;
integer iteration = 0;
integer value = 0;
reg finish = 0;
task send;
input [7 : 0] byte;
input real idleWait;
begin
uart = 1; // Idle
#uartDt uart = 0; // Start
#uartDt uart = byte[0]; // Bit 0
#uartDt uart = byte[1]; // Bit 1
#uartDt uart = byte[2]; // Bit 2
#uartDt uart = byte[3]; // Bit 3
#uartDt uart = byte[4]; // Bit 4
#uartDt uart = byte[5]; // Bit 5
#uartDt uart = byte[6]; // Bit 6
#uartDt uart = byte[7]; // Bit 7
#uartDt uart = 1; // Stop
#idleWait;
end
endtask
always #(clockDt * 0.5) clk = ~clk;
always #(uartDt * 0.5) uartClk = ~uartClk;
initial
begin
#(uartDt);
for (iteration = 0; iteration < nIteration; iteration = iteration + 1)
send(iteration[7 : 0], uartDt * $itor($urandom() & 24'hFFFFFF) / (2.0 ** 24.0)); // The $urandom distribution is not uniform, the AND operation improves the generator values
#(uartDt);
finish = 1;
end
always @(posedge clk)
begin
if (available)
begin
if (data != value)
begin
$display("Iteration %1d: Received 2'h%2h instead of 2'h%2h", iteration, data, value);
$finish;
end
value = (value == 255) ? 0 : value + 1;
end
if (finish)
begin
$display("No errors found!");
$finish;
end
end
UartRx #
(
.clockRate(clockRate),
.uartRate(uartRate)
)
uartRx
(
.clk(clk),
.uart(uart),
.available(available),
.data(data)
);
endmodule
| 6.918471 |
module TbUartRxTest();
localparam clockRate = 60_000_000;
localparam baudRate = 12_000_000;
localparam cycleBits = 12;
localparam real clkDt = 1_000_000_000.0 / clockRate;
localparam real uartDt = 1_000_000_000.0 / baudRate;
reg clk = 0;
reg uartClk = 0;
reg uart = 1;
reg reset = 0;
wire cycle;
wire timingError;
wire dataError;
integer nIteration = 1024;
integer iteration = 0;
integer t = 0;
reg finish = 0;
task send;
input [7 : 0] byte;
begin
uart = 1; // Idle
#uartDt uart = 0; // Start
#uartDt uart = byte[0]; // Bit 0
#uartDt uart = byte[1]; // Bit 1
#uartDt uart = byte[2]; // Bit 2
#uartDt uart = byte[3]; // Bit 3
#uartDt uart = byte[4]; // Bit 4
#uartDt uart = byte[5]; // Bit 5
#uartDt uart = byte[6]; // Bit 6
#uartDt uart = byte[7]; // Bit 7
#uartDt uart = 1; // Stop
end
endtask
always #(clkDt * 0.5) clk = ~clk;
always #(uartDt * 0.5) uartClk = ~uartClk;
initial
begin
#(uartDt);
for (iteration = 0; iteration < nIteration; iteration = iteration + 1)
send(iteration[7 : 0]);
#(uartDt);
finish = 1;
end
always @(posedge clk)
begin
if (dataError)
begin
$display("Time %1d: Data error!", t);
$finish;
end
if (timingError)
begin
$display("Time %1d: Timing error!", t);
$finish;
end
if (finish)
begin
$display("No errors found!");
$finish;
end
t = t + 1;
end
UartRxTest #
(
.clockRate(clockRate),
.baudRate(uartRate),
.cycleBits(cycleBits)
)
uartRxTest
(
.clk(clk),
.uart(uart),
.reset(reset),
.cycle(cycle),
.dataError(dataError),
.timingError(timingError)
);
endmodule
| 7.101164 |
module tbuart_microwatt #(
parameter baud_rate = 115200
) (
input ser_rx
);
reg [3:0] recv_state;
reg [2:0] recv_divcnt;
reg [7:0] recv_pattern;
reg clk;
initial begin
clk <= 1'b0;
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
end
// Our simulation is in nanosecond steps and we want 5 clocks per bit,
// ie 10 clock transitions
always #(1000000000 / baud_rate / 10) clk <= (clk === 1'b0);
always @(posedge clk) begin
recv_divcnt <= recv_divcnt + 1;
case (recv_state)
0: begin
if (!ser_rx) recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2 * recv_divcnt > 3'd3) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > 3'd3) begin
recv_state <= 0;
$write("%c", recv_pattern);
$fflush();
end
end
default: begin
if (recv_divcnt > 3'd3) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
endmodule
| 7.536785 |
module tbufcam_buf (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en,
chk_addr0,
chk_match0,
chk_addr1,
chk_match1,
free
);
localparam WIDTH = 11;
input clk;
input rst;
input except;
input except_thread;
input [WIDTH-1:0] new_addr;
input new_thread;
input new_en;
input [WIDTH-1:0] chk_addr0;
output chk_match0;
input [WIDTH-1:0] chk_addr1;
output chk_match1;
output reg free;
reg [WIDTH-1:0] addr;
reg thread;
assign chk_match0 = chk_addr0 == addr && ~free;
assign chk_match1 = chk_addr1 == addr && ~free;
always @(posedge clk) begin
if (rst) begin
thread <= 1'b0;
addr <= {WIDTH{1'B0}};
free <= 1'b1;
end else begin
if (new_en) begin
thread <= new_thread;
addr <= new_addr;
free <= 1'b0;
end
if (except && except_thread == thread) free <= 1'b1;
end
end
endmodule
| 6.574546 |
module tbufcam (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en,
chk_addr0,
chk_match0,
chk_addr1,
chk_match1,
free
);
localparam WIDTH = 11;
localparam BUF_COUNT = 4;
input clk;
input rst;
input except;
input except_thread;
input [WIDTH-1:0] new_addr;
input new_thread;
input new_en;
input [WIDTH-1:0] chk_addr0;
output chk_match0;
input [WIDTH-1:0] chk_addr1;
output chk_match1;
output free;
wire [BUF_COUNT-1:0] new_en_buf[1:0];
wire [BUF_COUNT*2-1:0] chk_match0_buf;
wire [BUF_COUNT*2-1:0] chk_match1_buf;
wire [BUF_COUNT-1:0] free_buf[1:0];
wire [BUF_COUNT-1:0] first[1:0];
wire freeA, freeB;
generate
genvar k;
for (k = 0; k < BUF_COUNT; k = k + 1) begin : buffers_gen
tbufcam_buf bufA_mod (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en_buf[0][k],
chk_addr0,
chk_match0_buf[k],
chk_addr1,
chk_match1_buf[k],
free_buf[0][k]
);
tbufcam_buf bufB_mod (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en_buf[1][k],
chk_addr0,
chk_match0_buf[k+BUF_COUNT],
chk_addr1,
chk_match1_buf[k+BUF_COUNT],
free_buf[1][k]
);
end
endgenerate
assign chk_match0 = |chk_match0_buf;
assign chk_match1 = |chk_match1_buf;
// assign free=|free_buf;
assign new_en_buf[0] = first[0] & {BUF_COUNT{new_en & ~new_thread}};
bit_find_first_bit #(BUF_COUNT) firstFreeA_mod (
free_buf[0],
first[0],
freeA
);
assign new_en_buf[1] = first[1] & {BUF_COUNT{new_en & new_thread}};
bit_find_first_bit #(BUF_COUNT) firstFreeB_mod (
free_buf[1],
first[1],
freeB
);
assign free = new_thread ? freeB : freeA;
endmodule
| 6.974965 |
module tb_seg_595_static;
// parameter CNT_MAX = 25'd24;
reg sys_clk;
reg sys_rst_n;
wire ds;
wire shcp;
wire stcp;
wire oe;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
seg_595_static seg_595_static_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.ds (ds),
.shcp(shcp),
.stcp(stcp),
.oe (oe)
);
endmodule
| 8.260895 |
module tb_034();
//
// 1801VP1-034 pins, register mode
//
wire [15:0] lat_nAD;
reg [15:0] lat_nD;
reg lat_C;
reg lat_nDME;
integer lat_i;
//
// 1801VP1-034 pins, pio mode
//
wire [7:0] pio_D;
wire [7:0] pio_nC;
wire pio_nCOM;
reg [7:0] pio_A;
reg [7:0] pio_B;
reg pio_nR;
reg pio_nST;
reg pio_nCA;
reg pio_nCB;
reg pio_nCD;
reg nCOM;
//
// 1801VP1-034 pins, avic mode
//
wire nSB;
wire nVIRQ;
wire [12:2] av_nAD;
wire av_nBS;
wire [1:0] av_NC;
reg [12:2] nAD;
reg [9:0] av_A;
reg [5:0] av_V;
reg nIAKI;
reg nSYNC;
reg nDIN;
reg nVIRI;
reg nBS;
tri1 nRPLY;
//______________________________________________________________________________
//
// VP1-034 register mode test
//
initial
begin
lat_nD = 16'h0000;
lat_C = 0;
lat_nDME = 1;
for(lat_i=0; lat_i<16; lat_i=lat_i+1)
begin
#`SIM_DELAY
lat_nD = 16'h0001 << lat_i;
#`SIM_DELAY
lat_C = 1;
#`SIM_DELAY
lat_C = 0;
#`SIM_DELAY
lat_nD = 16'h0000;
#`SIM_DELAY
lat_nDME = 1;
#`SIM_DELAY
lat_nDME = 0;
end
end
//______________________________________________________________________________
//
// VP1-034 pio mode test
//
assign pio_nCOM = nCOM;
initial
begin
pio_A = 8'h00;
pio_B = 8'h00;
pio_nR = 1;
pio_nST = 1;
pio_nCA = 1;
pio_nCB = 1;
pio_nCD = 1;
nCOM = 1;
#`SIM_DELAY
pio_A = 8'hA5;
#`SIM_DELAY
pio_nCA = 0;
#`SIM_DELAY
pio_nST = 0;
#`SIM_DELAY
pio_nST = 1;
#`SIM_DELAY
nCOM = 0;
#`SIM_DELAY
nCOM = 1;
#`SIM_DELAY
pio_nCA = 1;
#`SIM_DELAY
pio_nCD = 0;
#`SIM_DELAY
pio_B = 8'h8B;
#`SIM_DELAY
pio_nCB = 0;
#`SIM_DELAY
pio_nCB = 1;
#`SIM_DELAY
pio_nST = 0;
#`SIM_DELAY
nCOM = 0;
#`SIM_DELAY
nCOM = 1;
#`SIM_DELAY
pio_nST = 1;
#`SIM_DELAY
pio_nCB = 1;
#`SIM_DELAY
pio_nR = 0;
#`SIM_DELAY
pio_nR = 1;
#`SIM_DELAY
pio_nCB = 0;
#`SIM_DELAY
nCOM = 0;
#`SIM_DELAY
pio_nCB = 1;
end
//______________________________________________________________________________
//
// VP1-034 avic mode test
//
assign av_nBS = nBS;
assign av_nAD = nAD;
initial
begin
nAD = 13'hZZZZ;
av_A = 13'o01762 >> 3;
av_V = 8'o064 >> 2;
nIAKI = 1;
nSYNC = 1;
nDIN = 1;
nVIRI = 1;
nBS = 1;
#`SIM_DELAY
nVIRI = 0;
#`SIM_DELAY
nDIN = 0;
#`SIM_DELAY
nIAKI = 0;
#`SIM_DELAY
#`SIM_DELAY
nDIN = 1;
#`SIM_DELAY
nIAKI = 1;
nVIRI = 1;
#`SIM_DELAY
#`SIM_DELAY
nBS = 0;
nAD = 13'o01762 >> 2;
#`SIM_DELAY
nSYNC = 0;
#`SIM_DELAY
#`SIM_DELAY
nSYNC = 1;
nAD = 13'o11762 >> 2;
#`SIM_DELAY
nSYNC = 0;
#`SIM_DELAY
#`SIM_DELAY
nSYNC = 1;
end
//_____________________________________________________________________________
//
// Instantiation modules under test
//
//
vp_034 vp_034_reg
(
.PIN_RC(2'b10),
.PIN_nAD(lat_nAD),
.PIN_nD(lat_nD),
.PIN_nDME(lat_nDME),
.PIN_C(lat_C)
);
vp_034 vp_034_pio
(
.PIN_RC(2'b01),
.PIN_nAD({pio_D, pio_nC}),
.PIN_nD({pio_B, pio_A}),
.PIN_nDME(pio_nR),
.PIN_C(pio_nST),
.PIN_nCA(pio_nCA),
.PIN_nCB(pio_nCB),
.PIN_nCD(pio_nCD),
.PIN_nCOM(pio_nCOM)
);
vp_034 vp_034_avic
(
.PIN_RC(2'b11),
.PIN_nAD({av_NC, av_nBS, av_nAD[12:2], nVIRQ, nSB}),
.PIN_nD({av_V, av_A}),
.PIN_nDME(nIAKI),
.PIN_nCA(nSYNC),
.PIN_nCB(nDIN),
.PIN_nCD(nVIRI),
.PIN_nCOM(nRPLY)
);
endmodule
| 6.732185 |
module: miniRISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_1;
// Inputs
reg clk;
reg rst;
// Outputs
wire [31:0] out1;
wire [31:0] out2;
// Instantiate the Unit Under Test (UUT)
miniRISC uut (
.clk(clk),
.rst(rst),
.out1(out1),
.out2(out2)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
#5 rst = 0;
// Wait 100 ns for global reset to finish
#1000 $finish;
// Add stimulus here
end
endmodule
| 6.91385 |
module tb_1553;
reg tb_data_clk = 0;
reg tb_rst = 0;
wire [ 1:0] tb_dout;
wire tb_en_dout;
reg [15:0] tb_tdata;
reg tb_tvalid;
reg [ 7:0] tb_tuser;
wire tb_tready;
//1ns
localparam CLK_PERIOD = 50;
localparam RST_PERIOD = 100;
//device under test
util_axis_1553_encoder #(
.clock_speed(20000000)
) dut (
.aclk(tb_data_clk),
.arstn(~tb_rst),
//slave input
.s_axis_tdata(tb_tdata),
.s_axis_tvalid(tb_tvalid),
.s_axis_tuser(tb_tuser),
.s_axis_tready(tb_tready),
//diff output
.diff(tb_dout),
.en_diff(tb_en_dout)
);
//reset
initial begin
tb_rst <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_1553_enc.vcd");
$dumpvars(0, tb_1553);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 2);
end
//produce data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_tdata <= 16'hFFFF;
tb_tuser <= 8'h8F;
tb_tvalid <= 1'b0;
end else begin
tb_tvalid <= 1'b1;
if (tb_tready == 1'b1) begin
tb_tdata <= tb_tdata + 1;
end
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 6.751604 |
module tb_1bit_full_adder;
// Inputs
reg a, b, c;
// Outputs
wire sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
fa_1bit uut (
.a(a),
.b(b),
.cin(c),
.sum(sum),
.cout(cout)
);
initial begin
$dumpfile("tb_1bit_full_adder.vcd");
$dumpvars(0, tb_1bit_full_adder);
// Initialize Inputs
a = 0;
b = 0;
c = 0;
#30 $finish;
end
always #4 a = ~a;
always #2 b = ~b;
always #1 c = ~c;
endmodule
| 6.879291 |
module: miniRISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_2;
// Inputs
reg clk;
reg rst;
// Outputs
wire [31:0] out1;
wire [31:0] out2;
// Instantiate the Unit Under Test (UUT)
miniRISC uut (
.clk(clk),
.rst(rst),
.out1(out1),
.out2(out2)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
#5 rst = 0;
// Wait 100 ns for global reset to finish
#3000 $finish;
// Add stimulus here
end
endmodule
| 6.91385 |
module tb_2_input_nand_gate;
// Inputs
reg A, B;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
nand2 uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("tb_2_input_nand_gate.vcd");
$dumpvars(0, tb_2_input_nand_gate);
// Initialize Inputs
A = 0;
B = 0;
#20 $finish;
end
always #2 A = ~A;
always #1 B = ~B;
endmodule
| 7.127038 |
module tb_32bit_carry_ripple_adder;
parameter N = 32;
// Inputs
reg [N-1:0] input_a = 0;
reg [N-1:0] input_b = 0;
reg carry_in = 0;
// Outputs
wire [N-1:0] final_sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
ripple_carry_adder #(
.WIDTH(N)
) uut (
.input_a (input_a),
.input_b (input_b),
.carry_in (carry_in),
.final_sum(final_sum),
.carry_out(carry_out)
);
initial begin
$dumpfile("tb_32bit_carry_ripple_adder.vcd");
$dumpvars(0, tb_32bit_carry_ripple_adder);
#30 $finish;
end
always #1 input_a = $random;
always #2 input_b = $random;
endmodule
| 8.043136 |
module tbRegFile32;
reg Clock, Reset, RegWrite;
reg [4:0] ReadReg1, ReadReg2, WriteRegNo;
reg [31:0] WriteData;
wire [31:0] ReadData1, ReadData2;
RegFile_32 rgf (
ReadData1,
ReadData2,
Clock,
Reset,
RegWrite,
ReadReg1,
ReadReg2,
WriteRegNo,
WriteData
);
initial begin
$monitor(
$time,
": Reset = %b, RegWrite = %h, ReadReg1 = %h, ReadReg2 = %h, WriteRegNo = %b, WriteData = %h, ReadData1 = %h, ReadData2 = %h.",
Reset, RegWrite, ReadReg1, ReadReg2, WriteRegNo, WriteData, ReadData1, ReadData2);
#0 Clock = 1'b1;
ReadReg1 = 5'b00000;
ReadReg2 = 5'b11111;
Reset = 1'b1;
#2 Reset = 1'b0;
#10 Reset = 1'b1;
RegWrite = 1'b1;
WriteData = 32'h00000001;
WriteRegNo = 5'b00000;
repeat (31) begin
#10 WriteData = WriteData + 32'h00000001;
WriteRegNo = WriteRegNo + 5'b00001;
end
#10 RegWrite = 1'b0;
ReadReg1 = 5'b00000;
ReadReg2 = 5'b00001;
repeat (15) begin
#10 ReadReg1 = ReadReg1 + 5'b00010;
ReadReg2 = ReadReg2 + 5'b00010;
end
#10 $finish;
end
always #5 Clock = ~Clock;
endmodule
| 6.672416 |
module tb_3_input_and_gate (); // Test bench fortb_ and_gate.v
reg a, b, c; // a reg, to allow us to assign the input, and a wire to receive the output
wire out;
three_input_and_gate uut (
out,
a,
b,
c
); // this instantiates a and gate, uut is a label
initial begin
a = 1'b0; // here we apply inputs to the gate
b = 1'b0;
c = 1'b0;
#10;
a = 1'b0;
b = 1'b0;
c = 1'b1;
#10;
a = 1'b0;
b = 1'b1;
c = 1'b0;
#10;
a = 1'b0;
b = 1'b1;
c = 1'b1;
#10;
a = 1'b1;
b = 1'b0;
c = 1'b0;
#10;
a = 1'b1;
b = 1'b0;
c = 1'b1;
#10;
a = 1'b1;
b = 1'b1;
c = 1'b0;
#10;
a = 1'b1;
b = 1'b1;
c = 1'b1;
#10;
end
// set up the monitoring
initial begin
$monitor("a=%b, b=%b, c=%b, out=%b, time=%t\n", a, b, c, out, $time);
end
endmodule
| 6.993267 |
module tb_3_input_or_gate (); // Test bench fortb_ and_gate.v
reg a, b, c; // a reg, to allow us to assign the input, and a wire to receive the output
wire out;
three_input_or_gate uut (
out,
a,
b,
c
); // this instantiates a and gate, uut is a label
initial begin
a = 1'b0; // here we apply inputs to the gate
b = 1'b0;
c = 1'b0;
#10;
a = 1'b0;
b = 1'b0;
c = 1'b1;
#10;
a = 1'b0;
b = 1'b1;
c = 1'b0;
#10;
a = 1'b0;
b = 1'b1;
c = 1'b1;
#10;
a = 1'b1;
b = 1'b0;
c = 1'b0;
#10;
a = 1'b1;
b = 1'b0;
c = 1'b1;
#10;
a = 1'b1;
b = 1'b1;
c = 1'b0;
#10;
a = 1'b1;
b = 1'b1;
c = 1'b1;
#10;
end
// set up the monitoring
initial begin
$monitor("a=%b, b=%b, c=%b, out=%b, time=%t\n", a, b, c, out, $time);
end
endmodule
| 6.920155 |
module dmaer (
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
always @(negedge rst_n) begin
disable main_loop;
req = 1'b0;
rnw = 1'b1;
inprogress = 1'b0;
end
always begin : main_loop
wait (rst_n);
wait (start);
begin : dma_loop
forever begin
inprogress <= 1'b1;
rnw <= rnw_in;
req <= 1'b1;
@(negedge ack);
if (!start) disable dma_loop;
end
end
req <= 1'b0;
wait (done); /*@(posedge done);*/
inprogress <= 1'b0;
end
endmodule
| 7.059175 |
module tb_RTL ();
reg A, B, C, D;
reg [1:0] Sin;
wire out;
m4to1_MUX_RTL test_RTLMUX (
out,
Sin,
A,
B,
C,
D
);
initial begin
A = 0;
B = 0;
C = 0;
D = 1;
Sin = 2'b11;
#250 A = 0;
B = 0;
C = 0;
D = 1;
Sin = 2'b11;
#250 A = 0;
B = 0;
C = 1;
D = 0;
Sin = 2'b10;
#250 A = 0;
B = 1;
C = 0;
D = 1;
Sin = 2'b01;
#250 A = 1;
B = 0;
C = 0;
D = 0;
Sin = 2'b00;
end
endmodule
| 6.587275 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(et),
.gt(gt)
);
initial begin
A = 8'b00000001;
B = 8'b00000001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
A = 8'b00000010;
B = 8'b00000001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 8'b00000001;
B = 8'b00000010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
$finish;
end
endmodule
| 6.843472 |
module: abc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_abc;
// Inputs
reg clk;
reg ce;
reg signed [11:0] a;
reg signed [11:0] b;
reg signed [11:0] c;
// Outputs
wire signed [24:0] y;
// Instantiate the Unit Under Test (UUT)
abc uut (
.clk(clk),
.ce(ce),
.a(a),
.b(b),
.c(c),
.y(y)
);
integer i;
initial begin
// Initialize Inputs
clk = 0;
ce = 1;
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// 16 initial clock ticks
for(i = 0; i < 16; i = i + 1) begin
clk = 0; #1;
clk = 1; #1;
end
#10;
// test 1
a = 4;
b = 6;
c = 7;
// 4 clock ticks
for(i = 0; i < 4; i = i + 1) begin
clk = 0; #1;
clk = 1; #1;
end
clk = 0; #1;
if(y == (a+b)*c) $stop;
clk = 1; #1;
if(y != (a+b)*c) $stop;
#10;
// test 2
a = -4;
b = 26;
c = 23;
// 4 clock ticks
for(i = 0; i < 4; i = i + 1) begin
clk = 0; #1;
clk = 1; #1;
end
clk = 0; #1;
if(y == (a+b)*c) $stop;
clk = 1; #1;
if(y != (a+b)*c) $stop;
#10;
$stop;
end
endmodule
| 6.61642 |
module tb_adv_fsm;
reg clk, reset, a, b;
wire z;
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
abro UUT (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.z(z)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
a = 0;
b = 0;
#period;
// goes to state IDLE
if (z !== 0) begin
$display("test 1 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// // check reset with a,b=1
// reset = 1; a = 1; b=1;
// #period;
// // goes to state IDLE
// if(z!==0) begin
// $display("test 2 failed");
// $finish;
// end
// else $display("a=%b, b=%b z=%b",a,b,z);
// start fsm
reset = 0;
a = 0;
b = 0;
#period;
// goes to state IDLE
if (z !== 0) begin
$display("test 3 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// case: a then b
a = 1;
b = 0;
#period;
a = 0;
b = 1;
#period;
// goes to state IDLE
if (z !== 1) begin
$display("test 4 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// check if it goes back to 0
#period;
// goes to state IDLE
if (z !== 0) begin
$display("test 5 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// case: a , gap, then b
#period;
a = 1;
b = 0;
#period;
#period;
#period;
#period;
a = 0;
b = 1;
#period;
// goes to state IDLE
if (z !== 1) begin
$display("test 6 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// case: b then a
#period;
a = 0;
b = 1;
#period;
a = 1;
b = 0;
#period;
// goes to state IDLE
if (z !== 1) begin
$display("test 7 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// case: b , gap, then a
#period;
a = 0;
b = 1;
#period;
#period;
#period;
#period;
a = 1;
b = 0;
#period;
// goes to state IDLE
if (z !== 1) begin
$display("test 8 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
// case:a and b together
#period;
a = 1;
b = 1;
#period;
// goes to state IDLE
if (z !== 1) begin
$display("test 8 failed");
$finish;
end else $display("a=%b, b=%b z=%b", a, b, z);
$display("all tests passed");
$finish;
end
endmodule
| 7.116394 |
module tb_accumCol;
parameter DATA_WIDTH = 8; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output height of largest matrix
parameter MAX_OUT_COLS = 128; // output width of largest possible matrix
parameter SYS_ARR_COLS = 16; // height of the systolic array
localparam NUM_ACCUM_ROWS = MAX_OUT_ROWS * (MAX_OUT_COLS / SYS_ARR_COLS);
reg clk;
reg reset; // clears array and sets it to 0
reg rd_en; // reads the data at rd_addr when high
reg wr_en; // writes (and accumulates) data to wr_addr when high
reg [$clog2(NUM_ACCUM_ROWS)-1:0] rd_addr;
reg [$clog2(NUM_ACCUM_ROWS)-1:0] wr_addr;
wire [DATA_WIDTH-1:0] rd_data;
reg [DATA_WIDTH-1:0] wr_data;
accumCol test_column (
.clk(clk),
.reset(reset),
.rd_en(rd_en),
.wr_en(wr_en),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.rd_data(rd_data),
.wr_data(wr_data)
);
integer count, i;
initial begin
clk = 1'b0;
count = 0;
rd_en = 1'b1;
wr_en = 1'b1;
end // initial
always begin
#10 clk = ~clk;
end // always
always @(negedge clk) begin
i = count - 2;
if (count == 0) begin
reset = 1'b1;
end // if (count == 0)
else if (count == 1) begin
reset = 1'b0;
end // else if (count == 1)
else begin
wr_data = i % 8;
rd_addr = (i - 1) % 8;
wr_addr = i % 8;
end // else
if (i == 64) begin
reset = 1'b1;
wr_en = 1'b0;
end // if (count == 133)
else if (count == 70) begin
$stop;
end // if (count == 135)
/*if (count > 1) begin
if (count % 2 == 1) begin
rd_en = 1'b1;
wr_en = 1'b1;
end // if (count % 2 == 1)
else begin
rd_en = 1'b0;
wr_en = 1'b0;
end // else
end // if (count > 1)*/
count = count + 1;
end
endmodule
| 6.709093 |
module tb_aclk_timegen ();
reg clk, reset, reset_count, fast_watch;
wire one_minute, one_second;
aclk_timegen dut (
clk,
reset,
reset_count,
fast_watch,
one_minute,
one_second
);
initial begin
clk = 1;
forever #5 clk = !clk;
end
initial begin
#15;
reset = 1;
#30 reset = 0;
fast_watch = 0;
#10;
#20000;
$finish;
end
endmodule
| 7.465918 |
module TB_acm_controller ();
wire clk;
reg reset;
wire [7:0] ACM_rdata;
wire [7:0] ACM_wdata;
wire [7:0] ACM_addr;
wire ACM_wen;
wire ACM_reset;
wire ACM_clk;
reg wb_cyc_i, wb_stb_i, wb_we_i;
reg [15:0] wb_adr_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
wire wb_ack_o;
acm_controller acm_controller_inst (
.wb_clk_i (clk),
.wb_rst_i (reset),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_we_i (wb_we_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.acm_wdata(ACM_wdata),
.acm_rdata(ACM_rdata),
.acm_addr (ACM_addr),
.acm_wen (ACM_wen),
.acm_clk (ACM_clk),
.acm_reset(ACM_reset)
);
reg [7:0] clk_counter;
initial begin
$dumpvars();
clk_counter <= 8'b0;
reset <= 1'b1;
`ifdef DEBUG
$display("sim: starting sim");
`endif
#500 reset <= 1'b0;
`ifdef DEBUG
$display("sim: clearing reset");
`endif
#80000 $display("FAILED: simulation timed out");
$finish;
end
assign clk = clk_counter < ((`CLK_PERIOD) / 2);
always begin
#1 clk_counter <= (clk_counter == `CLK_PERIOD - 1 ? 32'b0 : clk_counter + 1);
end
/*ACM goodies*/
`ifdef MODELSIM
AB AB_inst (
.ACMADDR (ACM_addr),
.ACMCLK (ACM_clk),
.ACMRDATA(ACM_rdata),
.ACMWDATA(ACM_wdata),
.ACMRESET(~reset),
.ACMWEN (ACM_wen)
);
`else
reg [7:0] memdump[255:0];
reg [7:0] temp;
assign ACM_rdata = temp;
reg [7:0] prev;
always @(posedge ACM_clk) begin
if (~ACM_reset) begin
temp <= 8'b0;
end else begin
if (ACM_wen) begin
memdump[ACM_addr] <= ACM_wdata;
`ifdef DEBUG
$display("ACM: got data: %x", ACM_wdata);
`endif
end else begin
prev <= ACM_addr;
temp <= memdump[ACM_addr];
`ifdef DESPERATE_DEBUG
if (prev !== ACM_addr) begin
$display("ACM: sent data: %x", memdump[ACM_addr]);
end
`endif
end
end
end
`endif
reg [1:0] state;
`define TB_STATE_WRITE 2'd0
`define TB_STATE_READ 2'd1
`define TB_STATE_WAIT 2'd2
reg [15:0] counter;
always @(posedge clk) begin
wb_cyc_i <= 1'b0;
wb_stb_i <= 1'b0;
if (reset) begin
state <= `TB_STATE_WRITE;
counter <= 16'b0;
end else begin
case (state)
`TB_STATE_WRITE: begin
wb_we_i <= 1'b1;
wb_adr_i <= counter;
wb_dat_i <= counter;
wb_cyc_i <= 1'b1;
wb_stb_i <= 1'b1;
state <= `TB_STATE_WAIT;
`ifdef DEBUG
$display("wbm: write cmnd, data = %d, adr = %d", counter, counter);
`endif
end
`TB_STATE_READ: begin
wb_we_i <= 1'b0;
wb_cyc_i <= 1'b1;
wb_stb_i <= 1'b1;
wb_adr_i <= counter;
state <= `TB_STATE_WAIT;
`ifdef DEBUG
$display("wbm: read cmnd, adr = %d", counter);
`endif
end
`TB_STATE_WAIT: begin
if (wb_ack_o & wb_we_i) begin
state <= `TB_STATE_READ;
`ifdef DEBUG
$display("wbm: write reply");
`endif
end
if (wb_ack_o & ~wb_we_i) begin
state <= `TB_STATE_WRITE;
counter <= counter + 1;
/*only check analogue quag reads*/
if (counter > 16'b0 && counter <= 16'd40) begin
if ((counter & 16'h00ff) !== wb_dat_o) begin
$display("FAILED: data failure - got %x expected %x", wb_dat_o, counter & 16'h00ff);
$finish;
end else if (counter == 16'd40) begin
$display("PASSED");
$finish;
end
end
`ifdef DEBUG
$display("wbm: read reply, data = %d", wb_dat_o);
`endif
end
end
endcase
end
end
endmodule
| 7.588986 |
module tb ();
reg clk, reset;
wire [31:0] porta, portb;
ACog cog0 (
.clk_in (clk),
.reset_in(reset)
);
always #6.25 clk = ~clk;
initial begin
$dumpfile("acog.vcd");
$dumpvars(0, tb);
clk = 0;
reset = 1;
#61 reset = 0;
#160000 $finish;
end
endmodule
| 7.195167 |
module tb_action_engine #(
parameter STAGE = 0,
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter ACT_LEN = 25
) ();
reg clk;
reg rst_n;
//signals from lookup to ALUs
reg [ PHV_LEN-1:0] phv_in;
reg phv_valid_in;
reg [ACT_LEN*25-1:0] action_in;
reg action_valid_in;
//signals output from ALUs
wire [ PHV_LEN-1:0] phv_out;
wire phv_valid_out;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
setup new
*/
phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE)
/*
extract values from PHV
*/
phv_in <= {
48'h111111111111, 48'h222222222222, 172'b1, 100'hfffffffffffffffffffffffff, 400'b0, 356'b0
};
phv_valid_in <= 1'b1;
//switch the con_6B_7 with con_6B_6
// action_in <= {4'b0001, 5'd6, 5'd7, 11'b0, 600'b0};
action_in <= 625'b0;
action_valid_in <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE)
/*
extract values from imm
*/
phv_in <= {
48'hffffffffffff, 48'heeeeeeeeeeee, 672'b0, 356'b0
};
phv_valid_in <= 1'b1;
//switch the con_6B_7 with con_6B_6
action_in <= {4'b1010, 5'd6, 16'hffff, 600'b0};
action_valid_in <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE)
/*
test store action
*/
phv_in <= {
384'b0, 32'hffffffff, 224'b0, 128'b0, 356'b0
};
phv_valid_in <= 1'b1;
//switch the con_6B_7 with con_6B_6
action_in <= {200'b0, 4'b1000, 5'd7, 16'd7, 400'b0};
action_valid_in <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE)
/*
empty actions to take (return the original value)
*/
phv_in <= {
48'hffffffffffff, 48'heeeeeeeeeeee, 672'b0, 356'b0
};
phv_valid_in <= 1'b1;
//this is an invalid action
action_in <= {4'b0000, 5'd6, 16'hffff, 600'b0};
action_valid_in <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE)
//reset to zeros.
phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
action_in <= 625'b0;
action_valid_in <= 1'b0;
#(2 * CYCLE);
end
action_engine #(
.STAGE (STAGE),
.PHV_LEN(),
.ACT_LEN()
) action_engine (
.clk (clk),
.rst_n(rst_n),
//signals from lookup to ALUs
.phv_in(phv_in),
.phv_valid_in(phv_valid_in),
.action_in(action_in),
.action_valid_in(action_valid_in),
//signals output from ALUs
.phv_out(phv_out),
.phv_valid_out(phv_valid_out)
);
endmodule
| 8.348227 |
module TB_adc_config_mux();
wire sys_rst;
wire sys_clk;
/***************** DUT ***************/
adc_config_mux #(
.INTERLEAVED (0)
) adc_config_mux_inst (
.clk (sys_clk),
.rst (sys_rst),
.request (1'b0),
.ddrb_i (1'b0),
.mode_i (1'b0),
.config_start_i (1'b0),
.config_busy_o (),
.config_data_i (1'b0),
.config_addr_i (1'b0),
.ddrb_o (),
.dcm_reset_o (),
.mode_o (),
.ctrl_clk_o (),
.ctrl_strb_o (),
.ctrl_data_o ()
);
/****** System Signal generations ******/
reg [31:0] sys_clk_counter;
reg reset;
assign sys_rst = reset;
initial begin
$dumpvars;
sys_clk_counter <= 32'b0;
reset <= 1'b1;
#20
reset <= 1'b0;
`ifdef DEBUG
$display("sys: reset cleared");
`endif
#`SIMLENGTH
$display("PASSED");
$finish;
end
assign sys_clk = sys_clk_counter < ((`SYS_CLK_PERIOD) / 2);
always begin
#1 sys_clk_counter <= (sys_clk_counter == `SYS_CLK_PERIOD - 1 ? 32'b0 : sys_clk_counter + 1);
end
endmodule
| 7.801573 |
module tb_adc_diff;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg [7:0] tb_data;
reg tb_valid;
reg tb_valid_off;
reg tb_valid_toggle = 0;
reg tb_enable;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_adc_diff #(
.WORD_WIDTH(1),
.BYTE_WIDTH(1),
.UP_THRESH(64),
.LOW_THRESH(-64),
.NO_DIFF_WAIT(50)
) dut (
.clk(tb_data_clk),
.rstn(~tb_rst),
// diff output
.diff_out(),
// write input
.wr_data(tb_data),
.wr_valid(tb_valid),
.wr_enable(tb_enable)
);
//reset
initial begin
tb_rst <= 1'b1;
tb_valid_off <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
//#30000;
//tb_valid_off <= 1'b0;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_adc_diff.vcd");
$dumpvars(0, tb_adc_diff);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 4);
end
//valid off/on
always begin
tb_valid_toggle <= ~tb_valid_toggle;
#(CLK_PERIOD / 2);
end
//product data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_data <= 0;
tb_valid <= 0;
tb_enable <= 0;
end else begin
tb_enable <= $random % 2;
tb_valid <= tb_valid_off & tb_valid_toggle;
tb_data <= tb_data;
if (tb_valid == 1'b1) begin
tb_data <= tb_data + 1;
end
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 8.588449 |
module tb;
initial begin $$dumpfile("build/prefix_adder.vcd"); $$dumpvars(0,tb); end
reg [$n:0] term0,term1;
reg cin;
wire [$n:0] sum;
wire cout;
prefix_adder p0(term0,term1,cin,sum,cout);
initial begin
$test
end
endmodule
| 7.280203 |
module.
`timescale 1ns/1ns
`include "add1bit.v"
module tb_add1bit;
reg a, b, c_in;
wire sum, c_out;
add1bit test_add1bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add1bit.vcd");
$dumpvars(0, tb_add1bit);
$monitor("0x%0h + 0x%0h = 0x%0h (carry = %d)", a, b, sum, c_out);
{a, b} = 2'b00;
c_in = c_out; #10;
{a, b} = 2'b01;
c_in = c_out; #10;
{a, b} = 2'b10;
c_in = c_out; #10;
{a, b} = 2'b11;
c_in = c_out; #10;
$display("success.");
end // initial begin
endmodule
| 6.603418 |
module.
`timescale 1ns/1ns
`include "add2bit.v"
module tb_add1bit;
reg [1:0] a, b;
reg c_in;
wire [1:0] sum;
wire c_out;
add2bit test_add2bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add2bit.vcd");
$dumpvars(0, tb_add1bit);
$monitor("0x%0h + 0x%0h = 0x%0h (carry = %d)", a, b, sum, c_out);
{a, b} = 4'b0000;
c_in = c_out; #10;
{a, b} = 4'b0001;
c_in = c_out; #10;
{a, b} = 4'b0010;
c_in = c_out; #10;
{a, b} = 4'b0011;
c_in = c_out; #10;
{a, b} = 4'b0100;
c_in = c_out; #10;
{a, b} = 4'b0101;
c_in = c_out; #10;
{a, b} = 4'b0110;
c_in = c_out; #10;
{a, b} = 4'b0111;
c_in = c_out; #10;
{a, b} = 4'b1000;
c_in = c_out; #10;
{a, b} = 4'b1001;
c_in = c_out; #10;
{a, b} = 4'b1010;
c_in = c_out; #10;
{a, b} = 4'b1011;
c_in = c_out; #10;
{a, b} = 4'b1111;
c_in = c_out; #10;
$display("success.");
end // initial begin
endmodule
| 6.603418 |
module.
`timescale 1ns/1ns
`include "add4bit.v"
module tb_add1bit;
reg [3:0] a, b;
reg c_in;
wire [3:0] sum;
wire c_out;
integer i;
add4bit test_add4bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add4bit.vcd");
$dumpvars(0, tb_add1bit);
$monitor("0x%0h + 0x%0h = 0x%0h (carry = %d)", a, b, sum, c_out);
for (i = 0; i < 256; i = i + 1) begin
{a, b} = i;
c_in = c_out;
#10;
end;
$display("success.");
end // initial begin
endmodule
| 6.603418 |
module AdderTestbench;
reg [7:0] in;
wire [7:0] out;
Adder dut (
in,
out
);
initial begin
in = 0;
$display("Teste 1: Entrada = 1");
in = 1;
#1 $display("Saida = %d", out);
$display("Teste 2: Entrada = 2");
in = 2;
end
initial begin
$monitor("Tempo: %0d\tEntrada: %d\tSaida: %d\n", $time, in, out);
end
endmodule
| 7.444627 |
module tb_adder_chains ();
parameter MIN_WIDTH = 8;
parameter ADDER_NUM = 4;
reg clk; // Clock
reg rst_n; // Asynchronous reset active low
reg [MIN_WIDTH * ADDER_NUM - 1:0] adder_din;
wire [MIN_WIDTH + ADDER_NUM - 1:0] adder_dout;
adder_chains #(
.MIN_WIDTH(MIN_WIDTH),
.ADDER_NUM(ADDER_NUM)
) dut (
.clk(clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.adder_din(adder_din),
.adder_dout(adder_dout)
);
initial begin
clk = 1'b0;
forever begin
#50 clk = ~clk;
end
end
initial begin
rst_n = 1'b1;
#5 rst_n = 1'b0;
#10 rst_n = 1'b1;
end
reg [MIN_WIDTH - 1:0] adder_split_din[ADDER_NUM - 1:0];
integer i;
initial begin
i = 0;
adder_din = 'b0;
forever begin
@(negedge clk)
for (i = 0; i < ADDER_NUM; i = i + 1) begin
adder_split_din[i] = (MIN_WIDTH)'($urandom_range(0, 2 ** MIN_WIDTH - 1));
adder_din[i*MIN_WIDTH+:MIN_WIDTH] = adder_split_din[i];
end
end
end
endmodule
| 7.097643 |
module tb_top;
// TB_SIGNALS
reg clk, reset_b;
reg [15:0] a_in;
reg [15:0] b_in;
reg carry_in;
reg CG;
wire [15:0] sum_out;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
adder_clk_gating uut (
.clk(clk),
.reset_b(reset_b),
.a_in(a_in),
.b_in(b_in),
.carry_in(carry_in),
.sum_out(sum_out),
.carry_out(carry_out),
.CG(CG)
);
initial begin
clk = 0;
CG = 1;
reset_b = 0;
#20;
reset_b = 1;
#10;
a_in = 16'hA5A5;
b_in = 16'h5A5A;
carry_in = 0;
#15000;
CG = 0;
a_in = 16'h1707;
b_in = 16'h2345;
#30000 $finish;
end
initial begin
$dumpfile("tb_adder_clk_gating.vcd");
$dumpvars(0, tb_top);
forever begin
#10 clk = ~clk;
end
end
endmodule
| 6.630961 |
module tb_adder_subtractor_4bit ();
reg [3:0] A;
reg [3:0] B;
reg sel;
wire [3:0] sum;
wire [3:0] sum_delay;
wire cout;
wire cout_delay;
adder_subtractor_4bit test_adder_subtractor_4bit (
.A(A),
.B(B),
.sel(sel),
.S(sum),
.cout(cout)
);
adder_subtractor_4bit_delay test_adder_subtractor_4bit_delay (
.A(A),
.B(B),
.sel(sel),
.S(sum_delay),
.cout(cout_delay)
);
initial begin
A <= 4'b0101;
B <= 4'b0000;
sel <= 1'b0;
#100;
A <= 4'b0011;
B <= 4'b0011;
sel <= 1'b0;
#100;
A <= 4'b0101;
B <= 4'b0001;
sel <= 1'b0;
#100;
// subtracting test
A <= 4'b0101;
B <= 4'b0001;
sel <= 1'b1;
#100;
A <= 4'b0101;
B <= 4'b0010;
sel <= 1'b1;
#100;
A <= 4'b0111;
B <= 4'b0110;
sel <= 1'b1;
#100;
$finish;
end
endmodule
| 6.53318 |
module tb_adder_subtractor_4bit_delay ();
reg [3:0] A;
reg [3:0] B;
reg sel;
wire [3:0] sum;
wire [3:0] sum_delay;
wire cout;
wire cout_delay;
adder_subtractor_4bit_delay test_adder_subtractor_4bit_delay (
.A(A),
.B(B),
.sel(sel),
.S(sum_delay),
.cout(cout_delay)
);
initial begin
sel = 1'b1;
A = 4'b1101;
B = 4'b1111;
#10;
A = 4'b1000;
B = 4'b0101;
#10;
A = 4'b0011;
B = 4'b1100;
#10;
A = 4'b0100;
B = 4'b0111;
#10;
sel = 1'b0;
A = 4'b1101;
B = 4'b1111;
#10;
A = 4'b1000;
B = 4'b0101;
#10;
A = 4'b0011;
B = 4'b1100;
#10;
A = 4'b0100;
B = 4'b0111;
$finish;
end
endmodule
| 6.53318 |
module tb_adder_tree;
parameter WORD_SIZE = 8;
parameter BANK_SIZE = 4;
reg clk;
reg rst_n;
reg [ WORD_SIZE*BANK_SIZE-1:0] in;
wire [(WORD_SIZE+1)*(BANK_SIZE/2)-1:0] out;
adder_tree #(
.WORD_SIZE(WORD_SIZE),
.BANK_SIZE(BANK_SIZE)
) _adder_tree (
.clk (clk),
.rst_n(rst_n),
.in (in),
.out (out)
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_adder_tree.vcd");
$dumpvars(0, tb_adder_tree);
#1 rst_n <= 1'bx;
clk <= 1'bx;
in <= 32'hxxxx_xxxx;
#(CLK_PERIOD) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
in <= 0;
repeat (5) @(posedge clk);
rst_n <= 1;
@(posedge clk);
in <= {8'd1, 8'd2, 8'd3, 8'd4};
repeat (2) @(posedge clk);
if (out !== {9'd3, 9'd7})
$display("result == ", 9'd3, ", ", 9'd7, " expected but ", out[17:9], ", ", out[8:0]);
in <= {8'd15, 8'd255, 8'd255, 8'd255};
repeat (2) @(posedge clk);
if (out !== {9'd270, 9'd510})
$display("result == ", 9'd270, ", ", 9'd510, " expected but ", out[17:9], ", ", out[8:0]);
repeat (5) @(posedge clk);
$finish(2);
end
endmodule
| 6.562762 |
module tb_adder_tree_var ();
localparam NUM = 18;
localparam LEN = 16;
localparam LEVEL = 5;
localparam LEN_LAST = LEN + LEVEL;
reg clk;
reg signed [LEN-1:0] in_inner[NUM-1:0];
reg [NUM*LEN-1:0] in;
wire [LEN_LAST-1:0] sum;
adder_tree_var_bit #(
.NUM(NUM),
.LEN(LEN)
) dut (
.clk(clk),
.in (in),
.sum(sum)
);
integer i;
initial begin
clk = 0;
in = 0;
for (i = 0; i < NUM; i = i + 1) begin
in_inner[i] = 1;
end
for (i = 0; i < NUM; i = i + 1) begin
in = {in, in_inner[i]};
end
end
always #5 clk = ~clk;
endmodule
| 6.562762 |
module TB_addressGen;
/// when enabled, will generate address values from 0 to 1023, essentially a counter
/// then will raise done to high
reg clk, rst, gen_en, sobel_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen UUT (
clk,
rst,
gen_en,
sobel_en,
addr,
done
);
initial begin
rst = 1'b1;
#300;
rst = 1'b0;
gen_en = 1'b1;
#2000;
#50000;
#1000;
#50000;
#50000; // gets to 10000_00000
#50000; // 1111110111
#2000;
gen_en = 1'b0;
sobel_en = 1'b1;
#2000;
$stop;
end
always begin
if (rst == 1'b1) begin
clk = 1'b0;
#1;
end else begin
#100;
clk = ~clk;
end
end
endmodule
| 6.65016 |
module tb_address_generator ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator.vcd");
$dumpvars(0, tb_address_generator);
// #100000;
// $finish;
end
parameter RAND_BUSY = 1;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
always @(posedge clk) cke <= RAND_BUSY ? {$random()} : 1'b1;
parameter ADDR_WIDTH = 32;
parameter SIZE_WIDTH = 32;
parameter LEN_WIDTH = 4;
parameter SIZE_OFFSET = 1'b0;
parameter LEN_OFFSET = 1'b1;
parameter S_REGS = 1'b1;
reg [ADDR_WIDTH-1:0] s_addr;
reg [SIZE_WIDTH-1:0] s_size;
reg [ LEN_WIDTH-1:0] s_max_len;
reg s_valid;
wire s_ready;
wire [ADDR_WIDTH-1:0] m_addr;
wire [ LEN_WIDTH-1:0] m_len;
wire m_last;
wire m_valid;
reg m_ready;
jelly_address_generator #(
.ADDR_WIDTH (ADDR_WIDTH),
.SIZE_WIDTH (SIZE_WIDTH),
.LEN_WIDTH (LEN_WIDTH),
.SIZE_OFFSET(SIZE_OFFSET),
.LEN_OFFSET (LEN_OFFSET),
.S_REGS (S_REGS)
) i_address_generator (
.reset(reset),
.clk (clk),
.cke (cke),
.s_addr (s_addr),
.s_size (s_size),
.s_max_len(s_max_len),
.s_valid (s_valid),
.s_ready (s_ready),
.m_addr (m_addr),
.m_len (m_len),
.m_last (m_last),
.m_valid(m_valid),
.m_ready(m_ready)
);
localparam TEST_NUM = 257;
integer i = 0;
integer exp_i = 0;
integer count_s_size = 0;
integer count_m_size = 0;
integer count_m_exp = 0;
reg err = 0;
always @(posedge clk) begin
if (reset) begin
i = 0;
s_valid <= 0;
m_ready <= 0;
end else if (cke) begin
if (s_ready) begin
s_valid <= 1'b0;
i = i + s_valid;
if (i < TEST_NUM) begin
s_addr <= i * 256;
s_size <= i + 1 - SIZE_OFFSET;
s_max_len <= i;
s_valid <= RAND_BUSY ? {$random()} : 1'b1;
end
end
m_ready <= RAND_BUSY ? {$random()} : 1'b1;
if (s_valid && s_ready) begin
count_s_size <= count_s_size + s_size + SIZE_OFFSET;
end
if (m_valid && m_ready) begin
count_m_size <= count_m_size + m_len + LEN_OFFSET;
if (m_last) begin
exp_i <= exp_i + 1;
count_m_exp <= count_m_exp + (exp_i + 1);
if ((count_m_size + m_len + LEN_OFFSET) != (count_m_exp + (exp_i + 1))) begin
err <= 1;
$display("error");
end
end
end
end
end
initial begin
#1000;
while (i < TEST_NUM) begin
#1000;
end
#(RATE * 2000);
if (count_m_size != count_s_size) begin
$display("error");
end else begin
$display("OK");
end
$finish();
end
endmodule
| 8.348644 |
module tb_address_generator_range ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator_range.vcd");
$dumpvars(0, tb_address_generator_range);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
parameter SIZE_WIDTH = 8;
parameter LEN_WIDTH = 4;
parameter SIZE_OFFSET = 1'b0;
parameter LEN_OFFSET = 1'b1;
parameter S_REGS = 1'b1;
parameter INIT_ADDR = 0;
wire [SIZE_WIDTH-1:0] param_size = 33;
reg [ LEN_WIDTH-1:0] s_len;
reg s_valid;
wire s_ready;
wire [SIZE_WIDTH-1:0] m_addr;
wire [ LEN_WIDTH-1:0] m_len;
wire m_valid;
reg m_ready;
jelly_address_generator_range #(
.SIZE_WIDTH (SIZE_WIDTH),
.LEN_WIDTH (LEN_WIDTH),
.SIZE_OFFSET(SIZE_OFFSET),
.LEN_OFFSET (LEN_OFFSET),
.S_REGS (S_REGS),
.INIT_ADDR (INIT_ADDR)
) i_address_generator_range (
.reset(reset),
.clk (clk),
.cke (cke),
.param_size(param_size),
.s_len (s_len),
.s_valid(s_valid),
.s_ready(s_ready),
.m_addr (m_addr),
.m_len (m_len),
.m_valid(m_valid),
.m_ready(m_ready)
);
integer i = 0;
integer count_s_size = 0;
integer count_m_size = 0;
wire [SIZE_WIDTH-1:0] exp_addr = count_m_size % (param_size + SIZE_OFFSET);
reg err = 0;
always @(posedge clk) begin
if (reset) begin
s_valid <= 0;
m_ready <= 0;
end else if (cke) begin
i = i + 1;
if (i < 1000) begin
s_len <= {$random()};
s_valid <= {$random()};
m_ready <= {$random()};
end else begin
s_valid <= 1'b0;
m_ready <= 1'b1;
end
if (s_valid && s_ready) begin
count_s_size = count_s_size + s_len + LEN_OFFSET;
end
err = 0;
if (m_valid && m_ready) begin
count_m_size = count_m_size + m_len + LEN_OFFSET;
if ( m_addr != exp_addr || {1'b0, m_addr} + m_len + LEN_OFFSET > {1'b0, param_size} + SIZE_OFFSET ) begin
$display("error");
err = 1;
end
end
if (i > 2000) begin
$finish();
end
end
end
endmodule
| 8.348644 |
module tb_address_generator_step ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator_step.vcd");
$dumpvars(0, tb_address_generator_step);
#10000;
$finish;
end
parameter RAND_BUSY = 0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg cke = 1'b1;
always @(posedge clk) cke <= RAND_BUSY ? {$random()} : 1'b1;
parameter ADDR_WIDTH = 32;
parameter STEP_WIDTH = 32;
parameter LEN_WIDTH = 32;
parameter USER_WIDTH = 0;
parameter LEN_OFFSET = 1'b1;
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
reg [ADDR_WIDTH-1:0] s_addr = 32'h0001000;
reg [STEP_WIDTH-1:0] s_step = 32'h0000100;
reg [ LEN_WIDTH-1:0] s_len = 3;
reg [ USER_BITS-1:0] s_user = 0;
reg s_valid = 1;
wire s_ready;
wire [ADDR_WIDTH-1:0] m_addr;
wire m_first;
wire m_last;
wire [ USER_BITS-1:0] m_user;
wire m_valid;
reg m_ready = 1;
jelly_address_generator_step #(
.ADDR_WIDTH(ADDR_WIDTH),
.STEP_WIDTH(STEP_WIDTH),
.LEN_WIDTH (LEN_WIDTH),
.USER_WIDTH(USER_WIDTH),
.LEN_OFFSET(LEN_OFFSET)
) i_address_generator_step (
.reset(reset),
.clk (clk),
.cke (cke),
.s_addr (s_addr),
.s_step (s_step),
.s_len (s_len),
.s_user (s_user),
.s_valid(s_valid),
.s_ready(s_ready),
.m_addr (m_addr),
.m_first(m_first),
.m_last (m_last),
.m_user (m_user),
.m_valid(m_valid),
.m_ready(m_ready)
);
endmodule
| 8.348644 |
module tb_addSub_4bit ();
wire [3:0] sum;
wire cout;
reg [3:0] a, b;
reg cin;
reg sel;
addSub_4bit addsub (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin),
.sel(sel)
);
initial begin
$dumpfile("tb_addSub_4bit.vcd");
$dumpvars;
end
initial begin
a = 4'b0101;
b = 4'b1000;
cin = 0;
sel = 0;
#5 a = 4'b0101;
b = 4'b1000;
cin = 0;
sel = 1;
#5 a = 4'b0101;
b = 4'b1000;
cin = 1;
sel = 0;
#5 a = 4'b0101;
b = 4'b1000;
cin = 1;
sel = 1;
#5 a = 4'b1101;
b = 4'b1001;
cin = 0;
sel = 0;
#5 a = 4'b1101;
b = 4'b1001;
cin = 0;
sel = 1;
#5 a = 4'b1101;
b = 4'b1001;
cin = 1;
sel = 0;
#5 a = 4'b1101;
b = 4'b1001;
cin = 1;
sel = 1;
end
endmodule
| 7.67804 |
module tb_add_sub ();
reg [3:0] A, B; // Declaration of two four-bit inputs
reg sel; // and the one-bit input carry
wire [3:0] s; // Declaration of the five-bit outputs
wire v; // internal carry wires
add_sub DUT (
V,
s,
cout,
sel,
A,
B
);
initial begin
#10 A = 4'b0000;
B = 4'b0001;
sel = 1'b0;
#10 A = 4'b0001;
B = 4'b0001;
sel = 1'b0;
#10 A = 4'b0010;
B = 4'b0001;
sel = 1'b1;
#10 A = 4'b0100;
B = 4'b0001;
sel = 1'b1;
#10 A = 4'b0010;
B = 4'b0001;
sel = 1'b0;
#10 A = 4'b0100;
B = 4'b0001;
sel = 1'b0;
#10 A = 4'b0111;
B = 4'b0111;
sel = 1'b0; //overflow case
end
endmodule
| 6.721562 |
module Tb_Administrador_de_Salidas ();
reg [2:0] RY;
reg [7:0] RX;
reg [2:0] Num;
reg [1:0] Sel_Salidas;
wire [7:0] o_Dataout;
wire [7:0] o_Addressdata;
wire ReadWrite;
Administrador_de_salidas uut (
.RY(RY),
.RX(RX),
.Num(Num),
.Sel_Salidas(Sel_Salidas),
.o_Dataout(o_Dataout),
.o_Addressdata(o_Addressdata),
.ReadWrite(ReadWrite)
);
initial begin
RY = 0; // Inicializacin de las entradas
RX = 0;
Num = 0;
Sel_Salidas = 0;
#2 RY = 4'd4; //Se asigna valor a las entradas
RX = 4'd5;
Num = 4'd6;
#2 Sel_Salidas = 0; // Se actualiza el selector cada 2 tiempos
#2 Sel_Salidas = 1;
#2 Sel_Salidas = 2;
#2 Sel_Salidas = 3;
#2 Sel_Salidas = 0;
#2 Sel_Salidas = 1;
#2 Sel_Salidas = 2;
#2 Sel_Salidas = 3;
#2 Sel_Salidas = 0;
#2 Sel_Salidas = 1;
#2 Sel_Salidas = 2;
#2 Sel_Salidas = 3;
end
endmodule
| 7.372853 |
module tb_adr #(
parameter ADR_WIDTH = 5
) ();
reg clk;
reg rst;
reg [ADR_WIDTH-1:0] adr_i;
reg [`CTR_MARMUX_WIDTH-1:0] ctr_marmux_i;
reg ctr_mar_reg_en_i;
reg ctr_pc_reg_en_i;
wire [ADR_WIDTH-1:0] adr_o;
integer j;
adr #(
.ADR_WIDTH(ADR_WIDTH)
) i_adr (
.clk_i(clk),
.rst_i(rst),
.adr_i(adr_i),
.ctr_marmux_i(ctr_marmux_i),
.ctr_mar_reg_en_i(ctr_mar_reg_en_i),
.ctr_pc_reg_en_i(ctr_pc_reg_en_i),
.adr_o(adr_o)
);
initial begin
$dumpfile("tb_adr.vcd");
// $dumpvars(level, list_of_variables_or_modules)
// level = 1 -> only variables in list_of_variables_or_modules
$dumpvars(0, tb_adr);
//$readmemb("tb/egse.stim", stim);
//$monitor("%b%b LED:%b RS232TX:%b", clk, rst_n, led, rs232_tx);
/* Reset circuit */
clk = 0;
rst = 1;
ctr_marmux_i = `MAR_OP_ARG;
ctr_mar_reg_en_i = 1'b0;
ctr_pc_reg_en_i = 1'b0;
adr_i = 0;
#10 rst = 0;
/* Initialize MAR from adr_i */
ctr_marmux_i = `MAR_OP_ARG;
ctr_mar_reg_en_i = 1'b1;
ctr_pc_reg_en_i = 1'b0;
for (j = 0; j < 2 ** ADR_WIDTH; j = j + 1) begin
adr_i = j;
@(posedge clk);
#1
if (adr_o != adr_i) begin
$display("MAR_OP_ARG fail: j=%d", j);
end
end
/* Protect MAR state */
ctr_marmux_i = `MAR_OP_ARG;
ctr_mar_reg_en_i = 1'b1;
ctr_pc_reg_en_i = 1'b0;
adr_i = 26;
@(posedge clk);
#1;
ctr_mar_reg_en_i = 1'b0;
for (j = 0; j < 2 ** ADR_WIDTH; j = j + 1) begin
adr_i = j;
@(posedge clk);
#1
if (adr_o != 26) begin
$display("Protect MAR state fail: j=%d", j);
end
end
/* Initialize MAR from PC */
/* Let adr_i count up as well and assert difference */
ctr_marmux_i = `MAR_OP_ARG;
ctr_mar_reg_en_i = 1'b1;
ctr_pc_reg_en_i = 1'b1;
adr_i = 0;
@(posedge clk); /* 0 to MAR */
@(posedge clk); /* 1 to PC */
ctr_marmux_i = `MAR_OP_PC;
ctr_mar_reg_en_i = 1'b1;
ctr_pc_reg_en_i = 1'b1;
@(posedge clk);
@(posedge clk);
for (j = 0; j < 2 ** ADR_WIDTH; j = j + 1) begin
adr_i = j;
@(posedge clk);
@(posedge clk);
if (adr_o == adr_i) begin
$display("MAR_OP_PC fail: j=%d", j);
end
end
$finish;
end
always #1 clk = !clk;
endmodule
| 6.636031 |
module: adt_term
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_adt_term;
// Inputs
reg clk;
reg reset_n;
reg rx;
reg tx_frame_start;
reg [7:0] data_ram;
reg [15:0] addr_ram;
reg wr_ram;
// Outputs
wire tx;
wire tx_busy;
wire rx_frame_done;
wire [199:0] rx_frame;
wire comNoResponse;
wire check_sum_error;
// Instantiate the Unit Under Test (UUT)
adt_term uut (
.clk(clk),
.reset_n(reset_n),
.rx(rx),
.tx_frame_start(tx_frame_start),
.data_ram(data_ram),
.addr_ram(addr_ram),
.wr_ram(wr_ram),
.tx(tx),
.tx_busy(tx_busy),
.rx_frame_done(rx_frame_done),
.rx_frame(rx_frame),
.comNoResponse(comNoResponse),
.check_sum_error(check_sum_error)
);
reg wr_ram_r;
initial begin
// Initialize Inputs
clk = 0;
reset_n = 0;
rx = 0;
tx_frame_start = 0;
data_ram = 0;
addr_ram = 0;
wr_ram_r = 0;
// Wait 100 ns for global reset to finish
#20
reset_n = 1;
#40
reset_n = 0;
#20
reset_n = 1;
#90
wr_ram_r = 1;
// Add stimulus here
end
//reg clk_25M = 0;
always #10 clk = ~clk;
//always #20 clk_25M = ~clk_25M;
reg[3:0] clkCnt;
wire clk_25M;
always @ (posedge clk or negedge reset_n)
if(!reset_n)
clkCnt <= 0;
else
clkCnt <= clkCnt + 1'b1;
assign clk_25M = clkCnt[1];//clk_12P5M
always @ (posedge clk)
if(addr_ram == 99)
wr_ram_r <= 0;
else if(addr_ram == 100)
tx_frame_start <= 1'b1;
else
tx_frame_start <= 1'b0;
always @ (posedge clk_25M)
wr_ram <= wr_ram_r;
always @ (posedge clk_25M)
if(wr_ram)
addr_ram <= addr_ram + 1'b1;
else
addr_ram <= 0;
always @ (posedge clk or negedge reset_n)
case(addr_ram)
0: data_ram <= 8'h11;
1: data_ram <= 8'h22;
2: data_ram <= 8'h33;
3: data_ram <= 8'h44;
4: data_ram <= 8'h55;
5: data_ram <= 8'h66;
6: data_ram <= 8'h77;
7: data_ram <= 8'h88;
8: data_ram <= 8'h99;
9: data_ram <= 8'hAA;
10,11,12,13,14,15,16,17,18,19,20,
21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,
41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56:
data_ram <= 8'h55;
57: data_ram <= 8'h57;
58: data_ram <= 8'h58;
59: data_ram <= 8'h59;
60: data_ram <= 8'h60;
61: data_ram <= 8'h61;
62: data_ram <= 8'h62;
63: data_ram <= 8'h63;
64: data_ram <= 8'h64;
65: data_ram <= 8'h65;
66: data_ram <= 8'h66;
67,68,69,70,71,72,73,74,75,76,77,78,79,
80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96:
data_ram <= 8'h55;
97: data_ram <= 8'h97;
98: data_ram <= 8'h98;
99: data_ram <= 8'h99;
default:data_ram <= 0;
endcase;
endmodule
| 6.723427 |
module: canny_advanced
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_advanced;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
canny_advanced canny (
.clk(clk),
.reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
#10;
reset = 0;
// Wait 100 ns for global reset to finish
#10;
reset = 1;
forever
begin
#1;
clk = ~clk;
end
// Add stimulus here
end
endmodule
| 7.656574 |
module tb_adv_fsm;
reg clk, reset, x;
wire z;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
adv_fsm UUT (
.clk(clk),
.reset(reset),
.x(x),
.z(z)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
x = 0;
#period;
// goes to state IDLE
if (z !== 0) begin
$display("test 1 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
// start fsm
reset = 0;
x = 0;
#period;
// stays in state IDLE
if (z !== 0) begin
$display("test 2 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
// start pattern
x = 1;
#period;
// goes to S1
if (z !== 0) begin
$display("test 3 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
x = 0;
#period;
// goes to S2
if (z !== 0) begin
$display("test 4 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
x = 1;
#period;
// goes to S3
if (z !== 1) begin
$display("test 5 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
#period;
// goes to S1
if (z !== 0) begin
$display("test 6 failed");
$finish;
end else $display("x=%b, z=%b", x, z);
$display("all tests passed");
$finish;
end
endmodule
| 7.116394 |
module tb_adv_shifter;
reg clk, load, ena;
reg [ 1:0] amount;
reg [63:0] data;
wire [63:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
advshift UUT (
.clk(clk),
.load(load),
.amount(amount),
.data(data),
.ena(ena),
.q(q)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
// load data (load not enabled, should not load)
data = 64'hffff_ffff_ffff_ffff;
load = 0;
amount = 0;
ena = 0;
#period;
if (q === 64'hffff_ffff_ffff_ffff) begin
$display("test 1 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// enable load
load = 1;
amount = 0;
ena = 0;
#period;
if (q !== 64'hffff_ffff_ffff_ffff) begin
$display("test 2 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// chead load override
load = 1;
amount = 2;
ena = 0;
#period;
if (q !== 64'hffff_ffff_ffff_ffff) begin
$display("test 3 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// amount = 0 but not enabled (checking enable functionality)
load = 0;
amount = 0;
ena = 0;
#period;
if (q === 64'hffff_ffff_ffff_fffe) begin
$display("test 4 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// enable, amount=0
load = 0;
amount = 0;
ena = 1;
#period;
if (q !== 64'hffff_ffff_ffff_fffe) begin
$display("test 5 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// enable, amount=1
load = 0;
amount = 1;
ena = 1;
#period;
if (q !== 64'hffff_ffff_ffff_fe00) begin
$display("test 6 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// enable, amount=2
load = 0;
amount = 2;
ena = 1;
#period;
if (q !== 64'h7fff_ffff_ffff_ff00) begin
$display("test 7 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
// enable, amount=3
load = 0;
amount = 3;
ena = 1;
#period;
if (q !== 64'h007f_ffff_ffff_ffff) begin
$display("test 8 failed");
$finish;
end else $display("load =%b, amount = %b, ena=%b, q=%b", load, amount, ena, q);
$display("all tests passed");
$finish;
end
endmodule
| 7.101369 |
module tb_aes_control_unit ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
reg clk; // Clock
reg rst_n; // Asynchronous reset active low
reg i_en;
reg i_flag;
/**********************************************************************
* output as wires
**********************************************************************/
wire o_busy;
wire o_dp_en;
wire o_ready;
wire o_valid;
/**********************************************************************
* DUT
**********************************************************************/
aes_control_unit DUT (
.clk (clk), // Clock
.rst_n (rst_n), // Asynchronous reset active low
.i_en (i_en),
.i_flag (i_flag),
.o_busy (o_busy),
.o_dp_en(o_dp_en),
.o_ready(o_ready),
.o_valid(o_valid)
);
/**********************************************************************
* Define Clock Cycles
**********************************************************************/
localparam CLK_PRD = 10;
initial clk = 'b1;
always #((CLK_PRD) / 2) clk = !clk;
task reset_cu();
begin
rst_n = 1'b0;
repeat (5) begin
@(posedge clk) rst_n = 1'b0;
end
rst_n = 1'b1;
end
endtask
task run_cu_test();
begin
rst_n = 'b1;
i_flag = 'b0;
i_en = 'b1;
@(posedge clk) i_en = 'b1;
repeat (10) begin
@(posedge clk) i_flag = 'b0;
end
i_flag = 'b1;
end
endtask
/**********************************************************************
* Stimulus here
**********************************************************************/
initial begin
reset_cu();
run_cu_test();
end
endmodule
| 6.854026 |
module tb_aes_core_top ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
localparam RND_SIZE = 128;
localparam WRD_SIZE = 32;
localparam NUM_BLK = 4;
localparam MAX_CNT = 12;
localparam CNT_SIZE = 4;
localparam NUM_RND = 10;
/**********************************************************************
* Inputs as registers
**********************************************************************/
reg clk; // Clock
reg rst_n; // Asynchronous reset active low
reg i_en;
reg [RND_SIZE-1:0] i_msg;
reg [RND_SIZE-1:0] i_key;
/**********************************************************************
* output as wires
**********************************************************************/
wire o_valid;
wire [RND_SIZE-1:0] o_cypher;
wire o_ready;
wire busy;
/**********************************************************************
* DUT instantiation
**********************************************************************/
aes_core_top #(
.RND_SIZE(RND_SIZE),
.WRD_SIZE(WRD_SIZE),
.NUM_BLK (NUM_BLK),
.MAX_CNT (MAX_CNT),
.CNT_SIZE(CNT_SIZE),
.NUM_RND (NUM_RND)
) DUT (
.clk (clk), // Clock
.rst_n (rst_n), // Asynchronous reset active low
.i_en (i_en),
.i_msg (i_msg),
.i_key (i_key),
.o_valid (o_valid),
.o_cypher(o_cypher),
.o_ready (o_ready),
.busy (busy)
);
/**********************************************************************
* Define Clock Cycles
**********************************************************************/
localparam CLK_PRD = 10;
initial clk = 'b1;
always #((CLK_PRD) / 2) clk = !clk;
task reset_aes();
begin
i_en = 'b0;
i_msg = 'h0;
i_key = 'h0;
rst_n = 1'b0;
repeat (5) begin
@(posedge clk) rst_n = 1'b0;
end
rst_n = 1'b1;
end
endtask
task run_aes_test();
begin
i_en = 'b1;
i_msg = 'h3243f6a8885a308d313198a2e0370734;
i_key = 'h2b7e151628aed2a6abf7158809cf4f3c;
end
endtask
/**********************************************************************
* Stimulus here
**********************************************************************/
initial begin
reset_aes();
run_aes_test();
end
endmodule
| 7.132956 |
module tb_aes_data_path ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
localparam RND_SIZE = 128;
localparam WRD_SIZE = 32;
localparam NUM_BLK = 4;
localparam MAX_CNT = 11;
localparam CNT_SIZE = 4;
localparam NUM_RND = 10;
/**********************************************************************
* Inputs as registers
**********************************************************************/
reg clk;
reg rst_n;
reg i_dp_en;
reg [RND_SIZE-1:0] i_rnd_text;
reg [RND_SIZE-1:0] i_rnd_key;
/**********************************************************************
* output as wires
**********************************************************************/
wire [RND_SIZE-1:0] o_cypher_text;
wire o_flag;
/**********************************************************************
* DUT instantiation
**********************************************************************/
aes_data_path #(
.RND_SIZE(RND_SIZE),
.WRD_SIZE(WRD_SIZE),
.NUM_BLK (NUM_BLK),
.MAX_CNT (MAX_CNT),
.CNT_SIZE(CNT_SIZE),
.NUM_RND (NUM_RND)
) DUT (
// inputs
.clk (clk),
.rst_n (rst_n),
.i_dp_en (i_dp_en),
.i_rnd_text (i_rnd_text),
.i_rnd_key (i_rnd_key),
// outputs
.o_cypher_text(o_cypher_text),
.o_flag (o_flag)
);
/**********************************************************************
* Define Clock Cycles
**********************************************************************/
localparam CLK_PRD = 10;
initial clk = 'b1;
always #((CLK_PRD) / 2) clk = !clk;
task reset_dp();
begin
i_rnd_text = 'h0;
i_rnd_key = 'h0;
i_dp_en = 'b0;
rst_n =1'b0;
repeat (5) begin
@(posedge clk) rst_n = 1'b0;
end
rst_n = 1'b1;
end
endtask
task run_dp_test();
begin
i_dp_en <= 'b1;
i_rnd_text <= 'h3243f6a8885a308d313198a2e0370734;
i_rnd_key <= 'h2b7e151628aed2a6abf7158809cf4f3c;
end
endtask
/**********************************************************************
* Stimulus here
**********************************************************************/
initial begin
reset_dp();
@(posedge clk);
run_dp_test();
end
endmodule
| 6.814903 |
module tb_aes_cipher ();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg tb_clk; //tb时钟信号
reg tb_reset; //tb重置信号
reg tb_init;
wire [127:0] tb_key; //对应轮数的密钥
reg [127:0] tb_plaintext;
wire [127:0] tb_ciphertext;
wire [ 31:0] tb_sboxw; //对应位置的S-Box
wire [ 31:0] tb_new_sboxw;
wire tb_ready; //就绪标志位
reg [127:0] key;
assign tb_key = key;
aes_inv_sbox sbox (
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw)
);
aes_encipher dut (
.clk(tb_clk),
.reset(tb_reset),
.init(tb_init),
.key(tb_key),
.plaintext(tb_plaintext),
.ciphertext(tb_ciphertext),
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw),
.ready(tb_ready)
);
always begin
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end
task reset_dut;
begin
$display("Start reset.");
tb_reset = 0;
#(2 * CLK_PERIOD);
tb_reset = 1;
$display("Reset done.");
end
endtask
task init;
begin
tb_clk = 0;
tb_reset = 1;
tb_plaintext = {4{32'h00_00_00_00}};
end
endtask
task wait_ready;
begin
//没准备好就再等待两个时钟周期
while (!tb_ready) begin
#(CLK_PERIOD);
end
end
endtask
task test_ecb_enc(input [127:0] block, input [127:0] expected);
begin
tb_plaintext = block;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
#(2 * CLK_PERIOD);
wait_ready();
$display("Expected: 0x%032x", expected);
$display("Got: 0x%032x", tb_ciphertext);
end
endtask
initial begin : test
reg [127:0] plaintext;
reg [127:0] expected;
key = 128'h000102030405060708090a0b0c0d0e0f;
plaintext = 128'h00112233445566778899aabbccddeeff;
expected = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
init();
reset_dut();
test_ecb_enc(expected, plaintext);
$finish;
end
endmodule
| 7.638538 |
module tb_aes_cipher ();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg tb_clk; //tb时钟信号
reg tb_reset; //tb重置信号
reg tb_init;
wire [127:0] tb_key; //对应轮数的密钥
reg [127:0] tb_plaintext;
wire [127:0] tb_ciphertext;
wire [ 31:0] tb_sboxw; //对应位置的S-Box
wire [ 31:0] tb_new_sboxw;
wire tb_ready; //就绪标志位
reg [127:0] key;
assign tb_key = key;
aes_sbox sbox (
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw)
);
aes_encipher dut (
.clk(tb_clk),
.reset(tb_reset),
.init(tb_init),
.key(tb_key),
.plaintext(tb_plaintext),
.ciphertext(tb_ciphertext),
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw),
.ready(tb_ready)
);
always begin
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end
task reset_dut;
begin
$display("Start reset.");
tb_reset = 0;
#(2 * CLK_PERIOD);
tb_reset = 1;
$display("Reset done.");
end
endtask
task init;
begin
tb_clk = 0;
tb_reset = 1;
tb_plaintext = {4{32'h00_00_00_00}};
end
endtask
task wait_ready;
begin
//没准备好就再等待两个时钟周期
while (!tb_ready) begin
#(CLK_PERIOD);
end
end
endtask
task test_ecb_enc(input [127:0] block, input [127:0] expected);
begin
tb_plaintext = block;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
#(2 * CLK_PERIOD);
wait_ready();
$display("Expected: 0x%032x", expected);
$display("Got: 0x%032x", tb_ciphertext);
end
endtask
initial begin : test
reg [127:0] plaintext;
reg [127:0] expected;
key = 128'h000102030405060708090a0b0c0d0e0f;
plaintext = 128'h00112233445566778899aabbccddeeff;
expected = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
init();
reset_dut();
test_ecb_enc(plaintext, expected);
$finish;
end
endmodule
| 7.638538 |
module tb_aes_round ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
parameter RND_SIZE = 128;
parameter WRD_SIZE = 32;
parameter CNT_SIZE = 4;
parameter NUM_BLK = 4;
/**********************************************************************
* Inputs as registers
**********************************************************************/
reg clk;
reg rst_n;
reg [RND_SIZE-1:0] i_rnd_text;
reg [RND_SIZE-1:0] i_rnd_key;
reg [CNT_SIZE-1:0] i_rnd_cnt;
reg i_rnd_en;
/**********************************************************************
* output as wires
**********************************************************************/
wire [RND_SIZE-1:0] o_rnd_cypher;
/**********************************************************************
* DUT instantiation
**********************************************************************/
aes_round #(
.RND_SIZE(RND_SIZE),
.WRD_SIZE(WRD_SIZE),
.CNT_SIZE(CNT_SIZE),
.NUM_BLK (NUM_BLK)
) DUT (
// inputs
.clk (clk),
.rst_n (rst_n),
.i_rnd_en (i_rnd_en),
.i_rnd_text (i_rnd_text),
.i_rnd_key (i_rnd_key),
.i_rnd_cnt (i_rnd_cnt),
// outputs
.o_rnd_cypher(o_rnd_cypher)
);
/**********************************************************************
* Define Clock Cycles
**********************************************************************/
localparam CLK_PRD = 10;
initial clk = 'b1;
always #((CLK_PRD) / 2) clk = !clk;
task reset_round();
begin
i_rnd_text = 'h0; //TODO:
i_rnd_key = 'h0; //TODO:
i_rnd_cnt = 'h0; //TODO:
i_rnd_en = 'b0;
rst_n = 1'b0;
repeat (5) begin
@(posedge clk) rst_n = 1'b0;
end
rst_n = 1'b1;
end
endtask
integer i = 0;
task run_round_test();
begin
for (i = 0; i < 2; i = i + 1) begin
@(posedge clk) i_rnd_en = 'b1;
i_rnd_cnt = i;
i_rnd_text = (i_rnd_cnt=='h0)?'h3243f6a8885a308d313198a2e0370734:'h193de3bea0f4e22b9ac68d2ae9f84808;
i_rnd_key = (i_rnd_cnt=='h0)?'h2b7e151628aed2a6abf7158809cf4f3c:'ha0fafe1788542cb123a339392a6c7605;
end
end
endtask
/**********************************************************************
* Stimulus here
**********************************************************************/
initial begin
reset_round();
run_round_test();
end
endmodule
| 6.85432 |
module AESL_automem_RoundKey (
Q,
CPU_RESETN,
E,
D,
CLK100M_IBUF_BUFG
);
output [7:0] Q;
input CPU_RESETN;
input [0:0] E;
input [7:0] D;
input CLK100M_IBUF_BUFG;
wire CLK100M_IBUF_BUFG;
wire CPU_RESETN;
wire [7:0] D;
wire [0:0] E;
wire [7:0] Q;
FDRE #(
.INIT(1'b0)
) \dout0_reg[0] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[0]),
.Q (Q[0]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[1] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[1]),
.Q (Q[1]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[2] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[2]),
.Q (Q[2]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[3] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[3]),
.Q (Q[3]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[4] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[4]),
.Q (Q[4]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[5] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[5]),
.Q (Q[5]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[6] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[6]),
.Q (Q[6]),
.R (CPU_RESETN)
);
FDRE #(
.INIT(1'b0)
) \dout0_reg[7] (
.C (CLK100M_IBUF_BUFG),
.CE(E),
.D (D[7]),
.Q (Q[7]),
.R (CPU_RESETN)
);
endmodule
| 6.546446 |
module tb_aes_wrapper ();
reg clk, rst;
wire bitti;
aes_wrapper aw (
clk,
rst,
bitti
);
always begin
clk = ~clk;
#5;
end
initial begin
clk = 0;
rst = 1;
#100;
rst = 0;
end
endmodule
| 6.552137 |
module tb_ahb2apb ();
parameter AHB_DATA_WIDTH = 32;
parameter AHB_ADDR_WIDTH = 32;
parameter APB_DATA_WIDTH = 32;
parameter APB_ADDR_WIDTH = 32;
reg ahb_hclk;
reg ahb_hrstn;
reg ahb_hsel;
reg [ 1:0] ahb_htrans;
reg [AHB_ADDR_WIDTH-1:0] ahb_haddr;
reg [AHB_DATA_WIDTH-1:0] ahb_hdata;
reg ahb_hwrite;
wire ahb_hready;
wire [AHB_DATA_WIDTH-1:0] ahb_rdata;
reg apb_pclk;
reg apb_prstn;
wire apb_psel;
wire apb_pwrite;
wire apb_penable;
wire [APB_ADDR_WIDTH-1:0] apb_paddr;
wire [APB_DATA_WIDTH-1:0] apb_wdata;
reg apb_pready;
reg [APB_DATA_WIDTH-1:0] apb_prdata;
ahb2apb u_ahb2apb0 (
.ahb_hclk (ahb_hclk ),
.ahb_hrstn (ahb_hrstn ),
.ahb_hsel (ahb_hsel ),
.ahb_htrans (ahb_htrans ),
.ahb_haddr (ahb_haddr ),
.ahb_hdata (ahb_hdata ),
.ahb_hwrite (ahb_hwrite ),
.ahb_hready (ahb_hready ),
.ahb_rdata (ahb_rdata ),
.apb_pclk (apb_pclk ),
.apb_prstn (apb_prstn ),
.apb_psel (apb_psel ),
.apb_pwrite (apb_pwrite ),
.apb_penable(apb_penable),
.apb_paddr (apb_paddr ),
.apb_wdata (apb_wdata ),
.apb_pready (apb_pready ),
.apb_prdata (apb_prdata )
);
initial begin
ahb_hclk = 0;
ahb_hrstn = 0;
apb_pclk = 0;
apb_prstn = 0;
#50 ahb_hrstn = 1;
apb_prstn = 1;
end
initial begin
ahb_hsel = 0;
ahb_htrans = 0;
ahb_haddr = 0;
ahb_hwdata = 0;
ahb_hwrite = 0;
apb_pready = 0;
apb_prdata = 0;
end
always #5 ahb_hclk = ~ahb_hclk;
always #10 apb_pclk = ~apb_pclk;
initial begin
#100 send_write;
repeat (200) @(posedge ahb_hclk);
send_read;
repeat (200) @(posedge ahb_hclk);
$finish;
end
task send_write;
begin
fork
begin
@(posedge ahb_hclk) begin
ahb_hsel <= 1'b1;
ahb_hwrite <= 1'b1;
ahb_htrans <= 2'b10;
ahb_haddr <= 32'd100;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_htrans <= 2'b11;
ahb_haddr <= 32'd104;
ahb_hwdata <= 32'h200;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_htrans <= 2'b11;
ahb_haddr <= 32'd108;
ahb_hwdata <= 32'h300;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_htrans <= 2'b11;
ahb_haddr <= 32'd112;
ahb_hwdata <= 32'h400;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_hsel <= 1'b1;
ahb_htrans <= 2'b00;
ahb_haddr <= 32'd100;
ahb_hwdata <= 32'h500;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_hwdata <= 32'h500;
end
end
begin
@(posedge apb_pclk) apb_pready <= 1'b1;
end
join
end
endtask
task send_read;
begin
fork
begin
@(posedge ahb_hclk) begin
ahb_hsel <= 1'b1;
ahb_hwrite <= 1'b0;
ahb_htrans <= 2'b10;
ahb_haddr <= 32'd100;
end
#1 wait (ahb_hready == 1'b1);
@(posedge ahb_hclk) begin
ahb_htrans <= 2'b00;
ahb_hsel <= 1'b0;
end
end
begin
@(posedge apb_pclk) begin
apb_pready <= 1'b1;
apb_prdata <= 32'd200;
end
end
join
end
endtask
endmodule
| 6.83351 |
module of Alarm clock
which is used to generate stimulus patterns for the DUT .
Date: 01/05/2018
Author: Maven Silicon
Email: online@maven-silicon.com
Version: 1.0
*********************************************************************************************/
module tb_alarm_clock();
reg clk,
reset,
fast_watch,
alarm_button,
time_button;
reg [3:0] key;
wire [7:0] display_ms_hr,
display_ms_min,
display_ls_hr,
display_ls_min;
wire sound_alarm;
parameter cycle = 2;
alarm_clock_top DUV(.clock(clk),
.reset(reset),
.fast_watch(fast_watch),
.alarm_button(alarm_button),
.time_button(time_button),
.key(key),
.alarm_sound(sound_alarm),
.ms_hour(display_ms_hr),
.ls_hour(display_ls_hr),
.ms_minute(display_ms_min),
.ls_minute(display_ls_min));
//Clock generation logic
initial
begin
clk = 1'b0;
forever
#(cycle/2) clk = ~clk;
end
//
//Stimulus logic
initial
begin
//Hard reset the design
reset = 1;
#10;
reset = 0;
//Set fastwatch to 1 to make counting faster
fast_watch = 1;
//Set key time to current time :11:23
key = 1;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 1;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 2;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 3;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
time_button = 1;
@(negedge clk);
time_button = 0;
//Set key time to alarm time :11:30
key = 1;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 1;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 3;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
key = 0;
repeat(3)
@(negedge clk);
key = 10;
@(negedge clk);
alarm_button = 1;
@(negedge clk);
alarm_button = 0;
#(7*256*2);//7 -> 7minutes ->7seconds->7 *256 clock cycles ->7*256*2(Time period of clock)
//Time out for Alarm clock
//key = 7;
repeat(4*2564) //Wait for minimum 10second pulses i.e (10*256) clock cycles
@(negedge clk);
$finish;
end
initial
$monitor($time,"\-ns\t MAVEN SILICON : \tDISPLAY_MS_HR =%H >>> DISPLAY_LS_HR =%H>>> DISPLAY_MS_MIN =%H>>> DISPLAY_LS_MIN=%H",display_ms_hr[3:0],display_ls_hr[3:0],display_ms_min[3:0],display_ls_min[3:0]);
endmodule
| 7.569403 |
module
//-------------------------------------------------------------------
module tb_alaw_coder();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; // 65 MHz
end
reg tb_rst = 1;
initial
begin
#15;
tb_rst = 0;
end
//-------------------------------------------------------------------
// DUT
//-------------------------------------------------------------------
localparam DUT_DATA_IN_W = 15;
localparam DUT_DATA_OUT_W = 8;
reg [DUT_DATA_IN_W-1:0] data_in = 0;
reg valid_in = 0;
wire [DUT_DATA_OUT_W-1:0] data_out;
wire valid_out;
alaw_coder
#(
.DATA_IN_W (DUT_DATA_IN_W), // Data input width
.DATA_OUT_W (DUT_DATA_OUT_W) // Data output width
) dut (
// System
.clk (tb_clk), // System clock
.rst (tb_rst), // System reset
// Input data
.data_in (data_in), // Data input
.valid_in (valid_in), // Data input is valid
// Output data
.data_out (data_out), // Data output
.valid_out (valid_out) // Output data is valid
);
//-------------------------------------------------------------------
// Testbench body
//------------------------------------------------------------------
localparam DATA_N = 16384;
integer err_cnt = 0;
// Test memory array
reg [DUT_DATA_IN_W-1:0] test_mem_in [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] test_mem_out [DATA_N-1:0];
reg [DUT_DATA_OUT_W-1:0] golden_mem_out [DATA_N-1:0];
initial
begin
$readmemh("../tb/tb_alaw_coder_in.mem", test_mem_in);
$readmemh("../tb/tb_alaw_coder_out.mem", golden_mem_out);
end
task send_data();
begin : task_send_data
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
@(posedge tb_clk);
#0;
data_in = test_mem_in[i];
valid_in = 1'b1;
@(posedge tb_clk);
#0;
valid_in = 1'b0;
@(posedge valid_out);
#0;
end
end
endtask
task result_read();
begin : task_result_read
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
@(posedge valid_out);
@(posedge tb_clk);
test_mem_out[i] = data_out;
end
end
endtask
task check();
begin : task_check
integer i;
for (i = 0; i < DATA_N; i = i + 1) begin
if (test_mem_out[i] != golden_mem_out[i]) begin
err_cnt = err_cnt + 1;
$display("Error! Addr=%d, expected 0x%04x, got 0x%04x!", i, golden_mem_out[i], test_mem_out[i]);
end
end
end
endtask
// Main test
initial begin : tb_main
wait(!tb_rst);
#20;
fork
send_data();
result_read();
join
check();
#1000;
if (err_cnt)
$error("Test failed with %d errors!", err_cnt);
else
$display("Test passed!");
#20;
`ifdef __ICARUS__
$finish;
`else
$stop;
`endif
end
`ifdef __ICARUS__
initial begin
$dumpfile("work.vcd");
$dumpvars(0, tb_alaw_coder);
end
`endif
endmodule
| 8.13663 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire tb_all_vs_enable;
wire [1:0] tb_all_vs_mode;
wire [3:0] tb_all_vs_D;
wire reset, clk;
wire [3:0] scb_Q;
wire scb_rco, scb_load;
/// A, B, C
wire [3:0] C_syn_Q;
wire C_syn_rco, C_syn_load;
///////////////////////////////////////////////////////////////////////////////////////////
//////////// Scoreboard
////////////
///////////////////////////////////////////////////////////////////////////////////////////
tb_scoreboard scoreboard_all_vs ( /*AUTOINST*/
// outputs
.scb_Q (scb_Q),
.scb_load (scb_load),
.scb_rco (scb_rco),
.clk (clk),
.reset (reset),
.tb_enable(tb_all_vs_enable),
.tb_mode (tb_all_vs_mode), // choose from 00, 01, 10, 11
.tb_D (tb_all_vs_D),
// inputs
.C_syn_rco (C_syn_rco),
.C_syn_load(C_syn_load),
.C_syn_Q (C_syn_Q)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// DUT A
////////////
// ///////////////////////////////////////////////////////////////////////////////////////////
//
// counterA_module DUT_A (/*AUTOINST*/
// // outputs
// .load (C_syn_load),
// .rco (C_syn_rco),
// .Q (C_syn_Q),
// //inputs
// .clk (clk),
// .reset (reset),
// .enable (tb_all_vs_enable),
// .mode (tb_all_vs_mode),
// .D (tb_all_vs_D)
// );
//
// ///////////////////////////////////////////////////////////////////////////////////////////
// //////////// DUT B
// ////////////
// ///////////////////////////////////////////////////////////////////////////////////////////
counterB_module DUT_B ( /*AUTOINST*/
// outputs
.load (C_syn_load),
.rco (C_syn_rco),
.Q (C_syn_Q),
//inputs
.clk (clk),
.reset (reset),
.enable(tb_all_vs_enable),
.mode (tb_all_vs_mode),
.D (tb_all_vs_D)
);
// // ///////////////////////////////////////////////////////////////////////////////////////////
// // //////////// DUT C
// // ////////////
// // ///////////////////////////////////////////////////////////////////////////////////////////
// counterC_module DUT_C (/*AUTOINST*/
// // outputs
// .load (C_syn_load),
// .rco (C_syn_rco),
// .Q (C_syn_Q),
// //inputs
// .clk (clk),
// .reset (reset),
// .enable (tb_all_vs_enable),
// .mode (tb_all_vs_mode),
// .D (tb_all_vs_D)
// );
//
endmodule
| 7.554736 |
module tb_alram1x;
////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
parameter WID = 10; // 10-bit long data
parameter AWID = 2; // 2-bit long address (4 addresses)
parameter DEP = 1 << AWID; // DEP = 2**AWID
////////////////////////////////////////////////////////////////////////////////
// Port declarations
reg clkw;
reg clkr;
reg clk;
reg rst;
wire [ WID-1:0] rdo;
reg [AWID-1:0] ra;
reg [ WID-1:0] wdi;
reg [AWID-1:0] wa;
reg we;
////////////////////////////////////////////////////////////////////////////////
// Local logic and instantiation
always #10 clk = ~clk;
//always #10 clkw = ~clkw;
//always #15 clkr = ~clkr;
integer i, j;
initial begin
{clk, clkw, clkr, rst, ra, wdi, wa, we} <= 0;
repeat (1) @(posedge clk);
// for writing purpose
for (i = 0; i < 2 ** AWID; i = i + 1) begin
for (j = 0; j < 2 ** AWID; j = j + 1) begin
repeat (1) @(posedge clk) ra <= j;
wa <= i;
we <= 1'b1;
wdi <= $random;
end
end
end
// DUT
alram1x u_alram1x (
clk,
clk,
rst,
rdo,
ra,
wdi,
wa,
we
);
endmodule
| 6.643206 |
module tb_alu ();
// Inputs
reg clk;
reg reset;
reg [15:0] a;
reg [15:0] b;
wire [15:0] c;
reg [7:0] cond;
wire en;
// Instantiate the Unit Under Test (UUT)
vmicro16_alu uut (
.op(5'h19),
.a (a),
.b (b),
.c (c)
);
// Instantiate the Unit Under Test (UUT)
branch branch_check (
.flags(c[3:0]),
.cond (cond),
.en (en)
);
always #10 clk = ~clk;
// Nanosecond time format
initial $timeformat(-9, 0, " ns", 10);
initial begin
$monitor($time, "\ta=%h b=%h c=%b N=%b Z=%b C=%b V=%b COND=%h EN=%b", a, b, c[3:0], c[3], c[2],
c[1], c[0], cond, en);
// Initialize Inputs
clk = 0;
cond = `VMICRO16_OP_BR_U;
a = 5'h00;
b = 5'h00;
`rassert(c == 4'b0100);
`rassert(en == 1'b1);
@(posedge clk);
@(posedge clk);
a = 5'h0A;
b = 5'h0B;
@(posedge clk);
cond = `VMICRO16_OP_BR_U;
@(posedge clk);
`rassert(c == 4'b1000);
`rassert(en == 1'b1);
cond = `VMICRO16_OP_BR_E;
@(posedge clk);
`rassert(c == 4'b1000);
`rassert(en == 1'b0);
cond = `VMICRO16_OP_BR_NE;
@(posedge clk);
`rassert(c == 4'b1000);
`rassert(en == 1'b1);
cond = `VMICRO16_OP_BR_L;
@(posedge clk);
`rassert(c == 4'b1000);
`rassert(en == 1'b1);
cond = `VMICRO16_OP_BR_G;
@(posedge clk);
`rassert(c == 4'b1000);
`rassert(en == 1'b0);
a = 5'h0B;
b = 5'h0A;
cond = `VMICRO16_OP_BR_G;
@(posedge clk);
`rassert(c == 4'b0000);
`rassert(en == 1'b1);
cond = `VMICRO16_OP_BR_L;
@(posedge clk);
`rassert(c == 4'b0000);
`rassert(en == 1'b0);
cond = `VMICRO16_OP_BR_E;
@(posedge clk);
`rassert(c == 4'b0000);
`rassert(en == 1'b0);
a = 5'h0A;
b = 5'h0A;
@(posedge clk);
`rassert(c == 4'b0100);
`rassert(en == 1'b1);
$display("ALL tests passed!");
end
endmodule
| 7.098069 |
module tb_alu_1 #(
parameter STAGE = 0,
parameter ACTION_LEN = 25,
parameter DATA_WIDTH = 48
) ();
localparam STAGE_P = 0;
reg clk;
reg rst_n;
//input from sub_action
reg [ACTION_LEN-1:0] action_in;
reg action_valid;
reg [DATA_WIDTH-1:0] operand_1_in;
reg [DATA_WIDTH-1:0] operand_2_in;
//output to form PHV
wire [DATA_WIDTH-1:0] container_out;
wire container_out_valid;
//clk signal
localparam CYCLE = 10;
localparam width_6B = 48;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
ADD ---> 0001
*/
action_in <= {
4'b0001, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 48'b1;
operand_2_in <= 48'd3;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 48'b0;
operand_2_in <= 48'd3;
#(CYCLE)
/*
SUB ---> 0010
*/
action_in <= {
4'b0010, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 48'd20;
operand_2_in <= 48'd3;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 48'b0;
operand_2_in <= 48'd3;
#(CYCLE)
/*
illegitimate action
*/
action_in <= {
4'b0011, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 48'd20;
operand_2_in <= 48'd3;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 48'b0;
operand_2_in <= 48'd3;
#(CYCLE);
end
alu_1 #(
.STAGE(STAGE),
.ACTION_LEN(),
.DATA_WIDTH(width_6B)
) alu_1_0 (
.clk(clk),
.rst_n(rst_n),
.action_in(action_in),
.action_valid(action_valid),
.operand_1_in(operand_1_in),
.operand_2_in(operand_2_in),
.container_out(container_out),
.container_out_valid(container_out_valid)
);
endmodule
| 8.144164 |
module tb_alu_2 #(
parameter STAGE = 0,
parameter ACTION_LEN = 25,
parameter DATA_WIDTH = 32
) ();
reg clk;
reg rst_n;
//input from sub_action
reg [ACTION_LEN-1:0] action_in;
reg action_valid;
reg [DATA_WIDTH-1:0] operand_1_in;
reg [DATA_WIDTH-1:0] operand_2_in;
reg [DATA_WIDTH-1:0] operand_3_in;
//output to form PHV
wire [DATA_WIDTH-1:0] container_out;
wire container_out_valid;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
ADD ---> 0001
*/
action_in <= {
4'b0001, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 32'b1;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'b0;
#(2 * CYCLE)
/*
SUB ---> 0010
*/
action_in <= {
4'b0010, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 32'd20;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(2 * CYCLE)
/*
illegitimate action
*/
action_in <= {
4'b0011, 21'b0010001001
};
action_valid <= 1'b1;
operand_1_in <= 32'd20;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(2 * CYCLE)
/*
store action
*/
action_in <= {
4'b1000, 5'b00100, 16'b11111111
};
action_valid <= 1'b1;
operand_1_in <= 32'd20;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(2 * CYCLE)
/*
load action
*/
action_in <= {
4'b1011, 5'b00100, 16'b11111111
};
action_valid <= 1'b1;
operand_1_in <= 32'd20;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(CYCLE) action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(2 * CYCLE)
/*
reset to IDLE
*/
action_in <= 25'b0;
action_valid <= 1'b0;
operand_1_in <= 32'b0;
operand_2_in <= 32'd3;
operand_3_in <= 32'd12;
#(2 * CYCLE);
end
alu_2 #(
.STAGE(STAGE),
.ACTION_LEN(),
.DATA_WIDTH() //data width of the ALU
) alu_2_0 (
.clk(clk),
.rst_n(rst_n),
//input from sub_action
.action_in(action_in),
.action_valid(action_valid),
.operand_1_in(operand_1_in),
.operand_2_in(operand_2_in),
.operand_3_in(operand_3_in),
//output to form PHV
.container_out(container_out),
.container_out_valid(container_out_valid)
);
endmodule
| 8.279935 |
module tb_alu_3 #(
parameter ACTION_LEN = 25,
parameter META_LEN = 256,
parameter COMP_LEN = 100
) ();
localparam STAGE = 0;
reg clk;
reg rst_n;
//the input data shall be metadata & com_ins
reg [META_LEN+COMP_LEN-1:0] comp_meta_data_in;
reg comp_meta_data_valid_in;
reg [ ACTION_LEN-1:0] action_in;
reg action_valid_in;
//output is the modified metadata plus comp_ins
wire [META_LEN+COMP_LEN-1:0] comp_meta_data_out;
wire comp_meta_data_valid_out;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
multicast (modify metadata)
*/
action_in <= {
4'b1100, 8'b11111111, 13'b0
};
action_valid_in <= 1'b1;
comp_meta_data_in <= 356'b0;
comp_meta_data_valid_in <= 1'b1;
#CYCLE;
action_in <= 25'b0;
action_valid_in <= 1'b0;
comp_meta_data_in <= 356'b0;
comp_meta_data_valid_in <= 1'b0;
#CYCLE;
/*
discard (modify metadata)
*/
action_in <= {4'b1101, 8'b0, 1'b1, 12'b0};
action_valid_in <= 1'b1;
comp_meta_data_in <= 356'b0;
comp_meta_data_valid_in <= 1'b1;
#CYCLE;
action_in <= 25'b0;
action_valid_in <= 1'b0;
comp_meta_data_in <= 356'b0;
comp_meta_data_valid_in <= 1'b0;
#CYCLE;
#(2 * CYCLE);
end
alu_3 #(
.STAGE(STAGE),
.ACTION_LEN(),
.META_LEN(),
.COMP_LEN()
) alu_3_0 (
.clk(clk),
.rst_n(rst_n),
//input data shall be metadata & com_ins
.comp_meta_data_in(comp_meta_data_in),
.comp_meta_data_valid_in(comp_meta_data_valid_in),
.action_in(action_in),
.action_valid_in(action_valid_in),
//output is the modified metadata plus comp_ins
.comp_meta_data_out(comp_meta_data_out),
.comp_meta_data_valid_out(comp_meta_data_valid_out)
);
endmodule
| 8.172113 |
module for the processor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ALU_microprocessor;
// Inputs
reg alu_clk;
reg [ 5:0] alu_ctrl ;
reg [31:0] in_1 ;
reg [31:0] in_2 ;
// Outputs
wire [31:0] alu_rslt ;
wire [ 4:0] alu_checks;
// Instantiate the Unit Under Test (UUT)
ALU_microprocessor alu_mp_design (
.alu_ctrl (alu_ctrl ),
.in_1 (in_1 ),
.in_2 (in_2 ),
.alu_clk (alu_clk ),
.alu_rslt (alu_rslt ),
.alu_checks(alu_checks)
);
// ALU module operates on a whopping 8.93 GHz clock frequency accurately generated by point precision
always #0.055555556 alu_clk = ~alu_clk;
initial begin
// Initialize Inputs
alu_ctrl = 0;
in_1 = 0;
in_2 = 0;
alu_clk = 0;
// Stalling some 100 cycles
repeat(100)@(posedge alu_clk);
//Initial assignments for inputs
@(posedge alu_clk);
in_1 = 32'b0;
in_2 = 32'b0;
alu_ctrl = 6'hx;
//Maximum Input randomization
repeat(10000)@(posedge alu_clk) begin
in_1 = $urandom;
in_2 = $urandom;
alu_ctrl = $urandom;
@(posedge alu_clk);
end //repeat
end //initial
endmodule
| 7.413583 |
module tb_alu_setc ();
// Inputs
reg clk;
reg reset;
reg [15:0] a;
reg [15:0] b;
reg [3:0] flags;
wire [15:0] c;
// Instantiate the Unit Under Test (UUT)
vmicro16_alu uut (
.op(`VMICRO16_ALU_SETC),
.a(a),
.b(b),
.flags(flags),
.c(c)
);
always #10 clk = ~clk;
// Nanosecond time format
initial $timeformat(-9, 0, " ns", 10);
initial begin
$monitor($time, "\tb=%h N=%b Z=%b C=%b V=%b\tc=%h", b, flags[3], flags[2], flags[1], flags[0],
c[15:0]);
// Initialize Inputs
clk = 0;
flags = 4'b0000;
a = 16'h00;
b = 16'h00;
// NZCV
@(posedge clk);
b = {8'h00, `VMICRO16_OP_BR_U};
flags = 4'b0000;
@(posedge clk);
`rassert(c == 16'h01);
b = {8'h00, `VMICRO16_OP_BR_E};
flags = 4'b0000;
@(posedge clk);
`rassert(c == 16'h00);
b = {8'h00, `VMICRO16_OP_BR_E};
flags = 4'b0100;
@(posedge clk);
`rassert(c == 16'h01);
b = {8'h00, `VMICRO16_OP_BR_L};
flags = 4'b0100; // NZCV
@(posedge clk);
`rassert(c == 16'h01);
b = {8'h00, `VMICRO16_OP_BR_G};
flags = 4'b0100; // NZCV
@(posedge clk);
`rassert(c == 16'h00);
b = {8'h00, `VMICRO16_OP_BR_G};
flags = 4'b0000; // NZCV
@(posedge clk);
`rassert(c == 16'h01);
$display("ALL tests passed!");
end
endmodule
| 7.892946 |
module: ALU_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ALU_toplevel;
// Inputs
reg [2:0] FS;
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [15:0] out;
wire zero_flag;
// Instantiate the Unit Under Test (UUT)
ALU_toplevel uut (
.FS(FS),
.A(A),
.B(B),
.out(out),
.zero_flag(zero_flag)
);
initial begin
// Initialize Inputs
FS = 0;
A = 16'b0010100111001011;
B = 16'b0010100111001011;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
FS = 3'b000;
#100;
FS = 3'b001;
#100;
FS = 3'b010;
#100;
FS = 3'b011;
#100;
FS = 3'b100;
#100;
FS = 3'b101;
#100;
end
endmodule
| 8.602857 |
module tb_AM ();
//---------接口设置----------//
reg sclk;
reg rst_n;
wire signed [13:0] AM_mod;
//--------------------------//
initial sclk = 1;
always #5 sclk = ~sclk; //100M时钟
initial begin
rst_n = 0;
#500 rst_n = 1;
end
//--------------------------//
AM_create modulate_inst0 (
.clk(sclk),
.rst_n(rst_n),
.AM_mod(AM_mod)
);
endmodule
| 7.179422 |
module AndTestbench;
reg in1;
reg in2;
wire out;
And dut (
.out(out),
.in1(in1),
.in2(in2)
);
initial begin
$display("Teste 1: in1=0, in2=0");
in1 = 0;
in2 = 0;
#1 $display("Teste 2: in1=0, in2=1");
in1 = 0;
in2 = 1;
#1 $display("Teste 3: in1=1, in2=0");
in1 = 1;
in2 = 0;
#1 $display("Teste 4: in1=1, in2=1");
in1 = 1;
in2 = 1;
end
initial begin
$monitor("Tempo :%0d\tEntrada 1: %b\tEntrada 2: %b\tSaida: %b\n", $time, in1, in2, out);
end
endmodule
| 6.967934 |
module tb_and_gate;
reg a, b;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
and_gate UUT (
.a (a),
.b (b),
.out(out)
);
initial // initial block executes only once
begin
// values for inputs
a = 0;
b = 0;
#period; // wait for period
if (out !== 0) begin
$display("test 1 failed");
$finish;
end else $display("a = %b , b = %b, out = %b", a, b, out);
a = 0;
b = 1;
#period; // wait for period
if (out !== 0) begin
$display("test 2 failed");
$finish;
end else $display("a = %b , b = %b, out = %b", a, b, out);
a = 1;
b = 0;
#period; // wait for period
if (out !== 0) begin
$display("test 3 failed");
$finish;
end else $display("a = %b , b = %b, out = %b", a, b, out);
a = 1;
b = 1;
#period; // wait for period
if (out !== 1) begin
$display("test 4 failed");
$finish;
end else $display("a = %b , b = %b, out = %b", a, b, out);
$display("all tests passed");
$finish;
end
endmodule
| 7.252918 |
module tb_apple_out ();
`define simulation
//
// GMII Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
//
//TMDS clock 74.25MHz
//
reg tmds_clk;
initial tmds_clk = 1'b0;
always #13.468 tmds_clk = ~tmds_clk;
//
// Test Bench
//
reg sys_rst;
reg rx_dv;
reg [7:0] rxd;
//reg [7:0]o_r;
//reg [7:0]o_g;
//reg [7:0]o_b;
reg [11:0] i_vcnt;
reg [11:0] i_hcnt;
wire reset_timing;
wire [7:0] o_r, o_g, o_b;
datacontroller apple_out (
.i_clk_74M(tmds_clk), //74.25 MHZ pixel clock
.i_clk_125M(sys_clk),
.i_rst(sys_rst),
.i_format(2'b00),
.i_vcnt(i_vcnt), //vertical counter from video timing generator
.i_hcnt(i_hcnt), //horizontal counter from video timing generator^M
.rx_dv(rx_dv),
.rxd(rxd),
.reset_timing(reset_timing),
.gtxclk(sys_clk),
.LED(),
.SW(),
.o_r(o_r),
.o_g(o_g),
.o_b(o_b)
);
//
// a clock
//
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
//
// Scinario
//
reg [8:0] rom[0:1620];
reg [11:0] counter = 12'd0;
always @(posedge sys_clk) begin
{rx_dv, rxd} <= rom[counter];
counter <= counter + 12'd1;
end
reg [23:0] tmds[0:1188000];
reg [20:0] tmds_count = 21'd0;
always @(posedge tmds_clk) begin
{i_hcnt, i_vcnt} <= tmds[tmds_count];
tmds_count <= tmds_count + 21'd1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_apple_out);
$readmemh("request.mem", rom);
$readmemh("tmds.mem", tmds);
sys_rst = 1'b1;
counter = 0;
tmds_count = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#1000000;
$finish;
end
endmodule
| 7.463188 |
module tb ();
reg clk, reset;
wire [31:0] porta, portb;
AProp prop (
.clk_in (clk),
.reset_in(reset),
.port_a (porta)
); //, .port_b(portb));
//ACog cog0(.clk_in(clk), .reset_in(reset));
always #6.25 clk = ~clk;
initial begin
$dumpfile("aprop.vcd");
$dumpvars(0, tb);
clk = 0;
reset = 1;
#61 reset = 0;
#5000000 $finish;
end
endmodule
| 7.195167 |
module tb_aq_axi_ssm2603;
localparam CLK100M = 10000;
localparam CLK12M = 81380; // 12.288MHz
reg ARESETN, ACLK;
// Write Address Channel
wire [31:0] S_AXI_AWADDR;
wire [ 3:0] S_AXI_AWCACHE;
wire [ 2:0] S_AXI_AWPROT;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
// Write Data Channel
wire [31:0] S_AXI_WDATA;
wire [ 3:0] S_AXI_WSTRB;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
// Write Response Channel
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [ 1:0] S_AXI_BRESP;
// Read Address Channe
wire [31:0] S_AXI_ARADDR;
wire [ 3:0] S_AXI_ARCACHE;
wire [ 2:0] S_AXI_ARPROT;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
// Read Data Channel
wire [31:0] S_AXI_RDATA;
wire [ 1:0] S_AXI_RRESP;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
reg MCLK;
wire BCLK, PBLRC, PBDAT;
wire RECLRC;
wire RECDAT;
reg FIFO_RD_EMPTY;
wire FIFO_RD_ENA;
reg [31:0] FIFO_RD_DATA;
wire FIFO_WR_ENA;
wire [31:0] FIFO_WR_DATA;
// Clock
always begin
#(CLK100M / 2) ACLK = ~ACLK;
end
always begin
#(CLK12M / 2) MCLK = ~MCLK;
end
initial begin
ARESETN = 1'b0;
ACLK = 1'b0;
MCLK = 1'b0;
repeat (5) @(posedge MCLK);
ARESETN = 1'b1;
repeat (10) @(posedge MCLK);
repeat (2000) @(posedge MCLK);
$finish();
end
aq_axi_ssm2603 u_aq_axi_ssm2603 (
// Reset, Clock
.ARESETN(ARESETN),
.ACLK(ACLK),
// Write Address Channel
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
// Write Data Channel
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
// Write Response Channel
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
// Read Address Channel
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
// Read Data Channel
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
// SSM2603
.MCLK(MCLK),
.BCLK (BCLK),
.PBLRC (PBLRC),
.PBDAT (PBDAT),
.RECLRC(RECLRC),
.RECDAT(RECDAT),
.FIFO_RD_EMPTY(FIFO_RD_EMPTY),
.FIFO_RD_ENA (FIFO_RD_ENA),
.FIFO_RD_DATA (FIFO_RD_DATA),
.FIFO_WR_ENA (FIFO_WR_ENA),
.FIFO_WR_DATA (FIFO_WR_DATA)
);
assign RECDAT = PBDAT;
/*
* AXI Lite Slave
*/
aq_axi_lite_master_model bfm (
.ARESETN(ARESETN),
.ACLK(ACLK),
// Write Address Channel
.S_AXI_AWADDR (S_AXI_AWADDR),
// .S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
// Write Data Channel
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
// Write Response Channel
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
// Read Address Channel
.S_AXI_ARADDR (S_AXI_ARADDR),
// .S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
// Read Data Channel
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
initial begin
wait (!ARESETN);
@(negedge ACLK);
@(negedge ACLK);
// bfm.wrdata(32'h0000_0004, 32'h0000_0001); // half=0,max=1
// bfm.wrdata(32'h0000_0000, 32'h0000_0001); // 32bit, enable
bfm.wrdata(32'h0000_0004, 32'h0000_0307); // half=1, max=1
bfm.wrdata(32'h0000_0000, 32'h0000_0101); // 16bit, enable
end
initial begin
FIFO_RD_EMPTY = 1'b0;
FIFO_RD_DATA = 32'h12345678;
end
endmodule
| 6.61578 |
module tb_i2c_master;
// Inputs
reg rst_n;
reg clk;
reg [3:0] cmd_wr;
reg [31:0] cmd_din;
reg [9:0] adrs;
reg [3:0] wena;
reg [31:0] wdata;
reg isda;
// Outputs
wire [31:0] cmd_dout;
wire [31:0] rdata;
wire osda;
wire osck;
tri1 sda;
// Instantiate the Unit Under Test (UUT)
aq_i2c_master uut (
.rst_n(rst_n),
.clk(clk),
.cmd_wr(cmd_wr),
.cmd_din(cmd_din),
.cmd_dout(cmd_dout),
.adrs(adrs),
.wena(wena),
.wdata(wdata),
.rdata(rdata),
.osda(osda),
.isda(sda),
.osck(osck)
);
assign sda = (osda) ? 1'bZ : 1'b0;
aq_i2c_slave_model u_i2c_slabe_model (
.sck(osck),
.sda(sda)
);
always begin
#5 clk = ~clk;
end
initial begin
// Initialize Inputs
rst_n = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst_n = 1;
end
reg [31:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count[31:0] <= 32'd0;
end else begin
count[31:0] <= count[31:0] + 32'd1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cmd_wr <= 0;
cmd_din <= 0;
adrs <= 0;
wena <= 0;
wdata <= 0;
isda <= 0;
end else begin
case (count[31:0])
32'd1: begin
wena <= 4'hF;
adrs <= 10'h0;
wdata <= 32'h00610160;
end
32'd2: begin
wena <= 4'hF;
adrs <= 10'h4;
wdata <= 32'h99008F66;
end
32'd3: begin
wena <= 4'hF;
adrs <= 10'h8;
wdata <= 32'hFFEEDDCC;
end
32'd5: begin
cmd_wr <= 4'hF;
// cmd_din <= {1'b0, 6'd0, 9'd3, 7'd0, 9'd5};
cmd_din <= {1'b0, 6'd0, 9'd0, 7'd0, 9'd2};
end
32'd1100000: begin
wena <= 4'hF;
adrs <= 10'h0;
wdata <= 32'h00000061;
end
32'd1100001: begin
cmd_wr <= 4'hF;
cmd_din <= {1'b1, 6'd0, 9'd8, 7'd0, 9'd1};
end
32'd1200000: begin
adrs <= 10'h200;
end
32'd4000000: begin
$finish();
end
default: begin
cmd_wr <= 0;
cmd_din <= 0;
adrs <= 0;
wena <= 0;
wdata <= 0;
isda <= 0;
end
endcase
end
end
endmodule
| 7.069776 |
module tb_aq_sg;
reg RST_N1;
reg RST_N2;
reg CLK;
wire VSYNC;
wire HSYNC;
wire FSYNC;
wire ACTIVE;
reg ERROR;
aq_sg u_aq_sg (
.RST_N(RST_N2),
.CLK (CLK),
.VSYNC (VSYNC),
.HSYNC (HSYNC),
.FSYNC (FSYNC),
.ACTIVE(ACTIVE),
.DEBUG()
);
wire active_video_out, hsync_out, vsync_out;
design_1_wrapper u_design_1_wrapper (
.active_video_out(active_video_out),
.clk(CLK),
.hsync_out(hsync_out),
.resetn(RST_N1),
.vsync_out(vsync_out)
);
parameter CLK100M = 10;
initial begin
RST_N1 <= 1'b0;
RST_N2 <= 1'b0;
CLK <= 1'b0;
#100;
@(posedge CLK);
RST_N1 <= 1'b1;
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
RST_N2 <= 1'b1;
end
always begin
#(CLK100M / 2) CLK <= ~CLK;
end
always @(posedge CLK or negedge RST_N2) begin
if (!RST_N2) begin
ERROR <= 0;
end else begin
ERROR <= (vsync_out ^ VSYNC) | (hsync_out ^ HSYNC);
end
end
endmodule
| 6.573099 |
module tb_arithmetic_circuits (); // Signed RCA
reg [3:0] x;
reg [3:0] y;
reg ci;
wire cout;
wire [3:0] s;
wire signed [4:0] carry_with_sum;
assign carry_with_sum = {cout, s};
SRCA UUT (
x,
y,
ci,
cout,
s
);
integer i, j;
initial begin
ci = 0;
for (i = -8; i < 8; i = i + 1) begin
x = i;
for (j = -8; j < 8; j = j + 1) begin
y = j;
#20;
end
end
$finish;
end
endmodule
| 7.083368 |
module tb_arithmetic_circuits (); // UNTILL RCA ADDER + CLA
reg [3:0] x;
reg [3:0] y;
reg ci;
wire cout;
wire [3:0] s;
RCA UUT (
x,
y,
ci,
cout,
s
);
integer i;
initial begin
for (i = 0; i < 512; i = i + 1) begin
{x, y, ci} = i;
#20;
end
$finish;
end
endmodule
| 7.083368 |
module tb_arithmetic_circuits (); // - FOR PARAM RCA
parameter SIZE = 8;
reg [SIZE-1:0] x;
reg [SIZE-1:0] y;
reg cin;
wire cout;
wire [SIZE-1:0] s;
parametric_RCA UUT (
x,
y,
cin,
cout,
s
);
integer i;
initial begin
x = 199;
y = 121;
cin = 1;
#20 x = 255;
y = 255;
cin = 1;
#20 x = 1;
y = 0;
cin = 0;
#20 x = 53;
y = 45;
cin = 0;
#20 x = 127;
y = 127;
#20;
$finish;
end
endmodule
| 7.083368 |
module tb_arithmetic_circuits(); -- UNTILL RCA ADDER
reg [3:0]x;
reg [3:0]y;
reg ci;
wire cout;
wire [3:0]s;
RCA UUT(x,y,ci,cout,s);
integer i;
initial
begin
for(i =0; i<512;i = i + 1) begin
{x,y,ci} = i;
#20;
end
$finish;
end
endmodule
| 7.083368 |
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