code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module of four enemy's tanks
Modification History:
Date By Version Description
----------------------------------------------------------
180505 ctlvie 0.5 Module interface definition
180507 ctlvie 0.6 Add tank_state interfaces
180508 ctlvie 1.0 Initial coding completed(unverified)
180508 ctlvie 1.1 Corrected the reg conflict error(unverified)
180510 ctlvie 1.5 Full Version!
180525 ctlvie 2.0 Final Version
========================================================*/
`timescale 1ns/1ns
module tank_generate
(
input clk_4Hz,
input tank1_state,
input tank2_state,
input tank3_state,
input tank4_state,
output reg tank1_en,
output reg tank2_en,
output reg tank3_en,
output reg tank4_en
);
reg [3:0] cnt_reg_1;
reg [3:0] cnt_reg_2;
reg [3:0] cnt_reg_3;
reg [3:0] cnt_reg_4;
reg [5:0] cnt_game_start;
reg game_start_flag;
initial
begin
game_start_flag <= 1'b0;
cnt_reg_1 <= 4'b0;
cnt_reg_2 <= 4'b0;
cnt_reg_3 <= 4'b0;
cnt_reg_4 <= 4'b0;
cnt_game_start <= 6'b0;
end
always@(posedge clk_4Hz)
begin
if (game_start_flag == 1'b0)
begin
cnt_game_start <= cnt_game_start + 1'b1;
if (cnt_game_start >= 4)
begin
tank1_en <= 1'b1;
end
if (cnt_game_start >= 16)
begin
tank2_en <= 1'b1;
tank1_en <= 1'b0;
end
if (cnt_game_start >= 28)
begin
tank3_en <= 1'b1;
tank2_en <= 1'b0;
end
if (cnt_game_start >= 40)
begin
tank4_en <= 1'b1;
tank3_en <= 1'b0;
end
if (cnt_game_start >= 52)
begin
tank4_en <= 1'b0;
game_start_flag <= 1'b1;
cnt_game_start <= 6'b0;
end
end
else
begin
if (tank1_state == 0)
cnt_reg_1 <= cnt_reg_1 + 1'b1;
if (tank2_state == 0)
cnt_reg_2 <= cnt_reg_2 + 1'b1;
if (tank3_state == 0)
cnt_reg_3 <= cnt_reg_3 + 1'b1;
if (tank4_state == 0)
cnt_reg_4 <= cnt_reg_4 + 1'b1;
if (cnt_reg_1 >= 12 && cnt_reg_1 <= 15)
begin
cnt_reg_1 <= cnt_reg_1 + 1'b1;
tank1_en <= 1'b1;
end
if (cnt_reg_2 >= 12 && cnt_reg_2 <= 15)
begin
cnt_reg_2 <= cnt_reg_2 + 1'b1;
tank2_en <= 1'b1;
end
if (cnt_reg_3 >= 12 && cnt_reg_3 <= 15)
begin
cnt_reg_3 <= cnt_reg_3 + 1'b1;
tank3_en <= 1'b1;
end
if (cnt_reg_4 >= 12 && cnt_reg_4 <= 15)
begin
cnt_reg_4 <= cnt_reg_4 + 1'b1;
tank4_en <= 1'b1;
end
if (cnt_reg_1 == 16)
begin
tank1_en <= 0;
cnt_reg_1 <= 1'b0;
end
if (cnt_reg_2 == 16)
begin
tank2_en <= 0;
cnt_reg_2 <= 1'b0;
end
if (cnt_reg_3 == 16)
begin
tank3_en <= 0;
cnt_reg_3 <= 1'b0;
end
if (cnt_reg_4 == 16)
begin
tank4_en <= 0;
cnt_reg_4 <= 1'b0;
end
end
end
endmodule
| 6.72321 |
module tank_graphic (
x,
y,
flush_x,
flush_y,
direction,
colour,
enable
);
input [7:0] x;
input [7:0] y;
input [7:0] flush_x;
input [7:0] flush_y;
input [1:0] direction;
output [5:0] colour;
output enable;
wire [6:0] lut_out;
tank_graphic_lut(
flush_x - x, flush_y - y, lut_out
);
assign colour = lut_out[5:0];
assign enable = lut_out[6];
endmodule
| 6.526884 |
module selector_drawer_fsm (
x_out,
y_out,
colour_out,
done,
colour1,
x,
y,
load,
clk,
reset
);
endmodule
| 6.778432 |
module game_controller_fsm (
load_p,
load_s,
x_out,
y_out,
colour1_out,
colour2_out,
done_p,
done_s,
selector,
direction,
clk,
reset
);
input [3:0] selector; // Changes the cell the selector is on
input [3:0] direction; // Tries to move the selected peice up, down, left, right
input done_p, done_s; // Signals for when the other fsm's are done thier drawing.
input clk, reset; // Clk is clock, and reset resets.
output load_p, load_s; // The signals given to the piece_drawer_fsm and selector_drawer_fsm
output [7:0] x_out; // X and Y are the top left corner of what ever we want to draw
output [6:0] y_out;
output [2:0] colour1_out, colour2_out; // Two colour outputs used by the drawers.
reg [2:0] curr_state = RESET;
reg [2:0] next_state = DRAW_BOARD;
reg player_turn = 0;
reg player_input = 2'b00;
// Registers for holding the board information
// Each cell is 3 bits, and thus a 4x4 board.
// bit[2] -> 0 : black, 1 : white;
// bits[1:0] -> 00 : black, 11 : white, 01 : blue, 10 : yellow;
reg cells[47:0] = {
3'b001,
3'b111,
3'b000,
3'b110,
3'b101,
3'b000,
3'b111,
3'b010,
3'b001,
3'b111,
3'b000,
3'b110,
3'b101,
3'b000,
3'b111,
3'b010
};
assign player_has_input = in[0] | in[1] | in[2] | in[3];
parameter RESET = 3'b000, DRAW_BOARD = 3'b001, WAIT_BOARD_DONE = 3'b010, DRAW_SELECTOR = 3'b011,
WAIT_SELECTOR_DONE = 3'b100, WAIT_PLAYER = 3'b101, DO_LOGIC = 3'b110;
always @(*) begin
case (curr_state)
RESET: next_state = reset ? RESET : DRAW_BOARD;
DRAW_BOARD: next_state = WAIT_BOARD_DONE;
WAIT_BOARD_DONE: next_state = done_p ? DRAW_SELECTOR : WAIT_BOARD_DONE;
DRAW_SELECTOR: next_state = WAIT_SELECTOR_DONE;
WAIT_SELECTOR_DONE: next_state = done_s ? WAIT_PLAYER : WAIT_SELECTOR_DONE;
WAIT_PLAYER: next_state = player_has_input ? DO_LOGIC : WAIT_PLAYER;
DO_LOGIC: next_state = DRAW_BOARD;
endcase
end
endmodule
| 7.681663 |
module tap (
// Inputs
tck, // External Clock Source
tms, // State Machine Control
// Outputs
reset, // Register Reset signal
select, // Selects between IR and DR TDO signals
enable, // Enables TDO output (in Shift_Ir or Shift_Dr state)
// Instruction Register Signals
clock_ir, // Clock for Instruction Register Latches
capture_ir, // Signal to shift previous state out of the Shadow Latches
shift_ir, // Signal to shift TDI into Serial Latches
update_ir, // Singal to shift Serial state into Shadow Latches
// Data Register Signals
clock_dr, // Clock for Instruction Register Latches
capture_dr, // Signal to shift previous state out of the Shadow Latches
shift_dr, // Signal to shift TDI into Serial Latches
update_dr // Singal to shift Serial state into Shadow Latches
);
input tck, tms;
output reset, select, enable, clock_ir, capture_ir, shift_ir, update_ir, clock_dr, capture_dr, shift_dr, update_dr;
reg [3:0] state;
/*
JTAG TAP controller
TMS/TDI are sampled on the rising edge of TCK
TDO is sampled on the falling edge of TCK
*/
parameter // States of TAP Controller
Run_Test_Idle = 4'b0000,
Select_Dr = 4'b0001,
Capture_Dr = 4'b0010,
Shift_Dr = 4'b0011,
Exit1_Dr = 4'b0100,
Pause_Dr = 4'b0101,
Exit2_Dr = 4'b0110,
Update_Dr = 4'b0111,
Reset = 4'b1000,
Select_Ir = 4'b1001,
Capture_Ir = 4'b1010,
Shift_Ir = 4'b1011,
Exit1_Ir = 4'b1100,
Pause_Ir = 4'b1101,
Exit2_Ir = 4'b1110,
Update_Ir = 4'b1111;
always @(posedge tck) begin
case (state)
Run_Test_Idle: if (tms == 0) state = Run_Test_Idle;
else state = Select_Dr;
Select_Dr: if (tms == 0) state = Capture_Dr;
else state = Select_Ir;
Capture_Dr: if (tms == 0) state = Shift_Dr;
else state = Exit1_Dr;
Shift_Dr: if (tms == 0) state = Shift_Dr;
else state = Exit1_Dr;
Exit1_Dr: if (tms == 0) state = Pause_Dr;
else state = Update_Dr;
Pause_Dr: if (tms == 0) state = Pause_Dr;
else state = Exit2_Dr;
Exit2_Dr: if (tms == 0) state = Shift_Dr;
else state = Update_Dr;
Update_Dr: if (tms == 0) state = Run_Test_Idle;
else state = Select_Dr;
Select_Ir: if (tms == 0) state = Capture_Ir;
else state = Reset;
Capture_Ir: if (tms == 0) state = Shift_Ir;
else state = Exit1_Ir;
Shift_Ir: if (tms == 0) state = Shift_Ir;
else state = Exit1_Ir;
Exit1_Ir: if (tms == 0) state = Pause_Ir;
else state = Update_Ir;
Pause_Ir: if (tms == 0) state = Pause_Ir;
else state = Exit2_Ir;
Exit2_Ir: if (tms == 0) state = Shift_Ir;
else state = Update_Ir;
Update_Ir: if (tms == 0) state = Run_Test_Idle;
else state = Select_Dr;
Reset: if (tms == 0) state = Run_Test_Idle;
else state = Reset;
default: state = Reset;
endcase
end
// Output Assignments
assign reset = (state == 4'b1000);
assign select = state[3]; // 1 for IR, 0 otherwise
assign capture_ir = (state == Capture_Ir);
assign shift_ir = (state == Shift_Ir);
assign update_ir = (state == Update_Ir);
assign clock_ir = ((capture_ir || shift_ir || update_ir) && ~tck);
assign capture_dr = (state == Capture_Dr);
assign shift_dr = (state == Shift_Dr);
assign update_dr = (state == Update_Dr);
assign clock_dr = ((capture_dr || shift_dr || update_dr) && ~tck);
assign enable = shift_ir || shift_dr;
endmodule
| 6.779865 |
module tap_controller (
input tck,
tms,
trst,
output cdr1,
sdr1,
udr1,
cir1,
sir1,
uir1
);
/*where -
c= capture
u= update
s= shift
dr= data register
ir= instruction register
tck = input clock
tms = state mode signal
trst= reset signal
*/
localparam TEST_LOGIC_RESET = 4'h0;
localparam RUN_TEST_IDLE = 4'h1;
localparam SELECT_DR = 4'h2;
localparam CAPTURE_DR = 4'h3;
localparam SHIFT_DR = 4'h4;
localparam EXIT1_DR = 4'h5;
localparam EXIT2_DR = 4'h6;
localparam UPDATE_DR = 4'h7;
localparam PAUSE_DR = 4'h8;
localparam SELECT_IR = 4'h9;
localparam CAPTURE_IR = 4'hA;
localparam SHIFT_IR = 4'hB;
localparam EXIT1_IR = 4'hC;
localparam EXIT2_IR = 4'hD;
localparam UPDATE_IR = 4'hE;
localparam PAUSE_IR = 4'hf;
reg [3:0] state; // next_state;
//reg cdr1, sdr1, udr1, cir1,sir1,uir1;
assign cdr1 = (state == CAPTURE_DR);
assign sdr1 = (state == SHIFT_DR);
assign udr1 = (state == UPDATE_DR);
assign cir1 = (state == CAPTURE_IR);
assign sir1 = (state == SHIFT_IR);
assign uir1 = (state == UPDATE_IR);
always @(posedge tck or negedge trst) begin
if (~trst) begin
state <= TEST_LOGIC_RESET;
end else begin
/*
state <= next_state;
end
end
always@(*)begin */
case (state)
TEST_LOGIC_RESET:
if (tms) state <= TEST_LOGIC_RESET;
else state <= RUN_TEST_IDLE;
RUN_TEST_IDLE:
if (tms) state <= SELECT_DR;
else state <= RUN_TEST_IDLE;
SELECT_DR:
if (tms) state <= SELECT_IR;
else state <= CAPTURE_DR;
CAPTURE_DR:
if (tms) begin
state <= EXIT1_DR;
end else state <= SHIFT_DR;
SHIFT_DR:
if (tms) begin
state <= EXIT1_DR;
end else state <= SHIFT_DR;
EXIT1_DR:
if (tms) state <= UPDATE_DR;
else state <= PAUSE_DR;
PAUSE_DR:
if (tms) state <= EXIT2_DR;
else state <= PAUSE_DR;
EXIT2_DR:
if (tms) state <= UPDATE_DR;
else state <= SHIFT_DR;
UPDATE_DR:
if (tms) begin
state <= SELECT_DR;
end else state <= RUN_TEST_IDLE;
//Instruction
SELECT_IR:
if (tms) state <= TEST_LOGIC_RESET;
else state <= CAPTURE_IR;
CAPTURE_IR:
if (tms) begin
state <= EXIT1_IR;
end else state <= SHIFT_IR;
SHIFT_IR:
if (tms) begin
state <= EXIT1_IR;
end else state <= SHIFT_IR;
EXIT1_IR:
if (tms) state <= UPDATE_IR;
else state <= PAUSE_IR;
PAUSE_IR:
if (tms) state <= EXIT2_IR;
else state <= PAUSE_IR;
EXIT2_IR:
if (tms) state <= UPDATE_IR;
else state <= SHIFT_IR;
UPDATE_IR:
if (tms) begin
state <= SELECT_DR;
end else state <= RUN_TEST_IDLE;
//default : next_state = TEST_LOGIC_RESET;
endcase
end
end
endmodule
| 6.775217 |
module tape (
input reset,
input clk,
input ce_1m,
input ioctl_download,
input tape_pause,
output reg tape_audio,
output tape_active,
output reg tape_rd,
output reg [24:0] tape_addr,
input [ 7:0] tape_data
);
reg [23:0] cnt;
assign tape_active = (cnt > 0);
always @(posedge clk) begin
reg [23:0] size;
//reg [7:0] version;
reg [23:0] tmp;
reg [26:0] bit_cnt, bit_half;
reg ioctl_downloadD;
reg [2:0] reload32;
reg byte_ready;
reg [7:0] din;
reg play_pause;
reg pauseD;
pauseD <= tape_pause;
if (tape_pause && ~pauseD) play_pause <= !play_pause;
if (reset || ioctl_download) begin
cnt <= 0;
reload32 <= 0;
byte_ready <= 0;
play_pause <= 0;
tape_rd <= 0;
size <= 0;
bit_cnt <= 0;
ioctl_downloadD <= ioctl_download;
end else if (ce_1m) begin
ioctl_downloadD <= ioctl_download;
tape_rd <= 0;
if (tape_rd) begin
byte_ready <= 1;
din <= tape_data;
end
// download complete, start parsing
if (!ioctl_download && ioctl_downloadD) begin
cnt <= 8;
tape_rd <= 1;
tape_addr <= 12;
end
if (cnt != 0) begin
if (byte_ready) begin
if (tape_addr < 20) begin
cnt <= cnt - 1'd1;
tape_addr <= tape_addr + 1'd1;
byte_ready <= 0;
tape_rd <= 1;
case (tape_addr)
//12: version <= din;
16: size[7:0] <= din;
17: size[15:8] <= din;
18: size[23:16] <= din;
19: cnt <= size ? size : 24'd0;
default: ;
endcase
end else begin
if (bit_cnt <= 1) begin
cnt <= cnt - 1'd1;
tape_addr <= tape_addr + 1'd1;
byte_ready <= 0;
tape_rd <= 1;
if (reload32 != 0) begin
tmp <= {din, tmp[23:8]};
reload32 <= reload32 - 1'd1;
if (reload32 == 1) begin
bit_cnt <= {din, tmp[23:8], 3'd0};
bit_half <= {din, tmp[23:8], 2'd0};
tape_audio <= 1;
end
end else if (din == 0) begin
reload32 <= 3;
end else begin
bit_cnt <= {din, 3'd0};
bit_half <= {din, 2'd0};
tape_audio <= 1;
end
end
end
end
if (!play_pause && (bit_cnt > 1)) begin
bit_cnt <= bit_cnt - 1'd1;
if (bit_cnt < bit_half) tape_audio <= 0;
end
end
end
end
endmodule
| 6.742839 |
module used to instantiate I/O pads and connect them with the block-level design
//----------------------------------------------------------------------
// Pads
//----------------------------------------------------------------------
// EN : If 1, DOUT writes to PAD, if 0, short from PAD to DIN
// DOUT : Output of the chip, to the iocell, on the chip side
// DIN : Input to the chip from the iocell, on the chip side
// PAD : Signal pin on the pad side, (to the outside world)
//
// _______________________________________
// |
// ______________ EN |
// | |----------|
// PAD---| Iocell Pad | DIN | Chip Core Area
// | |----------|
// | | DOUT |
// |______________|----------|
// |
// ______________ |
// | | |
`define OUTPUT_PAD(name, pad, signal) \
BidirectionalIOPad name \
( \
.EN (1'b1 ), \
.DOUT(signal), \
.DIN ( ), \
.PAD (pad ) \
);
`define INPUT_PAD(name, pad, signal) \
BidirectionalIOPad name \
( \
.EN (1'b0 ), \
.DOUT( ), \
.DIN (signal), \
.PAD (pad ) \
);
//----------------------------------------------------------------------
// Design
//----------------------------------------------------------------------
module TapeOutBlockRTL__chip_top
(
input wire clk ,
input wire reset ,
input wire cs ,
output wire miso ,
input wire mosi ,
input wire sclk ,
input wire loopthrough_sel,
output wire minion_parity,
output wire adapter_parity
);
// From iocell to core area
logic clk_core;
logic cs_core;
logic miso_core;
logic mosi_core;
logic reset_core;
logic sclk_core;
logic minion_parity_core;
logic adapter_parity_core;
//name pad signal
`INPUT_PAD( clk_pad, clk, clk_core )
`INPUT_PAD( reset_pad, reset, reset_core )
`INPUT_PAD( cs_pad, cs, cs_core )
`OUTPUT_PAD( miso_pad, miso, miso_core )
`INPUT_PAD( mosi_pad, mosi, mosi_core )
`INPUT_PAD( sclk_pad, sclk, sclk_core )
`INPUT_PAD( loopthrough_sel_pad, loopthrough_sel, loopthrough_sel_core )
`OUTPUT_PAD( minion_parity_pad, minion_parity, minion_parity_core )
`OUTPUT_PAD( adapter_parity_pad, adapter_parity, adapter_parity_core )
// MODIFY THIS MODULE INSTANTIATION TO BE THE APPROPRIATE PARAMETER VALUES FOR YOUR DESIGN
SPI_TapeOutBlockRTL_32bits_5entries TapeOutBlock
(
.clk(clk_core),
.reset(reset_core),
.cs(cs_core),
.miso(miso_core),
.mosi(mosi_core),
.sclk(sclk_core),
.loopthrough_sel(loopthrough_sel_core),
.minion_parity(minion_parity_core),
.adapter_parity(adapter_parity_core)
);
endmodule
| 8.144031 |
module TappedDelayRegister (
input wire iClock,
input wire iEnable,
input wire [3:0] iM,
input wire [15:0] iData,
output wire [15:0] oData
);
parameter LENGTH = 32;
integer i;
reg [15:0] delay[0:LENGTH - 1];
reg [15:0] delay_tap;
assign oData = delay_tap;
always @(posedge iClock) begin
if (iEnable) begin
if (iM == 15) delay_tap <= iData;
else delay_tap <= delay[iM];
for (i = LENGTH - 1; i > 0; i = i - 1) begin
delay[i] <= delay[i-1];
end
delay[0] <= iData;
end
end
endmodule
| 6.744653 |
module tapped_fifo #(
parameter WIDTH = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] inp,
output wire [WIDTH*DEPTH-1:0] taps,
output wire [WIDTH-1:0] outp
);
reg [WIDTH-1:0] regs[DEPTH];
assign outp = regs[DEPTH-1];
dff #(WIDTH) sr0 (
clk,
rst,
inp,
regs[0]
);
assign taps[(WIDTH*DEPTH-1):(WIDTH*(DEPTH-1))] = regs[0];
genvar i;
generate
for (i = 0; i < DEPTH - 1; i++) begin : shift
dff #(WIDTH) sr (
clk,
rst,
regs[i],
regs[i+1]
);
assign taps[((WIDTH*DEPTH-1)-(WIDTH*(i+1))):(WIDTH*(DEPTH-(i+2)))] = regs[i+1];
end
endgenerate
endmodule
| 7.41901 |
module tapped_fifo_test1 (
input clk,
input rst,
input wire inp,
output wire [9:0] taps,
output wire outp
);
tapped_fifo #(
.WIDTH(1),
.DEPTH(10)
) f_1_10 (
clk,
rst,
inp,
taps,
outp
);
endmodule
| 6.789807 |
module tapped_fifo_test2 (
input clk,
input rst,
input wire [31:0] inp,
output wire [(32*10-1):0] taps,
output wire [31:0] outp
);
tapped_fifo #(
.WIDTH(32),
.DEPTH(10)
) f_1_10 (
clk,
rst,
inp,
taps,
outp
);
endmodule
| 6.789807 |
module taps (
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clk,
reset,
sel,
newt,
d,
x
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clk;
input reset;
input [1:0] sel;
input newt;
input [7:0] d;
output [7:0] x;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
// Wire Declaration
reg [7:0] x, xn, xn_1, xn_2, xn_3;
// Register element
always @(posedge clk or posedge reset) begin
if (reset) begin
xn = 8'b00000000;
xn_1 = 8'b00000000;
xn_2 = 8'b00000000;
xn_3 = 8'b00000000;
end else if (newt) begin
xn_3 = xn_2;
xn_2 = xn_1;
xn_1 = xn;
xn = d;
end
end
// Mux element
always @(sel or xn or xn_1 or xn_2 or xn_3)
case (sel)
2'b00: x = xn;
2'b01: x = xn_1;
2'b10: x = xn_2;
2'b11: x = xn_3;
default: x = 8'bXXXXXXXX;
endcase
endmodule
| 7.378744 |
module taptempo #(
parameter CLK_PER_NS = 40, // 25Mhz clock
parameter TP_CYCLE = 5120, // Number of cycles per timepulse
parameter BPM_MAX = 250
) (
input clk_i,
input btn_i,
output pwm_o
);
/* generate reset internally */
wire rst;
rstgen inst_rstgen (
.clk_i(clk_i),
.rst_o(rst)
);
/* TimePulse generation */
wire tp;
timepulse #(
.CLK_PER_NS (CLK_PER_NS),
.PULSE_PER_NS(TP_CYCLE)
) inst_timepulse (
.clk_i(clk_i),
.rst_i(rst),
.tp_o (tp)
);
/* Synchronize btn_i to avoid metastability*/
reg btn_old, btn_s;
always @(posedge clk_i or posedge rst) begin
if (rst) begin
btn_old <= 1'b0;
btn_s <= 1'b0;
end else begin
btn_old <= btn_i;
btn_s <= btn_old;
end
end
/* then debounce */
wire btn_d;
debounce #(
.PULSE_PER_NS(TP_CYCLE),
.DEBOUNCE_PER_NS(50_000_000) // 50ms
) inst_debounce (
.clk_i(clk_i),
.rst_i(rst),
.tp_i (tp),
.btn_i(btn_s),
.btn_o(btn_d)
);
/* count tap period */
`define MIN_NS 60_000_000_000
`define BTN_PER_MAX (`MIN_NS/TP_CYCLE)
`define BTN_PER_SIZE ($clog2(1 + `BTN_PER_MAX))
wire [(`BTN_PER_SIZE-1):0] btn_per;
wire btn_per_valid;
percount #(
.CLK_PER_NS (CLK_PER_NS),
.PULSE_PER_NS(TP_CYCLE),
) inst_percount (
.clk_i(clk_i),
.rst_i(rst),
.tp_i(tp),
.btn_i(btn_d),
.btn_per_o(btn_per),
.btn_per_valid(btn_per_valid)
);
/* convert period in bpm */
`define BPM_SIZE ($clog2(BPM_MAX + 1))
wire [(`BPM_SIZE -1):0] bpm;
wire bpm_valid;
per2bpm #(
.CLK_PER_NS(CLK_PER_NS),
.TP_CYCLE(TP_CYCLE),
.BPM_MAX(BPM_MAX)
) inst_per2bpm (
.clk_i(clk_i),
.rst_i(rst),
.btn_per_i(btn_per),
.btn_per_valid(btn_per_valid),
.bpm_o(bpm),
.bpm_valid(bpm_valid)
);
/* output pwm */
pwmgen #(
.BPM_MAX(BPM_MAX)
) inst_pwmgen (
.clk_i(clk_i),
.rst_i(rst),
.tp_i(tp),
.bpm_i(bpm),
.bpm_valid(bpm_valid),
.pwm_o(pwm_o)
);
endmodule
| 7.012471 |
module draw_target_k #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, WIDTH=40,HEIGHT=30, MEMFILE="") (
// input wire clk,
// input wire w_write,
// input wire [10:0] w_current_x,
// input wire [10:0] w_current_y,
// input wire [10:0] w_pos_x,
// input wire [10:0] w_pos_y,
// output reg [DATA_WIDTH-1:0] r_out_data
// );
// wire [ADDR_WIDTH-1:0] w_address;
// wire [DATA_WIDTH-1:0] w_data;
// sram #(
// .ADDR_WIDTH(ADDR_WIDTH),
// .DATA_WIDTH(DATA_WIDTH),
// .DEPTH(WIDTH*HEIGHT),
// .MEMFILE(MEMFILE))
// vram_read (
// .w_addr(address),
// .clk(clk),
// .w_write(0),
// .w_in_data(0),
// .r_out_data(data)
// );
// assign w_write = (((w_pos_x <= w_current_x) && (w_current_x < w_pos_x + WIDTH)) &&
// ((w_pos_y <= w_current_y) && (w_current_y < w_pos_y + HEIGHT)));
// assign address = (w_write) ? ((w_current_y - w_pos_y) * WIDTH + (w_current_x - w_pos_x)) : 0;
// always @(posedge clk) r_out_data <= w_data;
//endmodule
| 6.569762 |
module target_graphic_lut (
x,
y,
out
);
input [7:0] x;
input [7:0] y;
output reg [6:0] out;
always @(*) begin
out[6] <= 1'b1;
case ({
x, y
})
16'h0200: out[5:0] <= 6'b111111;
16'h0800: out[5:0] <= 6'b111111;
16'h0301: out[5:0] <= 6'b111111;
16'h0701: out[5:0] <= 6'b111111;
16'h0202: out[5:0] <= 6'b111111;
16'h0302: out[5:0] <= 6'b111111;
16'h0402: out[5:0] <= 6'b111111;
16'h0502: out[5:0] <= 6'b111111;
16'h0602: out[5:0] <= 6'b111111;
16'h0702: out[5:0] <= 6'b111111;
16'h0802: out[5:0] <= 6'b111111;
16'h0103: out[5:0] <= 6'b111111;
16'h0203: out[5:0] <= 6'b111111;
16'h0403: out[5:0] <= 6'b111111;
16'h0503: out[5:0] <= 6'b111111;
16'h0603: out[5:0] <= 6'b111111;
16'h0803: out[5:0] <= 6'b111111;
16'h0903: out[5:0] <= 6'b111111;
16'h0004: out[5:0] <= 6'b111111;
16'h0104: out[5:0] <= 6'b111111;
16'h0204: out[5:0] <= 6'b111111;
16'h0304: out[5:0] <= 6'b111111;
16'h0404: out[5:0] <= 6'b111111;
16'h0504: out[5:0] <= 6'b111111;
16'h0604: out[5:0] <= 6'b111111;
16'h0704: out[5:0] <= 6'b111111;
16'h0804: out[5:0] <= 6'b111111;
16'h0904: out[5:0] <= 6'b111111;
16'h0A04: out[5:0] <= 6'b111111;
16'h0005: out[5:0] <= 6'b111111;
16'h0205: out[5:0] <= 6'b111111;
16'h0305: out[5:0] <= 6'b111111;
16'h0405: out[5:0] <= 6'b111111;
16'h0505: out[5:0] <= 6'b111111;
16'h0605: out[5:0] <= 6'b111111;
16'h0705: out[5:0] <= 6'b111111;
16'h0805: out[5:0] <= 6'b111111;
16'h0A05: out[5:0] <= 6'b111111;
16'h0006: out[5:0] <= 6'b111111;
16'h0206: out[5:0] <= 6'b111111;
16'h0806: out[5:0] <= 6'b111111;
16'h0A06: out[5:0] <= 6'b111111;
16'h0307: out[5:0] <= 6'b111111;
16'h0407: out[5:0] <= 6'b111111;
16'h0607: out[5:0] <= 6'b111111;
16'h0707: out[5:0] <= 6'b111111;
default: out[6] <= 1'b0;
endcase
end
endmodule
| 6.565971 |
module target_graphic (
x,
y,
flush_x,
flush_y,
colour,
enable
);
input [7:0] x;
input [7:0] y;
input [7:0] flush_x;
input [7:0] flush_y;
output [5:0] colour;
output enable;
wire [6:0] lut_out;
target_graphic_lut(
flush_x - x, flush_y - y, lut_out
);
assign colour = lut_out[5:0];
assign enable = lut_out[6];
endmodule
| 6.565971 |
module target_ppn_generate_unit (
input [ 1:0] count,
input [49:0] pte_addr,
input [27:0] r_req_addr,
output [37:0] resp_ppn
);
assign resp_ppn = count >= 2 ? pte_addr[49:12] : ((count & 2'h1) >= 2'h1 ? {pte_addr[49:21], r_req_addr[8:0]} : {pte_addr[49:30], r_req_addr[17:0]});
endmodule
| 6.756571 |
module target_selector (
target_number,
encode_selector
);
input [3:0] target_number; //change to 32 bit
output [3:0] encode_selector;
assign encode_selector = target_number;
endmodule
| 7.085182 |
module target_sim;
// Inputs
reg clk_100Hz;
reg rst;
reg start;
reg [2:0] din;
reg shot;
// Outputs
wire [9:0] x;
wire [8:0] y;
wire [1:0] state;
wire [1:0] animation_state;
// Instantiate the Unit Under Test (UUT)
target uut (
.clk_100Hz(clk_100Hz),
.rst(rst),
.start(start),
.din(din),
.shot(shot),
.x(x),
.y(y),
.state(state),
.animation_state(animation_state)
);
initial begin
// Initialize Inputs
clk_100Hz = 1;
rst = 0;
start = 0;
din = 0;
shot = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
start = 1;
din = 3;
#5;
start = 0;
#2895;
start = 1;
din = 5;
#5;
start = 0;
#495;
shot = 1;
#5;
shot = 0;
#195;
// Try to change 'start' in state TARGET_DYING
// Should not affect the transition
start = 1;
#5;
start = 0;
#5;
start = 1;
#5;
start = 0;
#5;
start = 1;
#5;
start = 0;
#5;
start = 1;
#5;
start = 0;
#5;
start = 1;
#5;
start = 0;
#5;
end
always begin
#5;
clk_100Hz = ~clk_100Hz;
end
endmodule
| 6.844138 |
module iobs #(
parameter WIDTH = 24,
parameter MSB = WIDTH - 1,
parameter DELAY = `DELAY
) (
input clk,
input rst,
input en,
input [ 3:0] dly,
input [MSB:0] raw,
output [MSB:0] sig
);
wire [MSB:0] ddr, neg, pos;
assign ddr = dly[0] ? neg : pos;
// NOTE: This allow half-rate sampling, but at the expense of twice the
// usage of routing-resources.
IDDR2 #(
.DDR_ALIGNMENT("C0"),
.SRTYPE("SYNC")
) IOBS[MSB:0] (
.C0(clk),
.C1(~clk),
.R (rst),
.S ({WIDTH{1'b0}}),
.CE(en),
.D (raw),
.Q0(pos),
.Q1(neg) // lags by 180 degrees
);
//-------------------------------------------------------------------------
// Programmable delay that is used to phase-shift the incoming signal.
//-------------------------------------------------------------------------
shift_reg #(
.DEPTH(8),
.ABITS(3),
.DELAY(DELAY)
) SHREG[MSB:0] (
.clk(clk),
.ce (en),
.a (dly[3:1]),
.d (ddr),
.q (sig)
);
endmodule
| 7.305033 |
module dff_tb;
parameter PERIOD = 4;
reg clk, d_in;
wire d_out;
dff dff_inst1 (
.clk (clk),
.d_in (d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
d_in = 0;
@(negedge clk) d_in = 1;
repeat (20) begin
@(negedge clk) d_in = $random();
end
$finish;
end
endmodule
| 6.528672 |
module dff (
clk,
d_in,
d_out
);
input clk, d_in;
output reg d_out;
always @(posedge clk) begin
d_out <= d_in;
end
endmodule
| 6.824043 |
module circular_shifter_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, n_rst;
wire [WIDTH-1:0] out;
circular_shifter #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk (clk),
.n_rst(n_rst),
.out (out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
n_rst = 0;
repeat (2) @(negedge clk);
n_rst = 1;
repeat (30) @(negedge clk);
$finish;
end
endmodule
| 6.652056 |
module circular_shifter (
clk,
n_rst,
out
);
parameter WIDTH = 4;
input clk;
input n_rst;
output reg [WIDTH - 1 : 0] out;
always @(posedge clk, negedge n_rst)
if (!n_rst) begin
out[WIDTH-1] <= 1'b1;
out[WIDTH-2:0] <= 1'b0;
end else begin
out[WIDTH-1] <= out[0];
out <= out >> 1;
end
endmodule
| 6.652056 |
module jsn_counter_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, n_rst;
wire [WIDTH-1:0] out;
jsn_counter #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk (clk),
.n_rst(n_rst),
.out (out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
n_rst = 0;
repeat (2) @(negedge clk);
n_rst = 1;
repeat (15) @(negedge clk);
n_rst = 0;
repeat (3) @(negedge clk);
$finish;
end
endmodule
| 6.997089 |
module jsn_counter (
clk,
n_rst,
out
);
parameter WIDTH = 4;
input clk;
input n_rst;
output reg [WIDTH - 1 : 0] out;
always @(posedge clk, negedge n_rst)
if (!n_rst) begin
out <= {WIDTH{1'b0}};
end else begin
out <= out >> 1;
out[WIDTH-1] <= ~out[0];
end
endmodule
| 7.472176 |
module complex_latch_tb;
parameter PERIOD = 4;
reg clk, n_rst;
reg [3:0] data_in;
wire [3:0] jcnt_out, data_out;
complex_latch complex_latch (
.clk(clk),
.n_rst(n_rst),
.data_in(data_in),
.jcnt_out(jcnt_out),
.data_out(data_out)
);
initial begin
clk = 1'b0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
n_rst = 1'b0;
data_in = 4'b0100;
@(negedge clk) n_rst = 1'b1;
#(PERIOD * 2);
@(negedge clk) data_in = 4'b0001;
@(negedge clk) data_in = 4'b1001;
@(negedge clk) data_in = 4'b0011;
@(negedge clk) data_in = 4'b1101;
#(PERIOD * 2);
@(negedge clk) data_in = 4'b0101;
@(negedge clk) data_in = 4'b0010;
#(PERIOD * 2);
$finish;
end
endmodule
| 7.539083 |
module complex_latch (
clk,
n_rst,
data_in,
jcnt_out,
data_out
);
input clk;
input n_rst;
input [3:0] data_in;
output reg [3:0] jcnt_out;
output reg [3:0] data_out;
wire we;
assign we = (n_rst ^ (^jcnt_out ^ (^jcnt_out[2:1])));
always @(posedge clk, negedge n_rst) begin
if (!n_rst) jcnt_out <= 4'b0;
else jcnt_out <= {~jcnt_out[0], jcnt_out[3:1]};
end
always @(we, data_in, n_rst) begin
if (!n_rst) data_out <= 4'b0000;
else if (we) data_out <= data_in;
end
endmodule
| 7.539083 |
module pipeline (
clk,
n_rst,
A,
B,
C,
Q,
Q_pipe
);
parameter WIDTH = 4;
input clk;
input n_rst;
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
input [WIDTH-1:0] C;
output reg [WIDTH-1:0] Q;
output reg [WIDTH-1:0] Q_pipe;
reg [WIDTH-1:0] q_a;
reg [WIDTH-1:0] q_b;
reg [WIDTH-1:0] q_c;
reg [WIDTH-1:0] q_cc;
reg [WIDTH-1:0] q_ab;
always @(posedge clk, negedge n_rst) begin
if (!n_rst) begin
Q <= 0;
Q_pipe <= 0;
q_a <= 0;
q_b <= 0;
q_c <= 0;
q_ab <= 0;
q_cc <= 0;
end else begin
q_a <= A;
q_b <= B;
q_c <= C;
q_cc <= q_c;
q_ab <= q_a + q_b;
Q_pipe <= q_ab ^ q_cc;
Q <= (q_a + q_b) ^ q_c;
end
end
endmodule
| 7.698493 |
module dff_complex_tb;
parameter PERIOD = 4;
reg clk, rst_n, set_n, we, d_in;
wire d_out;
dff_complex dff_inst1 (
.clk(clk),
.rst_n(rst_n),
.set_n(set_n),
.we(we),
.d_in(d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
d_in = 0;
rst_n = 0;
set_n = 1;
we = 1;
@(negedge clk) rst_n = 1;
repeat (3) begin
@(negedge clk) d_in = ^$random();
end
we = 0;
repeat (2) begin
@(negedge clk) d_in = ^$random();
end
we = 1;
repeat (3) begin
@(negedge clk) d_in = ^$random();
end
rst_n = 0;
@(negedge clk) set_n = 0;
@(negedge clk) rst_n = 1;
repeat (5) @(negedge clk);
$finish;
end
endmodule
| 6.757942 |
module dff_complex (
clk,
rst_n,
set_n,
we,
d_in,
d_out
);
input clk, rst_n, set_n, we, d_in;
output reg d_out;
always @(posedge clk, negedge rst_n, negedge set_n) begin
if (!rst_n) begin
d_out <= 1'b0;
end else if (!set_n) begin
d_out <= 1'b1;
end else if (we) begin
d_out <= d_in;
end
end
endmodule
| 7.279003 |
module dff_complex_tb;
parameter PERIOD = 4;
reg clk, rst_n, set_n, we, d_in;
wire d_out;
dff_complex dff_inst1 (
.clk(clk),
.rst_n(rst_n),
.set_n(set_n),
.we(we),
.d_in(d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
d_in = 0;
rst_n = 0;
set_n = 1;
we = 1;
@(negedge clk) rst_n = 1;
repeat (3) begin
@(negedge clk) d_in = ^$random();
end
we = 0;
repeat (2) begin
@(negedge clk) d_in = ^$random();
end
we = 1;
repeat (3) begin
@(negedge clk) d_in = ^$random();
end
rst_n = 0;
@(negedge clk) set_n = 0;
@(negedge clk) rst_n = 1;
repeat (5) @(negedge clk);
$finish;
end
endmodule
| 6.757942 |
module dff_complex (
clk,
rst_n,
set_n,
we,
d_in,
d_out
);
input clk, rst_n, set_n, we, d_in;
output reg d_out;
always @(posedge clk, negedge rst_n, negedge set_n) begin
if (!rst_n) begin
d_out <= 1'b0;
end else if (!set_n) begin
d_out <= 1'b1;
end else if (we) begin
d_out <= d_in;
end
end
//synopsys translate_off
always @(rst_n, set_n) begin
if (rst_n && !set_n) begin
force d_out = 1'b1;
end else begin
release d_out;
end
end
//synopsys translate_on
endmodule
| 7.279003 |
module reg_8bit (
clk,
rst_n,
data_in,
data_out
);
input clk, rst_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <= data_in;
end
end
endmodule
| 7.417492 |
module reg_8bit_we (
clk,
rst_n,
data_in,
data_out,
we_n
);
input clk, rst_n, we_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else if (!we_n) begin
data_out <= data_in;
end
end
endmodule
| 7.706799 |
module param_shift_reg (
clk,
rst_n,
data_in,
data_out
);
parameter WIDTH = 8;
input clk, rst_n;
input data_in; //serial loading
output reg [WIDTH - 1 : 0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <= {data_out[WIDTH-2 : 0], data_in};
end
end
endmodule
| 8.752063 |
module param_shift_direct_parallel_reg_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, rst_n, we_n, direction;
reg [WIDTH - 1:0] par_in;
wire [ WIDTH-1:0] data_out;
param_shift_direct_parallel_reg #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk(clk),
.rst_n(rst_n),
.we_n(we_n),
.direction(direction),
.data_out(data_out),
.par_in(par_in)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
par_in = 0;
rst_n = 0;
we_n = 1;
direction = 0;
repeat (2) @(negedge clk);
rst_n = 1;
we_n = 0;
par_in = 4'b1;
@(negedge clk);
we_n = 1;
direction = 1;
repeat (3) @(negedge clk);
direction = 0;
repeat (5) @(negedge clk);
repeat (2) @(negedge clk);
rst_n = 1;
we_n = 0;
par_in = 4'b1111;
@(negedge clk);
we_n = 1;
direction = 1;
repeat (6) @(negedge clk);
$finish;
end
endmodule
| 8.50231 |
module param_shift_direct_parallel_reg (
par_in,
direction,
clk,
rst_n,
we_n,
data_out
);
parameter WIDTH = 4;
input clk, rst_n, we_n, direction;
input [WIDTH - 1:0] par_in;
output reg [WIDTH - 1 : 0] data_out;
always @(posedge clk, negedge rst_n)
if (!rst_n) data_out <= 0;
else if (!we_n) begin
data_out <= par_in;
end else if (direction) begin
data_out <= data_out << 1;
end else if (!direction) begin
data_out <= data_out >> 1;
end
endmodule
| 8.50231 |
module cyc_shift (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 4'b1000;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= tmp[0];
end
end
assign out = tmp;
endmodule
| 7.780546 |
module cyc_shift_tb;
parameter period = 4;
parameter width = 4;
reg clk, rst_n;
wire [width-1:0] out;
cyc_shift #(
.width(width)
) inst1 (
.clk (clk),
.rst_n(rst_n),
.out (out)
);
initial begin
clk = 0;
forever #(period / 2) clk = ~clk;
end
initial begin
rst_n = 0;
@(negedge clk);
@(negedge clk) rst_n = 1;
repeat (13) @(posedge clk);
$finish;
end
endmodule
| 7.044076 |
module johnson (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 0;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= ~tmp[0];
end
end
assign out = tmp;
endmodule
| 8.187334 |
module johnson_tb;
parameter period = 4;
parameter width = 4;
reg clk, rst_n;
wire [width-1:0] out;
johnson #(
.width(width)
) inst1 (
.clk (clk),
.rst_n(rst_n),
.out (out)
);
initial begin
clk = 0;
forever #(period / 2) clk = ~clk;
end
initial begin
rst_n = 0;
@(negedge clk);
@(negedge clk) rst_n = 1;
repeat (13) @(posedge clk);
$finish;
end
endmodule
| 7.153325 |
module jcnt (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 0;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= ~tmp[0];
end
end
assign out = tmp;
endmodule
| 7.886297 |
module complex_latch (
rst_n,
data_in,
jcnt_in,
data_out
);
parameter width = 4;
input rst_n;
input [width-1:0] data_in;
input [width-1:0] jcnt_in;
output reg [width-1:0] data_out;
always @(rst_n, data_in, jcnt_in) begin
if (!rst_n) begin
data_out <= 0;
end else begin
if (~((jcnt_in[3] ^ jcnt_in[2]) | (jcnt_in[2] ^ jcnt_in[1]) | (jcnt_in[1] ^ jcnt_in[0])))
data_out <= data_in;
end
end
endmodule
| 7.539083 |
module dev1 (
i_clk,
i_rst_n,
i_A,
i_B,
i_C,
o_Q
);
parameter width = 4;
input i_clk, i_rst_n;
input [width-1:0] i_A, i_B, i_C;
output reg [width-1:0] o_Q;
reg [width-1:0] A_t, B_t, C_t;
always @(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
o_Q <= 0;
A_t <= 0;
B_t <= 0;
C_t <= 0;
end else begin
A_t <= i_A;
B_t <= i_B;
C_t <= i_C;
o_Q <= (A_t + B_t) ^ C_t;
end
end
endmodule
| 7.077559 |
module dev2 (
i_clk,
i_rst_n,
i_A,
i_B,
i_C,
o_Q_pipe
);
parameter width = 4;
input i_clk, i_rst_n;
input [width-1:0] i_A, i_B, i_C;
output reg [width-1:0] o_Q_pipe;
reg [width-1:0] A_t, B_t, C_t;
reg [width-1:0] AB_sum_st2, C_st2;
always @(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
o_Q_pipe <= 0;
A_t <= 0;
B_t <= 0;
C_t <= 0;
AB_sum_st2 <= 0;
C_st2 <= 0;
end else begin
A_t <= i_A;
B_t <= i_B;
C_t <= i_C;
AB_sum_st2 <= A_t + B_t;
C_st2 <= C_t;
o_Q_pipe <= AB_sum_st2 ^ C_st2;
end
end
endmodule
| 7.517024 |
modules reg_8bit_we_mod and reg_8bit_we_mod_tb
Last one is the test bench of first module*/
`timescale 1 ns / 1 ps
module reg_8bit_we_mod(clk, rst_n, we_n, data_in, data_out);
input clk, rst_n, we_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 0;
end else begin
if(!we_n) begin
data_out <= data_in;
end else begin
data_out <= data_out;
end
end
end
endmodule
| 7.858398 |
module paral_shift (
clk,
rst_n,
dir,
par_seq,
data_in,
data_parallel_load,
data_out
);
parameter WIDTH = 8;
input clk, rst_n;
input dir, par_seq, data_in;
input [WIDTH-1:0] data_parallel_load;
output reg [WIDTH-1:0] data_out;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
if (par_seq) data_out <= data_parallel_load;
else begin
if (dir) data_out <= {data_out[WIDTH-2:0], data_in};
else data_out <= {1'b0, data_out[WIDTH-1:1]};
end
end
end
endmodule
| 8.344387 |
module paral_shift_tb;
parameter period = 4;
reg clk, rst_n, dir, data_in, par_seq;
reg [7:0] data_parallel_load;
wire [7:0] data_out;
paral_shift inst1 (
.clk(clk),
.rst_n(rst_n),
.dir(dir),
.par_seq(par_seq),
.data_in(data_in),
.data_parallel_load(data_parallel_load),
.data_out(data_out)
);
initial begin
clk = 0;
forever #(period / 2) clk = ~clk;
end
initial begin
dir = 0;
par_seq = 0;
data_parallel_load = 0;
rst_n = 0;
data_in = 0;
@(negedge clk) rst_n = 1;
par_seq = 1;
data_parallel_load = 8'b01111111;
@(negedge clk) par_seq = 0;
dir = 0;
repeat (5) @(negedge clk);
dir = 1;
repeat (3) @(negedge clk);
data_in = 1'b1;
repeat (3) @(negedge clk);
dir = 0;
@(negedge clk);
$finish;
end
endmodule
| 7.423766 |
module bitwise_nor (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NOR
nor nor_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.325548 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(i_carry),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
else if (i == (WIDTH - 1))
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(o_carry)
);
else
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 9.041993 |
module decoder (
i_data,
o_data
);
parameter WIDTH = 2;
input [WIDTH-1:0] i_data;
output [2**WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin : DC
assign o_data[i] = (i_data == i) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
| 7.018254 |
module mux4 (
i_sel,
i_d0,
i_d1,
i_d2,
i_d3,
o_data
);
parameter WIDTH = 4;
input [1:0] i_sel;
input [WIDTH-1:0] i_d0, i_d1, i_d2, i_d3;
output [WIDTH-1:0] o_data;
wire [3:0] one_hot;
genvar i;
decoder #(
.WIDTH(2)
) decoder_inst (
.i_data(i_sel),
.o_data(one_hot)
);
generate
for (i = 0; i < WIDTH; i = i + 1) begin : MUX
assign o_data[i] = ((one_hot[0] & i_d0[i])|
(one_hot[1] & i_d1[i])|
(one_hot[2] & i_d2[i])|
(one_hot[3] & i_d3[i])
);
end
endgenerate
endmodule
| 7.382717 |
module bitwise_nand (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NAND
nand nand_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.116582 |
module bitwise_nor (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NOR
nor nor_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.325548 |
module ALU_gate (
i_var1,
i_var2,
i_sel,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
input [2:0] i_sel;
output [2*WIDTH-1:0] o_res;
wire [WIDTH-1:0] sum, nor_res, nand_res;
wire [2*WIDTH-1:0] mult;
wire carry, borr;
wire [WIDTH-1:0] adder;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : SUB_OR_ADD
assign adder[i] = (((~i_var2[i]) & i_sel[2]) | (i_var2[i] & (~i_sel[2])));
end
endgenerate
adder_4bit #(
.WIDTH(WIDTH)
) adder_4bit_inst (
.i_a (i_var1),
.i_b (adder),
.i_carry(i_sel[2]),
.o_sum (sum),
.o_carry(carry)
);
/*subtractor #( .WIDTH ( WIDTH ) ) subtractor_inst( .i_a ( i_var1 ),
.i_b ( i_var2 ),
.i_borr ( 1'b1 ),
.o_sub ( sub ),
.o_borr ( borr )
);
*/
multiplier #(
.WIDTH(WIDTH)
) multiplier_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.o_mult(mult)
);
bitwise_nand #(
.WIDTH(WIDTH)
) bitwise_nand_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.o_res (nand_res)
);
bitwise_nor #(
.WIDTH(WIDTH)
) bitwise_nnor_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.o_res (nor_res)
);
mux4 #(
.WIDTH(2 * WIDTH)
) mux4_inst (
.i_sel (i_sel[1:0]),
.i_d0 ({WIDTH * {1'b0}, sum}),
.i_d1 (mult),
.i_d2 ({WIDTH * {1'b0}, nand_res}),
.i_d3 ({WIDTH * {1'b0}, nor_res}),
.o_data(o_res)
);
endmodule
| 8.473477 |
module ALU_behavior (
i_var1,
i_var2,
i_sel,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
input [2:0] i_sel;
output reg [2*WIDTH-1:0] o_res;
reg [2*WIDTH-1:0] res;
reg [WIDTH-1:0] sum, sub, nand_res, nor_res;
reg [2*WIDTH-1:0] mult;
always @* begin
sum = i_var1 + i_var2;
sub = i_var1 - i_var2;
mult = i_var1 * i_var2;
nand_res = ~(i_var1 & i_var2);
nor_res = ~(i_var1 | i_var2);
case (i_sel)
0: o_res = {WIDTH * {1'b0}, sum};
1: o_res = mult;
2: o_res = {WIDTH * {1'b0}, nand_res};
3: o_res = {WIDTH * {1'b0}, nor_res};
4: o_res = {WIDTH * {1'b0}, sub};
default: o_res = 0;
endcase
end
endmodule
| 9.07293 |
module ALU_tb ();
parameter WIDTH = 4;
wire [2*WIDTH-1:0] o_res_b, o_res_g;
reg [WIDTH-1:0] i_var1, i_var2;
reg [2:0] i_sel;
integer i, j, k;
integer error_count;
event stop;
ALU_behavior #(
.WIDTH(WIDTH)
) ALU_behavior_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.i_sel (i_sel),
.o_res (o_res_b)
);
ALU_gate #(
.WIDTH(WIDTH)
) ALU_gate_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.i_sel (i_sel),
.o_res (o_res_g)
);
initial begin
i_var1 = 0;
i_var2 = 0;
i_sel = 0;
for (i = 0; i < 5; i = i + 1)
for (j = 0; j < 2 ** WIDTH; j = j + 1)
for (k = 0; k < 2 ** WIDTH; k = k + 1) begin
#10 i_var1 = k;
i_var2 = j;
i_sel = i;
end
#15->stop;
end
initial begin
#5 error_count = 0;
forever begin
#10
if (o_res_b !== o_res_g) begin
$display("ERROR!!! o_res_b = %d, o_res_g = %d", o_res_b, o_res_g);
$display("i_var1 = %d\n,i_var2 = %d\n, i_sel = %d", i_var1, i_var2, i_sel);
error_count = error_count + 1;
end
end
end
initial begin
@(stop)
if (error_count === 0) $display("SUCCESS, error_count = %d", error_count);
else $display("ERROR!!!, error_count =%d", error_count);
$finish();
end
endmodule
| 7.60053 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(i_carry),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
else if (i == (WIDTH - 1))
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(o_carry)
);
else
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 9.041993 |
module add_sub (
i_var1,
i_var2,
o_res,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
output o_carry;
wire [WIDTH-1:0] adder;
wire carry_in;
`ifdef SUB
assign adder = ~i_var2;
assign carry_in = 1'b1;
`else
assign adder = i_var2;
assign carry_in = 1'b0;
`endif
adder_4bit #(
.WIDTH(WIDTH)
) adder_4bit_inst (
.i_a (i_var1),
.i_b (adder),
.i_carry(carry_in),
.o_sum (o_res),
.o_carry(o_carry)
);
endmodule
| 7.314322 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(i_carry),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
else if (i == (WIDTH - 1))
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(o_carry)
);
else
full_adder full_adder (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_carry(carry[i-1]),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 9.041993 |
module add_sub (
i_var1,
i_var2,
o_res,
o_carry
);
parameter MODE = 1;
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
output o_carry;
wire [WIDTH-1:0] adder;
wire carry_in;
generate
if (MODE) begin
assign adder = i_var2;
assign carry_in = 1'b0;
end else begin
assign adder = ~i_var2;
assign carry_in = 1'b1;
end
endgenerate
adder_4bit #(
.WIDTH(WIDTH)
) adder_4bit_inst (
.i_a (i_var1),
.i_b (adder),
.i_carry(carry_in),
.o_sum (o_res),
.o_carry(o_carry)
);
endmodule
| 7.314322 |
module task1_module (
clk,
rst_n,
a,
b,
i1_o,
i2_o
);
input clk;
input rst_n;
input [7:0] a;
input [7:0] b;
output [8:0] i1_o;
output [8:0] i2_o;
/***********************/
reg [8:0] rData1;
reg [8:0] rData2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rData1 <= 9'd0;
rData2 <= 9'd0;
end else begin
rData1 <= {a[7], a} + {b[7], b};
rData2 <= {a[7], a} + {~b[7], (~b + 1'b1)};
end
end
assign i1_o = rData1;
assign i2_o = rData2;
endmodule
| 6.583957 |
module vga_display_sim ();
reg clk, rst_n;
wire [3:0] out_r;
wire [3:0] out_g;
wire [3:0] out_b;
wire h_sync, v_sync;
top sim (
clk,
rst_n,
out_r,
out_g,
out_b,
h_sync,
v_sync
);
initial begin
clk = 0;
rst_n = 0;
#10 rst_n = 1;
end
always #5 clk = ~clk;
endmodule
| 6.776332 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module bitwise_nor (
i_op1,
i_op2,
o_nor
);
input [3:0] i_op1, i_op2;
output [3:0] o_nor;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : not_or
nor n (o_nor[i], i_op1[i], i_op2[i]);
end //nor
endgenerate
endmodule
| 7.325548 |
module subtractor_without_borrow_in (
i_op1,
i_op2,
o_subtract,
o_borrow_out
);
input [3:0] i_op1, i_op2;
output [3:0] o_subtract;
output o_borrow_out;
wire [3:0] borrow;
assign o_borrow_out = borrow[3];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : adder_iteration
if (i == 0)
half_subtractor cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.o_subtract(o_subtract[i]),
.o_borrow(borrow[i])
);
else
full_subtractor cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_borrow_in(borrow[i-1]),
.o_subtract(o_subtract[i]),
.o_borrow(borrow[i])
);
end
endgenerate
endmodule
| 7.030396 |
module behavioral_alu (
i_op1,
i_op2,
i_ctrl,
o_data
);
input [3:0] i_op1, i_op2;
input [2:0] i_ctrl;
output reg [7:0] o_data;
always @* begin
case (i_ctrl)
0: o_data <= i_op1 + i_op2;
1: o_data <= i_op1 - i_op2;
2: o_data <= i_op1 * i_op2;
3: o_data <= ~(i_op1 & i_op2);
4: o_data <= ~(i_op1 | i_op2);
default: o_data <= 0;
endcase // i_ctrl
end
endmodule
| 9.669933 |
module adder_or_subtractor (
i_op1,
i_op2,
i_carry_borrow_in,
o_res,
o_carry_borrow_out
);
input [3:0] i_op1, i_op2;
input i_carry_borrow_in;
output [3:0] o_res;
output o_carry_borrow_out;
`ifdef ADD
four_bit_adder adder (
.i_op1(i_op1),
.i_op2(i_op2),
.i_carry_in(i_carry_borrow_in),
.o_sum(o_res),
.o_carry_out(o_carry_borrow_out)
);
`else
`ifdef SUB
four_bit_subtractor subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.i_borrow_in(i_carry_borrow_in),
.o_subtract(o_res),
.o_borrow_out(o_carry_borrow_out)
);
`else
initial begin
$display("There are no defined macros");
$finish;
end
`endif
`endif
endmodule
| 6.716334 |
module adder_or_subtractor (
i_op1,
i_op2,
i_carry_borrow_in,
o_res,
o_carry_borrow_out
);
parameter mode = 1;
input [3:0] i_op1, i_op2;
input i_carry_borrow_in;
output [3:0] o_res;
output o_carry_borrow_out;
generate
if (mode == 1)
four_bit_adder adder (
.i_op1(i_op1),
.i_op2(i_op2),
.i_carry_in(i_carry_borrow_in),
.o_sum(o_res),
.o_carry_out(o_carry_borrow_out)
);
else if (mode == 0)
four_bit_subtractor subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.i_borrow_in(i_carry_borrow_in),
.o_subtract(o_res),
.o_borrow_out(o_carry_borrow_out)
);
else begin
initial begin
$display("There are no defined macros");
$finish;
end
end
endgenerate
endmodule
| 6.716334 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module param_adder (
i_op1,
i_op2,
i_carry_in,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
input i_carry_in;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : adder_iteration
if (i == 0)
full_adder cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_carry_prev(i_carry_in),
.o_sum(o_sum[i]),
.o_carry(carry[i])
);
else
full_adder cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_carry_prev(carry[i-1]),
.o_sum(o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 8.614904 |
module adder_tb;
parameter WIDTH = 8;
reg [WIDTH-1:0] op1, op2;
reg carry_in;
wire [WIDTH-1:0] sum;
wire carry_out;
reg [ WIDTH:0] carry_concat_sum;
param_adder #(
.WIDTH(WIDTH)
) add (
.i_op1(op1),
.i_op2(op2),
.i_carry_in(carry_in),
.o_sum(sum),
.o_carry_out(carry_out)
);
integer i, j, res, error = 0;
initial begin
carry_in = 0;
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin
for (j = 0; j < 2 ** WIDTH; j = j + 1) begin
res = i + j;
op1 = i;
op2 = j;
#1;
carry_concat_sum = {carry_out, sum};
if (res !== carry_concat_sum) begin
error = error + 1;
$display(
"Error at %d: i=%d, j=%d, i+j=%d, op1=%d, op2=%d, op1+op2=%d, carry_out=%d, sum=%d",
$time, i, j, res, op1, op2, carry_concat_sum, carry_out, sum);
end // if (res!= sum)
end // for (j=0; j<16; j=j+1)
end // for (i=0; i<16; i=i+1)
carry_in = 1;
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin
for (j = 0; j < 2 ** WIDTH; j = j + 1) begin
res = i + j + carry_in;
op1 = i;
op2 = j;
#1;
carry_concat_sum = {carry_out, sum};
if (res !== carry_concat_sum) begin
error = error + 1;
$display(
"Error at %d: i=%d, j=%d, i+j=%d, op1=%d, op2=%d, op1+op2=%d, carry_out=%d, sum=%d",
$time, i, j, res, op1, op2, carry_concat_sum, carry_out, sum);
end // if (res!= sum)
end // for (j=0; j<16; j=j+1)
end // for (i=0; i<16; i=i+1)
if (error == 0) $display("!!!Test completed succesfully");
else $display("Error counter: %d", error);
end // initial
endmodule
| 7.121349 |
module adder_without_carry_in (
i_op1,
i_op2,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : adder_iteration
if (i == 0)
half_adder cl (
.i_op1 (i_op1[i]),
.i_op2 (i_op2[i]),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
else
full_adder cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_carry_prev(carry[i-1]),
.o_sum(o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 8.878618 |
module subtractor_without_borrow_in (
i_op1,
i_op2,
o_subtract,
o_borrow_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_subtract;
output o_borrow_out;
wire [WIDTH-1:0] borrow;
assign o_borrow_out = borrow[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : subtractor_iteration
if (i == 0)
half_subtractor cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.o_subtract(o_subtract[i]),
.o_borrow(borrow[i])
);
else
full_subtractor cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_borrow_in(borrow[i-1]),
.o_subtract(o_subtract[i]),
.o_borrow(borrow[i])
);
end
endgenerate
endmodule
| 7.030396 |
module behavioral_alu (
i_op1,
i_op2,
i_ctrl,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
input [2:0] i_ctrl;
output reg [2*WIDTH-1:0] o_data;
always @* begin
case (i_ctrl)
0: o_data <= i_op1 + i_op2;
1: o_data <= i_op1 - i_op2;
2: o_data <= i_op1 * i_op2;
3: o_data <= ~(i_op1 & i_op2);
4: o_data <= ~(i_op1 | i_op2);
default: o_data <= 0;
endcase // i_ctrl
end
endmodule
| 9.669933 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module stage (
i_prev_stage,
i_op,
i_bit,
i_carry,
o_carry,
o_result
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_prev_stage;
input [WIDTH-1:0] i_op;
input i_bit, i_carry;
output [WIDTH-1:0] o_result;
output o_carry;
wire [WIDTH-1:0] carry_bit;
wire [WIDTH-1:0] o_and;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : component_iterarion
if (i == 0) begin
and (o_and[i], i_op[i], i_bit);
half_adder ha (
.i_op1 (o_and[i]),
.i_op2 (i_prev_stage[i]),
.o_sum (o_result[i]),
.o_carry(carry_bit[i])
);
end //(i==0)
else begin
if (i == WIDTH - 1) begin
and (o_and[i], i_op[i], i_bit);
full_adder fa (
.i_op1(o_and[i]),
.i_op2(i_carry),
.i_carry_prev(carry_bit[i-1]),
.o_sum(o_result[i]),
.o_carry(o_carry)
);
end //(i==WIDTH-1)
else begin
and (o_and[i], i_op[i], i_bit);
full_adder fa (
.i_op1(o_and[i]),
.i_op2(i_prev_stage[i]),
.i_carry_prev(carry_bit[i-1]),
.o_sum(o_result[i]),
.o_carry(carry_bit[i])
);
end //(i!=WIDTH-1)
end //(i!=0)
end //component_iteration
endgenerate
endmodule
| 8.328539 |
module bitwise_nand (
i_op1,
i_op2,
o_nand
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_nand;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : not_and
nand n (o_nand[i], i_op1[i], i_op2[i]);
end //nand
endgenerate
endmodule
| 7.116582 |
module bitwise_nor (
i_op1,
i_op2,
o_nor
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_nor;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : not_or
nor n (o_nor[i], i_op1[i], i_op2[i]);
end //nor
endgenerate
endmodule
| 7.325548 |
module half_subtractor (
i_op1,
i_op2,
o_subtract,
o_borrow
);
input i_op1, i_op2;
output o_subtract, o_borrow;
xor (o_subtract, i_op1, i_op2);
and (o_borrow, ~i_op1, i_op2);
endmodule
| 6.878143 |
module full_subtractor (
i_op1,
i_op2,
i_borrow_in,
o_subtract,
o_borrow
);
input i_op1, i_op2, i_borrow_in;
output o_subtract, o_borrow;
wire sub1, bor1, bor2;
or or1 (o_borrow, bor1, bor2);
half_subtractor first_half_subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.o_subtract(sub1),
.o_borrow(bor1)
);
half_subtractor second_half_subtractor (
.i_op1(sub1),
.i_op2(i_borrow_in),
.o_subtract(o_subtract),
.o_borrow(bor2)
);
endmodule
| 8.333169 |
module half_subtractor (
i_op1,
i_op2,
o_subtract,
o_borrow
);
input i_op1, i_op2;
output o_subtract, o_borrow;
xor (o_subtract, i_op1, i_op2);
and (o_borrow, ~i_op1, i_op2);
endmodule
| 6.878143 |
module full_subtractor (
i_op1,
i_op2,
i_borrow_in,
o_subtract,
o_borrow
);
input i_op1, i_op2, i_borrow_in;
output o_subtract, o_borrow;
wire sub1, bor1, bor2;
or or1 (o_borrow, bor1, bor2);
half_subtractor first_half_subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.o_subtract(sub1),
.o_borrow(bor1)
);
half_subtractor second_half_subtractor (
.i_op1(sub1),
.i_op2(i_borrow_in),
.o_subtract(o_subtract),
.o_borrow(bor2)
);
endmodule
| 8.333169 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module adder_without_carry_in (
i_op1,
i_op2,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : adder_iteration
if (i == 0)
half_adder cl (
.i_op1 (i_op1[i]),
.i_op2 (i_op2[i]),
.o_sum (o_sum[i]),
.o_carry(carry[i])
);
else
full_adder cl (
.i_op1(i_op1[i]),
.i_op2(i_op2[i]),
.i_carry_prev(carry[i-1]),
.o_sum(o_sum[i]),
.o_carry(carry[i])
);
end
endgenerate
endmodule
| 8.878618 |
module four_in_and (
o_out,
i_in0,
i_in1,
i_in2,
i_in3
);
output o_out;
input i_in0, i_in1, i_in2, i_in3;
wire c1, c2;
and (c1, i_in0, i_in1);
and (c2, i_in3, i_in2);
and (o_out, c1, c2);
endmodule
| 7.065281 |
module five_in_or (
o_out,
i_in
);
output o_out;
input [4:0] i_in;
wire c1, c2, c3;
or (c1, i_in[0], i_in[1]);
or (c2, i_in[2], i_in[3]);
or (c3, c1, c2);
or (o_out, i_in[4], c3);
endmodule
| 7.252666 |
module one_bit_mux (
i_in0,
i_in1,
i_in2,
i_in3,
i_in4,
i_ctrl,
o_out
);
input i_in0, i_in1, i_in2, i_in3, i_in4;
input [2:0] i_ctrl;
output o_out;
wire [4:0] select;
wire [2:0] not_ctrl;
not n1 (not_ctrl[0], i_ctrl[0]);
not n2 (not_ctrl[1], i_ctrl[1]);
not n3 (not_ctrl[2], i_ctrl[2]);
four_in_and and1 (
select[0],
i_in0,
not_ctrl[0],
not_ctrl[1],
not_ctrl[2]
);
four_in_and and2 (
select[1],
i_in1,
i_ctrl[0],
not_ctrl[1],
not_ctrl[2]
);
four_in_and and3 (
select[2],
i_in2,
not_ctrl[0],
i_ctrl[1],
not_ctrl[2]
);
four_in_and and4 (
select[3],
i_in3,
i_ctrl[0],
i_ctrl[1],
not_ctrl[2]
);
four_in_and and5 (
select[4],
i_in4,
not_ctrl[0],
not_ctrl[1],
i_ctrl[2]
);
five_in_or or1 (
o_out,
select
);
endmodule
| 6.639519 |
module mux (
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
i_ctrl,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_data0, i_data1, i_data2, i_data3, i_data4;
input [2:0] i_ctrl;
output [WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : mux
one_bit_mux stage (
.i_in0 (i_data0[i]),
.i_in1 (i_data1[i]),
.i_in2 (i_data2[i]),
.i_in3 (i_data3[i]),
.i_in4 (i_data4[i]),
.i_ctrl(i_ctrl),
.o_out (o_data[i])
);
end //mux
endgenerate
endmodule
| 7.052968 |
module bitwise_nand (
i_op1,
i_op2,
o_nand
);
input [3:0] i_op1, i_op2;
output [3:0] o_nand;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : not_and
nand n (o_nand[i], i_op1[i], i_op2[i]);
end //nand
endgenerate
endmodule
| 7.116582 |
module task2a (
input wire clk,
output wire uart_tx
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
reg [7:0] send_data = 42; //Data value to send
wire uart_busy;
// Instanciate Baud Clock Generator
baud_clk_generator bclk (
clk,
bclk_en,
baud_clk
);
// Instanciate UART
uart_tx_8n1 uart (
baud_clk,
send_enable,
send_data,
uart_busy,
uart_tx
);
endmodule
| 7.272731 |
module task2b_continuous (
input wire clk,
output wire uart_tx,
input wire switch1,
input wire switch2,
input wire switch3,
input wire switch4
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
// Data contains the current state of the switches
wire [7:0] send_data = {4'b0000, !switch1, !switch2, !switch3, !switch4};
wire uart_busy;
// Instanciate Baud Clock Generator
baud_clk_generator bclk (
clk,
bclk_en,
baud_clk
);
// Instanciate UART
uart_tx_8n1 uart (
baud_clk,
send_enable,
send_data,
uart_busy,
uart_tx
);
endmodule
| 8.64224 |
module task2b_onlywhenchanged (
input wire clk,
output wire uart_tx,
input wire switch1,
input wire switch2,
input wire switch3,
input wire switch4
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
// Data contains the current state of the switches
wire [7:0] switch_data = {4'b0000, !switch1, !switch2, !switch3, !switch4};
reg [7:0] send_data = 0;
wire uart_busy;
// Instanciate Baud Clock Generator
baud_clk_generator bclk (
clk,
bclk_en,
baud_clk
);
// Instanciate UART
uart_tx_8n1 uart (
baud_clk,
send_enable,
send_data,
uart_busy,
uart_tx
);
always @(posedge clk) begin
if (uart_busy == 0 && send_enable == 0 && (send_data != switch_data)) begin
send_data = switch_data;
send_enable = 1;
end else if (uart_busy == 1 && send_enable == 1) begin
send_enable = 0;
end
end
endmodule
| 8.379801 |
module bit1_nor (
i_a,
i_b,
o_data
);
input i_a, i_b;
output o_data;
nor (o_data, i_a, i_b);
endmodule
| 7.135021 |
module bit4_nor (
i_a,
i_b,
i_a_g,
i_b_g,
o_data,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_data, o_data_g;
bit1_nor br0 (
.i_a(i_a[0]),
.i_b(i_b[0]),
.o_data(o_data[0])
);
bit1_nor br1 (
.i_a(i_a[1]),
.i_b(i_b[1]),
.o_data(o_data[1])
);
bit1_nor br2 (
.i_a(i_a[2]),
.i_b(i_b[2]),
.o_data(o_data[2])
);
bit1_nor br3 (
.i_a(i_a[3]),
.i_b(i_b[3]),
.o_data(o_data[3])
);
assign o_data_g = ~(i_a | i_b);
endmodule
| 7.092375 |
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