code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sys_controler (
clk,
reset,
vsync,
mem_clr_finish,
mem_str_clr,
swap,
str_line_drawing,
select
);
input clk, reset, vsync, mem_clr_finish;
output reg mem_str_clr, swap, str_line_drawing, select;
always @(posedge clk or posedge reset) begin
if (reset) begin
swap <= 0;
mem_str_clr <= 0;
str_line_drawing <= 0;
select <= 0;
end else begin
if (vsync == 0) begin
swap <= ~swap;
mem_str_clr <= 1;
select <= 1;
end else if (vsync == 1 & mem_clr_finish == 0) begin
mem_str_clr <= 1;
select <= 1;
swap <= swap;
end else if (vsync == 1 & mem_clr_finish == 1) begin
select <= 0;
str_line_drawing <= 1;
mem_str_clr <= 0;
swap <= swap;
end
end
end
endmodule
| 6.600462 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 15/8/2022 Mina Hanna final version
//------------------------------------------------
// KEYWORDS: UART main controller, finite state machine, mealy FSM
//------------------------------------------------
// PURPOSE: finite state machine act as main controller for controlling the whole uart system\
//////////////////defining inputs and output port////////////////////
module SYS_Controller (
input wire [15:0] SYSCont_ALU_Out,
input wire [7:0] SYSCont_RXPdata,
input wire [7:0] SYSCont_RdData,
input wire SYSCont_ALU_Valid,
input wire SYSCont_RX_Data_Valid,
input wire SYSCont_Rf_Data_Valid,
input wire SYSCont_Busy,
input wire SYSCont_CLK,
input wire SYSCont_RST,
output wire [7:0] SYSCont_TXPdata,
output wire [7:0] SYSCont_WrData,
output wire [7:0] SYSCont_Addr,
output wire [3:0] SYSCont_ALU_Fun,
output wire SYSCont_ALU_en,
output wire SYSCont_CLK_en,
output wire SYSCont_Rd_en,
output wire SYSCont_Wr_en,
output wire SYSCont_TX_Data_Valid,
output wire SYSCont_CLK_div_en
);
wire [7:0] Recieved_Addr;
wire [7:0] Recieved_Data;
wire [2:0] Recieved_Command;
///////////////////////////////Design instantiations ///////////////////////
RX_Controller U0_RX_Controller(
.RXCont_Pdata(SYSCont_RXPdata),
.RXCont_Data_Valid(SYSCont_RX_Data_Valid),
.RXCont_CLK(SYSCont_CLK),
.RXCont_RST(SYSCont_RST),
.RXCont_Out_Data(Recieved_Data),
.RXCont_Out_Addr(Recieved_Addr),
.RXCont_Out_command(Recieved_Command)
);
TX_Controller U0_TX_Controller(
.TXCont_ALU_Out(SYSCont_ALU_Out),
.TXCont_Pdata(Recieved_Data),
.TXCont_RdData(SYSCont_RdData),
.TXCont_Addr(Recieved_Addr),
.TXCont_command(Recieved_Command),
.TXCont_ALU_valid(SYSCont_ALU_Valid),
.TXCont_RF_Valid(SYSCont_Rf_Data_Valid),
.TXCont_Busy(SYSCont_Busy),
.TXCont_CLK(SYSCont_CLK),
.TXCont_RST(SYSCont_RST),
.TXCont_Addr_Out(SYSCont_Addr),
.TXCont_TXPdata_Out(SYSCont_TXPdata),
.TXCont_RFWr_Data(SYSCont_WrData),
.TXCont_ALU_Fun(SYSCont_ALU_Fun),
.TXCont_ALU_en(SYSCont_ALU_en),
.TXCont_CLK_en(SYSCont_CLK_en),
.TXCont_Rd_en(SYSCont_Rd_en),
.TXCont_Wr_en(SYSCont_Wr_en),
.TXCont_Data_Valid(SYSCont_TX_Data_Valid),
.TXCont_CLK_Div_en(SYSCont_CLK_div_en)
);
endmodule
| 8.923686 |
module Sys_counter (
input rst,
input proc_clk,
input freeze, //include when 1Hz timer implemented
input [3:0] count_sel,
output reg [31:0] count,
input [31:0] csr_wrdata,
input [3:0] wr_sel,
input csr_wr_en,
output tick_en
);
wire [63:0] proc_count_int;
wire [63:0] instr_count_int; //include when 1Hz timer implemented
wire [63:0] real_count_int;
wire [63:0] timecmp_int;
wire [16:0] count_tick_int;
wire rd_instret;
wire rd_time;
wire rd_cycle;
wire real_tick_en;
wire [15:0] Num_tick_reg; //maximum for 43sec
//assign real_count = {Num_tick_reg[14:0],count_tick_int};
assign rd_instret = ~count_sel[3] && count_sel[2] && (~count_sel[1]);
assign rd_time = count_sel[3] && ~count_sel[2];
assign rd_cycle = ~count_sel[3] && ~count_sel[2] && (~count_sel[1]);
assign rd_counter_tick = count_sel[3] && count_sel[2] && (~count_sel[1]);
always @(posedge proc_clk) begin
if (rst) begin
count <= 32'b0;
end else if (~freeze) begin
case (count_sel)
4'b0000: count <= proc_count_int[31:0];
4'b0100: count <= instr_count_int[31:0]; //include when 1Hz timer implemented
4'b1000: count <= real_count_int[31:0];
4'b0001: count <= proc_count_int[63:32];
4'b0101: count <= instr_count_int[63:32]; //include when 1Hz timer implemented
4'b1001: count <= real_count_int[63:32];
4'b1010: count <= timecmp_int[31:0];
4'b1011: count <= timecmp_int[63:32];
4'b1100: count <= {15'b0, count_tick_int};
4'b1101: count <= {16'b0, Num_tick_reg}; //Number of tick Register
default: count <= 0;
endcase
end
end
counter_tick ct (
.out(count_tick_int), // Output of the counter
.clk(proc_clk), // clock Input
.wr_en(wr_sel[3] && (wr_sel[2]) && (~wr_sel[1]) && csr_wr_en),
.wr_en_timer(~wr_sel[0]),
.tick_en(tick_en),
.wr_data(csr_wrdata),
.rd_time(rd_counter_tick),
.Num_tick_reg(Num_tick_reg),
.reset(rst)
); // reset Input
counter_proc_clk cp1 (
.out (proc_count_int), // Output of the counter
.clk (proc_clk), // clock Input
.wr_en (~wr_sel[3] && ~wr_sel[2] && (~wr_sel[1]) && csr_wr_en),
.wr_en_h (wr_sel[0]),
.rd_cycle(rd_cycle),
.wr_data (csr_wrdata),
.reset (rst)
);
//include when 1Hz timer implemented
counter_real_clk cr1 (
.out (real_count_int), // Output of the counter
//`ifdef EXT_WALL_CLOCK
//.clk(real_clk) , // clock Input
//`else
.clk (proc_clk), // clock Input
//`endif
.wr_en (wr_sel[3] && (~wr_sel[2]) && csr_wr_en),
.real_tick_en(real_tick_en),
.wr_en_h (wr_sel[0]),
.wr_tcmp_en (wr_sel[1]),
.timecmp (timecmp_int),
.wr_data (csr_wrdata),
.rd_time (rd_time),
.reset (rst) // reset Input
);
//Pipeline flushing case to be included//
counter_instr_clk ci1 (
.out(instr_count_int), // Output of the counter
.clk(proc_clk), // clock Input
.wr_en(~wr_sel[3] && wr_sel[2] && (~wr_sel[1]) && csr_wr_en),
.wr_en_h(wr_sel[0]),
.rd_instret(rd_instret),
.wr_data(csr_wrdata),
.freeze(freeze), //if freeze is activated, the counter is stopped
.reset(rst) // reset Input
);
endmodule
| 7.74399 |
module counter_proc_clk (
out, // Output of the counter
clk, // clock Input
wr_en,
wr_en_h,
wr_data,
rd_cycle,
reset // reset Input
);
//----------Output Ports--------------
output [63:0] out;
//------------Input Ports--------------
input clk, reset, wr_en, wr_en_h, rd_cycle;
input [31:0] wr_data;
//------------Internal Variables--------
reg [63:0] out;
//-------------Code Starts Here-------
always @(posedge clk or posedge reset)
if (reset) begin
out <= 64'b0;
end else begin
if (wr_en)
if (wr_en_h) out <= {{wr_data}, {out[31:0]}};
else out <= {{out[63:32]}, {wr_data}};
else if (~rd_cycle) out <= out + 1;
end
endmodule
| 6.911442 |
module counter_real_clk (
out, // Output of the counter
clk, // clock Input
wr_en,
wr_en_h,
real_tick_en,
rd_time,
wr_data,
wr_tcmp_en,
timecmp,
reset // reset Input
);
//----------Output Ports--------------
output [63:0] out;
output [63:0] timecmp;
//------------Input Ports--------------
input clk, reset, wr_en, wr_en_h, wr_tcmp_en, rd_time;
output real_tick_en;
input [31:0] wr_data;
//------------Internal Variables--------
//`ifdef EXT_WALL_CLOCK
// reg [63:0] out;
// `else
reg [63:0] out;
reg [63:0] timecmp;
reg real_tick_en;
reg [26:0] tick_count;
//`endif
//-------------Code Starts Here-------
//`ifndef EXT_WALL_CLOCK
always @(posedge clk or posedge reset) begin
if (reset) begin
real_tick_en <= 1'b0;
end else begin
if (out >= timecmp) real_tick_en <= 1'b1;
else real_tick_en <= 1'b0;
end
end
//`endif
//`ifdef EXT_WALL_CLOCK
//always @(posedge clk or posedge reset) begin
// if(reset) begin
// out <= 64'b0;
// end
// else begin
// out <= out + 1;
// end
//end
//`else
always @(posedge clk or posedge reset) begin
if (reset) begin
out <= 64'b1;
end else begin
if (wr_en && ~wr_tcmp_en) begin
if (wr_en_h) out <= {{wr_data}, {out[31:0]}};
else out <= {{out[63:32]}, {wr_data}};
end else if (~rd_time) out <= out + 1;
end
end
//ila_0 your_instance_name (
// .clk(clk), // input wire clk
// .probe0(out), // input wire [63:0] probe0
// .probe1(timecmp), // input wire [63:0] probe1
// .probe2(tick_en) // input wire [0:0] probe2
//);
always @(posedge clk or posedge reset) begin
if (reset) begin
timecmp <= 64'hffffffffFFFFFFFF;
end else begin
if (wr_en && wr_tcmp_en) begin
if (wr_en_h) timecmp <= {{wr_data}, {timecmp[31:0]}};
else timecmp <= {{timecmp[63:32]}, {wr_data}};
end
end
end
//`endif
endmodule
| 6.760345 |
module: cpu_cpld
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sys_ctrl_task(
clk,rst_n
);
output reg clk; //ʱź
output reg rst_n; //λź
parameter PERIOD = 20; //ʱڣλns
parameter RST_ING = 1'b0; //ЧλֵĬϵ͵ƽλ
//----------------------------------------------------------------------//
//ϵͳʱźŲ
//----------------------------------------------------------------------//
initial begin
clk = 0;
forever
#(PERIOD/2) clk = ~clk;
end
//----------------------------------------------------------------------//
//ϵͳλװ
//----------------------------------------------------------------------//
task sys_reset;
input[31:0] reset_time; //λʱ룬λns
begin
rst_n = RST_ING; //λ
#reset_time; //λʱ
rst_n = ~RST_ING; //λ
end
endtask
endmodule
| 6.552299 |
module sys_i2c_fm (
i2c_sdat,
i2c_sclk
);
inout i2c_sdat;
input i2c_sclk;
wire akn;
reg akn_reg;
//Si sda en i2cc = 1, el bus a 1 o 0 segons akn. Si 0, 0.
assign i2c_sdat = (I_codec_avalon.I_controlador.i2cc_i.sda) ? akn : 0;
assign akn = akn_reg;
initial begin
akn_reg = 1;
end
task waitstart;
/*
El MF espera el senyal d'inici: i2c_sdat = 0 mentre i2c_sclk = 1
*/
fork : timeout
begin
// Timeout check
#100000 $display("%t : timeout, no START received", $time);
$finish();
disable timeout;
end
begin
// Wait on Start
@(negedge i2c_sdat);
if (i2c_sclk == 1) $display("%t : START signal received", $time);
else begin
$display("%t : Bad START signal", $time);
$finish();
end
disable timeout;
end
join
endtask
task measuresclk;
time tempsflanc[1:5], period[1:4];
real frequency;
integer i;
begin
i = 0;
repeat (5) begin
@(posedge i2c_sclk) begin
i = i + 1;
tempsflanc[i] = $realtime;
if (i > 1) period[i-1] = tempsflanc[i] - tempsflanc[i-1];
end
end
i = 1;
repeat (3) begin
//$display("Period %i = %t ", i,period[i]);
if (period[i+1] != period[i]) $display("Error! Variable Period for i2c_sclk!");
i = i + 1;
end
frequency = 1 / (period[1] * 1e-7);
$display("Measured frequency = %f KHz", frequency);
end
endtask
task listen_acknowledge;
//La funció mostreja la dada a cada flanc de pujada de i2c_sclk i compara amb el valor esperat
//Si l'input "ackno" = 1, la funció fa acknowledge de forma adecuada. Si no, no...
input ackno;
input [23:0] data_sent;
//output [7:0] received_data;
reg [23:0] received_data;
time temps[1:24];
integer i, nb;
if (ackno) begin
i = 0;
repeat (3) begin
repeat (8) begin
@(posedge i2c_sclk) temps[i] = $realtime;
received_data[23-i] = i2c_sdat;
if (received_data[23-i] === 1'bz) received_data[23-i] = 1'b1;
if (received_data[23-i] !== data_sent[23-i]) begin
$display("At %t: Transmission error, bit %d lost! Received %b, should be %b", temps[i],
i, received_data[23-i], data_sent[23-i]);
test_codec_top.error = test_codec_top.error + 1;
end else $display("At %t: received %b, ok", temps[i], received_data[23-i]);
i = i + 1;
end
//Acknowledge
@(negedge i2c_sclk) akn_reg = 0;
//Free bus after ack bit
@(negedge i2c_sclk) akn_reg = 1;
end
end else begin
i = 0;
repeat (8) begin
@(posedge i2c_sclk) temps[i] = $realtime;
received_data[23-i] = i2c_sdat;
if (received_data[23-i] === 1'bz) received_data[23-i] = 1'b1;
if (received_data[23-i] !== data_sent[23-i]) begin
$display("At %t: Transmission error, bit %d lost! Received %b, should be %b", temps[i],
i, received_data[23-i], data_sent[23-i]);
test_codec_top.error = test_codec_top.error + 1;
end else $display("At %t: received %b, ok", temps[i], received_data[23-i]);
i = i + 1;
end
$display("Failing to acknowledge at %t!", temps[i]);
//NoAcknowledge
@(negedge i2c_sclk) akn_reg = 1;
//Free bus after ack bit
@(negedge i2c_sclk) akn_reg = 1;
end
endtask
task waitend;
/*
El MF espera el senyal de fi
*/
fork : timeout
begin
// Timeout check
#100000 $display("%t : timeout, no END received", $time);
$finish();
disable timeout;
end
begin
// Wait on end
@(posedge i2c_sdat);
if (i2c_sclk == 1) $display("%t : END signal received", $time);
else begin
$display("%t : Bad END signal", $time);
$finish();
end
disable timeout;
end
join
endtask
endmodule
| 7.417626 |
module
module sys_io(
input clk,
input [7:0] io_addr,
output reg [7:0] io_dout,
input [7:0] io_din,
input io_we
);
reg [7:0] io_mem [255:0];
always @(posedge clk) begin
if (io_we)
io_mem[io_addr] <= io_din;
end
always @(*)
begin
io_dout = io_mem[io_addr];
end
endmodule
| 6.917958 |
module sys_mmcm_clk_rst_sync (
clk_i_p,
clk_i_n,
rst_n_i,
sys_rst_n_o,
clk_100m,
clk_50m,
clk_25m,
clk_10m,
clk_5m
);
parameter RST_N_HOLD_CNT = 50;
input clk_i_p;
input clk_i_n;
input rst_n_i; // low active
output sys_rst_n_o; // low active
output clk_100m;
output clk_50m;
output clk_25m;
output clk_10m;
output clk_5m;
wire rst_n_sync; // synced rst_n_i, low active
wire sys_mmcm_clk_rst; // high active
wire sys_mmcm_clk_locked;
wire sys_rst_n_o;
// reset synchronizer
// rst_n_i is asynchronous event
// When BUTTON[0] is pressed, rst_n_i is low, this enter reset mode
// When BUTTON[0] is released, rst_n_i is high, after one clk, will leave reset
// mode
rst_n_sync rst_n_sync_u0 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rst_n_o(rst_n_sync)
);
// reset signal extender
// rst_n_sync is synchronous event
// rst_n_sync is low, enter reset mode,
// Also PLL is in reset mode.
// rst_n_sync is high, after one clk, PLL will leave reset mode
// rst_n_hold will remain low during RST_N_HOLD_CNT clk periods after
// pll_locked is high
rst_n_hold #(
.RST_N_HOLD_CNT(RST_N_HOLD_CNT)
) rst_n_hold_u0 (
.clk_i(clk_i),
.rst_n_i(rst_n_sync),
.pll_locked(sys_mmcm_clk_locked),
.rst_n_hold_o(sys_rst_n_o)
);
assign sys_mmcm_clk_rst = ~rst_n_sync;
sys_mmcm_clk sys_mmcm_clk_u0 (
.clk_in1_p(clk_i_p),
.clk_in1_n(clk_i_n),
.reset(sys_mmcm_clk_rst),
.locked(sys_mmcm_clk_locked),
.clk_100m(clk_100m),
.clk_50m(clk_50m),
.clk_25m(clk_25m),
.clk_10m(clk_10m),
.clk_5m(clk_5m)
);
endmodule
| 9.517996 |
module sys_pll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("100.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("1.199882 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("1.536155 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.567661 |
module sys_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
sys_pll clknetwork ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1(clk_int[1]),
.CLK_OUT2(clk_int[2]),
.CLK_OUT3(clk_int[3]),
.CLK_OUT4(clk_int[4]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr (
.Q (CLK_OUT[clk_out_pins]),
.C0(clk[clk_out_pins]),
.C1(clk_n[clk_out_pins]),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
assign clk[4] = clk_int[4];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 6.97616 |
module sys_pll_sys_sdram_pll_0 (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire sys_clk_clk, // sys_clk.clk
output wire sdram_clk_clk, // sdram_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire sys_pll_locked_export; // sys_pll:locked -> reset_from_locked:locked
altera_up_altpll #(
.OUTCLK0_MULT (1),
.OUTCLK0_DIV (1),
.OUTCLK1_MULT (1),
.OUTCLK1_DIV (1),
.OUTCLK2_MULT (1),
.OUTCLK2_DIV (1),
.PHASE_SHIFT (-3000),
.DEVICE_FAMILY("Cyclone IV")
) sys_pll (
.refclk (ref_clk_clk), // refclk.clk
.reset (ref_reset_reset), // reset.reset
.locked (sys_pll_locked_export), // locked.export
.outclk0(sys_clk_clk), // outclk0.clk
.outclk1(sdram_clk_clk), // outclk1.clk
.outclk2() // outclk2.clk
);
altera_up_avalon_reset_from_locked_signal reset_from_locked (
.reset (reset_source_reset), // reset_source.reset
.locked(sys_pll_locked_export) // locked.export
);
endmodule
| 6.588117 |
module sys_reset (
RSTn,
CLK,
DOUT
);
input RSTn;
input CLK;
output DOUT;
reg [15:0] count;
wire count_up;
always @(negedge RSTn or posedge CLK) begin
if (~RSTn) count <= 16'h0000;
else if (count_up == 1'b0) count <= count + 1;
end
// count_up <= '1' when count=X"FFFF" else '0';
assign count_up = count[15];
assign DOUT = ~count_up;
endmodule
| 6.852544 |
module sys_reset_n #(
parameter N = 32, // debounce timer bitwidth
parameter MAX_TIME = 100, //us
parameter FREQ = 50 //model clock :Mhz
) (
input sys_clk,
input reset_n,
output sys_reset_n
);
localparam TIMER_MAX_VAL = 5000;
//------------------------------------------
// Delay
reg [N-1:0] timer_cnt;
always @(posedge sys_clk or negedge reset_n) begin
if (!reset_n) timer_cnt <= 0;
else begin
if (timer_cnt < TIMER_MAX_VAL) //100us
timer_cnt <= timer_cnt + 1'b1;
end
end
//------------------------------------------
//rst_n synchronism
reg syn_rst_n_d0;
reg syn_rst_n_d1;
always @(posedge sys_clk or negedge reset_n) begin
if (!reset_n) begin
syn_rst_n_d0 <= 0;
syn_rst_n_d1 <= 0;
end else if (timer_cnt == TIMER_MAX_VAL) begin
syn_rst_n_d0 <= 1;
syn_rst_n_d1 <= syn_rst_n_d0;
end else begin
syn_rst_n_d0 <= 0;
syn_rst_n_d1 <= 0;
end
end
assign sys_reset_n = syn_rst_n_d1;
endmodule
| 8.145894 |
module sys_rst (
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [ 5:0] cur_state;
reg [ 5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *)reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *)reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *)reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *)reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @(posedge cpu_bus_clk) begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @(posedge cpu_bus_clk or negedge cpu_bus_rst_n) begin
if (cpu_bus_rst_n == 0) cur_state <= S_RESET;
else cur_state <= next_state;
end
always @(*) begin
case (cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if (r_pcie_perst_n == 0) next_state <= S_RESET;
else if (r_rst_cnt == 0) next_state <= S_IDLE;
else next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if (r_pcie_perst_n == 0) next_state <= S_RESET;
else if (r_rst_cnt == 0) next_state <= S_HOT_RESET_WAIT;
else next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if (r_pcie_perst_n == 0) next_state <= S_RESET;
else if (r_pcie_pl_hot_rst == 1) next_state <= S_HOT_RESET_WAIT;
else next_state <= S_IDLE;
end
S_IDLE: begin
if (r_pcie_perst_n == 0) next_state <= S_RESET;
else if (r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1) next_state <= S_HOT_RESET;
else next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @(posedge cpu_bus_clk) begin
case (cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @(*) begin
case (cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule
| 7.896045 |
module sys_rst_fm (
Rst
);
output Rst; // Generated reset
reg Rst;
initial begin
Rst = 1;
end
// -----------------------------------------------------------------------------
// Task: sys.rstOn
// Asserts reset (Rst_n=0 & Rst=1)
// -----------------------------------------------------------------------------
task rstOn;
begin
Rst = 1;
end
endtask // rstOn
// -----------------------------------------------------------------------------
// Task: sys.rstOff
// Deasserts reset (Rst_n=0 & Rst=1)
// -----------------------------------------------------------------------------
task rstOff;
begin
Rst = 0;
end
endtask // rstOff
//
endmodule
| 6.698598 |
module sys_rst_n (
input clk,
input rst_n,
output reg rst_syn
);
reg rst_syn1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_syn1 <= 1'b0;
else rst_syn1 <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_syn <= 1'b0;
else rst_syn <= rst_syn1;
end
endmodule
| 7.440956 |
modules. //
// RUT will use limited SystemVerilog features which will help to develop the//
// library greatly. //
// //
// NOTE: //
// Copyright by Software Validation team from Lattice Semiconductor Corporation//
// ----------------------------------------------------------------------------//
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>> FILE DESCRIPTION <<<<<<<<<<<<<<<<<<<<<<<<<<<<<//
// ----------------------------------------------------------------------------//
// this file is used to generate system control signals like: //
// (1) clocks/clock enables (system clock, write clock and read clock) //
// (2) reset signal //
// //
// ----------------------------------------------------------------------------//
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>> VERSION CONTROL <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<//
// File Name: sys_signals.v //
// Owner: Yibin Sun //
// Version History: //
// Version Data Modifier Comments //
// V0.1 12.24.2014 Yibin initial Version //
// //
// ----------------------------------------------------------------------------//
`include "./global_param_sets.v"
module sys_signals (
output Sysclk,
output reg Sysclk_En,
output reg Wclk,
output reg Wclk_En,
output reg Rclk,
output reg Rclk_En,
output reg async_rst,
output reg sync_rst
);
/* START: system clock-Sysclk and clock enable generation */
reg Sysclk_base;
initial
begin
Sysclk_base <= 1'b1;
Sysclk_En <= 1'b0;
# `CLK_EN_ASSERTION Sysclk_En <= 1'b1;
end
always begin
# `HIGH_TIME Sysclk_base <= 0;
# `LOW_TIME Sysclk_base <= 1;
end
assign # `CLK_SHIFT_VAL Sysclk = Sysclk_base;
/* END:*/
/* START: write clock-Wclk and clock enable generation */
reg Wclk_base;
initial
begin
Wclk_base <= 1'b1;
Wclk_En <= 1'b0;
# `WCLK_EN_ASSERTION Wclk_En <= 1'b1;
end
always begin
# `WHIGH_TIME Wclk_base <= 0;
# `WLOW_TIME Wclk_base <= 1;
end
assign # `WCLK_SHIFT_VAL Wclk = Wclk_base;
/* END:*/
/* START: read clock-Rclk and clock enable generation */
reg Rclk_base;
initial
begin
Rclk_base <= 1'b1;
Rclk_En <= 1'b0;
# `RCLK_EN_ASSERTION Rclk_En <= 1'b1;
end
always begin
# `RHIGH_TIME Rclk_base <= 0;
# `RLOW_TIME Rclk_base <= 1;
end
assign # `RCLK_SHIFT_VAL Rclk = Rclk_base;
/* END:*/
/* START: Asynchronous Reset */
initial
begin
async_rst <= `ASYNC_RST_HIGH_LOW;
# `ASYNC_RST_ASSERT_LENGTH async_rst <= ~async_rst;
end
/* END:*/
/* START: Synchronous Reset */
integer cnt;
initial
begin
sync_rst <= `SYNC_RST_HIGH_LOW;
for ( cnt = 0; cnt < `SYNC_RST_ASSERT_CYCLE + 1; cnt = cnt + 1)
@( posedge Sysclk);
sync_rst <= ~sync_rst;
end
/* END:*/
// Other requiremetns
endmodule
| 7.062491 |
module sys_sig_gen (
masterClk,
masterRst,
sysclk,
nsysclk,
sdramclk,
sysRst
);
input masterClk;
input masterRst;
output sysclk;
output nsysclk;
output sdramclk;
output sysRst;
wire locked;
wire locked_Del;
reg [2:0] rstDel;
reg [2:0] rstDel2;
wire clk_nodelay;
wire clk_delay;
clkdiv div0 (
.RST_IN(masterRst),
.LOCKED_OUT(locked),
.CLKIN_IN(masterClk),
.CLKFX_OUT(clk_nodelay),
.CLK0_OUT(),
.CLKIN_IBUFG_OUT()
);
always @(posedge clk_nodelay or posedge masterRst) begin
if (masterRst) rstDel <= 3'b111;
else rstDel <= {rstDel[1:0], ~locked};
end
clkdel del0 (
.RST_IN(rstDel[2]),
.LOCKED_OUT(locked_Del),
.CLKIN_IN(clk_nodelay),
.CLK270_OUT(clk_delay),
//.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
always @(posedge clk_nodelay or posedge masterRst) begin
if (masterRst) rstDel2 <= 3'b111;
else rstDel2 <= {rstDel2[1:0], ~locked_Del};
end
assign sysRst = rstDel2[2];
assign sysclk = clk_nodelay;
assign sdramclk = clk_delay;
// *********************************************
// Infer a DDR register for sdram_clk generation
// *********************************************
OFDDRRSE ddr0 (
.CE(1'b1),
.S (1'b0),
.R (1'b0),
.C0(sysclk),
.C1(!sysclk),
.D0(1'b0),
.D1(1'b1),
.Q (nsysclk)
);
endmodule
| 6.9795 |
module SYS_TOP_TB ();
//parameters
parameter DATA_WIDTH = 8;
parameter REF_CLK_PER = 20;
parameter UART_RX_CLK_PER = 100;
parameter WR_NUM_OF_FRAMES = 3;
parameter RD_NUM_OF_FRAMES = 2;
parameter ALU_WP_NUM_OF_FRAMES = 4;
parameter ALU_NP_NUM_OF_FRAMES = 2;
//Testbench Signals
reg RST_N;
reg UART_CLK;
reg REF_CLK;
reg UART_RX_IN;
wire UART_TX_O;
reg [WR_NUM_OF_FRAMES*11-1:0] WR_CMD = 'b10_01110111_0_10_00000101_0_10_10101010_0;
reg [RD_NUM_OF_FRAMES*11-1:0] RD_CMD = 'b11_00000010_0_10_10111011_0;
reg [ALU_WP_NUM_OF_FRAMES*11-1:0] ALU_WP_CMD = 'b11_00000001_0_10_00000011_0_10_00000101_0_10_11001100_0 ;
reg [ALU_NP_NUM_OF_FRAMES*11-1:0] ALU_NP_CMD = 'b11_00000001_0_10_11011101_0;
reg TX_CLK_TB;
reg Data_Stimulus_En;
reg [5:0] count = 6'b0;
//Initial
initial begin
//initial values
UART_CLK = 1'b0;
TX_CLK_TB = 1'b0;
REF_CLK = 1'b0;
RST_N = 1'b1; // rst is deactivated
UART_RX_IN = 1'b1;
//Reset the design
#5 RST_N = 1'b0; // rst is activated
#5 RST_N = 1'b1; // rst is deactivated
#20 Data_Stimulus_En = 1'b1;
#400000 $stop;
end
always @(posedge DUT.U0_ClkDiv.o_div_clk) begin
if (Data_Stimulus_En && count < 6'd22) begin
UART_RX_IN <= RD_CMD[count];
count <= count + 6'b1;
end else UART_RX_IN <= 1'b1;
end
// REF Clock Generator
always #(REF_CLK_PER / 2) REF_CLK = ~REF_CLK;
// UART RX Clock Generator
always #(UART_RX_CLK_PER / 2) UART_CLK = ~UART_CLK;
// Design Instaniation
SYS_TOP DUT (
.UART_CLK(UART_CLK),
.REF_CLK(REF_CLK),
.RST_N(RST_N),
.UART_RX_IN(UART_RX_IN),
.UART_TX_O(UART_TX_O)
);
endmodule
| 7.60416 |
module SyzFETFlagReg (
input clockSig,
input value,
input [3:0] sel,
input write,
input reset,
output [15:0] dOut
);
reg [15:0] data = 16'h0000;
// Delay buffer
wire wBuf;
buf #(1) (wBuf, value);
// Reset on rising reset signal, set data on falling clock signal
always @(negedge clockSig) begin
if (reset) begin
data[15:0] = 16'h0000;
end else begin
if (write) begin
data[sel] = wBuf;
end
end
end
// Concatenate all data signals to one 16-bit value for output signals
assign dOut[15:0] = {
data[15],
data[14],
data[13],
data[12],
data[11],
data[10],
data[9],
data[8],
data[7],
data[6],
data[5],
data[4],
data[3],
data[2],
data[1],
data[0]
};
endmodule
| 6.528249 |
module SyzFETRegister2Out (
input [15:0] dIn,
input clockSig,
input read,
input write,
input reset,
output [15:0] dOut,
output [15:0] debugOut
);
reg [15:0] data = 16'h0000;
wire [15:0] wOutput;
wire [15:0] wBuf;
Buffer16B buf0 (
.dIn (dIn[15:0]),
.dOut(wBuf[15:0])
);
// Have a way to see the register's value
assign debugOut[15:0] = data[15:0];
// Reset on rising reset signal, set data on falling clock signal
always @(negedge clockSig) begin
if (reset) begin
data[15:0] <= 16'h0000;
end else begin
if (write) begin
data[15:0] <= wBuf[15:0];
end
end
end
// Only output if we get the read signal
assign wOutput[15:0] = (read) ? data[15:0] : 16'h0000;
// Clone the output to two standard outputs and one debug output
assign dOut[15:0] = wOutput[15:0];
endmodule
| 7.397064 |
module handles the data clock output from the ADC and provides the
// necessary signals required by the ISERDES input buffers.
//
//------------------------------------------------------------------------
// Copyright (c) 2017 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module syzygy_adc_dco (
input wire reset,
input wire adc_dco_p, // ADC Data clock
input wire adc_dco_n,
output wire clk_out_bufio,
output wire clk_out_div // 1/4 clock rate for data from SERDES
);
wire clk_out_int; // internal clock net
IBUFDS #(
.IOSTANDARD ("LVDS_25"),
.DIFF_TERM ("TRUE")
) adc_dco_ibufds (
.I (adc_dco_p),
.IB (adc_dco_n),
.O (clk_out_int)
);
BUFIO adc_dco_bufio (
.I (clk_out_int),
.O (clk_out_bufio)
);
BUFR #(
.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4")
) adc_dco_bufr (
.O (clk_out_div),
.CE (1'b1),
.CLR (reset),
.I (clk_out_int)
);
endmodule
| 7.227301 |
module for use with the SYZYGY DAC sample. Allows
// control of the AM depth.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module syzygy_dac_am(
input wire clk,
input wire reset,
input wire dis_mod,
input wire dis_out,
input wire [11:0] dds_out,
input wire [11:0] ampl,
input wire [7:0] depth,
output reg [11:0] data
);
reg [23:0] mult_out_r, mult_out_r2;
reg [19:0] div_out_r, div_out_r2;
reg [11:0] ampl_r;
reg [7:0] min_ampl_r, depth_r;
wire [19:0] min_ampl_padded;
assign min_ampl_padded = {min_ampl_r, 12'd0};
always @(posedge clk) begin
if (reset) begin
ampl_r <= 12'd0;
min_ampl_r <= 12'd0;
depth_r <= 12'd0;
mult_out_r <= 24'd0;
mult_out_r2 <= 24'd0;
div_out_r <= 20'd0;
div_out_r2 <= 20'd0;
data <= 12'd0;
end else if (dis_mod)
// Modulation disabled
data <= dds_out;
else if (dis_out)
// Output disabled
data <= 12'd0;
else begin
// Update registers
ampl_r <= ampl;
min_ampl_r <= 13'd256 - depth;
depth_r <= depth;
div_out_r <= ampl_r * depth_r;
// 2nd register for DSP pipelining
div_out_r2 <= div_out_r + min_ampl_padded;
mult_out_r <= div_out_r2[19:8] * dds_out;
// 2nd register for DSP pipelining
mult_out_r2 <= mult_out_r;
data <= mult_out_r2[23:12];
end
end
endmodule
| 6.836922 |
module for use with the SYZYGY DAC sample. Allows
// control of the FM Deviation.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module syzygy_dac_fm(
input wire clk,
input wire reset,
input wire dis,
input wire [15:0] freq_dev,
input wire [11:0] audio,
output reg [27:0] inc_delta
);
reg signed [27:0] inc_delta_r;
reg signed [15:0] freq_dev_r;
reg signed [11:0] audio_r;
localparam down_shift = 12'h7FF;
localparam shift_factor = 1'd1;
always @(posedge clk) begin
if (reset) begin
inc_delta <= 28'd0;
inc_delta_r <= 28'd0;
freq_dev_r <= 16'd0;
audio_r <= 12'd0;
end else if (dis)
// Output disabled
inc_delta <= 28'd0;
else begin
// Update buffers
freq_dev_r <= freq_dev >> shift_factor;
audio_r <= audio - down_shift;
inc_delta_r <= freq_dev_r * audio_r;
inc_delta <= inc_delta_r; // 2nd register for DSP pipelining
end
end
endmodule
| 6.836922 |
module syzygy_dac_phy (
input wire clk,
input wire reset,
input wire [11:0] data_i,
input wire [11:0] data_q,
output wire [11:0] dac_data,
output wire dac_clk
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT (1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q (dac_clk), // 1-bit DDR output
.C (clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R (1'b0), // 1-bit reset
.S (1'b0) // 1-bit set
);
wire phy_clk, locked;
reg [11:0] data_i_r, data_q_r;
always @(posedge phy_clk) begin
if (reset) begin
data_i_r <= 12'd0;
data_q_r <= 12'd0;
end else begin
data_i_r <= data_i;
data_q_r <= data_q;
end
end
clk_wiz_0 phy_pll (
// Clock out ports
.clk_out1(phy_clk),
// Status and control signals
.reset (reset),
.locked (locked),
// Clock in ports
.clk_in1 (clk)
);
selectio_wiz_0 dac_io (
.data_out_from_device({data_q_r, data_i_r}),
.data_out_to_pins (dac_data),
.clk_in (phy_clk),
.io_reset (~locked)
);
endmodule
| 6.897113 |
module syzygy_dac_tb ();
reg clk, reset;
wire [11:0] dac_data;
wire dac_clk, dac_reset_pinmd, dac_sclk, dac_sdio, dac_cs_n;
`define T_Clk 8 // 8ns clock period (125 MHz)
// clock generation
initial begin
clk = 0;
forever begin
#(`T_Clk) clk = 1'b1;
#(`T_Clk) clk = 1'b0;
end
end
// Reset
initial begin
reset = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) reset = 0;
end
syzygy_dac_top dut (
.dds_addr(),
.dds_data(32'h0),
.dds_rate(16'h1),
.dac_fsadj(16'h0),
.dac_data (dac_data),
.dac_clk (dac_clk),
.dac_reset_pinmd(dac_reset_pinmd),
.dac_sclk (dac_sclk),
.dac_sdio (dac_sdio),
.dac_cs_n (dac_cs_n),
.reset_async (reset),
.clk (clk)
);
endmodule
| 7.141031 |
module for the SYZYGY DAC Pod sample. This module
// contains the DAC DDS, PHY, and controller.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module syzygy_dac_top(
input wire clk,
input wire reset,
input wire dis_out, // Disable Output
input wire dis_am, // Disable AM
input wire dis_fm, // Disable FM
// Settings
input wire [31:0] freq,
input wire [15:0] freq_dev, // FM Frequency Deviation
input wire [11:0] ampl,
input wire [7:0] depth,
// SZG-DAC Connections
output wire [11:0] dac_data, // I data
output wire dac_clk,
output wire dac_reset_pinmd,
output wire dac_sclk, // SPI clock
inout wire dac_sdio, // SPI data I/O
output wire dac_cs_n // SPI Chip Select
);
// DAC //
// SPI
wire [5:0] spi_reg;
wire [7:0] spi_data_in, spi_data_out;
wire spi_send, spi_done, spi_rw;
// Datapath
wire [27:0] inc_delta;
wire [11:0] dac_data_i, dds_out;
wire dac_ready;
syzygy_dds_fp dds_i(
.clk (clk),
.reset (reset),
.dis_out (dis_out),
.freq (freq),
.phase (32'd0),
.inc_delta (inc_delta),
.data (dds_out)
);
syzygy_dac_am am_mod(
.clk (clk),
.reset (reset),
.dis_mod (dis_am),
.dis_out (dis_out),
.dds_out (dds_out),
.ampl (ampl),
.depth (depth),
.data (dac_data_i)
);
syzygy_dac_fm fm_mod(
.clk (clk),
.reset (reset),
.dis (dis_fm),
.freq_dev (freq_dev),
.audio (ampl),
.inc_delta (inc_delta)
);
syzygy_dac_phy dac_phy_impl(
.clk (clk),
.reset (reset),
.data_i (dac_data_i),
.data_q (dac_data_i), // Output the same data on both channels
.dac_data (dac_data),
.dac_clk (dac_clk)
);
syzygy_dac_spi dac_spi(
.clk (clk),
.reset (reset),
.dac_sclk (dac_sclk),
.dac_sdio (dac_sdio),
.dac_cs_n (dac_cs_n),
.dac_reset (dac_reset_pinmd),
.spi_reg (spi_reg), // DAC SPI register address
.spi_data_in (spi_data_in), // Data to DAC
.spi_data_out (spi_data_out), // Data from DAC (unused here)
.spi_send (spi_send), // Send command
.spi_done (spi_done), // Command is complete, data_out valid
.spi_rw (spi_rw) // Read or write
);
syzygy_dac_controller dac_control(
.clk (clk),
.reset (reset),
.dac_fsadj (16'h2020),
.spi_reg (spi_reg),
.spi_data_in (spi_data_in),
.spi_send (spi_send),
.spi_done (spi_done),
.spi_rw (spi_rw),
.dac_ready (dac_ready)
);
endmodule
| 7.878554 |
module syzygy_dds_fp (
input wire clk,
input wire reset,
input wire dis_out,
input wire [31:0] freq,
input wire [31:0] phase,
input wire [27:0] inc_delta,
output reg [11:0] data
);
// CORDIC
reg [69:0] delta;
reg [31:0] counter;
reg [31:0] freq_r, phase_r;
reg [11:0] cordic_out_shifted_up;
wire [31:0] inc_delta_signed;
wire [11:0] cordic_out;
wire data_valid;
assign inc_delta_signed = (inc_delta[27]) ? {4'hF, inc_delta} : {4'h0, inc_delta};
// Max value for CORDIC input, 1 (3 FPN)
localparam max_val = 32'h40000000;
// Value to subtract counter by before passing into CORDIC
localparam sub_val = 32'hE0000000;
// Left bitshift quantity.
localparam shift_factor = 6'd37;
// CORDIC Module
cordic_0 cordic_0_inst (
.aclk (clk),
.s_axis_phase_tdata (counter + phase_r + sub_val), // Input stream, 32-bit width
.s_axis_phase_tvalid(1'b1), // Input validity (always valid)
.m_axis_dout_tdata (cordic_out), // Output stream, 32-bits, 12-bit width
.m_axis_dout_tvalid (data_valid) // Output validity
);
always @(posedge clk) begin
if (reset) begin
delta <= 70'd0;
delta <= 70'd0;
counter <= 32'd0;
freq_r <= 32'd0;
phase_r <= 32'd0;
cordic_out_shifted_up <= 12'd0;
end else if (dis_out) data <= 12'd0;
else begin
// Update buffers
freq_r <= freq + inc_delta_signed;
phase_r <= phase;
delta <= freq_r << shift_factor;
data <= cordic_out_shifted_up;
counter <= counter + delta[65:34];
if (counter >= max_val - delta[65:34]) counter <= counter - max_val + delta[65:34];
// Shift output up by 1 (2 FPN) from CORDIC to DAC
cordic_out_shifted_up <= cordic_out + 12'h400;
end
end
endmodule
| 7.774741 |
module will read in data from a BRAM generator module and output
// a data signal for a DAC channel. The BRAM has a 32-bit data interface
// which is split into two 16-bit interfaces each truncated to 12-bits.
// This means that the usable depth of the BRAM is essentially double the
// depth setting on the BRAM.
//
//------------------------------------------------------------------------
// Copyright (c) 2017 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module syzygy_dds_mem (
input wire clk,
input wire reset,
// BRAM interface
input wire [15:0] rate,
output wire [31:0] mem_addr,
input wire [31:0] mem_data,
// DAC data stream
output wire [11:0] data
);
parameter MEM_SIZE_BITS = 12;
reg [MEM_SIZE_BITS:0] addr_counter;
assign mem_addr[31:14] = 0;
assign mem_addr[13:2] = addr_counter[MEM_SIZE_BITS:1];
assign mem_addr[1:0] = 0;
assign data = addr_counter[0] ? mem_data[27:16] : mem_data[11:0];
always @(posedge clk) begin
if (reset == 1'b1) begin
addr_counter <= 12'h0;
end else begin
addr_counter <= addr_counter + rate;
if (addr_counter[MEM_SIZE_BITS:1] == 2**MEM_SIZE_BITS - 2) begin
addr_counter <= 12'h0;
end
end
end
endmodule
| 8.488121 |
module sz (
input rst,
input clk
);
parameter TYPE = 'b00; //00:float; 01:double; 10: int; 11: float
parameter WIDTH = 32;
parameter OUT_WIDTH = 2;
//parameter ERROR = 0.0001; //absolute error
//stream data in from DRAM; having a FIFO/buffer to store
wire [WIDTH-1:0] data_in, dram_in, dram_out;
wire [OUT_WIDTH-1:0] data_out;
//stream data from the DRAM
wire [WIDTH-1:0] omit;
/*******************Out of Order Fitting*********************/
wire [31:0] data_in;
reg enable;
wire [1:0] data_out;
wire [31:0] phase3_data_out;
wire [15:0] phase2_data_out; // quant is 14 bits
wire phase2_valid;
wire phase3_valid;
sz_inner sz0 (
rst,
clk,
data_in,
enable,
data_out,
phase2_data_out,
phase2_valid,
phase3_data_out,
phase3_valid
);
//Gzip
//get the output, store in the buffer, and store into DRAM
endmodule
| 7.221755 |
module from Digilent. Implements
// an I2S master for the PMOD-I2S2 ADC.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module szg_i2s2_pmod_phy(
input wire clk, // 100.8MHz
input wire reset,
output wire mclk,
output wire lrck,
output wire sclk,
input wire sdin,
output reg [23:0] r_channel,
output reg [23:0] l_channel
);
reg [23:0] r_channel_r, l_channel_r;
reg [6:0] valid_count;
reg [10:0] count;
reg sclk_r, lrck_r;
// Every 4 clk
assign mclk = count[1];
// Every 8 * 4 clk
assign sclk = count[4];
// Every 8 * 64 clk
assign lrck = count[10];
// Upward shift constant
localparam up_shift = 24'h7FFFFF;
always @(posedge clk) begin
if (reset) begin
r_channel <= 24'd0;
l_channel <= 24'd0;
r_channel_r <= 24'd0;
l_channel_r <= 24'd0;
valid_count <= 7'd0;
count <= 11'd0;
sclk_r <= 1'b0;
lrck_r <= 1'b0;
end else begin
// Clock generation
count <= count + 1;
// Reset left/right count
if (lrck != lrck_r) valid_count <= 32'd0;
// Rising edge
if (sclk && ~sclk_r) begin
valid_count <= valid_count + 1;
if (valid_count >= 1 && valid_count <= 24) begin
// Update respective shift registers
if (lrck) begin
r_channel_r <= {r_channel_r[22:0], sdin};
// Shift upwards for DAC
l_channel <= l_channel_r + up_shift;
end else begin
l_channel_r <= {l_channel_r[22:0], sdin};
// Shift upwards for DAC
r_channel <= r_channel_r + up_shift;
end
end
end
// Update last states
sclk_r <= sclk;
lrck_r <= lrck;
end
end
endmodule
| 7.306128 |
module for the PMOD-I2S2 PHY from Digilent. Outputs mono audio
// data.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//------------------------------------------------------------------------
`default_nettype none
module szg_i2s2_pmod_top(
input wire clk,
input wire reset,
// FrontPanel
input wire volume,
// PHY
output wire rx_mclk,
output wire rx_lrck,
output wire rx_sclk,
input wire rx_sdin,
output reg [23:0] data
);
// I2S2 PHY
wire [23:0] r_channel, l_channel;
szg_i2s2_pmod_phy szg_i2s2_phy(
.clk (clk),
.reset (reset),
.mclk (rx_mclk),
.lrck (rx_lrck),
.sclk (rx_sclk),
.sdin (rx_sdin),
.r_channel (r_channel),
.l_channel (l_channel)
);
always @(posedge clk)
data <= (r_channel + l_channel) / 2;
endmodule
| 8.012345 |
module szznew (
LED_Hr,
LED_Min,
LED_Sec,
ALARM,
_1kHzIN,
Adj_Min_key,
Adj_Hour_key,
Set_Min_key,
Set_Hr_key,
Ctrl_Bell,
Mode,
LED_Min1,
LED_Min2,
LED_Hr1,
LED_Hr2,
YYY
);
input _1kHzIN;
input YYY;
output [7:0] LED_Hr, LED_Min, LED_Sec;
output [6:0] LED_Min1, LED_Min2, LED_Hr1, LED_Hr2;
wire [7:0] LED_Hr, LED_Min, LED_Sec;
wire [6:0] LED_Min1, LED_Min2, LED_Hr1, LED_Hr2;
supply1 Vdd;
input Adj_Min_key, Adj_Hour_key;
wire [7:0] Hour, Minute, Second;
wire MinL_EN, MinH_EN, Hour_EN;
reg ALARM_Radio;
wire ALARM_Clock;
output ALARM;
wire [7:0] Set_Hr, Set_Min;
wire Hr_H_EQU, Hr_L_EQU, Min_H_EQU, Min_L_EQU;
input Set_Hr_key, Set_Min_key;
input Ctrl_Bell;
input Mode;
Divier_50MHz_2Hz(
Vdd, _1kHzIN, _1Hz
);
//Divided_Frequency U0(_1Hz,_2Hz,_500Hz,Vdd,Vdd,_1kHz);
counter10 U1 (
Second[3:0],
YYY,
Vdd,
_1Hz
);
counter6 U2 (
Second[7:4],
YYY,
(Second[3:0] == 4'h9),
_1Hz
);
assign MinL_EN = Adj_Min_key ? Vdd : (Second == 8'h59);
assign MinH_EN=(Adj_Min_key&&(Minute[3:0]==4'h9))||(Minute[3:0]==4'h9)&&(Second==8'h59);
counter10 U3 (
Minute[3:0],
YYY,
MinL_EN,
_1Hz
);
counter6 U4 (
Minute[7:4],
YYY,
MinH_EN,
_1Hz
);
assign Hour_EN = Adj_Hour_key ? Vdd : ((Minute == 8'h59) && (Second == 8'h59));
counter24 U5 (
Hour[7:4],
Hour[3:0],
YYY,
Hour_EN,
_1Hz
);
always @(Minute or Second)
if (Minute == 8'h59)
case (Second)
8'h51, 8'h53, 8'h55, 8'h57, 8'h59: ALARM_Radio = _1Hz;
default: ALARM_Radio = 1'b0;
endcase
else ALARM_Radio = 1'b0;
counter10 SU1 (
Set_Min[3:0],
Vdd,
Set_Min_key,
_1Hz
);
counter6 SU2 (
Set_Min[7:4],
Vdd,
(Set_Min[3:0] == 4'h9),
_1Hz
);
counter24 SU3 (
Set_Hr[7:4],
Set_Hr[3:0],
Vdd,
Set_Hr_key,
_1Hz
);
_4bitComparer SU4 (
Hr_H_EQU,
Set_Hr[7:4],
Hour[7:4]
);
_4bitComparer SU5 (
Hr_L_EQU,
Set_Hr[3:0],
Hour[3:0]
);
_4bitComparer SU6 (
Min_H_EQU,
Set_Min[7:4],
Minute[7:4]
);
_4bitComparer SU7 (
Min_L_EQU,
Set_Min[3:0],
Minute[3:0]
);
assign ALARM_Clock=Ctrl_Bell?(((Hr_H_EQU&&Hr_L_EQU&&Min_H_EQU&&Min_L_EQU))&&
(((Second[0]==1'b0)&&_1kHzIN))):1'b0;
assign ALARM = ALARM_Clock || ALARM_Radio;
_2to1MUX MU1 (
LED_Hr,
Mode,
Set_Hr,
Hour
);
_2to1MUX MU2 (
LED_Min,
Mode,
Set_Min,
Minute
);
_2to1MUX MU3 (
LED_Sec,
Mode,
8'h00,
Second
);
Decoder(
LED_Min1, LED_Min[3:0]
); Decoder(
LED_Min2, LED_Min[7:4]
); Decoder(
LED_Hr1, LED_Hr[3:0]
); Decoder(
LED_Hr2, LED_Hr[7:4]
);
endmodule
| 8.263203 |
module Divier_50MHz_2Hz (
input CR,
CLK_50M,
output reg CLk_1HzOut
);
reg [24:0] Count_Div;
always @(posedge CLK_50M or negedge CR) begin
if (!CR) begin
CLk_1HzOut <= 0;
Count_Div <= 0;
end else begin
// if(Count_Div<(50000000/(2*100))) //20Hz
if (Count_Div < 5) Count_Div <= Count_Div + 1'b1;
else begin
Count_Div <= 0;
CLk_1HzOut <= ~CLk_1HzOut;
end
end
end
endmodule
| 6.710338 |
module _2to1MUX (
OUT,
SEL,
X,
Y
);
input [7:0] X, Y;
input SEL;
output [7:0] OUT;
assign OUT = SEL ? X : Y;
endmodule
| 7.664288 |
module _4bitComparer (
EQU,
A,
B
);
input [3:0] A, B;
output EQU;
assign EQU = (A == B);
endmodule
| 7.754256 |
module Divided_Frequency (
_1HzOut,
_2HzOut,
_500HzOut,
nCR,
EN,
_1kHzIN
);
input _1kHzIN, nCR, EN;
output _1HzOut, _2HzOut, _500HzOut;
wire [11:0] Q;
wire EN1, EN2;
counter10 DU0 (
Q[3:0],
nCR,
EN,
_1kHzIN
);
counter10 DU1 (
Q[7:4],
nCR,
EN1,
_1kHzIN
);
counter10 DU2 (
Q[11:8],
nCR,
EN2,
_1kHzIN
);
assign EN1 = (Q[3:0] == 4'd9);
assign EN2 = (Q[7:4] == 4'd9) & (Q[3:0] == 4'd9);
assign _1HzOut = Q[11];
assign _2HzOut = Q[10];
assign _500HzOut = Q[0];
endmodule
| 6.690209 |
module counter6 (
Q,
nCR,
EN,
CP
);
input CP, nCR, EN;
output [3:0] Q;
reg [3:0] Q;
always @(posedge CP or negedge nCR) begin
if (~nCR) Q <= 4'b0000;
else if (~EN) Q <= Q;
else if (Q == 4'b0101) Q <= 4'b0000;
else Q <= Q + 1'b1;
end
endmodule
| 6.765105 |
module sz_ex (
//sign or zero extended value
output reg [(`BUS_WIDTH - 1):0] sz_ex_out,
//sign or zero extend select
input sz_ex_sel,
//sign or zero extend mode
input [1:0] sz_ex_mode,
//immediate value
input [(`IMMEDIATE_WIDTH -1):0] imm
);
//combinational logic
always @(*) begin
//check the mode
case (sz_ex_mode)
//STANDARD
`STANDARD: begin
//copy the immediate value
sz_ex_out[11:0] = imm[11:0];
//perform sign or zero extend
if (sz_ex_sel == 1'b1) begin
//sign extend
sz_ex_out[31:12] = {(`BUS_WIDTH - 12) {imm[11]}};
end else begin
//zero extend
sz_ex_out[31:12] = {(`BUS_WIDTH - 12) {1'b0}};
end
end
//BRANCH
`BRANCH: begin
//set LSb to zero
sz_ex_out[0] = 1'b0;
//copy the immediate value
sz_ex_out[12:1] = imm[11:0];
//perform sign or zero extend
if (sz_ex_sel == 1'b1) begin
//sign extend
sz_ex_out[31:13] = {(`BUS_WIDTH - 13) {imm[11]}};
end else begin
//zero extend
sz_ex_out[31:13] = {(`BUS_WIDTH - 13) {1'b0}};
end
end
//U_TYPE
`U_TYPE: begin
//copy the immediate to MSb bits of output
sz_ex_out[31:12] = imm[(`IMMEDIATE_WIDTH-1):0];
//zero out the lower order bits
sz_ex_out[11:0] = {(`BUS_WIDTH - 20) {1'b0}};
end
//JAL
`JAL: begin
//set LSb to zero
sz_ex_out[0] = 1'b0;
sz_ex_out[20:1] = imm[(`IMMEDIATE_WIDTH-1):0];
//sign extend
sz_ex_out[31:21] = {(`BUS_WIDTH - 21) {imm[19]}};
end
//default
default: begin
//set output to defult value to x (unknown)
sz_ex_out = {`BUS_WIDTH{1'bx}};
end
endcase
end
endmodule
| 7.547605 |
module sz_ex_tb;
// Inputs
reg sz_ex_sel;
reg [1:0] sz_ex_mode;
reg [19:0] imm;
// Outputs
wire [31:0] sz_ex_out;
// Instantiate the Unit Under Test (UUT)
sz_ex uut (
.sz_ex_out(sz_ex_out),
.sz_ex_sel(sz_ex_sel),
.sz_ex_mode(sz_ex_mode),
.imm(imm)
);
initial begin
// Initialize Inputs
sz_ex_sel = 0;
sz_ex_mode = 0;
imm = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
//monitor values of signals
$monitor("imm = %x, sz_ex_sel = %b, sz_ex_mode = %b, sz_ex_out = %x", imm, sz_ex_sel,
sz_ex_mode, sz_ex_out);
sz_ex_mode = `STANDARD;
imm = 20'h00FFF;
//zero extend
sz_ex_sel = 1'b0;
#10;
//sign extend
sz_ex_sel = 1'b1;
#10;
sz_ex_mode = `BRANCH;
imm = 20'h00FFF;
//zero extend
sz_ex_sel = 1'b0;
#10;
//sign extend
sz_ex_sel = 1'b1;
#10;
sz_ex_mode = `U_TYPE;
imm = 20'hFFFFF;
//zero extend
sz_ex_sel = 1'b0;
#10;
//sign extend
sz_ex_sel = 1'b1;
#10;
sz_ex_mode = `JAL;
imm = 20'hFFFFF;
//zero extend
sz_ex_sel = 1'b0;
#10;
//sign extend
sz_ex_sel = 1'b1;
#10;
//terminate simulation
$finish;
end
endmodule
| 6.915071 |
module s_acq_change (
rst_n,
clk_sys,
change,
s_load,
s_loadin1,
s_loadin2,
s_rst,
s_rstin1,
s_rstin2,
//s_start,
//s_startin1,
//s_startin2,
s_acqnum,
s_acqnumin1,
s_acqnumin2,
s_stripnum,
s_stripnumin1,
s_stripnumin2
);
input rst_n;
input clk_sys;
input [1:0] change;
output s_load;
input s_loadin1;
input s_loadin2;
reg s_load;
output s_rst;
input s_rstin1;
input s_rstin2;
reg s_rst;
//output s_start;
//input s_startin1;
//input s_startin2;
//reg s_start;
output [15:0] s_acqnum;
input [15:0] s_acqnumin1;
input [15:0] s_acqnumin2;
reg [15:0] s_acqnum;
output [11:0] s_stripnum;
input [11:0] s_stripnumin1;
input [11:0] s_stripnumin2;
reg [11:0] s_stripnum;
always @(posedge clk_sys) begin
if (rst_n == 1'b0) begin
s_load <= 1'b0;
s_rst <= 1'b0;
//s_start <= 1'b0;
s_acqnum <= 16'b0;
s_stripnum <= 12'b0;
end else begin
if (change == 2'b00) begin
s_load <= s_loadin1;
s_rst <= s_rstin1;
//s_start <= s_startin1;
s_acqnum <= s_acqnumin1;
s_stripnum <= s_stripnumin1;
end else if (change == 2'b01) begin
s_load <= s_loadin2;
s_rst <= s_rstin2;
//s_start <= s_startin2;
s_acqnum <= s_acqnumin2;
s_stripnum <= s_stripnumin2;
end else begin
s_load <= s_load;
s_rst <= s_rst;
//s_start <= s_start;
s_acqnum <= s_acqnum;
s_stripnum <= s_stripnum;
end
end
end
endmodule
| 6.778593 |
module S_ADD #(
P = 8
) ( //SUMADOR EXPONENTE FORMATO PUNTO FLOTANTE EN 32 BITS
input wire [P-1:0] A, //ENTRADA A
input wire [ 4:0] B, //ENTRADA B
output wire [P-1:0] Y //SALIDA Y
);
assign Y = A + B; //SUMA DE ENTRADAS
endmodule
| 7.230735 |
module S_BOX (
clk,
addr,
out
);
input wire clk;
input wire [7:0] addr;
output reg [7:0] out;
reg [7:0] rom[0:255];
initial begin
$readmemh("S_BOX.txt", rom);
end
always @(posedge clk) begin
out <= rom[addr];
end
//assign out=out_reg;
endmodule
| 6.623843 |
module performs the function of the S-Boxes on the whole vector.
module S_Boxes(
input [47:0] i_vector,
output [31:0] o_vector
);
S_Box_1 S_Box_1_inst
(
.i_vector(i_vector[5:0]) , // input [5:0] i_vector[:]
.o_vector(o_vector[3:0]) // output [3:0] o_vector[:]
);
S_Box_2 S_Box_2_inst
(
.i_vector(i_vector[11:6]) , // input [5:0] i_vector[:]
.o_vector(o_vector[7:4]) // output [3:0] o_vector[:]
);
S_Box_3 S_Box_3_inst
(
.i_vector(i_vector[17:12]) , // input [5:0] i_vector[:]
.o_vector(o_vector[11:8]) // output [3:0] o_vector[:]
);
S_Box_4 S_Box_4_inst
(
.i_vector(i_vector[23:18]) , // input [5:0] i_vector[:]
.o_vector(o_vector[15:12]) // output [3:0] o_vector[:]
);
S_Box_5 S_Box_5_inst
(
.i_vector(i_vector[29:24]) , // input [5:0] i_vector[:]
.o_vector(o_vector[19:16]) // output [3:0] o_vector[:]
);
S_Box_6 S_Box_6_inst
(
.i_vector(i_vector[35:30]) , // input [5:0] i_vector[:]
.o_vector(o_vector[23:20]) // output [3:0] o_vector[:]
);
S_Box_7 S_Box_7_inst
(
.i_vector(i_vector[41:36]) , // input [5:0] i_vector[:]
.o_vector(o_vector[27:24]) // output [3:0] o_vector[:]
);
S_Box_8 S_Box_8_inst
(
.i_vector(i_vector[47:42]) , // input [5:0] i_vector[:]
.o_vector(o_vector[31:28]) // output [3:0] o_vector[:]
);
endmodule
| 7.634754 |
module performs the function of the S-Box 1.
module S_Box_1(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 14;
6'b000001 : o_vector = 0;
6'b000010 : o_vector = 4;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 13;
6'b000101 : o_vector = 7;
6'b000110 : o_vector = 1;
6'b000111 : o_vector = 4;
6'b001000 : o_vector = 2;
6'b001001 : o_vector = 14;
6'b001010 : o_vector = 15;
6'b001011 : o_vector = 2;
6'b001100 : o_vector = 11;
6'b001101 : o_vector = 13;
6'b001110 : o_vector = 8;
6'b001111 : o_vector = 1;
6'b010000 : o_vector = 3;
6'b010001 : o_vector = 10;
6'b010010 : o_vector = 10;
6'b010011 : o_vector = 6;
6'b010100 : o_vector = 6;
6'b010101 : o_vector = 12;
6'b010110 : o_vector = 12;
6'b010111 : o_vector = 11;
6'b011000 : o_vector = 5;
6'b011001 : o_vector = 9;
6'b011010 : o_vector = 9;
6'b011011 : o_vector = 5;
6'b011100 : o_vector = 0;
6'b011101 : o_vector = 3;
6'b011110 : o_vector = 7;
6'b011111 : o_vector = 8;
6'b100000 : o_vector = 4;
6'b100001 : o_vector = 15;
6'b100010 : o_vector = 1;
6'b100011 : o_vector = 12;
6'b100100 : o_vector = 14;
6'b100101 : o_vector = 8;
6'b100110 : o_vector = 8;
6'b100111 : o_vector = 2;
6'b101000 : o_vector = 13;
6'b101001 : o_vector = 4;
6'b101010 : o_vector = 6;
6'b101011 : o_vector = 9;
6'b101100 : o_vector = 2;
6'b101101 : o_vector = 1;
6'b101110 : o_vector = 11;
6'b101111 : o_vector = 7;
6'b110000 : o_vector = 15;
6'b110001 : o_vector = 5;
6'b110010 : o_vector = 12;
6'b110011 : o_vector = 11;
6'b110100 : o_vector = 9;
6'b110101 : o_vector = 3;
6'b110110 : o_vector = 7;
6'b110111 : o_vector = 14;
6'b111000 : o_vector = 3;
6'b111001 : o_vector = 10;
6'b111010 : o_vector = 10;
6'b111011 : o_vector = 0;
6'b111100 : o_vector = 5;
6'b111101 : o_vector = 6;
6'b111110 : o_vector = 0;
6'b111111 : o_vector = 13;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 2.
module S_Box_2(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 15;
6'b000001 : o_vector = 3;
6'b000010 : o_vector = 1;
6'b000011 : o_vector = 13;
6'b000100 : o_vector = 8;
6'b000101 : o_vector = 4;
6'b000110 : o_vector = 14;
6'b000111 : o_vector = 7;
6'b001000 : o_vector = 6;
6'b001001 : o_vector = 15;
6'b001010 : o_vector = 11;
6'b001011 : o_vector = 2;
6'b001100 : o_vector = 3;
6'b001101 : o_vector = 8;
6'b001110 : o_vector = 4;
6'b001111 : o_vector = 14;
6'b010000 : o_vector = 9;
6'b010001 : o_vector = 12;
6'b010010 : o_vector = 7;
6'b010011 : o_vector = 0;
6'b010100 : o_vector = 2;
6'b010101 : o_vector = 1;
6'b010110 : o_vector = 13;
6'b010111 : o_vector = 10;
6'b011000 : o_vector = 12;
6'b011001 : o_vector = 6;
6'b011010 : o_vector = 0;
6'b011011 : o_vector = 9;
6'b011100 : o_vector = 5;
6'b011101 : o_vector = 11;
6'b011110 : o_vector = 10;
6'b011111 : o_vector = 5;
6'b100000 : o_vector = 0;
6'b100001 : o_vector = 13;
6'b100010 : o_vector = 14;
6'b100011 : o_vector = 8;
6'b100100 : o_vector = 7;
6'b100101 : o_vector = 10;
6'b100110 : o_vector = 11;
6'b100111 : o_vector = 1;
6'b101000 : o_vector = 10;
6'b101001 : o_vector = 3;
6'b101010 : o_vector = 4;
6'b101011 : o_vector = 15;
6'b101100 : o_vector = 13;
6'b101101 : o_vector = 4;
6'b101110 : o_vector = 1;
6'b101111 : o_vector = 2;
6'b110000 : o_vector = 5;
6'b110001 : o_vector = 11;
6'b110010 : o_vector = 8;
6'b110011 : o_vector = 6;
6'b110100 : o_vector = 12;
6'b110101 : o_vector = 7;
6'b110110 : o_vector = 6;
6'b110111 : o_vector = 12;
6'b111000 : o_vector = 9;
6'b111001 : o_vector = 0;
6'b111010 : o_vector = 3;
6'b111011 : o_vector = 5;
6'b111100 : o_vector = 2;
6'b111101 : o_vector = 14;
6'b111110 : o_vector = 15;
6'b111111 : o_vector = 9;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 3.
module S_Box_3(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 10;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 0;
6'b000011 : o_vector = 7;
6'b000100 : o_vector = 9;
6'b000101 : o_vector = 0;
6'b000110 : o_vector = 14;
6'b000111 : o_vector = 9;
6'b001000 : o_vector = 6;
6'b001001 : o_vector = 3;
6'b001010 : o_vector = 3;
6'b001011 : o_vector = 4;
6'b001100 : o_vector = 15;
6'b001101 : o_vector = 6;
6'b001110 : o_vector = 5;
6'b001111 : o_vector = 10;
6'b010000 : o_vector = 1;
6'b010001 : o_vector = 2;
6'b010010 : o_vector = 13;
6'b010011 : o_vector = 8;
6'b010100 : o_vector = 12;
6'b010101 : o_vector = 5;
6'b010110 : o_vector = 7;
6'b010111 : o_vector = 14;
6'b011000 : o_vector = 11;
6'b011001 : o_vector = 12;
6'b011010 : o_vector = 4;
6'b011011 : o_vector = 11;
6'b011100 : o_vector = 2;
6'b011101 : o_vector = 15;
6'b011110 : o_vector = 8;
6'b011111 : o_vector = 1;
6'b100000 : o_vector = 13;
6'b100001 : o_vector = 1;
6'b100010 : o_vector = 6;
6'b100011 : o_vector = 10;
6'b100100 : o_vector = 4;
6'b100101 : o_vector = 13;
6'b100110 : o_vector = 9;
6'b100111 : o_vector = 0;
6'b101000 : o_vector = 8;
6'b101001 : o_vector = 6;
6'b101010 : o_vector = 15;
6'b101011 : o_vector = 9;
6'b101100 : o_vector = 3;
6'b101101 : o_vector = 8;
6'b101110 : o_vector = 0;
6'b101111 : o_vector = 7;
6'b110000 : o_vector = 11;
6'b110001 : o_vector = 4;
6'b110010 : o_vector = 1;
6'b110011 : o_vector = 15;
6'b110100 : o_vector = 2;
6'b110101 : o_vector = 14;
6'b110110 : o_vector = 12;
6'b110111 : o_vector = 3;
6'b111000 : o_vector = 5;
6'b111001 : o_vector = 11;
6'b111010 : o_vector = 10;
6'b111011 : o_vector = 5;
6'b111100 : o_vector = 14;
6'b111101 : o_vector = 2;
6'b111110 : o_vector = 7;
6'b111111 : o_vector = 12;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 4.
module S_Box_4(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 7;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 13;
6'b000011 : o_vector = 8;
6'b000100 : o_vector = 14;
6'b000101 : o_vector = 11;
6'b000110 : o_vector = 3;
6'b000111 : o_vector = 5;
6'b001000 : o_vector = 0;
6'b001001 : o_vector = 6;
6'b001010 : o_vector = 6;
6'b001011 : o_vector = 15;
6'b001100 : o_vector = 9;
6'b001101 : o_vector = 0;
6'b001110 : o_vector = 10;
6'b001111 : o_vector = 3;
6'b010000 : o_vector = 1;
6'b010001 : o_vector = 4;
6'b010010 : o_vector = 2;
6'b010011 : o_vector = 7;
6'b010100 : o_vector = 8;
6'b010101 : o_vector = 2;
6'b010110 : o_vector = 5;
6'b010111 : o_vector = 12;
6'b011000 : o_vector = 11;
6'b011001 : o_vector = 1;
6'b011010 : o_vector = 12;
6'b011011 : o_vector = 10;
6'b011100 : o_vector = 4;
6'b011101 : o_vector = 14;
6'b011110 : o_vector = 15;
6'b011111 : o_vector = 9;
6'b100000 : o_vector = 10;
6'b100001 : o_vector = 3;
6'b100010 : o_vector = 6;
6'b100011 : o_vector = 15;
6'b100100 : o_vector = 9;
6'b100101 : o_vector = 0;
6'b100110 : o_vector = 0;
6'b100111 : o_vector = 6;
6'b101000 : o_vector = 12;
6'b101001 : o_vector = 10;
6'b101010 : o_vector = 11;
6'b101011 : o_vector = 1;
6'b101100 : o_vector = 7;
6'b101101 : o_vector = 13;
6'b101110 : o_vector = 13;
6'b101111 : o_vector = 8;
6'b110000 : o_vector = 15;
6'b110001 : o_vector = 9;
6'b110010 : o_vector = 1;
6'b110011 : o_vector = 4;
6'b110100 : o_vector = 3;
6'b110101 : o_vector = 5;
6'b110110 : o_vector = 14;
6'b110111 : o_vector = 11;
6'b111000 : o_vector = 5;
6'b111001 : o_vector = 12;
6'b111010 : o_vector = 2;
6'b111011 : o_vector = 7;
6'b111100 : o_vector = 8;
6'b111101 : o_vector = 2;
6'b111110 : o_vector = 4;
6'b111111 : o_vector = 14;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 5.
module S_Box_5(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 2;
6'b000001 : o_vector = 14;
6'b000010 : o_vector = 12;
6'b000011 : o_vector = 11;
6'b000100 : o_vector = 4;
6'b000101 : o_vector = 2;
6'b000110 : o_vector = 1;
6'b000111 : o_vector = 12;
6'b001000 : o_vector = 7;
6'b001001 : o_vector = 4;
6'b001010 : o_vector = 10;
6'b001011 : o_vector = 7;
6'b001100 : o_vector = 11;
6'b001101 : o_vector = 13;
6'b001110 : o_vector = 6;
6'b001111 : o_vector = 1;
6'b010000 : o_vector = 8;
6'b010001 : o_vector = 5;
6'b010010 : o_vector = 5;
6'b010011 : o_vector = 0;
6'b010100 : o_vector = 3;
6'b010101 : o_vector = 15;
6'b010110 : o_vector = 15;
6'b010111 : o_vector = 10;
6'b011000 : o_vector = 13;
6'b011001 : o_vector = 3;
6'b011010 : o_vector = 0;
6'b011011 : o_vector = 9;
6'b011100 : o_vector = 14;
6'b011101 : o_vector = 8;
6'b011110 : o_vector = 9;
6'b011111 : o_vector = 6;
6'b100000 : o_vector = 4;
6'b100001 : o_vector = 11;
6'b100010 : o_vector = 2;
6'b100011 : o_vector = 8;
6'b100100 : o_vector = 1;
6'b100101 : o_vector = 12;
6'b100110 : o_vector = 11;
6'b100111 : o_vector = 7;
6'b101000 : o_vector = 10;
6'b101001 : o_vector = 1;
6'b101010 : o_vector = 13;
6'b101011 : o_vector = 14;
6'b101100 : o_vector = 7;
6'b101101 : o_vector = 2;
6'b101110 : o_vector = 8;
6'b101111 : o_vector = 13;
6'b110000 : o_vector = 15;
6'b110001 : o_vector = 6;
6'b110010 : o_vector = 9;
6'b110011 : o_vector = 15;
6'b110100 : o_vector = 12;
6'b110101 : o_vector = 0;
6'b110110 : o_vector = 5;
6'b110111 : o_vector = 9;
6'b111000 : o_vector = 6;
6'b111001 : o_vector = 10;
6'b111010 : o_vector = 3;
6'b111011 : o_vector = 4;
6'b111100 : o_vector = 0;
6'b111101 : o_vector = 5;
6'b111110 : o_vector = 14;
6'b111111 : o_vector = 3;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 6.
module S_Box_6(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 12;
6'b000001 : o_vector = 10;
6'b000010 : o_vector = 1;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 10;
6'b000101 : o_vector = 4;
6'b000110 : o_vector = 15;
6'b000111 : o_vector = 2;
6'b001000 : o_vector = 9;
6'b001001 : o_vector = 7;
6'b001010 : o_vector = 2;
6'b001011 : o_vector = 12;
6'b001100 : o_vector = 6;
6'b001101 : o_vector = 9;
6'b001110 : o_vector = 8;
6'b001111 : o_vector = 5;
6'b010000 : o_vector = 0;
6'b010001 : o_vector = 6;
6'b010010 : o_vector = 13;
6'b010011 : o_vector = 1;
6'b010100 : o_vector = 3;
6'b010101 : o_vector = 13;
6'b010110 : o_vector = 4;
6'b010111 : o_vector = 14;
6'b011000 : o_vector = 14;
6'b011001 : o_vector = 0;
6'b011010 : o_vector = 7;
6'b011011 : o_vector = 11;
6'b011100 : o_vector = 5;
6'b011101 : o_vector = 3;
6'b011110 : o_vector = 11;
6'b011111 : o_vector = 8;
6'b100000 : o_vector = 9;
6'b100001 : o_vector = 4;
6'b100010 : o_vector = 14;
6'b100011 : o_vector = 3;
6'b100100 : o_vector = 15;
6'b100101 : o_vector = 2;
6'b100110 : o_vector = 5;
6'b100111 : o_vector = 12;
6'b101000 : o_vector = 2;
6'b101001 : o_vector = 9;
6'b101010 : o_vector = 8;
6'b101011 : o_vector = 5;
6'b101100 : o_vector = 12;
6'b101101 : o_vector = 15;
6'b101110 : o_vector = 3;
6'b101111 : o_vector = 10;
6'b110000 : o_vector = 7;
6'b110001 : o_vector = 11;
6'b110010 : o_vector = 0;
6'b110011 : o_vector = 14;
6'b110100 : o_vector = 4;
6'b110101 : o_vector = 1;
6'b110110 : o_vector = 10;
6'b110111 : o_vector = 7;
6'b111000 : o_vector = 1;
6'b111001 : o_vector = 6;
6'b111010 : o_vector = 13;
6'b111011 : o_vector = 0;
6'b111100 : o_vector = 11;
6'b111101 : o_vector = 8;
6'b111110 : o_vector = 6;
6'b111111 : o_vector = 13;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 7.
module S_Box_7(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 4;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 11;
6'b000011 : o_vector = 0;
6'b000100 : o_vector = 2;
6'b000101 : o_vector = 11;
6'b000110 : o_vector = 14;
6'b000111 : o_vector = 7;
6'b001000 : o_vector = 15;
6'b001001 : o_vector = 4;
6'b001010 : o_vector = 0;
6'b001011 : o_vector = 9;
6'b001100 : o_vector = 8;
6'b001101 : o_vector = 1;
6'b001110 : o_vector = 13;
6'b001111 : o_vector = 10;
6'b010000 : o_vector = 3;
6'b010001 : o_vector = 14;
6'b010010 : o_vector = 12;
6'b010011 : o_vector = 3;
6'b010100 : o_vector = 9;
6'b010101 : o_vector = 5;
6'b010110 : o_vector = 7;
6'b010111 : o_vector = 12;
6'b011000 : o_vector = 5;
6'b011001 : o_vector = 2;
6'b011010 : o_vector = 10;
6'b011011 : o_vector = 15;
6'b011100 : o_vector = 6;
6'b011101 : o_vector = 8;
6'b011110 : o_vector = 1;
6'b011111 : o_vector = 6;
6'b100000 : o_vector = 1;
6'b100001 : o_vector = 6;
6'b100010 : o_vector = 4;
6'b100011 : o_vector = 11;
6'b100100 : o_vector = 11;
6'b100101 : o_vector = 13;
6'b100110 : o_vector = 13;
6'b100111 : o_vector = 8;
6'b101000 : o_vector = 12;
6'b101001 : o_vector = 1;
6'b101010 : o_vector = 3;
6'b101011 : o_vector = 4;
6'b101100 : o_vector = 7;
6'b101101 : o_vector = 10;
6'b101110 : o_vector = 14;
6'b101111 : o_vector = 7;
6'b110000 : o_vector = 10;
6'b110001 : o_vector = 9;
6'b110010 : o_vector = 15;
6'b110011 : o_vector = 5;
6'b110100 : o_vector = 6;
6'b110101 : o_vector = 0;
6'b110110 : o_vector = 8;
6'b110111 : o_vector = 15;
6'b111000 : o_vector = 0;
6'b111001 : o_vector = 14;
6'b111010 : o_vector = 5;
6'b111011 : o_vector = 2;
6'b111100 : o_vector = 9;
6'b111101 : o_vector = 3;
6'b111110 : o_vector = 2;
6'b111111 : o_vector = 12;
endcase
endmodule
| 7.634754 |
module performs the function of the S-Box 8.
module S_Box_8(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 13;
6'b000001 : o_vector = 1;
6'b000010 : o_vector = 2;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 8;
6'b000101 : o_vector = 13;
6'b000110 : o_vector = 4;
6'b000111 : o_vector = 8;
6'b001000 : o_vector = 6;
6'b001001 : o_vector = 10;
6'b001010 : o_vector = 15;
6'b001011 : o_vector = 3;
6'b001100 : o_vector = 11;
6'b001101 : o_vector = 7;
6'b001110 : o_vector = 1;
6'b001111 : o_vector = 4;
6'b010000 : o_vector = 10;
6'b010001 : o_vector = 12;
6'b010010 : o_vector = 9;
6'b010011 : o_vector = 5;
6'b010100 : o_vector = 3;
6'b010101 : o_vector = 6;
6'b010110 : o_vector = 14;
6'b010111 : o_vector = 11;
6'b011000 : o_vector = 5;
6'b011001 : o_vector = 0;
6'b011010 : o_vector = 0;
6'b011011 : o_vector = 14;
6'b011100 : o_vector = 12;
6'b011101 : o_vector = 9;
6'b011110 : o_vector = 7;
6'b011111 : o_vector = 2;
6'b100000 : o_vector = 7;
6'b100001 : o_vector = 2;
6'b100010 : o_vector = 11;
6'b100011 : o_vector = 1;
6'b100100 : o_vector = 4;
6'b100101 : o_vector = 14;
6'b100110 : o_vector = 1;
6'b100111 : o_vector = 7;
6'b101000 : o_vector = 9;
6'b101001 : o_vector = 4;
6'b101010 : o_vector = 12;
6'b101011 : o_vector = 10;
6'b101100 : o_vector = 14;
6'b101101 : o_vector = 8;
6'b101110 : o_vector = 2;
6'b101111 : o_vector = 13;
6'b110000 : o_vector = 0;
6'b110001 : o_vector = 15;
6'b110010 : o_vector = 6;
6'b110011 : o_vector = 12;
6'b110100 : o_vector = 10;
6'b110101 : o_vector = 9;
6'b110110 : o_vector = 13;
6'b110111 : o_vector = 0;
6'b111000 : o_vector = 15;
6'b111001 : o_vector = 3;
6'b111010 : o_vector = 3;
6'b111011 : o_vector = 5;
6'b111100 : o_vector = 5;
6'b111101 : o_vector = 6;
6'b111110 : o_vector = 8;
6'b111111 : o_vector = 11;
endcase
endmodule
| 7.634754 |
module is a test bench for the s_box. The output of test bench is
// a pass or fail results passed on the obtained values.
module s_box_tb;
reg [7:0] inputValue1;
reg [7:0] inputValue2;
reg [7:0] inputValue3;
reg [7:0] expectedValue1;
reg [7:0] expectedValue2;
reg [7:0] expectedValue3;
wire [7:0] outputValue1;
wire [7:0] outputValue2;
wire [7:0] outputValue3;
s_box dut1(
.inputValue (inputValue1),
.sboxOutput (outputValue1)
);
s_box dut2(
.inputValue (inputValue2),
.sboxOutput (outputValue2)
);
s_box dut3(
.inputValue (inputValue3),
.sboxOutput (outputValue3)
);
initial begin
// Set expected values
expectedValue1 = 8'h63;
expectedValue2 = 8'hf5;
expectedValue3 = 8'hc1;
end
always @(*) begin
inputValue1 = 8'h00;
inputValue2 = 8'h77;
inputValue3 = 8'hdd;
// Comparing the acquired outputs with the expected outputs and printing
// the corresponding message depending on the results.
if((outputValue1 != expectedValue1) | (outputValue2 != expectedValue2) | (outputValue3 != expectedValue3))begin
$display("Fail \n \n",
"For the following inputs: \n",
"Input Value: %h, %h, %h \n \n", inputValue1, inputValue2, inputValue3,
"Expected output: \n",
"Output Value: %h, %h, %h \n \n", expectedValue1, expectedValue2, expectedValue3,
"Aquired output: \n",
"Output Value: %h, %h, %h \n", outputValue1, outputValue2, outputValue3
);
end
if((outputValue1 == expectedValue1) & (outputValue2 == expectedValue2) & (outputValue3 == expectedValue3))begin
$display("Pass \n \n",
"For the following inputs: \n",
"Input Value: %h, %h, %h \n \n", inputValue1, inputValue2, inputValue3,
"Aquired output: \n",
"Output Value: %h, %h, %h \n", outputValue1, outputValue2, outputValue3
);
end
end
endmodule
| 6.595812 |
module s_bsc (
in,
out,
sdi,
sdo,
shift,
update,
clock,
brk
);
input [2:0] in;
input sdi, shift, update, clock, brk;
output [2:0] out;
output sdo;
wire di0, di1;
bsc
bsc0 (
sdi,
di0,
shift,
update,
clock,
in[0],
1'b1,
brk,
out[0]
),
bsc1 (
di0,
di1,
shift,
update,
clock,
in[1],
1'b1,
brk,
out[1]
),
bsc2 (
di1,
sdo,
shift,
update,
clock,
in[2],
1'b1,
brk,
out[2]
);
endmodule
| 6.584125 |
module S_Buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 256,
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.730376 |
module cpen4 (
e,
nz,
w
);
output [1:0] e;
output nz;
input [3:0] w;
assign #`da nz = |w[3:0];
assign #`da e[0] = (w[3:2] == 2'b01) || (w[3:0] == 4'b0001);
assign #`da e[1] = (w[3:2] == 2'b00);
endmodule
| 6.575312 |
module S_Const (
input nReset,
input Clk,
input [15:0] Bandwidth, // kHz
output reg [17:0] a
);
parameter fs = 18'd50_000; // f_Clk [kHz]
parameter fs_2 = 16'd25_000; // fs / 2
reg [ 1:0] state;
reg [15:0] bw;
reg [17:0] mask;
reg [17:0] x;
reg [17:0] y;
wire [35:0] z;
assign z = x * y;
always @(negedge nReset, posedge Clk) begin
if (!nReset) begin
state <= 0;
bw <= 0;
mask <= 0;
x <= 0;
y <= 0;
a <= 0;
end else begin
bw <= Bandwidth;
case (state)
2'b00: begin
if (bw >= fs_2) begin
a <= 0;
end else begin
x <= 18'h3_24_3F; // pi;
y[17:16] <= 2'b00;
y[15:0] <= bw;
state <= 2'b01;
end
end
2'b01: begin
y <= fs + z[32:15];
x <= 18'h2_00_00;
mask <= 18'h2_00_00;
state <= 2'b10;
end
2'b10: begin
if (z[35:18] > fs) begin
x <= x & (~mask);
end
mask <= {1'b0, mask[17:1]};
state <= 2'b11;
end
2'b11: begin
if (~|mask) begin
a <= x;
state <= 2'b00;
end else begin
x <= x | mask;
state <= 2'b10;
end
end
default: ;
endcase
end
end
endmodule
| 6.817469 |
module s_core(
//input wire clk ,
//input wire rst_n,
////pc
//input wire i_stall,
//input wire i_is_branch_true,
//input wire i_writing_first_addr,
//input wire[31:0] i_instr_start_addr,
////instr_mem
//input wire re,
//input wire is_write,
//input wire[31:0] im_inst,
////regs
//input wire write_en,
//input wire rd_ctrl,
//input wire[4:0] load_addr,
//input wire[31:0] load_data,
//output wire[31:0] o_r_pc,
//output wire[31:0] inst_data,
//output wire[31:0] rs1_data,
//output wire[31:0] rs2_data,
//output wire[31:0] w_output,
//output br_cond
//);
////////// regs
//wire[31:0] i_branch_addr;
//pc uut_pc (clk,rst_n,i_stall,i_is_branch_true,i_branch_addr,i_writing_first_addr,i_instr_start_addr,o_r_pc);
////////instr mem
//wire[31:0] pc_in;
//inst_ram1 uut_inst(
//clk,
//inst_data,
//pc_in,
//re,is_write,
//im_inst
//);
////////// reg
//wire[4:0] rs1_addr;
//wire[4:0] rs2_addr;
//wire[4:0] rd_addr;
//wire[31:0] rd_data;
//regs uut_reg (clk,rst_n,rs1_addr,rs2_addr,rd_addr,rd_data,write_en,rs1_data,rs2_data);
/////////ALU
//wire [31:0 ] r_input_1;
//wire [31:0 ] r_input_2;
//wire[4:0] r_operator;
//alu uut_alu(.i_alu_operator(r_operator),.i_alu_operand_1(r_input_1),.i_alu_operand_2(r_input_2),.o_alu_output(w_output),.o_alu_br_cond(br_cond));
//assign pc_in=o_r_pc;
//assign rs1_addr=inst_data[19:15];
//assign rs2_addr=inst_data[24:20];
//assign rd_addr= rd_ctrl==1?load_addr : inst_data[11:7];
//assign rd_data = rd_ctrl==1?load_data:w_output;
//assign r_operator = inst_data[14:12]==0 && inst_data[31:25]==0 ? `ADD :
// inst_data[14:12]==0 && inst_data[31:25]==32 ? `SUB:
// inst_data[14:12]==2 && inst_data[31:25]==0 ? `SLT_UNSIGN:`PASSTHROUGH_RS1;
//assign r_input_1 = rs1_data;
//assign r_input_2 = rs2_data;
//endmodule
| 6.660202 |
module forwarding (
input wire [4:0] ID_EX_rs2,
input wire [4:0] ID_EX_rs1,
input wire [6:0] ex_mem_opcode,
input wire ex_mem_REG_write_en,
input wire mem_wb_REG_write_en,
input wire [4:0] EX_MEM_rd,
input wire [4:0] MEM_WB_rd,
output wire [1:0] forward_mux1,
output wire [1:0] forward_mux2
);
//forwarding unit
assign forward_mux1=(ex_mem_REG_write_en==1'b1 && EX_MEM_rd!=5'b0 && EX_MEM_rd==ID_EX_rs1 )?2'b10:
(mem_wb_REG_write_en==1'b1 && MEM_WB_rd!=5'b0 && MEM_WB_rd==ID_EX_rs1)?2'b01:
(ex_mem_REG_write_en==1'b1 && MEM_WB_rd!=5'b0 && MEM_WB_rd==ID_EX_rs1 )?2'b11:
2'b00;
assign forward_mux2=(ex_mem_REG_write_en==1'b1 && EX_MEM_rd!=5'b0 && EX_MEM_rd==ID_EX_rs2 )?2'b10:
(mem_wb_REG_write_en==1'b1 && MEM_WB_rd!=5'b0 && MEM_WB_rd==ID_EX_rs2)?2'b01:
(ex_mem_REG_write_en==1'b1 && MEM_WB_rd!=5'b0 && MEM_WB_rd==ID_EX_rs2 )?2'b11:
2'b00;
endmodule
| 6.668885 |
module branch_prediction (
input wire clk,
input wire rst_n,
input wire [1:0] br_taken,
input wire [6:0] IF_ID_op,
input wire [6:0] ID_EX_op,
output wire branch_predict
);
//wire [1:0]branch_predict; /00 01 branch 10 11 branch no taken =11 not taken =00
//assign branch_predict=branch_pred;
reg [1:0] branch_reg;
always @(posedge clk) begin
if (rst_n == 1'b0) begin
branch_reg <= 2'b00;
end
if(branch_reg==2'b00 && (br_taken==2'b01 ) && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b00;
else if(branch_reg==2'b00 && br_taken==2'b10 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b01;
else if(branch_reg==2'b01 && br_taken==2'b01 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b00;
else if(branch_reg==2'b01 && br_taken==2'b10 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b10;
else if(branch_reg==2'b10 && br_taken==2'b01 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b01;
else if(branch_reg==2'b10 && br_taken==2'b10 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b10;
else if(branch_reg==2'b10 && br_taken==2'b01 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b11;
else if(branch_reg==2'b11 && br_taken==2'b10 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b10;
else if(branch_reg==2'b11 && br_taken==2'b01 && (ID_EX_op==`OPCODE_BRANCH ||ID_EX_op == `OPCODE_JAL || ID_EX_op == `OPCODE_JALR))
branch_reg <= 2'b11;
end
assign branch_predict= IF_ID_op == `OPCODE_JAL ? 1'b1 :
IF_ID_op !=`OPCODE_BRANCH ? 1'b0 :
(branch_reg==2'b00 || branch_reg==2'b01)?1'b1:
1'b0;
// if(branch_reg==2'b00 || branch_reg==2'b01)
// // =cla_adder_out[31:0];
// else if(branch_reg==2'b10 || branch_reg==2'b11)
// //o_pc=o_pc+4'b0100;
// end
endmodule
| 6.779337 |
module hazard_detection (
input wire [4:0] ID_EX_rd,
input wire [4:0] IF_ID_rs1,
input wire [4:0] IF_ID_rs2,
input wire ID_EX_read_enable,
output wire hazard_detection
);
assign hazard_detection=(ID_EX_read_enable==1'b1 && ( ID_EX_rd==IF_ID_rs1 || ID_EX_rd==IF_ID_rs2 ))?1'b1:1'b0;
endmodule
| 6.869872 |
module s_counter #(
// asclk frequency
parameter CLOCK_CYCLE_MHZ = 160
) (
// AXI ports
input asclk,
input aresetn,
output reg [`OPENFLOW_LAST_SEEN_WIDTH-1:0] s_counter,
output reg [9:0] ms_counter,
output reg [9:0] us_counter
);
//------------------------ Wires/Regs -----------------------------
reg [9:0] mhz_counter;
//--------------------------- Logic -------------------------------
always @(posedge asclk) begin
if (~aresetn) begin
mhz_counter <= 0;
us_counter <= 0;
ms_counter <= 0;
s_counter <= 0;
end else begin
if (mhz_counter >= CLOCK_CYCLE_MHZ - 1) begin
mhz_counter <= 0;
if (us_counter >= 999) begin
us_counter <= 0;
if (ms_counter >= 999) begin
ms_counter <= 0;
if (s_counter >= (1'b1 << (`OPENFLOW_LAST_SEEN_WIDTH + 1)) - 1) begin
s_counter <= 0;
end else begin
s_counter <= s_counter + 1;
end
end else begin
ms_counter <= ms_counter + 1;
end
end else begin
us_counter <= us_counter + 1;
end
end else begin
mhz_counter <= mhz_counter + 1;
end
end
end
endmodule
| 7.993778 |
module S_Coupling (
input nReset,
input Clk, // 45 MHz
input [23:0] Input, // 2's Compliment
output [23:0] Output, // 2's Compliment
input Coupling
); // 1 = AC (1 Hz), 0 = DC
wire [23:0] DC;
wire [23:0] AC;
ACDC #(24, 24, 8) ACDC1 (
nReset,
Clk,
Input,
AC,
DC
);
assign Output = Coupling ? AC : Input;
endmodule
| 6.706154 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end else if (J == 0 & K == 1) begin
Q <= 0;
NQ <= 1;
end else begin
Q <= ~Q;
NQ <= ~NQ;
end
end
endmodule
| 6.615218 |
module S_Ext16 (
input [15 : 0] simem15_0,
output [31 : 0] sto_mux4
);
assign sto_mux4 = {{(16) {simem15_0[15]}}, simem15_0};
endmodule
| 6.910846 |
module S_Ext18 (
input [15:0] data_in,
output [31:0] data_out
);
assign data_out = {{14{data_in[15]}}, data_in, 2'b00};
endmodule
| 6.680344 |
module S_Ext8 (
input [ 7:0] data_in,
output [31:0] data_out
);
assign data_out = {{24{data_in[7]}}, data_in};
endmodule
| 7.829551 |
module S_EXTEND (
IF_ID_instr_immed,
signext_out
);
input [15:0] IF_ID_instr_immed;
output [31:0] signext_out;
// Repeat most significant bit to pad
assign signext_out = {{16{IF_ID_instr_immed[15]}}, IF_ID_instr_immed};
endmodule
| 7.868308 |
module S_Filter (
input nReset,
input Clk, // 45 MHz
input [23:0] Input,
output reg [23:0] Output,
input [17:0] a
); // 2^18 - a
// H(z) = --------------
// 2^18 - a*z^-1
reg [23:0] xn;
reg [43:0] yn_1;
wire [44:0] yn;
wire [17:0] b;
wire [41:0] bx;
wire [61:0] ay;
assign b = -a;
always @(negedge nReset, posedge Clk) begin
if (!nReset) begin
xn <= 0;
yn_1 <= 0;
Output <= 0;
end else begin
if (~|a) begin
Output <= Input;
end else begin
xn <= {(~Input[23]), Input[22:0]};
if (!yn[44]) begin
yn_1 <= yn[43:0];
Output <= {~yn[43], yn[42:20]};
end else begin
yn_1 <= {44{1'b1}};
Output <= 24'h7FFFFF;
end
end
end
end
assign bx = b * xn;
assign ay = a * yn_1;
assign yn = {1'b0, ay[61:18]} + ay[17] + {1'b0, bx, 2'b00};
endmodule
| 6.661484 |
module S_FlipFlop(S, B, D, T, I, CLK);
output S;
input [11:0]B, [7:0]D, [7:0]T, I, CLK;
wire j, k;
assign j = D[7] & ~I & T[3] & B[0];
assign k = 1'b0;
JK_FLipFlop jkff(S, j, k, CLK);
endmodule
| 7.050833 |
module s_p (
input wire clk,
input wire rst_n,
input wire [ 33:0] data_in_1,
output reg [135:0] data_out_1,
output reg s_p_flag_out
);
reg [33:0] R0;
reg [33:0] R1;
reg [33:0] R2;
reg [33:0] R3;
reg [33:0] R4;
reg [33:0] R5;
reg [33:0] R6;
reg [33:0] R7;
reg [33:0] R8;
reg [33:0] R9;
reg [33:0] R10;
reg [33:0] R11;
reg [33:0] R12;
reg [33:0] R13;
reg [33:0] R14;
reg [33:0] R15;
reg [ 3:0] counter;
reg s_p_flag_mux;
// This always part controls signal counter.
always @(posedge clk or negedge rst_n) begin
if (!rst_n) counter <= 4'b0;
else if (counter == 4'b1111) counter <= 4'b0;
else counter <= counter + 4'b0001;
end
// This always part controls signal s_p_flag_out.
always @(posedge clk or negedge rst_n) begin
if (!rst_n) s_p_flag_out <= 0;
else if (counter == 4'b1100) s_p_flag_out <= 1'b1;
else s_p_flag_out <= 1'b0;
end
// This always part controls signal s_p_flag_mux.
always @(posedge clk or negedge rst_n) begin
if (!rst_n) s_p_flag_mux <= 0;
else begin
case (counter)
4'b0000: s_p_flag_mux <= 1'b1;
4'b1101: s_p_flag_mux <= 1'b1;
4'b1110: s_p_flag_mux <= 1'b1;
4'b1111: s_p_flag_mux <= 1'b1;
default: s_p_flag_mux <= 1'b0;
endcase
end
end
// This always part controls signal data_in_1.
always @(posedge clk or negedge rst_n) begin
case (counter)
4'b0000: data_out_1 = {R15, R11, R7, R3};
4'b1101: data_out_1 = {R12, R8, R4, R0};
4'b1110: data_out_1 = {R13, R9, R5, R1};
4'b1111: data_out_1 = {R14, R10, R6, R2};
endcase
end
// This always part controls register.
always @(posedge clk or negedge rst_n) begin
case (counter)
4'b0000: R0 <= data_in_1;
4'b0001: R1 <= data_in_1;
4'b0010: R2 <= data_in_1;
4'b0011: R3 <= data_in_1;
4'b0100: R4 <= data_in_1;
4'b0101: R5 <= data_in_1;
4'b0110: R6 <= data_in_1;
4'b0111: R7 <= data_in_1;
4'b1000: R8 <= data_in_1;
4'b1001: R9 <= data_in_1;
4'b1010: R10 <= data_in_1;
4'b1011: R11 <= data_in_1;
4'b1100: R12 <= data_in_1;
4'b1101: R13 <= data_in_1;
4'b1110: R14 <= data_in_1;
4'b1111: R15 <= data_in_1;
endcase
end
endmodule
| 7.481532 |
modules
module s_reg (clk,
reset,
datai,
datao,
load,
up,
cnt_enb);
input clk; // we use the IEEE standard 1164 logic types. + and - operators
input reset;
input [7:0] datai; // data bus in
output [7:0] datao; // data bus out
input load; // load enable
input up; // 1=count up, 0=down
input cnt_enb;
wire [7:0] datao;
// count enable
reg [7:0] dataol; // local version
// ------------------Architecture synth-----------
// be sure to include the following synopsys command in your synthesis script
// compile_preserve_sync_resets="true"
assign datao = dataol;
// drive the port
always @(posedge clk)
begin
if (reset == 1'b 1)
begin
dataol <= 8'b 00000000;
end
else if (load == 1'b 1 )
begin
dataol <= datai;
end
else if (cnt_enb == 1'b 1 & up == 1'b 1 )
begin
dataol <= dataol + 1;
end
else if (cnt_enb == 1'b 1 & up == 1'b 0 )
begin
dataol <= dataol - 1;
end
else
begin
dataol <= dataol;
end
end
endmodule
| 6.749981 |
module tb ();
parameter WIDTH_KEY = 256;
parameter WIDTH_DATA = 128;
// clock generator settings:
parameter cycles_reset = 2; // rst active (clk)
parameter clk_period = 10; // clk period ns
parameter clk_delay = 0; // clk initial delay
reg clk; // clock
reg rst; // sync reset
reg [WIDTH_KEY-1:0] key; // cipher key input
reg [WIDTH_DATA-1:0] pdata; // plain text input
reg [WIDTH_DATA-1:0] cdata; // cipher text output
reg [WIDTH_DATA-1:0] pdata_d; // plain text input
wire [WIDTH_DATA-1:0] cdata_d; // cipher text output
reg [WIDTH_DATA-1:0] reference_data; // reference data for verify
wire EQUAL = (cdata == reference_data);
wire [8*4-1:0] STATUS = EQUAL ? "OK" : "FAIL";
reg [24:0] clk_counter; // just clock counter for debug
reg [WIDTH_DATA-1:0] DATA[0:3];
assign DATA[0] = 128'hffeeddccbbaa99881122334455667700;
assign DATA[1] = 128'hb66cd8887d38e8d77765aeea0c9a7efc;
assign DATA[2] = 128'h559d8dd7bd06cbfe7e7b262523280d39;
assign DATA[3] = 128'h0c3322fed531e4630d80ef5c5a81c50b;
reg [WIDTH_DATA-1:0] REFERENCE[0:3];
assign REFERENCE[0] = 128'hb66cd8887d38e8d77765aeea0c9a7efc;
assign REFERENCE[1] = 128'h559d8dd7bd06cbfe7e7b262523280d39;
assign REFERENCE[2] = 128'h0c3322fed531e4630d80ef5c5a81c50b;
assign REFERENCE[3] = 128'h23ae65633f842d29c5df529c13f5acda;
/*
S(128'hffeeddccbbaa99881122334455667700) = 128'hb66cd8887d38e8d77765aeea0c9a7efc
S(128'hb66cd8887d38e8d77765aeea0c9a7efc) = 128'h559d8dd7bd06cbfe7e7b262523280d39
S(128'h559d8dd7bd06cbfe7e7b262523280d39) = 128'h0c3322fed531e4630d80ef5c5a81c50b
S(128'h0c3322fed531e4630d80ef5c5a81c50b) = 128'h23ae65633f842d29c5df529c13f5acda
*/
// Clock generation
always begin
#(clk_delay);
forever #(clk_period / 2) clk = ~clk;
end
always begin
@(posedge clk);
clk_counter <= clk_counter + 1;
end // always
reg [7:0] k;
// Initial statement
initial begin
#0 clk = 1'b0;
clk_counter = 0;
for (k = 0; k < 4; k = k + 1) begin
@(posedge clk) reference_data = REFERENCE[k];
pdata = DATA[k];
cdata = Sbox(pdata);
#1 $display("IN: %H \t REFOUT: %H \t OUT: %H ---> %s", pdata, reference_data, cdata, STATUS);
end
$finish;
end
/*
// ======= Sbox(x) =======
function [127:0] Sbox( input [127:0] x );
logic [7:0] K [0:15];
integer j;
localparam W = 8;
begin
//generate
for (j=0;j<16;j=j+1) begin
K[j] = PI(x[W*j+W-1:W*j]);
Sbox[W*(j+1)-1:W*j] = K[j];
end
//endgenerate
end
endfunction
*/
// ======= Sbox(x) =======
function [127:0] Sbox(input [127:0] x);
logic [7:0] K[0:15];
begin
K[0] = PI(x[7:0]);
K[1] = PI(x[15:8]);
K[2] = PI(x[23:16]);
K[3] = PI(x[31:24]);
K[4] = PI(x[39:32]);
K[5] = PI(x[47:40]);
K[6] = PI(x[55:48]);
K[7] = PI(x[63:56]);
K[8] = PI(x[71:64]);
K[9] = PI(x[79:72]);
K[10] = PI(x[87:80]);
K[11] = PI(x[95:88]);
K[12] = PI(x[103:96]);
K[13] = PI(x[111:104]);
K[14] = PI(x[119:112]);
K[15] = PI(x[127:120]);
Sbox = {
K[15],
K[14],
K[13],
K[12],
K[11],
K[10],
K[9],
K[8],
K[7],
K[6],
K[5],
K[4],
K[3],
K[2],
K[1],
K[0]
};
end
endfunction
/*
/////////////// dumping
initial
begin
$dumpfile("S_stage.vcd");
$dumpvars(0,tb);
end
*/
endmodule
| 7.147559 |
module S_SUBT #(
P = 8,
W = 5
) //RESTADOR EXPONENTE FORMATO PUNTO FLOTANTE EN 32 BITS
(
input wire [P-1:0] A, //ENTRADA A
input wire [W-1:0] B, //ENTRADA B
output wire [P-1:0] Y //SALIDA Y
);
assign Y = A - B; //RESTA DE ENTRADAS
endmodule
| 7.016327 |
module s_table_ROM (
input clk,
input rd,
input [7:0] address,
output [7:0] sub_val
);
parameter ROM_WIDTH = 8;
parameter ROM_ADDR_BITS = 8;
(* rom_style="{distributed | block}" *)
reg [ROM_WIDTH-1:0] substitution_table[(2**ROM_ADDR_BITS)-1:0];
reg [ROM_WIDTH-1:0] s_value;
wire [ROM_ADDR_BITS-1:0] rom_address = address;
assign sub_val = s_value;
initial
$readmemh(
"C:/Users/19259/Documents/AES_256/substitution_table.txt",
substitution_table,
0,
(2 ** ROM_ADDR_BITS) - 1
);
always @(posedge clk) if (rd) s_value <= substitution_table[rom_address];
endmodule
| 7.092453 |
module s_to_p_tb ();
// Tak
localparam IN_WIDTH = 8;
localparam OUT_WIDTH = 4;
reg clk;
reg rst;
reg [IN_WIDTH-1:0] i_data;
reg i_valid;
wire i_ready;
wire [IWIDTH*OWIDTH-1:0] o_data;
wire o_valid;
reg o_ready;
s_to_p uut (
.clk (clk),
.rst (rst),
.i_data (i_data),
.i_valid(i_valid),
.i_ready(i_ready),
.o_data (o_data),
.o_valid(o_valid),
.o_ready(o_ready)
);
reg [IN_WIDTH-1:0] good_in_data[4] = {8'hDE, 8'hAD, 8'hBE, 8'hEF};
reg [3:0] cntr;
initial begin
clk = 0;
rst = 1;
cntr = 0;
end
always #5 clk = !clk;
always @(posedge clk) begin
if (rst) rst <= 0;
end
endmodule
| 7.148499 |
module converts the input, represented in sign-magnitude format, to two's complement format.
For example: input = 100110
the first bit of the input being one indicates that it is a negative number.
the output in this case will be the negative(two's complement) of 000110 (absolute value of input) which is 111010.
output= 111010
--------------------------------------------------------------------------------*/
module S_to_T #(
parameter DATA_WIDTH = 5
)
//port declarations
(
//input port
input wire [DATA_WIDTH - 1 : 0] inp,
//output port
output wire [DATA_WIDTH - 1 : 0] out
);
//register to store values assigned in the procedural block
reg [DATA_WIDTH - 1 : 0] x;
//procedural block
always @* begin
if (inp[DATA_WIDTH-1] == 1'b1) //if number is negative:
x = -inp[DATA_WIDTH-2:0]; //two's complement of all the bits except the sign bit
else
x = inp; //representation of a positive number is same in both formats
end
assign out = x; //outputs the value stored in register x
endmodule
| 6.747013 |
module S_transmit (
input CLOCK,
input [2:0] color,
output reg O_TX_SERIAL
);
// input [7:0]TX_BYTE removed for now may be added later
// Time period 20ns freq = 50MHz
parameter clks_per_bit = 434;
parameter IDLE = 3'b000;
parameter TX_START_BIT = 3'B001;
parameter TX_DATA_BITS = 3'b011;
parameter TX_STOP_BIT = 3'b100;
parameter HASH = 8'b00100011;
parameter DASH = 8'b00101101;
parameter CHARS = 8'b01010011;
parameter CHARI = 8'b01001001;
parameter CHARF = 8'b01000110;
parameter CHARC = 8'b01000011;
parameter CHART = 8'b01010100;
parameter CHARW = 8'b01010111;
parameter CHARN = 8'b01001110;
parameter CHARO = 8'b01001111;
parameter CHARD = 8'b01000100;
parameter CHARE = 8'b01000101;
parameter ZERO = 8'b00110000;
reg TX_DATA_VALID = 1; //inputs
reg [3:0] next_limit = 9;
reg [3:0] next = 0;
reg [2:0] r_state = IDLE;
reg [8:0] r_clock_count = 0;
reg [2:0] r_bit_index = 0;
reg [7:0] r_data_bits = 0;
reg r_TX_DONE = 0;
always @(posedge CLOCK) begin
case (r_state)
IDLE: begin
r_clock_count <= 0;
r_bit_index <= 0;
O_TX_SERIAL <= 1'b1;
r_TX_DONE <= 1'b1;
if (TX_DATA_VALID & next < next_limit) begin
if (color != 3'b000) r_state <= TX_START_BIT;
else r_state <= IDLE;
end else r_state <= IDLE;
end
TX_START_BIT: begin
O_TX_SERIAL <= 0;
r_TX_DONE <= 0;
if (r_clock_count < clks_per_bit - 1) begin
r_clock_count <= r_clock_count + 1'b1;
r_state <= TX_START_BIT;
end else begin
r_clock_count <= 0;
r_state <= TX_DATA_BITS;
if (next == 0) r_data_bits <= CHARS;
else if (next == 1) r_data_bits <= CHARI;
else if (next == 2) r_data_bits <= DASH;
else if (next == 3) r_data_bits <= CHARW;
else if (next == 4) r_data_bits <= DASH;
else if (next == 5) begin
if (color == 1) r_data_bits <= CHARF;
else if (color == 2) r_data_bits <= CHARC;
else r_data_bits <= CHARC;
end else if (next == 6) begin
if (color == 1) r_data_bits <= CHARI;
else if (color == 2) r_data_bits <= CHART;
else r_data_bits <= CHARS;
end else if (next == 7) r_data_bits <= DASH;
else if (next == 8) r_data_bits <= HASH;
else r_data_bits <= 0;
end
end
TX_DATA_BITS: begin
O_TX_SERIAL <= r_data_bits[r_bit_index];
if (r_clock_count < clks_per_bit - 1) begin
r_clock_count <= r_clock_count + 1'b1;
r_state <= TX_DATA_BITS;
end else begin
if (r_bit_index == 7) begin
r_clock_count <= 0;
r_state <= TX_STOP_BIT;
end else begin
r_clock_count <= 0;
r_state <= TX_DATA_BITS;
r_bit_index <= r_bit_index + 1'b1;
end
end
end
TX_STOP_BIT: begin
O_TX_SERIAL <= 1;
r_TX_DONE <= 1;
if (r_clock_count < clks_per_bit - 1) begin
r_clock_count <= r_clock_count + 1'b1;
r_state <= TX_STOP_BIT;
end else begin
r_state <= IDLE;
next <= next + 1'b1;
end
end
default: begin
r_state <= IDLE;
end
endcase
end
endmodule
| 7.734834 |
module S_Trigger (
input nReset,
input Clk, // 45 MHz
input [15:0] Input,
output Output,
input [15:0] Level,
input [15:0] Hyst,
input Slope
); // 1 = Positive , 0 = Negative
reg tOutput;
wire [17:0] x2;
wire [17:0] x3;
wire [18:0] x4;
wire [17:0] x5;
wire [17:0] x6;
wire [17:0] x7;
wire [17:0] x8;
wire [17:0] x9;
wire [17:0] x10;
wire Top;
wire Bottom;
assign x2 = {Input[15], Input[15], Input};
assign x3 = {Level[15], Level[15], Level};
assign x4 = {3'b000, Hyst};
assign x5 = x3 + x4[18:1] + x4[0];
assign x6 = -x5;
assign x7 = x3 - x4[18:1];
assign x8 = -x7;
assign x9 = x2 + x6;
assign x10 = x2 + x8;
assign Top = x9[17];
assign Bottom = x10[17];
always @(negedge nReset, posedge Clk) begin
if (!nReset) begin
tOutput <= 1'b1;
end else begin
if (tOutput) begin
tOutput <= Top;
end else begin
tOutput <= Bottom;
end
end
end
assign Output = tOutput ^ Slope;
endmodule
| 7.275886 |
module TXctl0 ( /* in */
RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5,
SCLKg6,
SP_EN,
SP_ENg,
TFSsm,
TSack,
Twrap,
SLEN,
MWORD,
TBUF,
logTX,
MTTX_E,
DMD,
AUlaw_en,
SLEN_ex,
FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD,
TSreq,
IST,
TX,
SLOT_NUM
);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [4:0] SLEN;
input [15:0] MWORD;
input [7:0] logTX;
input [15:0] DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5, SCLKg6,
SP_EN,
SP_ENg,
SLEN_ex,
TFSsm,
TSack,
Twrap,
TBUF,
MTTX_E,
AUlaw_en;
input FSi_set;
output [15:0] TX;
output TD, TSreq, IST;
output [3:0] SLOT_NUM;
reg [15:0] TX, TXSHT;
reg [2:0] TCS, TNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg b_sync1, c_sync1, c_sync2, ldTX_cmp, TSreqi, TSreq, ISTai;
reg TAG_SLOT;
wire [15:0] TX_di, TXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire rawTX_we, TX_we, ISTa, sTSreq, rTSreq;
parameter TX_idle = 3'b001, TX_shift = 3'b010, TX_wstart = 3'b100;
always @(TCS or TFSsm or Bcnteq0 or Wcnteq0) begin
case (TCS)
TX_idle: TNS <= #`da TFSsm ? TX_shift : TX_idle;
TX_shift: begin
if (Bcnteq0) TNS <= #`da Wcnteq0 ? TX_idle : TX_wstart;
else TNS <= #`da TX_shift;
end
TX_wstart: TNS <= #`da TX_shift;
default: TNS <= #`da TX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_ENg_h = !SP_ENg;
wire rst_SP_ENg = SCAN_TEST ? RST : rst_SP_ENg_h;
`else
wire rst_SP_ENg = !SP_ENg;
`endif
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) TCS <= #`db 3'b001;
else TCS <= #`db TNS;
end
assign #`da ldBcnt = TNS[0] || TNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg5) TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = TNS[0];
assign #`da Wcnt_dn = TNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
assign #`da SLOT_NUM[3:0] = Wcnt[3:0];
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
assign #`da TXSHT_di[15:0] = TNS[1] ? {TXSHT[14:0], 1'b0} : TX[15:0];
always @(posedge SCLKg6) TXSHT[15:0] <= #`db TXSHT_di[15:0];
wire [3:0] slen_msb = SLEN[3:0];
assign #`d0 TD = SLEN_ex ? TXSHT[15] : TXSHT[slen_msb];
assign #`da rawTX_we = MTTX_E && EX_en && GO_Cx || TSack;
assign #`da TX_we = rawTX_we || ldTX_cmp;
assign #`da TX_di = ldTX_cmp ? {{8{logTX[7]}}, logTX[7:0]} : DMD[15:0];
always @(posedge DSPCLK) if (TX_we) TX[15:0] <= #`db TX_di;
always @(posedge DSPCLK) begin
b_sync1 <= #`db rawTX_we;
ldTX_cmp <= #`db b_sync1 && AUlaw_en /* && SP_EN*/;
end
Delaya d1 (
TSack,
delTSack
);
reg SP_EN_D1;
wire SP_EN_1T;
always @(posedge DSPCLK) SP_EN_D1 <= #`db SP_EN;
assign #`da SP_EN_1T = SP_EN && !SP_EN_D1;
`ifdef FD_DFT
wire rTSreq_h = (RST || delTSack);
assign rTSreq = SCAN_TEST ? RST : rTSreq_h;
`else
assign #`da rTSreq = RST || delTSack;
`endif
assign #`da sTSreq = SP_ENg && TBUF && !TCS[1] && TNS[1];
always @(posedge SCLKg5 or posedge rTSreq) begin
if (rTSreq) TSreqi <= #`db 1'b0;
else if (sTSreq) TSreqi <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge rTSreq) begin
if (rTSreq) TSreq <= #`db 1'b0;
else TSreq <= #`db TSreqi || (SP_EN_1T && MWORD[14]);
end
always @(posedge SCLKg5 or posedge RST)
if (RST) ISTai <= #`db 1'b0;
else ISTai <= #`db SP_ENg && (!TCS[1] && TNS[1]);
always @(posedge DSPCLK) begin
c_sync1 <= #`db ISTai;
c_sync2 <= #`db c_sync1;
end
assign #`da ISTa = c_sync1 && !c_sync2;
assign #`da IST = TBUF ? Twrap : ISTa;
endmodule
| 6.623283 |
module TXctl1 ( /* in */
RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5,
SCLKg6,
SP_EN,
SP_ENg,
TFSsm,
TSack,
Twrap,
SLEN,
MWORD,
TBUF,
SLEN_ex,
FSi_set,
/*logTX,*/ MTTX_E,
DMD,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD,
TSreq,
IST,
TX,
SLOT_NUM
);
`ifdef FD_DFT
input SCAN_TEST;
`endif
input [4:0] SLEN;
input [15:0] MWORD;
input [15:0] DMD;
input RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5, SCLKg6,
SP_EN,
SP_ENg,
SLEN_ex,
TFSsm,
TSack,
Twrap,
TBUF,
MTTX_E;
input FSi_set;
output [15:0] TX;
output TD, TSreq, IST;
output [3:0] SLOT_NUM;
reg [15:0] TX, TXSHT;
reg [2:0] TCS, TNS;
reg [4:0] Bcnt;
reg [7:0] Wcnt;
reg b_sync1, c_sync1, c_sync2, ldTX_cmp, TSreqi, TSreq, ISTai;
reg TAG_SLOT;
wire [15:0] TX_di, TXSHT_di;
wire ldBcnt, ldWcnt, Bcnteq0, Wcnteq0, Wcnt_dn;
wire rawTX_we, TX_we, ISTa, sTSreq, rTSreq;
parameter TX_idle = 3'b001, TX_shift = 3'b010, TX_wstart = 3'b100;
always @(TCS or TFSsm or Bcnteq0 or Wcnteq0) begin
case (TCS)
TX_idle: TNS <= #`da TFSsm ? TX_shift : TX_idle;
TX_shift: begin
if (Bcnteq0) TNS <= #`da Wcnteq0 ? TX_idle : TX_wstart;
else TNS <= #`da TX_shift;
end
TX_wstart: TNS <= #`da TX_shift;
default: TNS <= #`da TX_idle;
endcase
end
`ifdef FD_DFT
wire rst_SP_ENg_h = !SP_ENg && !SCAN_TEST;
wire rst_SP_ENg = SCAN_TEST ? RST : rst_SP_ENg_h;
`else
wire rst_SP_ENg = !SP_ENg;
`endif
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) TCS <= #`db 3'b001;
else TCS <= #`db TNS;
end
assign #`da ldBcnt = TNS[0] || TNS[2];
assign #`da Bcnteq0 = !(|Bcnt[4:0]);
always @(posedge SCLKg5) TAG_SLOT <= #`db MWORD[14] && FSi_set;
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Bcnt[4:0] <= #`db 5'b0;
else if (TAG_SLOT) Bcnt[4:0] <= #`db 5'hf;
else if (ldBcnt) Bcnt[4:0] <= #`db SLEN[4:0];
else Bcnt[4:0] <= #`db Bcnt[4:0] - 1;
end
assign #`da ldWcnt = TNS[0];
assign #`da Wcnt_dn = TNS[2];
assign #`da Wcnteq0 = !(|Wcnt[7:0]);
assign #`da SLOT_NUM[3:0] = Wcnt[3:0];
always @(posedge SCLKg5 or posedge rst_SP_ENg) begin
if (rst_SP_ENg) Wcnt[7:0] <= #`db 8'b0;
else if (ldWcnt) Wcnt[7:0] <= #`db MWORD[7:0];
else if (Wcnt_dn) Wcnt[7:0] <= #`db Wcnt[7:0] - 1;
end
assign #`da TXSHT_di[15:0] = TNS[1] ? {TXSHT[14:0], 1'b0} : TX[15:0];
always @(posedge SCLKg6) TXSHT[15:0] <= #`db TXSHT_di[15:0];
wire [3:0] slen_msb = SLEN[3:0];
assign #`d0 TD = SLEN_ex ? TXSHT[15] : TXSHT[slen_msb];
assign #`da rawTX_we = MTTX_E && EX_en && GO_Cx || TSack;
assign #`da TX_we = rawTX_we;
assign #`da TX_di = DMD[15:0];
always @(posedge DSPCLK) if (TX_we) TX[15:0] <= #`db TX_di;
Delaya d1 (
TSack,
delTSack
);
reg SP_EN_D1;
wire SP_EN_1T;
always @(posedge DSPCLK) SP_EN_D1 <= #`db SP_EN;
assign #`da SP_EN_1T = SP_EN && !SP_EN_D1;
`ifdef FD_DFT
wire rTSreq_h = (RST || delTSack);
assign rTSreq = SCAN_TEST ? RST : rTSreq_h;
`else
assign #`da rTSreq = RST || delTSack;
`endif
assign #`da sTSreq = SP_ENg && TBUF && !TCS[1] && TNS[1];
always @(posedge SCLKg5 or posedge rTSreq) begin
if (rTSreq) TSreqi <= #`db 1'b0;
else if (sTSreq) TSreqi <= #`db 1'b1;
end
always @(posedge DSPCLK or posedge rTSreq) begin
if (rTSreq) TSreq <= #`db 1'b0;
else TSreq <= #`db TSreqi || SP_EN_1T && MWORD[14];
end
always @(posedge SCLKg5 or posedge RST)
if (RST) ISTai <= #`db 1'b0;
else ISTai <= #`db SP_ENg && (!TCS[1] && TNS[1]);
always @(posedge DSPCLK) begin
c_sync1 <= #`db ISTai;
c_sync2 <= #`db c_sync1;
end
assign #`da ISTa = c_sync1 && !c_sync2;
assign #`da IST = TBUF ? Twrap : ISTa;
endmodule
| 6.562916 |
module
module S_type(
input [31:0] instr,
input [31:0] daddr,
output reg[3:0] we
);
always@(instr or daddr)
begin
case(instr[14:12])
3'b000: we = (4'b0001)<<daddr[1:0]; //SB
3'b001: we = (4'b0011)<<daddr[1:0]; //SH
3'b010: we = 4'b1111; //SW
endcase
end
endmodule
| 6.806973 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
module s_uart_tx(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 10000000;
parameter Baud = 500000;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
| 6.83375 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 10000000;
parameter Baud = 500000;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module s_up_counter (
L,
clk
);
input clk;
output [3:0] L;
wire qbar;
JK_FF ff1 (
1,
1,
L[0],
qbar,
clk
);
JK_FF ff2 (
L[0],
L[0],
L[1],
qbar,
clk
);
JK_FF ff3 (
L[0] & L[1],
L[0] & L[1],
L[2],
qbar,
clk
);
JK_FF ff4 (
L[0] & L[1] & L[2],
L[0] & L[1] & L[2],
L[3],
qbar,
clk
);
endmodule
| 6.748693 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end else if (J == 0 & K == 1) begin
Q <= 0;
NQ <= 1;
end else begin
Q <= ~Q;
NQ <= ~NQ;
end
end
endmodule
| 6.615218 |
module
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wire [6:0] HEX4,
output wire [6:0] HEX5,
output wire [9:0] LEDR, // LEDs
output wire [7:0] x, // VGA pixel coordinates
output wire [6:0] y,
output wire [2:0] colour, // VGA pixel colour (0-7)
output wire plot, // Pixel drawn when this is pulsed
output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
);
top v1(SW, LEDR);
endmodule
| 9.001229 |
module top (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
t_flipflop u1 (
SW[0],
SW[1],
SW[9],
LEDR[0]
);
endmodule
| 6.514573 |
module t (
output reg Q,
input T,
clk
);
wire DT = Q ^ T;
dff d (
T,
clk,
DT
);
endmodule
| 6.866031 |
module tbox0 (
input [7:0] index,
output [31:0] tbox
);
reg [7:0] mem[0:255];
wire [7:0] sbox;
wire [7:0] galois;
initial begin
$readmemh("T0.hex", mem);
end
assign sbox = mem[index];
assign galois = {sbox[6:0], 1'b0} ^ (sbox[7] ? 8'h1b : 8'h00);
assign tbox = {galois ^ sbox, sbox, sbox, galois};
endmodule
| 6.520176 |
module setbit (
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
wire LED1;
wire LED2;
wire LED3;
wire LED4;
wire LED5;
wire LED6;
wire LED7;
wire LED8;
//-- Implementacion: el pin deseado esta cableado a '1'
// los demas estan cableados a '0'
assign LED1 = 1;
assign LED2 = 0;
assign LED3 = 0;
assign LED4 = 0;
assign LED5 = 0;
assign LED6 = 0;
assign LED7 = 0;
assign LED8 = 0;
endmodule
| 8.044466 |
module setbit_tb;
//-- Cable para conectar al componente que pone
//-- el bit a uno
wire LED1;
//--Instanciar el componente. Conectado al cable A
setbit SB1 (.LED1(LED1));
//-- Comenzamos las pruebas
initial begin
//-- Definir el fichero donde volvar los datos
//-- para ver graficamente la salida
$dumpfile("T01-setbit_tb.vcd");
//-- Volcar todos los datos a ese fichero
$dumpvars(0, setbit_tb);
//-- Pasadas 10 unidades de tiempo comprobamos
//-- si el cable esta a 1
//-- En caso de no estar a 1, se informa del problema, pero la
//-- simulacion no se detiene
#10
if (LED1 != 1) $display("---->¡ERROR! Salida no esta a 1");
else $display("Componente ok!");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
#10 $finish;
end
endmodule
| 7.100034 |
module coeff_rom (
input clk,
input rstn,
input [13:0] aa,
input cena,
output reg [`W_WT1P*4-1:0] qa
);
logic [0:`TILE_WIDTH*`TILE_WIDTH-1][31:0] mem = {
256,
-896,
-4096,
-640,
832,
3200,
3328,
-1344,
576,
2624,
1600,
-2752,
4416,
-1408,
2176,
-3584,
0,
832,
256,
-5504,
6720,
-9344,
-1984,
-1792,
-2560,
2432,
6144,
1344,
-960,
5184,
1472,
1024,
-2880,
1600,
-1024,
-1280,
3008,
-2304,
-960,
-1984,
4672,
320,
5504,
704,
-3904,
4800,
1792,
-448,
-4160,
-1856,
-2048,
-512,
256,
-3520,
-3392,
1408,
-2176,
64,
1280,
1920,
-3392,
-2752,
-1408,
-1728,
1984,
5760,
5760,
-2304,
1600,
-1728,
-1920,
3456,
-7104,
-3968,
-2688,
1728,
1856,
128,
5632,
-1920,
-2176,
-6208,
448,
384,
-2240,
3392,
-3648,
-9024,
7104,
6528,
2560,
6592,
-832,
-4672,
-4224,
7552,
-12416,
320,
-1088,
-3904,
6272,
7744,
4800,
6464,
1792,
256,
-4224,
-896,
4480,
1344,
7040,
-5696,
2560,
-960,
2112,
1088,
2304,
-1280,
832,
-704,
-9152,
-4800,
-4928,
2304,
-704,
7936,
1408,
2688,
11072,
3520,
-5440,
3904,
-7616,
3264,
4032,
-7296,
2368,
-8768,
-3136,
10112,
-4096,
192,
3840,
2048,
2560,
-7168,
2048,
384,
5888,
-5312,
7552,
4736,
-4032,
-5504,
-6592,
-4736,
8896,
3840,
-5824,
2240,
-1472,
-192,
-320,
896,
1728,
-4608,
-1856,
4288,
1024,
-1792,
4992,
-7552,
-2752,
-6464,
-4288,
1664,
2304,
-2368,
-4992,
-6912,
4992,
9536,
-4352,
7360,
-4160,
-2240,
-512,
-11200,
256,
2048,
-3264,
6912,
7488,
-8064,
-512,
-1280,
1920,
-6528,
-5248,
-640,
-5184,
448,
12992,
192,
-4224,
64,
-10624,
-3776,
9920,
4736,
3456,
-7360,
2752,
6016,
-256,
-9536,
768,
14144,
2176,
2880,
-4288,
13056,
-5952,
-2944,
1984,
9280,
11904,
-1856,
-11584,
6272,
-2688,
-13760,
14464,
8704,
13504,
3968,
-960,
9664,
832,
-12928,
9600,
2816,
8384,
-7552,
-7232,
8832,
-4352,
-13888,
6784,
14144,
10048,
3136,
4544,
2688,
13888,
3776
};
logic [0:3][0:`TILE_WIDTH/2/4-1][0:`TILE_WIDTH/2-1][0:3][`W_WT1P-1:0] coeff_mem;
logic [0:`TILE_WIDTH*`TILE_WIDTH/4-1][`W_WT1P*4-1:0] coeff_mem_4x;
assign coeff_mem_4x = coeff_mem;
initial begin
for (int cb = 0; cb < 4; cb = cb + 1) begin
for (int h = 0; h < `TILE_WIDTH / 2 / 4; h = h + 1) begin
for (int w = 0; w < `TILE_WIDTH / 2; w = w + 1) begin
coeff_mem[cb][h][w][0] = mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 0 ) + w][31] ? (0 - mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 0 ) + w] /64) | 1<<`W_WT1 : mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 0 ) + w] /64;
coeff_mem[cb][h][w][1] = mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 1 ) + w][31] ? (0 - mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 1 ) + w] /64) | 1<<`W_WT1 : mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 1 ) + w] /64;
coeff_mem[cb][h][w][2] = mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 2 ) + w][31] ? (0 - mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 2 ) + w] /64) | 1<<`W_WT1 : mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 2 ) + w] /64;
coeff_mem[cb][h][w][3] = mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 3 ) + w][31] ? (0 - mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 3 ) + w] /64) | 1<<`W_WT1 : mem[ cb*(`TILE_WIDTH*`TILE_WIDTH)/4 + (`TILE_WIDTH/2)*(h*4 + 3 ) + w] /64;
end
end
end
end
always @(`CLK_RST_EDGE)
if (`RST) qa <= 0;
else if (!cena) qa <= coeff_mem_4x[aa];
endmodule
| 7.054666 |
modules ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////
`include "timescale.v"
module t2600(clk, reset_n);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
localparam [3:0] RIOT_ADDR_SIZE = 4'd7;
localparam [3:0] TIA_ADDR_SIZE = 4'd6;
input clk;
input reset_n;
t6507lp #(DATA_SIZE, ADDR_SIZE) t6507lp (
.clk (clk),
.reset_n (reset_n),
.data_in (data_in),
.rw_mem (rw_mem),
.data_out (data_out),
.address (address)
);
t6532 #(DATA_SIZE, RIOT_ADDR_SIZE) t6532 (
.clk (clk),
.io_lines (io_lines),
.enable (enable),
.address (address),
.data (data)
);
t2600_bus t2600_bus (
.address (address),
.data_from_cpu (data_from_cpu),
.cpu_rw_mem (cpu_rw_mem),
.riot_data (riot_data),
.rom_data (rom_data),
.tia_data (tia_data),
.address_riot (address_riot),
.address_rom (address_rom),
.address_tia (address_tia),
.data_to_cpu (data_to_cpu),
.enable_riot (enable_riot),
.enable_rom (enable_rom),
.enable_tia (enable_tia),
.rw_mem (rw_mem)
);
T2600_KB T2600_KB (
.CLK (clk),
.RST (reset_n),
.io_lines (io_lines),
.KC (kc),
.KD (kd)
);
video video (
);
// VIDEO
endmodule
| 8.868608 |
module t2600_bus (
address,
data_from_cpu,
cpu_rw_mem,
riot_data,
rom_data,
tia_data,
address_riot,
address_rom,
address_tia,
data_to_cpu,
enable_riot,
enable_rom,
enable_tia,
rw_mem
);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
localparam [3:0] RIOT_ADDR_SIZE_ = 4'd6;
localparam [3:0] TIA_ADDR_SIZE_ = 4'd5;
input [ADDR_SIZE_:0] address;
input [DATA_SIZE_:0] data_from_cpu;
input cpu_rw_mem;
inout [DATA_SIZE_:0] riot_data;
inout [DATA_SIZE_:0] rom_data;
inout [DATA_SIZE_:0] tia_data;
output reg [RIOT_ADDR_SIZE_:0] address_riot;
output reg [ADDR_SIZE_:0] address_rom;
output reg [TIA_ADDR_SIZE_:0] address_tia;
output reg [DATA_SIZE_:0] data_to_cpu;
output reg enable_riot;
output reg enable_rom;
output reg enable_tia;
output reg rw_mem;
assign riot_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
assign rom_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
assign tia_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
always @(*) begin
enable_riot = 1'b0;
enable_rom = 1'b0;
enable_tia = 1'b0;
rw_mem = cpu_rw_mem;
address_tia = address[5:0];
address_riot = address[6:0];
address_rom = address;
if (address[12]) begin
data_to_cpu = rom_data;
enable_rom = 1'b1;
end else if (address[7]) begin
data_to_cpu = riot_data;
enable_riot = 1'b1;
end else begin
data_to_cpu = tia_data;
enable_tia = 1'b1;
end
end
endmodule
| 7.133484 |
module t2600_bus_tb ();
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
localparam [3:0] RIOT_ADDR_SIZE_ = 4'd6;
localparam [3:0] TIA_ADDR_SIZE_ = 4'd5;
// these 3 registers are kind of drivers/wrappers for the tristate ones
reg [DATA_SIZE_:0] riot_data_drvr;
reg [DATA_SIZE_:0] rom_data_drvr;
reg [DATA_SIZE_:0] tia_data_drvr;
// list of all the inputs/outputs of the bus controller
reg [ADDR_SIZE_:0] address;
reg [DATA_SIZE_:0] data_from_cpu;
reg cpu_rw_mem;
tri [DATA_SIZE_:0] riot_data = riot_data_drvr;
tri [DATA_SIZE_:0] rom_data = rom_data_drvr;
tri [DATA_SIZE_:0] tia_data = tia_data_drvr;
wire [RIOT_ADDR_SIZE_:0] address_riot;
wire [ADDR_SIZE_:0] address_rom;
wire [TIA_ADDR_SIZE_:0] address_tia;
wire [DATA_SIZE_:0] data_to_cpu;
wire enable_riot;
wire enable_rom;
wire enable_tia;
wire rw_mem;
t2600_bus t2600_bus (
.address(address),
.data_from_cpu(data_from_cpu),
.cpu_rw_mem(cpu_rw_mem),
.riot_data(riot_data),
.rom_data(rom_data),
.tia_data(tia_data),
.address_riot(address_riot),
.address_rom(address_rom),
.address_tia(address_tia),
.data_to_cpu(data_to_cpu),
.enable_riot(enable_riot),
.enable_rom(enable_rom),
.enable_tia(enable_tia),
.rw_mem(rw_mem)
);
always @(*) begin
if (cpu_rw_mem == 1'b1) begin
tia_data_drvr = 8'hZ;
riot_data_drvr = 8'hZ;
rom_data_drvr = 8'hZ;
end
end
// this block is clockless so I cannot use @(negedge clk)
initial begin
address = 13'b0;
data_from_cpu = 8'h01;
cpu_rw_mem = 1'b0; // READ
#10;
address = 13'd8; // this is a TIA adress
#10;
address = 13'd128; // this is a RIOT adress
#10;
address = 13'd4096; // this is a ROM adress
#10;
cpu_rw_mem = 1'b1; // from now on I will be writing
riot_data_drvr = 8'h02;
rom_data_drvr = 8'h03;
tia_data_drvr = 8'h04;
address = 13'd8; // this is a TIA adress
#10;
address = 13'd128; // this is a RIOT adress
#10;
address = 13'd4096; // this is a ROM adress
#10;
$finish();
end
endmodule
| 7.863261 |
module t2600_kb_tb ();
// all inputs are regs
reg clk;
reg reset_n;
reg kd;
reg kc;
// all outputs are wires
wire [15:0] io_lines;
always #10 clk <= ~clk;
initial begin
clk = 1'b0;
reset_n = 1'b1;
kd = 1'b0;
kc = 1'b0;
#10;
reset_n = 1'b0;
#40000;
$finish;
end
always @(clk) begin
kc = $random;
kd = $random;
end
T2600_KB T2600_KB (
.CLK(clk),
.RST(reset_n),
.io_lines(io_lines),
.KC(kc),
.KD(kd)
);
endmodule
| 7.164282 |
module T2D (
input A,
B,
input S2,
output X
);
assign X = S2 ? ~A : ~B; // tmax = 2.7ns
endmodule
| 7.372875 |
module tbox3 (
input [7:0] index,
output [31:0] tbox
);
reg [31:0] mem[0:255];
initial begin
$readmemh("T3.hex", mem);
end
assign tbox = mem[index];
endmodule
| 6.770137 |
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