code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module system_rst_ps7_0_100M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
mb_debug_sys_rst,
ext_reset_in,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input mb_debug_sys_rst;
input ext_reset_in;
input aux_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire [0:0] exr_lpf;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_1_in4_in;
wire p_2_in;
wire p_2_in3_in;
wire p_3_in1_in;
wire p_3_in6_in;
wire slowest_sync_clk;
system_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX (
.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk)
);
system_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT (
.exr_lpf(exr_lpf),
.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_1_in4_in(p_1_in4_in),
.p_2_in3_in(p_2_in3_in),
.scndry_out(p_3_in6_in),
.slowest_sync_clk(slowest_sync_clk)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[1].asr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_in1_in),
.Q (p_2_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[2].asr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_2_in),
.Q (p_1_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[3].asr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_1_in),
.Q (asr_lpf),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[1].exr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_in6_in),
.Q (p_2_in3_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[2].exr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_2_in3_in),
.Q (p_1_in4_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[3].exr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_1_in4_in),
.Q (exr_lpf),
.R (1'b0)
);
(* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF)
) POR_SRL_I (
.A0 (1'b1),
.A1 (1'b1),
.A2 (1'b1),
.A3 (1'b1),
.CE (1'b1),
.CLK(slowest_sync_clk),
.D (1'b0),
.Q (Q)
);
FDRE #(
.INIT(1'b0)
) lpf_asr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q (lpf_asr),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) lpf_exr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q (lpf_exr),
.R (1'b0)
);
LUT4 #(
.INIT(16'hFFFD)
) lpf_int0 (
.I0(dcm_locked),
.I1(lpf_exr),
.I2(lpf_asr),
.I3(Q),
.O (lpf_int0__0)
);
FDRE #(
.INIT(1'b0)
) lpf_int_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (lpf_int0__0),
.Q (lpf_int),
.R (1'b0)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_100M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0] bus_struct_reset;
output [0:0] peripheral_reset;
output [0:0] interconnect_aresetn;
output [0:0] peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_3),
.Q (interconnect_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_4),
.Q (peripheral_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \BSR_OUT_DFF[0].FDRE_BSR (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Bsr_out),
.Q (bus_struct_reset),
.R (1'b0)
);
system_rst_ps7_0_100M_0_lpf EXT_LPF (
.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) FDRE_inst (
.C (slowest_sync_clk),
.CE(1'b1),
.D (MB_out),
.Q (mb_reset),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \PR_OUT_DFF[0].FDRE_PER (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Pr_out),
.Q (peripheral_reset),
.R (1'b0)
);
system_rst_ps7_0_100M_0_sequence_psr SEQ (
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.bsr_reg_0(SEQ_n_3),
.lpf_int(lpf_int),
.pr_reg_0(SEQ_n_4),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_100M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_rst_ps7_0_100M_0_proc_sys_reset U0 (
.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_100M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1)
) \q_int[0]_i_1 (
.I0(Q[0]),
.O (q_int0[0])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6)
) \q_int[1]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.O (q_int0[1])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78)
) \q_int[2]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O (q_int0[2])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80)
) \q_int[3]_i_1 (
.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O (q_int0[3])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \q_int[4]_i_1 (
.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O (q_int0[4])
);
LUT1 #(
.INIT(2'h1)
) \q_int[5]_i_1 (
.I0(seq_clr),
.O (clear)
);
LUT6 #(
.INIT(64'h7FFFFFFF80000000)
) \q_int[5]_i_2 (
.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O (q_int0[5])
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[0] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[0]),
.Q (Q[0]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[1] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[1]),
.Q (Q[1]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[2] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[2]),
.Q (Q[2]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[3] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[3]),
.Q (Q[3]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[4] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[4]),
.Q (Q[4]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[5] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[5]),
.Q (Q[5]),
.R (clear)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_rst_ps7_0_50M_0_proc_sys_reset U0 (
.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (asr_d1),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT1 #(
.INIT(2'h1)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 (
.I0(aux_reset_in),
.O (asr_d1)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_asr_i_1 (
.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O (lpf_asr_reg)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0] p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT2 #(
.INIT(4'hB)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 (
.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 )
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_exr_i_1 (
.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O (lpf_exr_reg)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0] p_3_out;
wire slowest_sync_clk;
system_rst_ps7_0_50M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX (
.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk)
);
system_rst_ps7_0_50M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT (
.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[1].asr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_in1_in),
.Q (p_2_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[2].asr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_2_in),
.Q (p_1_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[3].asr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_1_in),
.Q (asr_lpf),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[1].exr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[3]),
.Q (p_3_out[2]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[2].exr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[2]),
.Q (p_3_out[1]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[3].exr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[1]),
.Q (p_3_out[0]),
.R (1'b0)
);
(* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF)
) POR_SRL_I (
.A0 (1'b1),
.A1 (1'b1),
.A2 (1'b1),
.A3 (1'b1),
.CE (1'b1),
.CLK(slowest_sync_clk),
.D (1'b0),
.Q (Q)
);
FDRE #(
.INIT(1'b0)
) lpf_asr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q (lpf_asr),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) lpf_exr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q (lpf_exr),
.R (1'b0)
);
LUT4 #(
.INIT(16'hFFEF)
) lpf_int0 (
.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O (lpf_int0__0)
);
FDRE #(
.INIT(1'b0)
) lpf_int_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (lpf_int0__0),
.Q (lpf_int),
.R (1'b0)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0] bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0] interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_3),
.Q (interconnect_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_4),
.Q (peripheral_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \BSR_OUT_DFF[0].FDRE_BSR (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Bsr_out),
.Q (bus_struct_reset),
.R (1'b0)
);
system_rst_ps7_0_50M_0_lpf EXT_LPF (
.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) FDRE_inst (
.C (slowest_sync_clk),
.CE(1'b1),
.D (MB_out),
.Q (mb_reset),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \PR_OUT_DFF[0].FDRE_PER (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Pr_out),
.Q (peripheral_reset),
.R (1'b0)
);
system_rst_ps7_0_50M_0_sequence_psr SEQ (
.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1)
) \q_int[0]_i_1 (
.I0(Q[0]),
.O (q_int0[0])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6)
) \q_int[1]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.O (q_int0[1])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78)
) \q_int[2]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O (q_int0[2])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80)
) \q_int[3]_i_1 (
.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O (q_int0[3])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \q_int[4]_i_1 (
.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O (q_int0[4])
);
LUT1 #(
.INIT(2'h1)
) \q_int[5]_i_1 (
.I0(seq_clr),
.O (clear)
);
LUT6 #(
.INIT(64'h7FFFFFFF80000000)
) \q_int[5]_i_2 (
.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O (q_int0[5])
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[0] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[0]),
.Q (Q[0]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[1] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[1]),
.Q (Q[1]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[2] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[2]),
.Q (Q[2]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[3] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[3]),
.Q (Q[3]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[4] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[4]),
.Q (Q[4]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[5] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[5]),
.Q (Q[5]),
.R (clear)
);
endmodule
| 7.106127 |
module system_sim;
reg clk = 0;
reg reset = 1;
//----------------------------------------------------------------------------
// Memory-Tester System
//----------------------------------------------------------------------------
system dut (
.clk (clk),
.reset(reset)
);
//----------------------------------------------------------------------------
// Clock Generation (50 MHZ)
//----------------------------------------------------------------------------
initial clk <= 1'b0;
always #10 clk <= ~clk;
//----------------------------------------------------------------------------
// Reset Generation
//----------------------------------------------------------------------------
initial begin
$dumpfile("system_sim.vcd");
$dumpvars;
#0 reset <= 1'b1;
#80 reset <= 1'b0;
// #10000000000 $finish;
end
endmodule
| 6.837305 |
module system_testbench ();
// DUT I/O
reg system_clock = 0;
reg [7:0] gpio_switches = 0;
reg [4:0] gpio_buttons = 0;
wire [7:0] gpio_leds;
reg cpu_reset_b = 0;
reg rotary_A, rotary_B, rotary_push = 0;
wire led_c, led_n, led_e, led_w, led_s;
wire piezo_out;
wire fpga_serial_rx, fpga_serial_tx;
ml505top #(
// We are going to override debouncer parameters just to make the testbench faster
// Now we can saturate a debouncer in 1 clock cycle
.B_SAMPLE_COUNT_MAX(1),
.B_PULSE_COUNT_MAX (1),
.R_SAMPLE_COUNT_MAX(1),
.R_PULSE_COUNT_MAX (1)
) DUT (
.CLK_33MHZ_FPGA(system_clock),
.GPIO_DIP(gpio_switches),
.FPGA_ROTARY_INCA(rotary_A),
.FPGA_ROTARY_INCB(rotary_B),
.FPGA_ROTARY_PUSH(rotary_push),
.GPIO_BUTTONS({button_w, button_s, button_n, button_e, button_c}),
.FPGA_CPU_RESET_B(cpu_reset_b),
.PIEZO_SPEAKER(piezo_out),
.GPIO_LED(gpio_leds),
.GPIO_LED_C(led_c),
.GPIO_LED_N(led_n),
.GPIO_LED_E(led_e),
.GPIO_LED_W(led_w),
.GPIO_LED_S(led_s),
.AUDIO_BIT_CLK(bit_clk),
.AUDIO_SDATA_IN(), // Leave unconnected for this lab
.AUDIO_SDATA_OUT(sdata_out),
.AUDIO_SYNC(sync),
.FLASH_AUDIO_RESET_B(reset_b),
.FPGA_SERIAL_RX(fpga_serial_rx),
.FPGA_SERIAL_TX(fpga_serial_tx)
);
ac97_codec_model #(
// Can change to 1 if you want printouts of what the codec model received on every frame
.DEBUG_MODE(1'b0)
) model (
.sdata_out(sdata_out),
.sync(sync),
.reset_b(reset_b),
.bit_clk(bit_clk),
.sdata_in()
);
// Instantiate an off-chip UART here that uses the RX and TX lines
// You can refer to the echo_testbench from lab 4
always #(`SYSTEM_CLK_PERIOD / 2) system_clock = ~system_clock;
initial begin
// Enable piezo and audio controller output
gpio_switches[0] = 1'b1;
gpio_switches[7] = 1'b1;
// Simulate pushing the CPU_RESET button and holding it for a while
// Verify that the reset signal into the ac97 controller only pulses once
// Verify that the reset signal to the codec is held for t_RSTLOW seconds
cpu_reset_b = 1'b0;
repeat (10) @(posedge system_clock);
cpu_reset_b = 1'b1;
repeat (10) @(posedge system_clock);
// Send a few characters through the off_chip_uart
// Watch your Piano FSM at work
#(`MS * 20);
// ADD SOME MORE STUFF HERE TO TEST YOUR PIANO FSM
$finish();
end
endmodule
| 6.547751 |
module system_timer_tb ();
reg clk = 0, rst = 0;
wire usecond_pulse;
wire msecond_pulse;
wire second_pulse;
wire [9:0] usecond_cntr;
wire [9:0] msecond_cntr;
wire [5:0] second_cntr;
wire [5:0] minute_cntr;
wire [4:0] hour_cntr;
wire [9:0] day_cntr;
system_timer dut (
.clk,
.rst,
.usecond_cntr,
.msecond_cntr,
.second_cntr,
.minute_cntr,
.hour_cntr,
.day_cntr,
.usecond_pulse,
.msecond_pulse,
.second_pulse
);
defparam dut.CLOCK_MHZ = 100;
always begin
#5 clk = ~clk;
end
initial begin
@(negedge clk);
rst = 1;
@(negedge clk);
rst = 0;
#10000100
// cursory activity check, better tested in hardware
if (usecond_cntr == 10'h0 && msecond_cntr == 10'ha)
$display("PASS");
$stop();
end
endmodule
| 6.702788 |
module UART_RX (
UartRx_prescale,
UartRx_RX_IN,
UartRx_PAR_EN,
UartRx_Par_Type,
UartRx_CLK,
UartRx_RST,
UartRx_PDATA,
UartRx_Data_Valid
);
input [4:0] UartRx_prescale;
output [7:0] UartRx_PDATA;
input UartRx_RX_IN, UartRx_PAR_EN, UartRx_Par_Type, UartRx_CLK, UartRx_RST;
output UartRx_Data_Valid;
wire par_err, strt_glitch, stp_err, FINISH, EdgeFinish, data_samp_en,
deser_en, edge_cnt_enable, bit_cnt_enable, par_chk_en, strt_chk_en,
stp_chk_en, sample, Sample_Valid, n1, n2;
wire [2:0] bit_cnt;
wire [4:0] edge_cnt;
RXFSM U0_RXFSM (
.RXFSM_bit_cnt(bit_cnt),
.RXFSM_RX_IN(UartRx_RX_IN),
.RXFSM_par_err(par_err),
.RXFSM_strt_glitch(strt_glitch),
.RXFSM_stp_err(stp_err),
.RXFSM_PAR_EN(UartRx_PAR_EN),
.RXFSM_FINISH(FINISH),
.RXFSM_EdgeFinish(EdgeFinish),
.RXFSM_CLK(UartRx_CLK),
.RXFSM_RST(n1),
.RXFSM_data_samp_en(data_samp_en),
.RXFSM_deser_en(deser_en),
.RXFSM_edge_cnt_enable(edge_cnt_enable),
.RXFSM_bit_cnt_enable(bit_cnt_enable),
.RXFSM_data_valid(UartRx_Data_Valid),
.RXFSM_par_chk_en(par_chk_en),
.RXFSM_strt_chk_en(strt_chk_en),
.RXFSM_stp_chk(stp_chk_en)
);
edge_bit_counter U0_edge_bit_counter (
.Cnt_prescale(UartRx_prescale),
.Cnt_edge_cnt_enable(edge_cnt_enable),
.Cnt_bit_cnt_enable(bit_cnt_enable),
.Cnt_CLK(UartRx_CLK),
.Cnt_RST(n1),
.Cnt_edge_cnt(edge_cnt),
.Cnt_bit_cnt(bit_cnt),
.Cnt_EdgeFinish(EdgeFinish)
);
Data_Sampler U0_Data_Sampler (
.Sampler_edge_cnt(edge_cnt),
.Sampler_prescale(UartRx_prescale),
.Sampler_data_samp_en(data_samp_en),
.Sampler_RX_IN(UartRx_RX_IN),
.Sampler_CLK(UartRx_CLK),
.Sampler_RST(n1),
.Sampler_sample(sample),
.Sampler_Sample_Valid(Sample_Valid)
);
Deseralizer U0_Deseralizer (
.Deseralizer_SampledData(sample),
.Deseralizer_Sample_Valid(Sample_Valid),
.Deseralizer_EN(deser_en),
.Deseralizer_CLK(UartRx_CLK),
.Deseralizer_RST(n1),
.Deseralizer_PDATA(UartRx_PDATA)
);
Strt_Check U0_Strt_Check (
.StrtChk_EN(strt_chk_en),
.StrtChk_Sample_Valid(Sample_Valid),
.StrtChk_sample(sample),
.StrtChk_glitch(strt_glitch)
);
Parity_Check U0_Parity_Check (
.ParityCheck_PDATA(UartRx_PDATA),
.ParityCheck_EN(par_chk_en),
.ParityCheck_PAR_TYP(UartRx_Par_Type),
.ParityCheck_sample(sample),
.ParityCheck_Sample_Valid(Sample_Valid),
.ParityCheck_Par_err(par_err)
);
Stop_Check U0_Stop_Check (
.StpChk_stp_chk_en(stp_chk_en),
.StpChk_sample(sample),
.StpChk_Sample_Valid(Sample_Valid),
.StpChk_stp_err(stp_err),
.StpChk_finish(FINISH)
);
INVX2M U1 (
.A(n2),
.Y(n1)
);
INVX2M U2 (
.A(UartRx_RST),
.Y(n2)
);
endmodule
| 7.513316 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid, ParityCalc_ParType;
output ParityCalc_ParBit;
wire n1, n2, n3, n4;
XNOR2X2M U1 (
.A(ParityCalc_PDATA[7]),
.B(ParityCalc_PDATA[6]),
.Y(n4)
);
XOR3XLM U2 (
.A(ParityCalc_ParType),
.B(n1),
.C(n2),
.Y(ParityCalc_ParBit)
);
XOR3XLM U3 (
.A(ParityCalc_PDATA[1]),
.B(ParityCalc_PDATA[0]),
.C(n3),
.Y(n2)
);
XOR3XLM U4 (
.A(ParityCalc_PDATA[5]),
.B(ParityCalc_PDATA[4]),
.C(n4),
.Y(n1)
);
XNOR2X2M U5 (
.A(ParityCalc_PDATA[3]),
.B(ParityCalc_PDATA[2]),
.Y(n3)
);
endmodule
| 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
wire n1, n2;
MX2X2M U1 (
.A (n2),
.B (n1),
.S0(PISO_Count[2]),
.Y (PISO_SerialData)
);
MX4X1M U2 (
.A (PISO_ParallelData[4]),
.B (PISO_ParallelData[6]),
.C (PISO_ParallelData[5]),
.D (PISO_ParallelData[7]),
.S0(PISO_Count[1]),
.S1(PISO_Count[0]),
.Y (n1)
);
MX4X1M U3 (
.A (PISO_ParallelData[0]),
.B (PISO_ParallelData[2]),
.C (PISO_ParallelData[1]),
.D (PISO_ParallelData[3]),
.S0(PISO_Count[1]),
.S1(PISO_Count[0]),
.Y (n2)
);
endmodule
| 7.018949 |
module Uart_TX_Top (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy
);
input [7:0] P_DATA;
input CLK, RST_ASYN, Data_Valid, PAR_EN, PAR_TYP;
output TX_OUT, busy;
wire Parity_bit_To_Buffer, BuffEn, Parity_En, Parity_bit, Ser_Done, Ser_En, Serial_Data;
wire [7:0] Parallel_Data;
wire [1:0] FSM_MUXSelection;
InputBuffer U0_InputBuffer (
.Buffer_Pdata_in(P_DATA),
.Buffer_ParityEn_in(PAR_EN),
.Buffer_ParBit_in(Parity_bit_To_Buffer),
.Buffer_EN(BuffEn),
.Buffer_CLK(CLK),
.Buffer_RST_ASYN(RST_ASYN),
.Buffer_Pdata_out(Parallel_Data),
.Buffer_ParityEn_out(Parity_En),
.Buffer_ParBit_out(Parity_bit)
);
Parity_Calc U0_Parity_Calc (
.ParityCalc_PDATA(P_DATA),
.ParityCalc_DataValid(Data_Valid),
.ParityCalc_ParType(PAR_TYP),
.ParityCalc_ParBit(Parity_bit_To_Buffer)
);
FSM U0_FSM (
.FSM_RST_ASYN(RST_ASYN),
.FSM_CLK(CLK),
.FSM_DataValid(Data_Valid),
.FSM_SerDone(Ser_Done),
.FSM_ParEn(Parity_En),
.FSM_SerEn(Ser_En),
.FSM_MuxSel(FSM_MUXSelection),
.FSM_Busy(busy),
.FSM_BuffEn(BuffEn)
);
Seralizer U0_Seralizer (
.Seralizer_ParallelData(Parallel_Data),
.Seralizer_CLK(CLK),
.Seralizer_RST_ASYN(RST_ASYN),
.Seralizer_En(Ser_En),
.Seralizer_done(Ser_Done),
.Seralizer_SerialData(Serial_Data)
);
MUX U0_MUX (
.Selection_Bits(FSM_MUXSelection),
.in_00(1'b1),
.in_01(1'b0),
.in_10(Parity_bit),
.in_11(Serial_Data),
.MUX_Out(TX_OUT)
);
endmodule
| 6.543511 |
module system_toplevel (
input clk,
input reset,
input bit8,
input parity_en,
input odd_n_even,
input [3:0] baud_val,
input rx,
output tx
);
wire system_reset;
wire [7:0] data_in;
wire [7:0] data_out;
wire CSn, WE, OE, adrs;
//assign led = {bit8, parity_en, odd_n_even, baud_val};
// Instantiate the module
echo processor (
.clk(clk),
.reset_ns(system_reset),
.data_out(data_out),
.adrs(adrs),
.data_in(data_in),
.WE(WE),
.OE(OE),
.CSn(CSn)
);
lb_UART_toplevel full_uart (
.clk(clk),
.reset(system_reset),
.cs(CSn),
.we(WE),
.oe(OE),
.adrs(adrs),
.data(data_in), //Tx data
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.rx(rx),
.tx(tx),
.data_out(data_out) //Rx Data
);
lb_reset resetModule (
.clk(clk), //
.resetb(reset), //
.cs(1'b1), //
.system_reset(system_reset) //
);
endmodule
| 7.525686 |
module system_top (
output trap,
//tester uart
input uart_valid,
input [`iob_uart_swreg_ADDR_W-1:0] uart_addr,
input [ `DATA_W-1:0] uart_wdata,
input [ 3:0] uart_wstrb,
output [ `DATA_W-1:0] uart_rdata,
output uart_ready,
`include "iob_gen_if.vh"
);
localparam AXI_ID_W = 4;
localparam AXI_ADDR_W = `DDR_ADDR_W;
localparam AXI_DATA_W = `DATA_W;
//PWIRES
/////////////////////////////////////////////
// TEST PROCEDURE
//
initial begin
`ifdef VCD
$dumpfile("system.vcd");
$dumpvars();
`endif
end
//
// INSTANTIATE COMPONENTS
//
//AXI wires for connecting system to memory
`ifdef USE_DDR
`include "m_axi_wire.vh"
`endif
//
// UNIT UNDER TEST
//
system #(
.AXI_ID_W (AXI_ID_W),
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W)
) uut (
//PORTS
`ifdef USE_DDR
`include "m_axi_portmap.vh"
`endif
.clk (clk),
.rst (rst),
.trap(trap)
);
//instantiate the axi memory
`ifdef USE_DDR
axi_ram #(
`ifdef DDR_INIT
.FILE("firmware.hex"),
.FILE_SIZE(`FW_SIZE),
`endif
.ID_WIDTH(AXI_ID_W),
.DATA_WIDTH(`DATA_W),
.ADDR_WIDTH(`DDR_ADDR_W)
) ddr_model_mem (
`include "s_axi_portmap.vh"
.clk(clk),
.rst(rst)
);
`endif
//finish simulation on trap
/* always @(posedge trap) begin
#10 $display("Found CPU trap condition");
$finish;
end*/
//sram monitor - use for debugging programs
/*
wire [`SRAM_ADDR_W-1:0] sram_daddr = uut.int_mem0.int_sram.d_addr;
wire sram_dwstrb = |uut.int_mem0.int_sram.d_wstrb & uut.int_mem0.int_sram.d_valid;
wire sram_drdstrb = !uut.int_mem0.int_sram.d_wstrb & uut.int_mem0.int_sram.d_valid;
wire [`DATA_W-1:0] sram_dwdata = uut.int_mem0.int_sram.d_wdata;
wire sram_iwstrb = |uut.int_mem0.int_sram.i_wstrb & uut.int_mem0.int_sram.i_valid;
wire sram_irdstrb = !uut.int_mem0.int_sram.i_wstrb & uut.int_mem0.int_sram.i_valid;
wire [`SRAM_ADDR_W-1:0] sram_iaddr = uut.int_mem0.int_sram.i_addr;
wire [`DATA_W-1:0] sram_irdata = uut.int_mem0.int_sram.i_rdata;
always @(posedge sram_dwstrb)
if(sram_daddr == 13'h090d) begin
#10 $display("Found CPU memory condition at %f : %x : %x", $time, sram_daddr, sram_dwdata );
//$finish;
end
*/
endmodule
| 6.765998 |
module mux2X1_2 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X4M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 7.220422 |
module mux2X1_4 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X8M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 7.049355 |
module mux2X1_3 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X4M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 6.805713 |
module mux2X1_5 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
CLKMX2X6M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 6.667851 |
module BIT_SYNC_test_1 (
BitSync_ASYNC,
BitSync_CLK,
BitSync_RST,
BitSync_SYNC,
test_si,
test_se
);
input [0:0] BitSync_ASYNC;
input BitSync_CLK;
input BitSync_RST;
output [0:0] BitSync_SYNC;
input test_si;
input test_se;
// Internal wires
wire \FFSTAGES[0][0] ;
SDFFRQX2M \FFSTAGES_reg[0][1] (
.SI(\FFSTAGES[0][0] ),
.SE(test_se),
.D (\FFSTAGES[0][0] ),
.CK(BitSync_CLK),
.RN(BitSync_RST),
.Q (BitSync_SYNC[0])
);
SDFFRQX2M \FFSTAGES_reg[0][0] (
.SI(test_si),
.SE(test_se),
.D (BitSync_ASYNC[0]),
.CK(BitSync_CLK),
.RN(BitSync_RST),
.Q (\FFSTAGES[0][0] )
);
endmodule
| 6.676251 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid;
input ParityCalc_ParType;
output ParityCalc_ParBit;
// Internal wires
wire n1;
wire n2;
wire n3;
wire n4;
XNOR2X2M U1 (
.A(ParityCalc_PDATA[7]),
.B(ParityCalc_PDATA[6]),
.Y(n4)
);
XNOR2X2M U2 (
.A(ParityCalc_PDATA[3]),
.B(ParityCalc_PDATA[2]),
.Y(n3)
);
XOR3XLM U3 (
.A(ParityCalc_ParType),
.B(n1),
.C(n2),
.Y(ParityCalc_ParBit)
);
XOR3XLM U4 (
.A(ParityCalc_PDATA[1]),
.B(ParityCalc_PDATA[0]),
.C(n3),
.Y(n2)
);
XOR3XLM U5 (
.A(ParityCalc_PDATA[5]),
.B(ParityCalc_PDATA[4]),
.C(n4),
.Y(n1)
);
endmodule
| 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
// Internal wires
wire n1;
wire n2;
MX2X2M U1 (
.S0(PISO_Count[2]),
.B (n1),
.A (n2),
.Y (PISO_SerialData)
);
MX4X1M U2 (
.S1(PISO_Count[0]),
.S0(PISO_Count[1]),
.D (PISO_ParallelData[7]),
.C (PISO_ParallelData[5]),
.B (PISO_ParallelData[6]),
.A (PISO_ParallelData[4]),
.Y (n1)
);
MX4X1M U3 (
.S1(PISO_Count[0]),
.S0(PISO_Count[1]),
.D (PISO_ParallelData[3]),
.C (PISO_ParallelData[1]),
.B (PISO_ParallelData[2]),
.A (PISO_ParallelData[0]),
.Y (n2)
);
endmodule
| 7.018949 |
module Uart_TX_Top_test_1 (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy,
test_si,
test_so,
test_se,
UART_TX_CLK_m__L3_N0
);
input [7:0] P_DATA;
input CLK;
input RST_ASYN;
input Data_Valid;
input PAR_EN;
input PAR_TYP;
output TX_OUT;
output busy;
input test_si;
output test_so;
input test_se;
input UART_TX_CLK_m__L3_N0;
// Internal wires
wire Parity_bit_To_Buffer;
wire BuffEn;
wire Parity_En;
wire Parity_bit;
wire Ser_Done;
wire Ser_En;
wire Serial_Data;
wire n4;
wire [7:0] Parallel_Data;
wire [1:0] FSM_MUXSelection;
InputBuffer_test_1 U0_InputBuffer (
.Buffer_Pdata_in(P_DATA),
.Buffer_ParityEn_in(PAR_EN),
.Buffer_ParBit_in(Parity_bit_To_Buffer),
.Buffer_EN(BuffEn),
.Buffer_CLK(CLK),
.Buffer_RST_ASYN(RST_ASYN),
.Buffer_Pdata_out(Parallel_Data),
.Buffer_ParityEn_out(Parity_En),
.Buffer_ParBit_out(Parity_bit),
.test_si(n4),
.test_se(test_se),
.UART_TX_CLK_m__L3_N0(UART_TX_CLK_m__L3_N0)
);
Parity_Calc U0_Parity_Calc (
.ParityCalc_PDATA(P_DATA),
.ParityCalc_DataValid(Data_Valid),
.ParityCalc_ParType(PAR_TYP),
.ParityCalc_ParBit(Parity_bit_To_Buffer)
);
FSM_test_1 U0_FSM (
.FSM_RST_ASYN(RST_ASYN),
.FSM_CLK(CLK),
.FSM_DataValid(Data_Valid),
.FSM_SerDone(Ser_Done),
.FSM_ParEn(Parity_En),
.FSM_SerEn(Ser_En),
.FSM_MuxSel(FSM_MUXSelection),
.FSM_Busy(busy),
.FSM_BuffEn(BuffEn),
.test_si(test_si),
.test_so(n4),
.test_se(test_se),
.UART_TX_CLK_m__L3_N0(UART_TX_CLK_m__L3_N0)
);
Seralizer_test_1 U0_Seralizer (
.Seralizer_ParallelData(Parallel_Data),
.Seralizer_CLK(UART_TX_CLK_m__L3_N0),
.Seralizer_RST_ASYN(RST_ASYN),
.Seralizer_En(Ser_En),
.Seralizer_done(Ser_Done),
.Seralizer_SerialData(Serial_Data),
.test_so(test_so),
.test_se(test_se)
);
MUX U0_MUX (
.Selection_Bits(FSM_MUXSelection),
.in_10(Parity_bit),
.in_11(Serial_Data),
.MUX_Out(TX_OUT)
);
endmodule
| 6.728658 |
module MX2X8M (
S0,
B,
A,
Y,
VSS,
VDD
);
input S0;
input B;
input A;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.643904 |
module SDFFRQX1M (
SI,
SE,
D,
CK,
RN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.769267 |
module NAND2BX2M (
AN,
B,
Y,
VSS,
VDD
);
input AN;
input B;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.529063 |
module SDFFRHQX4M (
SI,
SE,
D,
CK,
RN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.948256 |
module NAND2X2M (
A,
B,
Y,
VSS,
VDD
);
input A;
input B;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.598616 |
module NAND4X2M (
A,
B,
C,
D,
Y,
VSS,
VDD
);
input A;
input B;
input C;
input D;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.835375 |
module SDFFSQX1M (
SI,
SE,
D,
CK,
SN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input SN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.530196 |
module MX4X1M (
S1,
S0,
D,
C,
B,
A,
Y,
VSS,
VDD
);
input S1;
input S0;
input D;
input C;
input B;
input A;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.507033 |
module SDFFRX1M (
SI,
SE,
D,
CK,
RN,
Q,
QN,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
output QN;
inout VSS;
inout VDD;
endmodule
| 6.860177 |
module NAND4XLM (
A,
B,
C,
D,
Y,
VSS,
VDD
);
input A;
input B;
input C;
input D;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.864833 |
module NAND3XLM (
A,
B,
C,
Y,
VSS,
VDD
);
input A;
input B;
input C;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.651028 |
module mux2X1_2 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X4M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 7.220422 |
module mux2X1_4 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X8M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 7.049355 |
module mux2X1_3 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X4M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 6.805713 |
module mux2X1_5 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
CLKMX2X6M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 6.667851 |
module BIT_SYNC_test_1 (
BitSync_ASYNC,
BitSync_CLK,
BitSync_RST,
BitSync_SYNC,
test_si,
test_se,
VDD,
VSS
);
input [0:0] BitSync_ASYNC;
input BitSync_CLK;
input BitSync_RST;
output [0:0] BitSync_SYNC;
input test_si;
input test_se;
inout VDD;
inout VSS;
// Internal wires
wire \FFSTAGES[0][0] ;
// Module instantiations
SDFFRQX2M \FFSTAGES_reg[0][1] (
.SI (\FFSTAGES[0][0] ),
.SE (test_se),
.D (\FFSTAGES[0][0] ),
.CK (BitSync_CLK),
.RN (BitSync_RST),
.Q (BitSync_SYNC[0]),
.VSS(VSS),
.VDD(VDD)
);
SDFFRQX2M \FFSTAGES_reg[0][0] (
.SI (test_si),
.SE (test_se),
.D (BitSync_ASYNC[0]),
.CK (BitSync_CLK),
.RN (BitSync_RST),
.Q (\FFSTAGES[0][0] ),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 6.676251 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit,
VDD,
VSS
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid;
input ParityCalc_ParType;
output ParityCalc_ParBit;
inout VDD;
inout VSS;
// Internal wires
wire n1;
wire n2;
wire n3;
wire n4;
// Module instantiations
XNOR2X2M U1 (
.A (ParityCalc_PDATA[7]),
.B (ParityCalc_PDATA[6]),
.Y (n4),
.VSS(VSS),
.VDD(VDD)
);
XNOR2X2M U2 (
.A (ParityCalc_PDATA[3]),
.B (ParityCalc_PDATA[2]),
.Y (n3),
.VSS(VSS),
.VDD(VDD)
);
XOR3XLM U3 (
.A (ParityCalc_ParType),
.B (n1),
.C (n2),
.Y (ParityCalc_ParBit),
.VSS(VSS),
.VDD(VDD)
);
XOR3XLM U4 (
.A (ParityCalc_PDATA[1]),
.B (ParityCalc_PDATA[0]),
.C (n3),
.Y (n2),
.VSS(VSS),
.VDD(VDD)
);
XOR3XLM U5 (
.A (ParityCalc_PDATA[5]),
.B (ParityCalc_PDATA[4]),
.C (n4),
.Y (n1),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData,
VDD,
VSS
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
inout VDD;
inout VSS;
// Internal wires
wire n1;
wire n2;
// Module instantiations
MX2X2M U1 (
.S0 (PISO_Count[2]),
.B (n1),
.A (n2),
.Y (PISO_SerialData),
.VSS(VSS),
.VDD(VDD)
);
MX4X1M U2 (
.S1 (PISO_Count[0]),
.S0 (PISO_Count[1]),
.D (PISO_ParallelData[7]),
.C (PISO_ParallelData[5]),
.B (PISO_ParallelData[6]),
.A (PISO_ParallelData[4]),
.Y (n1),
.VSS(VSS),
.VDD(VDD)
);
MX4X1M U3 (
.S1 (PISO_Count[0]),
.S0 (PISO_Count[1]),
.D (PISO_ParallelData[3]),
.C (PISO_ParallelData[1]),
.B (PISO_ParallelData[2]),
.A (PISO_ParallelData[0]),
.Y (n2),
.VSS(VSS),
.VDD(VDD)
);
endmodule
| 7.018949 |
module Uart_TX_Top_test_1 (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy,
test_si,
test_so,
test_se,
UART_TX_CLK_m__L3_N0,
VDD,
VSS
);
input [7:0] P_DATA;
input CLK;
input RST_ASYN;
input Data_Valid;
input PAR_EN;
input PAR_TYP;
output TX_OUT;
output busy;
input test_si;
output test_so;
input test_se;
input UART_TX_CLK_m__L3_N0;
inout VDD;
inout VSS;
// Internal wires
wire Parity_bit_To_Buffer;
wire BuffEn;
wire Parity_En;
wire Parity_bit;
wire Ser_Done;
wire Ser_En;
wire Serial_Data;
wire n4;
wire [7:0] Parallel_Data;
wire [1:0] FSM_MUXSelection;
// Module instantiations
InputBuffer_test_1 U0_InputBuffer (
.Buffer_Pdata_in(P_DATA),
.Buffer_ParityEn_in(PAR_EN),
.Buffer_ParBit_in(Parity_bit_To_Buffer),
.Buffer_EN(BuffEn),
.Buffer_CLK(CLK),
.Buffer_RST_ASYN(RST_ASYN),
.Buffer_Pdata_out(Parallel_Data),
.Buffer_ParityEn_out(Parity_En),
.Buffer_ParBit_out(Parity_bit),
.test_si(n4),
.test_se(test_se),
.UART_TX_CLK_m__L3_N0(UART_TX_CLK_m__L3_N0),
.VDD(VDD),
.VSS(VSS)
);
Parity_Calc U0_Parity_Calc (
.ParityCalc_PDATA(P_DATA),
.ParityCalc_DataValid(Data_Valid),
.ParityCalc_ParType(PAR_TYP),
.ParityCalc_ParBit(Parity_bit_To_Buffer),
.VDD(VDD),
.VSS(VSS)
);
FSM_test_1 U0_FSM (
.FSM_RST_ASYN(RST_ASYN),
.FSM_CLK(CLK),
.FSM_DataValid(Data_Valid),
.FSM_SerDone(Ser_Done),
.FSM_ParEn(Parity_En),
.FSM_SerEn(Ser_En),
.FSM_MuxSel(FSM_MUXSelection),
.FSM_Busy(busy),
.FSM_BuffEn(BuffEn),
.test_si(test_si),
.test_so(n4),
.test_se(test_se),
.UART_TX_CLK_m__L3_N0(UART_TX_CLK_m__L3_N0),
.VDD(VDD),
.VSS(VSS)
);
Seralizer_test_1 U0_Seralizer (
.Seralizer_ParallelData(Parallel_Data),
.Seralizer_CLK(UART_TX_CLK_m__L3_N0),
.Seralizer_RST_ASYN(RST_ASYN),
.Seralizer_En(Ser_En),
.Seralizer_done(Ser_Done),
.Seralizer_SerialData(Serial_Data),
.test_so(test_so),
.test_se(test_se),
.VDD(VDD),
.VSS(VSS)
);
MUX U0_MUX (
.Selection_Bits(FSM_MUXSelection),
.in_10(Parity_bit),
.in_11(Serial_Data),
.MUX_Out(TX_OUT),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 6.728658 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 15/8/2022 Mina Hanna final version
//------------------------------------------------
// KEYWORDS: uart system, communnication system
//------------------------------------------------
// PURPOSE: top module testbench for the uart system\
`timescale 1ns/1ps
//////////////////defining inputs and output port////////////////////
module SYSTEM_TOP_tb ();
/////////////////test bench signals///////////////////////
reg RX_IN_tb;
reg REF_CLK_tb;
reg UART_CLK_tb;
reg RST_tb;
reg en_transmission;
reg [6:0] count;
wire TX_OUT_tb;
/////////////////// parameters ///////////////////////////
parameter REF_CLK_PER = 20;
parameter UART_CLK_PER = 100;
parameter ALU_W_OP_NUM_OF_FRAMES = 4 ;
parameter RF_Wr_CMD_NUK_OF_FRAMES =3;
parameter RF_Rd_CMD_NUK_OF_FRAMES =2;
reg [RF_Wr_CMD_NUK_OF_FRAMES*10-1:0] RF_Wr_CMD = 'b1_0_00111_11_0_1_00000010_0_1_10101010_0;
reg [RF_Rd_CMD_NUK_OF_FRAMES*11-1:0] RF_Rd_CMD = 'b10_00000010_0_11_10111011_0;
reg [ALU_W_OP_NUM_OF_FRAMES*11-1:0] ALU_W_OP_CMD = 'b10_00000001_0_11_00000011_0_11_00000101_0_11_11001100_0 ;
////////////////// initial block /////////////////////////
initial
begin
RX_IN_tb = 1'b1;
REF_CLK_tb = 1'b0;
UART_CLK_tb = 1'b0;
RST_tb = 1'b1;
count = 6'd0;
#5
RST_tb = 1'b0;
#5
RST_tb = 1'b1;
en_transmission = 1'b1;
#500000
$finish;
end
//////////////////RX in///////////////////////////////////
always@(posedge DUT.U0_ClkDiv.o_div_clk)
begin
if(en_transmission && count < 7'd30 )
begin
RX_IN_tb <= RF_Wr_CMD[count] ;
count <= count + 7'b1 ;
end
else if(en_transmission && count < 7'd74)
begin
RX_IN_tb <= ALU_W_OP_CMD[count-30] ;
count <= count + 6'b1 ;
end
else
RX_IN_tb <= 1'b1 ;
end
//////////////////clocks definition///////////////////////
always #(REF_CLK_PER/2) REF_CLK_tb = ~ REF_CLK_tb;
always #(UART_CLK_PER/2) UART_CLK_tb = ~ UART_CLK_tb;
//////////////////Design instantiation////////////////////
SYSTEM_TOP DUT(
.RX_IN(RX_IN_tb),
.REF_CLK(REF_CLK_tb),
.UART_CLK(UART_CLK_tb),
.RST(RST_tb),
.TX_OUT(TX_OUT_tb)
);
endmodule
| 8.923686 |
module system_top_wrapper_wrapper (
gpio_led_tri_o,
gpio_trig_tri_o,
sys_clk_clk_n,
sys_clk_clk_p,
sys_reset,
uart_rxd,
uart_txd
);
output [9:0] gpio_led_tri_o;
output [0:0] gpio_trig_tri_o;
input sys_clk_clk_n;
input sys_clk_clk_p;
input sys_reset;
input uart_rxd;
output uart_txd;
wire [9:0] gpio_led_tri_o;
wire [0:0] gpio_trig_tri_o;
wire sys_clk_clk_n;
wire sys_clk_clk_p;
wire sys_reset;
wire uart_rxd;
wire uart_txd;
system_top_wrapper system_top_wrapper_i (
.gpio_led_tri_o(gpio_led_tri_o),
.gpio_trig_tri_o(gpio_trig_tri_o),
.sys_clk_clk_n(sys_clk_clk_n),
.sys_clk_clk_p(sys_clk_clk_p),
.sys_reset(sys_reset),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd)
);
endmodule
| 7.554459 |
module system_UART_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.895046 |
module system_UART_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
system_UART_sim_scfifo_w the_system_UART_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.895046 |
module system_UART_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.895046 |
module system_UART_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
system_UART_sim_scfifo_r the_system_UART_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.895046 |
module systest;
//-- parameter
parameter N_EXP = 16384;
parameter N_PAT = N_EXP;
//-- reg and wire
reg clk;
reg reset;
reg in_en;
reg [7:0] Din;
wire busy;
wire out_valid;
wire [7:0] Dout;
reg [7:0] pat_mem [0:N_PAT-1];
reg [7:0] exp_mem [0:N_EXP-1];
reg [7:0] out_temp;
reg stop;
integer i, out_f, err, pass, exp_num, times;
reg over;
//-- design under test
lmfe_top u_lmfe_top (
.clk(clk),
.reset(reset),
.Din(Din),
.in_en(in_en),
.busy(busy),
.out_valid(out_valid),
.Dout(Dout)
);
//-- read input and golden image
initial $readmemh(`PAT, pat_mem);
initial $readmemh(`EXP, exp_mem);
//-- initialization
initial begin
#0;
clk = 1'b0;
reset = 1'b0;
in_en = 1'b0;
Din = 'hz;
stop = 1'b0;
over = 1'b0;
exp_num = 0;
err = 0;
pass = 0;
times = 1;
end
//-- clock generator
always begin
#(`CYCLE / 2) clk = ~clk;
end
//-- dump waveform
initial begin
$dumpfile("top.vcd");
$dumpvars(1, systest);
out_f = $fopen("out.dat");
if (out_f == 0) begin
$display("Output file open error !");
$finish;
end
end
initial begin
@(negedge clk) reset = 1'b1;
#`CYCLE reset = 1'b0;
#(`CYCLE * 2);
@(negedge clk) i = 0;
while (i <= N_PAT) begin
if (!busy) begin
Din = pat_mem[i];
in_en = 1'b1;
i = i + 1;
end else begin
Din = 'hz;
in_en = 1'b0;
end
@(negedge clk);
end
in_en = 0;
Din = 'hz;
end
always @(posedge clk) begin
out_temp = exp_mem[exp_num];
if (out_valid) begin
$fdisplay(out_f, "%2h", Dout);
if (Dout !== out_temp) begin
$display("ERROR at %5d:output %2h !=expect %2h ", exp_num, Dout, out_temp);
err = err + 1;
end else begin
pass = pass + 1;
end
#1 exp_num = exp_num + 1;
end
if (exp_num === N_EXP) over = 1'b1;
end
always @(exp_num) begin
if (exp_num === (1000 * times) && err === 0) begin
$display("Output pixel: 0 ~ %5d are correct!\n", (1000 * times));
times = times + 1;
end
end
initial begin
#(`CYCLE * `End_CYCLE);
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
initial begin
@(posedge over)
if ((over) && (exp_num != 'd0)) begin
$display("-----------------------------------------------------\n");
if (err == 0) begin
$display("Congratulations! All data have been generated successfully!\n");
$display("-------------------------PASS------------------------\n");
end else begin
$display("There are %d errors!\n", err);
$display("-----------------------------------------------------\n");
end
end
#(`CYCLE / 2);
$finish;
end
endmodule
| 7.032771 |
module systolic_array_tb;
reg clk, ce;
reg [31:0] ctrl;
reg [3:0] mem_addr;
reg signed [7:0] x_in;
wire signed [7:0] y_out1, x_out1, y_out2, x_out2;
integer i;
systolic_array dut1 (
clk,
ce,
ctrl,
mem_addr,
x_in,
x_out1,
y_out1
);
defparam dut1.WIDTH = 8; defparam dut1.CELL_COUNT = 3; defparam dut1.CELL_MEM_ADDR_WIDTH = 4;
defparam dut1.CELL_ROM_BASENAME = "build/raw-mnist-weights-int8/conv2d/cell-weight-";
defparam dut1.CELL_ROM_EXTENSION = ".mem";
systolic_array dut2 (
clk,
ce,
ctrl,
mem_addr,
x_in,
x_out2,
y_out2
);
defparam dut2.WIDTH = 8; defparam dut2.CELL_COUNT = 3; defparam dut2.CELL_MEM_ADDR_WIDTH = 4;
defparam dut2.CELL_ROM_BASENAME = "build/raw-mnist-weights-int8/conv2d/cell-weight-";
defparam dut2.CELL_ROM_EXTENSION = ".mem";
initial begin
$dumpfile("./build/rtl-sim/vcd/systolic-array.vcd");
$dumpvars;
end
initial begin
clk = 0;
ce = 1;
x_in = 3;
ctrl = 0;
mem_addr = 0;
i = 0;
#100;
for (i = 0; i < 64; i = i + 1) begin
case (i)
32'd0: x_in = 0;
32'd1: x_in = 1;
32'd2: x_in = 0;
32'd3: x_in = 2;
32'd4: x_in = 5;
32'd5: x_in = 0;
32'd6: x_in = 0;
32'd7: x_in = 1;
32'd8: x_in = 2;
32'd9: x_in = 3;
32'd10: begin
x_in = 4;
mem_addr = 0;
end
32'd11: x_in = 10;
32'd12: x_in = 11;
32'd13: x_in = 0;
32'd14: x_in = 0;
32'd15: x_in = 6;
default: x_in = 0;
endcase
mem_addr = (mem_addr + 1) % 12;
clk = ~clk;
#100;
clk = ~clk;
#100;
end
end
endmodule
| 6.94034 |
module systolic_cell_tb;
reg clk, ce;
reg [31:0] ctrl_in;
reg [ 3:0] mem_addr_in;
reg signed [7:0] y_in, x_in;
wire signed [7:0] y_out, x_out;
wire [31:0] ctrl_out;
wire [3:0] mem_addr_out;
integer i;
systolic_cell dut (
clk,
ce,
ctrl_in,
ctrl_out,
mem_addr_in,
mem_addr_out,
y_in,
y_out,
x_in,
x_out
);
defparam dut.WIDTH = 8; defparam dut.MEM_ADDR_WIDTH = 4;
defparam dut.ROM_FILE = "build/raw-mnist-weights-int8/conv2d/cell-weight-0.mem";
initial begin
$dumpfile("./build/rtl-sim/vcd/systolic-cell.vcd");
$dumpvars;
end
initial begin
clk = 0;
ce = 1;
x_in = 15;
y_in = 3;
ctrl_in = 0;
mem_addr_in = 0;
i = 0;
#100;
for (i = 0; i < 32; i = i + 1) begin
clk = ~clk;
#100;
clk = ~clk;
#100;
end
end
endmodule
| 8.114695 |
module systolic_cell (
clk,
ce,
ctrl_in,
ctrl_out,
mem_addr_in,
mem_addr_out,
y_in,
y_out,
x_in,
x_out
);
// Parameters
parameter WIDTH = 8;
parameter MEM_ADDR_WIDTH = 4;
parameter ROM_FILE = "weights/cell-weights.mem";
localparam ACCUM_WIDTH = WIDTH * 2;
localparam SATURATED_MAX = (1 << WIDTH - 1) - 1;
localparam SATURATED_MIN = -(1 << WIDTH - 1);
// Port connections
input clk, ce;
input [31:0] ctrl_in;
input [MEM_ADDR_WIDTH-1:0] mem_addr_in;
input signed [WIDTH-1:0] y_in, x_in;
output signed [WIDTH-1:0] y_out, x_out;
output [31:0] ctrl_out;
output [MEM_ADDR_WIDTH-1:0] mem_addr_out;
// Internals
wire signed [ACCUM_WIDTH-1:0] mac_out;
wire signed [WIDTH-1:0] kernel_weight;
reg [31:0] ctrl_reg;
reg [MEM_ADDR_WIDTH-1:0] mem_addr_reg;
reg signed [WIDTH-1:0] x_in_reg1, x_in_reg2;
// Instantiate a MAC-unit
mac mac_inst (
clk,
ce,
x_in,
kernel_weight,
y_in,
mac_out
);
defparam mac_inst.WIDTH = WIDTH;
// Instantiate ROM unit
rom cell_memory (
clk,
1'b1,
mem_addr_reg,
kernel_weight
);
defparam cell_memory.ADDR_WIDTH = MEM_ADDR_WIDTH; defparam cell_memory.DATA_WIDTH = WIDTH;
defparam cell_memory.ROM_FILE = ROM_FILE;
// Init values (for simulation purposes)
initial begin
mem_addr_reg = 0;
ctrl_reg = 0;
x_in_reg1 = 0;
x_in_reg2 = 0;
end
// Cell dataflow pipeline logic
always @(posedge clk) begin
if (ce) begin
mem_addr_reg <= mem_addr_in;
ctrl_reg <= ctrl_in;
x_in_reg1 <= x_in;
x_in_reg2 <= x_in_reg1;
end
end
// Saturate/clamp the MAC's output value to max/min range
assign y_out =
/* if */ (mac_out >= SATURATED_MAX) ? (SATURATED_MAX) :
/* else if*/ (mac_out <= SATURATED_MIN) ? (SATURATED_MIN) :
/* else */ (mac_out[WIDTH-1:0]);
// Pass x_out to next systolic cell
assign x_out = x_in_reg2;
// Pass ctrl and mem_addr to next cell
assign ctrl_out = ctrl_reg;
assign mem_addr_out = mem_addr_reg;
endmodule
| 8.114695 |
module SystolicArray (
output wire done_PE11,
output wire done_PE22,
output wire [15:0] result_row1,
output wire [15:0] result_row2,
// input signals for processing element PE11
input wire [15:0] a11,
input wire [15:0] b1,
input wire [15:0] previous_StageOperand,
input wire start_PE11,
input reset,
input clear,
// input signals for processing element PE21
input wire [15:0] a21,
input wire start_PE21,
// input signal for processing element PE12
input wire [15:0] a12,
input wire [15:0] b2,
input wire start_PE12,
// input wire for processing element PE22
input wire [15:0] a22,
input wire start_PE22,
input wire clk
);
// wires to connect the processing elements with each other.
wire [15:0] w0;
wire [15:0] w1;
wire [15:0] w2;
wire [15:0] w3;
// instantiation of PE11
Systolic_Processor PE11 (
// output
.result(w1),
.next_row_operand(w0),
.delayed_done(done_PE11),
// input
.operand1(a11),
.operand2(b1),
.previous_StageOperand(previous_StageOperand),
.start(start_PE11),
.reset(reset),
.clear(clear),
.clk(clk)
);
// instantiation of PE12
Systolic_Processor PE12 (
// output
.result (result_row1),
.next_row_operand(w2),
.delayed_done (), // ignore, not used by controller
// input
.operand1(a12),
.operand2(b2),
.previous_StageOperand(w1),
.start(start_PE12),
.reset(reset),
.clear(clear),
.clk(clk)
);
// instantiation of PE21
Systolic_Processor PE21 (
// output
.result (w3),
.next_row_operand(), // not used further
.delayed_done (), // ignore, not used by controller
// input
.operand1(a21),
.operand2(w0),
.previous_StageOperand(previous_StageOperand),
.start(start_PE21),
.reset(reset),
.clear(clear),
.clk(clk)
);
// instantiation of PE22
Systolic_Processor PE22 (
// output
.result (result_row2),
.next_row_operand(), // not used further
.delayed_done (donw_PE22),
// input
.operand1(a22),
.operand2(w2),
.previous_StageOperand(w3),
.start(start_PE22),
.reset(reset),
.clear(clear),
.clk(clk)
);
endmodule
| 7.188821 |
module SystolicMult #(
parameter INT_WIDTH,
parameter FRAC_WIDTH,
parameter SYSTOLIC_SIZE,
parameter SYSTOLIC_STEP_SIZE
) (
input logic reset,
input logic clk,
input systolic_mult_recv_msg recv_msg,
input logic recv_val,
output logic recv_rdy,
output systolic_mult_send_msg send_msg,
output logic send_val,
input logic send_rdy,
output logic produce_run
);
logic finished, shift_result;
SystolicMultControl #(
// parameter for fixed point number, default is 11.5 (include sign bit)
.SYSTOLIC_SIZE(SYSTOLIC_SIZE),
.SYSTOLIC_STEP_SIZE(SYSTOLIC_STEP_SIZE)
) systolicMultControl (
.clk(clk),
.reset(reset),
.run(recv_msg.run),
.final_run(recv_msg.final_run),
.shift_result(shift_result),
.finished(finished),
.val(send_val),
.ready(recv_rdy),
.produce_run(produce_run)
);
parameter NUM_INTERCONNECT_1D = (SYSTOLIC_SIZE - 1) * SYSTOLIC_SIZE;
logic [NUM_INTERCONNECT_1D-1:0][INT_WIDTH + FRAC_WIDTH - 1:0] pass_a, pass_b;
logic [SYSTOLIC_SIZE-1:0] pass_shift_result, reg_finished;
Pe #(INT_WIDTH, FRAC_WIDTH) pe0 (
.clk(clk),
.reset(reset),
.a(recv_msg.data_0),
.b(recv_msg.weight_0),
.shift_result(shift_result),
.finished(finished),
.pass_shift_result(pass_shift_result[0]),
.reg_finished(reg_finished[0]),
.reg_pass_down(pass_a[0]),
.reg_pass_right(pass_b[0])
);
Pe #(INT_WIDTH, FRAC_WIDTH) pe1 (
.clk(clk),
.reset(reset),
.a(recv_msg.data_1),
.b(pass_b[0]),
.shift_result(pass_shift_result[0]),
.finished(reg_finished[0]),
.pass_shift_result(pass_shift_result[1]),
.reg_finished(reg_finished[1]),
.reg_pass_down(pass_a[1]),
.reg_pass_right()
);
Pe #(INT_WIDTH, FRAC_WIDTH) pe2 (
.clk(clk),
.reset(reset),
.a(pass_a[0]),
.b(recv_msg.weight_1),
.shift_result(pass_shift_result[0]),
.finished(reg_finished[0]),
.pass_shift_result(),
.reg_finished(),
.reg_pass_down(send_msg.result_0),
.reg_pass_right(pass_b[1])
);
Pe #(INT_WIDTH, FRAC_WIDTH) pe3 (
.clk(clk),
.reset(reset),
.a(pass_a[1]),
.b(pass_b[1]),
.shift_result(pass_shift_result[1]),
.finished(reg_finished[1]),
.pass_shift_result(),
.reg_finished(),
.reg_pass_down(send_msg.result_1),
.reg_pass_right()
);
endmodule
| 6.99911 |
module SystolicMultControl #(
// parameter for fixed point number, default is 11.5 (include sign bit)
parameter SYSTOLIC_SIZE,
parameter SYSTOLIC_STEP_SIZE
) (
input logic clk,
input logic reset,
input logic run,
input logic final_run,
output logic shift_result,
output logic finished,
output logic val,
output logic ready,
output logic produce_run
);
logic [$clog2(SYSTOLIC_STEP_SIZE*2) - 1 : 0] count;
logic count_start;
always @(posedge clk) begin
if (reset) count <= 'b0;
else count <= count_start ? count + 1'b1 : 0;
end
typedef enum {
STATE_WAIT,
STATE_RUN,
STATE_RUN_CONTINUOUS,
STATE_FINISH,
STATE_FINISHWAIT,
STATE_SHIFT,
STATE_SHIFTWAIT0,
STATE_SHIFTWAIT1,
STATE_READ_VAL
} states;
states current_state, next_state;
logic run_done;
assign run_done = (count == SYSTOLIC_STEP_SIZE - 2) && current_state == STATE_RUN;
logic finish_done;
assign finish_done = (count == (SYSTOLIC_STEP_SIZE-2+SYSTOLIC_SIZE)) && current_state == STATE_FINISH;
always @(posedge clk) begin
if (reset) current_state <= STATE_WAIT;
else current_state <= next_state;
end
always @(*) begin
next_state = current_state;
shift_result = 'b0;
finished = 'b0;
count_start = 'b0;
ready = 'b0;
val = 'b0;
produce_run = 'b0;
case (current_state)
STATE_WAIT: begin
if (run) begin
if (final_run) next_state = STATE_RUN;
else next_state = STATE_RUN_CONTINUOUS;
end
ready = 'b1;
shift_result = 'b1;
end
STATE_RUN_CONTINUOUS: begin
ready = 'b1;
if (final_run) next_state = STATE_RUN;
end
STATE_RUN: begin
if (run_done) next_state = STATE_FINISH;
count_start = 'b1;
end
STATE_FINISH: begin
if (finish_done) next_state = STATE_FINISHWAIT;
finished = 'b1;
count_start = 'b1;
end
STATE_FINISHWAIT: begin
next_state = STATE_SHIFT;
end
STATE_SHIFT: begin
next_state = STATE_SHIFTWAIT0;
shift_result = 1'b1;
end
STATE_SHIFTWAIT0: begin
next_state = STATE_SHIFTWAIT1;
val = 'b1;
end
STATE_SHIFTWAIT1: begin
next_state = STATE_READ_VAL;
val = 'b1;
end
STATE_READ_VAL: begin
next_state = STATE_WAIT;
produce_run = 'b1;
end
default: next_state = STATE_WAIT;
endcase
end
endmodule
| 7.539809 |
module sorting_engine (
input clk,
input reset
);
wire [15:0] right[0:6];
wire [1:0] odd_L, even_L, odd_R, even_R;
wire [1:0] sp_even_R;
assign sp_even_R = (even_R == 2'b10) ? 2'b00 : even_R;
wire [1:0] sp_odd_L;
assign sp_odd_L = (odd_L == 2'b10) ? 2'b00 : odd_L;
bus_controller controller (
.even_L(even_L),
.even_R(even_R),
.odd_L(odd_L),
.odd_R(odd_R),
.reset(reset),
.clk(clk)
);
processor p1 ( //.left(left),
.right(right[0]),
.L(sp_odd_L),
.R(odd_R),
.reset(reset),
.clk(clk),
.initval(32'h000f000e)
);
processor p2 (
.left(right[0]),
.right(right[1]),
.L(even_L),
.R(even_R),
.reset(reset),
.clk(clk),
.initval(32'h000a000d)
);
processor p3 (
.left(right[1]),
.right(right[2]),
.L(odd_L),
.R(odd_R),
.reset(reset),
.clk(clk),
.initval(32'h000c000b)
);
processor p4 (
.left(right[2]),
.right(right[3]),
.L(even_L),
.R(even_R),
.reset(reset),
.clk(clk),
.initval(32'h00080007)
);
processor p5 (
.left(right[3]),
.right(right[4]),
.L(odd_L),
.R(odd_R),
.reset(reset),
.clk(clk),
.initval(32'h00090006)
);
processor p6 (
.left(right[4]),
.right(right[5]),
.L(even_L),
.R(even_R),
.reset(reset),
.clk(clk),
.initval(32'h00030004)
);
processor p7 (
.left(right[5]),
.right(right[6]),
.L(odd_L),
.R(odd_R),
.reset(reset),
.clk(clk),
.initval(32'h00010002)
);
processor p8 (
.left(right[6]),
//.right(right[7]),
.L(even_L),
.R(sp_even_R),
.reset(reset),
.clk(clk),
.initval(32'h00000005)
);
endmodule
| 7.158008 |
module cmp_swap (
input [15:0] a,
input [15:0] b,
output [15:0] c,
output [15:0] d
);
assign c = (a > b) ? b : a;
assign d = (a > b) ? a : b;
endmodule
| 7.478135 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module systolic_array (
inp_west0,
inp_west4,
inp_west8,
inp_west12,
inp_north0,
inp_north1,
inp_north2,
inp_north3,
clk,
rst,
done
);
input [31:0] inp_west0, inp_west4, inp_west8, inp_west12,
inp_north0, inp_north1, inp_north2, inp_north3;
output reg done;
input clk, rst;
reg [3:0] count;
wire [31:0] inp_north0, inp_north1, inp_north2, inp_north3;
wire [31:0] inp_west0, inp_west4, inp_west8, inp_west12;
wire [31:0] outp_south0, outp_south1, outp_south2, outp_south3, outp_south4, outp_south5, outp_south6, outp_south7, outp_south8, outp_south9, outp_south10, outp_south11, outp_south12, outp_south13, outp_south14, outp_south15;
wire [31:0] outp_east0, outp_east1, outp_east2, outp_east3, outp_east4, outp_east5, outp_east6, outp_east7, outp_east8, outp_east9, outp_east10, outp_east11, outp_east12, outp_east13, outp_east14, outp_east15;
wire [63:0] result0, result1, result2, result3, result4, result5, result6, result7, result8, result9, result10, result11, result12, result13, result14, result15;
//from north and west
block P0 (
inp_north0,
inp_west0,
clk,
rst,
outp_south0,
outp_east0,
result0
);
//from north
block P1 (
inp_north1,
outp_east0,
clk,
rst,
outp_south1,
outp_east1,
result1
);
block P2 (
inp_north2,
outp_east1,
clk,
rst,
outp_south2,
outp_east2,
result2
);
block P3 (
inp_north3,
outp_east2,
clk,
rst,
outp_south3,
outp_east3,
result3
);
//from west
block P4 (
outp_south0,
inp_west4,
clk,
rst,
outp_south4,
outp_east4,
result4
);
block P8 (
outp_south4,
inp_west8,
clk,
rst,
outp_south8,
outp_east8,
result8
);
block P12 (
outp_south8,
inp_west12,
clk,
rst,
outp_south12,
outp_east12,
result12
);
//no direct inputs
//second row
block P5 (
outp_south1,
outp_east4,
clk,
rst,
outp_south5,
outp_east5,
result5
);
block P6 (
outp_south2,
outp_east5,
clk,
rst,
outp_south6,
outp_east6,
result6
);
block P7 (
outp_south3,
outp_east6,
clk,
rst,
outp_south7,
outp_east7,
result7
);
//third row
block P9 (
outp_south5,
outp_east8,
clk,
rst,
outp_south9,
outp_east9,
result9
);
block P10 (
outp_south6,
outp_east9,
clk,
rst,
outp_south10,
outp_east10,
result10
);
block P11 (
outp_south7,
outp_east10,
clk,
rst,
outp_south11,
outp_east11,
result11
);
//fourth row
block P13 (
outp_south9,
outp_east12,
clk,
rst,
outp_south13,
outp_east13,
result13
);
block P14 (
outp_south10,
outp_east13,
clk,
rst,
outp_south14,
outp_east14,
result14
);
block P15 (
outp_south11,
outp_east14,
clk,
rst,
outp_south15,
outp_east15,
result15
);
always @(posedge clk) begin
if (rst) begin
done <= 0;
count <= 0;
end else begin
if (count == 9) begin
done <= 1;
count <= 0;
end else begin
done <= 0;
count <= count + 1;
end
end
end
endmodule
| 6.94034 |
module block (
inp_north,
inp_west,
clk,
rst,
outp_south,
outp_east,
result
);
input [31:0] inp_north, inp_west;
output reg [31:0] outp_south, outp_east;
input clk, rst;
output reg [63:0] result;
wire [63:0] multi;
always @(posedge clk) begin
if (rst) begin
result <= 0;
outp_east <= 0;
outp_south <= 0;
end else begin
result <= result + multi;
outp_east <= inp_west;
outp_south <= inp_north;
end
end
assign multi = inp_north * inp_west;
endmodule
| 8.703735 |
module processing_element_systolic_4x4_fp (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
`ifdef complex_dsp
mac_fp_16 u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
`else
seq_mac_systolic_4x4_fp u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
`endif
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module FPMult_PrepModule_systolic_4x4_fp (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule_systolic_4x4_fp (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
// EXPONENT = 5
// EXPONENT -1 = 4
// NEED to subtract 2^4 -1 = 15
wire [`EXPONENT-1 : 0] bias;
assign bias = ((1 << (`EXPONENT - 1)) - 1);
assign RoundE = NormE - bias;
assign RoundEP = NormE - bias - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule_systolic_4x4_fp (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module fp16_to_fp32_systolic_4x4_fp (
input [15:0] a,
output [31:0] b
);
reg [31:0] b_temp;
reg [ 3:0] j;
reg [ 3:0] k;
reg [ 3:0] k_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[31] = a[15]; //sign bit
b_temp[30:0] = 31'b0;
end else begin
if (a[14 : 10] == 5'b0) begin //denormalized (covert to normalized)
for (j = 0; j <= 9; j = j + 1) begin
if (a[j] == 1'b1) begin
k_temp = j;
end
end
k = 9 - k_temp;
b_temp[22:0] = ((a[9:0] << (k + 1'b1)) & 10'h3FF) << 13;
b_temp[30:23] = 7'd127 - 4'd15 - k;
b_temp[31] = a[15];
end else if (a[14 : 10] == 5'b11111) begin //Infinity/ NAN
b_temp[22:0] = a[9:0] << 13;
b_temp[30:23] = 8'hFF;
b_temp[31] = a[15];
end else begin //Normalized Number
b_temp[22:0] = a[9:0] << 13;
b_temp[30:23] = 7'd127 - 4'd15 + a[14:10];
b_temp[31] = a[15];
end
end
end
assign b = b_temp;
endmodule
| 6.625109 |
module fp32_to_fp16_systolic_4x4_fp (
input [31:0] a,
output [15:0] b
);
reg [15:0] b_temp;
//integer j;
//reg [3:0]k;
always @(*) begin
if (a[30:0] == 15'b0) begin //signed zero
b_temp[15] = a[30]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
if (a[30 : 23] <= 8'd112 && a[30 : 23] >= 8'd103) begin //denormalized (covert to normalized)
b_temp[9:0] = {1'b1, a[22:13]} >> {8'd112 - a[30 : 23] + 1'b1};
b_temp[14:10] = 5'b0;
b_temp[15] = a[31];
end else if (a[30 : 23] == 8'b11111111) begin //Infinity/ NAN
b_temp[9:0] = a[22:13];
b_temp[14:10] = 5'h1F;
b_temp[15] = a[31];
end else begin //Normalized Number
b_temp[9:0] = a[22:13];
b_temp [14:10] = 4'd15 - 7'd127 + a[30:23]; //number should be in the range which can be depicted by fp16 (exp for fp32: 70h, 8Eh ; normalized exp for fp32: -15 to 15)
b_temp[15] = a[31];
end
end
end
assign b = b_temp;
endmodule
| 7.302343 |
module FPAddSub_single_systolic_4x4_fp (
clk,
rst,
a,
b,
operation,
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [31:0] a; // Input A, a 32-bit floating point number
input [31:0] b; // Input B, a 32-bit floating point number
input operation; // Operation select signal
// Output ports
output [31:0] result; // Result of the operation
output [4:0] flags; // Flags indicating exceptions according to IEEE754
reg [68:0] pipe_1;
reg [54:0] pipe_2;
reg [45:0] pipe_3;
//internal module wires
//output ports
wire Opout;
wire Sa;
wire Sb;
wire MaxAB;
wire [ 7:0] CExp;
wire [ 4:0] Shift;
wire [22:0] Mmax;
wire [ 4:0] InputExc;
wire [23:0] Mmin_3;
wire [32:0] SumS_5;
wire [ 4:0] Shift_1;
wire PSgn;
wire Opr;
wire [22:0] NormM; // Normalized mantissa
wire [ 8:0] NormE; // Adjusted exponent
wire ZeroSum; // Zero flag
wire NegE; // Flag indicating negative exponent
wire R; // Round bit
wire S; // Final sticky bit
wire FG;
FPAddSub_a_systolic_4x4_fp M1 (
a,
b,
operation,
Opout,
Sa,
Sb,
MaxAB,
CExp,
Shift,
Mmax,
InputExc,
Mmin_3
);
FPAddSub_b_systolic_4x4_fp M2 (
pipe_1[51:29],
pipe_1[23:0],
pipe_1[67],
pipe_1[66],
pipe_1[65],
pipe_1[68],
SumS_5,
Shift_1,
PSgn,
Opr
);
FPAddSub_c_systolic_4x4_fp M3 (
pipe_2[54:22],
pipe_2[21:17],
pipe_2[16:9],
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
FPAddSub_d_systolic_4x4_fp M4 (
pipe_3[13],
pipe_3[22:14],
pipe_3[45:23],
pipe_3[11],
pipe_3[10],
pipe_3[9],
pipe_3[8],
pipe_3[7],
pipe_3[6],
pipe_3[5],
pipe_3[12],
pipe_3[4:0],
result,
flags
);
always @(posedge clk) begin
if (rst) begin
pipe_1 <= 0;
pipe_2 <= 0;
pipe_3 <= 0;
end else begin
/*
pipe_1:
[68] Opout;
[67] Sa;
[66] Sb;
[65] MaxAB;
[64:57] CExp;
[56:52] Shift;
[51:29] Mmax;
[28:24] InputExc;
[23:0] Mmin_3;
*/
pipe_1 <= {Opout, Sa, Sb, MaxAB, CExp, Shift, Mmax, InputExc, Mmin_3};
/*
pipe_2:
[54:22]SumS_5;
[21:17]Shift;
[16:9]CExp;
[8]Sa;
[7]Sb;
[6]operation;
[5]MaxAB;
[4:0]InputExc
*/
pipe_2 <= {
SumS_5,
Shift_1,
pipe_1[64:57],
pipe_1[67],
pipe_1[66],
pipe_1[68],
pipe_1[65],
pipe_1[28:24]
};
/*
pipe_3:
[45:23] NormM ;
[22:14] NormE ;
[13]ZeroSum ;
[12]NegE ;
[11]R ;
[10]S ;
[9]FG ;
[8]Sa;
[7]Sb;
[6]operation;
[5]MaxAB;
[4:0]InputExc
*/
pipe_3 <= {
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG,
pipe_2[8],
pipe_2[7],
pipe_2[6],
pipe_2[5],
pipe_2[4:0]
};
end
end
endmodule
| 6.626859 |
module FPAddSub_b_systolic_4x4_fp (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
SumS_5,
Shift,
PSgn,
Opr
);
input [22:0] Mmax; // The larger mantissa
input [23:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
wire [32:0] Sum;
// Output ports
output [32:0] SumS_5; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 8'b00000000} - {Mmin, 8'b00000000}) : ({1'b1, Mmax, 8'b00000000} + {Mmin, 8'b00000000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[32] ? 5'b00000 :
Sum[31] ? 5'b00001 :
Sum[30] ? 5'b00010 :
Sum[29] ? 5'b00011 :
Sum[28] ? 5'b00100 :
Sum[27] ? 5'b00101 :
Sum[26] ? 5'b00110 :
Sum[25] ? 5'b00111 :
Sum[24] ? 5'b01000 :
Sum[23] ? 5'b01001 :
Sum[22] ? 5'b01010 :
Sum[21] ? 5'b01011 :
Sum[20] ? 5'b01100 :
Sum[19] ? 5'b01101 :
Sum[18] ? 5'b01110 :
Sum[17] ? 5'b01111 :
Sum[16] ? 5'b10000 :
Sum[15] ? 5'b10001 :
Sum[14] ? 5'b10010 :
Sum[13] ? 5'b10011 :
Sum[12] ? 5'b10100 :
Sum[11] ? 5'b10101 :
Sum[10] ? 5'b10110 :
Sum[9] ? 5'b10111 :
Sum[8] ? 5'b11000 :
Sum[7] ? 5'b11001 : 5'b11010
);
reg [32:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[16:0], 16'b0000000000000000} : Sum;
end
// Assign outputs
assign SumS_5 = Lvl1;
endmodule
| 6.823794 |
module FPAddSub_c_systolic_4x4_fp (
SumS_5,
Shift,
CExp,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [32:0] SumS_5; // Smaller mantissa after 16|12|8|4 shift
input [4:0] Shift; // Shift amount
// Input ports
input [7:0] CExp;
// Output ports
output [22:0] NormM; // Normalized mantissa
output [8:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
wire [3:0] Shift_1;
assign Shift_1 = Shift[3:0];
// Output ports
wire [32:0] SumS_7; // The smaller mantissa
reg [32:0] Lvl2;
wire [65:0] Stage1;
reg [32:0] Lvl3;
wire [65:0] Stage2;
integer i; // Loop variable
assign Stage1 = {SumS_5, SumS_5};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[32:0];
// Rotate by 4
2'b01: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift_1[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[32:0];
// Rotate by 1
2'b01: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign SumS_7 = Lvl3; // Take out smaller mantissa
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [8:0] ExpOF; // MSB set in sum indicates overflow
wire [8:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = SumS_7[32]; // Check MSB in unnormalized sum
assign ZeroSum = ~|SumS_7; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[8]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = SumS_7[31:9]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = SumS_7[8];
assign R = SumS_7[7];
assign S = |SumS_7[6:0];
endmodule
| 6.945986 |
module FPAddSub_d_systolic_4x4_fp (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
NegE,
InputExc,
P,
Flags
);
// Input ports
input ZeroSum; // Sum is zero
input [8:0] NormE; // Normalized exponent
input [22:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
input NegE; // Negative exponent?
input [4:0] InputExc; // Exceptions in inputs A and B
// Output ports
output [31:0] P; // Final result
output [4:0] Flags; // Exception flags
//
wire [31:0] Z; // Final result
wire EOF;
// Internal signals
wire [23:0] RoundUpM; // Rounded up sum with room for overflow
wire [22:0] RoundM; // The final rounded sum
wire [ 8:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire FSgn;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[22:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[23]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 8'b00000000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[7:0], RoundM[22:0]};
// Indicate exponent overflow
assign EOF = RoundE[8];
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[30:23]) & ~|(Z[30:23]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.659336 |
module processing_element_systolic_8x8 (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac_systolic_8x8 u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module quantize #(
parameter ARRAY_SIZE = 8,
parameter SRAM_DATA_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter OUTPUT_DATA_WIDTH = 16
) (
input signed [ARRAY_SIZE*(DATA_WIDTH+DATA_WIDTH+5)-1:0] ori_data,
output reg signed [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] quantized_data
);
localparam max_val = 32767, min_val = -32768;
localparam ORI_WIDTH = DATA_WIDTH + DATA_WIDTH + 5;
reg signed [ORI_WIDTH-1:0] ori_shifted_data;
integer i;
//quantize the data from 32 bit(16: integer, 8: precision) to 16 bit(8: integer, 8: precision)
always @* begin
for (i = 0; i < ARRAY_SIZE; i = i + 1) begin
ori_shifted_data = ori_data[i*ORI_WIDTH+:ORI_WIDTH];
if (ori_shifted_data >= max_val)
quantized_data[i*OUTPUT_DATA_WIDTH+:OUTPUT_DATA_WIDTH] = max_val;
else if (ori_shifted_data <= min_val)
quantized_data[i*OUTPUT_DATA_WIDTH+:OUTPUT_DATA_WIDTH] = min_val;
else
quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = ori_shifted_data[OUTPUT_DATA_WIDTH-1:0];
end
end
endmodule
| 8.510663 |
module
//==================================================================
module systolic_array_controller
#(parameter DATA_WIDTH = 32, DATA_SIZE = 8, DIM_SIZE = 4)
(clk,
rst_n,
sys_arr_ena,
clk_count,
go_bit,
done_bit); // port list
//==================================================================
// Declarations
//==================================================================
// I/O declarations
input wire clk; // clock
input wire rst_n; //Async reset
input wire go_bit; //go bit from riskv
output reg [3:0]clk_count;
input wire done_bit;
output reg sys_arr_ena; //enable to systolic array
// end I/O declarations
// inner wiring declarations
// end inner wiring declarations
//inner registers declarations
//end inner registers declarations
//assign initial values
initial begin
sys_arr_ena = 0;
clk_count[3:0] = 0;
end
//end assigning initial values
//==================================================================
// End Declarations
//==================================================================
//==================================================================
// Structural coding
//==================================================================
//==================================================================
// End Structural coding
//==================================================================
//==================================================================
// Structural Behavior
//==================================================================
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
clk_count[3:0] <= 4'b0000;
sys_arr_ena <= 0;
end//end if rst_n
else begin
if(go_bit && sys_arr_ena==0 && done_bit == 0) begin
sys_arr_ena <= 1;
clk_count[3:0] <= 4'b0000;
end
else if (sys_arr_ena) begin
clk_count <= clk_count+1;
end
if (done_bit) begin
sys_arr_ena <= 0;
clk_count[3:0] <= 4'b0000;
end
end // end if rst_n == 1
end // end always
//==================================================================
// End Structural Behavior
//==================================================================
endmodule
| 7.574158 |
module systolic_array_pe #(
parameter input_width = 8
) (
input clk,
reset, // sync active high reset
input [0:input_width - 1] in_a,
in_b,
output [0:input_width - 1] out_a,
out_b,
output [0:2 * input_width - 1] out_c
);
reg [0:input_width - 1] a_r, b_r;
reg [0:2 * input_width - 1] c_r; // output register for a, b, c;
always @(posedge clk) begin
if (reset) {a_r, b_r, c_r} <= 0;
else begin
a_r <= in_a;
b_r <= in_b;
c_r <= in_a * in_b + c_r;
end
end
assign out_a = a_r;
assign out_b = b_r;
assign out_c = c_r;
endmodule
| 6.94034 |
module systolic_array_sim_netlist ();
integer i, j;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in_A;
reg [7:0] shift_in_B;
wire [7:0] shift_out;
wire ack;
systolic_array test //top封装
(
.clk_p (clk),
.rstn_p(rstn),
.en_p (en),
.p_shift_in_A(shift_in_A),
.p_shift_in_B(shift_in_B),
.p_shift_out(shift_out),
.ack_p(ack)
);
/*
样例：
1. A = {
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
}
B = {
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
}
C = {
30 30 30 30
30 30 30 30
30 30 30 30
30 30 30 30
}
(done)
2. D = {
1 1 1 1
1 0 0 1
1 0 0 1
1 1 1 1
}
E = {
12 14 16 18
20 22 24 26
28 30 32 34
36 38 40 42
}
F = {
96 104 112 120
48 52 56 60
48 52 56 60
96 104 112 120
}
(done)
3. G = {
0 3 6 9
12 15 18 21
24 27 30 33
36 39 42 45
}
H = {
2 0 0 1
0 2 1 0
0 1 2 0
1 0 0 2
}
I = {
9 12 15 18
45 48 51 54
81 84 87 90
117 120 123 126
}
*/
//sdf反标
initial begin
$sdf_annotate("/bks2/PB20000328/ic_design/apr/result/systolic_array.output.sdf", test);
end
integer A[0:15];
integer B[0:15];
integer D[0:15];
integer E[0:15];
integer H[0:15];
integer I[0:15];
//矩阵输入
initial begin
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
A[i*4+j] = j + 1;
B[i*4+j] = i + 1;
if (i == 0 || i == 3 || j == 0 || j == 3) D[i*4+j] = 1;
else D[i*4+j] = 0;
E[i*4+j] = 2 * (i * 4 + j) + 12;
H[i*4+j] = 3 * (i * 4 + j);
if (i == j) I[i*4+j] = 2;
else if (i + j == 3) I[i*4+j] = 1;
else I[i*4+j] = 0;
end
end
//integer C[0:15]
/*integer REF1[0:15] = {
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30
};*/
//integer F[0:15];
/*integer REF2[0:15] = {
96, 104, 112, 120,
48, 52, 56, 60,
48, 52, 56, 60,
96, 104, 112, 120
};*/
//测试代码
//warning: 本版测试代码假设每个周期都会在每个buffer里填充一个数据，共4个周期（后期取决于sram驱动来修改）
//warning: 本版测试代码不含FSM，由人为自行控制
//时钟生成
parameter clk_period = 40;
initial begin
clk = 1;
forever #(clk_period / 2) clk = ~clk;
end
initial begin
//初始化系统
rstn = 0;
$monitor("T=%5d, out=%d, ack=%d", $time, shift_out, ack);
$monitoron;
//测试使用
en = 0;
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = A[i*4+3-j];
shift_in_B = B[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第二次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = D[i*4+3-j];
shift_in_B = E[(3-j)*4+i];
end
//计算
en = 0;
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第三次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1;
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = H[i*4+3-j];
shift_in_B = I[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
$monitoroff;
$finish;
end
endmodule
| 6.94034 |
module systolic_array_sim_top ();
integer i, j, k;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in;
wire [7:0] shift_out;
wire ack;
systolic_array test //top封装
(
.clk_p (clk),
.rstn_p(rstn),
.en_p (en),
.p_shift_in(shift_in),
.p_shift_out(shift_out),
.ack_p(ack)
);
/*
样例：
1. A = {
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
}
B = {
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
}
C = {
30 30 30 30
30 30 30 30
30 30 30 30
30 30 30 30
}
(done)
2. D = {
1 1 1 1
1 0 0 1
1 0 0 1
1 1 1 1
}
E = {
12 14 16 18
20 22 24 26
28 30 32 34
36 38 40 42
}
F = {
96 104 112 120
48 52 56 60
48 52 56 60
96 104 112 120
}
(done)
3. G = {
0 3 6 9
12 15 18 21
24 27 30 33
36 39 42 45
}
H = {
2 0 0 1
0 2 1 0
0 1 2 0
1 0 0 2
}
I = {
9 12 15 18
45 48 51 54
81 84 87 90
117 120 123 126
}
*/
integer A[0:15];
integer B[0:15];
integer D[0:15];
integer E[0:15];
integer H[0:15];
integer I[0:15];
//矩阵输入
initial begin
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
A[i*4+j] = j + 1;
B[i*4+j] = i + 1;
if (i == 0 || i == 3 || j == 0 || j == 3) D[i*4+j] = 1;
else D[i*4+j] = 0;
E[i*4+j] = 2 * (i * 4 + j) + 12;
H[i*4+j] = 3 * (i * 4 + j);
if (i == j) I[i*4+j] = 2;
else if (i + j == 3) I[i*4+j] = 1;
else I[i*4+j] = 0;
end
end
//integer C[0:15]
/*integer REF1[0:15] = {
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30
};*/
//integer F[0:15];
/*integer REF2[0:15] = {
96, 104, 112, 120,
48, 52, 56, 60,
48, 52, 56, 60,
96, 104, 112, 120
};*/
//测试代码
//warning: 本版测试代码假设每个周期都会在每个buffer里填充一个数据，共4个周期（后期取决于sram驱动来修改）
//时钟生成
parameter clk_period = 20;
initial begin
clk = 1;
forever #(clk_period / 2) clk = ~clk;
end
initial begin
//初始化系统
rstn = 0;
$monitor(
"T=%5d, out=%d, state=%d, state_load_AB=%d, state_load_id=%d, state_load_row=%d, state_compute_pump=%d, state_compute_out=%d, state_compute_out_counter=%d, ack=%d",
$time, shift_out, test.SA.ctrl.state_overall, test.SA.ctrl.state_load_AB,
test.SA.ctrl.state_load_id, test.SA.ctrl.state_load_row, test.SA.ctrl.state_compute_pump,
test.SA.ctrl.state_compute_out, test.SA.ctrl.state_compute_out_counter, ack);
$monitoron;
//测试使用
en = 0;
shift_in = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (k = 0; k < 2; k = k + 1)
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
if (k == 0) shift_in = A[i*4+3-j];
else shift_in = B[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 40; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第二次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (k = 0; k < 2; k = k + 1)
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
if (k == 0) shift_in = D[i*4+3-j];
else shift_in = E[(3-j)*4+i];
end
//计算
en = 0;
for (i = 0; i < 40; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第三次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in = 0;
#40 rstn = 1;
en = 1;
//装载数据
for (k = 0; k < 2; k = k + 1)
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
if (k == 0) shift_in = H[i*4+3-j];
else shift_in = I[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 40; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
$monitoroff;
$finish;
end
endmodule
| 6.94034 |
module systolic_array_sim_without_control ();
integer i, j;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in_A;
reg [7:0] shift_in_B;
wire [7:0] shift_out;
systolic_array_wrapper test //脉动阵列封装
(
.clk (clk),
.rstn(rstn),
.en (en),
.shift_in_A(shift_in_A),
.shift_in_B(shift_in_B),
.shift_out(shift_out)
);
/*
样例：
1. A = {
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
}
B = {
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
}
C = {
30 30 30 30
30 30 30 30
30 30 30 30
30 30 30 30
}
(done)
2. D = {
1 1 1 1
1 0 0 1
1 0 0 1
1 1 1 1
}
E = {
12 14 16 18
20 22 24 26
28 30 32 34
36 38 40 42
}
F = {
96 104 112 120
48 52 56 60
48 52 56 60
96 104 112 120
}
(done)
3. G = {
0 3 6 9
12 15 18 21
24 27 30 33
36 39 42 45
}
H = {
2 0 0 1
0 2 1 0
0 1 2 0
1 0 0 2
}
I = {
9 12 15 18
45 48 51 54
81 84 87 90
117 120 123 126
}
*/
integer A[0:15];
integer B[0:15];
integer D[0:15];
integer E[0:15];
integer H[0:15];
integer I[0:15];
//矩阵输入
initial begin
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
A[i*4+j] = j + 1;
B[i*4+j] = i + 1;
if (i == 0 || i == 3 || j == 0 || j == 3) D[i*4+j] = 1;
else D[i*4+j] = 0;
E[i*4+j] = 2 * (i * 4 + j) + 12;
H[i*4+j] = 3 * (i * 4 + j);
if (i == j) I[i*4+j] = 2;
else if (i + j == 3) I[i*4+j] = 1;
else I[i*4+j] = 0;
end
end
//integer C[0:15]
/*integer REF1[0:15] = {
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30,
30, 30, 30, 30
};*/
//integer F[0:15];
/*integer REF2[0:15] = {
96, 104, 112, 120,
48, 52, 56, 60,
48, 52, 56, 60,
96, 104, 112, 120
};*/
//测试代码
//warning: 本版测试代码假设每个周期都会在每个buffer里填充一个数据，共4个周期（后期取决于sram驱动来修改）
//warning: 本版测试代码不含FSM，由人为自行控制
//时钟生成
parameter clk_period = 20;
initial begin
clk = 1;
forever #(clk_period / 2) clk = ~clk;
end
initial begin
//初始化系统
rstn = 0;
$monitor(
"T=%5d, out=%d, state=%d, state_load_id=%d, state_load_row=%d, state_compute_pump=%d, state_compute_out=%d, state_compute_out_counter=%d",
$time, shift_out, test.ctrl.state_overall, test.ctrl.state_load_id,
test.ctrl.state_load_row, test.ctrl.state_compute_pump, test.ctrl.state_compute_out,
test.ctrl.state_compute_out_counter);
$monitoron;
//测试使用
en = 0;
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = A[i*4+3-j];
shift_in_B = B[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第二次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1; //启动
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = D[i*4+3-j];
shift_in_B = E[(3-j)*4+i];
end
//计算
en = 0;
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
//第三次实验
//初始化系统
#clk_period rstn = 0;
//测试使用
shift_in_A = 0;
shift_in_B = 0;
#40 rstn = 1;
en = 1;
//装载数据
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
#clk_period;
shift_in_A = H[i*4+3-j];
shift_in_B = I[(3-j)*4+i];
end
en = 0;
//计算
for (i = 0; i < 15; i = i + 1) #clk_period;
//输出
#(20 * clk_period);
$monitoroff;
$finish;
end
endmodule
| 6.94034 |
module systolic_array_tb ();
parameter IN_WORD_SIZE = 8;
parameter OUT_WORD_SIZE = 24; //Changed this
parameter ARR_ROWS = 8;
parameter ARR_COLS = 8;
reg clk;
reg rst;
// Changed the following
reg [IN_WORD_SIZE-1:0] left_inputs[0:ARR_ROWS * ARR_COLS -1];
reg [IN_WORD_SIZE-1:0] top_inputs[0:ARR_COLS * ARR_ROWS -1];
//Changed the following to reg
reg [IN_WORD_SIZE * ARR_ROWS-1:0] left_inputs_wire;
reg [IN_WORD_SIZE * ARR_COLS-1:0] top_inputs_wire;
wire compute_done_out;
wire [OUT_WORD_SIZE-1:0] cycles_count_out;
wire [0:OUT_WORD_SIZE * ARR_ROWS*ARR_COLS-1] pe_register_vals_wire;
wire [OUT_WORD_SIZE-1:0] pe_register_vals_mem[0:ARR_ROWS*ARR_COLS-1];
wire [511:0] tie_low;
wire [511:0] tie_high;
integer i, j;
integer row, col;
//Block to hint generation of waveforms
initial begin
$vcdplusfile("systolic_array.vcd");
$vcdplusmemon();
$vcdpluson();
end
//Initialize the design
initial begin
clk = 0;
rst = 1;
row = -1;
col = -1;
#20 rst = 0;
end
// Read the input matrices from file and populate the memory
initial $readmemh(`INPUTL, left_inputs);
initial $readmemh(`INPUTT, top_inputs);
//Free running clk
always #5 clk = ~clk;
assign tie_low = 512'b0;
assign tie_high = ~tie_low;
genvar r, c;
generate
for (r = 0; r < ARR_ROWS; r = r + 1) begin
always @(posedge clk) begin
if (rst == 1'b1) begin
left_inputs_wire[(r+1)*IN_WORD_SIZE-1-:(IN_WORD_SIZE)] <= tie_low[IN_WORD_SIZE-1:0];
end else begin
if (col < ARR_COLS) begin
left_inputs_wire[(r+1)*IN_WORD_SIZE-1-:(IN_WORD_SIZE)] <= left_inputs[(col*ARR_ROWS)+r];
end else begin
left_inputs_wire[(r+1)*IN_WORD_SIZE-1-:(IN_WORD_SIZE)] <= tie_low[IN_WORD_SIZE-1:0];
end
end
end
end
endgenerate
generate
for (c = 0; c < ARR_COLS; c = c + 1) begin
always @(posedge clk) begin
if (rst == 1'b1) begin
top_inputs_wire[(c+1)*IN_WORD_SIZE-1-:IN_WORD_SIZE] <= tie_low[IN_WORD_SIZE-1:0];
end else begin
if (row < ARR_ROWS) begin
top_inputs_wire[(c+1)*IN_WORD_SIZE-1-:IN_WORD_SIZE] <= top_inputs[(row*ARR_COLS)+c];
end else begin
top_inputs_wire[(c+1)*IN_WORD_SIZE-1-:IN_WORD_SIZE] <= tie_low[IN_WORD_SIZE-1:0];
end
end
end
end
endgenerate
always @(posedge clk) begin
if (rst == 1'b1) begin
row = -1;
col = -1;
end else begin
row = row + 1;
col = col + 1;
end
end
generate
for (r = 0; r < ARR_ROWS * ARR_COLS; r++) begin
assign pe_register_vals_mem[r] = pe_register_vals_wire[r*OUT_WORD_SIZE:(r+1)*OUT_WORD_SIZE-1];
end
endgenerate
// Display code
always @(posedge clk) begin
if (compute_done_out == 1'b1) begin
for (i = 0; i < ARR_ROWS; i = i + 1) begin
for (j = 0; j < ARR_COLS; j = j + 1) begin
$write("%h ", pe_register_vals_mem[i*ARR_ROWS+j]);
end
$write("\n");
//$write("Left: %h\n",left_inputs[i]);
end
$write("Cycles: %h\n", cycles_count_out);
$finish;
end
end
systolic_array #(
.IN_WORD_SIZE(IN_WORD_SIZE),
.OUT_WORD_SIZE(OUT_WORD_SIZE),
.NUM_ROW(ARR_ROWS),
.NUM_COL(ARR_COLS)
) dut (
.clk(clk),
.rst(rst),
.left_inputs(left_inputs_wire),
.top_inputs(top_inputs_wire),
.compute_done(compute_done_out),
.cycles_count(cycles_count_out),
.pe_register_vals(pe_register_vals_wire)
);
always #10000 $finish;
endmodule
| 6.94034 |
module systolic_array_with_skew #(
parameter IFMAP_WIDTH = 16,
parameter WEIGHT_WIDTH = 16,
parameter OFMAP_WIDTH = 32,
parameter ARRAY_HEIGHT = 4,
parameter ARRAY_WIDTH = 4
) (
input clk,
input rst_n,
input en,
input weight_en,
input weight_wen[ARRAY_HEIGHT - 1 : 0],
input signed [IFMAP_WIDTH - 1 : 0] ifmap_in[ARRAY_HEIGHT - 1 : 0],
input signed [WEIGHT_WIDTH - 1 : 0] weight_in[ARRAY_WIDTH - 1 : 0],
input signed [OFMAP_WIDTH - 1 : 0] ofmap_in[ARRAY_WIDTH - 1 : 0],
output signed [OFMAP_WIDTH - 1 : 0] ofmap_out[ARRAY_WIDTH - 1 : 0]
);
wire signed [IFMAP_WIDTH - 1 : 0] ifmap[ARRAY_HEIGHT - 1 : 0];
wire signed [OFMAP_WIDTH - 1 : 0] ofmap[ARRAY_WIDTH - 1 : 0];
wire signed [OFMAP_WIDTH - 1 : 0] ofmap_reversed[ARRAY_WIDTH - 1 : 0];
wire signed [OFMAP_WIDTH - 1 : 0] ofmap_out_reversed[ARRAY_WIDTH - 1 : 0];
skew_registers #(
.DATA_WIDTH(IFMAP_WIDTH),
.N(ARRAY_HEIGHT)
) ifmap_skew_registers (
.clk(clk),
.rst_n(rst_n),
.en(en),
.din(ifmap_in),
.dout(ifmap)
);
systolic_array #(
.IFMAP_WIDTH (IFMAP_WIDTH),
.WEIGHT_WIDTH(WEIGHT_WIDTH),
.OFMAP_WIDTH (OFMAP_WIDTH),
.ARRAY_HEIGHT(ARRAY_HEIGHT),
.ARRAY_WIDTH (ARRAY_WIDTH)
) systolic_array_inst (
.clk(clk),
.rst_n(rst_n),
.en(en),
.weight_en(weight_en),
.weight_wen(weight_wen),
.ifmap_in(ifmap),
.weight_in(weight_in),
.ofmap_in(ofmap_in),
.ofmap_out(ofmap)
);
skew_registers #(
.DATA_WIDTH(OFMAP_WIDTH),
.N(ARRAY_WIDTH)
) ofmap_skew_registers (
.clk(clk),
.rst_n(rst_n),
.en(en),
.din(ofmap_reversed),
.dout(ofmap_out_reversed)
);
genvar x;
generate
for (x = 0; x < ARRAY_WIDTH; x++) begin : reverse
// Because the 0th entry in the array must be delayed the most which is
// opposite from the way the skew resgiters are generated, so we just
// flip the inputs to them
assign ofmap_reversed[x] = ofmap[ARRAY_WIDTH-1-x];
assign ofmap_out[x] = ofmap_out_reversed[ARRAY_WIDTH-1-x];
end
endgenerate
endmodule
| 6.94034 |
module systolic_array_wrapper //脉动阵列封装
(
input clk,
input rstn,
input OutputSign,
input load, //load使能信号
input shift, //shift使能信号
//测试使用
input [2:0] id_A_0,
input [2:0] id_A_1,
input [2:0] id_A_2,
input [2:0] id_A_3,
//load_B的位置
input [2:0] id_B_0,
input [2:0] id_B_1,
input [2:0] id_B_2,
input [2:0] id_B_3,
input [7:0] shift_in_A_0,
input [7:0] shift_in_A_1,
input [7:0] shift_in_A_2,
input [7:0] shift_in_A_3,
input [7:0] shift_in_B_0,
input [7:0] shift_in_B_1,
input [7:0] shift_in_B_2,
input [7:0] shift_in_B_3,
output [7:0] shift_out_0,
output [7:0] shift_out_1,
output [7:0] shift_out_2,
output [7:0] shift_out_3
);
wire [7:0] row_0;
wire [7:0] row_1;
wire [7:0] row_2;
wire [7:0] row_3;
wire [7:0] col_0;
wire [7:0] col_1;
wire [7:0] col_2;
wire [7:0] col_3;
PEarray core (
.rstn(rstn),
.input_row_0(row_0),
.input_row_1(row_1),
.input_row_2(row_2),
.input_row_3(row_3),
.input_col_0(col_0),
.input_col_1(col_1),
.input_col_2(col_2),
.input_col_3(col_3),
.output_row_0(shift_out_0),
.output_row_1(shift_out_1),
.output_row_2(shift_out_2),
.output_row_3(shift_out_3),
.clk(clk),
.OutputSign(OutputSign) //pe计算结果移位输出使能信号
);
shift_buffer A_0 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_A_0), //load的位置
.shift_in (shift_in_A_0),
.shift_out(row_0)
);
shift_buffer A_1 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_A_1), //load的位置
.shift_in (shift_in_A_1),
.shift_out(row_1)
);
shift_buffer A_2 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_A_2), //load的位置
.shift_in (shift_in_A_2),
.shift_out(row_2)
);
shift_buffer A_3 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_A_3), //load的位置
.shift_in (shift_in_A_3),
.shift_out(row_3)
);
shift_buffer B_0 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_B_0), //load的位置
.shift_in (shift_in_B_0),
.shift_out(col_0)
);
shift_buffer B_1 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_B_1), //load的位置
.shift_in (shift_in_B_1),
.shift_out(col_1)
);
shift_buffer B_2 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_B_2), //load的位置
.shift_in (shift_in_B_2),
.shift_out(col_2)
);
shift_buffer B_3 (
.rstn(rstn),
.clk (clk),
.load(load), //load使能信号
.shift(shift), //shift使能信号
.id(id_B_3), //load的位置
.shift_in (shift_in_B_3),
.shift_out(col_3)
);
endmodule
| 6.94034 |
module systolic_array_wrapper //脉动阵列封装
(
input clk,
input rstn,
input en, //协处理器启动信号
input [7:0] shift_in,
output [7:0] shift_out,
output ack //示意结束
);
wire [7:0] row_0;
wire [7:0] row_1;
wire [7:0] row_2;
wire [7:0] row_3;
wire [7:0] col_0;
wire [7:0] col_1;
wire [7:0] col_2;
wire [7:0] col_3;
//load_A的位置
wire [2:0] id_A;
wire [1:0] row_A;
//load_B的位置
wire [2:0] id_B;
wire [1:0] row_B;
//shift_buffer使能信号
wire load_A_0;
wire load_A_1;
wire load_A_2;
wire load_A_3;
wire load_A;
wire load_B;
assign load_A_0 = load_A & (row_A == 2'b00);
assign load_A_1 = load_A & (row_A == 2'b01);
assign load_A_2 = load_A & (row_A == 2'b10);
assign load_A_3 = load_A & (row_A == 2'b11);
wire load_B_0;
wire load_B_1;
wire load_B_2;
wire load_B_3;
assign load_B_0 = load_B & (row_B == 2'b00);
assign load_B_1 = load_B & (row_B == 2'b01);
assign load_B_2 = load_B & (row_B == 2'b10);
assign load_B_3 = load_B & (row_B == 2'b11);
wire shift;
wire OutputSign;
wire [1:0] row_out;
wire rstn_pe;
assign rstn_pe = ((id_A == 2'b11 && row_A == 2'b11) || rstn == 0) ? 0 : 1'b1;
assign ack = OutputSign;
controller ctrl (
.rstn(rstn),
.clk (clk),
.en (en),
.OutputSign(OutputSign), //pe计算结果移位输出使能信号
//load使能信号
.load_A(load_A),
.load_B(load_B),
.shift(shift), //shift使能信号
.id_A (id_A),
.row_A(row_A),
.id_B (id_B),
.row_B(row_B),
.row_out(row_out)
);
PEarray core (
.rstn(rstn_pe),
.input_row_0(row_0),
.input_row_1(row_1),
.input_row_2(row_2),
.input_row_3(row_3),
.input_col_0(col_0),
.input_col_1(col_1),
.input_col_2(col_2),
.input_col_3(col_3),
.output_row(shift_out),
.row_out(row_out),
.clk(clk),
.OutputSign(OutputSign) //pe计算结果移位输出使能信号
);
shift_buffer A_0 (
.rstn(rstn),
.clk (clk),
.load(load_A_0), //load使能信号
.shift(shift), //shift使能信号
.id(id_A), //load的位置
.shift_in (shift_in),
.shift_out(row_0)
);
shift_buffer A_1 (
.rstn(rstn),
.clk (clk),
.load(load_A_1), //load使能信号
.shift(shift), //shift使能信号
.id(id_A), //load的位置
.shift_in (shift_in),
.shift_out(row_1)
);
shift_buffer A_2 (
.rstn(rstn),
.clk (clk),
.load(load_A_2), //load使能信号
.shift(shift), //shift使能信号
.id(id_A), //load的位置
.shift_in (shift_in),
.shift_out(row_2)
);
shift_buffer A_3 (
.rstn(rstn),
.clk (clk),
.load(load_A_3), //load使能信号
.shift(shift), //shift使能信号
.id(id_A), //load的位置
.shift_in (shift_in),
.shift_out(row_3)
);
shift_buffer B_0 (
.rstn(rstn),
.clk (clk),
.load(load_B_0), //load使能信号
.shift(shift), //shift使能信号
.id(id_B), //load的位置
.shift_in (shift_in),
.shift_out(col_0)
);
shift_buffer B_1 (
.rstn(rstn),
.clk (clk),
.load(load_B_1), //load使能信号
.shift(shift), //shift使能信号
.id(id_B), //load的位置
.shift_in (shift_in),
.shift_out(col_1)
);
shift_buffer B_2 (
.rstn(rstn),
.clk (clk),
.load(load_B_2), //load使能信号
.shift(shift), //shift使能信号
.id(id_B), //load的位置
.shift_in (shift_in),
.shift_out(col_2)
);
shift_buffer B_3 (
.rstn(rstn),
.clk (clk),
.load(load_B_3), //load使能信号
.shift(shift), //shift使能信号
.id(id_B), //load的位置
.shift_in (shift_in),
.shift_out(col_3)
);
endmodule
| 6.94034 |
module systolic_ctrl #(
parameter PE_ROW_NUM = 4,
parameter PE_COL_NUM = 4,
parameter DATA_WIDTH = 32,
parameter KERNEL_SIZE = 9
) (
input clk,
input rst_n,
input start,
output reg cal_done,
// to pe matrix
output res_shift,
output [PE_ROW_NUM-1:0] res_valid
);
wire valid;
reg [31:0] counter;
reg [PE_ROW_NUM-1:0] valid_reg;
reg enable;
// ****************************
// data input/output control
// ****************************
// ****************************
// systolic calculation control
// ****************************
always @(posedge clk or negedge rst_n)
if (~rst_n) enable <= 1'b0;
else if (start) enable <= 1'b1;
else if (cal_done) enable <= 1'b0;
always @(posedge clk or negedge rst_n)
if (~rst_n) counter <= 32'b0;
else if (enable) counter <= counter + 1'b1;
else counter <= 32'b0;
assign res_shift = counter > (KERNEL_SIZE+PE_COL_NUM+2) &&
counter < (KERNEL_SIZE+PE_COL_NUM+PE_ROW_NUM+2);
assign valid = counter > (KERNEL_SIZE+PE_COL_NUM+1) &&
counter < (KERNEL_SIZE+PE_COL_NUM+PE_ROW_NUM+2);
wire cal_done_wire = counter == (KERNEL_SIZE + PE_COL_NUM + PE_ROW_NUM + 1);
always @(posedge clk)
if (~rst_n) cal_done <= 1'b0;
else cal_done <= cal_done_wire;
genvar i;
always @(*) valid_reg[0] = valid;
generate
for (i = 1; i < PE_ROW_NUM; i = i + 1) begin : result_valid
always @(posedge clk) valid_reg[i] <= valid_reg[i-1];
end
endgenerate
assign res_valid = valid_reg;
endmodule
| 6.602816 |
module systolic_cube_without_fifo #(
parameter ARRAY_NUM = 3,
parameter BLOCK_NUM = 3,
parameter CUBE_NUM = 3, // dont change CUBE_NUM
parameter RAM_DEPTH = 2048
) (
input wire iClk,
input wire iRst,
input wire iStart,
output wire oReady,
output wire [$clog2(RAM_DEPTH)-1:0] oAddrForDataWeightRam,
input wire [ 31:0] iDataFromDataRam,
input wire [ 31:0] iWeightFromWeightRam,
output wire oWrEnForResultRam,
output wire [$clog2(RAM_DEPTH)-1:0] oAddrForResultRam,
output wire [ 31:0] oDataToResultRam
);
wire clear_acc;
wire [ ARRAY_NUM-2:0] pass_data_left;
wire [ 3*ARRAY_NUM-1:0] input_pattern;
wire [8*ARRAY_NUM*BLOCK_NUM*CUBE_NUM-1:0] result;
wire [ ARRAY_NUM*BLOCK_NUM*CUBE_NUM-1:0] result_valid;
wire data_from_ram_valid;
wire [ ARRAY_NUM*BLOCK_NUM*CUBE_NUM-1:0] result_fifo_empty;
wire [ ARRAY_NUM*BLOCK_NUM*CUBE_NUM-1:0] result_fifo_rd_en;
wire [ 7:0] result_from_fifo [0:ARRAY_NUM*BLOCK_NUM*CUBE_NUM-1];
wire [ 2:0] result_fifo_sel;
assign oDataToResultRam = (result_fifo_sel == 'd0) ? {result_from_fifo[3], result_from_fifo[2], result_from_fifo[1], result_from_fifo[0]} :
(result_fifo_sel == 'd1) ? {result_from_fifo[7], result_from_fifo[6], result_from_fifo[5], result_from_fifo[4]} :
(result_fifo_sel == 'd2) ? {result_from_fifo[11], result_from_fifo[10], result_from_fifo[9], result_from_fifo[8]} :
(result_fifo_sel == 'd3) ? {result_from_fifo[15], result_from_fifo[14], result_from_fifo[13], result_from_fifo[12]} :
(result_fifo_sel == 'd4) ? {result_from_fifo[19], result_from_fifo[18], result_from_fifo[17], result_from_fifo[16]} :
(result_fifo_sel == 'd5) ? {result_from_fifo[23], result_from_fifo[22], result_from_fifo[21], result_from_fifo[20]} :
(result_fifo_sel == 'd6) ? {7'd0, result_from_fifo[26], result_from_fifo[25], result_from_fifo[24]} : 'd0;
generate
genvar i;
for (i = 0; i < ARRAY_NUM * BLOCK_NUM * CUBE_NUM; i = i + 1) begin : unname100
FIFO result_fifo_i (
.clock(iClk),
.reset(iRst),
.io_din(result[8*(i+1)-1:8*i]),
.io_wr_en(result_valid[i]),
.io_rd_en(result_fifo_rd_en[i]),
.io_dout(result_from_fifo[i]),
.io_empty(result_fifo_empty[i])
);
end
endgenerate
micro_controller #(
.ARRAY_NUM(ARRAY_NUM),
.BLOCK_NUM(BLOCK_NUM),
.CUBE_NUM (CUBE_NUM),
.RAM_DEPTH(RAM_DEPTH)
) micro_controller_i (
.iClk(iClk),
.iRst(iRst),
.iStart(iStart),
.oReady(oReady),
.oClearAcc(clear_acc),
.oInputPattern(input_pattern),
.oPassDataLeft(pass_data_left),
.oDataRdValid(data_from_ram_valid),
.oAddrRd(oAddrForDataWeightRam),
.iAllResultFifoHasData(~(|result_fifo_empty)),
.oResultRdEn(result_fifo_rd_en),
.oWriteEn(oWrEnForResultRam),
.oAddrWr(oAddrForResultRam),
.oResultFifoSel(result_fifo_sel)
);
pe_cube #(
.ARRAY_NUM(ARRAY_NUM),
.BLOCK_NUM(BLOCK_NUM),
.CUBE_NUM (CUBE_NUM)
) pe_cube_i (
.iClk(iClk),
.iRst(iRst),
.iClearAcc(clear_acc),
.iWeight(data_from_ram_valid ? iWeightFromWeightRam[23:0] : 24'd0),
.iData1(data_from_ram_valid ? iDataFromDataRam[23:0] : 24'd0),
.iData2(data_from_ram_valid ? iDataFromDataRam[31:24] : 8'd0),
.iCfsInputPattern(input_pattern),
.iCfsPassDataLeft(pass_data_left),
.iCfsOutputLeftShift(data_from_ram_valid ? iWeightFromWeightRam[28:24] : 5'd0),
.oResult(result),
.oResultValid(result_valid)
);
endmodule
| 7.265994 |
module of the N bit digital-serial systolic multiplier.
@Author: Jinyu Xie, Wenzhao Xie, Yuteng Huang, Hao Sun.
@Date: 2018/11/21
*/
`include "configuration.vh"
module systolic_multiplier(
input wire clk,
input wire rst_n,
input wire start,
input wire [`DATA_WIDTH - 1 : 0] a,
input wire [`DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [`DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = `DATA_WIDTH / `N_DIGITAL;
parameter BWIDTH = (ITERATION_NUMBER + 1)*`N_DIGITAL;
parameter IDLE = 2'b00;
parameter CAL = 2'b01;
parameter DONE = 2'b10;
reg state;
reg [12:0] counter;
reg [`DATA_WIDTH - 1 : 0] reg_a;
reg [`DATA_WIDTH - 1 : 0] reg_g;
reg [BWIDTH - 1:0] reg_b;
wire [`N_DIGITAL - 1:0] N_bit_b_in;
wire [`DATA_WIDTH - 1 : 0] out_t_i_j;
wire wire_done;
N_bit_wrapper inst(
.clk(clk),
.rst_n(rst_n),
.start(start),
.a(reg_a),
.g(reg_g),
.b(N_bit_b_in),
.t_i_j(out_t_i_j),
.done(wire_done)
);
// done
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
done <= 0;
end else begin
case (wire_done)
1'b0: done <= 1'b0;
1'b1: done <= 1'b1;
default : done <= done;
endcase
end
end
// t_i_j
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
t_i_j <= 0;
end else begin
case (wire_done)
1'b0: t_i_j <= t_i_j;
1'b1: t_i_j <= out_t_i_j;
default : t_i_j <= t_i_j;
endcase
end
end
// counter
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 12'd0;
end
CAL: begin
if(counter < ITERATION_NUMBER)
counter <= counter + 1;
else
counter <= 12'd0;
end
default : counter <= 12'd0;
endcase
end
end
// N_bit_b_in
assign N_bit_b_in = reg_b[(ITERATION_NUMBER + 1 - counter)*`N_DIGITAL - 1 -: `N_DIGITAL];
// reg_a
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reg_a <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_a <= a;
else
reg_a <= 0;
end
default : reg_a <= reg_a;
endcase
end
end
// reg_b
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reg_b <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_b <= b;
else
reg_b <= 0;
end
default : reg_b <= reg_b;
endcase
end
end
// reg_g
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reg_g <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_g <= g;
else
reg_g <= 0;
end
default : reg_g <= reg_g;
endcase
end
end
// FSM
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
if(start) begin
state <= CAL;
end
else begin
state <= state;
end
end
CAL: begin
if (counter < ITERATION_NUMBER)
state <= CAL;
else
state <= DONE;
end
DONE: begin
state <= DONE;
end
default : state <= IDLE;
endcase
end
end
endmodule
| 7.400944 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module Systolic_Processor (
output wire [15:0] result,
output wire [15:0] next_row_operand,
output wire delayed_done,
input wire [15:0] operand1,
input wire [15:0] operand2,
input wire [15:0] previous_StageOperand,
input wire start,
input wire reset, //to reset the state machine
input wire clear, //to clear various registers
input wire clk
);
wire activate_BOOTH;
wire clr_result_reg;
wire clr_in_exp_reg;
wire clr_status_reg;
wire load_in_exp_reg;
// instantiation of DATAPATH
ProcessingElement_DATAPATH p0 (
.result(result),
.next_row_operand(next_row_operand),
.delayed_done(delayed_done),
.in1(operand1),
.in2(operand2),
.previous_StageOperand(previous_StageOperand),
.act_BOOTH(activate_BOOTH),
.clr_result_PIPO(clr_result_reg),
.clr_in_exp_PIPO(clr_in_exp_reg),
.clr_status_reg(clr_status_reg),
.load_in_exp_PIPO(load_in_exp_reg),
.clk(clk)
);
// instantiation of CONTROLLER
ProcessingElement_CONTROLLER p1 (
.act_BOOTH(activate_BOOTH),
.clr_in_exp_PIPO(clr_in_exp_reg),
.clr_result_PIPO(clr_result_reg),
.clr_status_reg(clr_status_reg),
.load_in_exp_PIPO(load_in_exp_reg),
.start(start),
// to reset the state machine
.rst(reset),
// to clear the various registers
.clr(clear),
.clk(clk)
);
endmodule
| 7.430204 |
module
/*
Authour: Wang Lei, National University of Defense Technology, P.R.China.
This is the top module of systolic array in our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang Lei of National University of Defense Technology, P.R.China
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module systolic_top #(
parameter PE_COL_NUM = 4,
parameter PE_ROW_NUM = 4,
parameter DATA_WIDTH = 16,
parameter REG_WIDTH = 16,
parameter KERNEL_SIZE = 9 // the actural data length of input and depth of weight
)
(
input clk,
input rst_n,
input start,
output cal_done,
input [PE_ROW_NUM*DATA_WIDTH-1:0] tdata_ram_i,
input [PE_COL_NUM*DATA_WIDTH-1:0] tdata_ram_w,
output [PE_ROW_NUM-1:0]tvalid_res,
output [PE_ROW_NUM*REG_WIDTH-1:0] tdata_res
);
wire res_shift;
// pe matrix
pe_mxn #(
.PE_COL_NUM(PE_COL_NUM),
.PE_ROW_NUM(PE_ROW_NUM),
.DATA_WIDTH(DATA_WIDTH),
.REG_WIDTH(REG_WIDTH)
)
pe_mxn_inst (
.clk (clk),
.rst_n (rst_n),
.shift_in (res_shift),
.i_in (tdata_ram_i[PE_ROW_NUM*DATA_WIDTH-1:0]),
.w_in (tdata_ram_w[PE_COL_NUM*DATA_WIDTH-1:0]),
.res_out (tdata_res[PE_ROW_NUM*DATA_WIDTH-1:0])
);
// controller
systolic_ctrl #(
.PE_ROW_NUM(PE_ROW_NUM),
.PE_COL_NUM(PE_COL_NUM),
.DATA_WIDTH(DATA_WIDTH),
.KERNEL_SIZE(KERNEL_SIZE)
)
systolic_ctrl_inst(
.clk (clk),
.rst_n (rst_n),
.start (start),
.cal_done (cal_done),
// to pe_matrix
.res_shift (res_shift),
.res_valid (tvalid_res)
);
endmodule
| 7.450309 |
module sys_array_basic #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //i
parameter ARRAY_L = 4
) //j
(
input clk,
input reset_n,
input param_load,
input [DATA_WIDTH*ARRAY_L-1:0] input_module,
input [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameter_data,
output [2*DATA_WIDTH*ARRAY_W-1:0] out_module
);
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] output_data;
wire [ DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] propagate_module;
/*reg [DATA_WIDTH-1:0] param;
always @(posedge clock)
begin
if (~reset_n)
begin
out_data <= 8'b00000000;
end
else if (param_load)
begin
param <= param_data;
end
else
begin
out_data<= input_data*param+prop_data;
end
end */
genvar i;
genvar j;
genvar t;
generate
for (i = 0; i < ARRAY_W; i = i + 1) begin : generate_array_proc
for (j = 0; j < ARRAY_L; j = j + 1) begin : generate_array_proc2
if ((i === 0) && (j === 0)) begin
sys_array_cell #(
.DATA_WIDTH(DATA_WIDTH)
) cell_inst (
.clock(clk),
.reset_n(reset_n),
.param_load(param_load),
.input_data(input_module[DATA_WIDTH-1:0]),
.prop_data({2 * DATA_WIDTH{1'b0}}),
.param_data(parameter_data[DATA_WIDTH-1:0]),
.out_data(output_data[2*DATA_WIDTH-1:0]),
.prop_param(propagate_module[DATA_WIDTH-1:0])
);
end else if (i === 0) begin
sys_array_cell #(
.DATA_WIDTH(DATA_WIDTH)
) cell_inst (
.clock(clk),
.reset_n(reset_n),
.param_load(param_load),
.input_data(input_module[DATA_WIDTH*(j+1)-1:DATA_WIDTH*j]), //
.prop_data(output_data[2*DATA_WIDTH*(ARRAY_L*i+j)-1:2*DATA_WIDTH*(ARRAY_L*i+j-1)]), //
.param_data(parameter_data[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)]), //
.out_data(output_data[2*DATA_WIDTH*(ARRAY_L*i+j+1)-1:2*DATA_WIDTH*(ARRAY_L*i+j)]),
.prop_param(propagate_module[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)])//
);
end else if (j === 0) begin
sys_array_cell #(
.DATA_WIDTH(DATA_WIDTH)
) cell_inst (
.clock(clk),
.reset_n(reset_n),
.param_load(param_load),
.input_data(propagate_module[DATA_WIDTH*(ARRAY_L*(i-1)+j+1)-1:DATA_WIDTH*(ARRAY_L*(i-1)+j)]),//
.prop_data({2 * DATA_WIDTH{1'b0}}), //
.param_data(parameter_data[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)]), //
.out_data(output_data[2*DATA_WIDTH*(ARRAY_L*i+j+1)-1:2*DATA_WIDTH*(ARRAY_L*i+j)]),
.prop_param(propagate_module[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)])//
);
end else begin
sys_array_cell #(
.DATA_WIDTH(DATA_WIDTH)
) cell_inst (
.clock(clk),
.reset_n(reset_n),
.param_load(param_load),
.input_data(propagate_module[DATA_WIDTH*(ARRAY_L*(i-1)+j+1)-1:DATA_WIDTH*(ARRAY_L*(i-1)+j)]),//
.prop_data(output_data[2*DATA_WIDTH*(ARRAY_L*i+j)-1:2*DATA_WIDTH*(ARRAY_L*i+j-1)]), //
.param_data(parameter_data[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)]), //
.out_data(output_data[2*DATA_WIDTH*(ARRAY_L*i+j+1)-1:2*DATA_WIDTH*(ARRAY_L*i+j)]),
.prop_param(propagate_module[DATA_WIDTH*(ARRAY_L*i+j+1)-1:DATA_WIDTH*(ARRAY_L*i+j)])//
);
end
end
end
endgenerate
generate
for (t = 0; t < ARRAY_W; t = t + 1) begin : output_prop
assign out_module[2*DATA_WIDTH*(t+1)-1:2*DATA_WIDTH*t] = output_data[2*DATA_WIDTH*(ARRAY_L*(t+1))-1:2*DATA_WIDTH*(ARRAY_L*(t+1)-1)];
end
endgenerate
endmodule
| 7.905776 |
module sys_array_cell #(
parameter DATA_WIDTH = 8
) (
input clock,
input reset_n,
input param_load,
input signed [DATA_WIDTH - 1:0] input_data,
input signed [2*DATA_WIDTH-1:0] prop_data,
input signed [DATA_WIDTH-1:0] param_data,
output reg signed [2*DATA_WIDTH-1:0] out_data,
output reg signed [DATA_WIDTH-1:0] prop_param
);
reg signed [DATA_WIDTH-1:0] param;
always @(posedge clock) begin
if (~reset_n) begin
out_data <= {2 * DATA_WIDTH{1'b0}};
param <= {DATA_WIDTH{1'b0}};
end else if (param_load) begin
param <= param_data;
end else begin
out_data <= prop_data + input_data * param;
prop_param <= input_data;
end
end
endmodule
| 7.455479 |
module sys_array_fetcher #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //i
parameter ARRAY_L = 4
) //j
(
input clock,
input reset_n,
input load_params,
input start_comp,
input [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] input_data_a,
input [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] input_data_b,
output reg ready,
output reg [2*DATA_WIDTH*ARRAY_W*ARRAY_W-1:0] out_data
);
localparam FETCH_LENGTH = ARRAY_L+ARRAY_W*2+1; //necessary amount of clk cycles to perform fetching and get back the results
reg [15:0] cnt; //counter
reg [ARRAY_L*2-1:0] control_sr_read;
reg [ARRAY_W*2-1:0] control_sr_write;
wire [DATA_WIDTH*ARRAY_L - 1:0] input_sys_array;
wire [DATA_WIDTH*ARRAY_L - 1:0] empty_wire_reads; //wire to connect read SRs' write ports
wire [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] empty_wire2_reads; //for read SR's out ports
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_W-1:0] empty_wire_writes; //for write SR's in ports
wire [2*DATA_WIDTH*ARRAY_W - 1:0] empty_wire2_writes; //for write SRs' read ports
wire [2*DATA_WIDTH*ARRAY_W - 1:0] output_sys_array;
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_W-1:0] output_wire; //for write SR's out ports
genvar i, j;
wire [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] transposed_a; //transposing a matrix
//transpose matrix a
generate
for (i = 0; i < ARRAY_W; i = i + 1) begin : transpose_i
for (j = 0; j < ARRAY_L; j = j + 1) begin : transpose_j
assign transposed_a [DATA_WIDTH*(ARRAY_W*j+i) +: DATA_WIDTH] = input_data_a [DATA_WIDTH*(ARRAY_L*i+j) +: DATA_WIDTH];
end
end
endgenerate
shift_reg #(
.DATA_WIDTH(DATA_WIDTH),
.LENGTH(ARRAY_W)
) reads[ARRAY_L-1:0] (
clock,
reset_n,
control_sr_read,
transposed_a,
empty_wire_reads,
input_sys_array,
empty_wire2_reads
); //read shift registers
shift_reg #(
.DATA_WIDTH(2 * DATA_WIDTH),
.LENGTH(ARRAY_W)
) writes[ARRAY_W-1:0] (
clock,
reset_n,
control_sr_write,
empty_wire_writes,
output_sys_array,
empty_wire2_writes,
output_wire
); //write shift registers
sys_array_basic #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARRAY_L(ARRAY_L)
) systolic_array (
.clk(clock),
.reset_n(reset_n),
.param_load(load_params),
.parameter_data(input_data_b),
.input_module(input_sys_array),
.out_module(output_sys_array)
);
always @(posedge clock) begin
if (~reset_n) //reset case
begin
cnt <= 15'd0;
control_sr_read <= {ARRAY_L * 2{1'b0}};
control_sr_write <= {ARRAY_W * 2{1'b0}};
ready <= 1'b0;
end
else if(start_comp) //initiate computation
begin
cnt <= 15'd1;
control_sr_read <= {ARRAY_L{2'b01}}; //initiate loading read registers
end
else if (cnt>0) //compute the whole thing
begin
if (cnt == 1) //fetch data into first array input
begin
control_sr_read[2*ARRAY_L-1:2] <= {2 * (ARRAY_L - 1) {1'b0}}; //idle mode on read registers
control_sr_read[1:0] <= 2'b11; //read mode on 1st register
cnt <= cnt + 1'b1;
end else //fetching logic
begin
if (cnt < ARRAY_L + 1) //enable read registers
control_sr_read[2*(cnt-1)+:2] = 2'b11;
if ((cnt > ARRAY_W) && (cnt < ARRAY_L + ARRAY_W + 1)) //start disabling read registers
control_sr_read[2*(cnt-ARRAY_W-1)+:2] = 2'b00;
if ((cnt > ARRAY_L + 1) && (cnt < ARRAY_L + ARRAY_W + 2)) //enable write registers
control_sr_write[2*(cnt-ARRAY_L-2)+:2] = 2'b10;
if ((cnt>ARRAY_L+ARRAY_W+1) && (cnt<=FETCH_LENGTH)) //start disabling write registers
control_sr_write[2*(cnt-(ARRAY_L+ARRAY_W)-2)+:2] = 2'b00;
if (cnt <= FETCH_LENGTH + 1) cnt = cnt + 1'b1;
else begin //propagate outputs.
cnt <= 15'd0;
out_data <= output_wire;
ready <= 1'b1;
end
end
end
end
endmodule
| 9.727713 |
module sys_array_wrapper #(
parameter DATA_WIDTH = 16,
parameter ARRAY_W = 10, //i
parameter ARRAY_L = 784, //j
parameter CLOCK_DIVIDE = 25
) (
input clk,
input reset_n,
input load_params,
input start_comp,
output [7:0] hex_connect
);
localparam MEM_SIZE = ARRAY_W * ARRAY_L;
localparam ARRAY_SIZE = ARRAY_W * ARRAY_W;
wire clk_div, ready;
wire [9:0] hex_input;
wire [DATA_WIDTH*ARRAY_W-1:0] biases;
wire [2*DATA_WIDTH*ARRAY_W - 1:0] output_value, empty_data_write;
wire [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] input_data_a, input_data_b;
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_W-1:0] outputs_fetcher, transposed_outputs, empty_data_out;
reg [CLOCK_DIVIDE : 0] small_cnt;
reg [1:0] propagate_reg_ctrl; //control the output of propagate parallel to serial converter register
genvar i, j;
roma #(
.DATA_WIDTH(DATA_WIDTH),
.SIZE(MEM_SIZE)
) rom_instance_a (
.clk(clk),
.data_rom(input_data_a)
);
romb #(
.DATA_WIDTH(DATA_WIDTH),
.SIZE(MEM_SIZE)
) rom_instance_b (
.clk(clk),
.data_rom(input_data_b)
);
rombias #(
.DATA_WIDTH(DATA_WIDTH),
.SIZE(ARRAY_W)
) rom_instance_bias (
.clk(clk),
.data_rom(biases)
);
sys_array_fetcher #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARRAY_L(ARRAY_L)
) fetching_unit (
.clock(clk),
.reset_n(reset_n),
.load_params(load_params),
.start_comp(start_comp),
.input_data_b(input_data_b),
.input_data_a(input_data_a),
.ready(ready),
.out_data(outputs_fetcher)
);
generate
for (i = 0; i < ARRAY_W; i = i + 1) begin : transpose_i
for (j = 0; j < ARRAY_W; j = j + 1) begin : transpose_j
assign transposed_outputs [2*DATA_WIDTH*(ARRAY_W*j+i) +: 2*DATA_WIDTH] = outputs_fetcher [2*DATA_WIDTH*(ARRAY_W*i+j) +: 2*DATA_WIDTH];
end
end
endgenerate
clock_divider #(
.DIVIDE_LEN(CLOCK_DIVIDE)
) clock_divaaa (
.clock(clk),
.div_clock(clk_div)
);
shift_reg #(
.DATA_WIDTH(2 * DATA_WIDTH * ARRAY_W),
.LENGTH(ARRAY_W)
) propagate_reg (
.clock(clk_div),
.reset_n(reset_n),
.ctrl_code(propagate_reg_ctrl),
.data_in(transposed_outputs),
.data_read(output_value),
.data_out(empty_data_out),
.data_write(empty_data_write)
);
sum_and_max #(
.DATA_WIDTH(DATA_WIDTH),
.LENGTH(ARRAY_W)
) max_voter (
.clk(clk_div),
.reset_n(reset_n),
.ready(ready),
.input_data(output_value),
.biases(biases),
.maxi(hex_input)
);
seg7_tohex hex_converter (
.code(hex_input),
.hexadecimal(hex_connect)
);
always @(posedge clk) begin
if (~reset_n) begin
propagate_reg_ctrl <= 2'b00;
small_cnt <= {(CLOCK_DIVIDE + 1) {1'b0}};
end else begin
case (ready)
1'b0: propagate_reg_ctrl <= 2'b01;
1'b1: begin
if (small_cnt[CLOCK_DIVIDE] == 1'b0) begin
propagate_reg_ctrl <= 2'b01;
small_cnt <= small_cnt + 1'b1;
end else propagate_reg_ctrl <= 2'b11;
end
default: propagate_reg_ctrl <= 2'b00;
endcase
end
end
endmodule
| 8.391784 |
module clock_divider #(
parameter DIVIDE_LEN = 23
) (
input clock,
output div_clock
);
reg [DIVIDE_LEN-1:0] cnt;
initial cnt <= {DIVIDE_LEN{1'b0}};
always @(posedge clock) begin
cnt <= cnt + 1'b1;
end
assign div_clock = cnt[DIVIDE_LEN-1];
endmodule
| 6.818038 |
module sys_bus (
input [31:0] cpu_imem_addr,
output [31:0] cpu_imem_data,
output [31:0] imem_addr, // cpu -> imem
input [31:0] imem_data, // imem -> cpu
input [31:0] cpu_dmem_addr, // device addr
input [31:0] cpu_dmem_data_in, // cpu -> device
input cpu_dmem_wen, // cpu -> device
output reg [31:0] cpu_dmem_data_out, // device -> cpu
input [31:0] dmem_read_data, // dmem -> cpu
output [31:0] dmem_write_data, // cpu -> dmem
output [31:0] dmem_addr, // cpu -> dmem
output reg dmem_wen, // cpu -> dmem
input [31:0] dmem_rom_read_data,
output [31:0] dmem_rom_addr,
input [31:0] uart_read_data, // uart -> cpu
output [31:0] uart_write_data, // cpu -> uart
output [31:0] uart_addr, // cpu -> uart
output reg uart_wen
);
assign imem_addr = cpu_imem_addr;
assign cpu_imem_data = imem_data;
assign dmem_addr = cpu_dmem_addr;
assign dmem_write_data = cpu_dmem_data_in;
assign dmem_rom_addr = cpu_dmem_addr;
assign uart_addr = cpu_dmem_addr;
assign uart_write_data = cpu_dmem_data_in;
always @(*) begin
case (cpu_dmem_addr[31:28])
4'h0: begin //ROM
cpu_dmem_data_out <= dmem_rom_read_data;
dmem_wen <= 0;
uart_wen <= 0;
end
4'h1: begin // RAM
dmem_wen <= cpu_dmem_wen;
cpu_dmem_data_out <= dmem_read_data;
uart_wen <= 0;
end
4'h2: begin // uart io
uart_wen <= cpu_dmem_wen;
cpu_dmem_data_out <= uart_read_data;
dmem_wen <= 0;
end
default: begin
dmem_wen <= 0;
uart_wen <= 0;
cpu_dmem_data_out <= 0;
end
endcase
end
endmodule
| 7.303789 |
module sys_bus_model #(
parameter AXI_DW = 32, // data width (8,16,...,1024)
parameter AXI_AW = 32, // address width
parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
) (
input sys_clk_i, // system clock
input sys_rstn_i, // system reset - active low
output reg [AXI_AW-1:0] sys_addr_o, // system read/write address.
output reg [AXI_DW-1:0] sys_wdata_o, // system write data.
output reg [AXI_SW-1:0] sys_sel_o, // system write byte select.
output reg sys_wen_o, // system write enable.
output reg sys_ren_o, // system read enable.
input [AXI_DW-1:0] sys_rdata_i, // system read data.
input sys_err_i, // system error indicator.
input sys_ack_i // system acknowledge signal.
);
initial begin
sys_wen_o <= 1'b0;
sys_ren_o <= 1'b0;
end
//---------------------------------------------------------------------------------
//
task bus_write;
input [32-1:0] addr;
input [32-1:0] wdata;
begin
@(posedge sys_clk_i) sys_sel_o <= {AXI_DW{1'b1}};
sys_wen_o <= 1'b1;
sys_addr_o <= addr;
sys_wdata_o <= wdata;
@(posedge sys_clk_i);
sys_wen_o <= 1'b0;
while (!sys_ack_i) @(posedge sys_clk_i);
end
endtask // bus_write
//---------------------------------------------------------------------------------
//
task bus_read;
input [32-1:0] addr;
reg [32-1:0] rdata;
begin
@(posedge sys_clk_i) sys_ren_o <= 1'b1;
sys_addr_o <= addr;
@(posedge sys_clk_i);
sys_ren_o <= 1'b0;
while (!sys_ack_i) @(posedge sys_clk_i);
rdata <= sys_rdata_i;
@(posedge sys_clk_i);
$display("@%g Readed value at %h is %h", $time, addr[19:0], rdata);
end
endtask // bus_read
endmodule
| 8.012986 |
module sys_clk #(
parameter DIFF_CLKIN = "TRUE",
parameter CLKIN_PERIOD = 10.0, // default 100MHz
parameter MULT = 10, // 100 X 1 = 1000
parameter DIV0 = 8 // 1000 / 8 = 125
) (
input rst_i,
input sysclk_p_i,
input sysclk_n_i,
output sysclk_buf_o,
output clk_out0_o,
output locked_o
);
generate
if (DIFF_CLKIN == "TRUE") begin : gen_ibufgds
IBUFGDS ibufgds_int (
.O (sysclk_buf_o),
.I (sysclk_p_i),
.IB(sysclk_n_i)
);
end else if (DIFF_CLKIN == "BYPASS") begin : gen_bypass
assign sysclk_buf_o = sysclk_p_i;
end else begin : gen_ibifg
IBUF ibufgds_int (
.O(sysclk_buf_o),
.I(sysclk_p_i)
);
end
endgenerate
wire mmcm_clkfbin;
wire mmcm_clkfbout;
wire clk_out0_int;
MMCME2_BASE #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MULT),
.CLKFBOUT_PHASE (0.0),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE_F (DIV0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE (0.0),
.REF_JITTER1 (0.01)
) MMCME2_BASE_inst (
.CLKOUT0 (clk_out0_int),
.LOCKED (locked_o),
.CLKIN1 (sysclk_buf_o),
.PWRDWN (1'b0),
.RST (rst_i),
.CLKFBIN (mmcm_clkfbin),
.CLKFBOUT(mmcm_clkfbout)
);
BUFG clkfbout_bufg (
.O(mmcm_clkfbin),
.I(mmcm_clkfbout)
);
BUFG clkout1_buf (
.O(clk_out0_o),
.I(clk_out0_int)
);
endmodule
| 7.141499 |
module sys_config (
wb_clk_i,
wb_rst_i,
wb_stb_i,
wb_cyc_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
sys_config_vector,
xtal_clk,
rtc_alarm
);
parameter BOARD_ID = 0;
parameter REV_MAJOR = 0;
parameter REV_MINOR = 0;
parameter REV_RCS = 0;
parameter RCS_UPTODATE = 0;
input wb_clk_i, wb_rst_i;
input wb_stb_i, wb_cyc_i, wb_we_i;
input [15:0] wb_adr_i;
input [15:0] wb_dat_i;
output [15:0] wb_dat_o;
output wb_ack_o;
output [7:0] sys_config_vector;
input xtal_clk;
output rtc_alarm;
reg wb_ack_o;
reg [7:0] sys_config_vector;
reg [3:0] wb_dat_src;
reg [47:0] current_time_reg;
reg [14:0] ticker_reg;
reg [47:0] current_time_buffer;
reg rtc_init_strb;
assign wb_dat_o = wb_dat_src == `REG_BOARD_ID ? BOARD_ID :
wb_dat_src == `REG_REV_MAJOR ? REV_MAJOR :
wb_dat_src == `REG_REV_MINOR ? REV_MINOR :
wb_dat_src == `REG_REV_RCS ? REV_RCS :
wb_dat_src == `REG_RCS_UPTODATE ? RCS_UPTODATE :
wb_dat_src == `REG_SYS_CONFIG ? {8'b0,sys_config_vector} :
wb_dat_src == `REG_TIME_SEC_2 ? current_time_reg[47:32] :
wb_dat_src == `REG_TIME_SEC_1 ? current_time_reg[31:16] :
wb_dat_src == `REG_TIME_SEC_0 ? current_time_reg[15:0 ] :
wb_dat_src == `REG_TIME_TICKER ? {1'b0, ticker_reg} :
16'b0;
always @(posedge wb_clk_i) begin
//strobes
wb_ack_o <= 1'b0;
rtc_init_strb <= 1'b0;
if (wb_rst_i) begin
sys_config_vector <= 8'd0;
end else begin
if (wb_cyc_i & wb_stb_i & ~wb_ack_o) begin
wb_ack_o <= 1'b1;
wb_dat_src <= wb_adr_i[3:0];
case (wb_adr_i)
`REG_BOARD_ID: begin
end
`REG_REV_MAJOR: begin
end
`REG_REV_MINOR: begin
end
`REG_REV_RCS: begin
end
`REG_RCS_UPTODATE: begin
end
`REG_SYS_CONFIG: begin
if (wb_we_i) begin
sys_config_vector <= wb_dat_i[7:0];
end
end
`REG_TIME_SEC_2: begin
if (wb_we_i) begin
current_time_buffer[47:32] <= wb_dat_i;
end
end
`REG_TIME_SEC_1: begin
if (wb_we_i) begin
current_time_buffer[31:16] <= wb_dat_i;
end
end
`REG_TIME_SEC_0: begin
if (wb_we_i) begin
current_time_buffer[15:0] <= wb_dat_i;
rtc_init_strb <= 1'b1;
end
end
`REG_TIME_TICKER: begin
end
endcase
end
end
end
/* Real-Time Clock */
reg [14:0] rtc_second_ticker;
reg [47:0] current_time; /* seconds since 1970 */
/* rtc value load handshaking registers */
/* these should probably be registered to their respective clock domains */
reg rtc_ack;
reg rtc_got;
always @(posedge xtal_clk) begin /* 32.768 kHz */
if (rtc_got) begin
rtc_ack <= 1'b1;
rtc_second_ticker <= 15'd0;
current_time <= current_time_buffer;
end else begin
rtc_ack <= 1'b0;
rtc_second_ticker <= rtc_second_ticker + 1;
if (rtc_second_ticker == 15'h7f_ff) begin
current_time <= current_time + 1;
end
end
end
always @(posedge wb_clk_i) begin
/* cross clock domains */
current_time_reg <= current_time;
ticker_reg <= rtc_second_ticker;
/* handshake for value loading */
if (wb_rst_i) begin
rtc_got <= 1'b0;
ticker_reg <= 7'b0001111;
end else begin
if (rtc_init_strb) rtc_got <= 1'b1;
if (rtc_ack) rtc_got <= 1'b0;
end
end
endmodule
| 8.737465 |
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