code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module synth_arb (
clk,
reset_n,
memadrs,
memdata,
wreq,
synth_ctrl,
synth_data,
fifo_full
);
input wire clk, reset_n, wreq, fifo_full;
input wire [7:0] memadrs, memdata;
output reg [7:0] synth_ctrl, synth_data;
reg [7:0] state_reg;
reg [3:0] wait_cnt;
reg wreq_inter, w_done;
always @(posedge wreq, posedge w_done, negedge reset_n) begin
if (reset_n == 0) wreq_inter <= 0;
else if (w_done == 1) wreq_inter <= 0;
else if (wreq == 1 && w_done != 1) wreq_inter <= 1;
end
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
state_reg <= 0;
synth_ctrl <= 0;
synth_data <= 0;
wait_cnt <= 0;
w_done <= 0;
end else begin
case (state_reg)
8'D0: state_reg <= state_reg + 1;
//recovery reset while 16count
8'D1: begin
if (wait_cnt != 4'b1111) wait_cnt <= wait_cnt + 1;
else state_reg <= state_reg + 1;
end
//step phase, operator 1
8'D2: begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b00000001;
end
//fifo full check, operator stall
8'D3: begin
synth_ctrl <= 8'b00000000;
if (fifo_full != 1) state_reg <= state_reg + 1;
else state_reg <= state_reg;
end
//write req to fifo, operator 1
8'D4: begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b10000001;
end
//write wait
8'D5: begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b00000000;
end
//jump to state 2 if write strobe is not active
8'D6: begin
if (wreq_inter == 1) state_reg <= state_reg + 1;
else state_reg <= 2;
end
//get recieve data and command, write data
8'D7: begin
synth_data <= memdata;
synth_ctrl <= d2ctrl_synth(memadrs);
state_reg <= state_reg + 1;
w_done <= 1;
end
//finishing write data
8'D8: begin
state_reg <= 2;
synth_ctrl <= 8'b00000000;
w_done <= 0;
end
default: state_reg <= 0;
endcase
end
end
function [7:0] d2ctrl_synth;
input [7:0] adrs;
begin
casex (adrs)
8'b00000001: d2ctrl_synth = 8'b01000001;
8'b00010001: d2ctrl_synth = 8'b00010001;
8'b00100001: d2ctrl_synth = 8'b01010001;
8'b1000xxxx: d2ctrl_synth = 8'b00100000;
default: d2ctrl_synth = 0;
endcase
end
endfunction
endmodule
| 7.050979 |
module top_small (
input clk,
resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) picorv32 (
.clk (clk),
.resetn (resetn),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
endmodule
| 7.770123 |
module top_regular (
input clk,
resetn,
output trap,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output [31:0] mem_la_wdata,
output [ 3:0] mem_la_wstrb
);
picorv32 picorv32 (
.clk (clk),
.resetn (resetn),
.trap (trap),
.mem_valid (mem_valid),
.mem_instr (mem_instr),
.mem_ready (mem_ready),
.mem_addr (mem_addr),
.mem_wdata (mem_wdata),
.mem_wstrb (mem_wstrb),
.mem_rdata (mem_rdata),
.mem_la_read (mem_la_read),
.mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb)
);
endmodule
| 6.893677 |
module synth_dual_port_memory (
clk,
rstb,
error,
//bus 0
wr_ena0,
addr0,
din0,
dout0,
//bus 1
wr_ena1,
addr1,
din1,
dout1
);
parameter N = 32; //bus width
parameter I_LENGTH = 512;
parameter I_WIDTH = 9;
parameter D_LENGTH = 1024;
parameter D_WIDTH = 10;
input wire clk, rstb;
output reg error = 0;
input wire wr_ena0, wr_ena1;
input wire [N-1:0] addr0, din0, addr1, din1;
output reg [N-1:0] dout0, dout1;
//memories
reg [N-1:0] IMEM[I_LENGTH-1:0];
reg [N-1:0] DMEM[D_LENGTH-1:0];
//physical addresses
wire [I_WIDTH-1:0] phy_i_addr0, phy_i_addr1;
wire [D_WIDTH-1:0] phy_d_addr0, phy_d_addr1;
assign phy_i_addr0 = addr0[I_WIDTH+1:2];
assign phy_d_addr0 = addr0[D_WIDTH+1:2];
assign phy_i_addr1 = addr1[I_WIDTH+1:2];
assign phy_d_addr1 = addr1[D_WIDTH+1:2];
wire i0, i1, d0, d1, wr_i_ena0, wr_d_ena0, wr_i_ena1, wr_d_ena1;
assign i0 = addr0[31:20] === `I_START_ADDRESS;
assign i1 = addr1[31:20] === `I_START_ADDRESS;
assign d0 = ~i0;
assign d1 = ~i1;
assign wr_i_ena0 = i0 & wr_ena0;
assign wr_d_ena0 = d0 & wr_ena0;
assign wr_i_ena1 = i1 & wr_ena1;
assign wr_d_ena1 = d1 & wr_ena1;
reg [N-1:0] i_dout0, i_dout1, d_dout0, d_dout1;
reg last_i0, last_i1;
//instruction memory and data memory coded separately to allow for easier synthesis
//instruction memory
always @(posedge clk) begin
if (wr_i_ena0) begin
IMEM[phy_i_addr0] <= din0;
end
i_dout0 <= IMEM[phy_i_addr0];
end
always @(posedge clk) begin
if (wr_i_ena1) begin
IMEM[phy_i_addr1] <= din1;
end
i_dout1 <= IMEM[phy_i_addr1];
end
//data memory
always @(posedge clk) begin
if (wr_d_ena0) begin
DMEM[phy_d_addr0] <= din0;
end
d_dout0 <= DMEM[phy_d_addr0];
end
always @(posedge clk) begin
if (wr_d_ena1) begin
DMEM[phy_d_addr1] <= din1;
end
d_dout1 <= DMEM[phy_d_addr1];
end
always @(posedge clk) begin
last_i0 <= i0;
last_i1 <= i1;
end
always @(*) begin
if (last_i0) begin
dout0 = i_dout0;
end else begin
dout0 = d_dout0;
end
if (last_i1) begin
dout1 = i_dout1;
end else begin
dout1 = d_dout1;
end
end
`ifndef SYNTHESIS
reg [8*100:0] INIT_INST;
reg [8*100:0] INIT_DATA;
initial begin
if (!$value$plusargs("INIT_INST=%s", INIT_INST)) begin
$display("no instruction file was supplied with +INIT_INST, quitting.");
$finish;
end
if (!$value$plusargs("INIT_DATA=%s", INIT_DATA)) begin
$display("no data file was supplied, using tests/zero.memh");
INIT_DATA = "d_synth.memh";
end
$display("initializing %m's instruction memory from '%s' and data memory from '%s'", INIT_INST,
INIT_DATA);
$readmemh(INIT_INST, IMEM, 0, I_LENGTH - 1);
$readmemh(INIT_DATA, DMEM, 0, D_LENGTH - 1);
end
`else
initial begin
$readmemh("i_synth.memh", IMEM, 0, I_LENGTH - 1);
$readmemh("d_synth.memh", DMEM, 0, D_LENGTH - 1);
end
`endif
endmodule
| 7.544256 |
module top (
input clk,
resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) picorv32 (
.clk (clk),
.resetn (resetn),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
endmodule
| 7.233807 |
module synth_ram #(
parameter integer WORDS = 64
) (
input clk,
input ena,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] rdata;
reg [31:0] mem[0:WORDS-1];
always @(posedge clk) begin
if (ena == 1'b1) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][7:0] <= wdata[7:0];
if (wen[1]) mem[addr][15:8] <= wdata[15:8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
end
endmodule
| 6.623284 |
module synth_tb ();
reg clk = 0;
always #1 clk = !clk;
reg reset = 0;
reg [1:0] shape = 1;
reg [5:0] tone = 60;
wire out;
reflet_synth_generator synth (
.clk (clk),
.reset(reset),
.shape(shape),
.tone (tone),
.out (out)
);
initial begin
$dumpfile("synth_tb.vcd");
$dumpvars(0, synth_tb);
#10;
reset = 1;
#10000;
tone = 48;
shape = 2;
#10000;
tone = 55;
shape = 3;
#10000;
shape = 0;
#10000;
$finish;
end
endmodule
| 7.219264 |
module synth_testbench ();
parameter SYSTEM_CLK_PERIOD = 8;
parameter SYSTEM_CLK_FREQ = 125_000_000;
reg sys_clk = 0;
reg sys_rst = 0;
always #(SYSTEM_CLK_PERIOD / 2) sys_clk <= ~sys_clk;
// UART Signals between the on-chip and off-chip UART
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
// Off-chip UART Ready/Valid interface
reg [7:0] data_in;
reg data_in_valid;
wire data_in_ready;
wire [7:0] data_out;
wire data_out_valid;
reg data_out_ready;
z1top #(
.SYSTEM_CLOCK_FREQ(SYSTEM_CLK_FREQ),
.B_SAMPLE_COUNT_MAX(5),
.B_PULSE_COUNT_MAX(5),
.RESET_PC(32'h1000_0000)
) top (
.CLK_125MHZ_FPGA(sys_clk),
.BUTTONS({3'b0, sys_rst}),
.SWITCHES(2'b0),
.LEDS(),
.FPGA_SERIAL_RX(FPGA_SERIAL_RX),
.FPGA_SERIAL_TX(FPGA_SERIAL_TX)
);
// Instantiate the off-chip UART
uart #(
.CLOCK_FREQ(SYSTEM_CLK_FREQ)
) off_chip_uart (
.clk(sys_clk),
.reset(sys_rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_in_ready(data_in_ready),
.data_out(data_out),
.data_out_valid(data_out_valid),
.data_out_ready(data_out_ready),
.serial_in(FPGA_SERIAL_TX),
.serial_out(FPGA_SERIAL_RX)
);
reg done = 0;
reg [31:0] cycle = 0;
initial begin
$readmemh("../../software/hw_piano/hw_piano.hex", top.cpu.imem.mem, 0, 16384 - 1);
$readmemh("../../software/hw_piano/hw_piano.hex", top.cpu.dmem.mem, 0, 16384 - 1);
`ifndef IVERILOG
$vcdpluson;
`endif
`ifdef IVERILOG
$dumpfile("synth_testbench.fst");
$dumpvars(0, synth_testbench);
`endif
// Reset all parts
sys_rst = 1'b0;
data_in = 8'd35; // '#' in ascii
data_in_valid = 1'b0;
data_out_ready = 1'b0;
repeat (20) @(posedge sys_clk);
#1;
sys_rst = 1'b1;
repeat (50) @(posedge sys_clk);
#1;
sys_rst = 1'b0;
while (!data_in_ready) @(posedge sys_clk);
#1;
data_in_valid = 1'b1;
@(posedge sys_clk);
#1;
data_in_valid = 1'b0;
// This wait can be shortened by increasing the sampling frequency of the NCO.
#(10 * `MS);
// Observe waveform for correct behavior.
// Note: In DVE, if you "Set Radix" to Two's Complement and
// "Set Draw Style Scheme" to analog for your LUT read values,
// you should see the shape of the sine/square/triangle/sawtooth waves.
`ifndef IVERILOG
$vcdplusoff;
`endif
$finish();
end
endmodule
| 7.871806 |
module counter_6 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55;
DFFQX1 \count_reg[0] (
.D (N25),
.CLK(clk),
.Q (count[0])
);
DFFQX1 \count_reg[7] (
.D (N32),
.CLK(clk),
.Q (count[7])
);
DFFQX1 \count_reg[6] (
.D (N31),
.CLK(clk),
.Q (count[6])
);
DFFQX1 \count_reg[5] (
.D (N30),
.CLK(clk),
.Q (count[5])
);
DFFQX1 \count_reg[4] (
.D (N29),
.CLK(clk),
.Q (count[4])
);
DFFQX1 \count_reg[3] (
.D (N28),
.CLK(clk),
.Q (count[3])
);
DFFQX1 \count_reg[2] (
.D (N27),
.CLK(clk),
.Q (count[2])
);
DFFQX1 \count_reg[1] (
.D (N26),
.CLK(clk),
.Q (count[1])
);
AND2X1 U3 (
.A(N13),
.B(n55),
.Z(N32)
);
AND2X1 U4 (
.A(N12),
.B(n55),
.Z(N31)
);
AND2X1 U6 (
.A(N11),
.B(n55),
.Z(N30)
);
AND2X1 U7 (
.A(N10),
.B(n55),
.Z(N29)
);
AND2X1 U8 (
.A(N9),
.B(n55),
.Z(N28)
);
AND2X1 U9 (
.A(N8),
.B(n55),
.Z(N27)
);
AND2X1 U10 (
.A(N7),
.B(n55),
.Z(N26)
);
AND2X1 U11 (
.A(n46),
.B(n55),
.Z(N25)
);
NOR2X1 U12 (
.A(reset),
.B(n54),
.Z(n55)
);
NOR2X1 U13 (
.A(N3),
.B(n53),
.Z(n54)
);
NOR2X1 U14 (
.A(n52),
.B(n51),
.Z(n53)
);
NAND2X1 U15 (
.A(n50),
.B(n49),
.Z(n51)
);
NOR2X1 U16 (
.A(count_to[3]),
.B(count_to[2]),
.Z(n49)
);
NOR2X1 U17 (
.A(count_to[1]),
.B(count_to[0]),
.Z(n50)
);
NAND2X1 U18 (
.A(n48),
.B(n47),
.Z(n52)
);
NOR2X1 U19 (
.A(count_to[7]),
.B(count_to[6]),
.Z(n47)
);
NOR2X1 U20 (
.A(count_to[5]),
.B(count_to[4]),
.Z(n48)
);
INVX2 U5 (
.A(count_to[7]),
.Z(n41)
);
INVX2 U21 (
.A(count[0]),
.Z(n46)
);
XOR2X1 U22 (
.A(count[2]),
.B(n1),
.Z(N8)
);
AND2X1 U23 (
.A(count[1]),
.B(count[0]),
.Z(n1)
);
INVX2 U24 (
.A(count[2]),
.Z(n42)
);
INVX2 U25 (
.A(count[3]),
.Z(n43)
);
INVX2 U26 (
.A(count[4]),
.Z(n44)
);
INVX2 U27 (
.A(count[6]),
.Z(n45)
);
INVX4 U28 (
.A(n2),
.Z(n17)
);
INVX2 U29 (
.A(count[5]),
.Z(n16)
);
XOR2X1 U30 (
.A(count[1]),
.B(count[0]),
.Z(N7)
);
NAND3X1 U31 (
.A(count[1]),
.B(count[0]),
.C(count[2]),
.Z(n2)
);
XOR2X1 U32 (
.A(count[3]),
.B(n17),
.Z(N9)
);
AND2X1 U33 (
.A(n17),
.B(count[3]),
.Z(n12)
);
XOR2X1 U34 (
.A(count[4]),
.B(n12),
.Z(N10)
);
NAND3X1 U35 (
.A(count[3]),
.B(n17),
.C(count[4]),
.Z(n13)
);
XOR2X1 U36 (
.A(n16),
.B(n13),
.Z(N11)
);
NOR2X1 U37 (
.A(n16),
.B(n13),
.Z(n14)
);
XOR2X1 U38 (
.A(count[6]),
.B(n14),
.Z(N12)
);
AND2X1 U39 (
.A(n14),
.B(count[6]),
.Z(n15)
);
XOR2X1 U40 (
.A(count[7]),
.B(n15),
.Z(N13)
);
OR2X1 U41 (
.A(n41),
.B(count[7]),
.Z(n40)
);
OR2X1 U42 (
.A(n16),
.B(count_to[5]),
.Z(n34)
);
OR2X1 U43 (
.A(n43),
.B(count_to[3]),
.Z(n28)
);
NAND2X1 U44 (
.A(count_to[0]),
.B(n46),
.Z(n18)
);
NAND2X1 U45 (
.A(count[1]),
.B(n18),
.Z(n22)
);
NOR2X1 U46 (
.A(count[1]),
.B(n18),
.Z(n19)
);
OR2X1 U47 (
.A(count_to[1]),
.B(n19),
.Z(n21)
);
OR2X1 U48 (
.A(n42),
.B(count_to[2]),
.Z(n20)
);
NAND3X1 U49 (
.A(n22),
.B(n21),
.C(n20),
.Z(n25)
);
NAND2X1 U50 (
.A(count_to[2]),
.B(n42),
.Z(n24)
);
NAND2X1 U51 (
.A(count_to[3]),
.B(n43),
.Z(n23)
);
NAND3X1 U52 (
.A(n25),
.B(n24),
.C(n23),
.Z(n27)
);
OR2X1 U53 (
.A(n44),
.B(count_to[4]),
.Z(n26)
);
NAND3X1 U54 (
.A(n28),
.B(n27),
.C(n26),
.Z(n31)
);
NAND2X1 U55 (
.A(count_to[4]),
.B(n44),
.Z(n30)
);
NAND2X1 U56 (
.A(count_to[5]),
.B(n16),
.Z(n29)
);
NAND3X1 U57 (
.A(n31),
.B(n30),
.C(n29),
.Z(n33)
);
OR2X1 U58 (
.A(n45),
.B(count_to[6]),
.Z(n32)
);
NAND3X1 U59 (
.A(n34),
.B(n33),
.C(n32),
.Z(n36)
);
NAND2X1 U60 (
.A(count_to[6]),
.B(n45),
.Z(n35)
);
NAND2X1 U61 (
.A(n36),
.B(n35),
.Z(n38)
);
NAND2X1 U62 (
.A(count[7]),
.B(n41),
.Z(n37)
);
NAND2X1 U63 (
.A(n38),
.B(n37),
.Z(n39)
);
NAND2X1 U64 (
.A(n40),
.B(n39),
.Z(N3)
);
endmodule
| 6.768667 |
module counter_5 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55;
DFFQX1 \count_reg[0] (
.D (N25),
.CLK(clk),
.Q (count[0])
);
DFFQX1 \count_reg[7] (
.D (N32),
.CLK(clk),
.Q (count[7])
);
DFFQX1 \count_reg[6] (
.D (N31),
.CLK(clk),
.Q (count[6])
);
DFFQX1 \count_reg[5] (
.D (N30),
.CLK(clk),
.Q (count[5])
);
DFFQX1 \count_reg[4] (
.D (N29),
.CLK(clk),
.Q (count[4])
);
DFFQX1 \count_reg[3] (
.D (N28),
.CLK(clk),
.Q (count[3])
);
DFFQX1 \count_reg[2] (
.D (N27),
.CLK(clk),
.Q (count[2])
);
DFFQX1 \count_reg[1] (
.D (N26),
.CLK(clk),
.Q (count[1])
);
AND2X1 U3 (
.A(N13),
.B(n55),
.Z(N32)
);
AND2X1 U4 (
.A(N12),
.B(n55),
.Z(N31)
);
AND2X1 U6 (
.A(N11),
.B(n55),
.Z(N30)
);
AND2X1 U7 (
.A(N10),
.B(n55),
.Z(N29)
);
AND2X1 U8 (
.A(N9),
.B(n55),
.Z(N28)
);
AND2X1 U9 (
.A(N8),
.B(n55),
.Z(N27)
);
AND2X1 U10 (
.A(N7),
.B(n55),
.Z(N26)
);
AND2X1 U11 (
.A(n46),
.B(n55),
.Z(N25)
);
NOR2X1 U12 (
.A(reset),
.B(n54),
.Z(n55)
);
NOR2X1 U13 (
.A(N3),
.B(n53),
.Z(n54)
);
NOR2X1 U14 (
.A(n52),
.B(n51),
.Z(n53)
);
NAND2X1 U15 (
.A(n50),
.B(n49),
.Z(n51)
);
NOR2X1 U16 (
.A(count_to[3]),
.B(count_to[2]),
.Z(n49)
);
NOR2X1 U17 (
.A(count_to[1]),
.B(count_to[0]),
.Z(n50)
);
NAND2X1 U18 (
.A(n48),
.B(n47),
.Z(n52)
);
NOR2X1 U19 (
.A(count_to[7]),
.B(count_to[6]),
.Z(n47)
);
NOR2X1 U20 (
.A(count_to[5]),
.B(count_to[4]),
.Z(n48)
);
INVX2 U5 (
.A(count_to[7]),
.Z(n41)
);
INVX2 U21 (
.A(count[0]),
.Z(n46)
);
XOR2X1 U22 (
.A(count[2]),
.B(n1),
.Z(N8)
);
AND2X1 U23 (
.A(count[1]),
.B(count[0]),
.Z(n1)
);
INVX2 U24 (
.A(count[2]),
.Z(n42)
);
INVX2 U25 (
.A(count[3]),
.Z(n43)
);
INVX2 U26 (
.A(count[4]),
.Z(n44)
);
INVX2 U27 (
.A(count[6]),
.Z(n45)
);
INVX4 U28 (
.A(n2),
.Z(n17)
);
INVX2 U29 (
.A(count[5]),
.Z(n16)
);
XOR2X1 U30 (
.A(count[1]),
.B(count[0]),
.Z(N7)
);
NAND3X1 U31 (
.A(count[1]),
.B(count[0]),
.C(count[2]),
.Z(n2)
);
XOR2X1 U32 (
.A(count[3]),
.B(n17),
.Z(N9)
);
AND2X1 U33 (
.A(n17),
.B(count[3]),
.Z(n12)
);
XOR2X1 U34 (
.A(count[4]),
.B(n12),
.Z(N10)
);
NAND3X1 U35 (
.A(count[3]),
.B(n17),
.C(count[4]),
.Z(n13)
);
XOR2X1 U36 (
.A(n16),
.B(n13),
.Z(N11)
);
NOR2X1 U37 (
.A(n16),
.B(n13),
.Z(n14)
);
XOR2X1 U38 (
.A(count[6]),
.B(n14),
.Z(N12)
);
AND2X1 U39 (
.A(n14),
.B(count[6]),
.Z(n15)
);
XOR2X1 U40 (
.A(count[7]),
.B(n15),
.Z(N13)
);
OR2X1 U41 (
.A(n41),
.B(count[7]),
.Z(n40)
);
OR2X1 U42 (
.A(n16),
.B(count_to[5]),
.Z(n34)
);
OR2X1 U43 (
.A(n43),
.B(count_to[3]),
.Z(n28)
);
NAND2X1 U44 (
.A(count_to[0]),
.B(n46),
.Z(n18)
);
NAND2X1 U45 (
.A(count[1]),
.B(n18),
.Z(n22)
);
NOR2X1 U46 (
.A(count[1]),
.B(n18),
.Z(n19)
);
OR2X1 U47 (
.A(count_to[1]),
.B(n19),
.Z(n21)
);
OR2X1 U48 (
.A(n42),
.B(count_to[2]),
.Z(n20)
);
NAND3X1 U49 (
.A(n22),
.B(n21),
.C(n20),
.Z(n25)
);
NAND2X1 U50 (
.A(count_to[2]),
.B(n42),
.Z(n24)
);
NAND2X1 U51 (
.A(count_to[3]),
.B(n43),
.Z(n23)
);
NAND3X1 U52 (
.A(n25),
.B(n24),
.C(n23),
.Z(n27)
);
OR2X1 U53 (
.A(n44),
.B(count_to[4]),
.Z(n26)
);
NAND3X1 U54 (
.A(n28),
.B(n27),
.C(n26),
.Z(n31)
);
NAND2X1 U55 (
.A(count_to[4]),
.B(n44),
.Z(n30)
);
NAND2X1 U56 (
.A(count_to[5]),
.B(n16),
.Z(n29)
);
NAND3X1 U57 (
.A(n31),
.B(n30),
.C(n29),
.Z(n33)
);
OR2X1 U58 (
.A(n45),
.B(count_to[6]),
.Z(n32)
);
NAND3X1 U59 (
.A(n34),
.B(n33),
.C(n32),
.Z(n36)
);
NAND2X1 U60 (
.A(count_to[6]),
.B(n45),
.Z(n35)
);
NAND2X1 U61 (
.A(n36),
.B(n35),
.Z(n38)
);
NAND2X1 U62 (
.A(count[7]),
.B(n41),
.Z(n37)
);
NAND2X1 U63 (
.A(n38),
.B(n37),
.Z(n39)
);
NAND2X1 U64 (
.A(n40),
.B(n39),
.Z(N3)
);
endmodule
| 6.894743 |
module counter_4 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55;
DFFQX1 \count_reg[0] (
.D (N25),
.CLK(clk),
.Q (count[0])
);
DFFQX1 \count_reg[7] (
.D (N32),
.CLK(clk),
.Q (count[7])
);
DFFQX1 \count_reg[6] (
.D (N31),
.CLK(clk),
.Q (count[6])
);
DFFQX1 \count_reg[5] (
.D (N30),
.CLK(clk),
.Q (count[5])
);
DFFQX1 \count_reg[4] (
.D (N29),
.CLK(clk),
.Q (count[4])
);
DFFQX1 \count_reg[3] (
.D (N28),
.CLK(clk),
.Q (count[3])
);
DFFQX1 \count_reg[2] (
.D (N27),
.CLK(clk),
.Q (count[2])
);
DFFQX1 \count_reg[1] (
.D (N26),
.CLK(clk),
.Q (count[1])
);
AND2X1 U3 (
.A(N13),
.B(n55),
.Z(N32)
);
AND2X1 U4 (
.A(N12),
.B(n55),
.Z(N31)
);
AND2X1 U6 (
.A(N11),
.B(n55),
.Z(N30)
);
AND2X1 U7 (
.A(N10),
.B(n55),
.Z(N29)
);
AND2X1 U8 (
.A(N9),
.B(n55),
.Z(N28)
);
AND2X1 U9 (
.A(N8),
.B(n55),
.Z(N27)
);
AND2X1 U10 (
.A(N7),
.B(n55),
.Z(N26)
);
AND2X1 U11 (
.A(n46),
.B(n55),
.Z(N25)
);
NOR2X1 U12 (
.A(reset),
.B(n54),
.Z(n55)
);
NOR2X1 U13 (
.A(N3),
.B(n53),
.Z(n54)
);
NOR2X1 U14 (
.A(n52),
.B(n51),
.Z(n53)
);
NAND2X1 U15 (
.A(n50),
.B(n49),
.Z(n51)
);
NOR2X1 U16 (
.A(count_to[3]),
.B(count_to[2]),
.Z(n49)
);
NOR2X1 U17 (
.A(count_to[1]),
.B(count_to[0]),
.Z(n50)
);
NAND2X1 U18 (
.A(n48),
.B(n47),
.Z(n52)
);
NOR2X1 U19 (
.A(count_to[7]),
.B(count_to[6]),
.Z(n47)
);
NOR2X1 U20 (
.A(count_to[5]),
.B(count_to[4]),
.Z(n48)
);
INVX2 U5 (
.A(count[0]),
.Z(n46)
);
XOR2X1 U21 (
.A(count[2]),
.B(n1),
.Z(N8)
);
AND2X1 U22 (
.A(count[1]),
.B(count[0]),
.Z(n1)
);
INVX2 U23 (
.A(count[2]),
.Z(n42)
);
INVX2 U24 (
.A(count[3]),
.Z(n43)
);
INVX2 U25 (
.A(count[4]),
.Z(n44)
);
INVX2 U26 (
.A(count[6]),
.Z(n45)
);
INVX4 U27 (
.A(n2),
.Z(n17)
);
INVX2 U28 (
.A(count[5]),
.Z(n16)
);
INVX2 U29 (
.A(count_to[7]),
.Z(n41)
);
XOR2X1 U30 (
.A(count[1]),
.B(count[0]),
.Z(N7)
);
NAND3X1 U31 (
.A(count[1]),
.B(count[0]),
.C(count[2]),
.Z(n2)
);
XOR2X1 U32 (
.A(count[3]),
.B(n17),
.Z(N9)
);
AND2X1 U33 (
.A(n17),
.B(count[3]),
.Z(n12)
);
XOR2X1 U34 (
.A(count[4]),
.B(n12),
.Z(N10)
);
NAND3X1 U35 (
.A(count[3]),
.B(n17),
.C(count[4]),
.Z(n13)
);
XOR2X1 U36 (
.A(n16),
.B(n13),
.Z(N11)
);
NOR2X1 U37 (
.A(n16),
.B(n13),
.Z(n14)
);
XOR2X1 U38 (
.A(count[6]),
.B(n14),
.Z(N12)
);
AND2X1 U39 (
.A(n14),
.B(count[6]),
.Z(n15)
);
XOR2X1 U40 (
.A(count[7]),
.B(n15),
.Z(N13)
);
OR2X1 U41 (
.A(n41),
.B(count[7]),
.Z(n40)
);
OR2X1 U42 (
.A(n16),
.B(count_to[5]),
.Z(n34)
);
OR2X1 U43 (
.A(n43),
.B(count_to[3]),
.Z(n28)
);
NAND2X1 U44 (
.A(count_to[0]),
.B(n46),
.Z(n18)
);
NAND2X1 U45 (
.A(count[1]),
.B(n18),
.Z(n22)
);
NOR2X1 U46 (
.A(count[1]),
.B(n18),
.Z(n19)
);
OR2X1 U47 (
.A(count_to[1]),
.B(n19),
.Z(n21)
);
OR2X1 U48 (
.A(n42),
.B(count_to[2]),
.Z(n20)
);
NAND3X1 U49 (
.A(n22),
.B(n21),
.C(n20),
.Z(n25)
);
NAND2X1 U50 (
.A(count_to[2]),
.B(n42),
.Z(n24)
);
NAND2X1 U51 (
.A(count_to[3]),
.B(n43),
.Z(n23)
);
NAND3X1 U52 (
.A(n25),
.B(n24),
.C(n23),
.Z(n27)
);
OR2X1 U53 (
.A(n44),
.B(count_to[4]),
.Z(n26)
);
NAND3X1 U54 (
.A(n28),
.B(n27),
.C(n26),
.Z(n31)
);
NAND2X1 U55 (
.A(count_to[4]),
.B(n44),
.Z(n30)
);
NAND2X1 U56 (
.A(count_to[5]),
.B(n16),
.Z(n29)
);
NAND3X1 U57 (
.A(n31),
.B(n30),
.C(n29),
.Z(n33)
);
OR2X1 U58 (
.A(n45),
.B(count_to[6]),
.Z(n32)
);
NAND3X1 U59 (
.A(n34),
.B(n33),
.C(n32),
.Z(n36)
);
NAND2X1 U60 (
.A(count_to[6]),
.B(n45),
.Z(n35)
);
NAND2X1 U61 (
.A(n36),
.B(n35),
.Z(n38)
);
NAND2X1 U62 (
.A(count[7]),
.B(n41),
.Z(n37)
);
NAND2X1 U63 (
.A(n38),
.B(n37),
.Z(n39)
);
NAND2X1 U64 (
.A(n40),
.B(n39),
.Z(N3)
);
endmodule
| 6.562775 |
module counter_2 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55;
DFFQX1 \count_reg[0] (
.D (N25),
.CLK(clk),
.Q (count[0])
);
DFFQX1 \count_reg[7] (
.D (N32),
.CLK(clk),
.Q (count[7])
);
DFFQX1 \count_reg[6] (
.D (N31),
.CLK(clk),
.Q (count[6])
);
DFFQX1 \count_reg[5] (
.D (N30),
.CLK(clk),
.Q (count[5])
);
DFFQX1 \count_reg[4] (
.D (N29),
.CLK(clk),
.Q (count[4])
);
DFFQX1 \count_reg[3] (
.D (N28),
.CLK(clk),
.Q (count[3])
);
DFFQX1 \count_reg[2] (
.D (N27),
.CLK(clk),
.Q (count[2])
);
DFFQX1 \count_reg[1] (
.D (N26),
.CLK(clk),
.Q (count[1])
);
AND2X1 U3 (
.A(N13),
.B(n55),
.Z(N32)
);
AND2X1 U4 (
.A(N12),
.B(n55),
.Z(N31)
);
AND2X1 U6 (
.A(N11),
.B(n55),
.Z(N30)
);
AND2X1 U7 (
.A(N10),
.B(n55),
.Z(N29)
);
AND2X1 U8 (
.A(N9),
.B(n55),
.Z(N28)
);
AND2X1 U9 (
.A(N8),
.B(n55),
.Z(N27)
);
AND2X1 U10 (
.A(N7),
.B(n55),
.Z(N26)
);
AND2X1 U11 (
.A(n46),
.B(n55),
.Z(N25)
);
NOR2X1 U12 (
.A(reset),
.B(n54),
.Z(n55)
);
NOR2X1 U13 (
.A(N3),
.B(n53),
.Z(n54)
);
NOR2X1 U14 (
.A(n52),
.B(n51),
.Z(n53)
);
NAND2X1 U15 (
.A(n50),
.B(n49),
.Z(n51)
);
NOR2X1 U16 (
.A(count_to[3]),
.B(count_to[2]),
.Z(n49)
);
NOR2X1 U17 (
.A(count_to[1]),
.B(count_to[0]),
.Z(n50)
);
NAND2X1 U18 (
.A(n48),
.B(n47),
.Z(n52)
);
NOR2X1 U19 (
.A(count_to[7]),
.B(count_to[6]),
.Z(n47)
);
NOR2X1 U20 (
.A(count_to[5]),
.B(count_to[4]),
.Z(n48)
);
INVX2 U5 (
.A(count_to[7]),
.Z(n41)
);
INVX2 U21 (
.A(count[0]),
.Z(n46)
);
XOR2X1 U22 (
.A(count[2]),
.B(n1),
.Z(N8)
);
AND2X1 U23 (
.A(count[1]),
.B(count[0]),
.Z(n1)
);
INVX2 U24 (
.A(count[2]),
.Z(n42)
);
INVX2 U25 (
.A(count[3]),
.Z(n43)
);
INVX2 U26 (
.A(count[4]),
.Z(n44)
);
INVX2 U27 (
.A(count[6]),
.Z(n45)
);
INVX4 U28 (
.A(n2),
.Z(n17)
);
INVX2 U29 (
.A(count[5]),
.Z(n16)
);
XOR2X1 U30 (
.A(count[1]),
.B(count[0]),
.Z(N7)
);
NAND3X1 U31 (
.A(count[1]),
.B(count[0]),
.C(count[2]),
.Z(n2)
);
XOR2X1 U32 (
.A(count[3]),
.B(n17),
.Z(N9)
);
AND2X1 U33 (
.A(n17),
.B(count[3]),
.Z(n12)
);
XOR2X1 U34 (
.A(count[4]),
.B(n12),
.Z(N10)
);
NAND3X1 U35 (
.A(count[3]),
.B(n17),
.C(count[4]),
.Z(n13)
);
XOR2X1 U36 (
.A(n16),
.B(n13),
.Z(N11)
);
NOR2X1 U37 (
.A(n16),
.B(n13),
.Z(n14)
);
XOR2X1 U38 (
.A(count[6]),
.B(n14),
.Z(N12)
);
AND2X1 U39 (
.A(n14),
.B(count[6]),
.Z(n15)
);
XOR2X1 U40 (
.A(count[7]),
.B(n15),
.Z(N13)
);
OR2X1 U41 (
.A(n41),
.B(count[7]),
.Z(n40)
);
OR2X1 U42 (
.A(n16),
.B(count_to[5]),
.Z(n34)
);
OR2X1 U43 (
.A(n43),
.B(count_to[3]),
.Z(n28)
);
NAND2X1 U44 (
.A(count_to[0]),
.B(n46),
.Z(n18)
);
NAND2X1 U45 (
.A(count[1]),
.B(n18),
.Z(n22)
);
NOR2X1 U46 (
.A(count[1]),
.B(n18),
.Z(n19)
);
OR2X1 U47 (
.A(count_to[1]),
.B(n19),
.Z(n21)
);
OR2X1 U48 (
.A(n42),
.B(count_to[2]),
.Z(n20)
);
NAND3X1 U49 (
.A(n22),
.B(n21),
.C(n20),
.Z(n25)
);
NAND2X1 U50 (
.A(count_to[2]),
.B(n42),
.Z(n24)
);
NAND2X1 U51 (
.A(count_to[3]),
.B(n43),
.Z(n23)
);
NAND3X1 U52 (
.A(n25),
.B(n24),
.C(n23),
.Z(n27)
);
OR2X1 U53 (
.A(n44),
.B(count_to[4]),
.Z(n26)
);
NAND3X1 U54 (
.A(n28),
.B(n27),
.C(n26),
.Z(n31)
);
NAND2X1 U55 (
.A(count_to[4]),
.B(n44),
.Z(n30)
);
NAND2X1 U56 (
.A(count_to[5]),
.B(n16),
.Z(n29)
);
NAND3X1 U57 (
.A(n31),
.B(n30),
.C(n29),
.Z(n33)
);
OR2X1 U58 (
.A(n45),
.B(count_to[6]),
.Z(n32)
);
NAND3X1 U59 (
.A(n34),
.B(n33),
.C(n32),
.Z(n36)
);
NAND2X1 U60 (
.A(count_to[6]),
.B(n45),
.Z(n35)
);
NAND2X1 U61 (
.A(n36),
.B(n35),
.Z(n38)
);
NAND2X1 U62 (
.A(count[7]),
.B(n41),
.Z(n37)
);
NAND2X1 U63 (
.A(n38),
.B(n37),
.Z(n39)
);
NAND2X1 U64 (
.A(n40),
.B(n39),
.Z(N3)
);
endmodule
| 6.703607 |
module: synth_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module synth_top_testbench;
// Inputs
reg reset_io_p;
reg clk_io_p;
reg [15:0] data_in_io_p;
// Outputs
wire core_to_mem_enable_io_p;
wire [9:0] addr_out_io_p;
wire [15:0] data_out_io_p;
wire pwm0_io_p;
wire pwm1_io_p;
wire pwm2_io_p;
wire pwm3_io_p;
wire pwm4_io_p;
wire pwm5_io_p;
wire pwm6_io_p;
wire pwm7_io_p;
reg [15:0] mem [0:1023];
// Bidirs
wire sda_io_p;
wire scl_io_p;
/*
// Instantiate the Unit Under Test (UUT)
synth_top uut (
.reset_io(reset_io),
.clk_io(clk_io),
.data_in_io(data_in_io),
.data_out_io(data_out_io),
.addr_out_io(addr_out_io),
.core_to_mem_enable_io(core_to_mem_enable_io),
.sda_io(sda_io),
.scl_io(scl_io),
.pwm0_io(pwm0_io),
.pwm1_io(pwm1_io),
.pwm2_io(pwm2_io),
.pwm3_io(pwm3_io),
.pwm4_io(pwm4_io),
.pwm5_io(pwm5_io),
.pwm6_io(pwm6_io),
.pwm7_io(pwm7_io)
);
*/
synth_top_top uut(
.reset_io(reset_io),
.clk_io(clk_io_p),
.data_in_io(data_in_io_p),
.data_out_io(data_out_io_p),
.addr_out_io(addr_out_io_p),
.core_to_mem_enable_io(core_to_mem_enable_io_p),
.sda_io(sda_io_p),
.scl_io(scl_io_p),
.pwm0_io(pwm0_io_p),
.pwm1_io(pwm1_io_p),
.pwm2_io(pwm2_io_p),
.pwm3_io(pwm3_io_p),
.pwm4_io(pwm4_io_p),
.pwm5_io(pwm5_io_p),
.pwm6_io(pwm6_io_p),
.pwm7_io(pwm7_io_p)
);
initial begin
// Initialize Inputs
reset_io_p = 0;
clk_io_p = 0;
data_in_io_p = 0;
// make memory
//* program to test PWM
mem[0] = 16'b0100_1111_0010_0000;
mem[1] = 16'b0100_1000_1111_1111;
mem[2] = 16'b0101_1000_0000_0000;
mem[3] = 16'b0100_0100_0000_1100;
mem[4] = 16'b0010_0000_0100_0100;
mem[5] = 16'b1001_0001_1000_0000;
mem[6] = 16'b0100_0111_0000_0001;
mem[7] = 16'b1101_0000_0001_0000;
mem[8] = 16'b0011_1000_1111_1000;
mem[9] = 16'b0100_0010_0000_0001;
mem[10] = 16'b1011_1000_1000_0010;
mem[11] = 16'b0011_0000_1111_0111;
mem[12] = 16'b0100_0010_0000_0001;
mem[13] = 16'b1010_1111_1111_0010;
mem[14] = 16'b0001_1111_0000_0011;
mem[15] = 16'b0100_0011_0001_0001;
mem[16] = 16'b0100_0001_1111_1111;
mem[17] = 16'b1101_0000_0001_0000;
mem[18] = 16'b0011_1000_0000_0010;
mem[19] = 16'b1011_0001_0001_0010;
mem[20] = 16'b0010_0000_0000_0011;
mem[21] = 16'b0000_1111_0000_0011;
mem[22] = 16'b1011_1111_1111_0010;
mem[23] = 16'b0010_0000_0000_0101;
/*end of test PWM */
/* program to test I2C
mem[0] = 16'b0100_0110_0101_1000;
mem[1] = 16'b0100_0111_0010_0001;
mem[2] = 16'b0101_0111_1111_0001;
mem[3] = 16'b0101_0110_0000_0001;
/*end of test I2C */
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#11;
reset_io_p = 1;
#502 reset_io_p = 0;
end
// read from memory
always @(*)
begin
data_in_io_p = mem[addr_out_io_p];
end
//write to memory
always @(posedge clk_io_p)
begin
if(core_to_mem_enable_io_p) begin
mem[addr_out_io_p] = data_out_io_p;
end
end
// run 10 MHz clock
always begin #50 assign clk_io_p = ~clk_io_p; end
endmodule
| 6.889969 |
module shift_register_v (
C,
SI,
SO
);
input C, SI;
output SO;
wire [6:0] tmp;
DFFQX1 \tmp_reg[0] (
.D (SI),
.CLK(C),
.Q (tmp[0])
);
DFFQX1 \tmp_reg[1] (
.D (tmp[0]),
.CLK(C),
.Q (tmp[1])
);
DFFQX1 \tmp_reg[2] (
.D (tmp[1]),
.CLK(C),
.Q (tmp[2])
);
DFFQX1 \tmp_reg[3] (
.D (tmp[2]),
.CLK(C),
.Q (tmp[3])
);
DFFQX1 \tmp_reg[4] (
.D (tmp[3]),
.CLK(C),
.Q (tmp[4])
);
DFFQX1 \tmp_reg[5] (
.D (tmp[4]),
.CLK(C),
.Q (tmp[5])
);
DFFQX1 \tmp_reg[6] (
.D (tmp[5]),
.CLK(C),
.Q (tmp[6])
);
DFFQX1 \tmp_reg[7] (
.D (tmp[6]),
.CLK(C),
.Q (SO)
);
endmodule
| 6.854847 |
module syn_4bit_upcounter (
d_out,
d_in,
load,
reset,
clk
);
output reg [3:0] d_out;
input [3:0] d_in;
input load, reset, clk;
always @(posedge clk) begin
if (reset) d_out <= 4'b0000;
else if (load) d_out <= d_in;
else d_out <= d_out + 1'b1;
end
endmodule
| 6.508778 |
module syn_4bit_upcounter_tb ();
reg [3:0] d_in;
reg load, reset, clk;
wire [3:0] d_out;
syn_4bit_upcounter DUT (
d_out,
d_in,
load,
reset,
clk
);
always begin
clk = 1'b0;
forever #5 clk = ~clk;
end
task initialize;
begin
d_in = 4'b0000;
load = 1'b0;
reset = 1'b0;
end
endtask
task loadip;
begin
@(negedge clk) load = 1'b1;
@(negedge clk) load = 1'b0;
end
endtask
task resetips;
begin
@(negedge clk) reset = 1'b1;
@(negedge clk) reset = 1'b0;
end
endtask
task dataip(input [3:0] d);
begin
@(negedge clk) d_in <= d;
end
endtask
initial begin
initialize;
resetips;
dataip(4'b0011);
loadip;
#40;
resetips;
dataip(4'b1011);
loadip;
#20;
loadip;
#30;
resetips;
initialize;
end
initial begin
$monitor("clock=%b,reset=%b , load=%b, d_in=%b %d ,d_out=%b %d", clk, reset, load, d_in,
d_in, d_out, d_out);
end
initial begin
#200 $finish;
end
endmodule
| 6.508778 |
module transform asynchrounous signal to a
// specific domain. We use four flip-flops in this module to do
// this work
// -----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
(*dont_touch = "yes" *)
module syn_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = 5
)
(
input clk,//clock to be sync'ed to
input data_in,//data to be synced
input enable,
output data_out//synced data
);
//------------------------------- Internal Signal ----------------------------------------
wire data_sync0;
wire data_sync1;
wire data_sync2;
wire data_sync3;
wire data_sync4;
wire data_sync5;
//-----------------------------------------------------------------------------
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT (INITIALISE[0])
) data_sync_reg0 (
.C (clk),
.D (data_in),
.Q (data_sync0),
.CE (enable),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT (INITIALISE[0])
) data_sync_reg1 (
.C (clk),
.D (data_sync0),
.Q (data_sync1),
.CE (enable),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT (INITIALISE[0])
) data_sync_reg2 (
.C (clk),
.D (data_sync1),
.Q (data_sync2),
.CE (enable),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT (INITIALISE[0])
) data_sync_reg3 (
.C (clk),
.D (data_sync2),
.Q (data_sync3),
.CE (enable),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT (INITIALISE[0])
) data_sync_reg4 (
.C (clk),
.D (data_sync3),
.Q (data_sync4),
.CE (enable),
.R (1'b0)
);
assign data_out = data_sync4;
endmodule
| 7.511081 |
module name - syn_clk_judge
// Version: V3.4.0.20220420
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
module syn_clk_judge(
input i_clk,
input i_rst_n,
input [63:0] iv_syn_clk,
input i_tsn_or_tte, //1表示1588，0表示6802
input [31:0] iv_syn_clk_cycle,//时钟同步周期6802
output reg [63:0] ov_syn_clk
);
reg r_syn_cycle_timer;//新增，周期计时，表示第几个时钟周期
reg [63:0] rv_syn_cycle_offset;
always@(posedge i_clk or negedge i_rst_n)begin
if(!i_rst_n) begin
r_syn_cycle_timer<=1'b0;
rv_syn_cycle_offset<=64'd0;
ov_syn_clk <=64'd0;
end
else begin
if(i_tsn_or_tte==1'b1)begin
ov_syn_clk<=iv_syn_clk;
end
else begin
if(iv_syn_clk==iv_syn_clk_cycle-32'd8)begin
if(r_syn_cycle_timer==1'b0) begin
r_syn_cycle_timer <=1'b1;
rv_syn_cycle_offset <= iv_syn_clk_cycle;
ov_syn_clk <= iv_syn_clk;
end
else begin
rv_syn_cycle_offset <= rv_syn_cycle_offset + iv_syn_clk_cycle;
r_syn_cycle_timer <= r_syn_cycle_timer;
ov_syn_clk <= rv_syn_cycle_offset+ iv_syn_clk;
end
end
else begin
ov_syn_clk <= rv_syn_cycle_offset +iv_syn_clk;
end
end
end
end
endmodule
| 7.149958 |
module syn_dff_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_syn_q;
//
// Synchronous DFF
//
syn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_syn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Generates a reset signal and the rising edge is active
//
initial begin
t_rst = 0;
#10;
t_rst = 1;
#20;
t_rst = 0;
end
//
// Control signal
//
initial begin
t_d = 1;
#25 t_d = 0;
#15 t_d = 1;
#25 t_d = 0;
#25 t_d = 1;
#25 t_d = 0;
#30 t_d = 1;
#20 $finish;
end
endmodule
| 7.077913 |
module syn_dual_16x8ram (
d_out,
d_in,
clock,
reset,
wr_en,
wr_addr,
rd_en,
rd_addr
);
parameter RAM_WIDTH = 8, RAM_DEPTH = 16, ADDR_SIZE = 4;
output reg [RAM_WIDTH-1:0] d_out;
input [RAM_WIDTH-1:0] d_in;
input clock, reset, wr_en, rd_en;
input [ADDR_SIZE-1:0] wr_addr, rd_addr;
reg [RAM_WIDTH-1:0] mem[0:RAM_DEPTH-1];
integer i;
always @(posedge clock) begin
if (reset) begin
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
mem[i] <= 0;
end
end else if (wr_en == 1) mem[wr_addr] <= d_in;
end
always @(posedge clock) begin
if (reset) d_out <= 0;
else if (rd_en) d_out <= mem[rd_addr];
end
endmodule
| 7.717203 |
module syn_dual_16x8ram_tb ();
parameter RAM_WIDTH = 8, RAM_DEPTH = 16, ADDR_SIZE = 4;
reg [RAM_WIDTH-1:0] d_in;
reg clock, reset, wr_en, rd_en;
reg [ADDR_SIZE-1:0] wr_addr, rd_addr;
wire [RAM_WIDTH-1:0] d_out;
syn_dual_16x8ram DUT (
d_out,
d_in,
clock,
reset,
wr_en,
wr_addr,
rd_en,
rd_addr
);
always begin
clock = 1'b0;
forever #5 clock = ~clock;
end
task initialize;
begin
d_in <= 0;
{wr_en, rd_en} = 2'b00;
{wr_addr, rd_addr} = 8'h00;
end
endtask
task resetips;
begin
@(negedge clock) reset = 1'b1;
@(negedge clock) reset = 1'b0;
end
endtask
task write(input [RAM_WIDTH-1:0] wd, input [ADDR_SIZE-1:0] wa);
begin
@(negedge clock) wr_en = 1'b1;
d_in <= wd;
wr_addr <= wa;
end
endtask
task read(input [ADDR_SIZE-1:0] rd);
begin
@(negedge clock) rd_en = 1'b1;
rd_addr <= rd;
end
endtask
initial begin
initialize;
resetips;
write(8'h10, 4'h7);
#10;
read(4'h7);
#10;
write(8'hAA, 4'hA);
#10 read(4'hA);
#10;
write(8'hFF, 4'hF);
#10;
read(4'hF);
#10;
resetips;
end
initial begin
$monitor("d_out=%b, d_in=%b, reset=%b, wr_en=%b, wr_addr=%b, rd_en=%b,rd_addr=%b", d_out, d_in,
reset, wr_en, wr_addr, rd_en, rd_addr);
end
initial begin
#200 $finish;
end
endmodule
| 7.717203 |
module syn_fifo (
clk,
rstn,
wr_en,
rd_en,
wr_data,
rd_data,
fifo_full,
fifo_empty
);
//
parameter width = 8;
parameter depth = 8;
parameter addr = 3;
//ź
input clk; //ʱź
input rstn; //½ظλ
input wr_en; //дʹ
input rd_en; //ȡʹ
//ź
input [width - 1 : 0] wr_data; //д
output [width - 1 : 0] rd_data; //
reg [width - 1 : 0] rd_data;
//жź
output fifo_full;
output fifo_empty;
//һжϿ
reg [$clog2(depth):0] cnt;
//дַ
reg [depth - 1 : 0] wr_ptr;
reg [depth - 1 : 0] rd_ptr;
//һΪΪwidthΪdepthfifo
reg [width - 1 : 0] fifo[depth - 1 : 0];
//дַ
always @(posedge clk or negedge rstn) begin
if (!rstn) wr_ptr <= 0;
else if (wr_en && !fifo_full) //дʹܣfifoδд
wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
end
//ַ
always @(posedge clk or negedge rstn) begin
if (!rstn) rd_ptr <= 0;
else if (rd_en && !fifo_empty) //ʹܣfifoΪ
rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
//д
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin //λfifo
for (i = 0; i < depth; i = i + 1) fifo[i] <= 0;
end else if (wr_en) //дʹʱдfifo
fifo[wr_ptr] <= wr_data;
else //
fifo[wr_ptr] <= fifo[wr_ptr];
end
//
always @(posedge clk or negedge rstn) begin
if (!rstn) rd_data <= 0;
else if (rd_en) rd_data <= fifo[rd_ptr]; //fifoжȡ
else rd_data <= rd_data;
end
//жϿ
always @(posedge clk or negedge rstn) begin
if (!rstn) cnt <= 0;
else if (wr_en && !rd_en && !fifo_full) //Чֻд
cnt <= cnt + 1;
else if (!wr_en && rd_en && !fifo_empty) //Чֻȡ
cnt <= cnt - 1;
else cnt <= cnt;
end
//ж
assign fifo_full = (cnt == depth) ? 1 : 0;
assign fifo_empty = (cnt == 0) ? 1 : 0;
endmodule
| 7.246965 |
module syn_fifo (
clk, // Clock input
rst, // Active high reset
wr_cs, // Write chip select
rd_cs, // Read chipe select
data_in, // Data input
rd_en, // Read enable
wr_en, // Write Enable
data_out, // Data Output
empty, // FIFO empty
full // FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk;
input rst;
input wr_cs;
input rd_cs;
input rd_en;
input wr_en;
input [DATA_WIDTH-1:0] data_in;
output full;
output empty;
output [DATA_WIDTH-1:0] data_out;
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH : 0] status_cnt;
reg [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_ram;
//-----------Variable assignments---------------
assign full = (status_cnt == (RAM_DEPTH - 1));
assign empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @(posedge clk or posedge rst) begin : WRITE_POINTER
if (rst) begin
wr_pointer <= 0;
end else if (wr_cs && wr_en) begin
wr_pointer <= wr_pointer + 1;
end
end
always @(posedge clk or posedge rst) begin : READ_POINTER
if (rst) begin
rd_pointer <= 0;
end else if (rd_cs && rd_en) begin
rd_pointer <= rd_pointer + 1;
end
end
always @(posedge clk or posedge rst) begin : READ_DATA
if (rst) begin
data_out <= 0;
end else if (rd_cs && rd_en) begin
data_out <= data_ram;
end
end
always @(posedge clk or posedge rst) begin : STATUS_COUNTER
if (rst) begin
status_cnt <= 0;
// Read but no write.
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en) && (status_cnt != 0)) begin
status_cnt <= status_cnt - 1;
// Write but no read.
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en) && (status_cnt != RAM_DEPTH)) begin
status_cnt <= status_cnt + 1;
end
end
ram_dp_ar_aw #(DATA_WIDTH, ADDR_WIDTH) DP_RAM (
.address_0(wr_pointer), // address_0 input
.data_0 (data_in), // data_0 bi-directional
.cs_0 (wr_cs), // chip select
.we_0 (wr_en), // write enable
.oe_0 (1'b0), // output enable
.address_1(rd_pointer), // address_q input
.data_1 (data_ram), // data_1 bi-directional
.cs_1 (rd_cs), // chip select
.we_1 (1'b0), // Read enable
.oe_1 (rd_en) // output enable
);
// Add assertion here
// synopsys translate_off
// Assertion to check overflow and underflow
assert_fifo_index #(`OVL_ERROR, // severity_level
(RAM_DEPTH - 1), // depth
1, // push width
1, // pop width
`OVL_ASSERT, // property type
"my_module_err", // msg
`OVL_COVER_NONE, //coverage_level
1) no_over_under_flow (
.clk (clk), // Clock
.reset_n(~rst), // Active low reset
.pop (rd_cs & rd_en), // FIFO Write
.push (wr_cs & wr_en) // FIFO Read
);
// Assertion to check full and write
assert_always #(`OVL_ERROR, // severity_level
`OVL_ASSERT, // property_type
"fifo_full_write", // msg
`OVL_COVER_NONE // coverage_level
) no_full_write (
.clk (clk),
.reset_n (~rst),
.test_expr(!(full && wr_cs && wr_en))
);
// Assertion to check empty and read
assert_never #(`OVL_ERROR, // severity_level
`OVL_ASSERT, // property_type
"fifo_empty_read", // msg
`OVL_COVER_NONE // coverage_level
) no_empty_read (
.clk (clk),
.reset_n (~rst),
.test_expr((empty && rd_cs && rd_en))
);
// Assertion to check if write pointer increments by just one
assert_increment #(`OVL_ERROR, // severity_level
ADDR_WIDTH, // width
1, // value
`OVL_ASSERT, // property_typ
"Write_Pointer_Error", // msg
`OVL_COVER_NONE // coverage_level
) write_count (
.clk (clk),
.reset_n (~rst),
.test_expr(wr_pointer)
);
// synopsys translate_on
endmodule
| 7.246965 |
module syn_fifo (
clk, // Clock input
rst, // Active high reset
wr_cs, // Write chip select
rd_cs, // Read chipe select
data_in, // Data input
rd_en, // Read enable
wr_en, // Write Enable
data_out, // Data Output
empty, // FIFO empty
full // FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk;
input rst;
input wr_cs;
input rd_cs;
input rd_en;
input wr_en;
input [DATA_WIDTH-1:0] data_in;
output full;
output empty;
output [DATA_WIDTH-1:0] data_out;
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH : 0] status_cnt;
reg [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_ram;
//-----------Variable assignments---------------
assign full = (status_cnt == (RAM_DEPTH - 1));
assign empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @(posedge clk or posedge rst) begin : WRITE_POINTER
if (rst) begin
wr_pointer <= 0;
end else if (wr_cs && wr_en) begin
wr_pointer <= wr_pointer + 1;
end
end
always @(posedge clk or posedge rst) begin : READ_POINTER
if (rst) begin
rd_pointer <= 0;
data_out <= 0;
end else if (rd_cs && rd_en) begin
rd_pointer <= rd_pointer + 1;
data_out <= data_ram;
end
end
always @(posedge clk or posedge rst) begin : READ_DATA
if (rst) begin
data_out <= 0;
end else if (rd_cs && rd_en) begin
data_out <= data_ram;
end
end
always @(posedge clk or posedge rst) begin : STATUS_COUNTER
if (rst) begin
status_cnt <= 0;
// Read but no write.
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en) && (status_cnt != 0)) begin
status_cnt <= status_cnt - 1;
// Write but no read.
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en) && (status_cnt != RAM_DEPTH)) begin
status_cnt <= status_cnt + 1;
end
end
ram_dp_ar_aw #(DATA_WIDTH, ADDR_WIDTH) DP_RAM (
.address_0(wr_pointer), // address_0 input
.data_0 (data_in), // data_0 bi-directional
.cs_0 (wr_cs), // chip select
.we_0 (wr_en), // write enable
.oe_0 (1'b0), // output enable
.address_1(rd_pointer), // address_q input
.data_1 (data_ram), // data_1 bi-directional
.cs_1 (rd_cs), // chip select
.we_1 (1'b0), // Read enable
.oe_1 (rd_en) // output enable
);
// Add assertion here
// psl default clock = (posedge clk);
// psl ERRORwritefull: assert never {full && wr_en && wr_cs};
// psl ERRORreadempty: assert never {empty && rd_en && rd_cs};
endmodule
| 7.246965 |
module syn_fifo_tb;
reg clk, rstn;
reg wr_en, rd_en;
wire fifo_full, fifo_empty;
reg [7 : 0] wr_data;
wire [7 : 0] rd_data;
//ɲ
initial begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars(0, myfifo);
$fsdbDumpon();
end
//
syn_fifo myfifo (
.clk(clk),
.rstn(rstn),
.wr_en(wr_en),
.rd_en(rd_en),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty),
.wr_data(wr_data),
.rd_data(rd_data)
);
initial begin
rstn = 1;
wr_en = 0;
rd_en = 0;
repeat (2) @(negedge clk);
rstn = 0;
@(negedge clk);
rstn = 1;
@(negedge clk);
wr_data = {$random} % 60;
wr_en = 1;
repeat (2) @(negedge clk);
wr_data = {$random} % 60;
@(negedge clk);
wr_en = 0;
rd_en = 1;
repeat (4) @(negedge clk);
rd_en = 0;
wr_en = 1;
wr_data = {$random} % 60;
repeat (5) @(negedge clk);
wr_data = {$random} % 60;
repeat (2) @(negedge clk);
wr_en = 0;
rd_en = 1;
repeat (2) @(negedge clk);
rd_en = 0;
wr_en = 1;
wr_data = {$random} % 60;
repeat (3) @(negedge clk);
wr_en = 0;
#50 $finish;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule
| 6.527895 |
module syn_fifo_v1_Nb #(
parameter BUS_WIDTH = 8,
FIFO_DEPTH = 8
) (
input RSTn,
input CLK,
input [BUS_WIDTH-1:0] DATA_IN,
input WR_EN,
input RD_EN,
output FULL,
output EMPTY,
output reg [BUS_WIDTH-1:0] DATA_OUT
);
localparam COUNTER_WIDTH = $clog2(FIFO_DEPTH) + (2 ** $clog2(FIFO_DEPTH) > FIFO_DEPTH);
reg [BUS_WIDTH-1:0] MEM[FIFO_DEPTH-1:0];
reg [COUNTER_WIDTH:0] count;
reg [COUNTER_WIDTH-1:0] wr_count, rd_count;
integer i = 0;
always @(posedge CLK or negedge RSTn) begin
count <= count;
wr_count <= wr_count;
rd_count <= rd_count;
DATA_OUT <= DATA_OUT;
for (i = 0; i < 2 ** COUNTER_WIDTH; i = i + 1) begin
//MEM[i] <= MEM[i];
end
if (!RSTn) begin
count <= 0;
wr_count <= 0;
rd_count <= 0;
end else begin
// Write first priority
if (count != FIFO_DEPTH && WR_EN) begin
count <= count + 1'b1;
wr_count <= wr_count + 1'b1;
MEM[wr_count] <= DATA_IN;
end else if (count != 0 && RD_EN) begin
count <= count - 1'b1;
rd_count <= rd_count + 1'b1;
DATA_OUT <= MEM[rd_count];
end
end
end
assign FULL = (count == FIFO_DEPTH);
assign EMPTY = (count == 0);
endmodule
| 7.046492 |
module syn_filt_pipe (
clk,
reset,
start,
memIn,
xAddr,
aAddr,
yAddr,
fMemAddr,
updateAddr,
done,
lagMuxSel,
lagMux1Sel,
lagMux2Sel,
lagMux3Sel,
testReadRequested,
testWriteRequested,
testWriteOut,
testWriteEnable
);
// Inputs
input clk;
input reset;
input start;
input [11:0] xAddr;
input [11:0] aAddr;
input [11:0] yAddr;
input [11:0] fMemAddr;
input [11:0] updateAddr;
// Outputs
output done;
output [31:0] memIn;
wire [31:0] L_addOutA;
wire [31:0] L_addOutB;
wire [15:0] L_multOutA;
wire [15:0] L_multOutB;
wire [31:0] L_shlOutVar1;
wire [15:0] L_shlNumShiftOut;
wire L_shlReady;
wire [15:0] L_msuOutA;
wire [15:0] L_msuOutB;
wire [31:0] L_msuOutC;
wire [31:0] L_addIn;
wire [31:0] L_multIn;
wire [31:0] L_shlIn;
wire [31:0] L_msuIn;
wire [31:0] memOut;
wire memWriteEn;
wire [11:0] memWriteAddr;
wire unusedOverflow1;
wire unusedOverflow2;
//Mux0 regs
input lagMuxSel;
reg [11:0] lagMuxOut;
input [11:0] testReadRequested;
//Mux1 regs
input lagMux1Sel;
reg [11:0] lagMux1Out;
input [11:0] testWriteRequested;
//Mux2 regs
input lagMux2Sel;
reg [31:0] lagMux2Out;
input [31:0] testWriteOut;
//Mux3 regs
input lagMux3Sel;
reg lagMux3Out;
input testWriteEnable;
//integer i, j;
// Instantiate the Unit Under Test (UUT)
syn_filt fsm (
.clk(clk),
.reset(reset),
.start(start),
.memIn(memIn),
.memWriteEn(memWriteEn),
.memWriteAddr(memWriteAddr),
.memOut(memOut),
.done(done),
.xAddr(xAddr),
.aAddr(aAddr),
.yAddr(yAddr),
.updateAddr(updateAddr),
.fMemAddr(fMemAddr),
.L_addOutA(L_addOutA),
.L_addOutB(L_addOutB),
.L_addIn(L_addIn),
.L_multOutA(L_multOutA),
.L_multOutB(L_multOutB),
.L_multIn(L_multIn),
.L_shlIn(L_shlIn),
.L_shlDone(L_shlDone),
.L_shlOutVar1(L_shlOutVar1),
.L_shlNumShiftOut(L_shlNumShiftOut),
.L_shlReady(L_shlReady),
.L_msuIn(L_msuIn),
.L_msuOutA(L_msuOutA),
.L_msuOutB(L_msuOutB),
.L_msuOutC(L_msuOutC)
);
Scratch_Memory_Controller convMem (
.addra(lagMux1Out),
.dina (lagMux2Out),
.wea (lagMux3Out),
.clk (clk),
.addrb(lagMuxOut),
.doutb(memIn)
);
L_add conv_L_add (
.a(L_addOutA),
.b(L_addOutB),
.overflow(),
.sum(L_addIn)
);
L_mult conv_L_mult (
.a(L_multOutA),
.b(L_multOutB),
.overflow(),
.product(L_multIn)
);
L_shl L_shl1 (
.clk(clk),
.reset(reset),
.ready(L_shlReady),
.overflow(unusedOverflow1),
.var1(L_shlOutVar1),
.numShift(L_shlNumShiftOut),
.done(L_shlDone),
.out(L_shlIn)
);
L_msu conv_L_msu (
.a(L_msuOutA),
.b(L_msuOutB),
.c(L_msuOutC),
.overflow(unusedOverflow2),
.out(L_msuIn)
);
//lag read address mux
always @(*) begin
case (lagMuxSel)
'd0: lagMuxOut = memWriteAddr;
'd1: lagMuxOut = testReadRequested;
endcase
end
//lag write address mux
always @(*) begin
case (lagMux1Sel)
'd0: lagMux1Out = memWriteAddr;
'd1: lagMux1Out = testWriteRequested;
endcase
end
//lag write output mux
always @(*) begin
case (lagMux2Sel)
'd0: lagMux2Out = memOut;
'd1: lagMux2Out = testWriteOut;
endcase
end
//lag write enable mux
always @(*) begin
case (lagMux3Sel)
'd0: lagMux3Out = memWriteEn;
'd1: lagMux3Out = testWriteEnable;
endcase
end
endmodule
| 6.531015 |
module Register #(
parameter WORD_WIDTH = 0,
parameter RESET_VALUE = 0
) (
input clock,
input clock_enable,
input clear,
input [WORD_WIDTH-1:0] data_in,
output reg [WORD_WIDTH-1:0] data_out
);
initial begin
data_out = RESET_VALUE;
end
always @(posedge clock) begin
if (clock_enable == 1'b1) begin
data_out <= data_in;
end
if (clear == 1'b1) begin
data_out <= RESET_VALUE;
end
end
endmodule
| 6.555282 |
module Multiplexer_Binary_Behavioural #(
parameter WORD_WIDTH = 0,
parameter ADDR_WIDTH = 0,
parameter INPUT_COUNT = 0,
// Do not set at instantiation
parameter TOTAL_WIDTH = WORD_WIDTH * INPUT_COUNT
) (
input [ADDR_WIDTH-1:0] selector,
input [TOTAL_WIDTH-1:0] words_in,
output reg [WORD_WIDTH-1:0] word_out
);
initial begin
word_out = {WORD_WIDTH{1'b0}};
end
always @(*) begin
word_out = words_in[(selector*WORD_WIDTH)+:WORD_WIDTH];
end
endmodule
| 7.156108 |
module Register_Pipeline #(
parameter WORD_WIDTH = 0,
parameter PIPE_DEPTH = 0,
// Don't set at instantiation
parameter TOTAL_WIDTH = WORD_WIDTH * PIPE_DEPTH,
// concatenation of each stage initial/reset value
parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0
) (
input clock,
input clock_enable,
input clear,
input parallel_load,
input [TOTAL_WIDTH-1:0] parallel_in,
output reg [TOTAL_WIDTH-1:0] parallel_out,
input [WORD_WIDTH-1:0] pipe_in,
output reg [WORD_WIDTH-1:0] pipe_out
);
localparam WORD_ZERO = {WORD_WIDTH{1'b0}};
initial begin
pipe_out = WORD_ZERO;
end
wire [WORD_WIDTH-1:0] pipe_stage_in [PIPE_DEPTH-1:0];
wire [WORD_WIDTH-1:0] pipe_stage_out[PIPE_DEPTH-1:0];
(* multstyle = "logic" *)
// Quartus
(* use_dsp = "no" *)
// Vivado
Multiplexer_Binary_Behavioural #(
.WORD_WIDTH (WORD_WIDTH),
.ADDR_WIDTH (1),
.INPUT_COUNT(2)
) pipe_input_select (
.selector(parallel_load),
.words_in({parallel_in[0+:WORD_WIDTH], pipe_in}),
.word_out(pipe_stage_in[0])
);
Register #(
.WORD_WIDTH (WORD_WIDTH),
.RESET_VALUE(RESET_VALUES[0+:WORD_WIDTH])
) pipe_stage (
.clock (clock),
.clock_enable(clock_enable),
.clear (clear),
.data_in (pipe_stage_in[0]),
.data_out (pipe_stage_out[0])
);
always @(*) begin
parallel_out[0+:WORD_WIDTH] = pipe_stage_out[0];
end
generate
genvar i;
for (i = 1; i < PIPE_DEPTH; i = i + 1) begin : pipe_stages
(* multstyle = "logic" *)
// Quartus
(* use_dsp = "no" *)
// Vivado
Multiplexer_Binary_Behavioural #(
.WORD_WIDTH (WORD_WIDTH),
.ADDR_WIDTH (1),
.INPUT_COUNT(2)
) pipe_input_select (
.selector(parallel_load),
.words_in({parallel_in[WORD_WIDTH*i+:WORD_WIDTH], pipe_stage_out[i-1]}),
.word_out(pipe_stage_in[i])
);
Register #(
.WORD_WIDTH (WORD_WIDTH),
.RESET_VALUE(RESET_VALUES[WORD_WIDTH*i+:WORD_WIDTH])
) pipe_stage (
.clock (clock),
.clock_enable(clock_enable),
.clear (clear),
.data_in (pipe_stage_in[i]),
.data_out (pipe_stage_out[i])
);
always @(*) begin
parallel_out[WORD_WIDTH*i+:WORD_WIDTH] = pipe_stage_out[i];
end
end
endgenerate
always @(*) begin
pipe_out = pipe_stage_out[PIPE_DEPTH-1];
end
endmodule
| 8.366929 |
module Synthesis_Harness_Input #(
parameter WORD_WIDTH = 0
) (
input clock,
input clear,
input bit_in,
input bit_in_valid,
output [WORD_WIDTH-1:0] word_out
);
localparam WORD_ZERO = {WORD_WIDTH{1'b0}};
// Vivado: don't put in I/O buffers, and keep netlists separate in synth and implementation.
(* IOB = "false" *)
(* DONT_TOUCH = "true" *)
// Quartus: don't use I/O buffers, and don't merge registers with others.
(* useioff = 0 *)
(* preserve *)
Register_Pipeline #(
.WORD_WIDTH (1),
.PIPE_DEPTH (WORD_WIDTH),
.RESET_VALUES(WORD_ZERO)
) shift_bit_into_word (
.clock (clock),
.clock_enable (bit_in_valid),
.clear (clear),
.parallel_load(1'b0),
.parallel_in (WORD_ZERO),
.parallel_out (word_out),
.pipe_in (bit_in),
.pipe_out ()
);
endmodule
| 8.207706 |
module Synthesis_Harness_Output #(
parameter WORD_WIDTH = 0
) (
input clock,
input clear,
input [WORD_WIDTH-1:0] word_in,
input word_in_valid,
output reg bit_out
);
localparam WORD_ZERO = {WORD_WIDTH{1'b0}};
initial begin
bit_out = 1'b0;
end
wire [WORD_WIDTH-1:0] word_out;
// Vivado: don't put in I/O buffers, and keep netlists separate in synth and implementation.
(* IOB = "false" *)
(* DONT_TOUCH = "true" *)
// Quartus: don't use I/O buffers, and don't merge registers with others.
(* useioff = 0 *)
(* preserve *)
Register_Pipeline #(
.WORD_WIDTH (WORD_WIDTH),
.PIPE_DEPTH (1),
.RESET_VALUES(WORD_ZERO)
) word_register (
.clock (clock),
.clock_enable (word_in_valid),
.clear (clear),
.parallel_load(1'b0),
.parallel_in (WORD_ZERO),
.parallel_out (),
.pipe_in (word_in),
.pipe_out (word_out)
);
always @(*) begin
bit_out = ^word_out;
end
endmodule
| 8.207706 |
module \$paramod\adder\WIDTH=32 (
operand_a,
operand_b,
result
);
(* src = "../core/common/adder.sv:12.24-12.33" *)
input [31:0] operand_a;
(* src = "../core/common/adder.sv:13.24-13.33" *)
input [31:0] operand_b;
(* src = "../core/common/adder.sv:14.24-14.30" *)
output [31:0] result;
assign result = operand_a + (* src = "../core/common/adder.sv:17.21-17.42" *) operand_b;
endmodule
| 7.306332 |
module \$paramod\multiplexer2\WIDTH=32 (
in0,
in1,
sel,
out
);
(* src = "../core/common/multiplexer2.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer2.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer2.sv:15.24-15.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer2.sv:14.24-14.27" *)
input sel;
(* src = "../core/common/multiplexer2.sv:21.7-25.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=2 multiplexer (
.in_bus({in0, in1}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module \$paramod\multiplexer4\WIDTH=32 (
in0,
in1,
in2,
in3,
sel,
out
);
(* src = "../core/common/multiplexer4.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer4.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer4.sv:14.24-14.27" *)
input [31:0] in2;
(* src = "../core/common/multiplexer4.sv:15.24-15.27" *)
input [31:0] in3;
(* src = "../core/common/multiplexer4.sv:17.24-17.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer4.sv:16.24-16.27" *)
input [1:0] sel;
(* src = "../core/common/multiplexer4.sv:23.7-27.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=4 multiplexer (
.in_bus({in0, in1, in2, in3}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module \$paramod\multiplexer8\WIDTH=32 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
(* src = "../core/common/multiplexer8.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer8.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer8.sv:14.24-14.27" *)
input [31:0] in2;
(* src = "../core/common/multiplexer8.sv:15.24-15.27" *)
input [31:0] in3;
(* src = "../core/common/multiplexer8.sv:16.24-16.27" *)
input [31:0] in4;
(* src = "../core/common/multiplexer8.sv:17.24-17.27" *)
input [31:0] in5;
(* src = "../core/common/multiplexer8.sv:18.24-18.27" *)
input [31:0] in6;
(* src = "../core/common/multiplexer8.sv:19.24-19.27" *)
input [31:0] in7;
(* src = "../core/common/multiplexer8.sv:21.24-21.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer8.sv:20.24-20.27" *)
input [2:0] sel;
(* src = "../core/common/multiplexer8.sv:27.7-31.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=8 multiplexer (
.in_bus({in0, in1, in2, in3, in4, in5, in6, in7}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=2 (
in_bus,
sel,
out
);
wire _0_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [63:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[0] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[1] ;
(* src = "../core/common/multiplexer.sv:14.45-14.48" *)
output [31:0] out;
(* src = "../core/common/multiplexer.sv:13.45-13.48" *)
input sel;
function [31:0] _1_;
input [31:0] a;
input [63:0] b;
input [1:0] s;
(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) (* parallel_case *)
casez (s)
2'b?1: _1_ = b[31:0];
2'b1?: _1_ = b[63:32];
default: _1_ = a;
endcase
endfunction
assign out = _1_(32'hxxxxxxxx, in_bus, {_0_, sel});
assign _0_ = ~(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) sel;
assign \input_array[0] = in_bus[63:32];
assign \input_array[1] = in_bus[31:0];
endmodule
| 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=4 (
in_bus,
sel,
out
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [127:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[0] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[1] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[2] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[3] ;
(* src = "../core/common/multiplexer.sv:14.45-14.48" *)
output [31:0] out;
(* src = "../core/common/multiplexer.sv:13.45-13.48" *)
input [1:0] sel;
function [31:0] _4_;
input [31:0] a;
input [127:0] b;
input [3:0] s;
(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) (* parallel_case *)
casez (s)
4'b???1: _4_ = b[31:0];
4'b??1?: _4_ = b[63:32];
4'b?1??: _4_ = b[95:64];
4'b1???: _4_ = b[127:96];
default: _4_ = a;
endcase
endfunction
assign out = _4_(32'hxxxxxxxx, in_bus, {_3_, _2_, _1_, _0_});
assign _0_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 2'h3;
assign _1_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 2'h2;
assign _2_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 2'h1;
assign _3_ = !(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) sel;
assign \input_array[0] = in_bus[127:96];
assign \input_array[1] = in_bus[95:64];
assign \input_array[2] = in_bus[63:32];
assign \input_array[3] = in_bus[31:0];
endmodule
| 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=8 (
in_bus,
sel,
out
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [255:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[0] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[1] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[2] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[3] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[4] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[5] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[6] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[7] ;
(* src = "../core/common/multiplexer.sv:14.45-14.48" *)
output [31:0] out;
(* src = "../core/common/multiplexer.sv:13.45-13.48" *)
input [2:0] sel;
function [31:0] _08_;
input [31:0] a;
input [255:0] b;
input [7:0] s;
(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) (* parallel_case *)
casez (s)
8'b???????1: _08_ = b[31:0];
8'b??????1?: _08_ = b[63:32];
8'b?????1??: _08_ = b[95:64];
8'b????1???: _08_ = b[127:96];
8'b???1????: _08_ = b[159:128];
8'b??1?????: _08_ = b[191:160];
8'b?1??????: _08_ = b[223:192];
8'b1???????: _08_ = b[255:224];
default: _08_ = a;
endcase
endfunction
assign out = _08_(32'hxxxxxxxx, in_bus, {_07_, _06_, _05_, _04_, _03_, _02_, _01_, _00_});
assign _00_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h7;
assign _01_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h6;
assign _02_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h5;
assign _03_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h4;
assign _04_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h3;
assign _05_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h2;
assign _06_ = sel == (* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) 3'h1;
assign _07_ = !(* full_case = 32'd1 *) (* src = "../core/common/multiplexer.sv:0.0-0.0" *) sel;
assign \input_array[0] = in_bus[255:224];
assign \input_array[1] = in_bus[223:192];
assign \input_array[2] = in_bus[191:160];
assign \input_array[3] = in_bus[159:128];
assign \input_array[4] = in_bus[127:96];
assign \input_array[5] = in_bus[95:64];
assign \input_array[6] = in_bus[63:32];
assign \input_array[7] = in_bus[31:0];
endmodule
| 6.780879 |
module control_transfer (
result_equal_zero,
inst_funct3,
take_branch
);
wire _00_;
wire _01_;
(* src = "../core/common/control_transfer.sv:17.36-17.54" *)
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
(* src = "../core/common/control_transfer.sv:11.18-11.29" *)
input [2:0] inst_funct3;
(* src = "../core/common/control_transfer.sv:10.12-10.29" *)
input result_equal_zero;
(* src = "../core/common/control_transfer.sv:12.18-12.29" *)
output take_branch;
assign _00_ = |{_07_, _05_, _03_};
assign _01_ = |{_08_, _06_, _04_};
assign _02_ = !(* src = "../core/common/control_transfer.sv:17.36-17.54" *) result_equal_zero;
function [0:0] _12_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *)
(* parallel_case *)
casez (s)
2'b?1: _12_ = b[0:0];
2'b1?: _12_ = b[1:1];
default: _12_ = a;
endcase
endfunction
assign take_branch = _12_(1'hx, {_02_, result_equal_zero}, {_01_, _00_});
assign _03_ = inst_funct3 == (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) 3'h7;
assign _04_ = inst_funct3 == (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) 3'h6;
assign _05_ = inst_funct3 == (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) 3'h5;
assign _06_ = inst_funct3 == (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) 3'h4;
assign _07_ = inst_funct3 == (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) 3'h1;
assign _08_ = ! (* full_case = 32'd1 *) (* src = "../core/common/control_transfer.sv:0.0-0.0|../core/common/control_transfer.sv:16.9-24.16" *) inst_funct3;
endmodule
| 6.898599 |
module \$paramod\multiplexer2\WIDTH=32 (
in0,
in1,
sel,
out
);
(* src = "../core/common/multiplexer2.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer2.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer2.sv:15.24-15.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer2.sv:14.24-14.27" *)
input sel;
(* src = "../core/common/multiplexer2.sv:21.7-25.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=2 multiplexer (
.in_bus({in0, in1}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module \$paramod\multiplexer4\WIDTH=32 (
in0,
in1,
in2,
in3,
sel,
out
);
(* src = "../core/common/multiplexer4.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer4.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer4.sv:14.24-14.27" *)
input [31:0] in2;
(* src = "../core/common/multiplexer4.sv:15.24-15.27" *)
input [31:0] in3;
(* src = "../core/common/multiplexer4.sv:17.24-17.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer4.sv:16.24-16.27" *)
input [1:0] sel;
(* src = "../core/common/multiplexer4.sv:23.7-27.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=4 multiplexer (
.in_bus({in0, in1, in2, in3}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module \$paramod\multiplexer8\WIDTH=32 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
(* src = "../core/common/multiplexer8.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer8.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer8.sv:14.24-14.27" *)
input [31:0] in2;
(* src = "../core/common/multiplexer8.sv:15.24-15.27" *)
input [31:0] in3;
(* src = "../core/common/multiplexer8.sv:16.24-16.27" *)
input [31:0] in4;
(* src = "../core/common/multiplexer8.sv:17.24-17.27" *)
input [31:0] in5;
(* src = "../core/common/multiplexer8.sv:18.24-18.27" *)
input [31:0] in6;
(* src = "../core/common/multiplexer8.sv:19.24-19.27" *)
input [31:0] in7;
(* src = "../core/common/multiplexer8.sv:21.24-21.27" *)
output [31:0] out;
(* src = "../core/common/multiplexer8.sv:20.24-20.27" *)
input [2:0] sel;
(* src = "../core/common/multiplexer8.sv:27.7-31.6" *)
\$paramod\multiplexer\WIDTH=32\CHANNELS=8 multiplexer (
.in_bus({in0, in1, in2, in3, in4, in5, in6, in7}),
.out(out),
.sel(sel)
);
endmodule
| 6.780879 |
module SYN_RESET (
input clk,
input rst_n,
input in,
output reg out
);
always @(posedge clk)
if (rst_n == 1'b0) out <= 1'b0;
else out <= in;
endmodule
| 7.127467 |
module syn_rst (
input wire clock,
input wire rstn, //async_negedge_active_reset
output wire syn_rstn
);
reg rst_nr1, rst_nr2;
always @(posedge clock or negedge rstn) begin
if (!rstn) begin
rst_nr1 <= 1'b0;
rst_nr2 <= 1'b0; //异步复位
end else begin
rst_nr1 <= 1'b1;
rst_nr2 <= rst_nr1; //同步释放
end
end
assign syn_rstn = rst_nr2; //新的系统复位信号rst_n
endmodule
| 7.991093 |
module_name>
-- Author : mammenx
-- Associated modules:
-- Function :
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- $Header$
-- $Log$
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module <module_name> (
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
//----------------------- Internal Wire Declarations ----------------------
//----------------------- FSM Parameters --------------------------------------
//only for FSM state vector representation
parameter [?:0] // synopsys enum fsm_pstate
IDLE = ,
//----------------------- FSM Register Declarations ------------------
reg [?:0] // synopsys enum fsm_pstate
fsm_pstate, next_state;
//----------------------- FSM String Declarations ------------------
//synthesis translate_off
reg [8*?:0] state_name;//"state name" is user defined
//synthesis translate_on
//----------------------- FSM Debugging Logic Declarations ------------------
//synthesis translate_off
always @ (fsm_pstate)
begin
case (fsm_pstate)
<IDLE> : state_name = "IDLE";
<state2> : state_name = "state2";
.
.
.
<default> : state_name = "default";
endcase
end
//synthesis translate_on
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
//code should be <=200 lines
/* comments for assign statements
*/
//assign statements
/* comments for combinatory logic
Asynchronous part of FSM
*/
/* comments for sequential logic
*/
//<sequential logic>;
endmodule
| 9.021353 |
module syn_XOR (
input IN,
output OUT,
input TX_CLK,
input RX_CLK,
input RST_N
);
wire Y;
wire a;
reg P;
reg Q;
always @(posedge TX_CLK or negedge RST_N) begin
if (!RST_N) P <= 0;
else P <= a;
end
always @(posedge RX_CLK or negedge RST_N) begin
if (!RST_N) Q <= 0;
else Q <= Y;
end
xor g2 (a, IN, P);
synchronizer x1 (
.D(P),
.Q(Y),
.clk(RX_CLK),
.rst_n(RST_N)
);
xor g1 (OUT, Q, Y);
endmodule
| 6.563798 |
module SyrupMemory1P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR,
input [ DATA_WIDTH-1:0] D,
input WE,
output [ DATA_WIDTH-1:0] Q,
input RE,
input [DATA_WIDTH/8-1:0] BE
);
endmodule
| 7.576154 |
module SyrupMemory2P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DATA_WIDTH-1:0] D0,
input WE0,
output [ DATA_WIDTH-1:0] Q0,
input RE0,
input [DATA_WIDTH/8-1:0] BE0,
input [ ADDR_WIDTH-1:0] ADDR1,
input [ DATA_WIDTH-1:0] D1,
input WE1,
output [ DATA_WIDTH-1:0] Q1,
input RE1,
input [DATA_WIDTH/8-1:0] BE1
);
endmodule
| 7.588846 |
module SyrupMemory3P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DATA_WIDTH-1:0] D0,
input WE0,
output [ DATA_WIDTH-1:0] Q0,
input RE0,
input [DATA_WIDTH/8-1:0] BE0,
input [ ADDR_WIDTH-1:0] ADDR1,
input [ DATA_WIDTH-1:0] D1,
input WE1,
output [ DATA_WIDTH-1:0] Q1,
input RE1,
input [DATA_WIDTH/8-1:0] BE1,
input [ ADDR_WIDTH-1:0] ADDR2,
input [ DATA_WIDTH-1:0] D2,
input WE2,
output [ DATA_WIDTH-1:0] Q2,
input RE2,
input [DATA_WIDTH/8-1:0] BE2
);
endmodule
| 7.531916 |
module SyrupMemory4P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DATA_WIDTH-1:0] D0,
input WE0,
output [ DATA_WIDTH-1:0] Q0,
input RE0,
input [DATA_WIDTH/8-1:0] BE0,
input [ ADDR_WIDTH-1:0] ADDR1,
input [ DATA_WIDTH-1:0] D1,
input WE1,
output [ DATA_WIDTH-1:0] Q1,
input RE1,
input [DATA_WIDTH/8-1:0] BE1,
input [ ADDR_WIDTH-1:0] ADDR2,
input [ DATA_WIDTH-1:0] D2,
input WE2,
output [ DATA_WIDTH-1:0] Q2,
input RE2,
input [DATA_WIDTH/8-1:0] BE2,
input [ ADDR_WIDTH-1:0] ADDR3,
input [ DATA_WIDTH-1:0] D3,
input WE3,
output [ DATA_WIDTH-1:0] Q3,
input RE3,
input [DATA_WIDTH/8-1:0] BE3
);
endmodule
| 7.809143 |
module SyrupMemory5P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DATA_WIDTH-1:0] D0,
input WE0,
output [ DATA_WIDTH-1:0] Q0,
input RE0,
input [DATA_WIDTH/8-1:0] BE0,
input [ ADDR_WIDTH-1:0] ADDR1,
input [ DATA_WIDTH-1:0] D1,
input WE1,
output [ DATA_WIDTH-1:0] Q1,
input RE1,
input [DATA_WIDTH/8-1:0] BE1,
input [ ADDR_WIDTH-1:0] ADDR2,
input [ DATA_WIDTH-1:0] D2,
input WE2,
output [ DATA_WIDTH-1:0] Q2,
input RE2,
input [DATA_WIDTH/8-1:0] BE2,
input [ ADDR_WIDTH-1:0] ADDR3,
input [ DATA_WIDTH-1:0] D3,
input WE3,
output [ DATA_WIDTH-1:0] Q3,
input RE3,
input [DATA_WIDTH/8-1:0] BE3,
input [ ADDR_WIDTH-1:0] ADDR4,
input [ DATA_WIDTH-1:0] D4,
input WE4,
output [ DATA_WIDTH-1:0] Q4,
input RE4,
input [DATA_WIDTH/8-1:0] BE4
);
endmodule
| 7.428162 |
module SyrupOutChannel #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input CLK,
input [DATA_WIDTH-1:0] D,
input WE
);
endmodule
| 8.06564 |
module SyrupInChannel #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input CLK,
output [DATA_WIDTH-1:0] Q,
input RE
);
endmodule
| 6.556349 |
module sys64b_reg (
input wire clk,
input wire rst,
//д˿
input wire we,
input wire [`RegBus64] idt_i,
input wire [`RegBus64] gdt_i,
input wire [`RegBus64] ldt_i,
input wire [`RegBus64] tr_i,
//˿1
output reg [`RegBus64] idt_o,
output reg [`RegBus64] gdt_o,
output reg [`RegBus64] ldt_o,
output reg [`RegBus64] tr_o
);
always @(posedge clk) begin
if (rst == `RstEnable) begin
idt_o <= `ZeroDWord;
gdt_o <= `ZeroDWord;
ldt_o <= `ZeroDWord;
tr_o <= `ZeroDWord;
end else if ((we == `WriteEnable)) begin
idt_o <= idt_i;
gdt_o <= gdt_i;
ldt_o <= ldt_i;
tr_o <= tr_i;
end
end
endmodule
| 7.032715 |
module sysace_top #(
parameter mpulba_top = 28'd65536 - 28'd256
) (
input CLK,
input RST,
output reg [27:0] mpulba,
output [ 7:0] nsectors,
output sysace_start,
input sysace_busy,
input [15:0] sysace_read_data,
input sysace_read_avail,
output reg wr_en,
output reg [127:0] dout,
input fifo_full,
input start,
output busy
);
`define SW 2
localparam s_idle = `SW'd0;
localparam s_start = `SW'd1;
localparam s_wait = `SW'd2;
localparam s_incr = `SW'd3;
reg [`SW-1:0] state;
`undef SW
localparam counter_top = 3'd7;
reg [ 2:0] counter;
wire [15:0] read_data;
assign read_data[7:0] = sysace_read_data[15:8];
assign read_data[15:8] = sysace_read_data[7:0];
assign nsectors = 8'h0;
assign sysace_start = state == s_start;
assign busy = state != s_idle;
always @(posedge CLK or negedge RST)
if (!RST) begin
state <= s_idle;
end else begin
case (state)
s_idle: if (start) state <= s_start;
s_start: state <= s_wait;
s_wait:
if (!sysace_busy) begin
if (mpulba == mpulba_top) state <= s_idle;
else state <= s_incr;
end
s_incr: state <= s_start;
default: ;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
mpulba <= 28'd0;
end else begin
case (state)
s_incr:
if (mpulba == mpulba_top) mpulba <= 28'd0;
else mpulba <= mpulba + 28'd256;
default: ;
endcase
end
always @(posedge CLK) begin
if (sysace_read_avail) dout <= {dout[111:0], read_data};
end
always @(posedge CLK or negedge RST)
if (!RST) begin
counter <= 3'd0;
end else begin
if (sysace_read_avail) counter <= counter + 3'd1;
end
always @(posedge CLK or negedge RST)
if (!RST) begin
wr_en <= 1'b0;
end else begin
if (counter == counter_top && sysace_read_avail) wr_en <= 1'b1;
else wr_en <= 1'b0;
end
endmodule
| 8.299039 |
module sysArr2x2 (
input clk,
input active,
input [15:0] datain, // 2 datain inputs
input [15:0] win, // 2 weight inputs
input [31:0] sumin, // 2 sumin inputs
input [1:0] wwrite, // 2 write enable inputs
output wire [15:0] maccout1, // 2 maccout outputs
output wire [15:0] maccout2,
output wire [7:0] wout1, // 2 weight outputs
output wire [7:0] wout2,
output wire wwriteout1, // 2 weight write outputs
output wire wwriteout2,
output wire activeout1, // 2 active outputs
output wire activeout2,
output wire [7:0] dataout1, // 2 dataout outputs
output wire [7:0] dataout2
);
// Interconnects
wire [15:0] macc_topLeft, macc_topRight;
wire activeOutTopLeft, activeOutTopRight, activeOutBotLeft, activeOutBotRight;
wire [7:0] dataoutTopLeft, dataoutBotLeft, dataoutTopRight, dataoutBotRight;
wire [7:0] woutTopLeft, woutTopRight;
wire wwriteoutTopLeft, wwriteoutTopRight;
wire [15:0] maccoutBotLeft, maccoutBotRight;
wire [7:0] woutBotLeft, woutBotRight;
wire wwriteoutBotLeft, wwriteoutBotRight;
assign maccout1 = maccoutBotLeft;
assign maccout2 = maccoutBotRight;
assign wout1 = woutBotLeft;
assign wout2 = woutBotRight;
assign wwriteout1 = wwriteoutBotLeft;
assign wwriteout2 = wwriteoutBotRight;
assign activeout1 = activeOutBotLeft;
assign activeout2 = activeOutBotRight;
assign dataout1 = dataoutTopRight;
assign dataout2 = dataoutBotRight;
pe topLeft (
.clk (clk), // done
.active (active),
.datain (datain[7:0]),
.win (win[7:0]),
.sumin (sumin[15:0]),
.wwrite (wwrite[0]),
.maccout (macc_topLeft),
.dataout (dataoutTopLeft),
.wout (woutTopLeft),
.wwriteout(wwriteoutTopLeft),
.activeout(activeOutTopLeft)
);
pe topRight (
.clk (clk), // done
.active (activeOutTopLeft),
.datain (dataoutTopLeft),
.win (win[15:8]),
.sumin (sumin[31:16]),
.wwrite (wwrite[1]),
.maccout (macc_topRight),
.dataout (dataoutTopRight),
.wout (woutTopRight),
.wwriteout(wwriteoutTopRight),
.activeout(activeOutTopRight)
);
pe botLeft (
.clk (clk), // done
.active (activeOutTopLeft),
.datain (datain[15:8]),
.win (woutTopLeft),
.sumin (macc_topLeft),
.wwrite (wwriteoutTopLeft),
.maccout (maccoutBotLeft),
.dataout (dataoutBotLeft),
.wout (woutBotLeft),
.wwriteout(wwriteoutBotLeft),
.activeout(activeOutBotLeft)
);
pe botRight (
.clk (clk), // done
.active (activeOutBotLeft & activeOutTopRight),
.datain (dataoutBotLeft),
.win (woutTopRight),
.sumin (macc_topRight),
.wwrite (wwriteoutTopRight),
.maccout (maccoutBotRight),
.dataout (dataoutBotRight),
.wout (woutBotRight),
.wwriteout(wwriteoutBotRight),
.activeout(activeOutBotRight)
);
endmodule
| 7.464933 |
module sysArrRow (
clk,
active,
datain,
win,
sumin,
wwrite,
maccout,
wout,
wwriteout,
activeout,
dataout
);
parameter row_width = 2;
localparam weight_width = 8 * row_width; // Number of weight bits needed
localparam sum_width = 16 * row_width; // Number of sum bits needed
input clk;
input active;
input signed [7:0] datain; // For single row, we only need one data in.
input [weight_width-1:0] win; // 8 bits for each PE. Left most PE has LSB
input [sum_width-1:0] sumin; // 16 bits for each PE. Left most PE has LSB
input [row_width-1:0] wwrite; // 1 bit for each PE. Left most PE has LSB
// Outputs to the next row in array (bottom)
output wire [sum_width-1:0] maccout;
output wire [weight_width-1:0] wout;
output wire [row_width-1:0] wwriteout;
output wire [row_width-1:0] activeout;
// Outputs to the right side of the array
output signed [7:0] dataout;
// Interconnects (PE - PE Connections)
wire [row_width-1:0] activeout_inter;
wire [(weight_width-8)-1:0] dataout_inter;
assign activeout = activeout_inter;
genvar i;
generate
for (i = 0; i < row_width; i = i + 1) begin : genblk1
if (i == 0) begin
// The first PE in the row has different inputs
pe first_pe_inst (
.clk(clk),
.active(active),
.datain(datain),
.win(win[7:0]),
.sumin(sumin[15:0]),
.wwrite(wwrite[0]),
.maccout(maccout[15:0]),
.dataout(dataout_inter[7:0]),
.wout(wout[7:0]),
.wwriteout(wwriteout[0]),
.activeout(activeout_inter[i])
);
end // if (i == 0)
else if (i == row_width - 1) begin
// The last PE in the row has different outputs
pe last_pe_inst (
.clk(clk),
.active(activeout_inter[i-1]),
.datain(dataout_inter[(i*8)-1:(i-1)*8]),
.win(win[((i+1)*8)-1:(i*8)]),
.sumin(sumin[((i+1)*16)-1:(i*16)]),
.wwrite(wwrite[row_width-1]),
.maccout(maccout[((i+1)*16)-1:(i*16)]),
.dataout(dataout),
.wout(wout[((i+1)*8)-1:(i*8)]),
.wwriteout(wwriteout[row_width-1]),
.activeout(activeout_inter[i])
);
end // else if (i == row_width - 1)
else begin
pe pe_inst (
.clk(clk),
.active(activeout_inter[i-1]),
.datain(dataout_inter[(i*8)-1:(i-1)*8]),
.win(win[((i+1)*8)-1:(i*8)]),
.sumin(sumin[((i+1)*16)-1:(i*16)]),
.wwrite(wwrite[i]),
.maccout(maccout[((i+1)*16)-1:(i*16)]),
.dataout(dataout_inter[((i+1)*8)-1:(i*8)]),
.wout(wout[((i+1)*8)-1:(i*8)]),
.wwriteout(wwriteout[i]),
.activeout(activeout_inter[i])
);
end // else
end // for (i = 0; i < row_width; i = i + 1)
endgenerate
endmodule
| 7.472352 |
module SysClockGen (
CLKIN_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT,
LOCKED_OUT
);
input CLKIN_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK2X_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (
.I(CLKFX_BUF),
.O(CLKFX_OUT)
);
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
BUFG CLK2X_BUFG_INST (
.I(CLK2X_BUF),
.O(CLK2X_OUT)
);
DCM_SP #(
.CLK_FEEDBACK("1X"),
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(4),
.CLKFX_MULTIPLY(2),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_SP_INST (
.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS()
);
endmodule
| 6.602624 |
module SysCodeBlock (
address,
byteena,
clock,
data,
wren,
q);
input [10:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../system_code.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SysC",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
| 6.538502 |
module syscon (
output logic clk_o,
output logic rst_o
);
logic clk, rst;
initial begin
clk <= 1'b0;
rst <= 1'b1;
#20 rst <= 1'b0;
end
//------------------------------------------------------------------------------
// main clock generation
//------------------------------------------------------------------------------
always #5 clk = ~clk;
//------------------------------------------------------------------------------
assign clk_o = clk;
assign rst_o = rst;
endmodule
| 7.340167 |
module syscon_top (
output reg clk_pin = 0,
output reg rst_pin = 1
);
wire clk;
wire rst;
always @(posedge clk) begin
clk_pin <= !clk_pin;
rst_pin <= rst;
end
syscon syscon_inst0 (
.clk(clk),
.rst(rst)
);
// Unit test
`ifdef SIMULATION
testAnythingProtocol #("build", "report.tap") tap ();
reg [63 * 8:0] test_message;
integer cycleCounter = 0;
always @(posedge clk) begin
cycleCounter = cycleCounter + 1;
// reset pin level: 1 1 1 0 0 0 0 0...
$sformat(test_message, "Reset Pin Level: %d", rst_pin);
if (cycleCounter <= 3) begin
tap.assert(rst_pin == 1, test_message);
end else begin
tap.assert(rst_pin == 0, test_message);
end
// clock pin level: 1 0 1 0 1 0 1 0...
$sformat(test_message, "Clock Pin Level: %d", clk_pin);
if (cycleCounter % 2 == 0) begin
tap.assert(clk_pin == 1, test_message);
end else begin
tap.assert(clk_pin == 0, test_message);
end
// finish after 10 cycles
if (cycleCounter >= 10) begin
tap.finish;
end
end
`endif
endmodule
| 7.986784 |
module syscon_wrapper (
input wire i_clk,
input wire i_rst,
input wire gpio_irq,
input wire ptc_irq,
output wire o_timer_irq,
// output wire o_sw_irq3,
// output wire o_sw_irq4,
input wire i_ram_init_done,
input wire i_ram_init_error,
output wire [31:0] o_nmi_vec,
output wire o_nmi_int,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [ 3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire [31:0] o_wb_rdt,
output wire o_wb_ack,
output wire [7 : 0] AN,
output wire [6 : 0] Digits_Bits
);
swervolf_syscon syscon (
.i_clk (i_clk),
.i_rst (i_rst),
.gpio_irq (gpio_irq),
.ptc_irq (ptc_irq),
.o_timer_irq (o_timer_irq),
.o_sw_irq3 (),
.o_sw_irq4 (),
.i_ram_init_done (i_ram_init_done),
.i_ram_init_error(i_ram_init_error),
.o_nmi_vec (o_nmi_vec),
.o_nmi_int (o_nmi_int),
.i_wb_adr (i_wb_adr[5:0]),
.i_wb_dat (i_wb_dat),
.i_wb_sel (i_wb_sel),
.i_wb_we (i_wb_we),
.i_wb_cyc (i_wb_cyc),
.i_wb_stb (i_wb_stb),
.o_wb_rdt (o_wb_rdt),
.o_wb_ack (o_wb_ack),
.AN (AN),
.Digits_Bits (Digits_Bits)
);
endmodule
| 6.905671 |
module sysctl_icap (
input sys_clk,
input sys_rst,
output reg ready,
input we,
input [15:0] d,
input ce,
input write
);
reg icap_clk;
reg icap_clk_r;
reg d_ce;
reg [15:0] d_r;
reg ce_r;
reg write_r;
always @(posedge sys_clk) begin
if (d_ce) begin
d_r[0] <= d[7];
d_r[1] <= d[6];
d_r[2] <= d[5];
d_r[3] <= d[4];
d_r[4] <= d[3];
d_r[5] <= d[2];
d_r[6] <= d[1];
d_r[7] <= d[0];
d_r[8] <= d[15];
d_r[9] <= d[14];
d_r[10] <= d[13];
d_r[11] <= d[12];
d_r[12] <= d[11];
d_r[13] <= d[10];
d_r[14] <= d[9];
d_r[15] <= d[8];
ce_r <= ce;
write_r <= write;
end
icap_clk_r <= icap_clk;
end
ICAP_SPARTAN6 icap (
.BUSY(),
.O(),
.CE(ce_r),
.CLK(icap_clk_r),
.I(d_r),
.WRITE(write_r)
);
parameter IDLE = 3'd0;
parameter C1 = 3'd1;
parameter C2 = 3'd2;
parameter C3 = 3'd3;
parameter C4 = 3'd4;
parameter C5 = 3'd5;
reg [2:0] state;
reg [2:0] next_state;
initial state = IDLE;
always @(posedge sys_clk) state <= next_state;
always @(*) begin
ready = 1'b0;
icap_clk = 1'b0;
d_ce = 1'b0;
next_state = state;
case (state)
IDLE: begin
ready = 1'b1;
if (we & ~sys_rst) begin
d_ce = 1'b1;
next_state = C1;
end
end
C1: begin
next_state = C2;
end
C2: begin
icap_clk = 1'b1;
next_state = C3;
end
C3: begin
icap_clk = 1'b1;
next_state = C4;
end
C4: begin
icap_clk = 1'b1;
next_state = C5;
end
C5: begin
next_state = IDLE;
end
endcase
end
endmodule
| 8.041401 |
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
parameter PWRGOOD = 8'h00,
parameter CLK_OUT = 8'h04,
parameter TRAP_OUT = 8'h08,
parameter IRQ_SRC = 8'h0c
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_dat_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output [31:0] wb_dat_o,
output wb_ack_o,
input usr1_vcc_pwrgood,
input usr2_vcc_pwrgood,
input usr1_vdd_pwrgood,
input usr2_vdd_pwrgood,
output clk1_output_dest,
output clk2_output_dest,
output trap_output_dest,
output irq_7_inputsrc,
output irq_8_inputsrc
);
wire resetn;
wire valid;
wire ready;
wire [3:0] iomem_we;
assign resetn = ~wb_rst_i;
assign valid = wb_stb_i && wb_cyc_i;
assign iomem_we = wb_sel_i & {4{wb_we_i}};
assign wb_ack_o = ready;
sysctrl #(
.BASE_ADR(BASE_ADR),
.PWRGOOD (PWRGOOD),
.CLK_OUT (CLK_OUT),
.TRAP_OUT(TRAP_OUT),
.IRQ_SRC (IRQ_SRC)
) sysctrl (
.clk(wb_clk_i),
.resetn(resetn),
.iomem_addr (wb_adr_i),
.iomem_valid(valid),
.iomem_wstrb(iomem_we),
.iomem_wdata(wb_dat_i),
.iomem_rdata(wb_dat_o),
.iomem_ready(ready),
.usr1_vcc_pwrgood(usr1_vcc_pwrgood),
.usr2_vcc_pwrgood(usr2_vcc_pwrgood),
.usr1_vdd_pwrgood(usr1_vdd_pwrgood),
.usr2_vdd_pwrgood(usr2_vdd_pwrgood),
.clk1_output_dest(clk1_output_dest),
.clk2_output_dest(clk2_output_dest),
.trap_output_dest(trap_output_dest),
.irq_8_inputsrc (irq_8_inputsrc),
.irq_7_inputsrc (irq_7_inputsrc)
);
endmodule
| 7.004691 |
module sysctrl #(
parameter BASE_ADR = 32'h2300_0000,
parameter PWRGOOD = 8'h00,
parameter CLK_OUT = 8'h04,
parameter TRAP_OUT = 8'h08,
parameter IRQ_SRC = 8'h0c
) (
input clk,
input resetn,
input [31:0] iomem_addr,
input iomem_valid,
input [3:0] iomem_wstrb,
input [31:0] iomem_wdata,
output reg [31:0] iomem_rdata,
output reg iomem_ready,
input usr1_vcc_pwrgood,
input usr2_vcc_pwrgood,
input usr1_vdd_pwrgood,
input usr2_vdd_pwrgood,
output clk1_output_dest,
output clk2_output_dest,
output trap_output_dest,
output irq_7_inputsrc,
output irq_8_inputsrc
);
reg clk1_output_dest;
reg clk2_output_dest;
reg trap_output_dest;
reg irq_7_inputsrc;
reg irq_8_inputsrc;
wire usr1_vcc_pwrgood;
wire usr2_vcc_pwrgood;
wire usr1_vdd_pwrgood;
wire usr2_vdd_pwrgood;
wire pwrgood_sel;
wire clk_out_sel;
wire trap_out_sel;
wire irq_sel;
assign pwrgood_sel = (iomem_addr[7:0] == PWRGOOD);
assign clk_out_sel = (iomem_addr[7:0] == CLK_OUT);
assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
assign irq_sel = (iomem_addr[7:0] == IRQ_SRC);
always @(posedge clk) begin
if (!resetn) begin
clk1_output_dest <= 0;
clk2_output_dest <= 0;
trap_output_dest <= 0;
irq_7_inputsrc <= 0;
irq_8_inputsrc <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
iomem_ready <= 1'b1;
if (pwrgood_sel) begin
iomem_rdata <= {
28'd0, usr2_vdd_pwrgood, usr1_vdd_pwrgood, usr2_vcc_pwrgood, usr1_vcc_pwrgood
};
// These are read-only bits; no write behavior on wstrb.
end else if (clk_out_sel) begin
iomem_rdata <= {30'd0, clk2_output_dest, clk1_output_dest};
if (iomem_wstrb[0]) begin
clk1_output_dest <= iomem_wdata[0];
clk2_output_dest <= iomem_wdata[1];
end
end else if (trap_out_sel) begin
iomem_rdata <= {31'd0, trap_output_dest};
if (iomem_wstrb[0]) trap_output_dest <= iomem_wdata[0];
end else if (irq_sel) begin
iomem_rdata <= {30'd0, irq_8_inputsrc, irq_7_inputsrc};
if (iomem_wstrb[0]) begin
irq_7_inputsrc <= iomem_wdata[0];
irq_8_inputsrc <= iomem_wdata[1];
end
end
end
end
end
endmodule
| 6.65308 |
module sysctrl_tb;
reg clock;
reg power1;
reg RSTB;
wire gpio;
wire [15:0] checkbits;
wire [7:0] spivalue;
wire [37:0] mprj_io;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire SDO;
integer ccount;
integer ucount;
assign checkbits = mprj_io[31:16];
assign spivalue = mprj_io[15:8];
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #10 clock <= (clock === 1'b0);
// User clock monitoring
always @(posedge mprj_io[15]) begin
ucount = ucount + 1;
end
// Core clock monitoring
always @(posedge mprj_io[14]) begin
ccount = ccount + 1;
end
initial begin
clock = 0;
end
initial begin
$dumpfile("sysctrl.vcd");
$dumpvars(0, sysctrl_tb);
repeat (25) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m", 27);
$display("Monitor: Timeout, Test Sysctrl (RTL) Failed");
$display("%c[0m", 27);
$finish;
end
// Monitor
initial begin
wait (checkbits == 16'hA040);
$display("Monitor: Test 1 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait (checkbits == 16'hA041);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 0 || ccount != 0) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait (checkbits == 16'hA042);
$display("Monitor: Test 1 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait (checkbits == 16'hA043);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 11 || ccount != 0) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait (checkbits == 16'hA044);
$display("Monitor: Test 2 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait (checkbits == 16'hA045);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 0 || ccount != 11) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait (checkbits == 16'hA090);
$display("Monitor: Test Sysctrl (RTL) Passed");
$finish;
end
initial begin
RSTB <= 1'b0;
#1000;
RSTB <= 1'b1; // Release reset
#2000;
end
initial begin
power1 <= 1'b0;
#200;
power1 <= 1'b1;
end
always @(checkbits) begin
#1 $display("GPIO state = %b ", checkbits);
end
wire VDD5V0;
wire VSS;
assign VDD5V0 = power1;
assign VSS = 1'b0;
assign mprj_io[3] = 1'b1; // Force CSB high.
caravel uut (
.VDD (VDD5V0),
.VSS (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("sysctrl.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.899735 |
module SYSCTRL_TXFSM #(
parameter DATA_WIDTH = 32
) (
input clk,
RST,
RdData_valid,
OUT_Valid,
input [$clog2(DATA_WIDTH/8) : 0] TX_CNTR,
output reg TX_CNTR_RST,
TX_CNTR_EN,
TX_D_VLD
);
localparam SEND_IDLE = 0, RF_TX_CNTR_EN = 1, ALU_TX_CNTR_EN = 2;
reg [1:0] tx_state;
always @(posedge clk) begin
if (RST) tx_state <= SEND_IDLE;
else
case (tx_state)
SEND_IDLE:
if (RdData_valid) tx_state <= RF_TX_CNTR_EN;
else if (OUT_Valid) tx_state <= ALU_TX_CNTR_EN;
RF_TX_CNTR_EN: if (TX_CNTR == DATA_WIDTH / 8) tx_state <= SEND_IDLE;
ALU_TX_CNTR_EN: if (TX_CNTR == DATA_WIDTH / 4) tx_state <= SEND_IDLE;
endcase
end
always @(*) begin
TX_CNTR_EN = 0 ;
TX_CNTR_RST = 0 ;
TX_D_VLD = 0 ;
case (tx_state)
SEND_IDLE: begin
TX_CNTR_EN = 0;
TX_CNTR_RST = 1;
TX_D_VLD = 0;
end
RF_TX_CNTR_EN: begin
TX_CNTR_EN = 1;
TX_CNTR_RST = 0;
TX_D_VLD = 1;
end
ALU_TX_CNTR_EN: begin
TX_CNTR_EN = 1;
TX_CNTR_RST = 0;
TX_D_VLD = 1;
end
endcase
end
endmodule
| 8.204743 |
module sysid_rom #(
parameter ROM_WIDTH = 32,
parameter ROM_ADDR_BITS = 6,
parameter PATH_TO_FILE = "path_to_mem_init_file"
) (
input clk,
input [ROM_ADDR_BITS-1:0] rom_addr,
output reg [ ROM_WIDTH-1:0] rom_data
);
reg [ROM_WIDTH-1:0] lut_rom[(2**ROM_ADDR_BITS)-1:0];
initial begin
$readmemh(PATH_TO_FILE, lut_rom, 0, (2 ** ROM_ADDR_BITS) - 1);
end
always @(posedge clk) begin
rom_data = lut_rom[rom_addr];
end
endmodule
| 8.593528 |
module sysmem0_ipgen_lscc_ahblmem_arbiter #(
parameter PORT_TYPE_S0 = "R/W",
parameter PORT_TYPE_S1 = "R/W",
parameter ADDR_WIDTH = 32,
parameter RESET_MODE = "async",
parameter ARBITER_EN = 0
) (
// ------------------------------------------------------------------------------
// Input/Output Ports
// ------------------------------------------------------------------------------
input clk_i,
input rst_i,
// ------------------------------------------------------------------------------
// Port S0 Signals
// ------------------------------------------------------------------------------
input [(ADDR_WIDTH - 1):0] addr_s0_i,
input mem_wr_rdn_s0_i,
input mem_req_s0_i,
output mem_wr_rdn_s0_o,
output mem_req_s0_o,
// ------------------------------------------------------------------------------
// Port S1 Signals
// ------------------------------------------------------------------------------
input [(ADDR_WIDTH - 1):0] addr_s1_i,
input mem_wr_rdn_s1_i,
input mem_req_s1_i,
output mem_wr_rdn_s1_o,
output mem_req_s1_o
);
localparam DUAL_WRITE = (((PORT_TYPE_S0 == "R/W") && ((PORT_TYPE_S1 == "R/W") || (PORT_TYPE_S1 == "W/O"))) ? ARBITER_EN : (((PORT_TYPE_S0 == "W/O") && ((PORT_TYPE_S1 == "R/W") || (PORT_TYPE_S1 == "W/O"))) ? ARBITER_EN : 0)) ;
// -----------------------------------------------------------------------------
// Generate Blocks
// -----------------------------------------------------------------------------
generate
if ((DUAL_WRITE == 1)) begin : dual_write
reg mem_wr_rdn_s0_r;
reg mem_wr_rdn_s1_r;
reg mem_req_s1_r;
reg mem_req_s0_r;
assign mem_wr_rdn_s0_o = mem_wr_rdn_s0_r;
assign mem_wr_rdn_s1_o = mem_wr_rdn_s1_r;
assign mem_req_s0_o = mem_req_s0_r;
assign mem_req_s1_o = mem_req_s1_r;
always @(*) begin
if ((((((addr_s0_i == addr_s1_i) && (mem_wr_rdn_s0_i == 1'b1)) && (mem_wr_rdn_s1_i == 1'b1)) && (mem_req_s0_i == 1'b1)) && (mem_req_s1_i == 1'b1)))
begin
mem_wr_rdn_s0_r = 1'b1;
mem_wr_rdn_s1_r = 1'b0;
mem_req_s0_r = 1'b1;
mem_req_s1_r = 1'b0;
end else begin
mem_wr_rdn_s0_r = mem_wr_rdn_s0_i;
mem_wr_rdn_s1_r = mem_wr_rdn_s1_i;
mem_req_s0_r = mem_req_s0_i;
mem_req_s1_r = mem_req_s1_i;
end
end
end else begin : single_write
assign mem_wr_rdn_s0_o = ((PORT_TYPE_S0 == "R/O") ? 1'b0 : mem_wr_rdn_s0_i);
assign mem_wr_rdn_s1_o = ((PORT_TYPE_S1 == "R/O") ? 1'b0 : mem_wr_rdn_s1_i);
assign mem_req_s0_o = mem_req_s0_i;
assign mem_req_s1_o = mem_req_s1_i;
end
endgenerate
endmodule
| 6.882045 |
module sysmem0_ipgen_lscc_fifo_streamer #(
parameter ADDR_DEPTH = 16384,
parameter ADDR_WIDTH = clog2(ADDR_DEPTH),
parameter FIFO_START = 0,
parameter DATA_WIDTH = 32,
parameter BYTE_WIDTH = (DATA_WIDTH / 8),
parameter MEM_TYPE = "EBR"
) (
input fifo_clk_i,
input fifo_wr_en_i,
input [7:0] fifo_wr_data_i,
input fifo_rst_i,
output reg fifo_full_o,
output [(DATA_WIDTH - 1):0] mem_wdata_o,
output mem_clk_en_o,
output [(ADDR_WIDTH - 1):0] mem_addr_o,
output [(BYTE_WIDTH - 1):0] mem_byte_en_o
);
reg fifo_full_int_r;
reg [ADDR_WIDTH:0] mem_addr_r;
reg [ADDR_WIDTH:0] mem_addr_nxt_c;
reg fifo_full_nxt_c;
reg [(BYTE_WIDTH - 1):0] mem_byte_en_r;
reg [(BYTE_WIDTH - 1):0] mem_byte_en_nxt_c;
assign mem_addr_o = mem_addr_r[(ADDR_WIDTH-1):0];
assign mem_wdata_o = {BYTE_WIDTH{fifo_wr_data_i}};
assign mem_clk_en_o = ((~fifo_full_int_r) & fifo_wr_en_i);
if ((MEM_TYPE == "LRAM")) begin : genblk1
genvar i0;
for (i0 = 0; (i0 < BYTE_WIDTH); i0 = (i0 + 1)) begin : genblk1
assign mem_byte_en_o[i0] = (~mem_byte_en_r[i0]);
end
end else begin : genblk1
assign mem_byte_en_o = mem_byte_en_r;
end
if ((BYTE_WIDTH == 1)) begin : genblk2
always @(*) begin
mem_addr_nxt_c = mem_addr_r;
if (mem_clk_en_o) begin
mem_addr_nxt_c = (mem_addr_r + 1'b1);
end
end
always @(*) begin
mem_byte_en_nxt_c = 1'b1;
end
end else begin : genblk2
always @(*) begin
mem_addr_nxt_c = mem_addr_r;
if ((mem_clk_en_o & mem_byte_en_r[(BYTE_WIDTH-1)])) begin
mem_addr_nxt_c = (mem_addr_r + 1'b1);
end
end
always @(*) begin
mem_byte_en_nxt_c = (mem_clk_en_o ? {mem_byte_en_r[(BYTE_WIDTH - 2):0],
mem_byte_en_r[(BYTE_WIDTH - 1)]} : mem_byte_en_r) ;
end
end
always @(*) begin
fifo_full_nxt_c = (fifo_full_int_r | (fifo_wr_en_i && (mem_addr_nxt_c == ADDR_DEPTH)));
end
always @(posedge fifo_clk_i or negedge fifo_rst_i) begin
if ((~fifo_rst_i)) begin
mem_addr_r <= FIFO_START;
mem_byte_en_r <= 4'h1;
fifo_full_o <= 1'b0;
fifo_full_int_r <= 1'b0;
end else begin
mem_addr_r <= mem_addr_nxt_c;
mem_byte_en_r <= mem_byte_en_nxt_c;
fifo_full_o <= fifo_full_nxt_c;
fifo_full_int_r <= fifo_full_nxt_c;
end
end
//------------------------------------------------------------------------------
// Function Definition
//------------------------------------------------------------------------------
function [31:0] clog2;
input [31:0] value;
reg [31:0] num;
begin
num = (value - 1);
for (clog2 = 0; (num > 0); clog2 = (clog2 + 1)) num = (num >> 1);
end
endfunction
endmodule
| 6.882045 |
module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_out,
output wire rst_out
);
// Signals
wire pll_lock;
wire pll_reset_n;
wire clk_i;
wire rst_i;
reg [3:0] rst_cnt;
// PLL instance
`ifdef SIM
assign clk_i = clk_in;
assign pll_lock = pll_reset_n;
`else
SB_PLL40_PAD #(
.DIVR(4'b0000),
.DIVF(7'b1001111),
.DIVQ(3'b101),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0)
) pll_I (
.PACKAGEPIN(clk_in),
.PLLOUTCORE(),
.PLLOUTGLOBAL(clk_i),
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'h00),
.RESETB(pll_reset_n),
.BYPASS(1'b0),
.LATCHINPUTVALUE(1'b0),
.LOCK(pll_lock),
.SDI(1'b0),
.SDO(),
.SCLK(1'b0)
);
`endif
assign clk_out = clk_i;
// PLL reset generation
assign pll_reset_n = ~rst_in;
// Logic reset generation
always @(posedge clk_i or negedge pll_lock)
if (!pll_lock) rst_cnt <= 4'h8;
else if (rst_cnt[3]) rst_cnt <= rst_cnt + 1;
assign rst_i = rst_cnt[3];
SB_GB rst_gbuf_I (
.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
.GLOBAL_BUFFER_OUTPUT(rst_out)
);
endmodule
| 7.349607 |
module sysmgr_hfosc (
input wire rst_in,
output wire clk_out,
output wire rst_out
);
// Signals
wire clk_i;
reg rst_i;
reg [7:0] rst_cnt = 8'h00;
// 48 MHz source
SB_HFOSC #(
.TRIM_EN ("0b0"),
.CLKHF_DIV("0b00")
) osc_I (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk_i)
);
assign clk_out = clk_i;
// Logic reset generation
// (need a larger delay here because without pll lock delay, BRAMs aren't
// ready in time ...)
always @(posedge clk_i or posedge rst_in)
if (rst_in) rst_cnt <= 8'h00;
else if (rst_i) rst_cnt <= rst_cnt + 1;
always @(posedge clk_i) rst_i <= ~&rst_cnt[7:4];
SB_GB rst_gbuf_I (
.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
.GLOBAL_BUFFER_OUTPUT(rst_out)
);
endmodule
| 8.735074 |
module sysmgr_pll (
input wire clk_in,
input wire rst_in,
output wire clk_24m,
output wire clk_48m,
output wire rst_out
);
// Signals
wire pll_lock;
wire pll_reset_n;
wire clk_1x;
wire clk_2x;
wire rst_i;
reg [3:0] rst_cnt;
// Clock frequency input depends on board
`ifdef BOARD_FOMU_HACKER
`define CLK_IN_FABRIC
`define CLK_IN_48M
`elsif BOARD_FOMU_PVT1
`define CLK_IN_FABRIC
`define CLK_IN_48M
`elsif BOARD_TINYFPGA_BX
`define CLK_IN_FABRIC
`define CLK_IN_16M
`endif
// PLL instance
`ifdef SIM
reg clk_div = 1'b0;
always @(posedge clk_in)
clk_div <= ~clk_div;
assign clk_1x = clk_div;
assign clk_2x = clk_in;
assign pll_lock = pll_reset_n;
initial
rst_cnt <= 4'h8;
`else
`ifdef CLK_IN_FABRIC
SB_PLL40_2F_CORE #(
`else
SB_PLL40_2F_PAD #(
`endif
`ifdef CLK_IN_48M
// clk_in is 48 MHz
.DIVR(4'b0000),
.DIVF(7'b0001111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b100),
`elsif CLK_IN_16M
// clk_in is 16 MHz
.DIVR(4'b0000),
.DIVF(7'b0101111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b001),
`else
// clk_in is 12 MHz
.DIVR(4'b0000),
.DIVF(7'b0111111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b001),
`endif
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT_PORTA("GENCLK"),
.PLLOUT_SELECT_PORTB("GENCLK_HALF"),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0)
) pll_I (
`ifdef CLK_IN_FABRIC
.REFERENCECLK (clk_in),
`else
.PACKAGEPIN (clk_in),
`endif
.PLLOUTCOREA (),
.PLLOUTGLOBALA (clk_2x),
.PLLOUTCOREB (),
.PLLOUTGLOBALB (clk_1x),
.EXTFEEDBACK (1'b0),
.DYNAMICDELAY (8'h00),
.RESETB (pll_reset_n),
.BYPASS (1'b0),
.LATCHINPUTVALUE(1'b0),
.LOCK (pll_lock),
.SDI (1'b0),
.SDO (),
.SCLK (1'b0)
);
`endif
assign clk_24m = clk_1x;
assign clk_48m = clk_2x;
// PLL reset generation
assign pll_reset_n = ~rst_in;
// Logic reset generation
always @(posedge clk_1x or negedge pll_lock)
if (!pll_lock)
rst_cnt <= 4'h8;
else if (rst_cnt[3])
rst_cnt <= rst_cnt + 1;
assign rst_i = rst_cnt[3];
SB_GB rst_gbuf_I (
.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
.GLOBAL_BUFFER_OUTPUT(rst_out)
);
endmodule
| 7.284812 |
module SysMon_exdes (
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
BUSY_OUT, // ADC Busy signal
CHANNEL_OUT, // Channel Selection Outputs
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
EOC_OUT, // End of Conversion Signal
EOS_OUT, // End of Sequence Signal
JTAGBUSY_OUT, // JTAG DRP transaction is in progress signal
JTAGLOCKED_OUT, // DRP port lock request has been made by JTAG
JTAGMODIFIED_OUT, // Indicates JTAG Write to the DRP has occurred
VP_IN, // Dedicated Analog Input Pair
VN_IN
);
input VP_IN;
input VN_IN;
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
output BUSY_OUT;
output [4:0] CHANNEL_OUT;
output [15:0] DO_OUT;
output DRDY_OUT;
output EOC_OUT;
output EOS_OUT;
output JTAGBUSY_OUT;
output JTAGLOCKED_OUT;
output JTAGMODIFIED_OUT;
wire GND_BIT;
wire [2:0] GND_BUS3;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_USER_TEMP_ALARM;
assign GND_BIT = 0;
SysMon sysmon_wiz_inst (
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(DCLK_IN),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.BUSY_OUT(BUSY_OUT),
.CHANNEL_OUT(CHANNEL_OUT[4:0]),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.EOC_OUT(EOC_OUT),
.EOS_OUT(EOS_OUT),
.JTAGBUSY_OUT(JTAGBUSY_OUT),
.JTAGLOCKED_OUT(JTAGLOCKED_OUT),
.JTAGMODIFIED_OUT(JTAGMODIFIED_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
| 8.414254 |
module SysMon_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20 * ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [ 6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [ 2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
wire BUSY_TB;
wire [ 4:0] CHANNEL_TB;
wire EOC_TB;
wire EOS_TB;
wire JTAGBUSY_TB;
wire JTAGLOCKED_TB;
wire JTAGMODIFIED_TB;
// Input clock generation
always begin
DCLK_TB = #(PER1 / 2) ~DCLK_TB;
end
assign DADDR_TB = {2'b00, CHANNEL_TB};
assign DI_TB = 16'b0000000000000000;
assign DWE_TB = 1'b0;
assign DEN_TB = EOC_TB;
// Start of the testbench
initial begin
$display("Single channel avereraging is enabled");
$display("This TB does not verify averaging");
$display("Please increase the simulation duration to see complete waveform");
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
`wait_done;
`wait_eoc;
$display("EOC is asserted");
if (CHANNEL_TB == 0) begin
$display("Monitored Temperature");
end else begin
$display("Temperature is not monitored");
$display("ERROR !!!");
$finish;
end
`wait_drdy;
$display("DRDY is asserted. Valid data is on the DO bus");
$display("Averaging Complete");
$finish;
`wait_eoc;
$display("EOC is asserted.");
if (CHANNEL_TB == 0) begin
$display("Monitored Temperature.");
end else begin
$display("USER TEMP is not monitored.");
$display("ERROR !!!");
$finish;
end
`wait_drdy;
$display("DRDY is asserted. Valid data is on the DO bus");
$display("Averaging Complete");
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
SysMon_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.BUSY_OUT(BUSY_TB),
.CHANNEL_OUT(CHANNEL_TB[4:0]),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.EOC_OUT(EOC_TB),
.EOS_OUT(EOS_TB),
.JTAGBUSY_OUT(JTAGBUSY_TB),
.JTAGLOCKED_OUT(JTAGLOCKED_TB),
.JTAGMODIFIED_OUT(JTAGMODIFIED_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
| 7.424903 |
module SystArr (
input wire clk,
input wire nrst,
input wire ena,
input wire [29:0] T,
input wire [11:0] i_tsrc,
input wire [29:0] R,
input wire [11:0] i_rsrc,
input wire [95:0] D0,
input wire [95:0] D1,
input wire [95:0] D2,
output wire [95:0] D,
output wire [11:0] o_path
);
// T序列 6 -> 5 -> ... -> 1
wire [179:0] T_in;
wire [179:0] T_out;
assign T_in = {T_out[149:0], 30'd0};
// R序列 1 -> 2 -> ... -> 6
wire [179:0] R_in;
wire [179:0] R_out;
assign R_in = {30'd0, R_out[179:30]};
generate
genvar i;
for (i = 0; i < 6; i = i + 1) begin : gen_pe
// PE输入：距离
wire [15:0] _D0;
wire [15:0] _D1;
wire [15:0] _D2;
assign _D0 = D0[95-i*16 : 80-i*16];
assign _D1 = D1[95-i*16 : 80-i*16];
assign _D2 = D2[95-i*16 : 80-i*16];
// PE输入：序列
wire [29:0] _T_pe;
wire [29:0] _R_pe;
wire [ 1:0] _tsrc;
wire [ 1:0] _rsrc;
assign _T_pe = T_in[179-i*30 : 150-i*30];
assign _R_pe = R_in[179-i*30 : 150-i*30];
assign _tsrc = i_tsrc[11-i*2 : 10-i*2];
assign _rsrc = i_rsrc[11-i*2 : 10-i*2];
// PE输出：至相邻PE
wire [29:0] _T;
wire [29:0] _R;
assign T_out[179-i*30 : 150-i*30] = _T;
assign R_out[179-i*30 : 150-i*30] = _R;
// PE输出：结果
wire [15:0] _D;
wire [ 1:0] _path;
assign D[95-i*16 : 80-i*16] = _D;
assign o_path[11-i*2 : 10-i*2] = _path;
// 实例化PE
ProcElem pe (
.clk(clk),
.nrst(nrst),
.ena(ena),
.D0(_D0),
.D1(_D1),
.D2(_D2),
.T_pe(_T_pe),
.T_ext(T),
.i_tsrc(_tsrc),
.R_pe(_R_pe),
.R_ext(R),
.i_rsrc(_rsrc),
.T(_T),
.R(_R),
.D(_D),
.o_path(_path)
);
end
endgenerate
endmodule
| 6.77583 |
module IntXbar (
input auto_int_in_0,
input auto_int_in_1,
input auto_int_in_2,
input auto_int_in_3,
input auto_int_in_4,
input auto_int_in_5,
input auto_int_in_6,
input auto_int_in_7,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_int_out_3,
output auto_int_out_4,
output auto_int_out_5,
output auto_int_out_6,
output auto_int_out_7
);
assign auto_int_out_0 = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_1 = auto_int_in_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_2 = auto_int_in_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_3 = auto_int_in_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_4 = auto_int_in_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_5 = auto_int_in_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_6 = auto_int_in_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_7 = auto_int_in_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.794458 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
output auto_out_2,
output auto_out_3,
output auto_out_4,
output auto_out_5,
output auto_out_6,
output auto_out_7
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire [7:0] chain_io_d; // @[ShiftReg.scala 45:23]
wire [7:0] chain_io_q; // @[ShiftReg.scala 45:23]
wire [3:0] chain_io_d_lo = {
auto_in_sync_3, auto_in_sync_2, auto_in_sync_1, auto_in_sync_0
}; // @[ShiftReg.scala 47:22]
wire [3:0] chain_io_d_hi = {
auto_in_sync_7, auto_in_sync_6, auto_in_sync_5, auto_in_sync_4
}; // @[ShiftReg.scala 47:22]
wire [7:0] _WIRE_1 = chain_io_q;
SynchronizerShiftReg_w8_d3 chain ( // @[ShiftReg.scala 45:23]
.clock(chain_clock),
.io_d (chain_io_d),
.io_q (chain_io_q)
);
assign auto_out_0 = _WIRE_1[0]; // @[ShiftReg.scala 48:24]
assign auto_out_1 = _WIRE_1[1]; // @[ShiftReg.scala 48:24]
assign auto_out_2 = _WIRE_1[2]; // @[ShiftReg.scala 48:24]
assign auto_out_3 = _WIRE_1[3]; // @[ShiftReg.scala 48:24]
assign auto_out_4 = _WIRE_1[4]; // @[ShiftReg.scala 48:24]
assign auto_out_5 = _WIRE_1[5]; // @[ShiftReg.scala 48:24]
assign auto_out_6 = _WIRE_1[6]; // @[ShiftReg.scala 48:24]
assign auto_out_7 = _WIRE_1[7]; // @[ShiftReg.scala 48:24]
assign chain_clock = clock;
assign chain_io_d = {chain_io_d_hi, chain_io_d_lo}; // @[ShiftReg.scala 47:22]
endmodule
| 6.70996 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_5_clock,
output auto_out_5_reset,
output auto_out_4_clock,
output auto_out_4_reset,
output auto_out_3_clock,
output auto_out_3_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_5_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_5_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_4_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_4_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_3_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_3_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.914809 |
module SourceE (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_sink,
output io_e_valid,
output [2:0] io_e_bits_sink
);
wire io_e_q_clock; // @[Decoupled.scala 361:21]
wire io_e_q_reset; // @[Decoupled.scala 361:21]
wire io_e_q_io_enq_ready; // @[Decoupled.scala 361:21]
wire io_e_q_io_enq_valid; // @[Decoupled.scala 361:21]
wire [2:0] io_e_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
wire io_e_q_io_deq_ready; // @[Decoupled.scala 361:21]
wire io_e_q_io_deq_valid; // @[Decoupled.scala 361:21]
wire [2:0] io_e_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
Queue_42 io_e_q ( // @[Decoupled.scala 361:21]
.clock(io_e_q_clock),
.reset(io_e_q_reset),
.io_enq_ready(io_e_q_io_enq_ready),
.io_enq_valid(io_e_q_io_enq_valid),
.io_enq_bits_sink(io_e_q_io_enq_bits_sink),
.io_deq_ready(io_e_q_io_deq_ready),
.io_deq_valid(io_e_q_io_deq_valid),
.io_deq_bits_sink(io_e_q_io_deq_bits_sink)
);
assign io_req_ready = io_e_q_io_enq_ready; // @[SourceE.scala 38:15 Decoupled.scala 365:17]
assign io_e_valid = io_e_q_io_deq_valid; // @[SourceE.scala 39:8]
assign io_e_bits_sink = io_e_q_io_deq_bits_sink; // @[SourceE.scala 39:8]
assign io_e_q_clock = clock;
assign io_e_q_reset = reset;
assign io_e_q_io_enq_valid = io_req_valid; // @[SourceE.scala 38:15 42:11]
assign io_e_q_io_enq_bits_sink = io_req_bits_sink; // @[SourceE.scala 38:15 44:15]
assign io_e_q_io_deq_ready = 1'h1; // @[SourceE.scala 39:8]
endmodule
| 6.986119 |
module SourceX (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input io_x_ready,
output io_x_valid
);
wire io_x_q_clock; // @[Decoupled.scala 361:21]
wire io_x_q_reset; // @[Decoupled.scala 361:21]
wire io_x_q_io_enq_ready; // @[Decoupled.scala 361:21]
wire io_x_q_io_enq_valid; // @[Decoupled.scala 361:21]
wire io_x_q_io_deq_ready; // @[Decoupled.scala 361:21]
wire io_x_q_io_deq_valid; // @[Decoupled.scala 361:21]
Queue_43 io_x_q ( // @[Decoupled.scala 361:21]
.clock(io_x_q_clock),
.reset(io_x_q_reset),
.io_enq_ready(io_x_q_io_enq_ready),
.io_enq_valid(io_x_q_io_enq_valid),
.io_deq_ready(io_x_q_io_deq_ready),
.io_deq_valid(io_x_q_io_deq_valid)
);
assign io_req_ready = io_x_q_io_enq_ready; // @[SourceX.scala 36:15 Decoupled.scala 365:17]
assign io_x_valid = io_x_q_io_deq_valid; // @[SourceX.scala 37:8]
assign io_x_q_clock = clock;
assign io_x_q_reset = reset;
assign io_x_q_io_enq_valid = io_req_valid; // @[SourceX.scala 36:15 40:11]
assign io_x_q_io_deq_ready = io_x_ready; // @[SourceX.scala 37:8]
endmodule
| 6.885755 |
module SinkE (
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
| 8.126739 |
module SinkX (
input clock,
input reset,
input io_req_ready,
output io_req_valid,
output [14:0] io_req_bits_tag,
output [ 9:0] io_req_bits_set,
output io_x_ready,
input io_x_valid,
input [31:0] io_x_bits_address
);
wire x_clock; // @[Decoupled.scala 361:21]
wire x_reset; // @[Decoupled.scala 361:21]
wire x_io_enq_ready; // @[Decoupled.scala 361:21]
wire x_io_enq_valid; // @[Decoupled.scala 361:21]
wire [31:0] x_io_enq_bits_address; // @[Decoupled.scala 361:21]
wire x_io_deq_ready; // @[Decoupled.scala 361:21]
wire x_io_deq_valid; // @[Decoupled.scala 361:21]
wire [31:0] x_io_deq_bits_address; // @[Decoupled.scala 361:21]
wire [6:0] offset_lo_lo = {
x_io_deq_bits_address[6],
x_io_deq_bits_address[5],
x_io_deq_bits_address[4],
x_io_deq_bits_address[3],
x_io_deq_bits_address[2],
x_io_deq_bits_address[1],
x_io_deq_bits_address[0]
}; // @[Cat.scala 31:58]
wire [14:0] offset_lo = {
x_io_deq_bits_address[14],
x_io_deq_bits_address[13],
x_io_deq_bits_address[12],
x_io_deq_bits_address[11],
x_io_deq_bits_address[10],
x_io_deq_bits_address[9],
x_io_deq_bits_address[8],
x_io_deq_bits_address[7],
offset_lo_lo
}; // @[Cat.scala 31:58]
wire [7:0] offset_hi_lo = {
x_io_deq_bits_address[22],
x_io_deq_bits_address[21],
x_io_deq_bits_address[20],
x_io_deq_bits_address[19],
x_io_deq_bits_address[18],
x_io_deq_bits_address[17],
x_io_deq_bits_address[16],
x_io_deq_bits_address[15]
}; // @[Cat.scala 31:58]
wire [30:0] offset = {
x_io_deq_bits_address[30],
x_io_deq_bits_address[29],
x_io_deq_bits_address[28],
x_io_deq_bits_address[27],
x_io_deq_bits_address[26],
x_io_deq_bits_address[25],
x_io_deq_bits_address[24],
x_io_deq_bits_address[23],
offset_hi_lo,
offset_lo
}; // @[Cat.scala 31:58]
wire [24:0] set = offset[30:6]; // @[Parameters.scala 212:22]
Queue_47 x ( // @[Decoupled.scala 361:21]
.clock(x_clock),
.reset(x_reset),
.io_enq_ready(x_io_enq_ready),
.io_enq_valid(x_io_enq_valid),
.io_enq_bits_address(x_io_enq_bits_address),
.io_deq_ready(x_io_deq_ready),
.io_deq_valid(x_io_deq_valid),
.io_deq_bits_address(x_io_deq_bits_address)
);
assign io_req_valid = x_io_deq_valid; // @[SinkX.scala 39:16]
assign io_req_bits_tag = set[24:10]; // @[Parameters.scala 213:19]
assign io_req_bits_set = set[9:0]; // @[Parameters.scala 214:28]
assign io_x_ready = x_io_enq_ready; // @[Decoupled.scala 365:17]
assign x_clock = clock;
assign x_reset = reset;
assign x_io_enq_valid = io_x_valid; // @[Decoupled.scala 363:22]
assign x_io_enq_bits_address = io_x_bits_address; // @[Decoupled.scala 364:21]
assign x_io_deq_ready = io_req_ready; // @[SinkX.scala 38:11]
endmodule
| 6.564372 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae_ptw,
input io_x_ae_final,
input io_x_pf,
input io_x_gf,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_ppp,
input io_x_pal,
input io_x_paa,
input io_x_eff,
input io_x_c,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae_ptw,
output io_y_ae_final,
output io_y_pf,
output io_y_gf,
output io_y_sw,
output io_y_sx,
output io_y_sr,
output io_y_pw,
output io_y_px,
output io_y_pr,
output io_y_ppp,
output io_y_pal,
output io_y_paa,
output io_y_eff,
output io_y_c
);
assign io_y_ppn = io_x_ppn; // @[package.scala 263:12]
assign io_y_u = io_x_u; // @[package.scala 263:12]
assign io_y_ae_ptw = io_x_ae_ptw; // @[package.scala 263:12]
assign io_y_ae_final = io_x_ae_final; // @[package.scala 263:12]
assign io_y_pf = io_x_pf; // @[package.scala 263:12]
assign io_y_gf = io_x_gf; // @[package.scala 263:12]
assign io_y_sw = io_x_sw; // @[package.scala 263:12]
assign io_y_sx = io_x_sx; // @[package.scala 263:12]
assign io_y_sr = io_x_sr; // @[package.scala 263:12]
assign io_y_pw = io_x_pw; // @[package.scala 263:12]
assign io_y_px = io_x_px; // @[package.scala 263:12]
assign io_y_pr = io_x_pr; // @[package.scala 263:12]
assign io_y_ppp = io_x_ppp; // @[package.scala 263:12]
assign io_y_pal = io_x_pal; // @[package.scala 263:12]
assign io_y_paa = io_x_paa; // @[package.scala 263:12]
assign io_y_eff = io_x_eff; // @[package.scala 263:12]
assign io_y_c = io_x_c; // @[package.scala 263:12]
endmodule
| 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 65:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 66:33]
wire add = io_cmd == 5'h8; // @[AMOALU.scala 67:20]
wire _logic_and_T = io_cmd == 5'ha; // @[AMOALU.scala 68:26]
wire logic_and = io_cmd == 5'ha | io_cmd == 5'hb; // @[AMOALU.scala 68:38]
wire logic_xor = io_cmd == 5'h9 | _logic_and_T; // @[AMOALU.scala 69:39]
wire _adder_out_mask_T_1 = ~io_mask[3]; // @[AMOALU.scala 73:61]
wire [31:0] _adder_out_mask_T_2 = {_adder_out_mask_T_1, 31'h0}; // @[AMOALU.scala 73:77]
wire [63:0] _adder_out_mask_T_3 = {{32'd0}, _adder_out_mask_T_2}; // @[AMOALU.scala 73:96]
wire [63:0] adder_out_mask = ~_adder_out_mask_T_3; // @[AMOALU.scala 73:16]
wire [63:0] _adder_out_T = io_lhs & adder_out_mask; // @[AMOALU.scala 74:13]
wire [63:0] _adder_out_T_1 = io_rhs & adder_out_mask; // @[AMOALU.scala 74:31]
wire [63:0] adder_out = _adder_out_T + _adder_out_T_1; // @[AMOALU.scala 74:21]
wire [4:0] _less_signed_T = io_cmd & 5'h2; // @[AMOALU.scala 87:17]
wire less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala 87:25]
wire _less_T_12 = io_lhs[31:0] < io_rhs[31:0]; // @[AMOALU.scala 80:35]
wire _less_T_14 = io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & _less_T_12; // @[AMOALU.scala 81:38]
wire _less_T_17 = less_signed ? io_lhs[63] : io_rhs[63]; // @[AMOALU.scala 89:58]
wire _less_T_18 = io_lhs[63] == io_rhs[63] ? _less_T_14 : _less_T_17; // @[AMOALU.scala 89:10]
wire _less_T_28 = less_signed ? io_lhs[31] : io_rhs[31]; // @[AMOALU.scala 89:58]
wire _less_T_29 = io_lhs[31] == io_rhs[31] ? _less_T_12 : _less_T_28; // @[AMOALU.scala 89:10]
wire less = io_mask[4] ? _less_T_18 : _less_T_29; // @[Mux.scala 47:70]
wire _minmax_T = less ? min : max; // @[AMOALU.scala 95:23]
wire [63:0] minmax = _minmax_T ? io_lhs : io_rhs; // @[AMOALU.scala 95:19]
wire [63:0] _logic_T = io_lhs & io_rhs; // @[AMOALU.scala 97:27]
wire [63:0] _logic_T_1 = logic_and ? _logic_T : 64'h0; // @[AMOALU.scala 97:8]
wire [63:0] _logic_T_2 = io_lhs ^ io_rhs; // @[AMOALU.scala 98:27]
wire [63:0] _logic_T_3 = logic_xor ? _logic_T_2 : 64'h0; // @[AMOALU.scala 98:8]
wire [63:0] logic_ = _logic_T_1 | _logic_T_3; // @[AMOALU.scala 97:42]
wire [63:0] _out_T_1 = logic_and | logic_xor ? logic_ : minmax; // @[AMOALU.scala 101:8]
wire [63:0] out = add ? adder_out : _out_T_1; // @[AMOALU.scala 100:8]
wire [7:0] _wmask_T_9 = io_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_11 = io_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_13 = io_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_15 = io_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_17 = io_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_19 = io_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_21 = io_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_23 = io_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [63:0] wmask = {
_wmask_T_23,
_wmask_T_21,
_wmask_T_19,
_wmask_T_17,
_wmask_T_15,
_wmask_T_13,
_wmask_T_11,
_wmask_T_9
}; // @[Cat.scala 31:58]
wire [63:0] _io_out_T = wmask & out; // @[AMOALU.scala 105:19]
wire [63:0] _io_out_T_1 = ~wmask; // @[AMOALU.scala 105:27]
wire [63:0] _io_out_T_2 = _io_out_T_1 & io_lhs; // @[AMOALU.scala 105:34]
assign io_out = _io_out_T | _io_out_T_2; // @[AMOALU.scala 105:25]
endmodule
| 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawA_isSpecial = rawA_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawA__isNaN = rawA_isSpecial & rawA_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire rawA__isInf = rawA_isSpecial & ~rawA_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
wire rawA__sign = io_a[64]; // @[rawFloatFromRecFN.scala 58:25]
wire [12:0] rawA__sExp = {1'b0, $signed(rawA_exp)}; // @[rawFloatFromRecFN.scala 59:27]
wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [53:0] rawA__sig = {1'h0, _rawA_out_sig_T, io_a[51:0]}; // @[Cat.scala 31:58]
wire [11:0] rawB_exp = io_b[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawB_isZero = rawB_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawB_isSpecial = rawB_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawB__isNaN = rawB_isSpecial & rawB_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire rawB__isInf = rawB_isSpecial & ~rawB_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
wire rawB__sign = io_b[64]; // @[rawFloatFromRecFN.scala 58:25]
wire [12:0] rawB__sExp = {1'b0, $signed(rawB_exp)}; // @[rawFloatFromRecFN.scala 59:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [53:0] rawB__sig = {1'h0, _rawB_out_sig_T, io_b[51:0]}; // @[Cat.scala 31:58]
wire ordered = ~rawA__isNaN & ~rawB__isNaN; // @[CompareRecFN.scala 57:32]
wire bothInfs = rawA__isInf & rawB__isInf; // @[CompareRecFN.scala 58:33]
wire bothZeros = rawA_isZero & rawB_isZero; // @[CompareRecFN.scala 59:33]
wire eqExps = $signed(rawA__sExp) == $signed(rawB__sExp); // @[CompareRecFN.scala 60:29]
wire common_ltMags = $signed(
rawA__sExp
) < $signed(
rawB__sExp
) | eqExps & rawA__sig < rawB__sig; // @[CompareRecFN.scala 62:33]
wire common_eqMags = eqExps & rawA__sig == rawB__sig; // @[CompareRecFN.scala 63:32]
wire _ordered_lt_T_1 = ~rawB__sign; // @[CompareRecFN.scala 67:28]
wire _ordered_lt_T_9 = _ordered_lt_T_1 & common_ltMags; // @[CompareRecFN.scala 70:41]
wire _ordered_lt_T_10 = rawA__sign & ~common_ltMags & ~common_eqMags | _ordered_lt_T_9; // @[CompareRecFN.scala 69:74]
wire _ordered_lt_T_11 = ~bothInfs & _ordered_lt_T_10; // @[CompareRecFN.scala 68:30]
wire _ordered_lt_T_12 = rawA__sign & ~rawB__sign | _ordered_lt_T_11; // @[CompareRecFN.scala 67:41]
wire ordered_lt = ~bothZeros & _ordered_lt_T_12; // @[CompareRecFN.scala 66:21]
wire ordered_eq = bothZeros | rawA__sign == rawB__sign & (bothInfs | common_eqMags); // @[CompareRecFN.scala 72:19]
wire _invalid_T_2 = rawA__isNaN & ~rawA__sig[51]; // @[common.scala 82:46]
wire _invalid_T_5 = rawB__isNaN & ~rawB__sig[51]; // @[common.scala 82:46]
wire _invalid_T_8 = io_signaling & ~ordered; // @[CompareRecFN.scala 76:27]
wire invalid = _invalid_T_2 | _invalid_T_5 | _invalid_T_8; // @[CompareRecFN.scala 75:58]
assign io_lt = ordered & ordered_lt; // @[CompareRecFN.scala 78:22]
assign io_eq = ordered & ordered_eq; // @[CompareRecFN.scala 79:22]
assign io_exceptionFlags = {invalid, 4'h0}; // @[Cat.scala 31:58]
endmodule
| 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RecFNToRecFN.scala 72:19]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RecFNToRecFN.scala 72:19]
wire [53:0] roundAnyRawFNToRecFN_io_in_sig; // @[RecFNToRecFN.scala 72:19]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RecFNToRecFN.scala 72:19]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RecFNToRecFN.scala 72:19]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RecFNToRecFN.scala 72:19]
wire [11:0] rawIn_exp = io_in[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawIn_isZero = rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawIn_isSpecial = rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawIn__isNaN = rawIn_isSpecial & rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [1:0] rawIn_out_sig_hi = {1'h0, _rawIn_out_sig_T}; // @[Cat.scala 31:58]
wire [53:0] rawIn__sig = {1'h0, _rawIn_out_sig_T, io_in[51:0]}; // @[Cat.scala 31:58]
RoundAnyRawFNToRecFN_3 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala 72:19]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RecFNToRecFN.scala 85:27]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RecFNToRecFN.scala 86:27]
assign roundAnyRawFNToRecFN_io_invalidExc = rawIn__isNaN & ~rawIn__sig[51]; // @[common.scala 82:46]
assign roundAnyRawFNToRecFN_io_in_isNaN = rawIn_isSpecial & rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
assign roundAnyRawFNToRecFN_io_in_isInf = rawIn_isSpecial & ~rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
assign roundAnyRawFNToRecFN_io_in_isZero = rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
assign roundAnyRawFNToRecFN_io_in_sign = io_in[64]; // @[rawFloatFromRecFN.scala 58:25]
assign roundAnyRawFNToRecFN_io_in_sExp = {
1'b0, $signed(rawIn_exp)
}; // @[rawFloatFromRecFN.scala 59:27]
assign roundAnyRawFNToRecFN_io_in_sig = {rawIn_out_sig_hi, io_in[51:0]}; // @[Cat.scala 31:58]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RecFNToRecFN.scala 83:48]
endmodule
| 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN_4 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN_4 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module OptimizationBarrier_42 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_43 (
input [43:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [43:0] io_y_ppn,
output io_y_d,
output io_y_a,
output io_y_g,
output io_y_u,
output io_y_x,
output io_y_w,
output io_y_r,
output io_y_v
);
assign io_y_ppn = io_x_ppn; // @[package.scala 263:12]
assign io_y_d = io_x_d; // @[package.scala 263:12]
assign io_y_a = io_x_a; // @[package.scala 263:12]
assign io_y_g = io_x_g; // @[package.scala 263:12]
assign io_y_u = io_x_u; // @[package.scala 263:12]
assign io_y_x = io_x_x; // @[package.scala 263:12]
assign io_y_w = io_x_w; // @[package.scala 263:12]
assign io_y_r = io_x_r; // @[package.scala 263:12]
assign io_y_v = io_x_v; // @[package.scala 263:12]
endmodule
| 7.587549 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 173:39]
endmodule
| 6.820992 |
module IntSyncAsyncCrossingSink_1 (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.clock(chain_clock),
.io_d (chain_io_d),
.io_q (chain_io_q)
);
assign auto_out_0 = chain_io_q; // @[ShiftReg.scala 48:24]
assign chain_clock = clock;
assign chain_io_d = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 1'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala 89:21]
AsyncResetRegVec_w1_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module PLICFanIn (
input [2:0] io_prio_0,
input [2:0] io_prio_1,
input [2:0] io_prio_2,
input [2:0] io_prio_3,
input [2:0] io_prio_4,
input [2:0] io_prio_5,
input [2:0] io_prio_6,
input [2:0] io_prio_7,
input [7:0] io_ip,
output [3:0] io_dev,
output [2:0] io_max
);
wire [3:0] effectivePriority_1 = {io_ip[0], io_prio_0}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_2 = {io_ip[1], io_prio_1}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_3 = {io_ip[2], io_prio_2}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_4 = {io_ip[3], io_prio_3}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_5 = {io_ip[4], io_prio_4}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_6 = {io_ip[5], io_prio_5}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_7 = {io_ip[6], io_prio_6}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_8 = {io_ip[7], io_prio_7}; // @[Cat.scala 31:58]
wire _T = 4'h8 >= effectivePriority_1; // @[Plic.scala 344:20]
wire [3:0] _T_2 = _T ? 4'h8 : effectivePriority_1; // @[Misc.scala 34:9]
wire _T_3 = _T ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_4 = effectivePriority_2 >= effectivePriority_3; // @[Plic.scala 344:20]
wire [3:0] _T_6 = _T_4 ? effectivePriority_2 : effectivePriority_3; // @[Misc.scala 34:9]
wire _T_7 = _T_4 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_8 = _T_2 >= _T_6; // @[Plic.scala 344:20]
wire [1:0] _GEN_0 = {{1'd0}, _T_7}; // @[Plic.scala 344:61]
wire [1:0] _T_9 = 2'h2 | _GEN_0; // @[Plic.scala 344:61]
wire [3:0] _T_10 = _T_8 ? _T_2 : _T_6; // @[Misc.scala 34:9]
wire [1:0] _T_11 = _T_8 ? {{1'd0}, _T_3} : _T_9; // @[Misc.scala 34:36]
wire _T_12 = effectivePriority_4 >= effectivePriority_5; // @[Plic.scala 344:20]
wire [3:0] _T_14 = _T_12 ? effectivePriority_4 : effectivePriority_5; // @[Misc.scala 34:9]
wire _T_15 = _T_12 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_16 = effectivePriority_6 >= effectivePriority_7; // @[Plic.scala 344:20]
wire [3:0] _T_18 = _T_16 ? effectivePriority_6 : effectivePriority_7; // @[Misc.scala 34:9]
wire _T_19 = _T_16 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_20 = _T_14 >= _T_18; // @[Plic.scala 344:20]
wire [1:0] _GEN_1 = {{1'd0}, _T_19}; // @[Plic.scala 344:61]
wire [1:0] _T_21 = 2'h2 | _GEN_1; // @[Plic.scala 344:61]
wire [3:0] _T_22 = _T_20 ? _T_14 : _T_18; // @[Misc.scala 34:9]
wire [1:0] _T_23 = _T_20 ? {{1'd0}, _T_15} : _T_21; // @[Misc.scala 34:36]
wire _T_24 = _T_10 >= _T_22; // @[Plic.scala 344:20]
wire [2:0] _GEN_2 = {{1'd0}, _T_23}; // @[Plic.scala 344:61]
wire [2:0] _T_25 = 3'h4 | _GEN_2; // @[Plic.scala 344:61]
wire [3:0] _T_26 = _T_24 ? _T_10 : _T_22; // @[Misc.scala 34:9]
wire [2:0] _T_27 = _T_24 ? {{1'd0}, _T_11} : _T_25; // @[Misc.scala 34:36]
wire _T_28 = _T_26 >= effectivePriority_8; // @[Plic.scala 344:20]
wire [3:0] maxPri = _T_28 ? _T_26 : effectivePriority_8; // @[Misc.scala 34:9]
assign io_dev = _T_28 ? {{1'd0}, _T_27} : 4'h8; // @[Misc.scala 34:36]
assign io_max = maxPri[2:0]; // @[Plic.scala 350:10]
endmodule
| 8.419901 |
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