code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
module syncreg (
CLKA,
CLKB,
RST,
DATA_IN,
DATA_OUT
);
input CLKA;
input CLKB;
input RST;
input [3:0] DATA_IN;
output [3:0] DATA_OUT;
reg [3:0] regA;
reg [3:0] regB;
reg strobe_toggle;
reg ack_toggle;
wire A_not_equal;
wire A_enable;
wire strobe_sff_out;
wire ack_sff_out;
wire [3:0] DATA_OUT;
// Combinatorial assignments
assign A_enable = A_not_equal & ack_sff_out;
assign A_not_equal = !(DATA_IN == regA);
assign DATA_OUT = regB;
// register A (latches input any time it changes)
always @ (posedge CLKA or posedge RST)
begin
if(RST)
regA <= 4'b0;
else if(A_enable)
regA <= DATA_IN;
end
// register B (latches data from regA when enabled by the strobe SFF)
always @ (posedge CLKB or posedge RST)
begin
if(RST)
regB <= 4'b0;
else if(strobe_sff_out)
regB <= regA;
end
// 'strobe' toggle FF
always @ (posedge CLKA or posedge RST)
begin
if(RST)
strobe_toggle <= 1'b0;
else if(A_enable)
strobe_toggle <= ~strobe_toggle;
end
// 'ack' toggle FF
// This is set to '1' at reset, to initialize the unit.
always @ (posedge CLKB or posedge RST)
begin
if(RST)
ack_toggle <= 1'b1;
else if (strobe_sff_out)
ack_toggle <= ~ack_toggle;
end
// 'strobe' sync element
syncflop strobe_sff (
.DEST_CLK (CLKB),
.D_SET (1'b0),
.D_RST (strobe_sff_out),
.RESET (RST),
.TOGGLE_IN (strobe_toggle),
.D_OUT (strobe_sff_out)
);
// 'ack' sync element
syncflop ack_sff (
.DEST_CLK (CLKA),
.D_SET (1'b0),
.D_RST (A_enable),
.RESET (RST),
.TOGGLE_IN (ack_toggle),
.D_OUT (ack_sff_out)
);
endmodule
| 7.4465 |
module across clock domains.
// Uses a Handshake Pulse protocol to trigger the load on
// destination side registers
// Transfer takes 3 dCLK for destination side to see data,
// sRDY recovers takes 3 dCLK + 3 sCLK
module SyncRegister(
sCLK,
sRST,
dCLK,
sEN,
sRDY,
sD_IN,
dD_OUT
);
parameter width = 1 ;
parameter init = { width {1'b0 }} ;
// Source clock domain ports
input sCLK ;
input sRST ;
input sEN ;
input [width -1 : 0] sD_IN ;
output sRDY ;
// Destination clock domain ports
input dCLK ;
output [width -1 : 0] dD_OUT ;
wire dPulse ;
reg [width -1 : 0] sDataSyncIn ;
reg [width -1 : 0] dD_OUT ;
// instantiate a Handshake Sync
SyncHandshake sync( .sCLK(sCLK), .sRST(sRST),
.dCLK(dCLK),
.sEN(sEN), .sRDY(sRDY),
.dPulse(dPulse) ) ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sDataSyncIn <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( sEN )
begin
sDataSyncIn <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
// Transfer the data to destination domain when dPulsed is asserted.
// Setup and hold time are assured since at least 2 dClks occured since
// sDataSyncIn have been written.
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dD_OUT <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( dPulse )
begin
dD_OUT <= `BSV_ASSIGNMENT_DELAY sDataSyncIn ;// clock domain crossing
end // if ( dPulse )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sDataSyncIn = {((width + 1)/2){2'b10}} ;
dD_OUT = {((width + 1)/2){2'b10}} ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 6.595237 |
module testSyncRegister() ;
parameter dsize = 8;
wire sCLK, sRST, dCLK ;
wire sEN ;
wire sRDY ;
reg [dsize -1:0] sCNT ;
wire [dsize -1:0] sDIN, dDOUT ;
ClockGen#(20,9,10) sc( sCLK );
ClockGen#(11,12,26) dc( dCLK );
initial
begin
sCNT = 0;
$dumpfile("SyncRegister.dump");
$dumpvars(5) ;
$dumpon ;
#100000 $finish ;
end
SyncRegister #(dsize)
dut( sCLK, sRST, dCLK,
sEN, sRDY, sDIN,
dDOUT ) ;
assign sDIN = sCNT ;
assign sEN = sRDY ;
always @(posedge sCLK)
begin
if (sRDY )
begin
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
end
end // always @ (posedge sCLK)
endmodule
| 7.222289 |
module syncRegisterFile #(
parameter LOG = 0,
PulseWidth = 100
) (
input clk,
input _wr_en,
input [1:0] wr_addr,
input [7:0] wr_data,
input _rdL_en,
input [1:0] rdL_addr,
output [7:0] rdL_data,
input _rdR_en,
input [1:0] rdR_addr,
output [7:0] rdR_data
);
logic [31:0] binding_for_tests;
assign binding_for_tests = {
{regFile.bankL_hi.registers[0], regFile.bankL_lo.registers[0]},
{regFile.bankL_hi.registers[1], regFile.bankL_lo.registers[1]},
{regFile.bankL_hi.registers[2], regFile.bankL_lo.registers[2]},
{regFile.bankL_hi.registers[3], regFile.bankL_lo.registers[3]}
};
function [7:0] get([1:0] r);
get = regFile.get(r);
endfunction
wire [7:0] wr_data_latched;
hct74574 #(
.LOG(0)
) input_register (
.D (wr_data),
.Q (wr_data_latched),
.CLK(clk),
._OE(1'b0)
); // registers data on clk +ve & _pulse goes low slightly later.
registerFile #(
.LOG(LOG)
) regFile (
._wr_en (_wr_en),
.wr_addr,
.wr_data(wr_data_latched),
._rdL_en,
.rdL_addr,
.rdL_data,
._rdR_en,
.rdR_addr,
.rdR_data
);
/*
if (LOG) always @(posedge clk) begin
$display("%9t ", $time, "REGFILE : REGISTERED input data %08b", wr_data);
end
*/
/*
if (LOG) always @(*) begin
//$display("%9t ", $time, "REGFILE-S : ARGS : _wr_en=%1b _pulse=%1b write[%d]=%d _rdX_en=%1b X[%d]=>%d _rdY_en=%1b Y[%d]=>%d (preletch=%d) _MR=%1b" ,
// _wr_en, _pulse, wr_addr, wr_data, _rdL_en, rdL_addr, rdL_data, _rdL_en, rdR_addr, rdR_data, wr_data_latched, _MR);
if (!_wr_en) $display("%9t ", $time, "REGFILE : UPDATING write[%d] = %d", wr_addr, wr_data_latched);
end
if (LOG) always @(posedge _wr_en) begin
$display("%9t ", $time, "REGFILE : LATCHED write[%d]=%d", wr_addr, wr_data_latched);
end
*/
endmodule
| 7.223018 |
module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is
// synchronized to the clock.
module SyncReset (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK ) // reset is read synchronous with clock
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY {(RSTDELAY + 1) {`BSV_RESET_VALUE}} ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE }} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.035349 |
module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK or `BSV_RESET_EDGE IN_RST )
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.035349 |
module syncreset_enable_divider (
clk,
ce,
syncreset,
reset_n,
enable_in,
enable_out
);
parameter count = 1;
parameter resetcount = 0;
input clk;
input ce;
input syncreset;
input reset_n;
input enable_in;
output enable_out;
parameter width = $clog2(count);
reg [width-1:0] count_reg;
reg [width-1:0] count_next;
reg enabled_out_next;
reg enabled_out_reg;
always @(posedge clk or negedge reset_n)
if (reset_n == 1'b0) begin
count_reg <= {width{1'b0}};
enabled_out_reg <= 1'b0;
end else if (ce) begin
count_reg <= count_next;
enabled_out_reg <= enabled_out_next;
end
always @(count_reg or enable_in or enabled_out_reg or syncreset) begin
count_next <= count_reg;
enabled_out_next <= enabled_out_reg;
if (enable_in == 1'b1) begin
count_next <= (count_reg + 1);
enabled_out_next <= 1'b0;
if (count_reg == (count - 1)) begin
count_next <= 0;
enabled_out_next <= 1'b1;
end
end
if (syncreset == 1'b1) count_next <= resetcount;
end
assign enable_out = enabled_out_reg & enable_in;
endmodule
| 7.174894 |
module Syncro (
input PixClk,
output reg HSync,
output reg VSync,
output reg Video
);
// -----------------------------------
// 640x360@60Hz -- PixClk = 25.200MHz
// -----------------------------------
parameter integer H_sync_start = 656;
parameter integer H_sync_stop = 751;
parameter integer H_img_start = 0;
parameter integer H_img_stop = 639;
parameter integer H_screen_stop = 799;
parameter integer H_polarity = 1'b0;
parameter integer V_sync_start = 361;
parameter integer V_sync_stop = 364;
parameter integer V_img_start = 0;
parameter integer V_img_stop = 359;
parameter integer V_screen_stop = 449;
parameter integer V_polarity = 1'b0;
reg [10:0] Row;
reg [10:0] Col;
initial begin
Row = 11'h000;
Col = 11'h000;
HSync = 1'b0;
VSync = 1'b0;
Video = 1'b0;
end
always @(negedge PixClk) begin
HSync = ((Col < H_sync_start) || (Col > H_sync_stop)) ? !H_polarity : H_polarity;
VSync = ((Row < V_sync_start) || (Row > V_sync_stop)) ? !V_polarity : V_polarity;
Video = ((Col < H_img_start) || (Row < V_img_start) || (Col > H_img_stop) || (Row > V_img_stop)) ? 1'b0 : 1'b1;
Col = Col + 1;
if (Col > H_screen_stop) begin
Col = 0;
Row = Row + 1;
if (Row > V_screen_stop) begin
Row = 0;
end
end
end
endmodule
| 7.711369 |
module sync #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
reg [WIDTH-1:0] buffer;
always @(posedge clk) begin
buffer <= d;
q <= buffer;
end
endmodule
| 7.012515 |
module d_flip_flop #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk) q <= d;
endmodule
| 8.794161 |
module syncSRAM #(
parameter DW = 256,
AW = 8
) (
input clk,
input we,
input [AW-1:0] wa,
input [DW-1:0] wd,
input re,
input [AW-1:0] ra,
output [DW-1:0] rd
);
parameter DP = 1 << AW; // depth
reg [DW-1:0] mem[0:DP-1];
reg [DW-1:0] reg_rd;
assign rd = reg_rd;
always @(posedge clk) begin
if (re) begin
reg_rd <= mem[ra];
end
if (we) begin
mem[wa] <= wd;
end
end
endmodule
| 8.304167 |
module is the dataflow level model of the counter.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncUp(q, clk, rst);
output [3:0] q;
input clk, rst;
wire [3:0] d, qb;
// Connecting DFFs to form a 4 bit counter
assign d[3] = (qb[0] & q[3]) | (qb[1] & q[3]) | (qb[2] & q[3]) | (qb[3] & q[2] & q[1] & q[0]);
DFlipFlop dff3 (q[3], qb[3], d[3], clk, rst);
assign d[2] = (q[2] & qb[0]) | (qb[1] & q[2]) | (qb[2] & q[1] & q[0]);
DFlipFlop dff2 (q[2], qb[2], d[2], clk, rst);
assign d[1] = q[1] ^ q[0];
DFlipFlop dff1 (q[1], qb[1], d[1], clk, rst);
assign d[0] = qb[0];
DFlipFlop dff0 (q[0], qb[0], d[0], clk, rst);
endmodule
| 8.908359 |
module DFlipFlop (
q,
qBar,
D,
clk,
rst
);
input D, clk, rst;
output q, qBar;
reg q;
not n1 (qBar, q);
always @(negedge rst or posedge clk) begin
if (!rst) q = 0;
else q = D;
end
endmodule
| 7.170064 |
module is intended for use with GTKwave on the PC.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
`include "syncUp.v"
module syncUpGTK;
// connect the two modules
wire [3:0] qBench;
wire clkBench, rstBench;
// declare an instance of the syncUp module
syncUp mySyncUp (qBench, clkBench, rstBench);
// declare an instance of the testIt module
Tester aTester (clkBench, rstBench, qBench);
// file for gtkwave
initial
begin
$dumpfile("syncUp.vcd");
$dumpvars(1, mySyncUp);
end
endmodule
| 9.106975 |
module is intended for use with the DE1_SoC and Spinal Tap.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncUpTop (LEDR, CLOCK_50, SW);
output [3:0] LEDR; // present state output
input CLOCK_50;
input [9:0] SW;
wire [31:0] clk; // choosing from 32 different clock speeds
syncUp mySyncUp (LEDR[3:0], clk[0], SW[9]); // Instantiate syncUp module; clock speed 0.75Hz
clock_divider cdiv (CLOCK_50, clk); // Instantiate clock_divider module
endmodule
| 9.106975 |
module clock_divider (
clock,
divided_clocks
);
input clock;
output [31:0] divided_clocks;
reg [31:0] divided_clocks;
initial divided_clocks = 0;
always @(posedge clock) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module syncUp_DE1 (
LEDR,
SW,
CLOCK_50
);
//Declaration of clocks, switches, and LEDs for usage
output [9:0] LEDR;
input [9:0] SW;
input CLOCK_50;
wire [31:0] clk;
//A 50 MHz clock is used for the DE1_SoC and Signal Tap
parameter clkBit = 0;
//Set unused LED's to low
assign LEDR[9:4] = 0;
//Declare an instance of the synthesized schematic module
syncSchematic mySyncSchm (
.q(LEDR[3:0]),
.clk(clk[clkBit]),
.reset(SW[9])
);
//Creates a clock divider to allow for a slower clock
clockDiv clkDiv (
.clkIn (CLOCK_50),
.clkOut(clk)
);
endmodule
| 7.044091 |
module that acts as our testbench. Required for iVerilog analysis
module Tester (clkTest, rstTest, qTest);
//Input and output decleration to connect to DUT
output reg rstTest, clkTest;
input [3:0] qTest;
parameter stimDelay = 20;
initial // Stimulus
begin
//Manually changing clock and applying reset
clkTest = 0; rstTest = 0;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest; rstTest = 1;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#stimDelay clkTest = ~clkTest;
#(2*stimDelay); // needed to see END of simulation
$finish; // finish simulation
end
endmodule
| 7.301252 |
module syncVGAGen (
input wire px_clk, // Pixel clock.
output wire [9:0] x_px, // X position for actual pixel.
output wire [9:0] y_px, // Y position for actual pixel.
output wire hsync, // Horizontal sync out.
output wire vsync, // Vertical sync out.
output wire activevideo // Active video.
);
// TODO: Utilizar una tabla de parámetros para obtener los valores para
// distintas resoluciones y poder modificar desde pines externos.
//
// https://www.digikey.com/eewiki/pages/viewpage.action?pageId=15925278#VGAController(VHDL)-Appendix:VGATimingSpecifications
//
// parameter [8:0] vga_table = {"800x600@72",72,50,800,56,120,64,600,37,6,23,'p','p'},
//
// Video structure constants.
parameter activeHvideo = 800; // Width of visible pixels.
parameter activeVvideo = 600; // Height of visible lines.
parameter hfp = 56; // Horizontal front porch length.
parameter hpulse = 120; // Hsync pulse length.
parameter hbp = 64; // Horizontal back porch length.
parameter vfp = 37; // Vertical front porch length.
parameter vpulse = 6; // Vsync pulse length.
parameter vbp = 23; // Vertical back porch length.
parameter blackH = hfp + hpulse + hbp; // Hide pixels in one line.
parameter blackV = vfp + vpulse + vbp; // Hide lines in one frame.
parameter hpixels = blackH + activeHvideo; // Total horizontal pixels.
parameter vlines = blackV + activeVvideo; // Total lines.
// Registers for storing the horizontal & vertical counters.
reg [10:0] hc;
reg [10:0] vc;
reg [ 9:0] x_px; // X position for actual pixel.
reg [ 9:0] y_px; // Y position for actual pixel.
// Counting pixels.
always @(posedge px_clk) begin
// Keep counting until the end of the line.
if (hc < hpixels - 1) hc <= hc + 1;
else
// When we hit the end of the line, reset the horizontal
// counter and increment the vertical counter.
// If vertical counter is at the end of the frame, then
// reset that one too.
begin
hc <= 0;
if (vc < vlines - 1) vc <= vc + 1;
else vc <= 0;
end
end
// Generate sync pulses (active low) and active video.
assign hsync = (hc >= hfp && hc < hfp + hpulse) ? 0 : 1;
assign vsync = (vc >= vfp && vc < vfp + vpulse) ? 0 : 1;
assign activevideo = (hc >= blackH && vc >= blackV) ? 1 : 0;
// Generate new pixel position.
always @(posedge px_clk) begin
// First check if we are within vertical active video range.
if (activevideo) begin
x_px <= hc - blackH;
y_px <= vc - blackV;
end else
// We are outside active video range so initial position it's ok.
begin
x_px <= 0;
y_px <= 0;
end
end
endmodule
| 7.856028 |
module SyncWire (
DIN,
DOUT
);
parameter width = 1;
input [width - 1 : 0] DIN;
output [width - 1 : 0] DOUT;
assign DOUT = DIN;
endmodule
| 7.635778 |
module sync_1bit #(
parameter N_STAGES = 2 // Should be >=2
) (
input wire clk,
input wire rst_n,
input wire i,
output wire o
);
(* keep = 1'b1 *) reg [N_STAGES-1:0] sync_flops;
always @(posedge clk or negedge rst_n)
if (!rst_n) sync_flops <= {N_STAGES{1'b0}};
else sync_flops <= {sync_flops[N_STAGES-2:0], i};
assign o = sync_flops[N_STAGES-1];
endmodule
| 8.65853 |
module clk_wiz_0 (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire reset;
clk_wiz_0_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.locked(locked),
.reset(reset)
);
endmodule
| 6.750754 |
module clk_wiz_0_clk_wiz (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire [15:0] NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf (
.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0)
);
(* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) (* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT")
) clkin1_ibufg (
.I(clk_in1),
.O(clk_in1_clk_wiz_0)
);
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf (
.I(clk_out1_clk_wiz_0),
.O(clk_out1)
);
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf (
.I(clk_out2_clk_wiz_0),
.O(clk_out2)
);
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(9),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(9),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(25),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE")
) plle2_adv_inst (
.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT1(clk_out2_clk_wiz_0),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0
}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PWRDWN(1'b0),
.RST(reset)
);
endmodule
| 7.432971 |
module sync_2ff (
clk,
din,
dout
);
input wire clk;
input wire din;
output wire dout;
reg temp1;
reg temp2;
assign dout = temp2;
always @(posedge clk) begin
temp1 <= din;
temp2 <= temp1;
end
endmodule
| 6.684057 |
module sync_2_fifo (
input clk,
input rst,
output [ 1:0] afull_out,
input [ 1:0] write_en_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_1_out,
output [63:0] data_0_out
);
wire [1:0] fifo_empty_s;
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full(afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full(afull_out[1])
);
assign empty_out = (fifo_empty_s != 2'd0);
endmodule
| 7.617307 |
module sync_3_fifo (
input clk,
input rst,
output [ 2:0] afull_out,
input [ 2:0] write_en_in,
input [63:0] data_2_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_2_out,
output [63:0] data_1_out,
output [63:0] data_0_out
);
// localparam FIFO_DEPTH = 512;
wire [2:0] fifo_empty_s;
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_0 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[0]),
// .write_en_in (write_en_in[0]),
// .data_in (data_0_in),
// .empty_out (fifo_empty_s[0]),
// .read_en_in (read_en_in),
// .data_out (data_0_out)
// );
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_1 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[1]),
// .write_en_in (write_en_in[1]),
// .data_in (data_1_in),
// .empty_out (fifo_empty_s[1]),
// .read_en_in (read_en_in),
// .data_out (data_1_out)
// );
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_2 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[2]),
// .write_en_in (write_en_in[2]),
// .data_in (data_2_in),
// .empty_out (fifo_empty_s[2]),
// .read_en_in (read_en_in),
// .data_out (data_2_out)
// );
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full(afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full(afull_out[1])
);
fifo_64x512 FIFO_2 (
.clk (clk),
.rst (rst),
.din (data_2_in),
.wr_en (write_en_in[2]),
.rd_en (read_en_in),
.dout (data_2_out),
.full (),
.empty (fifo_empty_s[2]),
.prog_full(afull_out[2])
);
assign empty_out = (fifo_empty_s != 3'd0);
endmodule
| 8.519773 |
module sync_addr_gray #(
parameter FIFO_DEPTH_BIT = 10'd4
) (
input w_clk,
r_clk,
input w_rst,
r_rst,
input [FIFO_DEPTH_BIT:0] write_addr_gray,
input [FIFO_DEPTH_BIT:0] read_addr_gray,
output reg [FIFO_DEPTH_BIT:0] write_addr_gray_sync,
output reg [FIFO_DEPTH_BIT:0] read_addr_gray_sync
);
reg [FIFO_DEPTH_BIT:0] write_addr_gray_sync_temp1, write_addr_gray_sync_temp2;
reg [FIFO_DEPTH_BIT:0] read_addr_gray_sync_temp1, read_addr_gray_sync_temp2;
always @(posedge w_clk or posedge w_rst) begin //write_addr_gary delay 2 clks
write_addr_gray_sync_temp1 <= write_addr_gray;
write_addr_gray_sync_temp2 <= write_addr_gray_sync_temp1;
write_addr_gray_sync <= write_addr_gray_sync_temp2;
end
always @(posedge r_clk or posedge r_rst) begin //write_addr_gary delay 2 clks
read_addr_gray_sync_temp1 <= read_addr_gray;
read_addr_gray_sync_temp2 <= read_addr_gray_sync_temp1;
read_addr_gray_sync <= read_addr_gray_sync_temp2;
end
endmodule
| 6.693009 |
module sync_adpll
(
refclk,
reset,
sync_stream,
out_bclk
);
parameter ACCUM_SIZE = 24;
parameter CLK_OVERSAMPLE_LOG2 = 4; // Clock oversample = 16
input refclk, reset, sync_stream;
output out_bclk;
// IO regs
reg out_bclk;
// Internal regs
reg [ACCUM_SIZE-1:0] accum;
reg [ACCUM_SIZE-1:0] freq_tuning_word;
// Reset synchroniser
reg reset_d, reset_dd;
always @(posedge refclk) reset_d <= reset;
always @(posedge refclk) reset_dd <= reset_d;
// Increment accumulator by FTW. We care more about frequency stability than relative phase.
always @(posedge refclk) begin
if (transition)
accum <= 0;
else
accum <= accum + freq_tuning_word;
end
// Detect transitions -- current input XOR previous input = 1; use a 3-stage synchronizer
// D-FF to reduce chance of metastability
reg in_d, in_dd, in_ddd, in_dddd;
always @(posedge refclk) begin
in_d <= sync_stream;
in_dd <= in_d;
in_ddd <= in_dd;
in_dddd <= in_ddd;
end
wire transition;
assign transition = in_dddd ^ in_ddd;
// Compare transition point with phase of the accumulator -- if the MSB of the accumulator is 1, increase FTW; otherwise, decrease FTW
always @(posedge refclk) begin
//if (reset_dd)
freq_tuning_word <= (2**ACCUM_SIZE-1)>>CLK_OVERSAMPLE_LOG2; // Works for a 200MHz clock (16x); 250MHz clock (20x) would require something else
//else if (transition)
// if (accum[ACCUM_SIZE-1]) // Increase FTW
// freq_tuning_word <= freq_tuning_word + 32'b1;
// else // Decrease FTW
// freq_tuning_word <= freq_tuning_word + (~32'b1 + 1); //2's complement subtraction
end
always @(posedge refclk) out_bclk <= accum[ACCUM_SIZE-1];
endmodule
| 7.403748 |
module sync_and_debounce_one #(
parameter depth = 8
) (
input clk,
input sw_in,
output reg sw_out
);
reg [depth - 1:0] cnt;
reg [ 2:0] sync;
wire sw_in_s;
assign sw_in_s = sync[2];
always @(posedge clk) sync <= {sync[1:0], sw_in};
always @(posedge clk)
if (sw_out ^ sw_in_s) cnt <= cnt + 1'b1;
else cnt <= {depth{1'b0}};
always @(posedge clk) if (cnt == {depth{1'b1}}) sw_out <= sw_in_s;
endmodule
| 7.085396 |
module sync_and_debounce #(
parameter w = 1,
depth = 8
) (
input clk,
input [w - 1:0] sw_in,
output [w - 1:0] sw_out
);
genvar sw_cnt;
generate
for (sw_cnt = 0; sw_cnt < w; sw_cnt = sw_cnt + 1) begin : gen_sync_and_debounce
sync_and_debounce_one #(
.depth(depth)
) i_sync_and_debounce_one (
.clk (clk),
.sw_in (sw_in[sw_cnt]),
.sw_out(sw_out[sw_cnt])
);
end
endgenerate
endmodule
| 7.085396 |
module sync_and_debounce_one #(
parameter depth = 8
) (
input clk,
input reset,
input sw_in,
output reg sw_out
);
reg [depth - 1:0] cnt;
reg [ 2:0] sync;
wire sw_in_s;
assign sw_in_s = sync[2];
always @(posedge clk or posedge reset)
if (reset) sync <= 3'b0;
else sync <= {sync[1:0], sw_in};
always @(posedge clk or posedge reset)
if (reset) cnt <= {depth{1'b0}};
else if (sw_out ^ sw_in_s) cnt <= cnt + 1'b1;
else cnt <= {depth{1'b0}};
always @(posedge clk or posedge reset)
if (reset) sw_out <= 1'b0;
else if (cnt == {depth{1'b1}}) sw_out <= sw_in_s;
endmodule
| 7.085396 |
module sync_async_reset (
input clock,
input reset_n,
input data_a,
input data_b,
output out_a,
output out_b
);
reg reg1, reg2;
reg reg3, reg4;
assign out_a = reg1;
assign out_b = reg2;
assign rst_n = reg4;
always @(posedge clock, negedge reset_n) begin
if (!reset_n) begin
reg3 <= 1'b0;
reg4 <= 1'b0;
end else begin
reg3 <= 1'b1;
reg4 <= reg3;
end
end
always @(posedge clock, negedge rst_n) begin
if (!rst_n) begin
reg1 <= 1'b0;
reg2 <= 1'b0;
end else begin
reg1 <= data_a;
reg2 <= data_b;
end
end
endmodule
| 6.677077 |
modules for Autonomous wrapper use
// Description : Clock crossing support for Autonomous
// This contains support for cross-clock-domain (CDC) synchronization
// as needed specifically for autonomous regs. This is basically
// only 4-phase handshakes
//
// ----------------------------------------------------------------------------
// Revision History
// ----------------------------------------------------------------------------
//
//
// ----------------------------------------------------------------------------
// Implementation details
// ----------------------------------------------------------------------------
// See the micro-arch spec and MIPI I3C spec
//
// This suppports the Clock Domain Crossing using named blocks
// so Spyglass (or equiv) can be told that the sync is here.
// For most modern process, the single flop model is fine, although
// the flop type may need to be changed by constraint for older
// process (e.g. a sync flop, which has a "gravity" to settle
// faster).
// 1 flop is fine in normal cases because the Q out metastable
// noise will be short enough in time for the paths used at the
// lower speeds. That is, there is ~40ns minimum to both settle
// and arrive settled at the other end.
// ----------------------------------------------------------------------------
// Note naming: SYNC_= synchronizing, 2PH_=2-phase, S2C_=SCL to CLK, STATE=state with clr in
// LVL_=level vs. pulse input, LVLH_=level high
// Other naming: ASet=async set, local clear, AClr=local set, async clear
// ASelfClr=local set and auto clear
// Seq2=2 flop sequencer to ensure we get 1 pulse in local domain
// Next is set local and clear async from SCL to CLK
module SYNC_AClr_S2C(
input SCL, // may be SCL_n
input RSTn,
input local_set,
input async_clear,
output o_value);
reg value; // SCL domain
always @ (posedge SCL or negedge RSTn)
if (!RSTn)
value <= 1'b0;
else if (local_set)
value <= 1'b1;
else if (async_clear) // CDC
value <= 1'b0;
assign o_value = value;
endmodule
| 8.776205 |
module SYNC_AClr_C2S (
input CLK, // system domain
input RSTn,
input local_set,
input async_clear,
output o_value
);
reg value; // CLK domain
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
value <= 1'b0;
assign o_value = value;
endmodule
| 6.822945 |
module SYNC_S2B #(
parameter WIDTH = 1
) (
input rst_n,
input clk,
input [WIDTH-1:0] scl_data,
output [WIDTH-1:0] out_clk // output copy in CLK domain
);
reg [WIDTH-1:0] clk_copy;
assign out_clk = clk_copy;
// note: could use clk_copy^scl_data as test to allow ICG
always @(posedge clk or negedge rst_n)
if (!rst_n) clk_copy <= {WIDTH{1'b0}};
else clk_copy <= scl_data;
endmodule
| 7.850005 |
module sync_axi2ddr_1bit (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [0:0] axi_data,
output wire [0:0] ddr_data
);
wire [0:0] ddr_stage1;
wire [0:0] ddr_stage2;
// axi data
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) axidata_0 (
.D (axi_data[0]),
.Q (ddr_stage1[0]),
.CE (1'b1),
.C (axi_clk),
.CLR(rst)
);
// ddr stage1
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) ddrdata1_0 (
.D (ddr_stage1[0]),
.Q (ddr_stage2[0]),
.CE (1'b1),
.C (ddr_clk),
.CLR(rst)
);
// ddr stage2
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) ddrdata2_0 (
.D (ddr_stage2[0]),
.Q (ddr_data[0]),
.CE (1'b1),
.C (ddr_clk),
.CLR(rst)
);
endmodule
| 8.11951 |
module sync_axi2ddr_nbit #(
parameter WIDTH = 32
) (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [WIDTH-1:0] axi_data,
output wire [WIDTH-1:0] ddr_data
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
sync_axi2ddr_1bit sync_axi2ddr_bits (
.rst(rst),
.axi_clk(axi_clk),
.ddr_clk(ddr_clk),
.axi_data(axi_data[i]),
.ddr_data(ddr_data[i])
);
end
endgenerate
endmodule
| 8.11951 |
module txtest (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output reg tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
//-- Pruebas del caso peor: a 300 baudios
parameter BAUD = 40000;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Señal de load registrada
reg load_r;
//-- Reloj para la transmision
wire clk_baud;
//-- Registrar la entrada load
//-- (para cumplir con las reglas de diseño sincrono)
always @(posedge clk) load_r <= load;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando load_r es 0, se carga la trama
//-- Cuando load_r es 1 y el reloj de baudios esta a 1 se desplaza hacia
//-- la derecha, enviando el siguiente bit
//-- Se introducen '1's por la izquierda
always @(posedge clk)
//-- Modo carga
if (load_r == 0)
shifter <= {"K", 2'b01};
//-- Modo desplazamiento
else if (load_r == 1 && clk_baud == 1) shifter <= {shifter[0], shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (load_r == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk) tx <= (load_r) ? shifter[0] : 1;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
endmodule
| 7.489425 |
module sync_bench;
parameter width = 16;
reg a_clk, a_reset;
reg b_clk, b_reset;
wire [width-1:0] a_data;
wire a_srdy, a_drdy;
wire b_srdy, b_drdy;
initial begin
`ifdef VCS
$vcdpluson;
`else
$dumpfile("sync.vcd");
$dumpvars;
`endif
a_clk = 0;
b_clk = 0;
a_reset = 1;
b_reset = 1;
#200;
a_reset = 0;
b_reset = 0;
#200;
seq_gen.send(25);
seq_gen.srdy_pat = 8'h01;
seq_gen.send(25);
seq_gen.srdy_pat = 8'hFF;
seq_chk.drdy_pat = 8'h01;
seq_gen.send(25);
seq_gen.srdy_pat = 8'h01;
seq_gen.send(25);
#2000;
if (seq_chk.last_seq == 100) $display("TEST PASSED");
else $display("TEST FAILED");
$finish;
end // initial begin
initial begin
#50000; // timeout value
$display("TEST FAILED");
$finish;
end
always a_clk = #5 ~a_clk;
always b_clk = #17 ~b_clk;
sd_seq_gen #(
.width(width)
) seq_gen (
.clk (a_clk),
.reset (a_reset),
.p_srdy(a_srdy),
.p_data(a_data),
// Inputs
.p_drdy(a_drdy)
);
sd_sync sync0 (
// Outputs
.c_drdy (a_drdy),
.p_srdy (b_srdy),
// Inputs
.c_clk (a_clk),
.c_reset(a_reset),
.c_srdy (a_srdy),
.p_clk (b_clk),
.p_reset(b_reset),
.p_drdy (b_drdy)
);
sd_seq_check #(
.width(width)
) seq_chk (
// Outputs
.c_drdy(b_drdy),
// Inputs
.clk (b_clk),
.reset (b_reset),
.c_srdy(b_srdy),
.c_data(a_data)
);
endmodule
| 6.86177 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
`timescale 1ns/100ps
module sync_bits #(
// Number of bits to synchronize
parameter NUM_OF_BITS = 1,
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1)(
input [NUM_OF_BITS-1:0] in_bits,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out_bits);
generate if (ASYNC_CLK == 1) begin
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in_bits;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out_bits = cdc_sync_stage2;
end else begin
assign out_bits = in_bits;
end endgenerate
endmodule
| 8.180735 |
module sync_cdc_bit #(
parameter integer C_SYNC_STAGES = 3
) (
input wire clk,
input wire d,
output wire q
);
xpm_cdc_single #(
.DEST_SYNC_FF(C_SYNC_STAGES), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0 ), // DECIMAL; 0 = disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0), // DECIMAL; 0 = disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG(0) // DECIMAL; 0 = do not register input, 1 = register input
) xpm_cdc_single_inst (
.src_clk(1'b0), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.dest_clk(clk), // 1-bit input: Clock signal for the destination clock domain.
.src_in(d), // 1-bit input: Input signal to be synchronized to dest_clk domain.
.dest_out ( q ) // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
);
endmodule
| 7.959215 |
module sync_cdc_bus #(
parameter integer C_SYNC_STAGES = 3,
parameter integer C_SYNC_WIDTH = 8
) (
input wire src_clk,
input wire [C_SYNC_WIDTH - 1 : 0] src_in,
input wire src_req,
output wire src_ack,
input wire dst_clk,
output wire [C_SYNC_WIDTH - 1 : 0] dst_out,
output wire dst_req,
input wire dst_ack
);
xpm_cdc_handshake #(
.DEST_EXT_HSK(1), // DECIMAL; 0 = internal handshake, 1 = external handshake
.DEST_SYNC_FF(C_SYNC_STAGES), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0 ), // DECIMAL; 0 = disable simulation init values, 1 = enable simulation init values
.SIM_ASSERT_CHK ( 0 ), // DECIMAL; 0 = disable simulation messages, 1 = enable simulation messages
.SRC_SYNC_FF(C_SYNC_STAGES), // DECIMAL; range: 2-10
.WIDTH(C_SYNC_WIDTH) // DECIMAL; range: 1-1024
) xpm_cdc_handshake_inst (
.src_clk (src_clk), // 1-bit input: Source clock.
.dest_clk(dst_clk), // 1-bit input: Destination clock.
.src_in ( src_in ), // WIDTH-bit input: Input bus that will be synchronized to the destination clock domain.
.dest_out ( dst_out ), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain. This output is registered.
.src_send ( src_req ), // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to
// the destination clock domain. This signal should only be asserted when src_rcv is
// deasserted, indicating that the previous data transfer is complete. This signal
// should only be deasserted once src_rcv is asserted, acknowledging that the src_in
// has been received by the destination logic.
.dest_req ( dst_req ), // 1-bit output: Assertion of this signal indicates that new dest_out data has been
// received and is ready to be used or captured by the destination logic. When
// DEST_EXT_HSK = 1, this signal will deassert once the source handshake
// acknowledges that the destination clock domain has received the transferred data.
// When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus
// is valid. This output is registered.
.src_rcv ( src_ack ), // 1-bit output: Acknowledgement from destination logic that src_in has been
// received. This signal will be deasserted once destination handshake has fully
// completed, thus completing a full data transfer. This output is registered.
.dest_ack(dst_ack) // 1-bit input: optional; required when DEST_EXT_HSK = 1
);
endmodule
| 8.114374 |
module sync_cell (
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
reg in_d1;
reg in_d2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
in_d1 <= 1'b0;
in_d2 <= 1'b0;
end else begin
in_d1 <= in;
in_d2 <= in_d1;
end
end
assign out = in_d2;
endmodule
| 6.838352 |
module sync_check (
pclk,
rst,
enable,
hsync,
vsync,
csync,
blanc,
hpol,
vpol,
cpol,
bpol,
thsync,
thgdel,
thgate,
thlen,
tvsync,
tvgdel,
tvgate,
tvlen
);
input pclk, rst, enable, hsync, vsync, csync, blanc;
input hpol, vpol, cpol, bpol;
input [7:0] thsync, thgdel;
input [15:0] thgate, thlen;
input [7:0] tvsync, tvgdel;
input [15:0] tvgate, tvlen;
time last_htime;
reg hvalid;
time htime;
time hhtime;
time last_vtime;
reg vvalid;
time vtime;
time vhtime;
wire [31:0] htime_exp;
wire [31:0] hhtime_exp;
wire [31:0] vtime_exp;
wire [31:0] vhtime_exp;
wire hcheck;
wire vcheck;
wire [31:0] bh_start;
wire [31:0] bh_end;
wire [31:0] bv_start;
wire [31:0] bv_end;
integer bdel1;
reg bval1;
reg bval;
integer bdel2;
wire bcheck;
//initial hvalid=0;
//initial vvalid=0;
parameter clk_time = 40;
assign hcheck = enable;
assign vcheck = enable;
assign hhtime_exp = (thsync + 1) * clk_time;
assign htime_exp = (thlen + 1) * clk_time;
assign vhtime_exp = (htime_exp * (tvsync + 1));
assign vtime_exp = htime_exp * (tvlen + 1);
always @(posedge pclk)
if (!rst | !enable) begin
hvalid = 0;
vvalid = 0;
end
// Verify HSYNC Timing
always @(hsync)
if (hcheck) begin
if (hsync == ~hpol) begin
htime = $time - last_htime;
//if(hvalid) $display("HSYNC length time: %0t", htime);
if (hvalid & (htime != htime_exp))
$display("HSYNC length ERROR: Expected: %0d Got: %0d (%0t)", htime_exp, htime, $time);
last_htime = $time;
hvalid = 1;
end
if (hsync == hpol) begin
hhtime = $time - last_htime;
//if(hvalid) $display("HSYNC pulse time: %0t", hhtime);
if (hvalid & (hhtime != hhtime_exp))
$display("HSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", hhtime_exp, hhtime, $time);
end
end
// Verify VSYNC Timing
always @(vsync)
if (vcheck) begin
if (vsync == ~vpol) begin
vtime = $time - last_vtime;
//if(vvalid) $display("VSYNC length time: %0t", vtime);
if (vvalid & (vtime != vtime_exp))
$display("VSYNC length ERROR: Expected: %0d Got: %0d (%0t)", vtime_exp, vtime, $time);
last_vtime = $time;
vvalid = 1;
end
if (vsync == vpol) begin
vhtime = $time - last_vtime;
//if(vvalid) $display("VSYNC pulse time: %0t", vhtime);
if (vvalid & (vhtime != vhtime_exp))
$display("VSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", vhtime_exp, vhtime, $time);
end
end
`ifdef VGA_12BIT_DVI
`else
// Verify BLANC Timing
//assign bv_start = tvsync + tvgdel + 2;
//assign bv_end = bv_start + tvgate + 2;
//assign bh_start = thsync + thgdel + 1;
//assign bh_end = bh_start + thgate + 2;
assign bv_start = tvsync + tvgdel + 1;
assign bv_end = bv_start + tvgate + 2;
assign bh_start = thsync + thgdel + 1;
assign bh_end = bh_start + thgate + 2;
assign bcheck = enable;
always @(vsync) if (vsync == ~vpol) bdel1 = 0;
always @(hsync) if (hsync == ~hpol) bdel1 = bdel1 + 1;
always @(bdel1) bval1 = (bdel1 > bv_start) & (bdel1 < bv_end);
always @(hsync) if (hsync == ~hpol) bdel2 = 0;
always @(posedge pclk) bdel2 = bdel2 + 1;
initial bval = 1;
always @(bdel2) bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end));
always @(bval or blanc)
#0.01
if (enable)
if (((blanc ^ bpol) != bval) & bcheck)
$display("BLANK ERROR: Expected: %0d Got: %0d (%0t)", bval, (blanc ^ bpol), $time);
// verify CSYNC
always @(csync or vsync or hsync)
if (enable)
if ((csync ^ cpol) != ((vsync ^ vpol) | (hsync ^ hpol)))
$display(
"CSYNC ERROR: Expected: %0d Got: %0d (%0t)",
((vsync ^ vpol) | (hsync ^ hpol)),
(csync ^ cpol),
$time
);
`endif
endmodule
| 7.543711 |
module sync_clk_core ( /*AUTOARG*/
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
//input ctrl_tx_disable_padding;
//output ctrl_tx_disable_padding_ccr;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
//wire [0:0] sig_out;
//assign {ctrl_tx_disable_padding_ccr} = sig_out;
//meta_sync #(.DWIDTH (1)) meta_sync0 (
// // Outputs
// .out (sig_out),
// // Inputs
// .clk (clk_xgmii_tx),
// .reset_n (reset_xgmii_tx_n),
// .in ({
// ctrl_tx_disable_padding
// }));
endmodule
| 6.713529 |
module sync_clk_wb ( /*AUTOARG*/
// Outputs
status_crc_error,
status_fragment_error,
status_txdfifo_ovflow,
status_txdfifo_udflow,
status_rxdfifo_ovflow,
status_rxdfifo_udflow,
status_pause_frame_rx,
status_local_fault,
status_remote_fault,
// Inputs
wb_clk_i,
wb_rst_i,
status_crc_error_tog,
status_fragment_error_tog,
status_txdfifo_ovflow_tog,
status_txdfifo_udflow_tog,
status_rxdfifo_ovflow_tog,
status_rxdfifo_udflow_tog,
status_pause_frame_rx_tog,
status_local_fault_crx,
status_remote_fault_crx
);
input wb_clk_i;
input wb_rst_i;
input status_crc_error_tog;
input status_fragment_error_tog;
input status_txdfifo_ovflow_tog;
input status_txdfifo_udflow_tog;
input status_rxdfifo_ovflow_tog;
input status_rxdfifo_udflow_tog;
input status_pause_frame_rx_tog;
input status_local_fault_crx;
input status_remote_fault_crx;
output status_crc_error;
output status_fragment_error;
output status_txdfifo_ovflow;
output status_txdfifo_udflow;
output status_rxdfifo_ovflow;
output status_rxdfifo_udflow;
output status_pause_frame_rx;
output status_local_fault;
output status_remote_fault;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire [6:0] sig_out1;
wire [1:0] sig_out2;
assign {status_crc_error,
status_fragment_error,
status_txdfifo_ovflow,
status_txdfifo_udflow,
status_rxdfifo_ovflow,
status_rxdfifo_udflow,
status_pause_frame_rx} = sig_out1;
assign {status_local_fault, status_remote_fault} = sig_out2;
meta_sync #(
.DWIDTH(7),
.EDGE_DETECT(1)
) meta_sync0 (
// Outputs
.out(sig_out1),
// Inputs
.clk(wb_clk_i),
.reset_n(~wb_rst_i),
.in({
status_crc_error_tog,
status_fragment_error_tog,
status_txdfifo_ovflow_tog,
status_txdfifo_udflow_tog,
status_rxdfifo_ovflow_tog,
status_rxdfifo_udflow_tog,
status_pause_frame_rx_tog
})
);
meta_sync #(
.DWIDTH(2),
.EDGE_DETECT(0)
) meta_sync1 (
// Outputs
.out (sig_out2),
// Inputs
.clk (wb_clk_i),
.reset_n(~wb_rst_i),
.in ({status_local_fault_crx, status_remote_fault_crx})
);
endmodule
| 6.854147 |
module sync_clk_xgmii_tx ( /*AUTOARG*/
// Outputs
ctrl_tx_enable_ctx,
status_local_fault_ctx,
status_remote_fault_ctx,
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n,
ctrl_tx_enable,
status_local_fault_crx,
status_remote_fault_crx
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input ctrl_tx_enable;
input status_local_fault_crx;
input status_remote_fault_crx;
output ctrl_tx_enable_ctx;
output status_local_fault_ctx;
output status_remote_fault_ctx;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire [2:0] sig_out;
assign {ctrl_tx_enable_ctx, status_local_fault_ctx, status_remote_fault_ctx} = sig_out;
meta_sync #(
.DWIDTH(3)
) meta_sync0 (
// Outputs
.out (sig_out),
// Inputs
.clk (clk_xgmii_tx),
.reset_n(reset_xgmii_tx_n),
.in ({ctrl_tx_enable, status_local_fault_crx, status_remote_fault_crx})
);
endmodule
| 7.832497 |
module name - clock_output_control
// Version: COC_V1.0.0_20211202
// Created:
// by - fenglin
// at - 12.2021
////////////////////////////////////////////////////////////////////////////
// Description:
// clock_output_control
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sync_clock_control(
i_sync_clk,
i_sim_ctrl,
o_sync_clk
);
// I/O
//input
input i_sync_clk ;
input i_sim_ctrl ;
//output
output o_sync_clk ;
assign o_sync_clk = !i_sim_ctrl ? i_sync_clk:1'b0;
endmodule
| 8.290552 |
module syn_control (
input clk_50m,
input cfg_rst,
input lose,
input corase_syn_en,
input fine_syn_en,
input slot_interrupt,
input [31:0] corase_syn_pos,
input [31:0] fine_syn_pos,
output [31:0] corase_pos,
output [31:0] fine_pos,
output reg send40k_en,
output reg send10k_en,
input data_send_end,
input [15:0] wr_addr_out,
output [255:0] debug
);
assign corase_pos = corase_pos_reg;
assign fine_pos = fine_pos_reg;
reg [ 3:0] syn_state;
reg [31:0] fine_pos_reg;
reg [31:0] corase_pos_reg;
always @(posedge clk_50m or posedge cfg_rst) begin
if (cfg_rst) begin
syn_state <= 4'd0;
fine_pos_reg <= 32'd0;
corase_pos_reg <= 32'd0;
send40k_en <= 1'b0;
send10k_en <= 1'b0;
end else begin
case (syn_state)
4'd0: begin
if (lose) begin
send40k_en <= 1'b0;
send10k_en <= 1'b0;
end else if (corase_syn_en) begin
syn_state <= 4'd1;
end else if (fine_syn_en) begin
syn_state <= 4'd2;
send40k_en <= 1'b0;
send10k_en <= 1'b1;
end else if (data_send_end) begin
syn_state <= 4'd0;
send10k_en <= 1'b0;
send40k_en <= 1'b1;
end else begin
send10k_en <= send10k_en;
send40k_en <= send40k_en;
syn_state <= 4'd0;
end
end
4'd1: begin
if (slot_interrupt) begin
corase_pos_reg <= corase_syn_pos;
send40k_en <= 1'b1;
syn_state <= 4'd0;
end else begin
syn_state <= 1'b1;
end
end
4'd2: begin
syn_state <= 4'd0;
if (fine_syn_pos == 32'd0) begin
fine_pos_reg <= 32'd0;
end else begin
fine_pos_reg <= fine_syn_pos;
end
end
default: begin
syn_state <= 4'd0;
end
endcase
end
end
assign debug[0] = corase_syn_en;
assign debug[1] = fine_syn_en;
assign debug[33:2] = corase_syn_pos;
assign debug[65:34] = fine_syn_pos;
assign debug[97:66] = corase_pos;
assign debug[129:98] = fine_pos;
assign debug[130] = send40k_en;
assign debug[131] = send10k_en;
assign debug[135:132] = syn_state;
assign debug[136] = lose;
assign debug[137] = data_send_end;
assign debug[255:138] = 0;
endmodule
| 6.86222 |
module sync_control_dual #(
parameter DATA_WIDTH = 32,
max_steps = 7
) (
input clk,
input finished1,
input finished2,
input rst, // a reset flag that reset all operations; after lap > max_steps, rst needs to be set high by PS to reset everything
output rdy1,
output rdy2, //
output reg finished_all,
output [DATA_WIDTH-1:0] l_step //
);
reg [DATA_WIDTH-1:0] l_step_reg = 0;
assign l_step = (rst == 1'b0) ? l_step_reg : {(DATA_WIDTH) {1'b0}};
assign rdy1 = (rst == 1'b0) ? (~((finished1 & finished2) ^ finished1)) : {1'b0};
assign rdy2 = (rst == 1'b0) ? (~((finished1 & finished2) ^ finished2)) : {1'b0};
//assign finished_all = finished1 & finished2;
always @(posedge clk) begin // need to double check if it should be posedge or negedge
if (rst == 1'b0 && finished1 == 1'b1 && finished2 == 1'b1 && l_step_reg < max_steps) begin
l_step_reg = l_step_reg + 1;
end
finished_all <= finished1 & finished2;
//if (l_step_reg == max_steps) begin
// l_step_reg = 0;
//end
end
endmodule
| 8.153933 |
module sync_control_dual_tb #(
parameter period = 10,
DATA_WIDTH = 32,
max_steps = 7
) ();
integer i, j;
reg clk, finished1, finished2, rst;
wire [DATA_WIDTH-1:0] l_step;
sync_control_dual #(
.DATA_WIDTH(DATA_WIDTH),
.max_steps (max_steps)
) lap_control (
.clk(clk),
.finished1(finished1),
.finished2(finished2),
.rst(rst), // a reset flag that reset all operations; after lap > max_steps, rst needs to be set high by PS to reset everything
.rdy1 (rdy1),
.rdy2 (rdy2), //
.l_step(l_step) //
);
initial begin
clk = 0;
for (i = 1; i < 100; i = i + 1) begin
#(period / 2) clk = ~clk;
end
end
initial begin
rst = 0;
for (j = 0; j < 10; j = j + 1) begin
finished1 = 0;
finished2 = 0;
#period;
finished1 = 1;
#period;
finished2 = 1;
#period;
end
end
initial begin
#(period * 100) rst = 1;
end
endmodule
| 8.153933 |
module that needs to keep track of which Row/Col
// position we are on in the middile of frame
////////////////////////////////////////////////////////////////////////////////
module sync_count
(
input i_clk,
input i_hsync,
input i_vsync,
output reg o_hsync,
output reg o_vsync,
output reg [9:0] o_col_count = 0,
output reg [9:0] o_row_count = 0
);
//Parameter Needed For producing horizontal and veritical sync
parameter TOTAL_COLS = 800;
parameter TOTAL_ROWS = 525;
wire w_frame_start;
//Registers syncs to align with the output data
always @(posedge i_clk) begin
o_vsync <= i_vsync;
o_hsync <= i_hsync;
end
//Keep the track of Row and column counters
always @(posedge i_clk) begin
if ( w_frame_start == 1'b1) begin
o_col_count <= 0;
o_row_count <= 0;
end
else begin
if ( o_col_count == (TOTAL_COLS - 1)) begin
o_col_count<= 0;
if ( o_row_count == (TOTAL_ROWS - 1) )
o_row_count<= 0;
else
o_row_count <= o_row_count + 1;
end
else begin
o_col_count<= o_col_count + 1;
end
end
end
//Look for rising edge on Vertical Sync to reset the counters
assign w_frame_start = (~o_vsync & i_vsync);
endmodule
| 7.477982 |
module Sync_counter_32bit (
out,
clock,
clear_bar,
count_en
);
output [31:0] out;
input clock, count_en, clear_bar;
Sync_counter_4bit C0 (
.out(out[3:0]),
.and_out(aout0),
.clock(clock),
.clear_bar(clear_bar),
.count_en(count_en)
);
and_2_GT6100 C0A (
ce1,
aout0,
out[3]
);
Sync_counter_4bit C1 (
.out(out[7:4]),
.and_out(aout1),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce1)
);
and_2_GT6100 C1A (
ce2,
aout1,
out[7]
);
Sync_counter_4bit C2 (
.out(out[11:8]),
.and_out(aout2),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce2)
);
and_2_GT6100 C2A (
ce3,
aout2,
out[11]
);
Sync_counter_4bit C3 (
.out(out[15:12]),
.and_out(aout3),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce3)
);
and_2_GT6100 C3A (
ce4,
aout3,
out[15]
);
Sync_counter_4bit C4 (
.out(out[19:16]),
.and_out(aout4),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce4)
);
and_2_GT6100 C4A (
ce5,
aout4,
out[19]
);
Sync_counter_4bit C5 (
.out(out[23:20]),
.and_out(aout5),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce5)
);
and_2_GT6100 C5A (
ce6,
aout5,
out[23]
);
Sync_counter_4bit C6 (
.out(out[27:24]),
.and_out(aout6),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce6)
);
and_2_GT6100 C6A (
ce7,
aout6,
out[27]
);
Sync_counter_4bit C7 (
.out(out[31:28]),
.and_out(not_used),
.clock(clock),
.clear_bar(clear_bar),
.count_en(ce7)
);
endmodule
| 6.642277 |
module Sync_counter_4bit (
out,
and_out,
clock,
clear_bar,
count_en
);
output [3:0] out;
output and_out;
input clock, count_en, clear_bar;
Toggle_FF_GT6100 T0 (
.out(out[0]),
.en(count_en),
.clear_bar(clear_bar),
.clock(clock)
);
Toggle_FF_GT6100 T1 (
.out(out[1]),
.en(a0),
.clear_bar(clear_bar),
.clock(clock)
);
Toggle_FF_GT6100 T2 (
.out(out[2]),
.en(a1),
.clear_bar(clear_bar),
.clock(clock)
);
Toggle_FF_GT6100 T3 (
.out(out[3]),
.en(and_out),
.clear_bar(clear_bar),
.clock(clock)
);
and_2_GT6100
A0 (
a0,
count_en,
out[0]
),
A1 (
a1,
a0,
out[1]
),
A2 (
and_out,
a1,
out[2]
);
endmodule
| 6.642277 |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [9:0] o_cnt_dat;
sync_counter cnt_inst (
.CLOCK_50(i_clk),
.KEY({i_rst_n, 1'b0}),
.LEDR(o_cnt_dat)
);
initial begin
i_clk = 0;
forever #(PERIOD / 2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (2000) @(negedge i_clk);
$finish;
end
endmodule
| 7.015571 |
module sync_cs_dev (
clk,
addr,
dq,
cs_,
we_,
oe_,
ack_
);
input clk;
input [15:0] addr;
inout [31:0] dq;
input cs_, we_, oe_;
output ack_;
reg [31:0] data_o;
reg [31:0] mem[0:1024];
wire rd, wr;
integer rd_del;
reg [31:0] rd_r;
wire rd_d;
integer wr_del;
reg [31:0] wr_r;
wire wr_d;
integer ack_del;
reg [31:0] ack_r;
wire ack_d;
initial ack_del = 2;
initial rd_del = 7;
initial wr_del = 3;
task mem_fill;
integer n;
begin
for (n = 0; n < 1024; n = n + 1) mem[n] = $random;
end
endtask
assign dq = rd_d ? data_o : 32'hzzzz_zzzz;
assign rd = ~cs_ & we_ & ~oe_;
assign wr = ~cs_ & ~we_;
always @(posedge clk)
if (~rd) rd_r <= #1 0;
else rd_r <= #1{rd_r[30:0], rd};
assign rd_d = rd_r[rd_del] & rd;
always @(posedge clk)
if (~wr) wr_r <= #1 0;
else wr_r <= #1{wr_r[30:0], wr};
assign wr_d = wr_r[wr_del] & wr;
always @(posedge clk) data_o <= #1 mem[addr[9:0]];
always @(posedge clk) if (wr_d) mem[addr[9:0]] <= #1 dq;
assign ack_d = rd | wr;
always @(posedge clk)
if (~rd & ~wr) ack_r <= #1 0;
else ack_r <= #1{ack_r[30:0], ack_d};
assign ack_ = ack_r[ack_del] & ack_d;
endmodule
| 6.681558 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_data #(
parameter NUM_OF_BITS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_BITS-1:0] in_data,
input out_clk,
output reg [NUM_OF_BITS-1:0] out_data
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
reg [NUM_OF_BITS-1:0] cdc_hold;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_load = in_toggle == in_toggle_d1;
wire out_load = out_toggle ^ out_toggle_d1;
always @(posedge in_clk) begin
if (in_load == 1'b1) begin
cdc_hold <= in_data;
in_toggle_d1 <= ~in_toggle_d1;
end
end
always @(posedge out_clk) begin
if (out_load == 1'b1) begin
out_data <= cdc_hold;
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_data <= in_data;
end
end
endgenerate
endmodule
| 8.180735 |
module sync_ddr2axi_1bit (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [0:0] ddr_data,
output wire [0:0] axi_data
);
wire [0:0] axi_stage1;
wire [0:0] axi_stage2;
// ddr data
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) ddrdata_0 (
.D (ddr_data[0]),
.Q (axi_stage1[0]),
.CE (1'b1),
.C (ddr_clk),
.CLR(rst)
);
// axi stage1
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) axidata1_0 (
.D (axi_stage1[0]),
.Q (axi_stage2[0]),
.CE (1'b1),
.C (axi_clk),
.CLR(rst)
);
// axi stage2
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) axidata2_0 (
.D (axi_stage2[0]),
.Q (axi_data[0]),
.CE (1'b1),
.C (axi_clk),
.CLR(rst)
);
endmodule
| 8.149816 |
module sync_ddr2axi_nbit #(
parameter WIDTH = 4
) (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [WIDTH-1:0] ddr_data,
output wire [WIDTH-1:0] axi_data
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
sync_ddr2axi_1bit sync_ddr2axi_bits (
.rst(rst),
.axi_clk(axi_clk),
.ddr_clk(ddr_clk),
.ddr_data(ddr_data[i]),
.axi_data(axi_data[i])
);
end
endgenerate
endmodule
| 8.149816 |
module sync_dd_c (
input wire clk,
input wire reset_,
input wire sync_in,
output wire sync_out
);
reg sync_in_p1;
reg sync_in_p2;
always @(posedge clk) begin
if (!reset_) begin
sync_in_p1 <= 1'b0;
sync_in_p2 <= 1'b0;
end else begin
sync_in_p1 <= sync_in;
sync_in_p2 <= sync_in_p1;
end
end
assign sync_out = sync_in_p2;
endmodule
| 7.332177 |
module sync_debouncer_10ms (
// OUTPUTs
signal_debounced, // Synchronized and 10ms debounced signal
// INPUTs
clk_50mhz, // 50MHz clock
rst, // reset
signal_async // Asynchonous signal
);
// OUTPUTs
//=========
output signal_debounced; // Synchronized and 10ms debounced signal
// INPUTs
//=========
input clk_50mhz; // 50MHz clock
input rst; // reset
input signal_async; // Asynchonous signal
// Synchronize signal
reg [1:0] sync_stage;
always @(posedge clk_50mhz or posedge rst)
if (rst) sync_stage <= 2'b00;
else sync_stage <= {sync_stage[0], signal_async};
wire signal_sync = sync_stage[1];
// Debouncer (10.48ms = 0x7ffff x 50MHz clock cycles)
reg [18:0] debounce_counter;
always @(posedge clk_50mhz or posedge rst)
if (rst) debounce_counter <= 19'h00000;
else if (signal_debounced == signal_sync) debounce_counter <= 19'h00000;
else debounce_counter <= debounce_counter + 1;
wire debounce_counter_done = (debounce_counter == 19'h7ffff);
// Output signal
reg signal_debounced;
always @(posedge clk_50mhz or posedge rst)
if (rst) signal_debounced <= 1'b0;
else if (debounce_counter_done) signal_debounced <= ~signal_debounced;
endmodule
| 6.58024 |
module sync_delay #(
//=============
// parameters
//=============
parameter DATA_WIDTH = 32,
parameter DELAY_CYCLES = 1
) (
//=====================
// input/output ports
//=====================
input clk,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout,
output dvalid
);
// set the size of count to the max bit width required
reg [DELAY_CYCLES-1:0] count = 0;
reg [ DATA_WIDTH-1:0] data_in;
reg [ DATA_WIDTH-1:0] data_out;
// increment counter and set the data out to the data in
// when count = DELAY_CYCLES
always @(posedge clk) begin
count <= count + 1;
if (count == 0) begin
data_in <= din;
end else begin
if (count == DELAY_CYCLES) begin
data_out <= data_in;
count <= 0;
end // else begin
end
end
// assign output to output reg
assign dout = data_out;
endmodule
| 6.888122 |
module sync_dp_ram #(
parameter ADDR_WIDTH = 8, // address's width
parameter DATA_WIDTH = 8 // data's width
) (
input clk, // systems's clock
input cen_0, // chip select, port 0, low active
input wen_0, // write enable, port 0, low active
input [ADDR_WIDTH-1:0] a_0, // address, port 0
input [DATA_WIDTH-1:0] d_0, // data in, port 0
output reg [DATA_WIDTH-1:0] q_0, // data out, port 0
input cen_1, // chip select, port 1, low active
input wen_1, // write enable, port 1, low active
input [ADDR_WIDTH-1:0] a_1, // address, port 1
input [DATA_WIDTH-1:0] d_1, // data in, port 1
output reg [DATA_WIDTH-1:0] q_1 // data out, port 1
);
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//reg [DATA_WIDTH-1:0] q_0_reg, q_1_reg;
reg [DATA_WIDTH-1:0] ram[RAM_DEPTH-1:0];
always @(posedge clk) begin : WRITE_IN
if (cen_0 == 0 && wen_0 == 0) begin
ram[a_0] <= d_0;
end else if (cen_1 == 0 && wen_1 == 0) begin
ram[a_1] <= d_1;
end
end
always @(posedge clk) begin : READ_0
if (cen_0 == 0 && wen_0 == 1) q_0 <= ram[a_0];
else q_0 <= 'b0;
end
always @(posedge clk) begin : READ_1
if (cen_1 == 0 && wen_1 == 1) q_1 <= ram[a_1];
else q_1 <= 'b0;
end
endmodule
| 8.376729 |
module
KEYWORDS: dual clock, sync
MODIFICATION HISTORY:
$Log$
Xudong 18/6/20 original version
\*-------------------------------------------------------------------------*/
module sync_dual_clock
#(
parameter WIDTH = 6, // 带同步的数据宽度
parameter SYNC_STAGE = 2 // 同步的级数（级数越多，竞争冒险越少）
)
(
input wire clock_dst,
input wire [WIDTH-1:0] src,
output wire [WIDTH-1:0] dst
);
//
reg [WIDTH-1:0] sync_reg [0:SYNC_STAGE-1];
integer p;
always @(posedge clock_dst)
begin
sync_reg[0] <= src;
for(p=1; p<SYNC_STAGE; p=p+1)
sync_reg[p] <= sync_reg[p-1];
end
assign dst = sync_reg[SYNC_STAGE-1]; // 输出
endmodule
| 7.592673 |
module sync_dual_port_ram #(
parameter ADDRESS_WIDTH = 4, // number of words in ram
DATA_WIDTH = 4 // number of bits in word
)
// IO ports
(
input wire clk, // clk for synchronous read/write
input wire write_en, // signal to enable synchronous write
input wire [ADDRESS_WIDTH-1:0] read_address,
write_address, // inputs for dual port addresses
input wire [ DATA_WIDTH-1:0] write_data_in, // input for data to write to ram
output wire [ DATA_WIDTH-1:0] read_data_out,
write_data_out // outputs for dual data ports
);
// internal signal declarations
reg [DATA_WIDTH-1:0] ram[2**ADDRESS_WIDTH-1:0]; // ADDRESS_WIDTH x DATA_WIDTH RAM declaration
reg [ADDRESS_WIDTH-1:0] read_address_reg, write_address_reg; // dual port address declarations
// synchronous write and address update
always @(posedge clk) begin
if (write_en) // if write enabled
ram[write_address] <= write_data_in; // write data to ram and write_address
read_address_reg <= read_address; // store read_address to reg
write_address_reg <= write_address; // store write_address to reg
end
// assignments for two data out ports
assign read_data_out = ram[read_address_reg];
assign write_data_out = ram[write_address_reg];
endmodule
| 9.050225 |
module sync_edge (
input clk,
rst_n,
sig,
output rise_edge,
fall_edge,
sig_edge
);
reg sig_r;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sig_r <= 0;
else sig_r <= sig;
end
assign rise_edge = sig & !sig_r;
assign fall_edge = !sig & sig_r;
assign sig_edge = sig ^ sig_r;
endmodule
| 6.90187 |
module sync_edge_detect (
input async_sig,
output sync_out,
input clk,
output reg rise,
output reg fall
);
reg [1:3] resync;
always @(posedge clk) begin
// detect rising and falling edges.
rise <= ~resync[3] & resync[2];
fall <= ~resync[2] & resync[3];
// update history shifter.
resync <= {async_sig, resync[1:2]};
end
assign sync_out = resync[2];
endmodule
| 6.898603 |
module sync_edge_detect_tb ();
reg t_clk;
reg t_rst_n;
reg t_d;
wire t_flag;
sync_edge_detect dut (
.clock(t_clk),
.rst_n(t_rst_n),
.din (t_d),
.flag (t_flag)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_rst_n = 1;
#8;
t_rst_n = 0;
#15;
t_rst_n = 1;
end
//Control signal
initial begin
t_d = 0;
#15 t_d = 1;
#25 t_d = 0;
#25 t_d = 1;
#25 t_d = 0;
#30 t_d = 1;
#20 $finish;
end
endmodule
| 6.898603 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_event #(
parameter NUM_OF_EVENTS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_EVENTS-1:0] in_event,
input out_clk,
output reg [NUM_OF_EVENTS-1:0] out_event
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_ready = in_toggle == in_toggle_d1;
wire load_out = out_toggle ^ out_toggle_d1;
reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
wire [NUM_OF_EVENTS-1:0] out_event_s;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
if (|pending_events == 1'b1) begin
in_toggle_d1 <= ~in_toggle_d1;
end
end else begin
in_event_sticky <= pending_events;
end
end
if (NUM_OF_EVENTS > 1) begin
reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
cdc_hold <= pending_events;
end
end
assign out_event_s = cdc_hold;
end else begin
// When there is only one event, we know that it is set.
assign out_event_s = 1'b1;
end
always @(posedge out_clk) begin
if (load_out == 1'b1) begin
out_event <= out_event_s;
end else begin
out_event <= {NUM_OF_EVENTS{1'b0}};
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_event <= in_event;
end
end
endgenerate
endmodule
| 8.180735 |
module sync_fifo_32 (
clk,
rst,
read_req,
write_data,
write_enable,
read_data,
fifo_empty,
rdata_valid
);
input clk;
input rst;
input read_req;
input [31:0] write_data;
input write_enable;
output [31:0] read_data;
output fifo_empty;
output rdata_valid;
reg [4:0] read_ptr;
reg [4:0] write_ptr;
reg [31:0] mem[0:15];
reg [31:0] read_data;
reg rdata_valid;
wire [3:0] write_addr = write_ptr[3:0];
wire [3:0] read_addr = read_ptr[3:0];
wire read_enable = read_req && (~fifo_empty);
assign fifo_empty = (read_ptr == write_ptr);
always @(posedge clk) begin
if (rst) write_ptr <= {(5) {1'b0}};
else if (write_enable) write_ptr <= write_ptr + {{4{1'b0}}, 1'b1};
end
always @(posedge clk) begin
if (rst) rdata_valid <= 1'b0;
else if (read_enable) rdata_valid <= 1'b1;
else rdata_valid <= 1'b0;
end
always @(posedge clk) begin
if (rst) read_ptr <= {(5) {1'b0}};
else if (read_enable) read_ptr <= read_ptr + {{4{1'b0}}, 1'b1};
end
// Mem write
always @(posedge clk) begin
if (write_enable) mem[write_addr] <= write_data;
end
// Mem Read
always @(posedge clk) begin
if (read_enable) read_data <= mem[read_addr];
end
endmodule
| 7.237888 |
module. */
`timescale 1ns / 100ps
module sync_fifo_ff (clk, rst, read_req, write_data, write_enable, rollover_write,
read_data, fifo_empty, rdata_valid);
input clk;
input rst;
input read_req;
input [90:0] write_data;
input write_enable;
input rollover_write;
output [90:0] read_data;
output fifo_empty;
output rdata_valid;
reg [4:0] read_ptr;
reg [4:0] write_ptr;
reg [90:0] mem [0:15];
reg [90:0] read_data;
reg rdata_valid;
wire [3:0] write_addr = write_ptr[3:0];
wire [3:0] read_addr = read_ptr[3:0];
wire read_enable = read_req && (~fifo_empty);
assign fifo_empty = (read_ptr == write_ptr);
always @(posedge clk)
begin
if (rst)
write_ptr <= {(5){1'b0}};
else if (write_enable & !rollover_write)
write_ptr <= write_ptr + {{4{1'b0}},1'b1};
else if (write_enable & rollover_write)
write_ptr <= write_ptr + 5'b00010;
// A rollover_write means that there have been a total of 4 FF's
// that have been detected in the bitstream. So an extra set of 32
// bits will be put into the bitstream (due to the 4 extra 00's added
// after the 4 FF's), and the input data will have to
// be delayed by 1 clock cycle as it makes its way into the output
// bitstream. So the write_ptr is incremented by 2 for a rollover, giving
// the output the extra clock cycle it needs to write the
// extra 32 bits to the bitstream. The output
// will read the dummy data from the FIFO, but won't do anything with it,
// it will be putting the extra set of 32 bits into the bitstream on that
// clock cycle.
end
always @(posedge clk)
begin
if (rst)
rdata_valid <= 1'b0;
else if (read_enable)
rdata_valid <= 1'b1;
else
rdata_valid <= 1'b0;
end
always @(posedge clk)
begin
if (rst)
read_ptr <= {(5){1'b0}};
else if (read_enable)
read_ptr <= read_ptr + {{4{1'b0}},1'b1};
end
// Mem write
always @(posedge clk)
begin
if (write_enable)
mem[write_addr] <= write_data;
end
// Mem Read
always @(posedge clk)
begin
if (read_enable)
read_data <= mem[read_addr];
end
endmodule
| 6.895322 |
module sync_fifo_in #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4
) (
input wire clk_i,
input wire resetn_i,
input wire fifo_write_en_h_i,
input wire [DATA_WIDTH-1:0] fifo_write_data_i,
output reg fifo_full_h_o,
input wire [ ADDR_WIDTH:0] read_addr_i,
output wire [ ADDR_WIDTH:0] write_addr_o,
output wire [DATA_WIDTH-1:0] read_data_o
);
localparam DEPTH = (1 << ADDR_WIDTH);
wire [ADDR_WIDTH:0] rd_ptr;
reg [ADDR_WIDTH:0] wr_ptr;
wire [ADDR_WIDTH-1:0] waddr;
wire [ADDR_WIDTH-1:0] raddr;
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
assign waddr = wr_ptr[ADDR_WIDTH-1:0];
assign raddr = read_addr_i[ADDR_WIDTH-1:0];
assign write_addr_o = wr_ptr;
assign rd_ptr = read_addr_i[ADDR_WIDTH:0];
always @(posedge clk_i or negedge resetn_i) begin
if (resetn_i == 1'b0) begin
wr_ptr <= 'h0;
end else if (fifo_write_en_h_i & (~fifo_full_h_o)) begin
wr_ptr <= wr_ptr + {{ADDR_WIDTH{1'b0}}, 1'b1};
end
end
always @(rd_ptr or wr_ptr) begin
fifo_full_h_o = 1'b0;
if ((rd_ptr[ADDR_WIDTH-1:0] == wr_ptr[ADDR_WIDTH-1:0]) &&
(rd_ptr[ADDR_WIDTH] != wr_ptr[ADDR_WIDTH])) begin
fifo_full_h_o = 1'b1;
end
end
always @(posedge clk_i) begin
if (fifo_write_en_h_i && (~fifo_full_h_o)) begin
mem[waddr] <= fifo_write_data_i;
end
end
assign read_data_o = mem[raddr];
endmodule
| 8.009897 |
module sync_fifo_out #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4
) (
input wire clk_i,
input wire resetn_i,
input wire [ ADDR_WIDTH:0] write_addr_i,
output wire [ ADDR_WIDTH:0] read_addr_o,
input wire [DATA_WIDTH-1:0] read_data_i,
input wire fifo_read_en_h_i,
output wire [DATA_WIDTH-1:0] fifo_read_data_o,
output reg fifo_empty_h_o
);
localparam DEPTH = (1 << ADDR_WIDTH);
wire [ADDR_WIDTH:0] wr_ptr;
reg [ADDR_WIDTH:0] rd_ptr;
assign wr_ptr = write_addr_i;
assign read_addr_o = rd_ptr;
always @(posedge clk_i or negedge resetn_i) begin
if (resetn_i == 1'b0) begin
rd_ptr <= 'h0;
end else if (fifo_read_en_h_i & (~fifo_empty_h_o)) begin
rd_ptr <= rd_ptr + {{ADDR_WIDTH{1'b0}}, 1'b1};
end
end
always @(rd_ptr or wr_ptr) begin
fifo_empty_h_o = 1'b0;
if ((rd_ptr[ADDR_WIDTH-1:0] == wr_ptr[ADDR_WIDTH-1:0]) &&
(rd_ptr[ADDR_WIDTH] == wr_ptr[ADDR_WIDTH])) begin
fifo_empty_h_o = 1'b1;
end
end
assign fifo_read_data_o = read_data_i;
endmodule
| 8.730267 |
module sync_fifo_sim ();
reg clk;
reg rst_n;
reg [31:0] counter_w;
wire [31:0] rdata;
reg [31:0] counter_r;
reg w_req;
reg r_req;
wire full;
wire empty;
initial begin
clk <= 0;
rst_n <= 0;
w_req <= 0;
r_req <= 0;
counter_w <= 0;
counter_r <= 0;
#100 rst_n <= 1;
#200 w_req = 1;
#200 r_req = 1;
#200 w_req = 0;
#200 w_req = 1;
#200 r_req = 0;
end
always #10 clk = ~clk;
syc_fifo syc_fifo_inst (
.clk (clk),
.rst_n(rst_n),
.w_req(w_req),
.wdata(counter_w),
.full (full),
.rdata(rdata),
.r_req(r_req),
.empty(empty)
);
always @(posedge clk) begin
if (!rst_n) begin
counter_w <= 0;
end else if (w_req && !full) begin
counter_w <= counter_w + 1;
end
end
always @(posedge clk) begin
if (!rst_n) begin
counter_r <= 0;
end else if (r_req && !empty) begin
counter_r <= rdata;
end
end
endmodule
| 7.300378 |
module sync_fifo_tb;
localparam FIFO_WIDTH = 32;
localparam FIFO_DEPTH = 8;
localparam ADDR_WIDTH = 3;
reg clk;
reg rst_n;
reg wr_en;
reg [FIFO_WIDTH-1:0] wr_data;
reg rd_en;
wire full;
wire wr_err;
wire empty;
wire rd_err;
wire [FIFO_WIDTH-1:0] rd_data;
integer idx = 0;
integer exp = 0;
`define TEST_CASE(VAR, VALUE) \
idx = idx + 1; \
if(VAR == VALUE) $display("Case %d passed!", idx); \
else begin $display("Case %d failed!", idx); $finish; end
sync_fifo #(
.FIFO_WIDTH(FIFO_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) dut (
.clk(clk),
.rst_n(rst_n),
.wr_en(wr_en),
.rd_en(rd_en),
.wr_data(wr_data),
.full(full),
.wr_err(wr_err),
.empty(empty),
.rd_err(rd_err),
.rd_data(rd_data)
);
initial begin
clk = 0;
rst_n = 1'b1;
rd_en = 1'b0;
wr_data = 32'b0;
wr_en = 1'b0;
#5 rst_n = 1'b0;
#5 rst_n = 1'b1;
// #5 wr_en = 1'b1;
// wr_data = 32'hffff_ffff;
repeat (10) begin
#10 wr_en = 1'b1;
wr_data = wr_data + 1;
#10 wr_en = 1'b0;
end
#50;
repeat (10) begin
#10 rd_en = 1'b1;
#10 rd_en = 1'b0;
// $display("%d",rd_data);
exp = idx > 7 ? 0 : idx + 1;
`TEST_CASE(rd_data, exp);
end
#50;
$display("Success!");
$finish;
end
initial begin
$dumpvars(0, sync_fifo_tb);
$dumpfile("a.dump");
end
always #5 begin
clk <= ~clk;
end
endmodule
| 6.967938 |
module Sync_gen (
input clk,
output vga_h_sync,
output vga_v_sync,
output reg InDisplayArea,
output reg [9:0] CounterX,
output reg [9:0] CounterY
);
//=======================================//
// Clock Divider //
//=======================================//
//VGA @ 640x480 resolution @ 60Hz requires a pixel clock of 25.175Mhz.
//The Kiwi has an Onboard 50Mhz oscillator, we can divide it and get a 25Mhz clock.
//It's not the exact frequency required for the VGA standard, but it works fine and it saves us the use of a PLL.
reg clkdiv;
reg [27:0] counter = 0;
parameter DIVISOR = 28'd2;
always @(posedge clk) begin
counter <= counter + 28'd1;
if (counter >= (DIVISOR - 1)) counter <= 28'd0;
clkdiv <= (counter < DIVISOR / 2) ? 1'b1 : 1'b0;
end
//=======================================//
reg h_sync, v_sync;
wire CounterXmaxed = (CounterX == 800); //16+48+96+640 - Pixel count for the horizontal lines (including porches)
wire CounterYmaxed = (CounterY == 525); //10+2+33+480 - Pixel count for the vertical lines (including porches)
always @(posedge clkdiv)
if (CounterXmaxed) CounterX <= 0;
else CounterX <= CounterX + 1;
always @(posedge clkdiv) begin
if (CounterXmaxed) begin
if (CounterYmaxed) CounterY <= 0;
else CounterY <= CounterY + 1;
end
end
always @(posedge clkdiv) begin
h_sync <= (CounterX > (640 + 16) && (CounterX < (640 + 16 + 96))); // active for 96 clocks
v_sync <= (CounterY > (480 + 10) && (CounterY < (480 + 10 + 2))); // active for 2 clocks
end
always @(posedge clkdiv) begin
InDisplayArea <= (CounterX < 640) && (CounterY < 480);
end
assign vga_h_sync = ~h_sync;
assign vga_v_sync = ~v_sync;
endmodule
| 8.172637 |
module sync_generate #(
parameter cw = 10,
parameter minc = 128
) (
input clk,
input [cw-1:0] cset,
output sync
);
reg [cw-1:0] count = 0;
reg ctl_bit = 0, invalid = 0;
wire rollover = count == 1;
always @(posedge clk) begin
count <= rollover ? cset : (count - 1);
invalid <= cset < minc;
if (rollover) ctl_bit <= ~ctl_bit | invalid;
end
assign sync = ctl_bit;
endmodule
| 6.900043 |
module sync_generator (
input wire vga_clk,
input wire reset,
output reg disp_en,
output reg hsync,
output reg vsync,
output reg [31:0] column,
output reg [31:0] row
);
localparam h_total = 800; //total number of pixels
localparam h_disp = 640; //displayed interval
localparam h_pw = 96; //pulse width
localparam h_fp = 16; //fronth porch
localparam h_bp = 48; //back porch
localparam v_total = 521;
localparam v_disp = 480;
localparam v_pw = 2;
localparam v_fp = 10;
localparam v_bp = 29;
reg [31:0] h_count;
reg [31:0] v_count;
always @(posedge vga_clk or posedge reset) begin
if (reset) begin
h_count <= h_disp + h_fp;
v_count <= v_disp + v_fp;
hsync <= 1'b0;
vsync <= 1'b0;
column <= h_disp + h_fp;
row <= v_disp + v_fp;
disp_en <= 1'b0;
end else begin
if (h_count < (h_total - 1)) begin
h_count <= h_count + 1;
end else begin
h_count <= 0;
end
if (h_count == (h_disp + h_fp)) begin
if ((v_count < (v_total - 1))) begin
v_count <= v_count + 1;
end else begin
v_count <= 0;
end
end
if (h_count < (h_disp + h_fp) || h_count > (h_total - h_bp)) begin
hsync <= 1'b1;
end else begin
hsync <= 1'b0;
end
if (v_count < (v_disp + v_fp) || v_count > (v_total - v_bp)) begin
vsync <= 1'b1;
end else begin
vsync <= 1'b0;
end
//pixel coords
if (h_count < h_disp) begin
column <= h_count;
end else begin
column <= column;
end
if (v_count < v_disp) begin
row <= v_count;
end else begin
row <= row;
end
if (h_count < h_disp && v_count < v_disp) begin
disp_en <= 1'b1;
end else begin
disp_en <= 1'b0;
end
end
end
endmodule
| 6.935912 |
module sync_generators (
input clk,
input reset,
input enable,
output wire hsync,
output wire vsync,
output wire valid_data,
output reg [`log2NUM_COLS-1:0] x,
output reg [`log2NUM_ROWS-1:0] y
);
/* Regs and Wires */
reg [`log2NUM_XCLKS_IN_ROW-1 : 0] pixel_counter;
reg [`log2NUM_LINES_IN_FRAME-1:0] hsync_counter;
wire valid_h, valid_v;
/* Logic for X, Y Outputs */
assign valid_data = valid_h && valid_v;
/* Counts pixels in a row...row counter is incemented every row */
always @(posedge clk)
if ((pixel_counter == `NUM_XCLKS_IN_ROW - 1) || reset) pixel_counter <= 0;
else if (enable) pixel_counter <= pixel_counter + 1;
else pixel_counter <= pixel_counter;
/* Combinational Logic for hsync */
assign hsync = pixel_counter >= `H_SYNC_PULSE;
/* Count the hsyncs */
always @(posedge clk)
if ((hsync_counter == `NUM_LINES_IN_FRAME - 1) || reset) hsync_counter <= 0;
else if (enable && (pixel_counter == `NUM_XCLKS_IN_ROW - 1)) hsync_counter <= hsync_counter + 1;
else hsync_counter <= hsync_counter;
/* Comb L for vsync */
assign vsync = (hsync_counter != `NUM_LINES_IN_FRAME) && (hsync_counter >= (`V_SYNC_PULSE));
assign valid_h = (pixel_counter >= (`H_SYNC_PULSE + `H_BACK_PORCH))
&& (pixel_counter <= (`NUM_XCLKS_IN_ROW - `H_FRONT_PORCH));
assign valid_v = (hsync_counter >= (`V_SYNC_PULSE + `V_BACK_PORCH))
&& (hsync_counter <= (`NUM_LINES_IN_FRAME - `V_FRONT_PORCH));
/* X & Y Generation */
always @(posedge clk)
if (~valid_h || reset) x <= 0;
else if (enable) x <= x + 1;
else x <= x;
always @(posedge clk)
if (~valid_v || reset) y <= 0;
else if (enable && (pixel_counter == `NUM_XCLKS_IN_ROW - 1)) y <= y + 1;
else y <= y;
endmodule
| 6.935912 |
module sync_generator_pal_ntsc (
input wire clk, // 7 MHz
input wire in_mode, // 0: PAL, 1: NTSC
output reg csync_n,
output reg hsync_n,
output reg vsync_n,
output wire [8:0] hc,
output wire [8:0] vc,
output reg vblank,
output reg hblank,
output reg blank
);
parameter PAL = 1'b0;
parameter NTSC = 1'b1;
reg [8:0] h = 9'd0;
reg [8:0] v = 9'd0;
reg mode = PAL;
assign hc = h;
assign vc = v;
always @(posedge clk) begin
if (mode == PAL) begin
if (h == 9'd447) begin
h <= 9'd0;
if (v == 9'd311) begin
v <= 9'd0;
mode <= in_mode;
end else v <= v + 9'd1;
end else h <= h + 9'd1;
end else begin // NTSC
if (h == 9'd444) begin
h <= 9'd0;
if (v == 9'd261) begin
v <= 9'd0;
mode <= in_mode;
end else v <= v + 9'd1;
end else h <= h + 9'd1;
end
end
//reg vblank, hblank;
always @* begin
vblank = 1'b0;
hblank = 1'b0;
vsync_n = 1'b1;
hsync_n = 1'b1;
if (mode == PAL) begin
if (v >= 9'd304 && v <= 9'd311) begin
vblank = 1'b1;
if (v >= 9'd304 && v <= 9'd307) begin
vsync_n = 1'b0;
end
end
if (h >= 9'd352 && h <= 9'd447) begin
hblank = 1'b1;
if (h >= 9'd376 && h <= 9'd407) begin
hsync_n = 1'b0;
end
end
end else begin // NTSC
if (v >= 9'd254 && v <= 9'd261) begin
vblank = 1'b1;
if (v >= 9'd254 && v <= 9'd257) begin
vsync_n = 1'b0;
end
end
if (h >= 9'd352 && h <= 9'd443) begin
hblank = 1'b1;
if (h >= 9'd376 && h <= 9'd407) begin
hsync_n = 1'b0;
end
end
end
blank = hblank | vblank;
csync_n = hsync_n & vsync_n;
end
endmodule
| 6.935912 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing a counter from one clock domain to another
* using gray code. To work correctly the counter must not change its value by
* more than one in one clock cycle in the source domain. I.e. the value may
* change by either -1, 0 or +1.
*/
`timescale 1ns/100ps
module sync_gray #(
// Bit-width of the counter
parameter DATA_WIDTH = 1,
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1)(
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count);
generate if (ASYNC_CLK == 1) begin
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = out_count_m;
end else begin
assign out_count = in_count;
end endgenerate
endmodule
| 8.180735 |
module sync_header_align #(
) (
input clk,
input reset,
input [65:0] i_data,
output i_slip,
input i_slip_done,
output [63:0] o_data,
output [1:0] o_header,
output o_block_sync
);
assign {o_header, o_data} = i_data;
// TODO : Add alignment FSM
localparam STATE_SH_HUNT = 3'b001;
localparam STATE_SH_SLIP = 3'b010;
localparam STATE_SH_LOCK = 3'b100;
localparam BIT_SH_HUNT = 0;
localparam BIT_SH_SLIP = 1;
localparam BIT_SH_LOCK = 2;
localparam RX_THRESH_SH_ERR = 16;
localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR);
reg [2:0] state = STATE_SH_HUNT;
reg [2:0] next_state;
reg [7:0] header_vcnt = 8'h0;
reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0;
wire valid_header;
assign valid_header = ^o_header;
always @(posedge clk) begin
if (reset | ~valid_header) begin
header_vcnt <= 'b0;
end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin
header_vcnt <= header_vcnt + 'b1;
end
end
always @(posedge clk) begin
if (reset | valid_header) begin
header_icnt <= 'b0;
end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
header_icnt <= header_icnt + 'b1;
end
end
always @(*) begin
next_state = state;
case (state)
STATE_SH_HUNT:
if (valid_header) begin
if (header_vcnt[7]) begin
next_state = STATE_SH_LOCK;
end
end else begin
next_state = STATE_SH_SLIP;
end
STATE_SH_SLIP:
if (i_slip_done) begin
next_state = STATE_SH_HUNT;
end
STATE_SH_LOCK:
if (~valid_header) begin
if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
next_state = STATE_SH_HUNT;
end
end
endcase
end
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= STATE_SH_HUNT;
end else begin
state <= next_state;
end
end
assign o_block_sync = state[BIT_SH_LOCK];
assign i_slip = state[BIT_SH_SLIP];
endmodule
| 7.188995 |
module sync_level2level (
clk,
rst_b,
sync_in,
sync_out
);
parameter SIGNAL_WIDTH = 1;
parameter FLOP_NUM = 3;
input clk;
input rst_b;
input [SIGNAL_WIDTH-1:0] sync_in;
output [SIGNAL_WIDTH-1:0] sync_out;
reg [SIGNAL_WIDTH-1:0] sync_ff [FLOP_NUM-1:0];
wire clk;
wire rst_b;
wire [SIGNAL_WIDTH-1:0] sync_in;
wire [SIGNAL_WIDTH-1:0] sync_out;
genvar i;
always @(posedge clk or negedge rst_b) begin
if (!rst_b) sync_ff[0][SIGNAL_WIDTH-1:0] <= {SIGNAL_WIDTH{1'b0}};
else sync_ff[0][SIGNAL_WIDTH-1:0] <= sync_in[SIGNAL_WIDTH-1:0];
end
generate
for (i = 1; i < FLOP_NUM; i = i + 1) begin : FLOP_GEN
always @(posedge clk or negedge rst_b) begin
if (!rst_b) sync_ff[i][SIGNAL_WIDTH-1:0] <= {SIGNAL_WIDTH{1'b0}};
else sync_ff[i][SIGNAL_WIDTH-1:0] <= sync_ff[i-1][SIGNAL_WIDTH-1:0];
end
end
endgenerate
assign sync_out[SIGNAL_WIDTH-1:0] = sync_ff[FLOP_NUM-1][SIGNAL_WIDTH-1:0];
endmodule
| 8.759645 |
module sync_level2pulse (
clk,
rst_b,
sync_in,
sync_out,
sync_ack
);
input clk;
input rst_b;
input sync_in;
output sync_out;
output sync_ack;
reg sync_ff;
wire clk;
wire rst_b;
wire sync_in;
wire sync_out;
wire sync_ack;
wire sync_out_level;
sync_level2level x_sync_level2level (
.clk (clk),
.rst_b (rst_b),
.sync_in (sync_in),
.sync_out(sync_out_level)
);
always @(posedge clk or negedge rst_b) begin
if (!rst_b) sync_ff <= 1'b0;
else sync_ff <= sync_out_level;
end
assign sync_out = sync_out_level & ~sync_ff;
assign sync_ack = sync_out_level;
endmodule
| 7.54875 |
module sync_logic #(
parameter c_DATA_WIDTH = 10
) (
rstn,
wr_clk,
wr_data,
rd_clk,
rd_data
);
input rstn;
input wr_clk;
input [c_DATA_WIDTH-1:0] wr_data;
input rd_clk;
output [c_DATA_WIDTH-1:0] rd_data;
//registers driven by wr_clk
reg [1:0] update_ack_dly;
reg update_strobe;
reg [c_DATA_WIDTH-1:0] data_buf /* synthesis syn_preserve=1 */;
//registers driven by rd_clk
reg update_ack;
reg [3:0] update_strobe_dly;
reg [c_DATA_WIDTH-1:0] data_buf_sync /* synthesis syn_preserve=1 */;
//************************************************************************************
always @(posedge wr_clk or negedge rstn)
if (!rstn) begin
update_ack_dly <= 0;
update_strobe <= 0;
data_buf <= 0;
end else begin
update_ack_dly <= {update_ack_dly[0], update_ack};
if (update_strobe == update_ack_dly[1]) begin
//latch new data
data_buf <= wr_data;
update_strobe <= ~update_strobe;
end
end
//************************************************************************************
always @(posedge rd_clk or negedge rstn)
if (!rstn) begin
update_ack <= 0;
update_strobe_dly <= 0;
data_buf_sync <= 0;
end else begin
update_strobe_dly <= {update_strobe_dly[2:0], update_strobe};
if (update_strobe_dly[3] != update_ack) begin
data_buf_sync <= data_buf;
update_ack <= update_strobe_dly[3];
end
end
assign rd_data = data_buf_sync;
endmodule
| 7.839665 |
module sync_low (
clk,
n_rst,
async_in,
sync_out
);
input clk, n_rst, async_in;
output sync_out;
wire values;
DFFSR values_reg (
.D (async_in),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (values)
);
DFFSR sync_out_reg (
.D (values),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (sync_out)
);
endmodule
| 6.522048 |
module sync_module (
input CLK_40M,
input RSTn,
output reg end_sig,
output reg start
);
reg [31:0] Count;
parameter T1s = 32'd25_000_000;
always @(posedge CLK_40M or negedge RSTn)
if (!RSTn) begin
end_sig <= 1'b0;
start <= 1'b1;
end else if (Count == T1s) begin
start <= ~start;
end_sig <= ~end_sig;
end else begin
end_sig <= end_sig;
start <= start;
end
always @(posedge CLK_40M or negedge RSTn)
if (!RSTn) begin
Count <= 32'b0;
end else if (Count == T1s) Count <= 32'b0;
else Count <= Count + 32'd1;
endmodule
| 6.618592 |
module sync_pre_process (
input clk,
input reset_n,
input ext_hsync_i,
input ext_vsync_i,
output hsync_redge_o,
output vsync_redge_o,
output hsync_fedge_o,
output vsync_fedge_o
);
parameter DLY_WIDTH = 12;
reg hsync_temp;
reg vsync_temp;
reg [DLY_WIDTH-1:0] hsync_shift;
reg [DLY_WIDTH-1:0] vsync_shift;
always @(posedge clk or negedge reset_n) begin //缓存
if (~reset_n) begin
hsync_shift <= 0;
vsync_shift <= 0;
end else begin
hsync_shift <= {hsync_shift[DLY_WIDTH-2:0], ext_hsync_i};
vsync_shift <= {vsync_shift[DLY_WIDTH-2:0], ext_vsync_i};
end
end
always @(posedge clk or negedge reset_n) begin //同步信号去抖
if (~reset_n) begin
hsync_temp <= 1;
vsync_temp <= 1;
end else begin
hsync_temp <= hsync_shift[4] || hsync_shift[6]; //参数需要根据实际信号的波动调节 以去除同步信号抖动
vsync_temp <= vsync_shift[4] || vsync_shift[6];
end
end
reg hsync_r;
reg vsync_r;
always @(posedge clk) begin
hsync_r <= hsync_temp;
vsync_r <= vsync_temp;
end
assign hsync_redge_o = (~hsync_r) & hsync_temp; //提取边沿
assign vsync_redge_o = (~vsync_r) & vsync_temp;
assign hsync_fedge_o = hsync_r & (~hsync_temp);
assign vsync_fedge_o = vsync_r & (~vsync_temp);
endmodule
| 9.524769 |
module sync_ptr #(
parameter ASIZE = 4
) (
input wire dest_clk,
input wire dest_rst_n,
input wire [ASIZE:0] src_ptr,
output reg [ASIZE:0] dest_ptr
);
reg [ASIZE:0] ptr_x;
always @(posedge dest_clk or negedge dest_rst_n) begin
if (!dest_rst_n) {dest_ptr, ptr_x} <= 0;
else {dest_ptr, ptr_x} <= {ptr_x, src_ptr};
end
endmodule
| 7.489374 |
module sync_pulse_synchronizer ( /*AUTOARG*/
// Outputs
sync_out,
so,
// Inputs
async_in,
gclk,
rclk,
si,
se
);
output sync_out;
output so;
input async_in;
input gclk;
input rclk;
input si;
input se;
wire pre_sync_out;
wire so_rptr;
wire so_lockup;
// Flop drive strengths to be adjusted as necessary
bw_u1_soff_8x repeater (
.q (pre_sync_out),
.so(so_rptr),
.ck(gclk),
.d (async_in),
.se(se),
.sd(si)
);
bw_u1_scanl_2x lockup (
.so(so_lockup),
.sd(so_rptr),
.ck(gclk)
);
bw_u1_soff_8x syncff (
.q (sync_out),
.so(so),
.ck(rclk),
.d (pre_sync_out),
.se(se),
.sd(so_lockup)
);
endmodule
| 6.944583 |
module sync_ram (
aclr,
data,
rdclk,
wrclk,
q
);
parameter data_bits = 32;
input aclr;
input [data_bits-1:0] data;
input rdclk;
input wrclk;
output [data_bits-1:0] q;
wire [2:0] wraddress;
wire [2:0] rdaddress;
assign wraddress = 0;
assign rdaddress = 0;
dp_ram #(
.DATA_WIDTH(data_bits),
.ADDR_WIDTH(3)
) dp_ram (
.aclr(aclr),
.data(data),
.rdaddress(rdaddress),
.wraddress(wraddress),
.wren(1'b1),
.rdclock(rdclk),
.wrclock(wrclk),
.q(q)
);
endmodule
| 6.884981 |
module sync_ram_data (
input clk,
input en, //access enable, HIGH valid
input [ 3:0] wen, //write enable by byte, HIGH valid
input [ 9:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] bit_array[10:0];
reg en_r;
reg [ 3:0] wen_r;
reg [ 9:0] addr_r;
reg [31:0] wdata_r;
wire [31:0] rd_out;
initial begin
$readmemh("D:/vivado/ram.txt", bit_array);
end
// inputs latch
//always @(posedge clk) begin
// en_r <= en;
// if (en) begin
// wen_r <= wen;
// addr_r <= addr;
// wdata_r <= wdata;
// end
//end
// bit array write
always @(posedge clk) begin
if (en) begin
if (wen[0]) bit_array[addr][7:0] <= wdata[7:0];
if (wen[1]) bit_array[addr][15:8] <= wdata[15:8];
if (wen[2]) bit_array[addr][23:16] <= wdata[23:16];
if (wen[3]) bit_array[addr][31:24] <= wdata[31:24];
end
end
// bit array read
assign rd_out = bit_array[addr];
// final output
assign rdata = rd_out;
endmodule
| 6.88962 |
module sync_ram_display (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
parameter data_bits = 41;
parameter addr_bits = 4;
input aclr;
input [data_bits-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [data_bits-1:0] q;
output [3:0] rdusedw;
output [3:0] wrusedw;
wire [addr_bits-1:0] wraddress;
wire [addr_bits-1:0] rdaddress;
assign wraddress = 0;
assign rdaddress = 0;
dp_ram_display #(
.DATA_WIDTH(data_bits),
.ADDR_WIDTH(addr_bits)
) dp_ram (
.data(data),
.rdaddress(rdaddress),
.wraddress(wraddress),
.wren(1'b1),
.rdclock(rdclk),
.wrclock(wrclk),
.q(q)
);
endmodule
| 6.967505 |
module sync_ram_emul (
input clk,
input en, //access enable, HIGH valid
input [ 3:0] wen, //write enable by byte, HIGH valid
input [ 9:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] bit_array[100:0];
reg en_r;
reg [ 3:0] wen_r;
reg [ 9:0] addr_r;
reg [31:0] wdata_r;
wire [31:0] rd_out;
initial begin
$readmemh("F:/verilog/yaoqing_pipeline/test.txt", bit_array);
end
// inputs latch
always @(posedge clk) begin
en_r <= en;
if (en) begin
wen_r <= wen;
addr_r <= addr;
wdata_r <= wdata;
end
end
// bit array write
always @(posedge clk) begin
if (en_r) begin
if (wen_r[0]) bit_array[addr_r][7:0] <= wdata_r[7:0];
if (wen_r[1]) bit_array[addr_r][15:8] <= wdata_r[15:8];
if (wen_r[2]) bit_array[addr_r][23:16] <= wdata_r[23:16];
if (wen_r[3]) bit_array[addr_r][31:24] <= wdata_r[31:24];
end
end
// bit array read
assign rd_out = bit_array[addr_r];
// final output
assign rdata = rd_out;
endmodule
| 6.861571 |
module sync_ram_wf_x32 ( /*AUTOARG*/
// Outputs
dout,
// Inputs
clk,
web,
enb,
addr,
din
);
parameter ADDR_WIDTH = 10;
input clk;
input [3:0] web;
input [3:0] enb;
input [9:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] RAM [(2<<ADDR_WIDTH)-1:0];
reg [31:0] dout;
always @(posedge clk) begin
if (enb[0]) begin
if (web[0]) begin
RAM[addr][7:0] <= din[7:0];
dout[7:0] <= din[7:0];
end else begin
dout[7:0] <= RAM[addr][7:0];
end
end
end // always @ (posedge clk)
always @(posedge clk) begin
if (enb[1]) begin
if (web[1]) begin
RAM[addr][15:8] <= din[15:8];
dout[15:8] <= din[15:8];
end else begin
dout[15:8] <= RAM[addr][15:8];
end
end
end // always @ (posedge clk)
always @(posedge clk) begin
if (enb[2]) begin
if (web[2]) begin
RAM[addr][23:16] <= din[23:16];
dout[23:16] <= din[23:16];
end else begin
dout[23:16] <= RAM[addr][23:16];
end
end
end
always @(posedge clk) begin
if (enb[3]) begin
if (web[3]) begin
RAM[addr][31:24] <= din[31:24];
dout[31:24] <= din[31:24];
end else begin
dout[31:24] <= RAM[addr][31:24];
end
end
end
endmodule
| 6.793915 |
module sync_rebuiltSignal (
input clock,
input [3:0] sensors,
output [3:0] rebuiltSignal
);
reg [3:0] rebuiltSignal_reg;
wire [3:0] rising_edge_wire;
wire [3:0] falling_edge_wire;
//syncing sensors /////////////
signalSync sync_reb0 (
.clock(clock),
.asynchronous_signal(sensors[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0]) //active low, so falling edge is start of activity
);
always @(posedge clock) begin
if (rising_edge_wire[0]) rebuiltSignal_reg[0] <= 1;
else if (falling_edge_wire[0]) rebuiltSignal_reg[0] <= 0;
// else
// rebuiltSignal_reg[0] <= rebuiltSignal_reg[0];
end
signalSync sync_reb1 (
.clock(clock),
.asynchronous_signal(sensors[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1]) //active low, so falling edge is start of activity
);
always @(posedge clock) begin
if (rising_edge_wire[1]) rebuiltSignal_reg[1] <= 1;
else if (falling_edge_wire[1]) rebuiltSignal_reg[1] <= 0;
// else
// rebuiltSignal_reg[1] <= rebuiltSignal_reg[1];
end
signalSync sync_reb2 (
.clock(clock),
.asynchronous_signal(sensors[2]),
.rising_edge(rising_edge_wire[2]),
.falling_edge(falling_edge_wire[2]) //active low, so falling edge is start of activity
);
always @(posedge clock) begin
if (rising_edge_wire[2]) rebuiltSignal_reg[2] <= 1;
else if (falling_edge_wire[2]) rebuiltSignal_reg[2] <= 0;
// else
// rebuiltSignal_reg[2] <= rebuiltSignal_reg[2];
end
signalSync sync_reb3 (
.clock(clock),
.asynchronous_signal(sensors[3]),
.rising_edge(rising_edge_wire[3]),
.falling_edge(falling_edge_wire[3]) //active low, so falling edge is start of activity
);
always @(posedge clock) begin
if (rising_edge_wire[3]) rebuiltSignal_reg[3] <= 1;
else if (falling_edge_wire[3]) rebuiltSignal_reg[3] <= 0;
// else
// rebuiltSignal_reg[3] <= rebuiltSignal_reg[3];
end
assign rebuiltSignal = rebuiltSignal_reg;
endmodule
| 7.126084 |
module sync_reg #(
parameter INIT = 0,
parameter ASYNC_RESET = 0
) (
input clk,
input rst,
input in,
output out
);
(* ASYNC_REG = "TRUE" *)reg sync1;
(* ASYNC_REG = "TRUE" *)reg sync2;
assign out = sync2;
generate
if (ASYNC_RESET) begin
always @(posedge clk or posedge rst) begin
if (rst) begin
sync1 <= INIT;
sync2 <= INIT;
end else begin
sync1 <= in;
sync2 <= sync1;
end
end
end else begin
always @(posedge clk) begin
if (rst) begin
sync1 <= INIT;
sync2 <= INIT;
end else begin
sync1 <= in;
sync2 <= sync1;
end
end
end
endgenerate
endmodule
| 6.715762 |
module sync_regf (
clk, // system clock
reset_b, // power on reset
halt, // system wide halt
addra, // Port A read address
a_en, // Port A read enable
addrb, // Port B read address
b_en, // Port B read enable
addrc, // Port C write address
dc, // Port C write data
wec, // Port C write enable
qra, // Port A registered output data
qrb
); // Port B registered output data
parameter AWIDTH = 5;
parameter DSIZE = 32;
input clk;
input reset_b;
input halt;
input [AWIDTH-1:0] addra;
input a_en;
input [AWIDTH-1:0] addrb;
input b_en;
input [AWIDTH-1:0] addrc;
input [DSIZE-1:0] dc;
input wec;
output [DSIZE-1:0] qra;
output [DSIZE-1:0] qrb;
// Internal varibles and signals
integer i;
reg [DSIZE-1:0] reg_file[0:(1<<AWIDTH)-1]; // Syncronous Reg file
assign qra = ((addrc == addra) && wec) ? dc : reg_file[addra];
assign qrb = ((addrc == addrb) && wec) ? dc : reg_file[addrb];
always @(posedge clk or negedge reset_b) begin
if (!reset_b) for (i = 0; i < (1 << AWIDTH); i = i + 1) reg_file[i] <= {DSIZE{1'bx}};
else if (wec) reg_file[addrc] <= dc;
end
task reg_display;
integer k;
begin
for (k = 0; k < (1 << AWIDTH); k = k + 1) $display("Location %d = %h", k, reg_file[k]);
end
endtask
endmodule
| 7.134558 |
module sync_regs #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -to [get_keepers *sync_regs*din_meta\[*\]]\" " */;
reg [WIDTH*(DEPTH-1)-1:0] sync_sr = 0 /* synthesis preserve dont_replicate */;
always @(posedge clk) begin
din_meta <= din;
sync_sr <= (sync_sr << WIDTH) | din_meta;
end
assign dout = sync_sr[WIDTH*(DEPTH-1)-1:WIDTH*(DEPTH-2)];
endmodule
| 7.401305 |
module sync_regs_aclr_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input aclr,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_multicycle_path -to [get_keepers *sync_regs_aclr_m*din_meta\[*\]] 2\" " */ ;
reg [WIDTH*(DEPTH-1)-1:0]
sync_sr = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -hold -to [get_keepers *sync_regs_aclr_m*din_meta\[*\]]\" " */ ;
always @(posedge clk or posedge aclr) begin
if (aclr) begin
din_meta <= {WIDTH{1'b0}};
sync_sr <= {(WIDTH * (DEPTH - 1)) {1'b0}};
end else begin
din_meta <= din;
sync_sr <= (sync_sr << WIDTH) | din_meta;
end
end
assign dout = sync_sr[WIDTH*(DEPTH-1)-1:WIDTH*(DEPTH-2)];
endmodule
| 6.640836 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.