code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sync_regs_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_multicycle_path -to [get_keepers *sync_regs_m*din_meta\[*\]] 2\" " */ ;
reg [WIDTH*(DEPTH-1)-1:0]
sync_sr = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -hold -to [get_keepers *sync_regs_m*din_meta\[*\]]\" " */ ;
always @(posedge clk) begin
din_meta <= din;
sync_sr <= (sync_sr << WIDTH) | din_meta;
end
assign dout = sync_sr[WIDTH*(DEPTH-1)-1:WIDTH*(DEPTH-2)];
endmodule
| 6.766461 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sync_resets#(
parameter WIDTH = 1,
parameter REGISTER = 4 // number of registers used at crossing clocks >1
)(
input arst, // async reset
input [WIDTH-1:0] locked, // clk[i] MMCM/PLL is locked
input [WIDTH-1:0] clk, // clk[0] - master clock generation should not depend on resets)
output [WIDTH-1:0] rst // resets matching input clocks
);
reg en_locked=0; // mostly for simulation, locked[0] is 1'bx until the first clock[0] pulse
wire [WIDTH-1:0] rst_w; // resets matching input clocks
wire rst_early_master_w;
reg rst_early_master;
assign rst = rst_w;
reg mrst = 1;
always @ (posedge arst or posedge clk[0]) begin
if (arst) en_locked <= 0;
else en_locked <= 1;
if (arst) mrst <= 1;
else mrst <= ~(locked[0] && en_locked);
end
always @(posedge clk[0]) begin
rst_early_master <= rst_early_master_w | mrst;
end
level_cross_clocks #(
.WIDTH (1),
.REGISTER (REGISTER)
) level_cross_clocks_mrst_i (
.clk (clk[0]), // input
.d_in (mrst), // input[0:0]
.d_out (rst_early_master_w) // output[0:0]
);
generate
genvar i;
for (i = 1; i < WIDTH; i = i + 1) begin: rst_block
level_cross_clocks #(
.WIDTH (1),
.REGISTER ((i==5) ? 1: REGISTER), // disable for aclk
// .REGISTER (REGISTER), // disable for aclk - aclk is now (0)
.FAST1 (1) // Switch to next cycle, to 0 - regeisterd
) level_cross_clocks_rst_i (
.clk (clk[i]), // input
.d_in (mrst || rst_early_master || ~locked[i] ), // input[0:0]
.d_out (rst_w[i]) // output[0:0]
);
end
endgenerate
assign rst_w[0]= rst_early_master;
endmodule
| 8.081644 |
module sync_reset_stretch #(
parameter CYCLES = 2 // clock cycles by which pulse needs to be streched
) (
input clk_i,
input rst_n_i,
input data_i,
output reg data_o
);
//--------------------------------------------------------------------------------
// Pulse stretching logic
//--------------------------------------------------------------------------------
wire rst_n;
reg [CYCLES-1:0] rst_n_d;
always @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin
rst_n_d <= 'h0; // reset is applied in very next cycle
end else begin
rst_n_d <= {rst_n_d[CYCLES-2:0], (rst_n_i)}; // reset is removed after 2 cycles
end
end
assign rst_n = rst_n_d[CYCLES-1]; // stretched pulse
//--------------------------------------------------------------------------------
always @(posedge clk_i) begin
if (!rst_n) begin
data_o <= 1'b0;
end else begin
data_o <= data_i;
end
end
endmodule
| 7.925087 |
module sync_reset_tb ();
reg rst_n_i;
reg clk_i;
reg data_i;
wire data_o;
sync_reset dut (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.data_i (data_i),
.data_o (data_o)
);
initial begin
clk_i = 1'b0;
forever #5 clk_i = ~clk_i;
end
initial begin
rst_n_i = 1'b0;
data_i = 1'b0;
#12 data_i = 1'b1;
rst_n_i = 1'b1;
#35 rst_n_i = 1'b0;
#50 rst_n_i = 1'b1;
#45 rst_n_i = 1'b0;
#2 rst_n_i = 1'b1;
end
endmodule
| 7.351688 |
module sync_sig (
input clk,
input rst_n,
input in_sig,
output reg out_sig
);
parameter SHIFT_WIDTH = 2;
reg [SHIFT_WIDTH-1:0] sig_dly;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
sig_dly <= {SHIFT_WIDTH{1'b0}};
end else begin //Sync signal
sig_dly[0] <= in_sig;
sig_dly[SHIFT_WIDTH-1:1] <= sig_dly[SHIFT_WIDTH-2:0];
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
out_sig <= 1'b0;
end else begin //Sync signal
if ((|sig_dly) == 1'b0) begin
out_sig <= 1'b0;
end else if ((&sig_dly) == 1'b1) begin
out_sig <= 1'b1;
end else begin
out_sig <= out_sig;
end
end
end
endmodule
| 7.187767 |
module sync_signal #(
parameter WIDTH = 1, // width of the input and output signals
parameter N = 2 // depth of synchronizer
) (
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
| 8.633074 |
module sync_sp_ram #(
// Parameters
parameter ADDR_WIDTH = 8, // address's width
parameter DATA_WIDTH = 8 // data's width
) (
input clk, // system clock
input cen, // chip select, low active
input wen, // write enable, low active
input [ADDR_WIDTH-1:0] a, // address
input [DATA_WIDTH-1:0] d, // data in
output reg [DATA_WIDTH-1:0] q // data out
);
// Internal values
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(posedge clk) begin : RAM
if (cen == 1'b0) begin
if (wen == 1'b0) ram[a] <= d;
q <= ram[a];
end
end
endmodule
| 7.34309 |
modules for general use
// Description : Clock crossing support for Slave
// This contains support for cross-clock-domain (CDC) synchronization
// of type 2-phase and other, covering pulses and levels. Used for
// SCL to (system) CLK and CLK to SCL. Used for single nets, handshakes,
// FIFOs, etc.
// Note use of 2-phase handshakes due to SCL stopping suddenly.
//
// ----------------------------------------------------------------------------
// Revision History
// ----------------------------------------------------------------------------
//
//
// ----------------------------------------------------------------------------
// Implementation details
// ----------------------------------------------------------------------------
// See the micro-arch spec and MIPI I3C spec
//
// This suppports the Clock Domain Crossing using named blocks
// so Spyglass (or equiv) can be told that the sync is here.
// For most modern process, the single flop model is fine, although
// the flop type may need to be changed by constraint for older
// process (e.g. a sync flop, which has a "gravity" to settle
// faster).
// 1 flop is fine in normal cases because the Q out metastable
// noise will be short enough in time for the paths used at the
// lower speeds. That is, there is ~40ns minimum to both settle
// and arrive settled at the other end.
// ----------------------------------------------------------------------------
// Note naming: SYNC_= synchronizing, 2PH_=2-phase, S2P_=SCL to CLK, STATE=state with clr in
// LVL_=level vs. pulse input, LVLH_=level high
// Other naming: ASet=async set, local clear, AClr=local set, async clear
// Seq2=2 flop sequencer to ensure we get 1 pulse in local domain
module SYNC_2PH_S2C_STATE(
input rst_n,
input scl,
input clk,
input trig_scl, // trigger input from SCL domain
output out_clk, // output state in CLK domain
input clear_clk // input clear from CLK domain
);
reg scl_hshake;
reg clk_state;
reg clk_ack;
// NOTE: this can be a bit confusing. The scl_ to clk_
// is 2-phase. The scl_hshake changes on the trigger.
// The clk_state changes on hshake^ack==1 for the
// purpose of the use in the CLK domain. The clk_ack
// only changes when the clk_state has, so that we
// do not miss it and yet we do not expose metastable
// logic (hshake^ack) outside.
// We use 2-phase because SCL is not free running and
// may stop. So, CLK does all of the work.
// Note that state based ones are only cleared by
// explit request; so more changes may happen before
// cleared and that is OK.
always @ (posedge scl or negedge rst_n)
if (!rst_n)
scl_hshake <= 1'b0;
else if (trig_scl) // trigger pulse (1 clock in scl)
scl_hshake <= ~scl_hshake; // flips state
always @ (posedge clk or negedge rst_n)
if (!rst_n)
clk_state <= 1'b0;
else if (scl_hshake ^ clk_ack) // CDC
clk_state <= 1'b1; // sets on diff
else if (clear_clk)
clk_state <= 1'b0; // clears on explicit clear
assign out_clk = clk_state;
// ACK only chnages after state does and if still diff
always @ (posedge clk or negedge rst_n)
if (!rst_n)
clk_ack <= 1'b0;
else if (clk_state & (scl_hshake^clk_ack)) // change on state - CDC
clk_ack <= ~clk_ack;
endmodule
| 9.122374 |
module SYNC_2PH_LVL_S2C_STATE (
input rst_n,
input scl,
input clk,
input trig_scl, // trigger level from SCL domain
output out_clk, // output state in CLK domain
input clear_clk // input clear from CLK domain
);
reg clk_state;
reg clk_ack;
// see SYNC_2PH_S2C_STATE for details. Only difference is
// level held does not need scl_hshake since level (and
// if level too short for clk, then not registered). If
// we want to make sure seen, then need independent bit
// FUTURE: look at that for cases of stopped CLK
always @(posedge clk or negedge rst_n)
if (!rst_n) clk_state <= 1'b0;
else if (trig_scl ^ clk_ack) // level change - CDC
clk_state <= 1'b1;
else if (clear_clk) clk_state <= 1'b0;
assign out_clk = clk_state;
always @(posedge clk or negedge rst_n)
if (!rst_n) clk_ack <= 1'b0;
else if (clk_state & (trig_scl ^ clk_ack)) // still diff - CDC
clk_ack <= ~clk_ack;
endmodule
| 7.703339 |
module SYNC_Pulse_S2C (
input SCL,
input CLK,
input RSTn,
input local_set,
output o_pulse
);
// 4 phase handshake, but pulse out
reg svalue, cvalue, cpulse;
always @(posedge SCL or negedge RSTn)
if (!RSTn) svalue <= 1'b0;
else if (local_set) svalue <= 1'b1;
else if (cvalue) // CDC
svalue <= 1'b0;
always @(posedge CLK or negedge RSTn)
if (!RSTn) cvalue <= 1'b0;
else if (svalue) // CDC
cvalue <= 1'b1;
else cvalue <= 1'b0;
always @(posedge CLK or negedge RSTn)
if (!RSTn) cpulse <= 1'b0;
else if (cvalue) cpulse <= 1'b1;
else cpulse <= 1'b0;
assign o_pulse = cvalue & ~cpulse;
endmodule
| 6.541296 |
module SYNC_ASet_Seq2 (
input CLK,
input RSTn,
input async_set,
input local_clear,
output o_pulse
);
reg value, seq;
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (async_set) // CDC
value <= 1'b1;
else if (local_clear) value <= 1'b0;
always @(posedge CLK or negedge RSTn)
if (!RSTn) seq <= 1'b0;
else if (seq ^ value) seq <= ~seq;
// below pulses for 1 clock high, else is low
assign o_pulse = value & ~seq;
endmodule
| 6.607617 |
module SYNC_AClr_Seq2 (
input CLK,
input RSTn,
input local_set,
input async_clear,
output o_pulse
);
reg value, seq;
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
value <= 1'b0;
always @(posedge CLK or negedge RSTn)
if (!RSTn) seq <= 1'b0;
else if (seq ^ value) seq <= ~seq;
// below pulses for 1 clock high, else is low
assign o_pulse = value & ~seq;
endmodule
| 6.659348 |
module SYNC_S2C #(
parameter WIDTH = 1
) (
input rst_n,
input clk,
input [WIDTH-1:0] scl_data,
output [WIDTH-1:0] out_clk // output copy in CLK domain
);
reg [WIDTH-1:0] clk_copy;
assign out_clk = clk_copy;
// note: could use clk_copy^scl_data as test to allow ICG
always @(posedge clk or negedge rst_n)
if (!rst_n) clk_copy <= {WIDTH{1'b0}};
else clk_copy <= scl_data;
endmodule
| 8.207379 |
module SYNC_C2S #(
parameter WIDTH = 1
) (
input rst_n,
input scl, // could be SCL_n as well
input [WIDTH-1:0] clk_data,
output [WIDTH-1:0] out_scl // output copy in CLK domain
);
reg [WIDTH-1:0] scl_copy;
assign out_scl = scl_copy;
// note: could use clk_copy^scl_data as test to allow ICG
always @(posedge scl or negedge rst_n)
if (!rst_n) scl_copy <= {WIDTH{1'b0}};
else scl_copy <= clk_data;
endmodule
| 8.248687 |
module SYNC_AClr_C2S (
input CLK, // system domain
input RSTn,
input local_set,
input async_clear,
output o_value
);
reg value; // CLK domain
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
value <= 1'b0;
assign o_value = value;
endmodule
| 6.822945 |
module tb_dff ();
reg D, clk, reset;
wire Q;
integer i;
dff dut (
D,
clk,
reset,
Q
);
initial
//begin
clk = 0;
always #100 clk = ~clk;
//end
initial begin
$dumpfile("sync_DFF.vcd");
$dumpvars;
$monitor("Clock=%d, D=%d, Q=%d", clk, D, Q);
D <= 1;
reset = 1;
#200 D <= 0;
reset = 1;
#200 D <= 0;
reset = 0;
#200 D <= 1;
reset = 0;
#40 $finish;
end
endmodule
| 6.88469 |
module will take incoming horizontal and veritcal sync pulses and
// create Row and Column counters based on these syncs.
// It will align the Row/Col counters to the output Sync pulses.
// Useful for any module that needs to keep track of which Row/Col position we
// are on in the middle of a frame
module Sync_To_Count
#(parameter TOTAL_COLS = 800,
parameter TOTAL_ROWS = 525)
(input i_Clk,
input i_HSync,
input i_VSync,
output reg o_HSync = 0,
output reg o_VSync = 0,
output reg [9:0] o_Col_Count = 0,
output reg [9:0] o_Row_Count = 0);
wire w_Frame_Start;
// Register syncs to align with output data.
always @(posedge i_Clk)
begin
o_VSync <= i_VSync;
o_HSync <= i_HSync;
end
// Keep track of Row/Column counters.
always @(posedge i_Clk)
begin
if (w_Frame_Start == 1'b1)
begin
o_Col_Count <= 0;
o_Row_Count <= 0;
end
else
begin
if (o_Col_Count == TOTAL_COLS-1)
begin
if (o_Row_Count == TOTAL_ROWS-1)
begin
o_Row_Count <= 0;
end
else
begin
o_Row_Count <= o_Row_Count + 1;
end
o_Col_Count <= 0;
end
else
begin
o_Col_Count <= o_Col_Count + 1;
end
end
end
// Look for rising edge on Vertical Sync to reset the counters
assign w_Frame_Start = (~o_VSync & i_VSync);
endmodule
| 7.054311 |
module sync_up_counter (
input clk_i, // Clock
input rst_i, // Reset
output [3:0] count_o // Count Value
);
wire [3:0] d;
wire [3:0] q;
wire [3:0] q_n;
assign d[0] = q_n[0];
assign d[1] = (q_n[1] & q[0]) | (q[1] & q_n[0]);
assign d[2] = (q[2] & q_n[1]) | (q[2] & q_n[0]) | (q_n[2] & q[1] & q[0]);
assign d[3] = (q[3] & q_n[1]) | (q[3] & q_n[2]) | (q[3] & q[1] & q_n[0]) |
(q_n[3] & q[2] & q[1] & q[0]);
assign count_o = q;
// DFF 0
dff dff_1 (
.clk_i(clk_i), // Input Clock
.rst_i(rst_i),
.d_i (d[0]),
.q_o (q[0]),
.q_n_o(q_n[0])
);
// DFF 1
dff dff_2 (
.clk_i(clk_i),
.rst_i(rst_i),
.d_i (d[1]),
.q_o (q[1]),
.q_n_o(q_n[1])
);
// DFF 2
dff dff_3 (
.clk_i(clk_i),
.rst_i(rst_i),
.d_i (d[2]),
.q_o (q[2]),
.q_n_o(q_n[2])
);
// DFF 3
dff dff_4 (
.clk_i(clk_i),
.rst_i(rst_i),
.d_i (d[3]),
.q_o (q[3]),
.q_n_o(q_n[3])
);
endmodule
| 6.737946 |
module dff (
input clk_i,
input rst_i,
input d_i,
output reg q_o,
output q_n_o
);
assign q_n_o = ~q_o;
always @(posedge clk_i) begin
if (rst_i) begin
q_o <= 1'b0;
end else begin
q_o <= d_i;
end
end
endmodule
| 7.174483 |
module sync_vg # (
parameter X_BITS=12,
parameter Y_BITS=12,
//MODE_720p
parameter V_TOTAL = 12'd750,
parameter V_FP = 12'd5,
parameter V_BP = 12'd20,
parameter V_SYNC = 12'd5,
parameter V_ACT = 12'd720,
parameter H_TOTAL = 12'd1650,
parameter H_FP = 12'd110,
parameter H_BP = 12'd220,
parameter H_SYNC = 12'd40,
parameter H_ACT = 12'd1280,
parameter HV_OFFSET = 12'd0
)(
input clk,
input rstn,
output reg vs_out,
output reg hs_out,
output reg de_out,
output reg de_re,
output reg [X_BITS-1:0] x_act,
output reg [Y_BITS-1:0] y_act
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
/* horizontal counter */
always @(posedge clk)
begin
if (!rstn)
h_count <= `UD 0;
else
begin
if (h_count < H_TOTAL - 1)
h_count <= `UD h_count + 1;
else
h_count <= `UD 0;
end
end
/* vertical counter */
always @(posedge clk)
begin
if (!rstn)
v_count <= `UD 0;
else
if (h_count == H_TOTAL - 1)
begin
if (v_count == V_TOTAL - 1)
v_count <= `UD 0;
else
v_count <= `UD v_count + 1;
end
end
always @(posedge clk)
begin
if (!rstn)
hs_out <= `UD 4'b0;
else
hs_out <= `UD ((h_count < H_SYNC));
end
always @(posedge clk)
begin
if (!rstn)
vs_out <= `UD 4'b0;
else
begin
if ((v_count == 0) && (h_count == HV_OFFSET))
vs_out <= `UD 1'b1;
else if ((v_count == V_SYNC) && (h_count == HV_OFFSET))
vs_out <= `UD 1'b0;
else
vs_out <= `UD vs_out;
end
end
always @(posedge clk)
begin
if (!rstn)
de_out <= `UD 4'b0;
else
de_out <= (((v_count >= V_SYNC + V_BP) && (v_count <= V_TOTAL - V_FP - 1)) &&
((h_count >= H_SYNC + H_BP) && (h_count <= H_TOTAL - H_FP - 1)));
end
always @(posedge clk)
begin
if (!rstn)
de_re <= `UD 4'b0;
else
de_re <= (((v_count >= V_SYNC + V_BP) && (v_count <= V_TOTAL - V_FP - 1)) &&
((h_count >= H_SYNC + H_BP-2'd2) && (h_count <= H_TOTAL - H_FP - 3)));
end
// active pixels counter output
always @(posedge clk)
begin
if (!rstn)
x_act <= `UD 'd0;
else
begin
/* X coords C for a backend pattern generator */
if(h_count > (H_SYNC + H_BP - 1'b1))
x_act <= `UD (h_count - (H_SYNC + H_BP));
else
x_act <= `UD 'd0;
end
end
always @(posedge clk)
begin
if (!rstn)
y_act <= `UD 'd0;
else
begin
/* Y coords C for a backend pattern generator */
if(v_count > (V_SYNC + V_BP - 1'b1))
y_act <= `UD (v_count - (V_SYNC + V_BP));
else
y_act <= `UD 'd0;
end
end
endmodule
| 8.440742 |
module sync_vg
#(
parameter X_BITS=12,
parameter Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire interlaced,
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [X_BITS-1:0]
input wire [X_BITS-1:0]
input wire [X_BITS-1:0]
input wire [X_BITS-1:0]
input wire [X_BITS-1:0]
input wire [X_BITS-1:0]
output reg vs_out,
output reg hs_out,
output reg de_out,
output reg [Y_BITS:0]
output reg [X_BITS-1:0]
output reg [X_BITS-1:0]
output reg [Y_BITS:0]
output reg field_out,
output wire clk_out
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
reg field;
reg [Y_BITS-1:0] v_total;
reg [Y_BITS-1:0] v_fp;
reg [Y_BITS-1:0] v_bp;
reg [Y_BITS-1:0] v_sync;
reg [X_BITS-1:0] hv_offset;
assign clk_out = !clk;
/* horizontal counter */
always @(posedge clk)
if (reset)
h_count <= 0;
else
if (h_count < h_total - 1)
h_count <= h_count + 1;
else
h_count <= 0;
/* vertical counter */
always @(posedge clk)
if (reset)
v_count <= 0;
else
if (h_count == h_total - 1)
begin
if (v_count == v_total - 1)
v_count <= 0;
else
v_count <= v_count + 1;
end
/* field */
always @(posedge clk)
if (reset)
begin
field <= 0;
v_total <= v_total_0;
field <= field0;
vp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0
v_bp <= v_bp_0;
v_sync <= v_sync_0
hv_offset <= hv_offset_0;
end
else
if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1)))
begin
field <= field + interlaced;
v_total <= field ? v_total_0 : v_total_1;
v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0
v_bp <= field ? v_bp_0 : v_bp_1;
v_sync <= field ? v_sync_0 : v_sync_1;
hv_offset <= field ? hv_offset_0 : hv_offset_1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, de_out, field_out } <= 4'b0;
else begin
hs_out <= ((h_count < h_sync));
de_out <= (((v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1)) &&
((h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1)));
if ((v_count == 0) && (h_count == hv_offset))
vs_out <= 1'b1;
else if ((v_count == v_sync) && (h_count == hv_offset))
vs_out <= 1'b0;
/* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count;
if (field)
v_count_out <= v_count + v_total_0;
else
v_count_out <= v_count;
/* X and Y coords – for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp);
if (interlaced)
y_out <= { (v_count - (v_sync + v_bp)) , field };
else
y_out <= { 1'b0, (v_count - (v_sync + v_bp)) };
field_out <= field;
end
endmodule
| 7.274187 |
module cde_sync_with_reset #(
parameter DEPTH = 2,
RST_VAL = 1'b0,
WIDTH = 1
) (
input wire clk,
input wire reset_n,
input wire [WIDTH-1 : 0] data_in,
output wire [WIDTH-1 : 0] data_out
);
reg [WIDTH - 1:0] sync_data[DEPTH:0];
always @(*) begin
sync_data[0] = data_in;
end
integer i;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
for (i = 1; i <= DEPTH; i = i + 1) sync_data[i] <= RST_VAL;
end else begin
for (i = 1; i <= DEPTH; i = i + 1) sync_data[i] <= sync_data[i-1];
end
assign data_out = sync_data[DEPTH];
endmodule
| 7.756212 |
modules provides an an interface to
// instantiate the synchronizer block in VHDL.
//
`default_nettype none
module sync_wrapper #(
parameter WIDTH = 1,
parameter STAGES = 2,
parameter INITIAL_VAL = 0,
parameter FALSE_PATH_TO_IN = 1
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] signal_in,
output wire [WIDTH-1:0] signal_out
);
synchronizer #(
.WIDTH (WIDTH),
.STAGES (STAGES),
.INITIAL_VAL (INITIAL_VAL),
.FALSE_PATH_TO_IN (FALSE_PATH_TO_IN)
) synchronizer_i (
.clk (clk),
.rst (rst),
.in (signal_in),
.out (signal_out)
);
endmodule
| 8.032052 |
module synDff (
D,
clr_n,
clk,
Q
);
input D;
input clr_n;
input clk;
output reg Q;
always @(posedge clk) begin
if (!clr_n) begin
Q <= 0;
end else Q <= D;
end
endmodule
| 6.572321 |
module SynFIFO (
clk,
rst_n,
rdata,
wfull,
rempty,
wdata,
winc,
rinc
);
parameter DSIZE = 32;
parameter ASIZE = 9;
parameter MEMDEPTH = 1 << ASIZE;
parameter RAM_TYPE = "block"; // Type of RAM: string; "auto", "block", or "distributed";
output reg [DSIZE-1:0] rdata;
output wfull;
output rempty;
input [DSIZE-1:0] wdata;
input winc, rinc, clk, rst_n;
reg [ASIZE:0] wptr;
reg [ASIZE:0] rptr;
(* ram_style = RAM_TYPE *) reg [DSIZE-1:0] ex_mem[0:MEMDEPTH-1];
wire [DSIZE-1:0] rdata_tmp;
wire wfull_r;
wire [ASIZE:0] wptr_1;
always @(posedge clk)
if (!rst_n) wptr <= 0;
else if (winc && !wfull) begin
ex_mem[wptr[ASIZE-1:0]] <= wdata;
wptr <= wptr + 1;
end
always @(posedge clk)
if (!rst_n) rptr <= 0;
else if (rinc && !rempty) rptr <= rptr + 1;
assign wptr_1 = wptr + 1;
assign rdata_tmp = ex_mem[rptr[ASIZE-1:0]];
assign rempty = (rptr == wptr);
assign wfull = ((wptr_1[ASIZE-1:0] == rptr[ASIZE-1:0]) && (wptr_1[ASIZE] != rptr[ASIZE])) || wfull_r;
assign wfull_r = (wptr[ASIZE-1:0] == rptr[ASIZE-1:0]) && (wptr[ASIZE] != rptr[ASIZE]);
always @(posedge clk) begin
if (!rst_n) begin
rdata <= 0;
end else if (rinc) begin
rdata <= rdata_tmp;
end else begin
rdata <= rdata;
end
end
endmodule
| 7.205019 |
module fulladdersync (
a,
b,
phi,
y,
c_out
);
input a, b, phi;
output c_out, y;
wire cin1;
dynamicFF m1 (
c_out,
phi,
cin1
);
fulladder1 m2 (
a,
b,
cin1,
y,
c_out
);
endmodule
| 6.930859 |
module SYNinterrupt (
input clk,
input rst,
input INT,
output SYN_INT
);
reg SYNINT;
always @(posedge clk or posedge rst or posedge INT) begin
if (rst) SYNINT <= 1'b0;
else begin
if (INT) SYNINT <= 1'b1;
else SYNINT <= INT;
end
end
assign SYN_INT = SYNINT;
endmodule
| 7.077049 |
module synAddSub (
in1,
in2,
outp
);
parameter inp1_width = 16;
parameter inp2_width = 16;
parameter out_width = 16;
parameter opr = "add";
parameter dataType = "signed"; // for unsigned, use datatype = ""
input [inp1_width-1:0] in1;
input [inp2_width-1:0] in2;
output [out_width-1:0] outp;
wire [out_width-1:0] in1S;
wire [out_width-1:0] in2S;
wire [out_width-1:0] outpS;
generate
if (dataType == "signed") begin
assign in1S = $signed(in1);
assign in2S = $signed(in2);
end else if (dataType == "unsign") begin
assign in1S = $unsigned(in1);
assign in2S = $unsigned(in2);
end
if (opr == "add") assign outpS = in1S + in2S;
else if (opr == "subtract") assign outpS = in1S - in2S;
assign outp = outpS;
endgenerate
endmodule
| 6.919617 |
module synMult (
in1,
in2,
outp
);
parameter inp1_width = 16;
parameter inp2_width = 16;
parameter out_width = 32;
parameter dataType = "signed";
input [inp1_width-1:0] in1;
input [inp2_width-1:0] in2;
output [out_width-1:0] outp;
wire signed [inp1_width-1:0] in1S;
wire signed [inp2_width-1:0] in2S;
wire signed [inp1_width+inp2_width-1:0] outpS; // too cautious width, but will be optimized anyway
wire [inp1_width-1:0] in1U;
wire [inp2_width-1:0] in2U;
wire [inp1_width+inp2_width-1:0] outpU; // too cautious width, but will be optimized anyway
generate
begin : genBlock
if (dataType == "signed") begin : sig
assign in1S = $signed(in1);
assign in2S = $signed(in2);
assign outpS = in1S * in2S;
assign outp = outpS;
end // sig
if (dataType == "unsign") begin : uns
assign in1U = in1;
assign in2U = in2;
assign outpU = in1U * in2U;
assign outp = outpU;
end // uns
end // genBlock
endgenerate
endmodule
| 6.86167 |
module synBusAdapter (
inp,
outp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter datatype = "signed";
parameter preshift = 0; // negative values denote left shift
// Arguments to sat logic
parameter infrac = 0;
parameter outfrac = 0;
parameter round = 0;
parameter sat = 0;
parameter saType = "SS";
input [inp_width-1:0] inp;
output [out_width-1:0] outp;
parameter tmpInpWidth = inp_width + (preshift>0 ? preshift : -preshift) + ( infrac>inp_width ? infrac-inp_width: 0 );
// The Verilog compiler will issue warnings that some bits
// of the "inp" input will not be used. This is a normal
// consequence of shifting. The number of bits not used
// will equal the pre-shift value
wire signed [ inp_width-1:0] inpS;
wire [ inp_width-1:0] inpU;
wire signed [tmpInpWidth - 1:0] shiftedinpS;
wire [tmpInpWidth - 1:0] shiftedinpU;
wire [tmpInpWidth - 1:0] tmpInputOfSatBlock;
assign inpS = $signed(inp);
assign inpU = $unsigned(inp);
generate
if (datatype == "signed") begin
assign shiftedinpU = {tmpInpWidth{1'b0}}; // only one of these 2 signals is used per instance
assign tmpInputOfSatBlock = shiftedinpS;
if (preshift < 0) assign shiftedinpS = inpS <<< (-preshift);
else if (preshift > 0) assign shiftedinpS = inpS >>> preshift;
else if (preshift == 0) assign shiftedinpS = inpS;
end else begin
assign shiftedinpS = 'bz; // to eliminate compiler warnings for no assignment
assign tmpInputOfSatBlock = shiftedinpU;
if (preshift < 0) assign shiftedinpU = inpU <<< (-preshift);
else if (preshift > 0) assign shiftedinpU = inpU >>> preshift;
else if (preshift == 0) assign shiftedinpU = inpU;
end
endgenerate
generate
if (sat == 0 && round == 0)
if (datatype == "signed") assign outp = $signed(shiftedinpS);
else assign outp = shiftedinpU;
endgenerate
generate
if (sat == 1 || round >= 1)
synBusSatRnd #(
.inp_width(tmpInpWidth),
.out_width(out_width),
.infrac(infrac),
.outfrac(outfrac),
.round(round),
.sat(sat),
.datatype(saType)
) Convert (
.inp (tmpInputOfSatBlock),
.outp(outp)
);
endgenerate
endmodule
| 7.549782 |
module synBusAdapter_sat (
inp,
outp,
outsp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter datatype = "signed";
parameter preshift = 0; // negative values denote left shift
// Arguments to sat logic
parameter infrac = 0;
parameter outfrac = 0;
parameter round = 0;
parameter sat = 0;
parameter saType = "SS";
input [inp_width-1:0] inp;
output [out_width-1:0] outp;
output outsp;
parameter tmpInpWidth = inp_width + (preshift>0 ? preshift : -preshift) + ( infrac>inp_width ? infrac-inp_width: 0 );
// The Verilog compiler will issue warnings that some bits
// of the "inp" input will not be used. This is a normal
// consequence of shifting. The number of bits not used
// will equal the pre-shift value
wire signed [ inp_width-1:0] inpS;
wire [ inp_width-1:0] inpU;
wire signed [tmpInpWidth - 1:0] shiftedinpS;
wire [tmpInpWidth - 1:0] shiftedinpU;
wire [tmpInpWidth - 1:0] tmpInputOfSatBlock;
assign inpS = $signed(inp);
assign inpU = $unsigned(inp);
generate
if (datatype == "signed") begin
assign shiftedinpU = {tmpInpWidth{1'b0}}; // only one of these 2 signals is used per instance
assign tmpInputOfSatBlock = shiftedinpS;
if (preshift < 0) assign shiftedinpS = inpS <<< (-preshift);
else if (preshift > 0) assign shiftedinpS = inpS >>> preshift;
else if (preshift == 0) assign shiftedinpS = inpS;
end else begin
assign shiftedinpS = 'bz; // to eliminate compiler warnings for no assignment
assign tmpInputOfSatBlock = shiftedinpU;
if (preshift < 0) assign shiftedinpU = inpU <<< (-preshift);
else if (preshift > 0) assign shiftedinpU = inpU >>> preshift;
else if (preshift == 0) assign shiftedinpU = inpU;
end
endgenerate
generate
if (sat == 0 && round == 0)
if (datatype == "signed") assign outp = $signed(shiftedinpS);
else assign outp = shiftedinpU;
endgenerate
generate
if (sat == 1 || round >= 1)
synBusSatRnd_sat #(
.inp_width(tmpInpWidth),
.out_width(out_width),
.infrac(infrac),
.outfrac(outfrac),
.round(round),
.sat(sat),
.datatype(saType)
) Convert (
.inp (tmpInputOfSatBlock),
.outp (outp),
.outsp(outsp)
);
endgenerate
endmodule
| 7.549782 |
module synGain (
inp,
outp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter coef_width = 2;
parameter coefVal = 128'b1;
parameter dataType = "signed";
input [inp_width-1:0] inp;
output [out_width-1:0] outp;
wire signed [ inp_width-1:0] inpS;
wire signed [ coef_width-1:0] coefS;
wire signed [coef_width+inp_width-1:0] outS;
wire [ inp_width-1:0] inpU;
wire [ coef_width-1:0] coefU;
wire [coef_width+inp_width-1:0] outU;
generate
begin : signed_gen
if (dataType == "signed") begin
assign coefS = $signed(coefVal);
assign inpS = $signed(inp);
assign outS = coefS * inpS;
assign outp = outS[out_width-1:0];
end
end // signed_gen
begin : unsigned_gen
if (dataType == "unsign") begin
assign coefU = coefVal;
assign inpU = inp;
assign outU = coefU * inpU;
assign outp = outU[out_width-1:0];
end
end //unsigned_gen
endgenerate
endmodule
| 7.616726 |
module singleDelayWithEnableGeneric (
clk,
grst,
rst,
en,
inp,
outp
);
parameter bitwidth = 16;
input clk, grst, rst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outreg;
always @(`proclineg) begin
if (grst == `activehigh) outreg <= {bitwidth{1'b0}};
else if (rst == 1) outreg <= {bitwidth{1'b0}};
else if (en) outreg <= inp;
end
assign outp = outreg;
endmodule
| 6.583835 |
module synDelayWithEnable (
clk,
grst,
rst,
en,
inp,
outp
);
parameter preferRAMImpl = 1;
parameter bitwidth = 16;
parameter delaylength = 100;
input clk, grst, rst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
generate
begin : GenBlock
if (delaylength == 0) assign outp = inp;
else if (delaylength == 1)
singleDelayWithEnableGeneric #(
.bitwidth(bitwidth)
) theDelay (
.clk (clk),
.en (en),
.grst(grst),
.rst (rst),
.inp (inp),
.outp(outp)
);
else
synDelayWithEnableGeneric #(
.bitwidth(bitwidth),
.delaylength(delaylength),
.preferRAMImpl(preferRAMImpl)
) theDelay (
.clk (clk),
.en (en),
.grst(grst),
.rst (rst),
.inp (inp),
.outp(outp)
);
end // GenBlock
endgenerate
endmodule
| 6.727391 |
module synMux (
sel,
inp,
outp
);
parameter inp_width = 2;
parameter inp_size = 3;
parameter sel_bits = 2;
input [sel_bits-1:0] sel;
input [inp_width*inp_size-1:0] inp;
reg [inp_width-1:0] inpBuf[0:inp_size-1];
reg [inp_width-1:0] tmp;
output reg [inp_width-1:0] outp;
integer i, j;
always @(inp) begin
for (i = 0; i < inp_size; i = i + 1) begin
// synthesis loop_limit 128
for (j = 0; j < inp_width; j = j + 1) begin
tmp[j] = inp[i*inp_width+j];
end
inpBuf[i] = tmp;
end
end
always @(*) begin
outp <= inpBuf[sel];
end
endmodule
| 6.920522 |
module synCounter (
clk,
en,
grst,
rst,
up,
ld,
din,
cnt,
rdy
);
parameter en_exists = 1;
parameter rst_exists = 1;
parameter ld_exists = 0;
parameter rdy_exists = 0;
parameter ctype = 2;
parameter ival = 0;
parameter signed ivalS = ival;
parameter ivalU = ival;
parameter tval = 127;
parameter bitwidth = 16;
parameter isSigned = 0;
input clk, en, grst, rst, up, ld;
input [bitwidth-1:0] din;
output [bitwidth-1:0] cnt;
output rdy;
reg [bitwidth-1:0] cntU;
reg signed [bitwidth-1:0] cntS;
//assign cntU=$unsigned(ival);
//assign cntS=$signed(ival);
generate
begin : CounterGen
assign cnt = isSigned ? cntS : cntU;
if (!isSigned) begin
always @(`proclineg) begin : countU
if (grst == `activehigh) cntU <= ivalU;
else if (rst == 'b1 && rst_exists == 'b1) cntU <= ivalU;
else begin
if (en == 'b1 || en_exists == 'b0) begin
if (ld == 'b1 && ld_exists == 'b1) cntU <= $unsigned(din);
else if (cntU == $unsigned(tval)) cntU <= ivalU;
else if (ctype == 'd1)
if (up == 'b1) cntU <= cntU + 1;
else cntU <= cntU - 1;
else if (ctype == 'd2) cntU <= cntU + 'b1;
else cntU <= cntU - 'b1;
end
end
end //countU
assign rdy = (rdy_exists && cntU == $unsigned(tval));
end else if (isSigned) begin
always @(`proclineg) begin : countS
if (grst == `activehigh) cntS <= ivalS;
else if (rst == 'b1 && rst_exists == 'b1) cntS <= ivalS;
else begin
if (en == 'b1 || en_exists == 'b0) begin
if (ld == 'b1 && ld_exists == 'b1) cntS <= $signed(din);
else if (cntS == $signed(tval)) cntS <= ivalS;
else if (ctype == 'd1)
if (up == 'b1) cntS <= cntS + 'b1;
else cntS <= cntS - 'b1;
else if (ctype == 'd2) cntS <= cntS + 'b1;
else cntS <= cntS - 'b1;
end
end
end //countS
assign rdy = (rdy_exists && cntS == $signed(tval));
end
end // CounterGen
endgenerate
endmodule
| 7.088457 |
module synCounterSync (
clk,
en,
grst,
rdy
);
parameter tval = 127;
parameter bitwidth = 16;
parameter sample_offset = 0;
localparam resetVal = sample_offset != 0 ? 1'b0 : 1'b1;
input clk, en, grst;
output rdy;
reg [bitwidth-1:0] cntU;
reg rdyR;
generate
begin : CounterGen
always @(`proclineg) begin : countU
if (grst == `activehigh) begin
cntU <= 0;
rdyR <= resetVal;
end else begin
if (en == 1'b1) begin
if (cntU == $unsigned(tval)) cntU <= $unsigned(0);
else cntU <= cntU + 1;
if (cntU == ($unsigned(sample_offset + tval) % $unsigned(tval + 1))) rdyR <= 1'b1;
else rdyR <= 1'b0;
end
end
end //countU
assign rdy = rdyR;
end
endgenerate
endmodule
| 6.739524 |
module synCounterFR (
clk,
en,
grst,
rst,
up,
ld,
din,
cnt
);
parameter en_exists = 1;
parameter rst_exists = 1;
parameter ld_exists = 0;
parameter ctype = 2;
parameter ival = 0;
parameter signed ivalS = ival;
parameter ivalU = ival; //$unsigned(ival);
parameter tval = 127;
parameter bitwidth = 16;
parameter isSigned = 0;
input clk, en, grst, rst, up, ld;
input [bitwidth-1:0] din;
output [bitwidth-1:0] cnt;
reg [bitwidth-1:0] cntU;
reg signed [bitwidth-1:0] cntS;
// VHDL model is initialized, Verilog is not.
generate
begin : CounterGen
assign cnt = isSigned ? cntS : cntU;
if (!isSigned)
always @(`proclineg) begin : countU
if (grst == `activehigh) cntU <= ivalU;
else if (rst == 'b1 && rst_exists == 'b1) cntU <= ivalU;
else begin
if (en == 'b1 || en_exists == 'b0) begin
if (ld == 'b1 && ld_exists == 'b1) cntU <= $unsigned(din);
else if (ctype == 'd1)
if (up == 'b1) cntU <= cntU + 1;
else cntU <= cntU - 1;
else if (ctype == 'd2) cntU <= cntU + 'b1;
else cntU <= cntU - 'b1;
end
end
end //countU
else if (isSigned)
always @(`proclineg) begin : countS
if (grst == `activehigh) cntS <= ivalS;
else if (rst == 'b1 && rst_exists == 'b1) cntS <= ivalS;
else begin
if (en == 'b1 || en_exists == 'b0) begin
if (ld == 'b1 && ld_exists == 'b1) cntS <= $signed(din);
else if (ctype == 'd1)
if (up == 'b1) cntS <= cntS + 'b1;
else cntS <= cntS - 'b1;
else if (ctype == 'd2) cntS <= cntS + 'b1;
else cntS <= cntS - 'b1;
end
end
end //countS
end // CounterGen
endgenerate
endmodule
| 7.100612 |
module synRegister (
clk,
D,
en,
rst,
outp
);
parameter bitwidth = 16;
input clk;
input [bitwidth-1:0] D;
input en;
input rst;
output [bitwidth-1:0] outp;
// NOTE: VHDL initializes this to zero.
reg [bitwidth-1:0] outp;
//regproc: process(clk)
always @(`procline) begin
if (rst == `activehigh) outp <= {bitwidth{1'b0}};
else if (en) outp <= D;
end // always process;
endmodule
| 7.000795 |
module synStepFunction (
clk,
en,
grst,
rst,
outp
);
parameter bitwidth = 16;
parameter delaylength = 32;
parameter stepvalue = 1;
parameter cntWidth = `log_floor(delaylength);
parameter resetType = `grsttype;
input clk, en, grst, rst;
output [bitwidth-1:0] outp;
reg [cntWidth-1:0] cnt;
reg [bitwidth-1:0] outp;
generate
begin : synStepFunctionGen
if (resetType == "synch") begin : synch_implementation
always @(`proclineg) begin
if (rst == `activehigh || grst == `activehigh) begin
outp <= 0;
cnt <= 0;
end else begin
if (en) begin
if (cnt < delaylength - 1) begin
cnt <= cnt + 1;
outp <= 0;
end else outp <= stepvalue;
end
end
end
end else begin : asynch_implementation
always @(`proclineg) begin
if (grst == `activehigh) begin
outp <= 0;
cnt <= 0;
end else if (rst == `activehigh) begin
outp <= 0;
cnt <= 0;
end else begin
if (en) begin
if (cnt < delaylength - 1) begin
cnt <= cnt + 1;
outp <= 0;
end else outp <= stepvalue;
end
end
end
end
end
// synStepFunctionGen
endgenerate
endmodule
| 7.331865 |
module synAbs (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output reg [bitwidth-1:0] outp;
always @(inp) begin
if ($signed(inp) < 0) outp <= -$signed(inp);
else outp <= inp;
end
endmodule
| 7.552306 |
module synBinLogic (
inpA,
inpB,
outp
);
parameter bitwidth = 16;
parameter opr = "ANDD";
input [bitwidth-1:0] inpA;
input [bitwidth-1:0] inpB;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outp;
always @(*)
case (opr)
"ANDD": outp = inpA & inpB;
"ORRR": outp = inpA | inpB;
"XORR": outp = inpA ^ inpB;
"NAND": outp = ~(inpA & inpB);
"NORR": outp = ~(inpA | inpB);
"XNOR": outp = ~(inpA ^ inpB);
default: outp = {bitwidth{1'bx}};
endcase
endmodule
| 7.51569 |
module synComparator (
inpA,
inpB,
outp
);
parameter bitwidth = 16;
parameter datatype = "signed";
parameter opr = "equ";
input [bitwidth-1:0] inpA;
input [bitwidth-1:0] inpB;
output outp;
reg outp;
wire signed [bitwidth-1:0] AS;
wire signed [bitwidth-1:0] BS;
wire [bitwidth-1:0] AU;
wire [bitwidth-1:0] BU;
generate
begin : synComparator_block
assign AS = inpA;
assign AU = inpA;
assign BS = inpB;
assign BU = inpB;
always @(AS, BS, AU, BU)
if (datatype == "signed") begin : signed_wires
case (opr)
"equ": outp = AS == BS ? 1 : 0;
"neq": outp = AS != BS ? 1 : 0;
"les": outp = AS < BS ? 1 : 0;
"leq": outp = AS <= BS ? 1 : 0;
"gtr": outp = AS > BS ? 1 : 0;
"geq": outp = AS >= BS ? 1 : 0;
default: outp = 0;
endcase
end else begin : unsigned_wires
case (opr)
"equ": outp = AU == BU ? 1 : 0;
"neq": outp = AU != BU ? 1 : 0;
"les": outp = AU < BU ? 1 : 0;
"leq": outp = AU <= BU ? 1 : 0;
"gtr": outp = AU > BU ? 1 : 0;
"geq": outp = AU >= BU ? 1 : 0;
default: outp = 0;
endcase
end
end // Block
endgenerate
endmodule
| 7.482897 |
module synInverter (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
assign outp = ~inp;
endmodule
| 7.159415 |
module synNegate (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
assign outp = $signed(-(inp));
endmodule
| 6.820187 |
module synFIFO (
clk,
din,
en,
we,
re,
grst,
rst,
dout,
full,
empty,
itemcnt
);
parameter bitwidth = 16;
parameter depth = 16;
parameter cntwidth = 5;
parameter adrWidth = 4;
parameter isFwftMode = 0;
input clk;
input [bitwidth-1:0] din;
input en;
input we;
input re;
input grst;
input rst;
output [bitwidth-1:0] dout;
output full;
output empty;
output [cntwidth-1:0] itemcnt;
reg [bitwidth-1:0] fifoMem [0:depth-1];
reg full_reg;
reg not_empty_reg;
reg [cntwidth-1:0] cnt;
reg [adrWidth-1:0] readAddr;
reg [adrWidth-1:0] writeAddr;
reg [bitwidth-1:0] dout_reg;
wire willWrite;
wire willRead;
wire incCnt;
wire decCnt;
integer i;
assign dout = dout_reg;
assign full = full_reg;
assign itemcnt = cnt;
assign incCnt = willWrite && !willRead;
assign decCnt = willRead && !willWrite;
generate
if (isFwftMode == 1) begin : fwft_mode
wire fifo_re;
wire temp;
reg dout_valid;
assign temp = !dout_valid || re;
assign fifo_re = not_empty_reg && temp;
assign empty = !dout_valid;
assign willRead = not_empty_reg && fifo_re && en;
assign willWrite = (!full_reg || fifo_re) && we;
always @(`proclineg) begin
if (grst == `activehigh) dout_valid <= 0;
else if (rst == 1) dout_valid <= 0;
else begin
if (en) dout_valid <= not_empty_reg || (!temp);
end
end
end // fwft_mode
else
begin : normal_mode
assign empty = !(not_empty_reg);
assign willRead = not_empty_reg && re;
assign willWrite = (!full_reg || re) && we;
end // normal_mode
endgenerate
always @(`proclineg) begin : fifoProc
if (grst == `activehigh) begin
dout_reg <= {bitwidth{1'b0}};
full_reg <= 0;
not_empty_reg <= 0;
readAddr <= {adrWidth{1'b0}};
writeAddr <= {adrWidth{1'b0}};
cnt <= {cntwidth{1'b0}};
// synthesis loop_limit 65536
for (i = 0; i < depth; i = i + 1) fifoMem[i] <= 0;
end else if (rst == 1) begin
dout_reg <= {bitwidth{1'b0}};
full_reg <= 0;
not_empty_reg <= 0;
readAddr <= {adrWidth{1'b0}};
writeAddr <= {adrWidth{1'b0}};
cnt <= {cntwidth{1'b0}};
end else begin
if (willRead) begin
dout_reg <= fifoMem[readAddr];
if (readAddr == depth - 1) readAddr <= {adrWidth{1'b0}};
else readAddr <= readAddr + 1;
end
if (willWrite) begin
fifoMem[writeAddr] <= din;
if (writeAddr == depth - 1) writeAddr <= {adrWidth{1'b0}};
else writeAddr <= writeAddr + 1;
end
if ((cnt == depth && !decCnt) || (cnt == depth - 1 && incCnt)) full_reg <= 1;
else full_reg <= 0;
if ((cnt == 0 && !incCnt) || (cnt == 1 && decCnt)) not_empty_reg <= 0;
else not_empty_reg <= 1;
if (incCnt) cnt <= cnt + 1;
else if (decCnt) cnt <= cnt - 1;
end
end // fifoProc
endmodule
| 6.555056 |
module synFIFO_MC (
clk,
st,
din,
we,
re,
grst,
rst,
dout,
full,
empty,
itemcnt
);
parameter ch_no = 2;
parameter st_width = 1;
parameter bitwidth = 16;
parameter depth = 16;
parameter cntwidth = 5;
parameter adrWidth = 4;
parameter isFwftMode = 0;
input clk, grst, rst, we, re;
input [st_width-1:0] st;
input [bitwidth-1:0] din;
output full, empty;
output [bitwidth-1:0] dout;
output [cntwidth-1:0] itemcnt;
wire [ 0:ch_no-1] wes; //??please double check
wire [ 0:ch_no-1] res; //??please double check
wire [ 0:ch_no-1] rsts; //??please double check
wire [ 0:ch_no-1] fuls; //??please double check
wire [ 0:ch_no-1] emps; //??please double check
wire [ 0:ch_no-1] ens;
wire [bitwidth-1:0] out_buffer [0:ch_no-1];
wire [cntwidth-1:0] ics [0:ch_no-1];
assign dout = out_buffer[st];
assign full = fuls[st];
assign empty = emps[st];
assign itemcnt = ics[st];
generate
genvar i;
for (i = 0; i < ch_no; i = i + 1) begin : multiFifos
assign wes[i] = (st == i && we == 1) ? 1'b1 : 1'b0;
assign res[i] = (st == i && re == 1) ? 1'b1 : 1'b0;
assign rsts[i] = (st == i && rst == 1) ? 1'b1 : 1'b0;
assign ens[i] = (st == i) ? 1'b1 : 1'b0;
synFIFO #(
.bitwidth(bitwidth),
.depth(depth),
.cntwidth(cntwidth),
.adrWidth(adrWidth),
.isFwftMode(isFwftMode)
) myFIFO (
.clk(clk),
.din(din),
.en(ens[i]),
.we(wes[i]),
.re(res[i]),
.grst(grst),
.rst(rsts[i]),
.full(fuls[i]),
.empty(emps[i]),
.dout(out_buffer[i]),
.itemcnt(ics[i])
);
end
endgenerate
endmodule
| 6.772367 |
module synDownsampleSimple (
clk,
en,
grst,
inp,
outp
);
parameter bitwidth = 16;
input clk, grst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outreg;
wire [bitwidth-1:0] inp_ds;
reg [bitwidth-1:0] outp_ds /* synthesis syn_allow_retiming = 0 */;
assign inp_ds = inp;
assign outp = outp_ds;
always @(`proclineg) begin : nzp_proc
integer i;
if (grst == 1) outp_ds <= 0;
else if (en == 1) outp_ds <= inp_ds;
end // nzp
endmodule
| 7.63334 |
module SynPC (
input clk,
input rst_n,
input en,
input load_use,
//input halt,
input jp_success,
input [31:0] pc_new,
output [31:0] pc,
pc_4
);
reg [9:0] pc_simp;
wire [9:0] pc_4_simp = pc_simp + 1;
assign pc = {{20{1'b0}}, pc_simp, {2{1'b0}}};
assign pc_4 = {{20{1'b0}}, pc_4_simp, {2{1'b0}}};
always @(posedge clk, negedge rst_n) begin
if (!rst_n) pc_simp = 0;
else if (jp_success) pc_simp = pc_new[11:2];
else if (load_use) pc_simp = pc_simp;
else if (en) pc_simp = pc_4_simp;
end
endmodule
| 7.278982 |
module SynPiplIntf (
clk,
rst_n,
en,
nop,
data_i,
data_o
);
parameter NBit = 32;
input clk, rst_n, en, nop;
input [NBit - 1:0] data_i;
output reg [NBit - 1:0] data_o;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) data_o <= {NBit{1'b0}};
else if (en) begin
data_o <= nop ? {NBit{1'b0}} : data_i;
end
end
endmodule
| 7.587627 |
module SynPS2 (
input clk,
input rst_n,
input en,
input clear,
input [4:0] rd_in,
input regfile_w_en_in,
input r_datamem_in,
input [1:0] bht_state_in,
input is_branch_in,
output reg [4:0] rd,
output reg regfile_w_en,
output reg r_datamem,
output reg [1:0] bht_state,
output reg is_branch
);
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
rd <= 0;
regfile_w_en <= 0;
r_datamem <= 0;
bht_state <= 0;
is_branch <= 0;
end else if (!clear) begin
rd <= 0;
regfile_w_en <= 0;
r_datamem <= 0;
bht_state <= 0;
is_branch <= 0;
end else if (en) begin
rd <= rd_in;
regfile_w_en <= regfile_w_en_in;
r_datamem <= r_datamem_in;
bht_state <= bht_state_in;
is_branch <= is_branch_in;
end
end
endmodule
| 7.33424 |
module SynPS4 (
input clk,
input rst_n,
input en,
input clear,
input data_in,
input regfile_w_en_in,
input [4:0] regfile_req_w_in,
input r_datamem_in,
output reg data,
output reg regfile_w_en,
output reg [4:0] regfile_req_w,
output reg r_datamem
);
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data <= 0;
regfile_w_en <= 0;
regfile_req_w <= 0;
r_datamem <= 0;
end else if (!clear) begin
data <= 0;
regfile_w_en <= 0;
regfile_req_w <= 0;
r_datamem <= 0;
end else if (en) begin
data <= data_in;
regfile_w_en <= regfile_w_en_in;
regfile_req_w <= regfile_req_w_in;
r_datamem <= r_datamem_in;
end
end
endmodule
| 7.150542 |
module synqrst (
input wire clk,
input wire asynq_rst_n,
output wire synq_rst_n
);
reg [2:0] synq = 3'b000;
always @(posedge clk) begin
synq[2] <= synq[1];
synq[1] <= synq[0];
synq[0] <= asynq_rst_n;
end
assign synq_rst_n = synq[2];
endmodule
| 7.446645 |
module synrecounter10 (
input clk,
input reset, //synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0000;
else if (q == 4'b1001) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 7.096496 |
module synrecounter10_tb;
`define synrecounter10_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
synrecounter10 x_synrecounter10 (
.clk(clk),
.reset(reset),
.q(q)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
#5 reset <= 1'b0;
#5 `synrecounter10_TEST(8'd1, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd2, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd3, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter10_TEST(8'd4, 1'b1, 1'b0, 4'b0001);
#5 `synrecounter10_TEST(8'd5, 1'b0, 1'b0, 4'b0010);
#5 `synrecounter10_TEST(8'd6, 1'b1, 1'b0, 4'b0010);
#5 `synrecounter10_TEST(8'd7, 1'b0, 1'b0, 4'b0011);
#5 `synrecounter10_TEST(8'd8, 1'b1, 1'b0, 4'b0011);
#5 `synrecounter10_TEST(8'd9, 1'b0, 1'b0, 4'b0100);
#5 `synrecounter10_TEST(8'd10, 1'b1, 1'b0, 4'b0100);
#5 `synrecounter10_TEST(8'd11, 1'b0, 1'b0, 4'b0101);
#5 `synrecounter10_TEST(8'd12, 1'b1, 1'b0, 4'b0101);
#5 `synrecounter10_TEST(8'd13, 1'b0, 1'b0, 4'b0110);
#5 `synrecounter10_TEST(8'd14, 1'b1, 1'b0, 4'b0110);
#5 `synrecounter10_TEST(8'd15, 1'b0, 1'b0, 4'b0111);
#5 `synrecounter10_TEST(8'd16, 1'b1, 1'b0, 4'b0111);
#5 `synrecounter10_TEST(8'd17, 1'b0, 1'b0, 4'b1000);
#5 `synrecounter10_TEST(8'd18, 1'b1, 1'b0, 4'b1000);
#5 `synrecounter10_TEST(8'd19, 1'b0, 1'b0, 4'b1001);
#5 `synrecounter10_TEST(8'd20, 1'b1, 1'b0, 4'b1001);
#5 `synrecounter10_TEST(8'd21, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd22, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd23, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter10_TEST(8'd24, 1'b1, 1'b0, 4'b0001);
#5 reset <= 1'b1;
`synrecounter10_TEST(8'd25, 1'b0, 1'b0, 4'b0010);
#5 `synrecounter10_TEST(8'd26, 1'b1, 1'b1, 4'b0010);
#5 reset <= 1'b0;
`synrecounter10_TEST(8'd27, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd28, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter10_TEST(8'd29, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter10_TEST(8'd30, 1'b1, 1'b0, 4'b0001);
$display("Success!");
$finish;
end
endmodule
| 7.096496 |
module synrecounter15 (
input wire clk,
input wire reset, //synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 7.096496 |
module synrecounter15_tb;
`define synrecounter15_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
synrecounter15 x_synrecounter15 (
.clk(clk),
.reset(reset),
.q(q)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
#5 reset <= 1'b0;
#5 `synrecounter15_TEST(8'd1, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd2, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd3, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter15_TEST(8'd4, 1'b1, 1'b0, 4'b0001);
#5 `synrecounter15_TEST(8'd5, 1'b0, 1'b0, 4'b0010);
#5 `synrecounter15_TEST(8'd6, 1'b1, 1'b0, 4'b0010);
#5 `synrecounter15_TEST(8'd7, 1'b0, 1'b0, 4'b0011);
#5 `synrecounter15_TEST(8'd8, 1'b1, 1'b0, 4'b0011);
#5 `synrecounter15_TEST(8'd9, 1'b0, 1'b0, 4'b0100);
#5 `synrecounter15_TEST(8'd10, 1'b1, 1'b0, 4'b0100);
#5 `synrecounter15_TEST(8'd11, 1'b0, 1'b0, 4'b0101);
#5 `synrecounter15_TEST(8'd12, 1'b1, 1'b0, 4'b0101);
#5 `synrecounter15_TEST(8'd13, 1'b0, 1'b0, 4'b0110);
#5 `synrecounter15_TEST(8'd14, 1'b1, 1'b0, 4'b0110);
#5 `synrecounter15_TEST(8'd15, 1'b0, 1'b0, 4'b0111);
#5 `synrecounter15_TEST(8'd16, 1'b1, 1'b0, 4'b0111);
#5 `synrecounter15_TEST(8'd17, 1'b0, 1'b0, 4'b1000);
#5 `synrecounter15_TEST(8'd18, 1'b1, 1'b0, 4'b1000);
#5 `synrecounter15_TEST(8'd19, 1'b0, 1'b0, 4'b1001);
#5 `synrecounter15_TEST(8'd20, 1'b1, 1'b0, 4'b1001);
#5 `synrecounter15_TEST(8'd21, 1'b0, 1'b0, 4'b1010);
#5 `synrecounter15_TEST(8'd22, 1'b1, 1'b0, 4'b1010);
#5 `synrecounter15_TEST(8'd23, 1'b0, 1'b0, 4'b1011);
#5 `synrecounter15_TEST(8'd24, 1'b1, 1'b0, 4'b1011);
#5 `synrecounter15_TEST(8'd25, 1'b0, 1'b0, 4'b1100);
#5 `synrecounter15_TEST(8'd26, 1'b1, 1'b0, 4'b1100);
#5 `synrecounter15_TEST(8'd27, 1'b0, 1'b0, 4'b1101);
#5 `synrecounter15_TEST(8'd28, 1'b1, 1'b0, 4'b1101);
#5 `synrecounter15_TEST(8'd29, 1'b0, 1'b0, 4'b1110);
#5 `synrecounter15_TEST(8'd30, 1'b1, 1'b0, 4'b1110);
#5 `synrecounter15_TEST(8'd31, 1'b0, 1'b0, 4'b1111);
#5 `synrecounter15_TEST(8'd32, 1'b1, 1'b0, 4'b1111);
#5 `synrecounter15_TEST(8'd33, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd34, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd35, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter15_TEST(8'd36, 1'b1, 1'b0, 4'b0001);
#5 reset <= 1'b1;
`synrecounter15_TEST(8'd37, 1'b0, 1'b0, 4'b0010);
#5 `synrecounter15_TEST(8'd38, 1'b1, 1'b1, 4'b0000);
#5 reset <= 1'b0;
`synrecounter15_TEST(8'd39, 1'b0, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd40, 1'b1, 1'b0, 4'b0000);
#5 `synrecounter15_TEST(8'd41, 1'b0, 1'b0, 4'b0001);
#5 `synrecounter15_TEST(8'd42, 1'b1, 1'b0, 4'b0001);
$display("Success!");
$finish;
end
endmodule
| 7.096496 |
module synrefsm1 (
input wire clk,
input wire reset, //synchronous active-high reset
input wire in,
output reg out
);
reg state;
parameter A = 1'b0, B = 1'b1;
always @(posedge clk)
if (reset) begin
state <= B;
out <= 1'b1;
end else if (state == A) begin
if (in == 0) begin
state <= B;
out <= 1'b1;
end
if (in == 1) begin
state <= A;
out <= 1'b0;
end
end else begin
if (in == 0) begin
state <= A;
out <= 1'b0;
end
if (in == 1) begin
state <= B;
out <= 1'b1;
end
end
endmodule
| 7.067922 |
module synrefsm1_tb;
`define synrefsm1_TEST(ID, CLK, RESET, IN, OUT)\
clk=CLK;\
reset=RESET;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg in;
wire out;
synrefsm1 x_synrefsm1 (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
in <= 1'b1;
#5 reset <= 1'b0;
#5 `synrefsm1_TEST(8'd1, 1'b0, 1'b0, 1'b1, 1'b1);
#5 `synrefsm1_TEST(8'd2, 1'b1, 1'b0, 1'b1, 1'b1);
#5 in <= 1'b0;
`synrefsm1_TEST(8'd3, 1'b0, 1'b0, 1'b1, 1'b1);
#5 `synrefsm1_TEST(8'd4, 1'b1, 1'b0, 1'b0, 1'b1);
#5 in <= 1'b1;
`synrefsm1_TEST(8'd5, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `synrefsm1_TEST(8'd6, 1'b1, 1'b0, 1'b1, 1'b0);
#5 in <= 1'b0;
`synrefsm1_TEST(8'd7, 1'b0, 1'b0, 1'b1, 1'b0);
#5 `synrefsm1_TEST(8'd8, 1'b1, 1'b0, 1'b0, 1'b0);
#5 `synrefsm1_TEST(8'd9, 1'b0, 1'b0, 1'b0, 1'b1);
#5 in <= 1'b1;
reset <= 1'b1;
`synrefsm1_TEST(8'd10, 1'b1, 1'b0, 1'b0, 1'b1);
#5 `synrefsm1_TEST(8'd11, 1'b0, 1'b1, 1'b1, 1'b0);
#5 `synrefsm1_TEST(8'd12, 1'b1, 1'b1, 1'b1, 1'b0);
#5 `synrefsm1_TEST(8'd13, 1'b0, 1'b1, 1'b1, 1'b1);
$display("Success!");
$finish;
end
endmodule
| 7.227527 |
module synrefsm2 (
input wire clk,
input wire reset, //synchronous active-high reset
input wire j,
input wire k,
output reg out
);
reg state;
parameter ON = 1'b1, OFF = 1'b0;
always @(posedge clk)
if (reset) begin
state <= OFF;
out <= 1'b0;
end else if (state == OFF) begin
if (j == 1) begin
state <= ON;
out <= 1'b1;
end
if (j == 0) begin
state <= OFF;
out <= 1'b0;
end
end else begin
if (k == 0) begin
state <= ON;
out <= 1'b1;
end
if (k == 1) begin
state <= OFF;
out <= 1'b0;
end
end
endmodule
| 7.485647 |
module synrefsm2_tb;
`define synrefsm2_TEST(ID, CLK, RESET, J, K, OUT)\
clk=CLK;\
reset=RESET;\
j=J;\
k=K;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg j;
reg k;
wire out;
synrefsm2 x_synrefsm2 (
.clk(clk),
.reset(reset),
.j(j),
.k(k),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
j <= 1'b0;
k <= 1'b0;
#5 reset <= 1'b0;
#5 `synrefsm2_TEST(8'd1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `synrefsm2_TEST(8'd2, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0);
#5 j <= 1'b1;
`synrefsm2_TEST(8'd3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `synrefsm2_TEST(8'd4, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
#5 j <= 1'b0;
`synrefsm2_TEST(8'd5, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1);
#5 `synrefsm2_TEST(8'd6, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1);
#5 k <= 1'b1;
`synrefsm2_TEST(8'd7, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1);
#5 `synrefsm2_TEST(8'd8, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1);
#5 k <= 1'b0;
j <= 1'b1;
`synrefsm2_TEST(8'd9, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0);
#5 `synrefsm2_TEST(8'd10, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
#5 reset <= 1'b1;
j <= 1'b0;
`synrefsm2_TEST(8'd11, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1);
#5 `synrefsm2_TEST(8'd12, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1);
#5 `synrefsm2_TEST(8'd13, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0);
$display("Success!");
$finish;
end
endmodule
| 7.015763 |
module SynRegFile (
clk,
rst_n,
en,
w_en,
req_dbg,
req_w,
req_a,
req_b,
data_w,
data_dbg,
data_a,
data_b
);
input clk;
input rst_n;
input en;
input w_en;
input [4:0] req_dbg;
input [4:0] req_w;
input [4:0] req_a;
input [4:0] req_b;
input [31:0] data_w;
output [31:0] data_dbg;
output [31:0] data_a;
output [31:0] data_b;
reg [31:0] regs[31:1];
assign data_dbg = req_dbg == 0 ? 32'd0 : regs[req_dbg];
assign data_a = req_a == 0 ? 32'd0 : regs[req_a];
assign data_b = req_b == 0 ? 32'd0 : regs[req_b];
always @(negedge clk) begin
if (en && w_en && req_w != 5'd0) regs[req_w] <= data_w;
end
endmodule
| 7.308638 |
module synrevem (
input wire clk,
input wire rst, //synchronous active-high reset
input wire [1:0]in,
output reg [1:0]out
);
reg [2:0] cur_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always @(posedge clk)
if (rst) begin
cur_state <= s0;
out <= 2'b00;
end else cur_state <= next_state;
always @(cur_state)
case (cur_state)
s0: out = 2'b00;
s1: out = 2'b00;
s2: out = 2'b00;
s3: out = 2'b10;
s4: out = 2'b11;
default: out = 2'b00;
endcase
always @(cur_state, in[0], in[1])
case (cur_state)
s0: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
s1: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s2;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s3;
else next_state <= s0;
end
s2: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s2;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s3;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s4;
else next_state <= s0;
end
s3: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
s4: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
endcase
endmodule
| 8.320534 |
module synrevem_tb;
`define synrevem_TEST(ID, CLK, RST, IN, OUT)\
clk=CLK;\
rst=RST;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg rst;
reg [1:0] in;
wire [1:0] out;
synrevem x_synrevem (
.clk(clk),
.rst(rst),
.in (in),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
rst <= 1'b1;
in <= 2'b00;
#5 rst <= 1'b0;
#5 in <= 2'b01;
`synrevem_TEST(8'd1, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd2, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b01;
`synrevem_TEST(8'd3, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd4, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b01;
`synrevem_TEST(8'd5, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd6, 1'b1, 1'b0, 2'b01, 2'b00);
#5 `synrevem_TEST(8'd7, 1'b0, 1'b0, 2'b00, 2'b10);
#5 `synrevem_TEST(8'd8, 1'b1, 1'b0, 2'b00, 2'b10);
#5 in <= 2'b10;
`synrevem_TEST(8'd9, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd10, 1'b1, 1'b0, 2'b10, 2'b00);
#5 in <= 2'b10;
`synrevem_TEST(8'd11, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd12, 1'b1, 1'b0, 2'b10, 2'b00);
#5 `synrevem_TEST(8'd13, 1'b0, 1'b0, 2'b00, 2'b11);
#5 `synrevem_TEST(8'd14, 1'b1, 1'b0, 2'b00, 2'b11);
#5 in <= 2'b01;
`synrevem_TEST(8'd15, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd16, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b10;
`synrevem_TEST(8'd17, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd18, 1'b1, 1'b0, 2'b10, 2'b00);
#5 `synrevem_TEST(8'd19, 1'b0, 1'b0, 2'b00, 2'b10);
#5 `synrevem_TEST(8'd20, 1'b1, 1'b0, 2'b00, 2'b10);
#5 in <= 2'b10;
`synrevem_TEST(8'd21, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd22, 1'b1, 1'b0, 2'b10, 2'b00);
#5 in <= 2'b01;
`synrevem_TEST(8'd23, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`synrevem_TEST(8'd24, 1'b1, 1'b0, 2'b01, 2'b00);
#5 rst <= 1'b1;
`synrevem_TEST(8'd25, 1'b0, 1'b0, 2'b00, 2'b10);
#5 rst <= 1'b0;
`synrevem_TEST(8'd26, 1'b1, 1'b1, 2'b00, 2'b10);
#5 `synrevem_TEST(8'd27, 1'b0, 1'b0, 2'b00, 2'b00);
$display("Success!");
$finish;
end
endmodule
| 7.009266 |
module SynSyscall (
clk,
rst_n,
en,
syscall_en,
data_v0,
data_a0,
display,
halt
);
input clk;
input rst_n;
input en;
input syscall_en;
input [31:0] data_v0;
input [31:0] data_a0;
output reg [31:0] display;
output halt;
wire enabled = en && syscall_en;
assign halt = (enabled && data_v0 != 'd34) ? 1 : 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) display <= 0;
else if (enabled && data_v0 == 'd34) display <= data_a0;
end
endmodule
| 6.629811 |
module SynTestbed (
A,
B,
control,
Out,
flagout,
clk,
reset
);
input [`WIDTH-1:0] A, B;
input [`WCONTROL-1:0] control;
input clk;
input reset;
output [`WIDTH-1:0] Out;
output [`WFLAG-1:0] flagout;
wire [`WFLAG-1:0] flags;
reg [`WFLAG-1:0] flags2;
reg [`WCONTROL-1:0] control2;
wire [`WIDTH-1:0] C, D, X;
flop flopA (
clk,
reset,
A,
C
);
flop flopB (
clk,
reset,
B,
D
);
flop flopOut (
clk,
reset,
X,
Out
);
always @(posedge clk) control2 <= control;
fpmul multest (
C,
D,
X,
control2,
flags
);
always @(posedge clk) flags2 <= flags;
assign flagout = flags2;
endmodule
| 6.553513 |
module flop (
clk,
reset,
d,
q
);
input clk;
input reset;
input [31:0] d;
output [31:0] q;
reg [31:0] state;
always @(posedge clk or posedge reset) begin
if (reset) state <= #1 0;
else state <= #1 d;
end
assign #1 q = state;
endmodule
| 6.813917 |
module.
*HDL depends on other modules.
*It is
* spi_rx.v
* synth_arb.v
* operator.v
* -sine.v
* -diff_rom.v
* -sin_rom.v
* pwm_out.v
* fifo_tx.v(Altera QuartusII Megafunction IP dcfifo)
* pll.v(Altera QuartusII Megafunction IP altpll)
*
*External MicroController can controll module by 3wire-Serial interface like SPI(mode 0,0)
*
*Input Freq : 12.288MHz(XO or TCXO)
*
*PLL output Freq :
* C0 24.576MHz
* C1 196.608MHz
*/
module synth1(
input wire clk,
input wire reset_n,
input wire sdi,
input wire sck,
input wire ss_n,
output wire pwm_out_l,
output wire pwm_out_r,
input wire [3:0] gnd);
/*Signal Declaration*/
reg clr_reg1, clr_reg2;
wire clr_n, wrreq, wwreq2arb, rdreq, full, empty, clk_int, clk_ext;
wire [20:0] phase;
wire [15:0] data_out;
wire [31:0] data, fifo_in;
wire [7:0] synth_ctrl, synth_data, memadrs, memdata;
reg [7:0] clr_cnt = 8'h00;
/*End Declaration*/
/*Instantiation Modules*/
synth_arb arbiter(
.clk(clk_int),
.reset_n(clr_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wrreq2arb),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.fifo_full(full)
);
spi_rx spi_rx(
.clk(clk_int),
.reset_n(clr_n),
.sdi(sdi),
.sck(sck),
.ss_n(ss_n),
.adrs(memadrs),
.data(memdata),
.rx_valid(wrreq2arb));
pwm_out pwm_out(
.clk(clk_ext),
.reset_n(clr_n),
.fifo_rdreq(rdreq),
.fifo_empty(empty),
.fifo_data(data),
.pwm_out_r(pwm_out_r),
.pwm_out_l(pwm_out_l)
);
operator operator_1(
.clk(clk_int),
.reset_n(clr_n),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.data_out(data_out),
.wreq(wrreq));
fifo_tx fifo_tx (
.aclr ( clr ),
.data ( fifo_in ),
.rdclk ( clk_ext ),
.rdreq ( rdreq ),
.wrclk ( clk_int ),
.wrreq ( wrreq ),
.q ( data ),
.rdempty ( empty ),
.wrfull ( full )
);
pll pll (
.inclk0 ( clk ),
.c0 ( clk_int ),
.c1 ( clk_ext )
);
/*End Instantiation*/
/*Reset Logic*/
assign clr_n = clr_reg2 | (~&clr_cnt);
always @(posedge clk_int, negedge reset_n)
begin
if(!reset_n)
begin
clr_reg1 <= 0;
clr_reg2 <= 0;
end
else
begin
clr_reg1 <= 1;
clr_reg2 <= clr_reg1;
end
end
always @(posedge clk_int)
begin
if(clr_cnt == 8'hFF) clr_cnt <= clr_cnt;
else clr_cnt <= clr_cnt + 1;
end
/*Assign*/
assign fifo_in = {12'd0, gnd, data_out};
assign clr = ~clr_n;
endmodule
| 7.207867 |
module synth1_test();
`timescale 1ps / 1ps
reg clk, reset_n, ss_n, sck_r;
wire sdi, sck;
reg [15:0] shift_reg, add_reg;
assign sdi = shift_reg[15];
initial
begin
clk <= 0;
reset_n <= 0;
ss_n <= 0;
sck_r <= 1;
add_reg <= 16'h01AB;
shift_reg <= 16'h01AB;
#1000
reset_n <= 1;
end
parameter CLOCK_INT = 20;
always #(CLOCK_INT / 10) clk <= ~clk;
always #(CLOCK_INT / 2 ) if(reset_n)sck_r <= ~sck_r;
always @(posedge sck_r)
begin
if(!reset_n)
begin
shift_reg <= shift_reg;
end
else
begin
shift_reg <= {shift_reg[14:0], 1'b0};
end
end
synth1 s1(
.clk(clk),
.reset_n(reset_n),
.sdi(sdi),
.sck(sck_r),
.ss_n(ss_n),
.lrck(),
.sdo(),
.bck());
endmodule
| 6.946935 |
module adder_N #(
parameter N = 8
) (
input [N-1:0] ina,
inb,
input cin,
output [N-1:0] sum,
output cout
);
assign {cout, sum} = ina + inb + cin;
endmodule
| 7.024611 |
module compare_N #(
parameter N = 8
) (
input [N-1:0] a,
b, // Ƚ
output equal // ȽϽ
);
assign equal = (a == b) ? 1 : 0; //ȽϽ
endmodule
| 7.961439 |
module decoder3_8 (
input [2:0] in,
output [7:0] out
);
assign out = 1'b1 << in; //ݴinֵ,λ1ƶӦλ
endmodule
| 7.729152 |
module mux_N #(
parameter N = 8
) (
input [N-1:0] a,
b,
input sel,
output [N-1:0] out
);
//ʹassignselѡa,b
assign out = sel ? a : b; //selΪ1ʱoutΪaΪb
endmodule
| 6.786136 |
module mux_N2 #(
parameter N = 6
) (
input [N-1:0] a,
b,
input sel,
output reg [N-1:0] out
);
always @(*)
case (sel) //ʹif_elseźselֵ
1'b0: out = a;
1'b0: out = b;
default: out = a;
endcase
endmodule
| 6.757377 |
module tri_Gate #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
output [N-1:0] out
); //ʹassign״̬
assign out = enable ? in : 'bz;
endmodule
| 8.76848 |
module tri_Gate1 #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
output [N-1:0] out
); //bufif1һVerilogżԭ
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin : buf_test
bufif1 mybuf1 (out[i], in[i], enable);
end
endgenerate
endmodule
| 7.045924 |
module bidir #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
inout [N-1:0] tri_inout,
output [N-1:0] out
);
assign tri_inout = enable ? in : 'bz; //̬ŵΪin
assign out = tri_inout; //̬ŵ
endmodule
| 6.687599 |
module DFF_N #(
parameter N = 6
) (
input CLK,
input RESET_N,
input [N-1:0] D,
output reg [N-1:0] Q
);
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) Q <= 'h0;
else Q <= D;
endmodule
| 8.05977 |
module shiftReg_N #(
parameter N = 8
) (
input CLK,
RESET_N,
input din,
output reg [N-1:0] dout
);
always @(posedge CLK)
if (!RESET_N) //
dout <= 'b0;
else begin
dout[N-1:1] <= dout[N-2:0]; //һλ
dout[0] <= din; //źŷĴλ
end
endmodule
| 7.990468 |
module counter_N #(
parameter N = 16
) (
input clk,
input load,
input [N-1:0] data,
output reg [N-1:0] cnt,
output cout // ־
);
always @(posedge clk)
if (load) //źż
cnt <= data;
else cnt <= cnt + 1;
assign cout = &cnt;
endmodule
| 7.94355 |
module counter_N2 #(
parameter N = 16
) (
input clk,
input load,
input [N-1:0] data,
output reg [N-1:0] cnt,
output reg cout // ־
);
reg [N-1:0] preout; // FSMһ״̬ʱΪ
always @(posedge clk) cnt <= preout;
always @(*) begin
{cout, preout} = cnt + 1'b1; //λ
if (load) preout = data; //жϼź
end
endmodule
| 7.390396 |
module latch_N #(
parameter N = 16
) (
input clk,
input [N-1:0] d,
output [N-1:0] q
);
assign q = clk ? d : q; //ͨassign䣬ʵֵһ
endmodule
| 7.259438 |
module latch_N1 #(
parameter N = 16
) (
input clk,
input [N-1:0] d,
output reg [N-1:0] q
);
always @(*)
if (clk) //clkΪߵƽʱqdֵ
q = d;
endmodule
| 7.449385 |
module adderN #(
parameter N = 8
) (
input clk,
cin,
input [N-1:0] ina,
inb,
output reg [N-1:0] sum,
output reg cout
);
reg [7:0] tempa, tempb;
reg tempc;
always @(posedge clk) begin
tempa = ina;
tempb = inb;
tempc = cin; //
end
always @(posedge clk) begin
{cout, sum} = tempa + tempb + tempc;
end
endmodule
| 7.016561 |
module pipeline_adderN #(
parameter N = 8
) (
input clk,
cin,
input [N-1:0] ina,
inb,
output reg [N-1:0] sum,
output reg cout
);
reg [7:0] tempa, tempb;
reg tempci, firstco, secondco, thirdco;
reg [1:0] firsts, thirda, thirdb;
reg [3:0] seconda, secondb, seconds;
reg [5:0] firsta, firstb, thirds;
always @(posedge clk) begin
tempa = ina;
tempb = inb;
tempci = cin; //ݻ
end
always @(posedge clk) begin
{firstco, firsts} = tempa[1:0] + tempb[1:0] + tempci; //һӣ 2 λ
firsta = tempa[7:2]; //δμӼݻ
firstb = tempb[7:2];
end
always @(posedge clk) begin
//ڶӣ 23 λӣ
{secondco, seconds} = {firsta[1:0] + firstb[1:0] + firstco, firsts};
seconda = firsta[5:2]; //ݻ
secondb = firstb[5:2];
end
always @(posedge clk) begin //ӣ 45 λӣ
{thirdco, thirds} = {seconda[1:0] + secondb[1:0] + secondco, seconds};
thirda = seconda[3:2]; //ݻ
thirdb = secondb[3:2];
end
always @(posedge clk) begin //ļӣλӣ
{cout, sum} = {thirda[1:0] + thirdb[1:0] + thirdco, thirds};
end
endmodule
| 6.839437 |
module add_ahead #(
parameter N = 8
) (
input cin,
input [N-1:0] a,
b,
output [N-1:0] sum,
output cout
);
wire [N-1:0] G, P, C;
assign C[0] = cin;
assign cout = C[N-1];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin : adder_ahead
assign G[i] = a[i] & b[i]; //iλλֵ
assign P[i] = a[i] | b[i];
assign sum[i] = G[i] ^ P[i] ^ C[i];
end
for (i = 1; i < N; i = i + 1) begin : adder_carry
assign C[i] = G[i-1] | (P[i-1] & C[i-1]); //iλλֵ
end
endgenerate
endmodule
| 7.708081 |
module FSM (
input clk,
rst_n,
start,
step2,
step3,
output reg [2:0] out
);
reg [1:0] state, next_state;
localparam state0 = 2'b00, state1 = 2'b01, state2 = 2'b11, state3 = 2'b10;
always @(posedge clk or negedge rst_n) //FSM״̬
if (!rst_n) state <= state0;
else state <= next_state;
always @(*) // FSM һ״̬
case (state)
state0: begin
if (start) next_state <= state1;
else next_state <= state0;
end
state1: begin
next_state <= state2;
end
state2: begin
if (step2) next_state <= state3;
else next_state <= state0;
end
state3: begin
if (step3) next_state <= state0;
else next_state <= state3;
end
default: next_state <= state0;
endcase
always @(state) //ý̶FSM
case (state)
state0: out = 3'b001;
state1: out = 3'b010;
state2: out = 3'b100;
state3: out = 3'b111;
default: out = 3'b001;
endcase
endmodule
| 8.007563 |
module trigger #(
parameter wait_time = 12,
N = 5
) (
input clk,
input trig_in,
output trig_flag
);
reg [N-1:0] cnt;
reg state = 0; //
assign trig_flag = (cnt == 'b0) ? 1'b1 : 1'b0;
always @(posedge clk)
if (state == 0) cnt <= wait_time;
else if (state) cnt <= cnt - 1;
always @(posedge clk)
if (trig_flag) state <= 1'b0;
else if (trig_in) state <= 1'b1;
endmodule
| 6.963093 |
module edge_detect (
input clk,
input rst_n,
input trig_in,
output pos_edge,
output neg_edge
); //
//
reg trig_in_r0, trig_in_r1, trig_in_r2;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
trig_in_r0 <= 1'b0;
trig_in_r1 <= 1'b0;
trig_in_r2 <= 1'b0;
end else begin
trig_in_r0 <= trig_in;
trig_in_r1 <= trig_in_r0;
trig_in_r2 <= trig_in_r1;
end
assign pos_edge = trig_in_r1 & ~trig_in_r2;
assign neg_edge = ~trig_in_r1 & trig_in_r2;
endmodule
| 7.114144 |
module input16_mux (
A_0,
B_1,
Select,
Out
);
input [31:0] A_0, B_1;
input Select;
output [15:0] Out;
wire [31:0] A_0, B_1;
wire Select;
wire [15:0] Out;
wire n_0, n_3, n_4, n_5, n_17;
NAND2_X2 g184 (
.A1(n_5),
.A2(n_17),
.ZN(Out[1])
);
MUX2_X2 g194 (
.A(B_1[3]),
.B(A_0[3]),
.S(n_3),
.Z(Out[3])
);
OAI21_X2 g185 (
.A (n_4),
.B1(Select),
.B2(n_0),
.ZN(Out[0])
);
MUX2_X2 g193 (
.A(B_1[4]),
.B(A_0[4]),
.S(n_3),
.Z(Out[4])
);
MUX2_X2 g182 (
.A(A_0[2]),
.B(B_1[2]),
.S(Select),
.Z(Out[2])
);
NAND2_X2 g195 (
.A1(n_3),
.A2(A_0[1]),
.ZN(n_17)
);
MUX2_X2 g179 (
.A(A_0[15]),
.B(B_1[15]),
.S(Select),
.Z(Out[15])
);
MUX2_X2 g189 (
.A(A_0[14]),
.B(B_1[14]),
.S(Select),
.Z(Out[14])
);
MUX2_X2 g190 (
.A(A_0[13]),
.B(B_1[13]),
.S(Select),
.Z(Out[13])
);
MUX2_X2 g180 (
.A(A_0[12]),
.B(B_1[12]),
.S(Select),
.Z(Out[12])
);
MUX2_X2 g186 (
.A(A_0[11]),
.B(B_1[11]),
.S(Select),
.Z(Out[11])
);
MUX2_X2 g191 (
.A(A_0[10]),
.B(B_1[10]),
.S(Select),
.Z(Out[10])
);
MUX2_X2 g183 (
.A(A_0[8]),
.B(B_1[8]),
.S(Select),
.Z(Out[8])
);
MUX2_X2 g187 (
.A(A_0[7]),
.B(B_1[7]),
.S(Select),
.Z(Out[7])
);
MUX2_X2 g181 (
.A(A_0[9]),
.B(B_1[9]),
.S(Select),
.Z(Out[9])
);
MUX2_X2 g188 (
.A(A_0[6]),
.B(B_1[6]),
.S(Select),
.Z(Out[6])
);
MUX2_X2 g192 (
.A(A_0[5]),
.B(B_1[5]),
.S(Select),
.Z(Out[5])
);
NAND2_X2 g196 (
.A1(B_1[1]),
.A2(Select),
.ZN(n_5)
);
NAND2_X2 g197 (
.A1(B_1[0]),
.A2(Select),
.ZN(n_4)
);
INV_X2 g198 (
.A (Select),
.ZN(n_3)
);
INV_X2 g201 (
.A (A_0[0]),
.ZN(n_0)
);
endmodule
| 7.268914 |
module input5_mux (
A_0,
B_1,
Select,
Out
);
input [4:0] A_0, B_1;
input Select;
output [4:0] Out;
wire [4:0] A_0, B_1;
wire Select;
wire [4:0] Out;
MUX2_X2 g58 (
.A(A_0[4]),
.B(B_1[4]),
.S(Select),
.Z(Out[4])
);
MUX2_X2 g62 (
.A(A_0[2]),
.B(B_1[2]),
.S(Select),
.Z(Out[2])
);
MUX2_X2 g59 (
.A(A_0[1]),
.B(B_1[1]),
.S(Select),
.Z(Out[1])
);
MUX2_X2 g60 (
.A(A_0[0]),
.B(B_1[0]),
.S(Select),
.Z(Out[0])
);
MUX2_X2 g61 (
.A(A_0[3]),
.B(B_1[3]),
.S(Select),
.Z(Out[3])
);
endmodule
| 7.793605 |
module input16_mux (
A_0,
B_1,
Select,
Out
);
input [31:0] A_0;
input [31:0] B_1;
input Select;
output [15:0] Out;
// Internal wires
wire n_0;
wire n_3;
wire n_4;
wire n_5;
wire n_17;
NAND2_X2 g184 (
.A1(n_5),
.A2(n_17),
.ZN(Out[1])
);
MUX2_X2 g194 (
.A(B_1[3]),
.B(A_0[3]),
.S(n_3),
.Z(Out[3])
);
OAI21_X2 g185 (
.A (n_4),
.B1(Select),
.B2(n_0),
.ZN(Out[0])
);
MUX2_X2 g193 (
.A(B_1[4]),
.B(A_0[4]),
.S(n_3),
.Z(Out[4])
);
MUX2_X2 g182 (
.A(A_0[2]),
.B(B_1[2]),
.S(Select),
.Z(Out[2])
);
NAND2_X2 g195 (
.A1(n_3),
.A2(A_0[1]),
.ZN(n_17)
);
MUX2_X2 g179 (
.A(A_0[15]),
.B(B_1[15]),
.S(Select),
.Z(Out[15])
);
MUX2_X2 g189 (
.A(A_0[14]),
.B(B_1[14]),
.S(Select),
.Z(Out[14])
);
MUX2_X2 g190 (
.A(A_0[13]),
.B(B_1[13]),
.S(Select),
.Z(Out[13])
);
MUX2_X2 g180 (
.A(A_0[12]),
.B(B_1[12]),
.S(Select),
.Z(Out[12])
);
MUX2_X2 g186 (
.A(A_0[11]),
.B(B_1[11]),
.S(Select),
.Z(Out[11])
);
MUX2_X2 g191 (
.A(A_0[10]),
.B(B_1[10]),
.S(Select),
.Z(Out[10])
);
MUX2_X2 g183 (
.A(A_0[8]),
.B(B_1[8]),
.S(Select),
.Z(Out[8])
);
MUX2_X2 g187 (
.A(A_0[7]),
.B(B_1[7]),
.S(Select),
.Z(Out[7])
);
MUX2_X2 g181 (
.A(A_0[9]),
.B(B_1[9]),
.S(Select),
.Z(Out[9])
);
MUX2_X2 g188 (
.A(A_0[6]),
.B(B_1[6]),
.S(Select),
.Z(Out[6])
);
MUX2_X2 g192 (
.A(A_0[5]),
.B(B_1[5]),
.S(Select),
.Z(Out[5])
);
NAND2_X2 g196 (
.A1(B_1[1]),
.A2(Select),
.ZN(n_5)
);
NAND2_X2 g197 (
.A1(B_1[0]),
.A2(Select),
.ZN(n_4)
);
INV_X2 g198 (
.A (Select),
.ZN(n_3)
);
INV_X2 g201 (
.A (A_0[0]),
.ZN(n_0)
);
endmodule
| 7.268914 |
module input5_mux (
A_0,
B_1,
Select,
Out
);
input [4:0] A_0;
input [4:0] B_1;
input Select;
output [4:0] Out;
MUX2_X2 g58 (
.A(A_0[4]),
.B(B_1[4]),
.S(Select),
.Z(Out[4])
);
MUX2_X2 g62 (
.A(A_0[2]),
.B(B_1[2]),
.S(Select),
.Z(Out[2])
);
MUX2_X2 g59 (
.A(A_0[1]),
.B(B_1[1]),
.S(Select),
.Z(Out[1])
);
MUX2_X2 g60 (
.A(A_0[0]),
.B(B_1[0]),
.S(Select),
.Z(Out[0])
);
MUX2_X2 g61 (
.A(A_0[3]),
.B(B_1[3]),
.S(Select),
.Z(Out[3])
);
endmodule
| 7.793605 |
module synthesizer (
CLOCK_50,
CLOCK2_50,
KEY,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
AUD_XCK,
AUD_DACLRCK,
AUD_ADCLRCK,
AUD_BCLK,
AUD_ADCDAT,
AUD_DACDAT,
PS2_DAT,
PS2_CLK,
SW,
LEDR
);
input CLOCK_50, CLOCK2_50;
input [3:0] KEY;
input [9:0] SW;
// I2C Audio/Video config interface
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
//PS2 inputs
inout PS2_DAT;
inout PS2_CLK;
// Audio CODEC
output AUD_XCK;
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
input AUD_ADCDAT;
output AUD_DACDAT;
output [9:0] LEDR;
// Local wires.
wire read_ready, write_ready, read, write;
wire [23:0] readdata_left, readdata_right;
wire [23:0] writedata_left, writedata_right;
wire resetn = ~KEY[0];
wire keyboard_pushed = |kb;
wire load = ~KEY[1];
wire release_done;
wire out;
rate_divider_frequency rdf0 (
CLOCK_50,
resetn,
outkb,
out
);
assign LEDR[3:0] = shift_amount_out;
wire counter_clock;
wire load_a, load_d, load_s, load_r, load_p, load_amp, reset_p, reset_attack, preset_release;
wire [ 3:0] shift_amount_out;
wire [11:0] kb;
wire [31:0] outkb;
keyboard_tracker #(
.PULSE_OR_HOLD(0)
) kt0 (
.clock(CLOCK_50),
.reset(!resetn),
.PS2_CLK(PS2_CLK),
.PS2_DAT(PS2_DAT),
.a(kb[11]),
.w(kb[10]),
.s(kb[9]),
.e(kb[8]),
.d(kb[7]),
.f(kb[6]),
.t(kb[5]),
.g(kb[4]),
.y(kb[3]),
.h(kb[2]),
.u(kb[1]),
.j(kb[0])
);
Keyboard_LUT kbt (
CLOCK_50,
resetn,
kb,
outkb
);
control c0 (
.load(load),
.keyboard_pushed(keyboard_pushed),
.write_ready(write_ready),
.enable(out),
.release_done(release_done),
.clock(CLOCK_50),
.resetn(resetn),
.load_a(load_a),
.load_d(load_d),
.load_s(load_s),
.load_r(load_r),
.load_p(load_p),
.load_amp(load_amp),
.reset_p(reset_p),
.counter_clk(counter_clock),
.write(write),
.reset_attack(reset_attack),
.preset_release(preset_release),
.current_state_out()
);
datapath d0 (
.clk(CLOCK_50),
.counter_clock(counter_clock),
.resetn(resetn),
.offset(SW[7:4]),
.adsr_data_in(SW[3:0]),
.wave_select(SW[9:8]),
.keyboard_pushed(keyboard_pushed),
.load_a(load_a),
.load_d(load_d),
.load_s(load_s),
.load_r(load_r),
.load_p(load_p),
.load_amp(load_amp),
.reset_p(reset_p),
.reset_attack(reset_attack),
.preset_release(preset_release),
.amp_out(writedata_left),
.release_done(release_done),
.shift_amount_out(shift_amount_out),
.done_out(LEDR[6:4])
);
assign writedata_right = writedata_left;
/////////////////////////////////////////////////////////////////////////////////
// Audio CODEC interface.
//
// The interface consists of the following wires:
// read_ready, write_ready - CODEC ready for read/write operation
// readdata_left, readdata_right - left and right channel data from the CODEC
// read - send data from the CODEC (both channels)
// writedata_left, writedata_right - left and right channel data to the CODEC
// write - send data to the CODEC (both channels)
// AUD_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio CODEC
// I2C_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio/Video Config module
/////////////////////////////////////////////////////////////////////////////////
clock_generator my_clock_gen (
// inputs
CLOCK2_50,
resetn,
// outputs
AUD_XCK
);
audio_and_video_config cfg (
// Inputs
CLOCK_50,
resetn,
// Bidirectionals
FPGA_I2C_SDAT,
FPGA_I2C_SCLK
);
audio_codec codec (
// Inputs
CLOCK_50,
resetn,
read,
write,
writedata_left,
writedata_right,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
read_ready,
write_ready,
readdata_left,
readdata_right,
AUD_DACDAT
);
endmodule
| 7.72962 |
module control (
// ~KEY[1]
input load,
// ~KEY[3]
input keyboard_pushed,
input write_ready,
input enable,
input release_done,
input clock,
input resetn,
output reg load_a,
load_d,
load_s,
load_r,
load_p,
load_amp,
output reg reset_p,
output reg counter_clk,
output reg write,
output reg reset_attack,
preset_release,
output [3:0] current_state_out
);
reg [3:0] current_state, next_state;
assign current_state_out = current_state;
localparam
LOAD_ATTACK = 4'd0,
LOAD_ATTACK_WAIT = 4'd1,
LOAD_DECAY = 4'd2,
LOAD_DECAY_WAIT = 4'd3,
LOAD_SUSTAIN = 4'd4,
LOAD_SUSTAIN_WAIT = 4'd5,
LOAD_RELEASE = 4'd6,
LOAD_RELEASE_WAIT = 4'd7,
KEYBOARD_LISTEN = 4'd8,
LOAD_AMP_REG = 4'd9,
LISTEN_WRITE_READY = 4'd11,
WRITE_DATA = 4'd12,
UPDATE_PHASE = 4'd13;
// Next state logic aka our state table
always @(*) begin : state_table
case (current_state)
LOAD_ATTACK: next_state = load ? LOAD_ATTACK_WAIT : LOAD_ATTACK;
LOAD_ATTACK_WAIT: next_state = load ? LOAD_ATTACK_WAIT : LOAD_DECAY;
LOAD_DECAY: next_state = load ? LOAD_DECAY_WAIT : LOAD_DECAY;
LOAD_DECAY_WAIT: next_state = load ? LOAD_DECAY_WAIT : LOAD_SUSTAIN;
LOAD_SUSTAIN: next_state = load ? LOAD_SUSTAIN_WAIT : LOAD_SUSTAIN;
LOAD_SUSTAIN_WAIT: next_state = load ? LOAD_SUSTAIN_WAIT : LOAD_RELEASE;
LOAD_RELEASE: next_state = load ? LOAD_RELEASE_WAIT : LOAD_RELEASE;
LOAD_RELEASE_WAIT: next_state = load ? LOAD_RELEASE_WAIT : KEYBOARD_LISTEN;
KEYBOARD_LISTEN:
next_state = (keyboard_pushed || !release_done) ? LOAD_AMP_REG : KEYBOARD_LISTEN;
LOAD_AMP_REG: next_state = enable ? LISTEN_WRITE_READY : LOAD_AMP_REG;
LISTEN_WRITE_READY: next_state = write_ready ? WRITE_DATA : LISTEN_WRITE_READY;
WRITE_DATA: next_state = UPDATE_PHASE;
UPDATE_PHASE: next_state = KEYBOARD_LISTEN;
default: next_state = LOAD_ATTACK;
endcase
end
// Output logic for datapath control signals
always @(*) begin : enable_signals
// By default make all signals 0
load_a = 0;
load_d = 0;
load_s = 0;
load_r = 0;
load_p = 0;
load_amp = 0;
reset_p = 0;
counter_clk = 0;
write = 0;
reset_attack = 0;
preset_release = 0;
case (current_state)
LOAD_ATTACK: begin
reset_p = 1;
load_a = 1;
end
LOAD_ATTACK_WAIT: begin
load_a = 0;
end
LOAD_DECAY: begin
load_d = 1;
end
LOAD_DECAY_WAIT: begin
end
LOAD_SUSTAIN: begin
load_s = 1;
end
LOAD_SUSTAIN_WAIT: begin
end
LOAD_RELEASE: begin
load_r = 1;
end
LOAD_RELEASE_WAIT: begin
reset_attack = 1;
preset_release = 1;
end
KEYBOARD_LISTEN: begin
load_p = 1;
if (~keyboard_pushed) begin
reset_p = 1;
reset_attack = 1;
end
end
LOAD_AMP_REG: begin
load_amp = 1;
end
LISTEN_WRITE_READY: begin
end
WRITE_DATA: begin
write = 1;
end
UPDATE_PHASE: begin
counter_clk = 1;
end
endcase
end // enable_signals
// current_state registers
always @(posedge clock) begin : state_FFs
if (resetn) current_state <= LOAD_ATTACK;
else current_state <= next_state;
end // state_FFS
endmodule
| 7.715617 |
module datapath (
input clk,
input counter_clock,
input resetn,
input [3:0] offset,
input [3:0] adsr_data_in,
input [1:0] wave_select,
input keyboard_pushed,
input load_a,
load_d,
load_s,
load_r,
load_p,
load_amp,
input reset_p,
input reset_attack,
input preset_release,
output [23:0] amp_out,
output release_done,
output [3:0] shift_amount_out,
output [2:0] done_out
);
assign amp_out = amp;
assign shift_amount_out = shift_amount;
// input registers
reg [3:0] a, d, s, r;
reg [23:0] amp;
reg [ 7:0] phase;
wire [23:0] shifted_adsr_out;
wire [ 7:0] phase_counter_out;
// Registers with respective input logic
always @(posedge clk) begin
if (resetn) begin
a <= 4'd0;
d <= 4'd0;
s <= 4'd0;
r <= 4'd0;
amp <= 24'd0;
phase <= 8'd0;
end else begin
if (load_a) begin
a <= adsr_data_in;
end
if (load_d) begin
d <= adsr_data_in;
end
if (load_s) begin
s <= adsr_data_in;
end
if (load_r) begin
r <= adsr_data_in;
end
if (load_p) begin
phase <= phase_counter_out;
end
if (load_amp) begin
amp <= shifted_adsr_out;
end
end
end
phase_counter p0 (
counter_clock,
reset_p,
offset,
phase_counter_out
);
wire [15:0] wave_out_to_adsr;
wave_rom w0 (
clk,
wave_select,
phase,
wave_out_to_adsr
);
wire [15:0] adsr_out;
wire [3:0] shift_amount_a, shift_amount_d, shift_amount_r;
reg reset_decay, reset_release;
reg [3:0] shift_amount;
wire attack_done, decay_done;
always @(*) begin
if (!attack_done && keyboard_pushed) begin
reset_release = 1;
reset_decay = 1;
shift_amount = shift_amount_a;
end else if (!decay_done && keyboard_pushed) begin
reset_release = 1;
reset_decay = 0;
shift_amount = shift_amount_d;
end else if (keyboard_pushed) begin
reset_release = 1;
reset_decay = 0;
shift_amount = (4'd15 - s);
end else if (!release_done) begin
reset_release = 0;
reset_decay = 0;
shift_amount = shift_amount_r;
end else begin
shift_amount = 15;
reset_release = 0;
reset_decay = 0;
end
end
assign done_out = {attack_done, decay_done, release_done};
attack_shift_amount aso1 (
clk,
reset_attack,
a,
shift_amount_a,
attack_done
);
decay_shift_amount dso1 (
clk,
reset_decay,
0,
d,
s,
shift_amount_d,
decay_done
);
release_shift_amount rso1 (
clk,
reset_release,
preset_release,
r,
s,
shift_amount_r,
release_done
);
adsr_modification am1 (
wave_out_to_adsr,
shift_amount,
adsr_out
);
assign shifted_adsr_out = {8'b0, adsr_out} << 8;
endmodule
| 6.91752 |
module demux (
in0,
in1,
in2,
in3,
d0,
d1,
out
);
input in0, in1, in2, in3, d0, d1;
output out;
wire n1, n2;
MUX2X1 U26 (
.B(n1),
.A(n2),
.S(d1),
.Y(out)
);
MUX2X1 U27 (
.B(in2),
.A(in3),
.S(d0),
.Y(n2)
);
MUX2X1 U28 (
.B(in0),
.A(in1),
.S(d0),
.Y(n1)
);
endmodule
| 7.081334 |
module synthfilt (
input wire clk,
input wire rst,
input wire v,
input wire signed [15:0] x,
input wire signed [15:0] A0,
input wire signed [15:0] A1,
input wire signed [15:0] A2,
input wire signed [15:0] A3,
input wire signed [15:0] A4,
input wire signed [15:0] A5,
input wire signed [15:0] A6,
input wire signed [15:0] A7,
input wire signed [15:0] A8,
input wire signed [15:0] A9,
input wire signed [15:0] A10,
output reg signed [15:0] y,
output reg vout
);
reg signed [15:0] y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, x_tmp;
reg signed [31:0] y1_tmp, y2_tmp, y3_tmp, y4_tmp, y5_tmp, y6_tmp, y7_tmp, y8_tmp, y9_tmp, y10_tmp;
reg v1;
always @(posedge clk) begin
if (rst) begin
y <= 16'b0;
y1 <= 16'b0;
y2 <= 16'b0;
y3 <= 16'b0;
y4 <= 16'b0;
y5 <= 16'b0;
y6 <= 16'b0;
y7 <= 16'b0;
y8 <= 16'b0;
y9 <= 16'b0;
y10 <= 16'b0;
y1_tmp <= 16'b0;
y2_tmp <= 16'b0;
y3_tmp <= 16'b0;
y4_tmp <= 16'b0;
y5_tmp <= 16'b0;
y6_tmp <= 16'b0;
y7_tmp <= 16'b0;
y8_tmp <= 16'b0;
y9_tmp <= 16'b0;
y10_tmp <= 16'b0;
vout <= 1'b0;
v1 <= 1'b0;
x_tmp <= 1'b0;
end
if (v) begin
y1_tmp <= y1 * (* multstyle = "dsp" *) A1;
y2_tmp <= y2 * (* multstyle = "dsp" *) A2;
y3_tmp <= y3 * (* multstyle = "dsp" *) A3;
y4_tmp <= y4 * (* multstyle = "dsp" *) A4;
y5_tmp <= y5 * (* multstyle = "dsp" *) A5;
y6_tmp <= y6 * (* multstyle = "dsp" *) A6;
y7_tmp <= y7 * (* multstyle = "dsp" *) A7;
y8_tmp <= y8 * (* multstyle = "dsp" *) A8;
y9_tmp <= y9 * (* multstyle = "dsp" *) A9;
y10_tmp <= y10 * (* multstyle = "dsp" *) A10;
x_tmp <= x;
v1 <= 1'b1;
end else v1 <= 1'b0;
if (v1) begin
y <= (x_tmp - y1_tmp - y2_tmp - y3_tmp - y4_tmp - y5_tmp
- y6_tmp - y7_tmp - y8_tmp - y9_tmp - y10_tmp) >>> 14;
vout <= 1'b1;
end else vout <= 1'b0;
if (v || v1 || vout) begin
y1 <= x_tmp;
y2 <= y1;
y3 <= y2;
y4 <= y3;
y5 <= y4;
y6 <= y5;
y7 <= y6;
y8 <= y7;
y9 <= y8;
y10 <= y9;
end
end
endmodule
| 6.683529 |
module synthfilt_tb;
reg clk, rst, v;
reg signed [15:0] A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10;
wire signed [15:0] x, x1, y;
wire vout;
synthfilt synthfilt (
.clk(clk),
.rst(rst),
.v(v),
.x(x),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.A5(A5),
.A6(A6),
.A7(A7),
.A8(A8),
.A9(A9),
.A10(A10),
.y(y),
.vout(vout)
);
pulsegen pulsegen (
.clk(clk),
.rst(rst),
.v(v),
.pulserate(16'd4),
.lpcrate(16'd240),
.pulseout(x),
.vout(vout)
);
LFSR LFSR (
.clk (clk),
.rst (rst),
.d_out(x1)
);
initial begin
clk <= 1'b0;
rst <= 1'b0;
A0 <= 16'd8192;
A1 <= -16'd13493;
A2 <= -16'd6443;
A3 <= 16'd2996;
A4 <= -16'd789;
A5 <= -16'd3255;
A6 <= 16'd2701;
A7 <= -16'd2226;
A8 <= 16'd2985;
A9 <= -16'd1412;
A10 <= -16'd239;
end
always #10 clk = ~clk;
initial begin
repeat (3) @(posedge clk);
rst <= 1'b1;
@(posedge clk);
rst <= 1'b0;
repeat (2) @(posedge clk);
v <= 1'b1;
repeat (240) @(posedge clk);
v <= 1'b0;
repeat (3) @(posedge clk);
$stop;
end
endmodule
| 6.535263 |
module adder2bit (
a_in,
b_in,
o_sum
);
(* src = "adder2bit.v:4" *)
input [1:0] a_in;
(* src = "adder2bit.v:5" *)
input [1:0] b_in;
(* src = "adder2bit.v:6" *)
output [2:0] o_sum;
(* src = "adder2bit.v:9" *)
wire r_c0;
(* src = "adder2bit.v:10" *)
wire r_s1;
assign o_sum[0] = a_in[0] ^ (* src = "adder2bit.v:12" *) b_in[0];
assign r_c0 = a_in[0] & (* src = "adder2bit.v:13" *) b_in[0];
assign r_s1 = a_in[1] ^ (* src = "adder2bit.v:15" *) b_in[1];
assign o_sum[1] = r_s1 ^ (* src = "adder2bit.v:16" *) r_c0;
assign o_sum[2] = a_in[1] & (* src = "adder2bit.v:17" *) b_in[1];
endmodule
| 7.19208 |
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