code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IntSyncCrossingSource_16 (
input auto_in_3_0,
input auto_in_2_0,
input auto_in_1_0,
input auto_in_0_0,
output auto_out_3_sync_0,
output auto_out_2_sync_0,
output auto_out_1_sync_0,
output auto_out_0_sync_0
);
assign auto_out_3_sync_0 = auto_in_3_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_sync_0 = auto_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_sync_0 = auto_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_sync_0 = auto_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[SynchronizerReg.scala 51:87]
reg sync_2; // @[SynchronizerReg.scala 51:87]
assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 51:87]
sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
end else begin
sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
end else begin
sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 54:22]
sync_2 <= 1'h0;
end else begin
sync_2 <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
sync_0 = 1'h0;
end
if (reset) begin
sync_1 = 1'h0;
end
if (reset) begin
sync_2 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
| 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
.clock(io_out_source_valid_0_clock),
.reset(io_out_source_valid_0_reset),
.io_d (io_out_source_valid_0_io_d),
.io_q (io_out_source_valid_0_io_q)
);
assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:{24,24}]
assign io_out_source_valid_0_clock = clock;
assign io_out_source_valid_0_reset = reset;
assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
endmodule
| 6.70336 |
module BundleBridgeNexus_42 (
output [1:0] auto_out_3,
output [1:0] auto_out_2,
output [1:0] auto_out_1,
output [1:0] auto_out_0
);
wire [1:0] outputs_0 = 2'h0; // @[HasTiles.scala 161:32]
wire [1:0] outputs_1 = 2'h1; // @[HasTiles.scala 161:32]
wire [1:0] outputs_2 = 2'h2; // @[HasTiles.scala 161:32]
wire [1:0] outputs_3 = 2'h3; // @[HasTiles.scala 161:32]
assign auto_out_3 = outputs_3; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
assign auto_out_2 = outputs_2; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
assign auto_out_1 = outputs_1; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
assign auto_out_0 = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 2'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 2'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_17 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
AsyncResetRegVec_w2_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = {auto_in_1, auto_in_0}; // @[Cat.scala 31:58]
endmodule
| 6.689384 |
module AsyncResetRegVec_w8_i0 (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 8'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[7:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 8'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_29 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output auto_out_sync_2,
output auto_out_sync_3,
output auto_out_sync_4,
output auto_out_sync_5,
output auto_out_sync_6,
output auto_out_sync_7
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [7:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
wire [7:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
wire [3:0] lo = {auto_in_3, auto_in_2, auto_in_1, auto_in_0}; // @[Cat.scala 31:58]
wire [3:0] hi = {auto_in_7, auto_in_6, auto_in_5, auto_in_4}; // @[Cat.scala 31:58]
AsyncResetRegVec_w8_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
assign auto_out_sync_2 = reg__io_q[2]; // @[Crossing.scala 41:52]
assign auto_out_sync_3 = reg__io_q[3]; // @[Crossing.scala 41:52]
assign auto_out_sync_4 = reg__io_q[4]; // @[Crossing.scala 41:52]
assign auto_out_sync_5 = reg__io_q[5]; // @[Crossing.scala 41:52]
assign auto_out_sync_6 = reg__io_q[6]; // @[Crossing.scala 41:52]
assign auto_out_sync_7 = reg__io_q[7]; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = {hi, lo}; // @[Cat.scala 31:58]
endmodule
| 6.689384 |
module IntXbar (
input auto_int_in_0,
input auto_int_in_1,
input auto_int_in_2,
input auto_int_in_3,
input auto_int_in_4,
input auto_int_in_5,
input auto_int_in_6,
input auto_int_in_7,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_int_out_3,
output auto_int_out_4,
output auto_int_out_5,
output auto_int_out_6,
output auto_int_out_7
);
assign auto_int_out_0 = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_1 = auto_int_in_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_2 = auto_int_in_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_3 = auto_int_in_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_4 = auto_int_in_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_5 = auto_int_in_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_6 = auto_int_in_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_int_out_7 = auto_int_in_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.794458 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
output auto_out_2,
output auto_out_3,
output auto_out_4,
output auto_out_5,
output auto_out_6,
output auto_out_7
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire [7:0] chain_io_d; // @[ShiftReg.scala 45:23]
wire [7:0] chain_io_q; // @[ShiftReg.scala 45:23]
wire [3:0] chain_io_d_lo = {
auto_in_sync_3, auto_in_sync_2, auto_in_sync_1, auto_in_sync_0
}; // @[ShiftReg.scala 47:22]
wire [3:0] chain_io_d_hi = {
auto_in_sync_7, auto_in_sync_6, auto_in_sync_5, auto_in_sync_4
}; // @[ShiftReg.scala 47:22]
wire [7:0] _WIRE_1 = chain_io_q;
SynchronizerShiftReg_w8_d3 chain ( // @[ShiftReg.scala 45:23]
.clock(chain_clock),
.io_d (chain_io_d),
.io_q (chain_io_q)
);
assign auto_out_0 = _WIRE_1[0]; // @[ShiftReg.scala 48:24]
assign auto_out_1 = _WIRE_1[1]; // @[ShiftReg.scala 48:24]
assign auto_out_2 = _WIRE_1[2]; // @[ShiftReg.scala 48:24]
assign auto_out_3 = _WIRE_1[3]; // @[ShiftReg.scala 48:24]
assign auto_out_4 = _WIRE_1[4]; // @[ShiftReg.scala 48:24]
assign auto_out_5 = _WIRE_1[5]; // @[ShiftReg.scala 48:24]
assign auto_out_6 = _WIRE_1[6]; // @[ShiftReg.scala 48:24]
assign auto_out_7 = _WIRE_1[7]; // @[ShiftReg.scala 48:24]
assign chain_clock = clock;
assign chain_io_d = {chain_io_d_hi, chain_io_d_lo}; // @[ShiftReg.scala 47:22]
endmodule
| 6.70996 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.914809 |
module BroadcastFilter (
output io_request_ready,
input io_request_valid,
input [ 1:0] io_request_bits_mshr,
input [31:0] io_request_bits_address,
input io_request_bits_allocOH,
input io_request_bits_needT,
input io_response_ready,
output io_response_valid,
output [ 1:0] io_response_bits_mshr,
output [31:0] io_response_bits_address,
output io_response_bits_allocOH,
output io_response_bits_needT
);
assign io_request_ready = io_response_ready; // @[Broadcast.scala 362:20]
assign io_response_valid = io_request_valid; // @[Broadcast.scala 363:21]
assign io_response_bits_mshr = io_request_bits_mshr; // @[Broadcast.scala 365:28]
assign io_response_bits_address = io_request_bits_address; // @[Broadcast.scala 366:28]
assign io_response_bits_allocOH = io_request_bits_allocOH; // @[Broadcast.scala 368:28]
assign io_response_bits_needT = io_request_bits_needT; // @[Broadcast.scala 367:28]
endmodule
| 9.561359 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae_ptw,
input io_x_ae_final,
input io_x_pf,
input io_x_gf,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_ppp,
input io_x_pal,
input io_x_paa,
input io_x_eff,
input io_x_c,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae_ptw,
output io_y_ae_final,
output io_y_pf,
output io_y_gf,
output io_y_sw,
output io_y_sx,
output io_y_sr,
output io_y_pw,
output io_y_px,
output io_y_pr,
output io_y_ppp,
output io_y_pal,
output io_y_paa,
output io_y_eff,
output io_y_c
);
assign io_y_ppn = io_x_ppn; // @[package.scala 263:12]
assign io_y_u = io_x_u; // @[package.scala 263:12]
assign io_y_ae_ptw = io_x_ae_ptw; // @[package.scala 263:12]
assign io_y_ae_final = io_x_ae_final; // @[package.scala 263:12]
assign io_y_pf = io_x_pf; // @[package.scala 263:12]
assign io_y_gf = io_x_gf; // @[package.scala 263:12]
assign io_y_sw = io_x_sw; // @[package.scala 263:12]
assign io_y_sx = io_x_sx; // @[package.scala 263:12]
assign io_y_sr = io_x_sr; // @[package.scala 263:12]
assign io_y_pw = io_x_pw; // @[package.scala 263:12]
assign io_y_px = io_x_px; // @[package.scala 263:12]
assign io_y_pr = io_x_pr; // @[package.scala 263:12]
assign io_y_ppp = io_x_ppp; // @[package.scala 263:12]
assign io_y_pal = io_x_pal; // @[package.scala 263:12]
assign io_y_paa = io_x_paa; // @[package.scala 263:12]
assign io_y_eff = io_x_eff; // @[package.scala 263:12]
assign io_y_c = io_x_c; // @[package.scala 263:12]
endmodule
| 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8; // @[AMOALU.scala 66:20]
wire _logic_and_T = io_cmd == 5'ha; // @[AMOALU.scala 67:26]
wire logic_and = io_cmd == 5'ha | io_cmd == 5'hb; // @[AMOALU.scala 67:38]
wire logic_xor = io_cmd == 5'h9 | _logic_and_T; // @[AMOALU.scala 68:39]
wire _adder_out_mask_T_1 = ~io_mask[3]; // @[AMOALU.scala 72:63]
wire [31:0] _adder_out_mask_T_2 = {_adder_out_mask_T_1, 31'h0}; // @[AMOALU.scala 72:79]
wire [63:0] _adder_out_mask_T_3 = {{32'd0}, _adder_out_mask_T_2}; // @[AMOALU.scala 72:98]
wire [63:0] adder_out_mask = ~_adder_out_mask_T_3; // @[AMOALU.scala 72:16]
wire [63:0] _adder_out_T = io_lhs & adder_out_mask; // @[AMOALU.scala 73:13]
wire [63:0] _adder_out_T_1 = io_rhs & adder_out_mask; // @[AMOALU.scala 73:31]
wire [63:0] adder_out = _adder_out_T + _adder_out_T_1; // @[AMOALU.scala 73:21]
wire [4:0] _less_signed_T = io_cmd & 5'h2; // @[AMOALU.scala 86:17]
wire less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala 86:25]
wire _less_T_12 = io_lhs[31:0] < io_rhs[31:0]; // @[AMOALU.scala 79:35]
wire _less_T_14 = io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & _less_T_12; // @[AMOALU.scala 80:38]
wire _less_T_17 = less_signed ? io_lhs[63] : io_rhs[63]; // @[AMOALU.scala 88:58]
wire _less_T_18 = io_lhs[63] == io_rhs[63] ? _less_T_14 : _less_T_17; // @[AMOALU.scala 88:10]
wire _less_T_28 = less_signed ? io_lhs[31] : io_rhs[31]; // @[AMOALU.scala 88:58]
wire _less_T_29 = io_lhs[31] == io_rhs[31] ? _less_T_12 : _less_T_28; // @[AMOALU.scala 88:10]
wire less = io_mask[4] ? _less_T_18 : _less_T_29; // @[Mux.scala 47:70]
wire _minmax_T = less ? min : max; // @[AMOALU.scala 94:23]
wire [63:0] minmax = _minmax_T ? io_lhs : io_rhs; // @[AMOALU.scala 94:19]
wire [63:0] _logic_T = io_lhs & io_rhs; // @[AMOALU.scala 96:27]
wire [63:0] _logic_T_1 = logic_and ? _logic_T : 64'h0; // @[AMOALU.scala 96:8]
wire [63:0] _logic_T_2 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27]
wire [63:0] _logic_T_3 = logic_xor ? _logic_T_2 : 64'h0; // @[AMOALU.scala 97:8]
wire [63:0] logic_ = _logic_T_1 | _logic_T_3; // @[AMOALU.scala 96:42]
wire [63:0] _out_T_1 = logic_and | logic_xor ? logic_ : minmax; // @[AMOALU.scala 100:8]
wire [63:0] out = add ? adder_out : _out_T_1; // @[AMOALU.scala 99:8]
wire [7:0] _wmask_T_9 = io_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_11 = io_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_13 = io_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_15 = io_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_17 = io_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_19 = io_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_21 = io_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [7:0] _wmask_T_23 = io_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
wire [63:0] wmask = {
_wmask_T_23,
_wmask_T_21,
_wmask_T_19,
_wmask_T_17,
_wmask_T_15,
_wmask_T_13,
_wmask_T_11,
_wmask_T_9
}; // @[Cat.scala 31:58]
wire [63:0] _io_out_T = wmask & out; // @[AMOALU.scala 104:19]
wire [63:0] _io_out_T_1 = ~wmask; // @[AMOALU.scala 104:27]
wire [63:0] _io_out_T_2 = _io_out_T_1 & io_lhs; // @[AMOALU.scala 104:34]
assign io_out = _io_out_T | _io_out_T_2; // @[AMOALU.scala 104:25]
endmodule
| 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawA_isSpecial = rawA_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawA__isNaN = rawA_isSpecial & rawA_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire rawA__isInf = rawA_isSpecial & ~rawA_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
wire rawA__sign = io_a[64]; // @[rawFloatFromRecFN.scala 58:25]
wire [12:0] rawA__sExp = {1'b0, $signed(rawA_exp)}; // @[rawFloatFromRecFN.scala 59:27]
wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [53:0] rawA__sig = {1'h0, _rawA_out_sig_T, io_a[51:0]}; // @[Cat.scala 31:58]
wire [11:0] rawB_exp = io_b[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawB_isZero = rawB_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawB_isSpecial = rawB_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawB__isNaN = rawB_isSpecial & rawB_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire rawB__isInf = rawB_isSpecial & ~rawB_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
wire rawB__sign = io_b[64]; // @[rawFloatFromRecFN.scala 58:25]
wire [12:0] rawB__sExp = {1'b0, $signed(rawB_exp)}; // @[rawFloatFromRecFN.scala 59:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [53:0] rawB__sig = {1'h0, _rawB_out_sig_T, io_b[51:0]}; // @[Cat.scala 31:58]
wire ordered = ~rawA__isNaN & ~rawB__isNaN; // @[CompareRecFN.scala 57:32]
wire bothInfs = rawA__isInf & rawB__isInf; // @[CompareRecFN.scala 58:33]
wire bothZeros = rawA_isZero & rawB_isZero; // @[CompareRecFN.scala 59:33]
wire eqExps = $signed(rawA__sExp) == $signed(rawB__sExp); // @[CompareRecFN.scala 60:29]
wire common_ltMags = $signed(
rawA__sExp
) < $signed(
rawB__sExp
) | eqExps & rawA__sig < rawB__sig; // @[CompareRecFN.scala 62:33]
wire common_eqMags = eqExps & rawA__sig == rawB__sig; // @[CompareRecFN.scala 63:32]
wire _ordered_lt_T_1 = ~rawB__sign; // @[CompareRecFN.scala 67:28]
wire _ordered_lt_T_9 = _ordered_lt_T_1 & common_ltMags; // @[CompareRecFN.scala 70:41]
wire _ordered_lt_T_10 = rawA__sign & ~common_ltMags & ~common_eqMags | _ordered_lt_T_9; // @[CompareRecFN.scala 69:74]
wire _ordered_lt_T_11 = ~bothInfs & _ordered_lt_T_10; // @[CompareRecFN.scala 68:30]
wire _ordered_lt_T_12 = rawA__sign & ~rawB__sign | _ordered_lt_T_11; // @[CompareRecFN.scala 67:41]
wire ordered_lt = ~bothZeros & _ordered_lt_T_12; // @[CompareRecFN.scala 66:21]
wire ordered_eq = bothZeros | rawA__sign == rawB__sign & (bothInfs | common_eqMags); // @[CompareRecFN.scala 72:19]
wire _invalid_T_2 = rawA__isNaN & ~rawA__sig[51]; // @[common.scala 82:46]
wire _invalid_T_5 = rawB__isNaN & ~rawB__sig[51]; // @[common.scala 82:46]
wire _invalid_T_8 = io_signaling & ~ordered; // @[CompareRecFN.scala 76:27]
wire invalid = _invalid_T_2 | _invalid_T_5 | _invalid_T_8; // @[CompareRecFN.scala 75:58]
assign io_lt = ordered & ordered_lt; // @[CompareRecFN.scala 78:22]
assign io_eq = ordered & ordered_eq; // @[CompareRecFN.scala 79:22]
assign io_exceptionFlags = {invalid, 4'h0}; // @[Cat.scala 31:58]
endmodule
| 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RecFNToRecFN.scala 72:19]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RecFNToRecFN.scala 72:19]
wire [53:0] roundAnyRawFNToRecFN_io_in_sig; // @[RecFNToRecFN.scala 72:19]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RecFNToRecFN.scala 72:19]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RecFNToRecFN.scala 72:19]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RecFNToRecFN.scala 72:19]
wire [11:0] rawIn_exp = io_in[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawIn_isZero = rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
wire rawIn_isSpecial = rawIn_exp[11:10] == 2'h3; // @[rawFloatFromRecFN.scala 52:54]
wire rawIn__isNaN = rawIn_isSpecial & rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala 60:39]
wire [1:0] rawIn_out_sig_hi = {1'h0, _rawIn_out_sig_T}; // @[Cat.scala 31:58]
wire [53:0] rawIn__sig = {1'h0, _rawIn_out_sig_T, io_in[51:0]}; // @[Cat.scala 31:58]
RoundAnyRawFNToRecFN_3 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala 72:19]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RecFNToRecFN.scala 85:27]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RecFNToRecFN.scala 86:27]
assign roundAnyRawFNToRecFN_io_invalidExc = rawIn__isNaN & ~rawIn__sig[51]; // @[common.scala 82:46]
assign roundAnyRawFNToRecFN_io_in_isNaN = rawIn_isSpecial & rawIn_exp[9]; // @[rawFloatFromRecFN.scala 55:33]
assign roundAnyRawFNToRecFN_io_in_isInf = rawIn_isSpecial & ~rawIn_exp[9]; // @[rawFloatFromRecFN.scala 56:33]
assign roundAnyRawFNToRecFN_io_in_isZero = rawIn_exp[11:9] == 3'h0; // @[rawFloatFromRecFN.scala 51:54]
assign roundAnyRawFNToRecFN_io_in_sign = io_in[64]; // @[rawFloatFromRecFN.scala 58:25]
assign roundAnyRawFNToRecFN_io_in_sExp = {
1'b0, $signed(rawIn_exp)
}; // @[rawFloatFromRecFN.scala 59:27]
assign roundAnyRawFNToRecFN_io_in_sig = {rawIn_out_sig_hi, io_in[51:0]}; // @[Cat.scala 31:58]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RecFNToRecFN.scala 83:48]
endmodule
| 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN_4 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN_4 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module OptimizationBarrier_42 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_43 (
input [43:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [43:0] io_y_ppn,
output io_y_d,
output io_y_a,
output io_y_g,
output io_y_u,
output io_y_x,
output io_y_w,
output io_y_r,
output io_y_v
);
assign io_y_ppn = io_x_ppn; // @[package.scala 263:12]
assign io_y_d = io_x_d; // @[package.scala 263:12]
assign io_y_a = io_x_a; // @[package.scala 263:12]
assign io_y_g = io_x_g; // @[package.scala 263:12]
assign io_y_u = io_x_u; // @[package.scala 263:12]
assign io_y_x = io_x_x; // @[package.scala 263:12]
assign io_y_w = io_x_w; // @[package.scala 263:12]
assign io_y_r = io_x_r; // @[package.scala 263:12]
assign io_y_v = io_x_v; // @[package.scala 263:12]
endmodule
| 7.587549 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 173:39]
endmodule
| 6.820992 |
module IntSyncAsyncCrossingSink_1 (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.clock(chain_clock),
.io_d (chain_io_d),
.io_q (chain_io_q)
);
assign auto_out_0 = chain_io_q; // @[ShiftReg.scala 48:24]
assign chain_clock = clock;
assign chain_io_d = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 1'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala 89:21]
AsyncResetRegVec_w1_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module PLICFanIn (
input [2:0] io_prio_0,
input [2:0] io_prio_1,
input [2:0] io_prio_2,
input [2:0] io_prio_3,
input [2:0] io_prio_4,
input [2:0] io_prio_5,
input [2:0] io_prio_6,
input [2:0] io_prio_7,
input [7:0] io_ip,
output [3:0] io_dev,
output [2:0] io_max
);
wire [3:0] effectivePriority_1 = {io_ip[0], io_prio_0}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_2 = {io_ip[1], io_prio_1}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_3 = {io_ip[2], io_prio_2}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_4 = {io_ip[3], io_prio_3}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_5 = {io_ip[4], io_prio_4}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_6 = {io_ip[5], io_prio_5}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_7 = {io_ip[6], io_prio_6}; // @[Cat.scala 31:58]
wire [3:0] effectivePriority_8 = {io_ip[7], io_prio_7}; // @[Cat.scala 31:58]
wire _T = 4'h8 >= effectivePriority_1; // @[Plic.scala 345:20]
wire [3:0] _T_2 = _T ? 4'h8 : effectivePriority_1; // @[Misc.scala 34:9]
wire _T_3 = _T ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_4 = effectivePriority_2 >= effectivePriority_3; // @[Plic.scala 345:20]
wire [3:0] _T_6 = _T_4 ? effectivePriority_2 : effectivePriority_3; // @[Misc.scala 34:9]
wire _T_7 = _T_4 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_8 = _T_2 >= _T_6; // @[Plic.scala 345:20]
wire [1:0] _GEN_0 = {{1'd0}, _T_7}; // @[Plic.scala 345:61]
wire [1:0] _T_9 = 2'h2 | _GEN_0; // @[Plic.scala 345:61]
wire [3:0] _T_10 = _T_8 ? _T_2 : _T_6; // @[Misc.scala 34:9]
wire [1:0] _T_11 = _T_8 ? {{1'd0}, _T_3} : _T_9; // @[Misc.scala 34:36]
wire _T_12 = effectivePriority_4 >= effectivePriority_5; // @[Plic.scala 345:20]
wire [3:0] _T_14 = _T_12 ? effectivePriority_4 : effectivePriority_5; // @[Misc.scala 34:9]
wire _T_15 = _T_12 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_16 = effectivePriority_6 >= effectivePriority_7; // @[Plic.scala 345:20]
wire [3:0] _T_18 = _T_16 ? effectivePriority_6 : effectivePriority_7; // @[Misc.scala 34:9]
wire _T_19 = _T_16 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
wire _T_20 = _T_14 >= _T_18; // @[Plic.scala 345:20]
wire [1:0] _GEN_1 = {{1'd0}, _T_19}; // @[Plic.scala 345:61]
wire [1:0] _T_21 = 2'h2 | _GEN_1; // @[Plic.scala 345:61]
wire [3:0] _T_22 = _T_20 ? _T_14 : _T_18; // @[Misc.scala 34:9]
wire [1:0] _T_23 = _T_20 ? {{1'd0}, _T_15} : _T_21; // @[Misc.scala 34:36]
wire _T_24 = _T_10 >= _T_22; // @[Plic.scala 345:20]
wire [2:0] _GEN_2 = {{1'd0}, _T_23}; // @[Plic.scala 345:61]
wire [2:0] _T_25 = 3'h4 | _GEN_2; // @[Plic.scala 345:61]
wire [3:0] _T_26 = _T_24 ? _T_10 : _T_22; // @[Misc.scala 34:9]
wire [2:0] _T_27 = _T_24 ? {{1'd0}, _T_11} : _T_25; // @[Misc.scala 34:36]
wire _T_28 = _T_26 >= effectivePriority_8; // @[Plic.scala 345:20]
wire [3:0] maxPri = _T_28 ? _T_26 : effectivePriority_8; // @[Misc.scala 34:9]
assign io_dev = _T_28 ? {{1'd0}, _T_27} : 4'h8; // @[Misc.scala 34:36]
assign io_max = maxPri[2:0]; // @[Plic.scala 351:10]
endmodule
| 8.419901 |
module IntSyncCrossingSource_4 (
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[SynchronizerReg.scala 51:87]
reg sync_2; // @[SynchronizerReg.scala 51:87]
assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 51:87]
sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
end else begin
sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
end else begin
sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin // @[SynchronizerReg.scala 54:22]
sync_2 <= 1'h0;
end else begin
sync_2 <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
sync_0 = 1'h0;
end
if (reset) begin
sync_1 = 1'h0;
end
if (reset) begin
sync_2 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
assign output_chain_clock = clock;
assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
| 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
.clock(io_out_source_valid_0_clock),
.reset(io_out_source_valid_0_reset),
.io_d (io_out_source_valid_0_io_d),
.io_q (io_out_source_valid_0_io_q)
);
assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:{24,24}]
assign io_out_source_valid_0_clock = clock;
assign io_out_source_valid_0_reset = reset;
assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
endmodule
| 6.70336 |
module BundleBridgeNexus_15 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 2'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 2'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_5 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
AsyncResetRegVec_w2_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = {auto_in_1, auto_in_0}; // @[Cat.scala 31:58]
endmodule
| 6.689384 |
module AsyncResetRegVec_w8_i0 (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[AsyncResetReg.scala 65:16]
reg_ <= 8'h0; // @[AsyncResetReg.scala 66:9]
end else begin
reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[7:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 8'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module IntSyncCrossingSource_8 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output auto_out_sync_2,
output auto_out_sync_3,
output auto_out_sync_4,
output auto_out_sync_5,
output auto_out_sync_6,
output auto_out_sync_7
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [7:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
wire [7:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
wire [3:0] lo = {auto_in_3, auto_in_2, auto_in_1, auto_in_0}; // @[Cat.scala 31:58]
wire [3:0] hi = {auto_in_7, auto_in_6, auto_in_5, auto_in_4}; // @[Cat.scala 31:58]
AsyncResetRegVec_w8_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
.clock(reg__clock),
.reset(reg__reset),
.io_d (reg__io_d),
.io_q (reg__io_q)
);
assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
assign auto_out_sync_2 = reg__io_q[2]; // @[Crossing.scala 41:52]
assign auto_out_sync_3 = reg__io_q[3]; // @[Crossing.scala 41:52]
assign auto_out_sync_4 = reg__io_q[4]; // @[Crossing.scala 41:52]
assign auto_out_sync_5 = reg__io_q[5]; // @[Crossing.scala 41:52]
assign auto_out_sync_6 = reg__io_q[6]; // @[Crossing.scala 41:52]
assign auto_out_sync_7 = reg__io_q[7]; // @[Crossing.scala 41:52]
assign reg__clock = clock;
assign reg__reset = reset;
assign reg__io_d = {hi, lo}; // @[Cat.scala 31:58]
endmodule
| 6.689384 |
module wait_for_buffer_ready
(input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll_isbuffer,
output ready,
output busy
);
`define W 3
reg [`W-1:0] state;
parameter state_idle = `W'b000;
parameter state_databufrdy = `W'b001;
parameter state_wait_databufrdy = `W'b010;
`undef W
assign lladdr = state == state_databufrdy ? `ADDR_STATUSREG_15_0
: 7'h00;
assign llread = state == state_databufrdy;
assign llwrite = 1'b0;
assign ready = (state == state_wait_databufrdy) && llavail && llreaddata[5];
assign ll_isbuffer = 1'b0;
assign llwritedata = 16'h0;
assign busy = state != state_idle;
assign llreq = state != state_idle;
always @(posedge CLK or negedge RST)
begin
if (!RST)
state <= state_idle;
else
if (!llbusy) begin
case (state)
state_idle:
if (start)
state <= state_databufrdy;
state_databufrdy:
state <= state_wait_databufrdy;
state_wait_databufrdy:
if (llavail && llreaddata[5]) // Data buffer ready!
state <= state_idle;
else if (llavail)
state <= state_databufrdy; // Data buffer not ready...
default:; // impossible
endcase // case (state)
end
end // always @ (posedge CLK or negedge RST)
endmodule
| 8.414605 |
module read_data_buffer (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll_isbuffer,
output start_buffer_ready,
input buffer_ready,
input buffer_ready_busy,
output sysace_read_avail,
output busy
);
`define W 7
reg [`W-1:0] state;
parameter state_idle = `W'b000_0001;
parameter state_wait_for_buffer_ready = `W'b000_0010;
parameter state_consume = `W'b000_0100;
parameter state_transfer = `W'b000_1000;
parameter state_last_word = `W'b001_0000;
parameter state_blank_read = `W'b010_0000;
parameter state_blank = `W'b100_0000;
`undef W
reg [7:0] counter;
parameter max_counter = 8'd255;
reg [3:0] w_counter;
parameter max_w_counter = 4'd10;
assign llwrite = 1'b0;
assign llread = state == state_consume || state == state_transfer || state == state_blank_read;
assign llwritedata = 16'h0000;
assign lladdr = state == state_blank_read ? `ADDR_STATUSREG_15_0 : `ADDR_DATABUFREG_15_0;
assign ll_isbuffer = state != state_blank && state != state_blank_read;
assign busy = state != state_idle;
assign llreq = state != state_idle && state != state_wait_for_buffer_ready;
assign start_buffer_ready = state == state_wait_for_buffer_ready;
assign sysace_read_avail = (state == state_transfer || state == state_last_word) && llavail;
always @(posedge CLK or negedge RST) begin
if (!RST) state <= state_idle;
else
case (state)
state_idle: if (start) state <= state_wait_for_buffer_ready;
state_wait_for_buffer_ready: if (buffer_ready) state <= state_consume;
state_consume: if (llavail) state <= state_transfer;
state_transfer: if (counter == max_counter) state <= state_last_word;
state_last_word: if (llavail) state <= state_blank_read;
state_blank_read: if (w_counter == max_w_counter) state <= state_blank;
state_blank: if (w_counter == max_w_counter) state <= state_idle;
endcase // case (state)
end // always @ (posedge CLK or negedge RST)
always @(posedge CLK or negedge RST) begin
if (!RST) counter <= 8'h00;
else begin
case (state)
state_transfer: if (llavail) counter <= counter + 1;
default: counter <= 8'h00;
endcase // case (state)
end // else: !if(!RST)
end // always @ (posedge CLK or negedge RST)
always @(posedge CLK or negedge RST) begin
if (!RST) w_counter <= 4'd0;
else
case (state)
state_blank, state_blank_read:
if (w_counter == max_w_counter) w_counter <= 4'd0;
else w_counter <= w_counter + 4'd1;
default: w_counter <= 4'd0;
endcase // case (state)
end
endmodule
| 8.732224 |
module get_cf_lock (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll_isbuffer,
output busy
);
`define W 3
reg [`W-1:0] state;
parameter state_idle = `W'b000;
parameter state_lockreq = `W'b001;
parameter state_mpulock = `W'b010;
parameter state_wait_mpulock = `W'b100;
`undef W
assign llread = state == state_mpulock;
assign llwrite = state == state_lockreq;
assign llwritedata = 16'b0000_0000_0000_0010;
assign lladdr = state == state_lockreq ? `ADDR_CONTROLREG_15_0 :
state == state_mpulock ? `ADDR_STATUSREG_15_0 :
7'h00;
assign llreq = state != state_idle;
assign ll_isbuffer = 1'b0;
assign busy = state != state_idle;
always @(posedge CLK or negedge RST) begin
if (!RST) state <= state_idle;
else
case (state)
state_idle: if (start) state <= state_lockreq;
state_lockreq: if (!llbusy) state <= state_mpulock;
state_mpulock: if (!llbusy) state <= state_wait_mpulock;
state_wait_mpulock:
if (llavail && llreaddata[1]) state <= state_idle;
else if (llavail) state <= state_lockreq;
default: ;
endcase // case (state)
end
endmodule
| 8.434283 |
module check_if_ready_for_command (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll_isbuffer,
output busy
);
`define W 2
reg [`W-1:0] state;
parameter state_idle = `W'b00;
parameter state_rdyforcmd = `W'b01;
parameter state_wait_rdyforcmd = `W'b10;
`undef W
assign llread = state == state_rdyforcmd;
assign llwrite = 1'b0;
assign llwritedata = 16'h0000;
assign lladdr = `ADDR_STATUSREG_15_0;
assign llreq = state != state_idle;
assign ll_isbuffer = 1'b0;
assign busy = state != state_idle;
always @(posedge CLK or negedge RST) begin
if (!RST) state <= state_idle;
else
case (state)
state_idle: if (start) state <= state_rdyforcmd;
state_rdyforcmd: state <= state_wait_rdyforcmd;
state_wait_rdyforcmd:
if (llavail && llreaddata[8]) state <= state_idle;
else if (llavail) state <= state_rdyforcmd;
default: ;
endcase // case (state)
end
endmodule
| 8.306368 |
module SystemClockUnit ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP #(
.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (13),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm_sp_inst
// Input clock
(
.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180(),
.CLKFX (clkfx),
.CLKFX180(),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC(1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0)
);
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfb),
.I(clk0)
);
BUFG clkout1_buf (
.O(CLK_OUT1),
.I(clkfx)
);
endmodule
| 7.808239 |
module SystemClockUnit_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
SystemClockUnit clknetwork ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1(clk_int),
// Status and control signals
.LOCKED (LOCKED)
);
assign clk_n = ~clk;
ODDR2 clkout_oddr (
.Q (CLK_OUT[1]),
.C0(clk),
.C1(clk_n),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ{C_W{1'b0}};
end else begin
counter <= #TCQ counter + 1'b1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
| 7.808239 |
module SystemClockUnit_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
SystemClockUnit_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.808239 |
module SystemMonitor (
input wire clk,
input wire [6:0] DADDR_IN,
output wire DRDY_OUT,
output wire [15:0] DO_OUT
);
//wire [6:0] DADDR_IN;
wire DEN_IN, DWE_IN, VP_IN, VN_IN;
wire [15:0] DI_IN;
//assign DADDR_IN = 7'h00;
assign DEN_IN = 1'b1;
assign DWE_IN = 1'b0;
assign VP_IN = 1'b0;
assign VN_IN = 1'b0;
assign DI_IN = 16'h0000;
TemperatureMonitor SysMon1 (
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(clk),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
| 6.9415 |
module systemout (
clk,
RW,
WE,
result,
sysout,
notEqual
);
input [4:0] RW;
input WE, clk;
input [31:0] result;
output [31:0] sysout;
output notEqual;
reg [31:0] re2, re4;
initial begin
re2 <= 0;
re4 <= 0;
end
always @(posedge clk) begin
if (WE == 1) begin
if (RW == 2) re2 <= result;
if (RW == 4) re4 <= result;
end
end
assign notEqual = (re2 == 34) ? 0 : 1;
assign sysout = re4;
endmodule
| 6.546045 |
module systemTasks (
input [7:0] x,
output [7:0] z
);
assign z = ~x;
endmodule
| 6.857967 |
module systemTasks_tb ();
reg [7:0] x;
wire [7:0] z;
systemTasks DUT (
x,
z
);
initial begin
#0;
x = 8'd1;
$display("THIS IS A DISPLAY TASK x=%d \t\t z=%d t=%t", x, z,
$time); //Displayed in active region as integers
$monitor("THIS IS A MONITOR TASK x=%b \t z=%b t=%t", x, z,
$time); //Displayed in postpone region in binary radix every value is updated
#10;
x = 8'd2;
$display("THIS IS A DISPLAY TASK x=%c \t z=%c t=%t", x, z,
$time); //Displayed in active region as characters
#10;
x = 8'd4;
$strobe("THIS IS A STROBE TASK x=%b \t z=%b t=%t", x, z,
$time); //Displayed in postpone region in binary radix
#10;
x = 8'd8;
$strobe("THIS IS A STROBE TASK x=%H \t z=%H t=%t", x, z,
$time); //Displayed in postpone region in hex radix
#10;
x = 8'd16;
$write("THIS IS A WRITE TASK x=%H \t z=%H t=%t", x, z,
$time); //Displayed in active region in hex radix without new line
#10;
end
endmodule
| 8.118296 |
module wrapper (
input CLK,
input ASYNC_RST,
input ASYNC_CLK_DIV_RST,
inout SDA,
inout SCL,
output CS,
output DATA_OUT,
output [7:0] TEST_STATE,
output [7:0] TEST_ADC_OUT
);
//synchronize the clock reset
wire CLK_DIV_RST;
synchronizer clk_div_rst (
.clk(CLK),
.async_in(ASYNC_CLK_DIV_RST),
.Q(CLK_DIV_RST)
);
//divide the Clock
wire DIV_CLK;
divider clk_divider (
.clk(CLK),
.rst(CLK_DIV_RST),
.div_clk(DIV_CLK)
);
//sync RST
wire RST;
synchronizer rst_syncronize (
.clk(CLK),
.async_in(ASYNC_RST),
.Q(RST)
);
reg [15:0] data_transfer;
wire [7:0] ADC_data;
wire its_time;
ADC_CONTROL ADC (
.CLK(DIV_CLK),
.RST(RST),
.SDA(SDA),
.SCL(SCL),
.its_time(its_time), //to make sure the DAC only reads input when it needs to
.TEST_STATE(TEST_STATE), //TEST
.DATA_out(ADC_data) //this either changes every state_WACK or every state transition
);
always @(its_time) begin
if (its_time == 1'b1) begin
data_transfer = {ADC_data, 8'b0};
end
end
DAC_CONTROL DAC (
.data_in(data_transfer),
.clk(DIV_CLK),
.rst(RST),
.data_out(DATA_OUT),
.cs(CS)
);
//TEST
assign TEST_ADC_OUT = ADC_data;
endmodule
| 9.12716 |
module sys_wrap_TB ();
reg ASYNC_RST;
reg ASYNC_CLK_DIV_RST;
reg CLK;
//SDA
wire SDA;
reg output_value;
reg output_valid;
//ADC out
wire SCL;
wire CS;
wire DATA_OUT;
wire [7:0] TEST_STATE;
wire [7:0] TEST_ADC_OUT;
//divide the clock
wrapper UUT (
.CLK(CLK),
.ASYNC_CLK_DIV_RST(ASYNC_CLK_DIV_RST),
.ASYNC_RST(ASYNC_RST),
.SDA(SDA),
.SCL(SCL),
.CS(CS),
.DATA_OUT(DATA_OUT),
.TEST_STATE(TEST_STATE),
.TEST_ADC_OUT(TEST_ADC_OUT)
);
//these are to alternate the SDA input (so data_out is all 1's, all 0's, etc)
reg [2:0] count;
reg [7:0] addr = 8'b01010101;
assign SDA = (output_valid == 1'b1) ? output_value : 1'hz;
//when output_valid is 0, read, else write
always begin
#2 CLK = ~CLK;
end
always @(TEST_STATE) begin
if (TEST_STATE == 4) begin
output_valid = 1;
output_value = 1;
count = count + 1;
end else if (TEST_STATE == 5) begin
output_valid = 1;
output_value = addr[count];
end else begin
output_valid = 0;
output_value = 0;
count = count + 1;
end
end
initial begin
$dumpfile("sys_TB_dump.vcd");
$dumpvars;
end
initial begin
// ASYNC_CLK_DIV_RST = 1;
CLK = 1;
ASYNC_RST = 1;
output_value = 1;
count = 0;
ASYNC_CLK_DIV_RST = 1;
#200 ASYNC_CLK_DIV_RST = 0;
#20 ASYNC_RST = 0;
#5000 ASYNC_RST = 1;
#200 $stop;
end
endmodule
| 7.617219 |
module ISP1362_avalon_slave_1_arbitrator (
// inputs:
ISP1362_avalon_slave_1_irq_n,
clk,
reset_n,
// outputs:
ISP1362_avalon_slave_1_irq_n_from_sa
)
/* synthesis auto_dissolve = "FALSE" */;
output ISP1362_avalon_slave_1_irq_n_from_sa;
input ISP1362_avalon_slave_1_irq_n;
input clk;
input reset_n;
wire ISP1362_avalon_slave_1_irq_n_from_sa;
//assign ISP1362_avalon_slave_1_irq_n_from_sa = ISP1362_avalon_slave_1_irq_n so that symbol knows where to group signals which may go to master only, which is an e_assign
assign ISP1362_avalon_slave_1_irq_n_from_sa = ISP1362_avalon_slave_1_irq_n;
endmodule
| 7.851613 |
module system_0_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.04994 |
module system_0_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.04994 |
module system_0_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.04994 |
module system_0_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.04994 |
module system_0_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_0_onchip_memory2_0.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 51200,
the_altsyncram.numwords_a = 51200, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.558597 |
module system_0_switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [17:0] in_port;
input reset_n;
wire clk_en;
wire [17:0] data_in;
wire [17:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.720262 |
module system_AD (
input WE,
input [31:0] A,
output WEM,
output WE1,
output WE2,
output reg [1:0] RdSel
);
assign WE1 = (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'H08 && A[15:0] < 16'H900 && WE) ? 1 : 0;
assign WE2 = (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'H09 && WE) ? 1 : 0;
assign WEM = (A[15:8] < 32'H800 && WE) ? 1 : 0;
always @(A) begin
if (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'b00001000) RdSel <= 2'b10;
else if (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'b00001001) RdSel <= 2'b11;
else RdSel <= 2'b00;
end
endmodule
| 6.631674 |
module system_bus_access (
//AXI4-lite master memory interface
//AXI4-lite global signal
input ACLK,
input ARESETn,
//AXI4-lite Write Address Channel
output AWVALID,
input AWREADY,
output [`AXI_ADDR_WIDTH - 1 : 0] AWADDR,
output [ 2:0] AWPROT,
//AXI4-lite Write Data Channel
output WVALID,
input WREADY,
output [`AXI_DATA_WIDTH - 1 : 0] WDATA,
output [`AXI_STRB_WIDTH - 1 : 0] WSTRB,
//AXI4-lite Write Response Channel
input BVALID,
output BREADY,
input [1:0] BRESP,
//AXI4-lite Read Address Channel
output ARVALID,
input ARREADY,
output [`AXI_ADDR_WIDTH - 1 : 0] ARADDR,
output [ 2:0] ARPROT,
//AXI4-lite Read Data Channel
input RVALID,
output RREADY,
input [`AXI_DATA_WIDTH - 1 : 0] RDATA,
input [ 1:0] RRESP,
//dm global clock
input sys_clk,
input sys_rstn,
//interface with dm_regs block
input [`DM_REG_WIDTH - 1 : 0] sbaddress0,
input sbaddress0_update,
input [`DM_REG_WIDTH - 1 : 0] sbdata0,
input sbdata0_update,
input sbdata0_rd,
output [`DM_REG_WIDTH - 1 : 0] system_bus_read_data,
output system_bus_read_data_valid,
output sbbusy,
input sbreadonaddr,
input [ 2:0] sbaccess,
input sbreadondata,
output reg [ 2:0] sberror,
input [ 2:0] sberror_w1,
output reg sbbusyerror,
input sbbusyerror_w1
);
wire M_access;
wire ready_M;
wire[3:0] M_write_strobe;
wire M_rd0_wr1;
wire[`ADDR_WIDTH - 1 : 0] M_addr;
wire[`DATA_WIDTH - 1 : 0] M_write_data;
wire [`DATA_WIDTH - 1 : 0] read_data_M;
wire read_data_valid_M;
wire [1:0] resp_M;
axi_master DAXI_M (
.ACLK (ACLK ),
.ARESETn (ARESETn ),
.AWVALID (AWVALID ),
.AWREADY (AWREADY ),
.AWADDR (AWADDR ),
.AWPROT (AWPROT ),
.WVALID (WVALID ),
.WREADY (WREADY ),
.WDATA (WDATA ),
.WSTRB (WSTRB ),
.BVALID (BVALID ),
.BREADY (BREADY ),
.BRESP (BRESP ),
.ARVALID (ARVALID ),
.ARREADY (ARREADY ),
.ARADDR (ARADDR ),
.ARPROT (ARPROT ),
.RVALID (RVALID ),
.RREADY (RREADY ),
.RDATA (RDATA ),
.RRESP (RRESP ),
.cpu_clk (cpu_clk ),
.cpu_resetn (cpu_resetn ),
.M_access (M_access ),
.ready_M (ready_M ),
.M_write_strobe (M_write_strobe ),
.M_rd0_wr1 (M_rd0_wr1 ),
.M_addr (M_addr ),
.M_write_data (M_write_data ),
.read_data_M (read_data_M ),
.read_data_valid_M (read_data_valid_M ),
.resp_M (resp_M )
);
assign M_access = (sbdata0_rd || sbdata0_update || (sbaddress0_update && sbreadonaddr)) && !sbbusy;
assign M_write_strobe = 4'hf;
assign M_rd0_wr1 = sbdata0_update;
assign M_addr = sbaddress0;
assign M_write_data = sbdata0;
assign system_bus_read_data_valid = read_data_valid_M;
assign system_bus_read_data = read_data_M;
always @(posedge sys_clk or negedge sys_rstn) begin
if (!sys_rstn) begin
sbbusyerror <= 1'b0;
end else begin
if (sbbusyerror_w1) begin
sbbusyerror <= 1'b0;
end else if (sbbusy && (sbdata0_update || (sbaddress0_update && sbreadonaddr))) begin
sbbusyerror <= 1'b1;
end
end
end
integer i;
always @(posedge sys_clk or negedge sys_rstn) begin
if (!sys_rstn) begin
sberror <= 3'h0;
end else begin
if (|sberror_w1) begin
for (i = 0; i < 3; i = i + 1) begin
if (sberror_w1[i]) sberror[i] <= 1'b0;
end
end else if (M_access) begin
if (sbaccess > 3'b10) sberror <= 3'h4;
else sberror <= 3'h0;
end
end
end
endmodule
| 7.996618 |
module system_clk_reset_block (
input sys_clk,
input hard_resetn,
output hard_reset_n,
output hard_reset_p,
output sys_pll_clk_calc,
output sys_pll_clk_data,
output sys_pll_nios_clk,
output sys_pll_reset_n,
output sys_pll_locked
);
wire hard_reset_in_sync;
wire sig_hard_reset_n;
wire sig_hard_reset_p;
wire pll_locked;
wire sig_sys_pll_clkout0;
wire sig_sys_pll_clkout1;
wire sig_sys_pll_clkout2;
reset_block reset_block_inst0 (
.clk (sys_clk),
.en (hard_reset_in_sync),
.rst_n(sig_hard_reset_n),
.rst_p(sig_hard_reset_p)
);
reset_sync_block reset_sync_block_inst0 (
.clk (sys_clk),
.rst_n_in (hard_resetn),
.rst_n_out(hard_reset_in_sync)
);
iopll inst0_iopll (
.rst (sig_hard_reset_p), // reset.reset
.refclk (sys_clk), // refclk.clk
.locked (pll_locked), // locked.export
.outclk_0(sig_sys_pll_clkout0), // outclk0.clk
.outclk_1(sig_sys_pll_clkout1), // outclk1.clk
.outclk_2(sig_sys_pll_clkout2) // outclk1.clk
);
reset_sync_block reset_sync_block_inst1 (
.clk (sig_sys_pll_clkout0),
.rst_n_in (pll_locked),
.rst_n_out(sys_pll_reset_n)
);
// reset_sync_block reset_sync_block_inst2(
// .clk (sig_sys_pll_clkout1),
// .rst_n_in (pll_locked ),
// .rst_n_out ()
// );
assign hard_reset_n = sig_hard_reset_n;
assign hard_reset_p = sig_hard_reset_p;
assign sys_pll_locked = pll_locked;
assign sys_pll_clk_data = sig_sys_pll_clkout0;
assign sys_pll_clk_calc = sig_sys_pll_clkout1;
assign sys_pll_nios_clk = sig_sys_pll_clkout2;
endmodule
| 6.704873 |
module System_clk_wiz_0_0 (
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
System_clk_wiz_0_0_clk_wiz inst (
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
| 6.888088 |
module System_clk_wiz_0_0_clk_wiz ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in1_System_clk_wiz_0_0),
.I(clk_in1)
);
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_System_clk_wiz_0_0;
wire clkfbout_buf_System_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_System_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_System_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_System_clk_wiz_0_0),
.CLKIN1 (clk_in1_System_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high)
);
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfbout_buf_System_clk_wiz_0_0),
.I(clkfbout_System_clk_wiz_0_0)
);
BUFG clkout1_buf (
.O(clk_out1),
.I(clk_out1_System_clk_wiz_0_0)
);
endmodule
| 6.888088 |
module system_clk_wiz_0_0 (
clk_out1,
clk_out2,
resetn,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst (
.clk_in1 (clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.locked (locked),
.resetn (resetn)
);
endmodule
| 6.573608 |
module system_control (
input wb_clk_i,
output reg ram_loader_rst_o,
output reg wb_rst_o,
input ram_loader_done_i
);
reg POR = 1'b1;
reg [3:0] POR_ctr;
initial POR_ctr = 4'd0;
always @(posedge wb_clk_i)
if (POR_ctr == 4'd15) POR <= 1'b0;
else POR_ctr <= POR_ctr + 4'd1;
always @(posedge POR or posedge wb_clk_i)
if (POR) ram_loader_rst_o <= 1'b1;
else ram_loader_rst_o <= #1 1'b0;
// Main system reset
reg delayed_rst;
always @(posedge POR or posedge wb_clk_i)
if (POR) begin
wb_rst_o <= 1'b1;
delayed_rst <= 1'b1;
end else if (ram_loader_done_i) begin
delayed_rst <= 1'b0;
wb_rst_o <= delayed_rst;
end
endmodule
| 6.919572 |
module system_control_tb ();
reg aux_clk, clk_fpga;
wire wb_clk, dsp_clk;
wire wb_rst, dsp_rst, rl_rst, proc_rst;
reg rl_done, clock_ready;
initial aux_clk = 1'b0;
always #25 aux_clk = ~aux_clk;
initial clk_fpga = 1'b0;
initial clock_ready = 1'b0;
initial begin
@(negedge proc_rst);
#1003 clock_ready <= 1'b1;
end
always #7 clk_fpga = ~clk_fpga;
initial begin
$dumpfile("system_control_tb.vcd");
$dumpvars(0, system_control_tb);
end
initial #10000 $finish;
initial begin
@(negedge rl_rst);
rl_done <= 1'b0;
#1325 rl_done <= 1'b1;
end
initial begin
@(negedge proc_rst);
clock_ready <= 1'b0;
#327 clock_ready <= 1'b1;
end
system_control system_control (
.aux_clk_i(aux_clk),
.clk_fpga_i(clk_fpga),
.dsp_clk_o(dsp_clk),
.wb_clk_o(wb_clk),
.ram_loader_rst_o(rl_rst),
.processor_rst_o(proc_rst),
.wb_rst_o(wb_rst),
.dsp_rst_o(dsp_rst),
.ram_loader_done_i(rl_done),
.clock_ready_i(clock_ready),
.debug_o()
);
endmodule
| 6.919572 |
module system_crtl (
//clk interface
input clk,
input rst_n,
//global interface
output wire clk_24,
output wire clk_40, //90 degree
output wire clk_100,
output reg sys_rst_n
);
//--------------------------------
////Funtion : Ĵ
always @(posedge clk) begin
sys_rst_n <= rst_n;
end
//--------------------------------
////Funtion : pll crtl
pll_crtl pll_inst (
.refclk (clk), // refclk.clk
.rst (!sys_rst_n), // reset.reset
.outclk_0(clk_40), // outclk0.clk
.outclk_1(clk_24), // outclk1.clk
.outclk_2(clk_100),
.locked () // locked.export
);
endmodule
| 6.828106 |
module system_ctrl (
//global clock
input clk,
input rst_n,
//synced signal
output clk_ref, //clock output
output sys_rst_n //system reset
);
//----------------------------------------------
//rst_n sync, only controlled by the main clk
reg rst_nr1, rst_nr2;
always @(posedge clk) begin
if (!rst_n) begin
rst_nr1 <= 1'b0;
rst_nr2 <= 1'b0;
end else begin
rst_nr1 <= 1'b1;
rst_nr2 <= rst_nr1;
end
end
//----------------------------------
//component instantiation for system_delay
wire delay_done; //system init delay has done
system_init_delay #(
.SYS_DELAY_TOP(24'd2500000)
// .SYS_DELAY_TOP (24'd256) //Just for test
) u_system_init_delay (
//global clock
.clk(clk),
.rst_n(1'b1), //It don't depend on rst_n when power up
//system interface
.delay_done(delay_done)
);
assign clk_ref = clk;
assign sys_rst_n = rst_nr2 & delay_done; //active High
endmodule
| 7.861887 |
module system_ctrl_pll (
//globol clock
input clk,
input rst_n,
//synced signal
output sys_rst_n, //system reset
output clk_c0, //clock output
output clk_c1, //clock output
output clk_c2, //clock output
output clk_c3, //clock output
output clk_c4 //clock output
);
//----------------------------------
//component instantiation for system_delay
wire delay_done; //system init delay has done
system_init_delay #(
.SYS_DELAY_TOP(24'd2500000)
// .SYS_DELAY_TOP (24'd256) //Just for test
) u_system_init_delay (
//global clock
.clk(clk),
.rst_n(1'b1), //It don't depend on rst_n when power up
//system interface
.delay_done(delay_done)
);
wire pll_rst = ~delay_done; // ? ~locked : 1'b1; //PLL reset, H valid
//-----------------------------------
//system pll module
wire locked;
pll pll_inst (
.areset(pll_rst),
.inclk0(clk),
.c0(clk_c0),
.c1(clk_c1),
.c2(clk_c2),
.c3(clk_c3),
.c4(clk_c4),
.locked(locked)
);
/*
sys_pll u_sys_pll
(
.inclk0 (clk),
.areset (pll_rst),
.locked (locked),
.c0 (clk_c0),
.c1 (clk_c1),
.c2 (clk_c2),
.c3 (clk_c3)
// .c4 (clk_c4)
);
*/
wire clk_ref = clk_c0;
//----------------------------------------------
//rst_n sync, only controlled by the main clk
reg rst_nr1, rst_nr2;
always @(posedge clk_ref) begin
if (!rst_n) begin
rst_nr1 <= 1'b0;
rst_nr2 <= 1'b0;
end else begin
rst_nr1 <= 1'b1;
rst_nr2 <= rst_nr1;
end
end
assign sys_rst_n = rst_nr2 & locked; //active low
endmodule
| 7.076926 |
module DE1_system (
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3,
UART_TXD,
UART_RXD,
KEY,
SW,
CLOCK_50,
GPIO_0,
CLOCK_24,
TXB,
RXB
);
// Define System Abstraction
wire txU;
wire rxU;
wire [15:0] hexD;
wire clk; // System base-clock @ 50mhz
wire rst; // System wide reset
wire out;
// LEDs
// Switches
// Board Specific I/O
output [9:0] LEDR;
output [35:0] GPIO_0;
output TXB;
input RXB;
output [7:0] LEDG;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output UART_TXD;
input UART_RXD;
input [3:0] KEY;
input [9:0] SW;
input [1:0] CLOCK_24;
input CLOCK_50;
// Board Specific Assigns
assign clk = CLOCK_50;
assign rst = !KEY[0];
assign rxU = RXB;
assign TXB = txU;
SEG7_LUT hexLut0 (
.oSEG(HEX0[6:0]),
.iDIG(hexD[3:0])
);
SEG7_LUT hexLut1 (
.oSEG(HEX1[6:0]),
.iDIG(hexD[7:4])
);
SEG7_LUT hexLut2 (
.oSEG(HEX2[6:0]),
.iDIG(hexD[11:8])
);
SEG7_LUT hexLut3 (
.oSEG(HEX3[6:0]),
.iDIG(hexD[15:12])
);
//assign hexD[9:0] = SW[9:0];
assign LEDG[0] = clk;
assign LEDG[1] = rst;
assign GPIO_0[35] = out;
//assign out = ;
// Test Area
wire [7:0] r;
wire [7:0] g;
wire [7:0] b;
wire next;
wire done;
wire rst_led;
reg [23:0] color;
wire [15:0] ledNUM;
assign LEDR[0] = done;
assign rst_led = reset;
led_serializer ul0 (
.rst(rst_led),
.clk50(clk),
.r(SW[0] ? r : 8'd255),
.g(SW[1] ? g : 8'd255),
.b(SW[2] ? b : 8'd255),
.o(out),
.oNEXT(next),
.oDONE(done),
.oLED(ledNUM)
);
reg reset;
reg ledr;
assign LEDR[3] = ledr;
reg [16:0] seed;
assign hexD = 16'hbeef;
wire ser_clk;
//assign ser_clk = clk;
wire [15:0] ser_addr;
wire [7:0] ser_dta_out;
wire [7:0] ser_dta_in;
wire ser_write;
pll upll (
.areset(rst),
.inclk0(clk),
.c0(ser_clk),
.locked(LEDR[9])
);
assign LEDR[8] = ser_clk;
uart2bus_top(
.clock(ser_clk),
.reset(rst),
.ser_in(rxU),
.ser_out(txU),
.int_address(ser_addr),
.int_wr_data(ser_dta_in),
.int_write(ser_write),
.int_rd_data(ser_dta_out),
.int_gnt(1'b1)
);
bram_tdp u10 (
.a_clk (clk),
.a_wr (1'b0),
.a_addr(ledNUM),
.a_din (0),
.a_dout({r, g, b}),
.b_clk (ser_clk),
.b_wr (ser_write),
.b_addr(ser_addr[9:0]),
.b_din (ser_dta_in),
.b_dout(ser_dta_out)
);
/*
parameter DATA = 8,
parameter ADDR = 8
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
input clock; // global clock input
input reset; // global reset input
input ser_in; // serial data input
output ser_out; // serial data output
output [15:0] int_address; // address bus to register file
output [7:0] int_wr_data; // write data to register file
output int_write; // write control to register file
output int_read; // read control to register file
input [7:0] int_rd_data; // data read from register file
output int_req; // bus access request signal
input int_gnt; // bus access grant signal
);
*/
always @(posedge clk, posedge rst) begin
if (rst) begin
ledr <= 0;
//seed <= 0;
end else if (done) begin
reset <= 1'b1;
ledr <= 1;
//seed <= seed + 1;
end else begin
reset <= 1'b0;
// if (next) begin
// {r, g, b} <= color;
// end
end
end
endmodule
| 7.185585 |
module system_de2_tb ();
reg CLOCK_50;
reg [2:0] KEY; //last input
wire VGA_CLK; // VGA Clock
wire VGA_HS; // VGA H_SYNC
wire VGA_VS; // VGA V_SYNC
wire VGA_BLANK; // VGA BLANK
wire VGA_SYNC; // VGA SYNC
wire [9:0] VGA_R; // VGA Red[9:0]
wire [9:0] VGA_G; // VGA Green[9:0]
wire [9:0] VGA_B;
system_de2 system_de2_uut (
.CLOCK_50 (CLOCK_50),
.KEY (KEY),
.VGA_CLK (VGA_CLK), // VGA Clock
.VGA_HS (VGA_HS), // VGA H_SYNC
.VGA_VS (VGA_VS), // VGA V_SYNC
.VGA_BLANK(VGA_BLANK), // VGA BLANK
.VGA_SYNC (VGA_SYNC), // VGA SYNC
.VGA_R (VGA_R), // VGA Red[9:0]
.VGA_G (VGA_G), // VGA Green[9:0]
.VGA_B (VGA_B)
);
initial begin
CLOCK_50 = 0;
KEY = 3'd0;
#1000;
$stop;
end
endmodule
| 7.220196 |
module System_Delay #(
parameter SYS_DELAY_TOP = 24'd2500000 //50ms system init delay
) (
input clk_50m,
input rst_n,
output delay_done
);
reg [23:0] delay_cnt = 24'd0;
always @(posedge clk_50m or negedge rst_n) begin
if (!rst_n) delay_cnt <= 0;
else if (delay_cnt < SYS_DELAY_TOP - 1'b1) delay_cnt <= delay_cnt + 1'b1;
else delay_cnt <= SYS_DELAY_TOP - 1'b1;
end
assign delay_done = (delay_cnt == SYS_DELAY_TOP - 1'b1) ? 1'b1 : 1'b0;
endmodule
| 7.154635 |
module System_Index #(
parameter SYS_DELAY_TOP = 24'd2500000 //延时50ms
) (
input clk_50m,
input rst_n,
output clk_c0,
output sys_rst_n
);
//------------------------
//延时模块例化
wire delay_done; //system init delay has done
System_Delay #(
.SYS_DELAY_TOP(SYS_DELAY_TOP)
) u_System_Delay (
.clk_50m (clk_50m),
.rst_n (1'b1), //只有上电会延时，上电之后的复位不会延时
.delay_done(delay_done)
);
wire pll_rst = ~delay_done;
//------------------------------------------------
//PLL例化
wire locked;
PLL_0002 pll_inst (
.refclk(clk_50m), // refclk.clk
.rst (pll_rst), // reset.reset
.outclk_0(clk_c0), // outclk0.clk
.locked (locked) // locked.export
);
//----------------------------------------------
//异步复位同步释放模块例化
wire asy_rst_n;
Asy_Rst_Syn u_Asy_Rst_Syn (
.clk_50m(clk_50m),
.rst_n (rst_n),
.asy_rst_n(asy_rst_n)
);
//----------------------------------------------
//系统复位信号
assign sys_rst_n = asy_rst_n & locked;
endmodule
| 6.694612 |
module system_init_delay #(
parameter SYS_DELAY_TOP = 24'd2500000 //50ms system init delay
) (
//global clock
input clk, //50MHz
input rst_n,
//system interface
output delay_done
);
//------------------------------------------
//Delay 50ms for steady state when power on
reg [23:0] delay_cnt = 24'd0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) delay_cnt <= 0;
else if (delay_cnt < SYS_DELAY_TOP - 1'b1) delay_cnt <= delay_cnt + 1'b1;
else delay_cnt <= SYS_DELAY_TOP - 1'b1;
end
assign delay_done = (delay_cnt == SYS_DELAY_TOP - 1'b1) ? 1'b1 : 1'b0;
endmodule
| 6.721599 |
module system_m6502 (
input wire clk,
input wire reset_n,
output wire [7 : 0] leds
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter MEM_BASE_ADDR = 16'h0000;
parameter MEM_SIZE = 16'h03ff;
parameter IO_LED0_ADDR = 16'h1000;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [ 7 : 0] mem [0 : 1023];
reg mem_we;
reg [ 7 : 0] led0_reg;
reg [ 7 : 0] led0_new;
reg led0_we;
reg ready_reg;
reg valid_reg;
//----------------------------------------------------------------
// Wires for cpu connectivity.
//----------------------------------------------------------------
wire cpu_cs;
wire cpu_wr;
wire [15 : 0] cpu_address;
reg [ 7 : 0] cpu_read_data;
wire [ 7 : 0] cpu_write_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign leds = led0_reg;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
m6502 m6502_cpu (
.clk(clk),
.reset_n(reset_n),
.cs(cpu_cs),
.wr(cpu_wr),
.address(cpu_address),
.mem_ready(ready_reg),
.data_valid(valid_reg),
.read_data(cpu_read_data),
.write_data(cpu_write_data)
);
//----------------------------------------------------------------
// sync mem and I/O access.
// TODO Add I/O for reading pins.
//----------------------------------------------------------------
always @(posedge clk) begin : mem_io_update
integer i;
if (!reset_n) begin
led0_reg <= 8'h0;
for (i = 0; i <= MEM_SIZE; i = i + 1) mem[i] <= 8'h0;
end else begin
ready_reg <= 1;
valid_reg <= 0;
if ((cpu_address <= MEM_BASE_ADDR) && (cpu_address <= MEM_BASE_ADDR + MEM_SIZE)) begin
valid_reg <= 1;
cpu_read_data <= mem[cpu_address[9 : 0]];
if (cpu_wr) mem[cpu_address[9 : 0]] <= cpu_write_data;
end
if (cpu_address == IO_LED0_ADDR) begin
valid_reg <= 1;
cpu_read_data <= led0_reg;
if (cpu_wr) led0_reg <= cpu_write_data;
end
end
end // mem_io_update
endmodule
| 8.226803 |
module system_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [16:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//system_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
system_nios2_gen2_0_cpu_nios2_oci_td_mode system_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode (
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000000111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000111);
end
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.536019 |
module system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.594915 |
module system_RAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_RAM.hex";
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.730175 |
module system_reset_controller_tb;
// Parameters
localparam SYS_CLK_SPEED = 50000000;
localparam NO_OF_CLK_CYCLES = 20;
// Ports
reg clk = 0;
wire reset;
system_reset_controller #(
.NO_OF_CLK_CYCLES(NO_OF_CLK_CYCLES)
) system_reset_controller_dut (
.clk (clk),
.reset(reset)
);
initial begin
#1000;
end
always begin
#5 clk = !clk;
end
endmodule
| 6.554486 |
module system_rst_processing_system7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_rst_processing_system7_0_50M_0_proc_sys_reset U0 (
.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 6.740538 |
module system_rst_processing_system7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (asr_d1),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT1 #(
.INIT(2'h1)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 (
.I0(aux_reset_in),
.O (asr_d1)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_asr_i_1 (
.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O (lpf_asr_reg)
);
endmodule
| 6.740538 |
module system_rst_processing_system7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0] p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT2 #(
.INIT(4'hB)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 (
.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 )
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_exr_i_1 (
.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O (lpf_exr_reg)
);
endmodule
| 6.740538 |
module system_rst_processing_system7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0] p_3_out;
wire slowest_sync_clk;
system_rst_processing_system7_0_50M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX (
.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk)
);
system_rst_processing_system7_0_50M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT (
.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[1].asr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_in1_in),
.Q (p_2_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[2].asr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_2_in),
.Q (p_1_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[3].asr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_1_in),
.Q (asr_lpf),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[1].exr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[3]),
.Q (p_3_out[2]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[2].exr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[2]),
.Q (p_3_out[1]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[3].exr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[1]),
.Q (p_3_out[0]),
.R (1'b0)
);
(* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF)
) POR_SRL_I (
.A0 (1'b1),
.A1 (1'b1),
.A2 (1'b1),
.A3 (1'b1),
.CE (1'b1),
.CLK(slowest_sync_clk),
.D (1'b0),
.Q (Q)
);
FDRE #(
.INIT(1'b0)
) lpf_asr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q (lpf_asr),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) lpf_exr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q (lpf_exr),
.R (1'b0)
);
LUT4 #(
.INIT(16'hFFEF)
) lpf_int0 (
.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O (lpf_int0__0)
);
FDRE #(
.INIT(1'b0)
) lpf_int_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (lpf_int0__0),
.Q (lpf_int),
.R (1'b0)
);
endmodule
| 6.740538 |
module system_rst_processing_system7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0] bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0] interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_3),
.Q (interconnect_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_4),
.Q (peripheral_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \BSR_OUT_DFF[0].FDRE_BSR (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Bsr_out),
.Q (bus_struct_reset),
.R (1'b0)
);
system_rst_processing_system7_0_50M_0_lpf EXT_LPF (
.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) FDRE_inst (
.C (slowest_sync_clk),
.CE(1'b1),
.D (MB_out),
.Q (mb_reset),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \PR_OUT_DFF[0].FDRE_PER (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Pr_out),
.Q (peripheral_reset),
.R (1'b0)
);
system_rst_processing_system7_0_50M_0_sequence_psr SEQ (
.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 6.740538 |
module system_rst_processing_system7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1)
) \q_int[0]_i_1 (
.I0(Q[0]),
.O (q_int0[0])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6)
) \q_int[1]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.O (q_int0[1])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78)
) \q_int[2]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O (q_int0[2])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80)
) \q_int[3]_i_1 (
.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O (q_int0[3])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \q_int[4]_i_1 (
.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O (q_int0[4])
);
LUT1 #(
.INIT(2'h1)
) \q_int[5]_i_1 (
.I0(seq_clr),
.O (clear)
);
LUT6 #(
.INIT(64'h7FFFFFFF80000000)
) \q_int[5]_i_2 (
.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O (q_int0[5])
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[0] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[0]),
.Q (Q[0]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[1] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[1]),
.Q (Q[1]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[2] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[2]),
.Q (Q[2]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[3] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[3]),
.Q (Q[3]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[4] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[4]),
.Q (Q[4]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[5] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[5]),
.Q (Q[5]),
.R (clear)
);
endmodule
| 6.740538 |
module system_rst_ps7_0_100M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (asr_d1),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT1 #(
.INIT(2'h1)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 (
.I0(aux_reset_in),
.O (asr_d1)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_asr_i_1 (
.I0(lpf_asr),
.I1(p_1_in),
.I2(p_2_in),
.I3(scndry_out),
.I4(asr_lpf),
.O (lpf_asr_reg)
);
endmodule
| 7.106127 |
module system_rst_ps7_0_100M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_1_in4_in,
p_2_in3_in,
exr_lpf,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input p_1_in4_in;
input p_2_in3_in;
input [0:0] exr_lpf;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire exr_d1;
wire [0:0] exr_lpf;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire p_1_in4_in;
wire p_2_in3_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (exr_d1),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT2 #(
.INIT(4'hB)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 (
.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O (exr_d1)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_exr_i_1 (
.I0(lpf_exr),
.I1(p_1_in4_in),
.I2(p_2_in3_in),
.I3(scndry_out),
.I4(exr_lpf),
.O (lpf_exr_reg)
);
endmodule
| 7.106127 |
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