code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SYM_Mod (
input CLK_I,
RST_I,
input [5:0] DAT_I,
input CYC_I,
WE_I,
STB_I,
output ACK_O,
output reg [31:0] DAT_O,
output reg CYC_O,
STB_O,
output WE_O,
input ACK_I,
input [1:0] STD,
input [1:0] MOD
);
reg [5:0] idat_Q64;
reg [3:0] idat_Q16;
reg [1:0] idat_QPSK;
reg idat_BPSK;
reg ival;
wire out_halt, ena;
reg [15:0] datout_Re, datout_Im;
assign out_halt = STB_O & (~ACK_I);
assign ena = CYC_I & STB_I & WE_I;
assign ACK_O = ena & (~out_halt);
wire mod_q64_ena = (MOD == 2'b11);
wire mod_q16_ena = (MOD == 2'b10);
wire mod_qpsk_ena = (MOD == 2'b00);
wire mod_bpsk_ena = (MOD == 2'b01);
wire [5:0] datQ64_inv;
wire [3:0] datQ16_inv;
wire [1:0] datQPSK_inv;
assign datQ64_inv = ~{DAT_I[0], DAT_I[1], DAT_I[2], DAT_I[3], DAT_I[4], DAT_I[5]};
assign datQ16_inv = datQ64_inv[5:2];
assign datQPSK_inv = datQ64_inv[5:4];
wire wmax_ena = (STD == 2'b01);
always @(posedge CLK_I) begin
if (RST_I) idat_Q64 <= 6'b000000;
else if (ACK_O & mod_q64_ena) idat_Q64 <= (wmax_ena) ? datQ64_inv : DAT_I;
end
always @(posedge CLK_I) begin
if (RST_I) idat_Q16 <= 4'b0000;
else if (ACK_O & mod_q16_ena) idat_Q16 <= (wmax_ena) ? datQ16_inv : DAT_I[3:0];
end
always @(posedge CLK_I) begin
if (RST_I) idat_QPSK <= 2'b00;
else if (ACK_O & mod_qpsk_ena) idat_QPSK <= (wmax_ena) ? datQPSK_inv : DAT_I[1:0];
end
always @(posedge CLK_I) begin
if (RST_I) idat_BPSK <= 1'b0;
else if (ACK_O & mod_bpsk_ena) idat_BPSK <= (wmax_ena) ? (~DAT_I[0]) : DAT_I[0];
end
always @(posedge CLK_I) begin
if (RST_I) ival <= 1'b0;
else if (ena) ival <= 1'b1;
else ival <= 1'b0;
end
always @(posedge CLK_I) begin
if (RST_I) begin
STB_O <= 1'b0;
DAT_O <= 32'b0;
end else if (ival & (~out_halt)) begin
DAT_O <= {datout_Im, datout_Re};
STB_O <= 1'b1;
end else if (~ival) begin
STB_O <= 1'b0;
end
end
reg icyc;
always @(posedge CLK_I) begin
if (RST_I) icyc <= 1'b0;
else icyc <= CYC_I;
end
always @(posedge CLK_I) begin
if (RST_I) CYC_O <= icyc;
else CYC_O <= icyc;
end
assign WE_O = STB_O;
reg [15:0] Q64_Im, Q16_Im;
reg [15:0] Q64_Re, Q16_Re;
always @(*) begin
case (idat_Q64[5:3])
3'b000: Q64_Im = `Q64n7;
3'b100: Q64_Im = `Q64n5;
3'b110: Q64_Im = `Q64n3;
3'b010: Q64_Im = `Q64n1;
3'b011: Q64_Im = `Q64p1;
3'b111: Q64_Im = `Q64p3;
3'b101: Q64_Im = `Q64p5;
3'b001: Q64_Im = `Q64p7;
default: Q64_Im = 16'd0;
endcase
end
always @(*) begin
case (idat_Q64[2:0])
3'b000: Q64_Re = `Q64n7;
3'b100: Q64_Re = `Q64n5;
3'b110: Q64_Re = `Q64n3;
3'b010: Q64_Re = `Q64n1;
3'b011: Q64_Re = `Q64p1;
3'b111: Q64_Re = `Q64p3;
3'b101: Q64_Re = `Q64p5;
3'b001: Q64_Re = `Q64p7;
default: Q64_Re = 16'd0;
endcase
end
always @(*) begin
case (idat_Q16[3:2])
2'b00: Q16_Im = `Q16n3;
2'b10: Q16_Im = `Q16n1;
2'b11: Q16_Im = `Q16p1;
2'b01: Q16_Im = `Q16p3;
default: Q16_Im = 16'd0;
endcase
end
always @(*) begin
case (idat_Q16[1:0])
2'b00: Q16_Re = `Q16n3;
2'b10: Q16_Re = `Q16n1;
2'b11: Q16_Re = `Q16p1;
2'b01: Q16_Re = `Q16p3;
default: Q16_Re = 16'd0;
endcase
end
wire [15:0] QPSK_Re, BPSK_Re;
wire [15:0] QPSK_Im;
assign QPSK_Im = (idat_QPSK[1]) ? `QPSKp : `QPSKn;
assign QPSK_Re = (idat_QPSK[0]) ? `QPSKp : `QPSKn;
assign BPSK_Re = (idat_BPSK) ? 16'h7FFF : 16'h8001;
always @(*) begin
case (MOD)
2'b11: datout_Im = Q64_Im;
2'b10: datout_Im = Q16_Im;
2'b00: datout_Im = QPSK_Im;
2'b01: datout_Im = 16'd0;
default: datout_Im = 16'd0;
endcase
end
always @(*) begin
case (MOD)
2'b11: datout_Re = Q64_Re;
2'b10: datout_Re = Q16_Re;
2'b00: datout_Re = QPSK_Re;
2'b01: datout_Re = BPSK_Re;
default: datout_Re = 16'd0;
endcase
end
endmodule
| 6.895176 |
module MYMUL (
A,
B,
Y
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule
| 8.265005 |
module \$mul (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #(
.WIDTH(Y_WIDTH)
) g (
.A(A),
.B(B),
.Y(Y)
);
endmodule
| 7.524175 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other special number
//
always @(posedge clk)
expa_ff <= &expa;
always @(posedge clk)
expb_ff <= &expb;
always @(posedge clk)
infa_f_r <= !(|fracta);
always @(posedge clk)
infb_f_r <= !(|fractb);
always @(posedge clk)
qnan_r_a <= fracta[22];
always @(posedge clk)
snan_r_a <= !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= fractb[22];
always @(posedge clk)
snan_r_b <= !fractb[22] & |fractb[21:0];
always @(posedge clk)
ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= !(|expa);
always @(posedge clk)
expb_00 <= !(|expb);
always @(posedge clk)
fracta_00 <= !(|fracta);
always @(posedge clk)
fractb_00 <= !(|fractb);
always @(posedge clk)
opa_00 <= expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= expa_00;
always @(posedge clk)
opb_dn <= expb_00;
endmodule
| 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= #1 opa * opb;
always @(posedge clk) prod <= #1 prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module is designed for asynchronous clocks and transfers a one clock
// period long pulse from one clock domain to another. The maximum delay is
// one clock domain A period plus two clock domain B periods.
//
module syn2clk(
input a, // input
input aclk, // input clock
input arst, // reset input
output b, // output
input bclk, // output clock
input brst // reset output
);
// registers
reg t; // clock domain A
reg s0,s1,s2; // clock domain B
// flip-flop toggles when input logic one
always @ (posedge aclk)
begin
if (arst) t <= 1'b0; // reset for simulation
else if (a) t <= ~t; // toggle when enabled
// else t <= t^a;
end
// output logic synchronizes transition to output clock
// first flip-flop can enter meta-stable states
// second flip-flop waits for instablity to end
// third flip-flop and exclusive-or convert transition to logic one for one clock period
always @ (posedge bclk)
begin
if (brst) s0 <= 0;
else s0 <= t; // unstable
if (brst) s1 <= 0;
else s1 <= s0; // absorbs instability
if (brst) s2 <= 0;
else s2 <= s1; // for transition detection
end
assign b = s1 ^ s2; // create pulse
endmodule
| 7.589677 |
module is designed for asynchronous clocks and transfers a one clock
// period long pulse from one clock domain to another. The maximum delay is
// one clock domain A period plus two clock domain B periods. This version
// has an enable for the output clock.
//
module syn2clkoe(
input a, // input
input aclk, // input clock
input arst, // reset input
output b, // output
input boe, // output enable
input bclk, // output clock
input brst // reset output
);
// registers
reg t; // clock domain A
reg s0,s1,s2; // clock domain B
// flip-flop toggles when input logic one
always @ (posedge aclk)
begin
if (arst) t <= 1'b0; // reset for simulation
else if (a) t <= ~t; // toggle when enabled
// else t <= t^a;
end
// output logic synchronizes transition to output clock
// first flip-flop can enter meta-stable states
// second flip-flop waits for instablity to end
// third flip-flop and exclusive-or convert transition to logic one for one clock period
always @ (posedge bclk)
begin
if (brst) s0 <= 0;
else s0 <= t; // unstable
if (brst) s1 <= 0;
else if (boe) s1 <= s0; // absorbs instability
if (brst) s2 <= 0;
else if (boe) s2 <= s1; // for transition detection
end
assign b = s1 ^ s2; // create pulse
endmodule
| 7.589677 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other special number
//
always @(posedge clk)
expa_ff <= &expa;
always @(posedge clk)
expb_ff <= &expb;
always @(posedge clk)
infa_f_r <= !(|fracta);
always @(posedge clk)
infb_f_r <= !(|fractb);
always @(posedge clk)
qnan_r_a <= fracta[22];
always @(posedge clk)
snan_r_a <= !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= fractb[22];
always @(posedge clk)
snan_r_b <= !fractb[22] & |fractb[21:0];
always @(posedge clk)
ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= !(|expa);
always @(posedge clk)
expb_00 <= !(|expb);
always @(posedge clk)
fracta_00 <= !(|fracta);
always @(posedge clk)
fractb_00 <= !(|fractb);
always @(posedge clk)
opa_00 <= expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= expa_00;
always @(posedge clk)
opb_dn <= expb_00;
endmodule
| 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= #1 opa * opb;
always @(posedge clk) prod <= #1 prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module SynAddCounter (
clk,
reset,
dout
);
input clk, reset;
wire [3:0] Q;
output [6:0] dout;
wire T2, T3;
and T_2 (T2, Q[0], Q[1]);
and T_3 (T3, T2, Q[2]);
Tflip_flop Q_0 (
.T(1'b1),
.clk(clk),
.reset(reset),
.Q(Q[0])
);
Tflip_flop Q_1 (
.T(Q[0]),
.clk(clk),
.reset(reset),
.Q(Q[1])
);
Tflip_flop Q_2 (
.T(T2),
.clk(clk),
.reset(reset),
.Q(Q[2])
);
Tflip_flop Q_3 (
.T(T3),
.clk(clk),
.reset(reset),
.Q(Q[3])
);
BCD7 bcd7 (
.din (Q),
.dout(dout)
);
endmodule
| 7.005917 |
module SynAddCounter_tb;
reg clk, reset;
wire [6:0] dout;
initial begin
clk <= 0;
repeat (40) #55 clk <= ~clk;
end
initial begin
reset <= 0;
#10 reset <= ~reset;
#2000 reset <= ~reset;
#50 reset <= ~reset;
end
SynAddCounter synaddcounter (
.clk (clk),
.reset(reset),
.dout (dout)
);
endmodule
| 7.005917 |
module synapse #(
parameter p_width = 9,
parameter p_weight_width = 9
) (
input i_clk,
input i_rst_n,
input i_event,
input [ p_weight_width-1:0] i_weight,
output [ p_width -1:0] o_tr,
output [p_weight_width+p_width-1:0] o_cell_out
);
wire w_syncout;
wire [p_width-1:0] w_decaying;
wire w_rst;
synchronizer u_sync (
.i_event(i_event),
.i_clk(i_clk),
.i_rst_n(~w_rst),
.o_syncout(w_syncout)
);
leaky_accu #(
.p_base_width(p_width - 3)
) u_la (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_event(w_syncout),
.o_clr(w_rst),
.o_ln(w_decaying)
);
trace_reg #(
.p_width(p_width)
) u_tr (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_tr(w_decaying),
.o_tr(o_tr)
);
synaps_weight #(
.p_input_width (p_width),
.p_weight_width(p_weight_width)
) u_weights (
.i_synaps (w_decaying),
.i_weight (i_weight),
.o_cell_out(o_cell_out)
);
endmodule
| 7.703646 |
module synaps_weight #(
parameter p_input_width = 9,
parameter p_weight_width = 9
) (
input [ p_input_width -1:0] i_synaps,
input [ p_weight_width -1:0] i_weight,
output [p_weight_width + p_input_width -1 : 0] o_cell_out
);
assign o_cell_out = i_synaps * i_weight;
endmodule
| 7.23079 |
module SynapticIntegrationUnit #(
parameter INTEGER_WIDTH = 16,
parameter DATA_WIDTH_FRAC = 32,
parameter DATA_WIDTH = INTEGER_WIDTH + DATA_WIDTH_FRAC
) (
input wire signed [(DATA_WIDTH-1):0] gex,
input wire signed [(DATA_WIDTH-1):0] gin,
input wire signed [(DATA_WIDTH-1):0] ExWeightSum,
input wire signed [(DATA_WIDTH-1):0] InWeightSum,
output wire signed [(DATA_WIDTH-1):0] gexOut,
output wire signed [(DATA_WIDTH-1):0] ginOut
);
//Combinational Computation
assign gexOut = gex + ExWeightSum;
assign ginOut = gin + InWeightSum;
endmodule
| 8.293417 |
module
//
// Project: ODIN - An online-learning digital spiking neuromorphic processor
//
// Author: C. Frenkel, Université catholique de Louvain (UCLouvain), 04/2017
//
// Cite/paper: C. Frenkel, M. Lefebvre, J.-D. Legat and D. Bol, "A 0.086-mm² 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning
// Digital Spiking Neuromorphic Processor in 28-nm CMOS," IEEE Transactions on Biomedical Circuits and Systems,
// vol. 13, no. 1, pp. 145-158, 2019.
//
//------------------------------------------------------------------------------
module synaptic_core #(
parameter N = 256,
parameter M = 8
)(
// Global inputs ------------------------------------------
input wire RSTN_syncn,
input wire CLK,
// Inputs from SPI configuration registers ----------------
input wire SPI_GATE_ACTIVITY_sync,
input wire [ N-1:0] SPI_SYN_SIGN,
input wire SPI_UPDATE_UNMAPPED_SYN,
// Inputs from controller ---------------------------------
input wire [ 7:0] CTRL_PRE_EN,
input wire CTRL_BIST_REF,
input wire CTRL_SYNARRAY_WE,
input wire [ 12:0] CTRL_SYNARRAY_ADDR,
input wire CTRL_SYNARRAY_CS,
input wire [2*M-1:0] CTRL_PROG_DATA,
input wire [2*M-1:0] CTRL_SPI_ADDR,
// Inputs from neurons ------------------------------------
input wire [ N-1:0] NEUR_V_UP,
input wire [ N-1:0] NEUR_V_DOWN,
// Outputs ------------------------------------------------
output wire [ 31:0] SYNARRAY_RDATA,
output wire [ 31:0] SYNARRAY_WDATA,
output wire SYN_SIGN
);
// Internal regs and wires definitions
wire [ 31:0] SYNARRAY_WDATA_int;
wire [ N-1:0] NEUR_V_UP_int, NEUR_V_DOWN_int;
wire [ N-2:0] syn_sign_dummy;
genvar i;
// SDSP update logic
generate
for (i=0; i<8; i=i+1) begin
sdsp_update #(
.WIDTH(3)
) sdsp_update_gen (
// Inputs
// General
.SYN_PRE(CTRL_PRE_EN[i] & (SPI_UPDATE_UNMAPPED_SYN | SYNARRAY_RDATA[(i<<2)+3])),
.SYN_BIST_REF(CTRL_BIST_REF),
// From neuron
.V_UP(NEUR_V_UP_int[i]),
.V_DOWN(NEUR_V_DOWN_int[i]),
// From SRAM
.WSYN_CURR(SYNARRAY_RDATA[(i<<2)+3:(i<<2)]),
// Output
.WSYN_NEW(SYNARRAY_WDATA_int[(i<<2)+3:(i<<2)])
);
end
endgenerate
assign NEUR_V_UP_int = NEUR_V_UP >> ({3'b0,CTRL_SYNARRAY_ADDR[4:0]} << 3);
assign NEUR_V_DOWN_int = NEUR_V_DOWN >> ({3'b0,CTRL_SYNARRAY_ADDR[4:0]} << 3);
// Updated or configured weights to be written to the synaptic memory
generate
for (i=0; i<4; i=i+1) begin
assign SYNARRAY_WDATA[(i<<3)+7:(i<<3)] = SPI_GATE_ACTIVITY_sync
?
((i == CTRL_SPI_ADDR[14:13])
? ((CTRL_PROG_DATA[M-1:0] & ~CTRL_PROG_DATA[2*M-1:M]) | (SYNARRAY_RDATA[(i<<3)+7:(i<<3)] & CTRL_PROG_DATA[2*M-1:M]))
: SYNARRAY_RDATA[(i<<3)+7:(i<<3)])
: SYNARRAY_WDATA_int[(i<<3)+7:(i<<3)];
end
endgenerate
// Synaptic memory wrapper
SRAM_8192x32_wrapper synarray_0 (
// Global inputs
.RSTN (RSTN_syncn),
.CK (CLK),
// Control and data inputs
.CS (CTRL_SYNARRAY_CS),
.WE (CTRL_SYNARRAY_WE),
.A (CTRL_SYNARRAY_ADDR),
.D (SYNARRAY_WDATA),
// Data output
.Q (SYNARRAY_RDATA)
);
assign {syn_sign_dummy,SYN_SIGN} = SPI_SYN_SIGN >> CTRL_SYNARRAY_ADDR[12:5];
endmodule
| 7.855863 |
module SRAM_8192x32_wrapper (
// Global inputs
input RSTN, // Reset
input CK, // Clock (synchronous read/write)
// Control and data inputs
input CS, // Chip select (active low) (init low)
input WE, // Write enable (active low)
input [12:0] A, // Address bus
input [31:0] D, // Data input bus (write)
// Data output
output [31:0] Q // Data output bus (read)
);
/*
* Simple behavioral code for simulation, to be replaced by a 8192-word 32-bit SRAM macro
* or Block RAM (BRAM) memory with the same format for FPGA implementations.
*/
reg [31:0] SRAM[8191:0];
reg [31:0] Qr;
always @(posedge CK) begin
Qr <= CS ? SRAM[A] : Qr;
if (CS & WE) SRAM[A] <= D;
end
assign Q = Qr;
endmodule
| 7.469494 |
module sync (
////////// inputs //////////
input clk, // clock
input rst_n, // active low reset
input a, // input to be synchronized
////////// outputs //////////
output y
);
parameter P_DEFVAL = 1'b0;
parameter P_NFF = 2;
localparam NFF = (P_NFF > 1) ? P_NFF : 2;
// TBA Fri May 23 13:25:04 EDT 2014
// A generic synchronizer modelled after altera/13.1/ip/altera/primitives/altera_std_synchronizer/altera_std_synchronizer.v
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*sync:*|ff[0]}]\" "} *)
reg [NFF-1:0] ff;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) ff <= {NFF{P_DEFVAL}};
else ff <= {ff[NFF-2:0], a};
end
assign y = ff[NFF-1];
endmodule
| 8.281552 |
module sync1(
input clk,rst_n,
input din,
output reg dout
);
reg din_r;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
dout<=0;
din_r<=0;
else begin
din_r<=din;
dout<=din_r;
end
end
endmodule
| 6.712543 |
module sync1s (
f_clk,
s_clk,
rst_n,
in_fclk,
out_sclk
);
parameter WIDTH = 1;
input f_clk; // Fast clock.
input s_clk; // Slow clock.
input rst_n; // reset signal.
input [WIDTH-1:0] in_fclk; // Input pulse in fast clock domain.
output [WIDTH-1:0] out_sclk; // Output pulse in slow clock domain.
reg [WIDTH-1:0] f_reg1;
reg [WIDTH-1:0] f_reg2;
reg [WIDTH-1:0] f_reg3;
reg [WIDTH-1:0] s_reg1;
reg [WIDTH-1:0] s_reg2;
wire [WIDTH-1:0] hold_fb;
wire [WIDTH-1:0] out_sclk;
integer i;
// register fast clock signal edge and hold it untill
// it is transfered into slower clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n) f_reg1 <= {WIDTH{1'b0}};
else
for (i = 0; i <= WIDTH - 1; i = i + 1) begin
f_reg1[i] <= (hold_fb[i] === 1'b1) ? f_reg1[i] : in_fclk[i];
end
end
// first register in slower clock domain, this can be
// a metastable flop.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n) s_reg1 <= {WIDTH{1'b0}};
else s_reg1 <= f_reg1;
end
// Cleaner registering in slower clock domain.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n) s_reg2 <= {WIDTH{1'b0}};
else s_reg2 <= s_reg1;
end
// Output signal.
assign out_sclk = s_reg2;
// Register clean output in slower clock domain into
// fast clock domains, this can be metastable flop.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n) f_reg2 <= {WIDTH{1'b0}};
else f_reg2 <= s_reg2;
end
// Cleaner registering in faster clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n) f_reg3 <= {WIDTH{1'b0}};
else f_reg3 <= f_reg2;
end
// generate feed back hold signal for holding
// input signal in fast clock domain, until it reaches
// slower clock domain.
assign hold_fb = f_reg1 ^ f_reg3;
endmodule
| 6.646049 |
module sync2bcs (
input clk,
input rst, // !SPI_running
input [31:0] frame_No, // FIFO_TIME_TO_XIKE
output [11:0] sec,
output sync_pulse
);
parameter fs = 25000;
parameter pulse_width = 100; //100ms
//parameter [7:0] INTERVAL [7:0] = {1, 3, 14, 15, 92, 65, 35, 89, 79};
// get frame_pulse
reg frameNo_lastbit;
reg frameNo_lastbit_previous;
always @(posedge clk) begin
frameNo_lastbit <= frame_No[0];
frameNo_lastbit_previous <= frameNo_lastbit;
end
(* mark_debug = "true" *) reg frame_pulse;
always @(posedge clk) begin
frame_pulse <= frameNo_lastbit ^ frameNo_lastbit_previous;
end
// sample cnt and seconds timer
(* mark_debug = "true" *)wire sync_reset = rst;
(* mark_debug = "true" *)reg [15:0] cnt = {16{1'b0}}; // number of frame
(* mark_debug = "true" *)reg [11:0] sec = {12{1'b0}}; // time in seconds
(* mark_debug = "true" *)reg sec_vld = 0; // time in seconds (vld signal)
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
sec <= 0;
sec_vld <= 0;
end else begin
if (frame_pulse) cnt <= cnt + 1'b1;
if (cnt == fs) begin
cnt <= 0;
sec_vld <= 1;
sec <= sec + 1'b1;
end else if (frame_pulse && cnt == 0 && sec == 0) sec_vld <= 1;
else begin
sec_vld <= 0;
end
end
end
//
(* mark_debug = "true" *) wire sync_pulse;
syncGen_0 syncGen (
.ap_clk(clk), // input wire ap_clk
.ap_rst_n(!rst), // input wire ap_rst_n
.time_stream_V_sec_V_TVALID(sec_vld), // input wire time_stream_V_sec_V_TVALID
.time_stream_V_sec_V_TREADY(time_stream_V_sec_V_TREADY), // output wire time_stream_V_sec_V_TREADY
.time_stream_V_sec_V_TDATA(sec), // input wire [15 : 0] time_stream_V_sec_V_TDATA
.sync_pulse_V(sync_pulse) // output wire [0 : 0] sync_pulse_V
);
endmodule
| 7.14964 |
module sync2ff (
input wire dst_clk,
input wire din,
output wire dout
);
reg [1:0] d = 2'b00;
assign dout = d[1];
always @(posedge dst_clk) d[0] <= din;
always @(posedge dst_clk) d[1] <= d[0];
endmodule
| 6.84922 |
module sync2s (
rst,
clk,
i,
o
);
input rst;
input clk;
input i;
output o;
reg [1:0] s;
always @(posedge clk)
if (rst) s <= 0;
else s <= {s[0], i};
assign o = s[1];
endmodule
| 7.424263 |
module sync2_toggle_to_pulse (
input clk,
input rst,
input toggle,
output pulse,
output reg out_toggle
);
wire s_toggle;
sync2 i_sync2 (
clk,
rst,
toggle,
s_toggle
);
always @(posedge clk or posedge rst)
if (rst) out_toggle <= 0;
else out_toggle <= s_toggle;
assign pulse = s_toggle ^ out_toggle;
endmodule
| 6.659074 |
module, where data is synchronized
// by passing through 2 registers of the destination clock
module SyncBit (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
assign dD_OUT = dSyncReg2 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY (sD_IN == 1'b1) ? 1'b1 : 1'b0 ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
dSyncReg2 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.352735 |
module, where data is synchronized
// by passing through ONLY ONE register of the destination clock, and
// that clocked on the negedge.
module SyncBit05 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1;
assign dD_OUT = dSyncReg1 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(negedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
end
end // always @ (negedge dCLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.352735 |
module, where data is synchronized
// by passing through ONLY ONE register of the destination clock.
module SyncBit1 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1;
assign dD_OUT = dSyncReg1 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.352735 |
module, where data is synchronized
// by passing through 2 registers of the destination clock where the first
// register is triggered on the negative edge
module SyncBit15 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
assign dD_OUT = dSyncReg2 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(negedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (negedge dCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
dSyncReg2 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.352735 |
module syncbram_fifo (
clk,
rst,
buf_in,
buf_out,
wr_en,
rd_en,
buf_empty,
buf_full
);
// system clock, reset
input clk;
input rst;
// write enable, read enable
input wr_en;
input rd_en;
// buffer data in
input [7 : 0] buf_in;
// buffer data out
output [7 : 0] buf_out;
// full and empty flags
output buf_empty; // buffer empty flag
output buf_full; // buffer full flag
reg [ 7 : 0] buf_out; // read data from buffer
reg [`BUF_WIDTH : 0] rd_ptr; // pointer to read address
reg [`BUF_WIDTH : 0] wr_ptr; // pointer to write address
reg [ 7 : 0] buf_mem [`BUF_SIZE - 1 : 0]; // buffer memory
// generation of full and empty signals
assign buf_full = (( rd_ptr[`BUF_WIDTH] != wr_ptr[`BUF_WIDTH]) && ( rd_ptr[`BUF_WIDTH-1 : 0] == wr_ptr[`BUF_WIDTH-1 : 0] ));
assign buf_empty = (rd_ptr == wr_ptr);
always @(posedge clk) begin
if (rst) buf_out <= 8'b0; //On reset output of buffer is all 0.
else if (rd_en && !buf_empty)
buf_out <= buf_mem[rd_ptr[`BUF_WIDTH-1 : 0]]; //Reading the 8 bit data from buffer location indicated by read pointer
end
always @(posedge clk) begin
if (wr_en && !buf_full)
buf_mem[wr_ptr[`BUF_WIDTH-1 : 0]] <= buf_in; // wrting data to the buffer memory
end
always @(posedge clk) begin
if ( rst ) // reset condition
begin
wr_ptr <= `BUF_WIDTH'd0; // Initializing write pointer
rd_ptr <= `BUF_WIDTH'd0; // Initializing read pointer
end else begin
if (!buf_full && wr_en) // check whether fifo is not full and write enable high condition
wr_ptr <= wr_ptr + `BUF_WIDTH'd1; // increment write pointer
if (!buf_empty && rd_en) // check whether fifo is not full, and read enable high condition
rd_ptr <= rd_ptr + `BUF_WIDTH'd1; // increment read pointer
end
end
endmodule
| 7.246447 |
module master (
input clock,
w,
output [15:0] address,
inout [15:0] data
);
reg [15:0] ar, dr;
assign address = ar;
assign data = (w) ? dr : 16'hzzzz;
always @(*) begin
if (!w) dr = #1 data;
end
endmodule
| 7.034859 |
module syncCorrector (
input wire pxlClk,
input wire rst,
input wire vsync,
input wire hsync,
input wire de,
output wire vsync_o,
output wire hsync_o,
output wire de_o
);
wire normalVsync, normalHsync;
syncPolDecter hdect (
.pxlClk(pxlClk),
.rst(rst),
.sync(hsync),
.normalSync(normalHsync)
);
syncPolDecter vdect (
.pxlClk(pxlClk),
.rst(rst),
.sync(vsync),
.normalSync(normalVsync)
);
assign de_o = de && hsync_o && vsync_o;
assign hsync_o = normalHsync == hsync;
assign vsync_o = normalVsync == vsync;
/*
always @(posedge pxlClk or negedge rst) begin
if(!rst)begin
normalHsync <= 1'b1;
normalVsync <= 1'b1;
end else begin
if (de) begin
normalHsync <= hsync;
normalVsync <= vsync;
end
end
end
*/
endmodule
| 7.346458 |
module SyncCounter (
CountEn,
clock,
Q
);
input CountEn, clock;
output [3:0] Q;
wire w0, w1, w2;
JK_Flip_Flop jk1 (
CountEn,
CountEn,
clock,
Q[0]
);
and gate1 (w0, CountEn, Q[0]);
JK_Flip_Flop jk2 (
w0,
w0,
clock,
Q[1]
);
and gate2 (w1, w0, Q[1]);
JK_Flip_Flop jk3 (
w1,
w1,
clock,
Q[2]
);
and gate3 (w2, w1, Q[2]);
JK_Flip_Flop jk4 (
w2,
w2,
clock,
Q[3]
);
endmodule
| 6.712306 |
module syncdivider (
input CLK,
input sync_in, // Input sync signal, should stay up exactly one cycle.
output sync_out, // Divided output sync signal, will stay up exactly one cycle.
input pb_divby, // Preferably debounced, staying up exactly one FPGA-cycle.
input pb_offset, // As well.
output [3:0] divby, // For displaying on 7-SEG display.
output [3:0] sel_offset, // As well.
output invert_sync_in
);
function [7:0] rol8bits;
input [7:0] b;
rol8bits = {b[6], b[5], b[4], b[3], b[2], b[1], b[0]};
endfunction
function [2:0] choose_n_lsbs;
input [2:0] b;
input [1:0] n;
begin
case (n)
2'b00: choose_n_lsbs = {3'b000};
2'b01: choose_n_lsbs = {2'b00, b[0]};
2'b10: choose_n_lsbs = {1'b0, b[1:0]};
2'b11: choose_n_lsbs = b[2:0];
endcase
end
endfunction
// if everynth = 00 --> take every sync
// = 01 --> take every 2nd sync
// = 10 --> take every 4th sync
// = 11 --> take every 8th sync
reg [1:0] everynth = 2'b00;
reg [2:0] isyncs_since_last_osync = 3'b000;
reg [3:0] offset_and_invert_flag = 4'b0000;
assign invert_sync_in = offset_and_invert_flag[0];
wire [2:0] offset = offset_and_invert_flag[3:1];
wire sync_now = sync_in; // (sync_in ^ invert_sync_in);
assign divby = (1 << everynth);
assign sel_offset = offset;
// Too hard for Verilog:
// assign sync_out = (sync_now & ~|isyncs_since_last_osync[everynth:0]);
assign sync_out = (sync_now & (~|choose_n_lsbs(isyncs_since_last_osync, everynth)));
always @(posedge CLK) begin
if (sync_now) isyncs_since_last_osync <= isyncs_since_last_osync + 1;
if (pb_divby) everynth <= everynth + 1; // Toggle frequency from 1/1 to 1/8.
if(pb_offset) // Toggle invert_sync_in and increase offset circularly from 0 to 7.
begin
offset_and_invert_flag <= offset_and_invert_flag + 1;
if (invert_sync_in) isyncs_since_last_osync <= isyncs_since_last_osync - 1;
end
end
endmodule
| 7.672204 |
module will simulate the operation of a 4 bit synchronous down counter.
module syncDownCounter(clk, rst, out);
input clk;
input rst;
output [3:0] out;
wire [3:0] d;
// assign each bit of wire to logical operations with outputs.
assign d[0] = ~out[0];
assign d[1] = out[1] ~^ out[0];
assign d[2] = out[2] ~^ (out[1] | out[0]);
assign d[3] = out[3] ~^ (out[2] | out[1] | out[0]);
// inputs each bit of wire d to a D flip flop.
// outputs of D flip flops are the bits of the output out.
DFlipFlop dff0(.q(out[0]), .qBar(), .D(d[0]), .clk(clk), .rst(rst));
DFlipFlop dff1(.q(out[1]), .qBar(), .D(d[1]), .clk(clk), .rst(rst));
DFlipFlop dff2(.q(out[2]), .qBar(), .D(d[2]), .clk(clk), .rst(rst));
DFlipFlop dff3(.q(out[3]), .qBar(), .D(d[3]), .clk(clk), .rst(rst));
endmodule
| 7.492578 |
module syncDownCounter_gl (
clk,
rst,
out
);
input clk, rst;
wire [3:0] d;
output [3:0] out;
wire orOut1, orOut2;
not firstBit (d[0], out[0]);
xnor secondBit (d[1], out[1], out[0]);
or orOne (orOut1, out[1], out[0]);
xnor thirdBit (d[2], out[2], orOut1);
or orTwo (orOut2, out[2], out[1], out[0]);
xnor fourthBit (d[3], out[3], orOut2);
DFlipFlop dff0 (
.q(out[0]),
.qBar(),
.D(d[0]),
.clk,
.rst
);
DFlipFlop dff1 (
.q(out[1]),
.qBar(),
.D(d[1]),
.clk,
.rst
);
DFlipFlop dff2 (
.q(out[2]),
.qBar(),
.D(d[2]),
.clk,
.rst
);
DFlipFlop dff3 (
.q(out[3]),
.qBar(),
.D(d[3]),
.clk,
.rst
);
endmodule
| 6.929131 |
module syncDownCounter_gl_tb ();
wire clk, rst;
wire [3:0] out;
syncDownCounter_gl syncDownCounter_gl (
.clk,
.rst,
.out
);
syncDownCounter_gl_tester tester (
.out,
.clk,
.rst
);
initial begin
$dumpfile("syncDownCounter_gl_tb.vcd");
$dumpvars;
end
endmodule
| 6.929131 |
module syncDownCounter_gl_tester (
out,
clk,
rst
);
input [3:0] out;
output clk, rst;
reg clk, rst;
parameter CLOCK_PERIOD = 2;
initial begin
clk = 1;
forever #(CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
$display("\t\t rst \t clk \t bit");
$monitor("\t\t %b \t %b \t %b %b %b %b", rst, clk, out[3], out[2], out[1], out[0], $time);
end
initial begin
// Active low reset:
// Reset with rst = 0 and keep it
// one for the rest of the time.
rst <= 1'b1;
@(posedge clk);
rst <= 1'b0;
@(posedge clk);
rst <= 1'b1;
@(posedge clk);
repeat (32) @(posedge clk);
$finish;
end
endmodule
| 6.929131 |
module syncDownCounter_tb ();
wire clk, rst;
wire [3:0] out;
syncDownCounter sd_counter (
.clk,
.rst,
.out
);
sd_counter_tester tester (
.out,
.clk,
.rst
);
initial begin
$dumpfile("syncDownCounter_tb.vcd");
$dumpvars;
end
endmodule
| 6.929131 |
module sd_counter_tester (
rst,
clk,
out
);
output reg rst, clk;
input [3:0] out;
parameter CLOCK_PERIOD = 2; //gtkwave simulates in seconds
initial begin
clk = 0;
forever #(CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
$display("\t\t rst \t clk \t out");
$monitor("\t\t %b \t %b \t %b %b %b %b", rst, clk, out[3], out[2], out[1], out[0], $time);
end
initial begin
// Active low rst:
// rst with rst = 0 and keep it
// one for the rest of the time.
rst <= 1'b1;
@(posedge clk);
rst <= 1'b0;
@(posedge clk);
rst <= 1'b1;
@(posedge clk);
repeat (32) @(posedge clk); // ascend once then descend once
$finish;
end
endmodule
| 7.194704 |
module SYNCEDGE (
I,
O,
CLK,
PIPE
);
//% Number of clock edges required before output is true when condition met.
parameter LATENCY = 1;
//% Edge detector type - "RISING" or "FALLING".
parameter EDGE = "RISING";
//% Output signal "true" polarity - "POSITIVE" or "NEGATIVE"
parameter POLARITY = "POSITIVE";
//% Clock edge to use - "RISING" or "FALLING"
parameter CLKEDGE = "RISING";
localparam [1:0] match_value = {(EDGE == "FALLING"), (EDGE == "RISING")};
//% Input signal.
input I;
//% Flag when edge is detected.
output O;
//% System clock.
input CLK;
//% Output registered history of input signal.
output [LATENCY:0] PIPE;
//% Input signal (I_pipe[0]) and registered history
reg [LATENCY+1:0] I_pipe = {LATENCY{1'b0}};
//% 1 of value has been matched, 0 if not
wire EDGE_DETECTED = (I_pipe[LATENCY+1:LATENCY] == match_value);
generate
genvar i;
for (i = 0; i <= LATENCY + 1; i = i + 1) begin : LOOP
if (i == 0) begin : HEAD
if (CLKEDGE == "RISING") begin : CLKRISE
always @(*) I_pipe[i] <= I;
end else begin : CLKFALL
always @(*) I_pipe[i] <= I;
end
end else begin : TAIL
if (CLKEDGE == "RISING") begin : CLKRISE
always @(posedge CLK) I_pipe[i] <= I_pipe[i-1];
end else begin : CLKFALL
always @(negedge CLK) I_pipe[i] <= I_pipe[i-1];
end
end
end
endgenerate
assign O = EDGE_DETECTED ? POLARITY == "POSITIVE" : POLARITY == "NEGATIVE";
endmodule
| 7.812723 |
module based on SYNCEDGE. Rising edge detector.
//% @gensymbol
//% MODULE SYNCEDGE_R
//% LPORT I input
//% LPORT CLK input
//% RPORT O output
//% @endgensymbol
module SYNCEDGE_R(
I,
O,
CLK
);
input I;
output O;
input CLK;
SYNCEDGE #(.EDGE("RISING"),.POLARITY("POSITIVE"),.LATENCY(1),.CLKEDGE("RISING")) edge_detector(.I(I),.O(O),.CLK(CLK));
endmodule
| 6.941394 |
module SyncEventCounterV1 (
input clk,
input event_trigger,
input reset,
output reg [31:0] events_counted,
// Note this next parameter is new and is not in the original implementation
// from the earlier Chapter 5 project.
output reg data_ready = 0
);
// ----- Begin copy of Language Template.
// Taken from: Verilog/Synthesis Constructs/Coding Examples/State Machines/Moore/Binary (parameter)/Fast/4 States
parameter STARTUP = 2'b00;
parameter COUNTING = 2'b01;
parameter STORE_COUNTS = 2'b10;
parameter RESET_COUNTERS = 2'b11;
parameter CLOCK_FREQUENCY = 100_000_000; // 100 MHz
reg [ 1:0] state = STARTUP;
reg [31:0] clock_cycles; // n
reg [31:0] events_running_total;
always @(posedge clk)
if (reset) begin
state <= STARTUP;
end else
case (state)
STARTUP: begin
clock_cycles <= 0;
events_running_total <= 0;
data_ready <= 0;
end
COUNTING: begin
// The concept of t_ref here is poorly explained in the book.
if (clock_cycles < CLOCK_FREQUENCY - 1) begin
state <= COUNTING;
end else if (clock_cycles == CLOCK_FREQUENCY - 1) begin
state <= STORE_COUNTS;
end
if (event_trigger) begin
events_running_total <= events_running_total + 1;
end
end
STORE_COUNTS: begin
events_counted <= events_running_total;
end
RESET_COUNTERS: begin
state <= COUNTING;
clock_cycles <= 0;
events_running_total <= 0;
events_counted <= events_counted;
data_ready <= 1'b1;
end
endcase
// End copy of Language Template.
endmodule
| 7.219404 |
module syncff (
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff syncFF (
.CLK(CLK),
.D (IN_ASYNC),
.Q (wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D (wSyncFFQ),
.Q (OUT_SYNC)
);
endmodule
| 7.613166 |
module testSyncFIFO() ;
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
wire [dsize -1:0] sDIN, dDOUT ;
reg [dsize -1:0] sCNT, dCNT ;
reg sRST, sCLR ;
ClockGen#(15,14,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK );
initial
begin
sCNT = 0;
dCNT = 0;
sCLR = 1'b0 ;
sRST = `BSV_RESET_VALUE ;
$display( "running test" ) ;
$dumpfile("SyncFIFO.vcd");
$dumpvars(5,testSyncFIFO) ;
$dumpon ;
#200 ;
sRST = !`BSV_RESET_VALUE ;
#100000 $finish ;
end // initial begin
initial
begin
#50000 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end
SyncFIFO #(dsize,fifodepth,fifoidx)
dut( sCLK, sRST, dCLK, sENQ, sDIN,
sFULL_N, // sCLR,
dDEQ, dDOUT, dEMPTY_N );
assign sDIN = sCNT ;
assign sENQ = sFULL_N ;
always @(posedge sCLK)
begin
if (sENQ )
begin
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
end
end // always @ (posedge sCLK)
assign dDEQ = dEMPTY_N ;
always @(posedge dCLK)
begin
if (dDEQ )
begin
$display( "dequeing %d", dDOUT ) ;
end
end // always @ (posedge dCLK)
endmodule
| 7.223533 |
module testSyncFIFO0() ;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
reg sRST, sCLR ;
ClockGen#(15,14,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK );
initial
begin
sCLR = 1'b0 ;
sRST = `BSV_RESET_VALUE ;
$display( "running test" ) ;
$dumpfile("SyncFIFO0.vcd");
$dumpvars(5,testSyncFIFO0) ;
$dumpon ;
#200 ;
sRST = !`BSV_RESET_VALUE ;
#100000 $finish ;
end // initial begin
initial
begin
#50000 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end
SyncFIFO0 #(fifodepth,fifoidx)
dut( sCLK, sRST, dCLK, sENQ,
sFULL_N, // sCLR,
dDEQ, dEMPTY_N );
assign sENQ = sFULL_N ;
always @(posedge sCLK)
begin
if (sENQ )
begin
$display( "enqueuing" ) ;
end
end // always @ (posedge sCLK)
assign dDEQ = dEMPTY_N ;
always @(posedge dCLK)
begin
if (dDEQ )
begin
$display( "dequeing" ) ;
end
end // always @ (posedge dCLK)
endmodule
| 6.561957 |
module SyncFIFO1(
sCLK,
sRST,
dCLK,
sENQ,
sD_IN,
sFULL_N,
dDEQ,
dD_OUT,
dEMPTY_N
) ;
parameter dataWidth = 1 ;
// input clock domain ports
input sCLK ;
input sRST ;
input sENQ ;
input [dataWidth -1 : 0] sD_IN ;
output sFULL_N ;
// destination clock domain ports
input dCLK ;
input dDEQ ;
output dEMPTY_N ;
output [dataWidth -1 : 0] dD_OUT ;
// FIFO DATA
reg [dataWidth -1 : 0] syncFIFO1Data ;
// Reset generation
wire dRST = sRST;
// sCLK registers
reg sEnqToggle, sDeqToggle, sSyncReg1;
// dCLK registers
reg dEnqToggle, dDeqToggle, dSyncReg1;
// output assignment
assign dD_OUT = syncFIFO1Data;
assign dEMPTY_N = dEnqToggle != dDeqToggle;
assign sFULL_N = sEnqToggle == sDeqToggle;
always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin
if (sRST == `BSV_RESET_VALUE) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY {dataWidth {1'b0}};
sEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
sDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b1; // FIFO marked as full during reset
end
else begin
if (sENQ && (sEnqToggle == sDeqToggle)) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY sD_IN;
sEnqToggle <= `BSV_ASSIGNMENT_DELAY ! sEnqToggle;
end
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dDeqToggle; // clock domain crossing
sDeqToggle <= `BSV_ASSIGNMENT_DELAY sSyncReg1;
end
end
always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin
if (dRST == `BSV_RESET_VALUE) begin
dEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
dDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else begin
if (dDEQ && (dEnqToggle != dDeqToggle)) begin
dDeqToggle <= `BSV_ASSIGNMENT_DELAY ! dDeqToggle;
end
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sEnqToggle; // clock domain crossing
dEnqToggle <= `BSV_ASSIGNMENT_DELAY dSyncReg1;
end
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin : initBlock
syncFIFO1Data = {((dataWidth + 1)/2){2'b10}} ;
sEnqToggle = 1'b0;
sDeqToggle = 1'b0;
sSyncReg1 = 1'b0;
dEnqToggle = 1'b0;
dDeqToggle = 1'b0;
dSyncReg1 = 1'b0;
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
always@(posedge sCLK)
begin: error_checks1
reg enqerror ;
enqerror = 0;
if (sRST == ! `BSV_RESET_VALUE)
begin
if ( sENQ && (sEnqToggle != sDeqToggle)) begin
enqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end
end
always@(posedge dCLK)
begin: error_checks2
reg deqerror ;
deqerror = 0;
if (dRST == ! `BSV_RESET_VALUE)
begin
if ( dDEQ && (dEnqToggle == dDeqToggle)) begin
deqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Dequeuing from an empty full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
endmodule
| 6.548293 |
module testSyncFIFOLevel() ;
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
wire [dsize -1:0] sDIN, dDOUT ;
reg [dsize -1:0] sCNT, dCNT ;
reg sRST ;
wire [fifoidx:0] dItemCnt, sItemCnt ;
wire sCLR_RDY;
wire dCLR_RDY;
wire sCLR;
wire dCLR;
reg [31:0] count ;
reg started ;
reg ddeq ;
ClockGen#(14,15,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK ); // Pause the generation of the destination side clock
initial
begin
sCNT = 0;
dCNT = 0;
sRST = `BSV_RESET_VALUE ;
count = 0;
started = 0;
ddeq = 0;
$display( "running test" ) ;
$dumpfile("SyncFIFOLevel.vcd");
$dumpvars(10,testSyncFIFOLevel) ;
#1
$dumpon ;
#200 ;
sRST = !`BSV_RESET_VALUE ;
#50000 $finish ;
end
SyncFIFOLevel #(dsize,fifodepth,fifoidx)
dut( sCLK, sRST, dCLK, sENQ, sDIN,
sFULL_N, dDEQ, dDOUT, dEMPTY_N, dItemCnt, sItemCnt,
sCLR, sCLR_RDY, dCLR, dCLR_RDY );
assign sDIN = sCNT ;
assign sENQ = sFULL_N ;
assign dCLR = ((count[7:0] == 8'b0010_0011) && dCLR_RDY);
assign sCLR = ((count[7:0] == 8'b0000_0001) && sCLR_RDY);
always @(posedge sCLK)
begin
count <= count + 1 ;
$display( "scount is %d", sItemCnt ) ;
if (sENQ )
begin
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
$display( "enqueuing is %d", sCNT ) ;
end // if (sENQ )
end // always @ (posedge sCLK)
assign dDEQ = ddeq ;
always @(dItemCnt or dEMPTY_N or started or count)
begin
ddeq = (count > 40) && dEMPTY_N && (started || dItemCnt > 4);
end // always @ (dItemCnt or dEMPTY_N or started)
always @(posedge dCLK)
begin
$display( "dcount is %d", dItemCnt ) ;
if (ddeq)
begin
started <= 1;
$display( "dequeing %d", dDOUT ) ;
end // if (dDEQ )
else
begin
started <= 0;
end
end // always @ (posedge dCLK)
endmodule
| 7.415524 |
module testSyncFIFOLevel ();
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N;
reg sRST;
wire [fifoidx:0] dItemCnt, sItemCnt;
wire sCLR_RDY;
wire dCLR_RDY;
wire sCLR;
wire dCLR;
reg [31:0] count;
reg started;
reg ddeq;
ClockGen #(14, 15, 10) sc (sCLK);
ClockGen #(11, 12, 2600) dc (dCLK); // Pause the generation of the destination side clock
initial begin
sRST = `BSV_RESET_VALUE;
count = 0;
started = 0;
ddeq = 0;
$display("running test");
$dumpfile("SyncFIFOLevel.vcd");
$dumpvars(10, testSyncFIFOLevel);
#1 $dumpon;
#200;
sRST = !`BSV_RESET_VALUE;
#50000 $finish;
end
SyncFIFOLevel #(fifodepth, fifoidx) dut (
sCLK,
sRST,
dCLK,
sENQ,
sFULL_N,
dDEQ,
dEMPTY_N,
dItemCnt,
sItemCnt,
sCLR,
sCLR_RDY,
dCLR,
dCLR_RDY
);
assign sENQ = sFULL_N;
assign dCLR = ((count[7:0] == 8'b0010_0011) && dCLR_RDY);
assign sCLR = ((count[7:0] == 8'b0000_0001) && sCLR_RDY);
always @(posedge sCLK) begin
count <= count + 1;
$display("scount is %d", sItemCnt);
if (sENQ) begin
$display("enqueuing");
end // if (sENQ )
end // always @ (posedge sCLK)
assign dDEQ = ddeq;
always @(dItemCnt or dEMPTY_N or started or count) begin
ddeq = (count > 40) && dEMPTY_N && (started || dItemCnt > 4);
end // always @ (dItemCnt or dEMPTY_N or started)
always @(posedge dCLK) begin
$display("dcount is %d", dItemCnt);
if (ddeq) begin
started <= 1;
$display("dequeing");
end // if (dDEQ )
else
begin
started <= 0;
end
end // always @ (posedge dCLK)
endmodule
| 7.415524 |
module syncfifo_512x32 (
clk,
din,
rd_en,
srst,
wr_en,
dout,
empty,
full
);
input clk;
input [31 : 0] din;
input rd_en;
input srst;
input wr_en;
output [31 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(510),
.C_PROG_FULL_THRESH_NEGATE_VAL(509),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.SRST(srst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.RST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.970954 |
module syncfifo_512x32 (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
endmodule
| 6.970954 |
module syncfifo_512x36 (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full
);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(5),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(6),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(510),
.C_PROG_FULL_THRESH_NEGATE_VAL(509),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.970954 |
module syncfifo_512x36_fallthrough (
clk,
din,
rd_en,
rst,
wr_en,
almost_full,
dout,
empty,
full
);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output almost_full;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(5),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(6),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(510),
.C_PROG_FULL_THRESH_NEGATE_VAL(509),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.ALMOST_FULL(almost_full),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.970954 |
module syncfifo_512x72 (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full
);
input clk;
input [71 : 0] din;
input rd_en;
input rst;
input wr_en;
output [71 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(72),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(72),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(5),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(6),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(510),
.C_PROG_FULL_THRESH_NEGATE_VAL(509),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.970954 |
module SyncFIFO_RTL #(
parameter width = 32,
parameter depth = 16,
parameter depth_LOG = 4,
parameter FWFT = 1 //1:First Word Fall Through,0:Standard
) (
input wire clk_i,
input wire rst_i,
input wire read_i,
input wire write_i,
output reg full_o,
output reg empty_o,
input wire [width-1 : 0] data_i,
output wire [width-1 : 0] data_o
);
reg [width-1 : 0] data_o_std;
reg [width-1 : 0] mem[depth-1 : 0];
reg [depth_LOG-1 : 0] wp, rp;
reg w_flag, r_flag;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
wp <= 0;
w_flag <= 0;
end else if (~full_o & write_i) begin
wp <= (wp == depth - 1) ? 'b0 : wp + 1;
w_flag <= (wp == depth - 1) ? ~w_flag : w_flag;
end
end
always @(posedge clk_i) begin
if (~full_o & write_i) begin
mem[wp] <= data_i;
end
end
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
rp <= 0;
r_flag <= 0;
end else if (~empty_o & read_i) begin
rp <= (rp == depth - 1) ? 'b0 : rp + 1;
r_flag <= (rp == depth - 1) ? ~r_flag : r_flag;
end
end
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) data_o_std <= 0;
else begin
if (~empty_o & read_i) data_o_std <= mem[rp];
end
end
always @(*) begin
if (wp == rp) begin
if (r_flag == w_flag) begin
full_o = 0;
empty_o = 1;
end else begin
full_o = 1;
empty_o = 0;
end
end else begin
full_o = 0;
empty_o = 0;
end
end
generate
if (FWFT == 0) begin : FWFT_MODE
assign data_o = data_o_std;
end else begin : STANDARD_MOD
assign data_o = mem[rp];
end
endgenerate
endmodule
| 8.203937 |
module syncfifo_showahead_aclr_w35d4 (
input wire [34:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [34:0] q, // fifo_output.dataout
output wire [ 1:0] usedw, // .usedw
output wire full, // .full
output wire empty // .empty
);
syncfifo_showahead_aclr_w35d4_fifo_191_vo6tksa fifo_0 (
.data (data), // fifo_input.datain
.wrreq(wrreq), // .wrreq
.rdreq(rdreq), // .rdreq
.clock(clock), // .clk
.aclr (aclr), // .aclr
.q (q), // fifo_output.dataout
.usedw(usedw), // .usedw
.full (full), // .full
.empty(empty) // .empty
);
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w35d4_fifo_191_vo6tksa (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [34:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [34:0] q;
output [1:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [34:0] sub_wire2;
wire [1:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [34:0] q = sub_wire2[34:0];
wire [1:0] usedw = sub_wire3[1:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus(),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10", scfifo_component.lpm_numwords = 4,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 35, scfifo_component.lpm_widthu = 2,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w64d256 (
input wire [63:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [63:0] q, // fifo_output.dataout
output wire [ 7:0] usedw, // .usedw
output wire full, // .full
output wire empty // .empty
);
syncfifo_showahead_aclr_w64d256_fifo_191_uadsfsq fifo_0 (
.data (data), // fifo_input.datain
.wrreq(wrreq), // .wrreq
.rdreq(rdreq), // .rdreq
.clock(clock), // .clk
.aclr (aclr), // .aclr
.q (q), // fifo_output.dataout
.usedw(usedw), // .usedw
.full (full), // .full
.empty(empty) // .empty
);
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w64d256_fifo_191_uadsfsq (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [63:0] q;
output [7:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [63:0] sub_wire2;
wire [7:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [63:0] q = sub_wire2[63:0];
wire [7:0] usedw = sub_wire3[7:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus(),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10", scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 64, scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w71d32 (
input wire [70:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [70:0] q, // fifo_output.dataout
output wire [ 4:0] usedw, // .usedw
output wire full, // .full
output wire empty // .empty
);
syncfifo_showahead_aclr_w71d32_fifo_191_wojwlyy fifo_0 (
.data (data), // fifo_input.datain
.wrreq(wrreq), // .wrreq
.rdreq(rdreq), // .rdreq
.clock(clock), // .clk
.aclr (aclr), // .aclr
.q (q), // fifo_output.dataout
.usedw(usedw), // .usedw
.full (full), // .full
.empty(empty) // .empty
);
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w71d32_fifo_191_wojwlyy (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [70:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [70:0] q;
output [4:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [70:0] sub_wire2;
wire [4:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [70:0] q = sub_wire2[70:0];
wire [4:0] usedw = sub_wire3[4:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus(),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10", scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 71, scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w9d256 (
input wire [8:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [8:0] q, // fifo_output.dataout
output wire [7:0] usedw, // .usedw
output wire full, // .full
output wire empty // .empty
);
syncfifo_showahead_aclr_w9d256_fifo_191_53aeptq fifo_0 (
.data (data), // fifo_input.datain
.wrreq(wrreq), // .wrreq
.rdreq(rdreq), // .rdreq
.clock(clock), // .clk
.aclr (aclr), // .aclr
.q (q), // fifo_output.dataout
.usedw(usedw), // .usedw
.full (full), // .full
.empty(empty) // .empty
);
endmodule
| 6.738914 |
module syncfifo_showahead_aclr_w9d256_fifo_191_53aeptq (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [8:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [8:0] q;
output [7:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire [7:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [8:0] q = sub_wire2[8:0];
wire [7:0] usedw = sub_wire3[7:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus(),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10", scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 9, scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.738914 |
module SyncFIFO_tb;
// Parameters
localparam Depth = 8;
localparam WordWidth = 32;
// Ports
reg push_i = 0;
reg [WordWidth-1:0] push_payload_i;
reg pop_i = 0;
wire [WordWidth-1:0] pop_payload_o;
wire full_o;
wire empty_o;
reg flush_i = 0;
reg clk = 0;
reg rstn = 0;
bit [WordWidth-1:0] golden_fifo[$];
bit [WordWidth-1:0] random_payload;
bit [WordWidth-1:0] golden_fifo_front;
int iter = 1000000;
initial begin
begin
#10 rstn = 1'b1;
repeat (iter) begin : random_test
@(negedge clk);
pop_i = 1'b0;
push_i = 1'b0;
if ($urandom_range(0, 1) && ~empty_o) begin : test_pop
pop_i = 1'b1;
golden_fifo_front = golden_fifo.pop_front();
CHECK_EQUALATION :
assert (pop_payload_o == golden_fifo_front)
else begin
$fatal("\n Error: Fail when check equalation, ours[%x] -- gloden[%x]", pop_payload_o,
golden_fifo_front);
end
;
end
if ($urandom_range(0, 1) && ~full_o) begin : test_push
random_payload = $urandom();
push_i = 1'b1;
push_payload_i = random_payload;
golden_fifo.push_back(random_payload);
end
end
$info("\n PASS after %d iter \n", iter);
$finish;
end
end
SyncFIFO #(
.Depth(Depth),
.WordWidth(WordWidth)
) SyncFIFO_dut (
.push_i(push_i),
.push_payload_i(push_payload_i),
.pop_i(pop_i),
.pop_payload_o(pop_payload_o),
.full_o(full_o),
.empty_o(empty_o),
.flush_i(flush_i),
.clk(clk),
.rstn(rstn)
);
`ifdef DUMPON
initial begin : GEN_WAVEFORM
$fsdbDumpfile("SyncFIFO_tb.fsdb");
$fsdbDumpvars(0, SyncFIFO_tb);
$fsdbDumpvars("+mda");
$fsdbDumpvars("+all");
$fsdbDumpon();
end
`endif
always #20 clk = !clk;
endmodule
| 6.503114 |
module syncfifo_w9d128_aclr_showahead (
input wire [8:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [8:0] q, // fifo_output.dataout
output wire [6:0] usedw, // .usedw
output wire full, // .full
output wire empty // .empty
);
syncfifo_w9d128_aclr_showahead_fifo_191_sqyurki fifo_0 (
.data (data), // fifo_input.datain
.wrreq(wrreq), // .wrreq
.rdreq(rdreq), // .rdreq
.clock(clock), // .clk
.aclr (aclr), // .aclr
.q (q), // fifo_output.dataout
.usedw(usedw), // .usedw
.full (full), // .full
.empty(empty) // .empty
);
endmodule
| 6.585977 |
module syncfifo_w9d128_aclr_showahead_fifo_191_sqyurki (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [8:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [8:0] q;
output [6:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire [6:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [8:0] q = sub_wire2[8:0];
wire [6:0] usedw = sub_wire3[6:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus(),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10", scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 9, scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.585977 |
module SyncGen ( /*AUTOARG*/
// Outputs
vs,
hs,
x,
y,
border,
// Inputs
fbclk,
rst_b
);
input fbclk;
input rst_b;
output reg vs, hs;
output reg [11:0] x, y;
output reg border;
parameter XRES = 640;
parameter XFPORCH = 24;
parameter XSYNC = 40;
parameter XBPORCH = 128;
parameter YRES = 480;
parameter YFPORCH = 9;
parameter YSYNC = 3;
parameter YBPORCH = 28;
always @(posedge fbclk) begin
if (!rst_b) begin
x <= 0;
y <= 0;
end else begin
if (x >= (XRES + XFPORCH + XSYNC + XBPORCH)) begin
if (y >= (YRES + YFPORCH + YSYNC + YBPORCH)) y <= 0;
else y <= y + 1;
x <= 0;
end else x <= x + 1;
end
end
always @(*) begin
hs = (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC));
vs = (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC));
border = (x >= XRES) || (y >= YRES);
end
endmodule
| 7.245209 |
module syncGen_time_to_sync_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 6;
parameter MEM_SIZE = 42;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./syncGen_time_to_sync_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 7.084799 |
module syncGen_time_to_sync (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd42;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
syncGen_time_to_sync_rom syncGen_time_to_sync_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 7.084799 |
module SyncHandshake(
sCLK,
sRST,
dCLK,
sEN,
sRDY,
dPulse
);
parameter init = 1'b0;
// Source clock port signal
input sCLK ;
input sRST ;
input sEN ;
output sRDY ;
// Destination clock port signal
input dCLK ;
output dPulse ;
// Flops to hold data
reg dSyncReg1, dSyncReg2 ;
reg dLastState ;
reg sToggleReg ;
reg sSyncReg1, sSyncReg2 ;
// Output signal
assign dPulse = dSyncReg2 != dLastState ;
assign sRDY = sSyncReg2 == sToggleReg;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ;
sToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
// hadshake return synchronizer
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;// clock domain crossing
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
// Pulse send
if ( sEN )
begin
sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ;
end // if ( sEN )
end
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init;
dLastState <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
dSyncReg1 = init ;
dSyncReg2 = init ;
dLastState = init ;
sToggleReg = init ;
sSyncReg1 = ! init ;
sSyncReg2 = ! init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 7.226902 |
module synchroniser #(
parameter width = 1,
parameter depth = 2,
parameter init_high = 0
) (
input clk,
input [width-1:0] signal,
output [width-1:0] sync_signal
);
reg [width-1:0] sync[depth-1:0];
assign sync_signal = sync[depth-1];
integer i;
initial begin
for (i = 0; i < depth; i = i + 1) sync[i] = (init_high) ? {width{1'b1}} : 'd0;
end
always @(posedge clk) begin
sync[0] <= signal;
for (i = 1; i < depth; i = i + 1) sync[i] <= sync[i-1];
end
endmodule
| 7.631043 |
module for ADC and LA sourses
******************************************************************************
**/
/* Internal includes */
`include "ADC_TRIG.v"
`include "LA_TRIG.v"
module Synchronization
(
input [7:0] SYNC_DATA_IN,
input [7:0] Delay,
input [7:0] Trg_Lv_UP,
input [7:0] Trg_Lv_DOWN,
input [7:0] LA_MASK_CND,
input [7:0] LA_MASK_DIFF,
input ADC_LA_SYNC_SOURSE,
input ADC_SYNC_OUT_WIN,
input LA_SYNC_AND_OR_MODE,
input SYNC_GLOBAL_ON,
input Start_Write,
input ENABLE_TRIGG,
input CLK_EN,
input CLK,
output reg TRIG_EV_OUT
);
/* wires and assigns */
wire ADC_trigger_event;
wire LA_trigger_event;
wire [1:0] la_sync_mode;
assign la_sync_mode[0] = LA_SYNC_AND_OR_MODE;
assign la_sync_mode[1] = ADC_SYNC_OUT_WIN;
/* sync sourse registers */
reg sync_gl_on_adc;
reg sync_gl_on_la;
/* */
always @(posedge CLK) begin
if(SYNC_GLOBAL_ON == 0) begin
TRIG_EV_OUT <= 1'b1;
end
else begin
TRIG_EV_OUT <= (ADC_trigger_event & LA_trigger_event);
if(ADC_LA_SYNC_SOURSE == 0) begin
sync_gl_on_adc <= 1'b1;
sync_gl_on_la <= 1'b0;
end
else begin
sync_gl_on_adc <= 1'b0;
sync_gl_on_la <= 1'b1;
end
end
end
/* Include module ADC sync */
ADC_TRIG ADC_TRIG_1
(
.Trg_Lv_UP(Trg_Lv_UP),
.Trg_Lv_DOWN(Trg_Lv_DOWN),
.TRIG_DATA_IN(SYNC_DATA_IN),
.Delay(Delay[3:0]),
.Sync_OUT_WIN(ADC_SYNC_OUT_WIN),
.TRG_EV_EN(ENABLE_TRIGG),
.RST(sync_gl_on_adc),
.CLK_EN(CLK_EN),
.CLK(CLK),
.trig_out(ADC_trigger_event)
);
/* Include module LA sync */
LA_TRIG LA_TRIG_1
(
.DATA_IN(SYNC_DATA_IN),
.LA_DIFF_DATA(Trg_Lv_DOWN),
.LA_DIFF_MASK(LA_MASK_DIFF),
.LA_CND_DATA(Trg_Lv_UP),
.LA_CND_MASK(LA_MASK_CND),
.SYNC_MODE(la_sync_mode),
.TRG_EV_EN(ENABLE_TRIGG),
.RST(sync_gl_on_la),
.CLK_EN(CLK_EN),
.CLK(CLK),
.TRIG_OUT(LA_trigger_event)
);
endmodule
| 6.64064 |
module is for synchronization of signals between 200M( System workspace)clk domain and
// 83M(flash controller moduler) clk domain.
// Method: Adding two FFs betwwn the two specified clk domains to mitigate the damage cased by metastability.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SynchronizeClkDomains(
clk_200M,clk_83M,rst_n,
//From flash controller module to Scheduler module
controller_rb_l,controller_rb_l_o, read_data_stall ,read_data_stall_o,
//From Scheduler module to flash controller module
Target_Addr, page_offset_addr, Operation_en,Operation_Type,
Target_Addr_o,page_offset_addr_o,Operation_en_o,Operation_Type_o
);
`include"Dynamic_Controller_Parameters.vh"
//clk and reset
input clk_200M;
input clk_83M;
input rst_n;
//From flash controller module to Scheduler module
input controller_rb_l;
input read_data_stall;
output reg controller_rb_l_o;
output reg read_data_stall_o;
//From Scheduler module to flash controller module
input [2:0] Target_Addr;
input [ADDR_WIDTH-4:0] page_offset_addr;
input Operation_en;
input [2:0] Operation_Type;
output reg [2:0] Target_Addr_o;
output reg [ADDR_WIDTH-4:0] page_offset_addr_o;
output reg Operation_en_o;
output reg [2:0] Operation_Type_o;
////////////////////////////////////////////////////////////////
reg controller_rb_l_sync;
reg read_data_stall_sync;
//From flash controller module to Scheduler module
always@(posedge clk_200M or negedge rst_n)
begin
if(!rst_n)
begin
controller_rb_l_sync<=1'b0;
read_data_stall_sync<=1'b0;
controller_rb_l_o<=1'b0;
read_data_stall_o<=1'b0;
end
else
begin
controller_rb_l_sync<=controller_rb_l;
controller_rb_l_o<=controller_rb_l_sync;
read_data_stall_sync<=read_data_stall;
read_data_stall_o<=read_data_stall_sync;
end
end
//sync FFs
reg [2:0] Target_Addr_sync;
reg [ADDR_WIDTH-4:0] page_offset_addr_sync;
reg Operation_en_sync;
reg [2:0] Operation_Type_sync;
//From Scheduler module to flash controller module.
always@(posedge clk_83M or negedge rst_n)
begin
if(!rst_n)
begin
Target_Addr_sync<=3'b0;
page_offset_addr_sync<='b0;
Operation_Type_sync<=3'b0;
Operation_en_sync<=1'b0;
Target_Addr_o<=3'b0;
page_offset_addr_o<='b0;
Operation_en_o<=1'b0;
Operation_Type_o<=3'b0;
end
else
begin
Target_Addr_sync<=Target_Addr;
page_offset_addr_sync<=page_offset_addr;
Operation_en_sync<=Operation_en;
Operation_Type_sync<=Operation_Type;
Target_Addr_o<=Target_Addr_sync;
page_offset_addr_o<=page_offset_addr_sync;
Operation_en_o<=Operation_en_sync;
Operation_Type_o<=Operation_Type_sync;
end
end
endmodule
| 7.12845 |
module synchronizer (
input wire clk,
input wire [10:0] cnt_h,
input wire [ 9:0] cnt_v,
output reg sync_h,
output reg sync_v,
output reg disp_en
);
reg h_disp_band;
reg v_disp_band;
reg h_sync_band;
reg v_sync_band;
always @(posedge clk) begin
case (cnt_h)
`IDH: h_disp_band = 1;
`ODH: h_disp_band = 0;
`ODH + `HFP: h_sync_band = 0;
`ODH + `HFP + `HS: h_sync_band = 1;
endcase
case (cnt_v)
`IDV: v_disp_band = 1;
`ODV: v_disp_band = 0;
`ODV + `VFP: v_sync_band = 0;
`ODV + `VFP + `VS: v_sync_band = 1;
endcase
sync_h <= h_sync_band;
sync_v <= v_sync_band;
disp_en <= (h_disp_band & v_disp_band);
end
endmodule
| 6.883367 |
module SynchronizerShiftReg_w1_d3 ( // @[:freechips.rocketchip.system.TinyConfig.fir@115270.2]
input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115271.4]
input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4]
output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4]
);
reg sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115278.4]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115279.4]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115280.4]
reg [31:0] _RAND_2;
assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@115284.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w2_d3 (
input clock,
input [1:0] io_d,
output [1:0] io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
wire output_chain_1_clock; // @[ShiftReg.scala 45:23]
wire output_chain_1_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_1_io_q; // @[ShiftReg.scala 45:23]
wire output_1 = output_chain_1_io_q; // @[ShiftReg.scala 48:24 ShiftReg.scala 48:24]
wire output_0 = output_chain_io_q; // @[ShiftReg.scala 48:24 ShiftReg.scala 48:24]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_1 ( // @[ShiftReg.scala 45:23]
.clock(output_chain_1_clock),
.io_d (output_chain_1_io_d),
.io_q (output_chain_1_io_q)
);
assign io_q = {output_1, output_0}; // @[Cat.scala 29:58]
assign output_chain_clock = clock;
assign output_chain_io_d = io_d[0]; // @[SynchronizerReg.scala 163:39]
assign output_chain_1_clock = clock;
assign output_chain_1_io_d = io_d[1]; // @[SynchronizerReg.scala 163:39]
endmodule
| 6.820992 |
module synchronizer (
input clk, // Clock
input async_in, // input signal
output reg Q // output after synchronization
);
reg connect = 1'b0; //to implement double flip flop
always @(posedge clk) begin
connect <= async_in;
Q <= connect;
end
endmodule
| 6.883367 |
module changes signals from one domain to another, when the signals
// have no relation to each other. For signals that are vectors, use the
// synchronizer_vector module instead.
//
// This module has variable width to synchronize several signals using
// one instantiation of the module. Uses a simple double register scheme to
// change clock domains.
//
`timescale 1ps / 1ps
module synchronizer_simple #
(
parameter DATA_WIDTH = 1
)
(
input [DATA_WIDTH-1:0] data_in,
input new_clk,
output wire [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] sync_1reg, sync_2reg;
// Register twice for metastability
always @(posedge new_clk)
begin
sync_1reg <= data_in;
sync_2reg <= sync_1reg;
end
assign data_out = sync_2reg;
endmodule
| 7.072679 |
module Synchronizer_tb #(
parameter NUM_STAGES = 2,
BUS_WIDTH = 1
) ();
reg [BUS_WIDTH-1:0] ASYNC_tb;
reg CLK_tb;
reg RST_tb;
wire [BUS_WIDTH-1:0] SYNC_tb;
parameter Clock_Period = 10;
integer i;
always #(Clock_Period / 2) CLK_tb = ~CLK_tb;
initial begin
$dumpfile("Synchronizer.vcd");
$dumpvars;
CLK_tb = 1'b0;
RST_tb = 1'b0;
ASYNC_tb = 'b1;
#Clock_Period;
$display("Test Case #1 RST");
if (SYNC_tb == 'b0) begin
$display("Passed");
end else begin
$display("Failed");
end
RST_tb = 1'b1;
repeat (NUM_STAGES) #Clock_Period;
$display("Test Case #2 SYNC after NUM_STAGES Clocks");
if (SYNC_tb == ASYNC_tb) begin
$display("Passed");
end else begin
$display("Failed");
end
#Clock_Period;
$stop;
end
Multi_Flop_Synchronizer_Multi_bits #(
.NUM_STAGES(NUM_STAGES),
.BUS_WIDTH (BUS_WIDTH)
) u_Multi_Flop_Synchronizer_Multi_bits (
.ASYNC(ASYNC_tb),
.CLK (CLK_tb),
.RST (RST_tb),
.SYNC (SYNC_tb)
);
endmodule
| 6.568034 |
module asynchronus_ram #(
parameter ADDR_WDITH = 8,
DATA_WDITH = 1
) (
clk,
we,
addr,
din,
dout
);
input wire clk, we;
input wire [ADDR_WDITH-1:0] addr;
input wire [DATA_WDITH-1:0] din;
output wire [DATA_WDITH-1:0] dout;
reg [DATA_WDITH-1:0] ram[2*ADDR_WDITH-1:0];
reg [ADDR_WDITH-1:0] add_reg;
always @(posedge clk) begin
if (we) ram[addr] <= din;
add_reg <= addr;
end
assign dout = ram[addr_reg];
endmodule
| 7.327964 |
module SynchronousROMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Addr1,
input wire [7:0] Addr2,
input wire [7:0] REAddr,
input wire RE,
output wire [7:0] Data1,
output wire [7:0] Data2,
output wire [7:0] REData
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [7:0] Inputs_Addr1;
wire [7:0] Inputs_Addr2;
wire [7:0] Inputs_REAddr;
wire Inputs_RE;
reg [7:0] State_Data1 = 8'b00000000;
reg [7:0] State_Data2 = 8'b00000000;
reg [7:0] State_REData = 8'b00000000;
reg [7:0] State_Buff[0 : 255];
initial begin : Init_State_Buff
$readmemh("SynchronousROMModule_TopLevel_State_Buff.hex", State_Buff);
end
always @(posedge Clock) begin
State_Data1 <= State_Buff[Inputs_Addr1];
end
always @(posedge Clock) begin
State_Data2 <= State_Buff[Inputs_Addr2];
end
always @(posedge Clock) begin
if (Inputs_RE == 1) begin
State_REData <= State_Buff[Inputs_REAddr];
end
end
assign Inputs_Addr1 = Addr1;
assign Inputs_Addr2 = Addr2;
assign Inputs_REAddr = REAddr;
assign Inputs_RE = RE;
assign Data1 = State_Data1;
assign Data2 = State_Data2;
assign REData = State_REData;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.353306 |
module Synchronous_FIFO #(
parameter A_WIDTH = 8,
parameter D_WIDTH = 48
) (
input i_clk, // single clock domain
input i_rst_n, // active low reset
input i_wr_en, // write enable signal
input i_rd_en, // read enable signal
input [D_WIDTH-1:0] i_data, // data input //
output o_fifo_empty, // fifo empty flag
output o_fifo_full, // fifo full flag
output o_fifo_almst_full, // fifo almost full flag , for controlling the write enable //
output [D_WIDTH-1:0] o_fifo_data
);
reg [ A_WIDTH:0] rd_cnt = 0; // read counter
reg [ A_WIDTH:0] wr_cnt = 0; // write counter
reg [ A_WIDTH:0] rd_cnt_nxt;
reg [ A_WIDTH:0] wr_cnt_nxt;
wire r_enable; // read enable control
wire w_enable; // write_enable control
wire [A_WIDTH-1:0] o_rd_addr;
wire [A_WIDTH-1:0] o_wr_addr;
assign r_enable = i_rd_en && ~o_fifo_empty;
assign w_enable = i_wr_en && ~o_fifo_full;
assign o_rd_addr = rd_cnt_nxt[A_WIDTH-1:0];
assign o_wr_addr = wr_cnt_nxt[A_WIDTH-1:0];
//depth of fifo == 256//
localparam DEPTH_FIFO = 2 ** A_WIDTH;
always @(posedge i_clk) begin
if (~i_rst_n) begin
rd_cnt <= 0;
wr_cnt <= 0;
end else begin
rd_cnt <= rd_cnt_nxt;
wr_cnt <= wr_cnt_nxt;
end
end
/// increment the read pointer //
always @(posedge i_clk) begin
if (~i_rst_n) rd_cnt_nxt <= 0;
else if (r_enable) rd_cnt_nxt <= rd_cnt_nxt + 1'b1;
else rd_cnt_nxt <= rd_cnt_nxt;
end
// increment the write pointer //
always @(posedge i_clk) begin
if (~i_rst_n) wr_cnt_nxt <= 0;
else if (w_enable) wr_cnt_nxt <= wr_cnt_nxt + 1'b1;
else wr_cnt_nxt <= wr_cnt_nxt;
end
assign o_fifo_empty = (wr_cnt[A_WIDTH-1:0] == rd_cnt[A_WIDTH-1:0]);
assign o_fifo_full = (wr_cnt == DEPTH_FIFO - 1);
assign o_fifo_almst_full = (wr_cnt == DEPTH_FIFO - 2);
D_PRAM #(
.WIDTH_DATA(D_WIDTH),
.WIDTH_ADDR(A_WIDTH)
) BRAM_U1 (
///write block signals//
.i_wclk (i_clk),
.i_wr_en(w_enable),
.i_WADDR(o_wr_addr),
.i_WDATA(i_data),
///read block signals //
.i_rdclk(i_clk),
.i_rd_en(r_enable),
.i_RADDR(o_rd_addr),
.o_RDATA(o_fifo_data)
);
endmodule
| 8.091587 |
module synchronous_two_input_multiplexer #(
parameter WIDTH = 16
) (
input clk,
input select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
output reg [WIDTH-1:0] out
);
always @(posedge clk)
case (select)
1'b0: out = in0;
1'b1: out = in1;
endcase // case (select)
endmodule
| 7.068496 |
module synchro_ram (
clk,
datain,
addr,
read,
write,
dataout
);
input clk;
input [3:0] addr;
input read;
input write;
input [3:0] datain;
output [3:0] dataout;
//While asynchronous read,please comment it.
reg [3:0] dataout;
//Memory 4 bits,16 words.
reg [3:0] memory [0:15];
initial begin
//Attention:.txt file path should be '/' instead of '\'
$readmemb("ram.txt", memory);
end
// //Asynchronous read
// assign dataout = read ? memory[addr] : 4'b0000;
//Synchronous read
always @(posedge clk) begin
if (read) begin
dataout <= memory[addr];
end else begin
dataout <= 4'b0000;
end
end
//Synchronous write
always @(posedge clk) begin
if (write) begin
memory[addr] <= datain;
//Display message in transcript window.
$display("%b", memory[addr]);
end
end
endmodule
| 7.148942 |
module rw_seperate_ram_tb ();
reg [3:0] t_datain;
reg [3:0] t_addr;
reg t_read;
reg t_write;
wire [3:0] t_dataout;
rw_seperate_ram dut (
.datain (t_datain),
.addr (t_addr),
.read (t_read),
.write (t_write),
.dataout(t_dataout)
);
//Generates the read and write signal
initial begin
t_read = 1;
t_write = 0;
#12 t_read = 0;
t_write = 0;
#12 t_read = 1;
t_write = 0;
#12 t_read = 0;
t_write = 0;
#12 t_read = 1;
t_write = 0;
#12 t_read = 0;
t_write = 0;
#12 t_read = 0;
t_write = 1;
#12 t_read = 0;
t_write = 0;
end
//Generates the input data
initial begin
t_datain = 4'h4;
#12;
t_datain = 4'h6;
#12;
t_datain = 4'h1;
#12;
t_datain = 4'hA;
#12;
t_datain = 4'hF;
#12;
t_datain = 4'h0;
end
//Memory address
initial begin
t_addr = 4'h2;
#10 t_addr = 4'h3;
#10 t_addr = 4'hA;
#10 t_addr = 4'hF;
#10 t_addr = 4'h1;
#10 t_addr = 4'h6;
#10 t_addr = 4'hB;
#50 $finish;
end
endmodule
| 6.780476 |
module SYNCH_FIFO #(
parameter data_width = 25,
parameter addr_width = 8,
parameter depth = 61
) (
/// Control signal
input clk,
input rd_en,
input wr_en,
input rst_n,
/// status signal
output empty,
output full,
/// data signal
output reg [data_width-1:0] data_out,
input [data_width-1:0] data_in
);
reg [ addr_width:0] cnt;
reg [data_width-1:0] fifo_mem[0:depth-1];
reg [addr_width-1:0] rd_ptr;
reg [addr_width-1:0] wr_ptr;
/// Status generation
assign empty = (cnt == 0);
assign full = (cnt == depth);
/// Updata read pointer && Read operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rd_ptr <= 0;
else if (rd_en && !empty) begin
rd_ptr <= rd_ptr + 1;
if (rd_ptr == 60) rd_ptr <= 0;
end else rd_ptr <= rd_ptr;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) data_out <= 0;
else if (rd_en && !empty) data_out <= fifo_mem[rd_ptr];
end
/// Update write pointer && write operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) wr_ptr <= 0;
else if (wr_en && !full) begin
wr_ptr <= wr_ptr + 1;
if (wr_ptr == 60) wr_ptr <= 0;
end else wr_ptr <= wr_ptr;
end
always @(posedge clk) begin
if (wr_en && !full) fifo_mem[wr_ptr] = data_in;
end
/// Update the counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 0;
else begin
case ({
wr_en, rd_en
})
2'b00: cnt <= cnt;
2'b01: cnt <= !empty ? cnt - 1 : cnt;
2'b10: cnt <= !full ? cnt + 1 : cnt;
2'b11: cnt <= cnt;
endcase
end
end
endmodule
| 8.231823 |
module Synch_out (
input clk,
rst,
input [31:0] dat_in,
input cyc_i,
input stb_i,
output ack_o,
output reg time_syn_run,
input time_syn_done,
output reg [31:0] dat_out,
output reg cyc_o,
stb_o,
output we_o,
input ack_i
);
reg cyc_i_pp;
always @(posedge clk) begin
if (rst) cyc_i_pp <= 1'b0;
else cyc_i_pp <= cyc_i;
end
always @(posedge clk) begin
if (rst) time_syn_run <= 1'b0;
else if (cyc_i & (~cyc_i_pp)) time_syn_run <= 1'b1;
else if (time_syn_done) time_syn_run <= 1'b0;
end
reg syn_done;
always @(posedge clk) begin
if (rst) syn_done <= 1'b0;
else if (time_syn_done) syn_done <= 1'b1;
else if (~cyc_i) syn_done <= 1'b0;
end
always @(posedge clk) begin
if (rst) begin
dat_out <= 32'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
end else if (syn_done) begin
cyc_o <= 1'b1;
dat_out <= dat_in;
stb_o <= stb_i;
end else if (~cyc_i) begin
dat_out <= 32'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
end
end
assign ack_o = (cyc_i & stb_i & (ack_i | (~stb_o)));
assign we_o = stb_o;
endmodule
| 6.593513 |
module synch_ram #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire write_en,
input wire [ADDR_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data_in,
output wire [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr;
always @(posedge clk) begin
if (write_en) ram[addr] <= data_in;
q_addr <= addr;
end
assign data_out = ram[q_addr];
endmodule
| 8.110761 |
module synch_reg #(
parameter wbits = 128
) (
input clock,
input resetn,
input wen,
input ren,
input [wbits-1:0] wdata,
output [wbits-1:0] rdata,
output reg full,
output empty
);
reg [wbits-1:0] mem;
always @(posedge clock) begin
if (!resetn) begin
full <= 1'b0;
mem <= 128'h0;
end else if (wen & (~full)) begin
full <= 1'b1;
mem <= wdata;
end else if (ren & full) begin
full <= 1'b0;
end
end
assign empty = ~full;
assign rdata = mem;
endmodule
| 7.918275 |
module syncInput (
input clk,
input btn,
output reg syncBtn = 0
);
reg b1;
reg b2;
always @(posedge clk) begin
b1 <= btn;
b2 <= b1;
if (b1 && !b2) begin
syncBtn <= 1;
end
if (!b1 && b2) begin
syncBtn <= 0;
end
end
endmodule
| 6.850704 |
module is the behavioral level model of the counter.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncJohn(out, clk, rst);
output reg [3:0] out; // present state output
input clk, rst;
// DFF
always @(posedge clk)
if (!rst)
out <= 4'b0000;
else begin
out[3] <= ~out[0];
out[2:0] <= out[3:1];
end
endmodule
| 7.595207 |
module is intended for use with GTKwave on the PC.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
`include "syncJohn.v"
module syncJohnGTK;
// connect the two modules
wire [3:0] outBench;
wire clkBench, rstBench;
// declare an instance of the syncJohn module
syncJohn mySyncJohn (outBench, clkBench, rstBench);
// declare an instance of the testIt module
Tester aTester (rstBench, clkBench, outBench);
// file for gtkwave
initial
begin
$dumpfile("syncJohn.vcd");
$dumpvars(1, mySyncJohn);
end
endmodule
| 9.106975 |
module is intended for use with the DE1_SoC and Spinal Tap.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncJohnTop (LEDR, CLOCK_50, SW);
output [3:0] LEDR;
input CLOCK_50;
input [9:0] SW;
wire [31:0] clk; // choosing from 32 different clock speeds
syncJohn mySyncJohn (LEDR[3:0], clk[0], SW[9]); // Instantiate syncJohn module; clock speed 0.75Hz
clock_divider cdiv (CLOCK_50, clk); // Instantiate clock_divider module
endmodule
| 9.106975 |
module clock_divider (
clock,
divided_clocks
);
input clock;
output [31:0] divided_clocks;
reg [31:0] divided_clocks;
initial divided_clocks = 0;
always @(posedge clock) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module synCordicAtan (clk, rst, en, x, y, atanOut); // {
22 //省略了非关键性代码，完整内容请参考电子附件
23 assign negzo = -zo;
24 assign tmpx = -x;
25 assign tmpy = -y;//调用Cordic流水实现，由多个旋转模块串接组合而成
28 CordicSeq cs (.clk(clk),.rst(rst), .en(en), .xi(xi), .yi(yi), .zi(zi), .xo(xo),.yo(yo),.zo(zo));
39 always @( posedge clk)
40 begin
41 if (rst==1’b1)
42 begin
43 rcnt <= 0; //旋转次数
44 xi <= 0;
45 yi <= 0;
46 atanOut <= 0; //角度输出
47 for (i=0;i<depth;i=i+1)
48 quadrant[i] <= 2'b00;
49 end
50 else if (en)
51 begin
52 if(rcnt!=depth)
53 rcnt <= rcnt+1;
54
55 if (x[bitWidth-1] == 0)
56 xi <= {x[bitWidth-1],x[bitWidth-1],x};
57 else
58 xi <= {tmpx[bitWidth-1],tmpx[bitWidth-1],tmpx};
59
60 if (y[bitWidth-1] == 0)
61 yi <= {y[bitWidth-1],y[bitWidth-1],y};
62 else
63 yi <= {tmpy[bitWidth-1],tmpy[bitWidth-1],tmpy};
64
65 quadrant[0][0] <= x[bitWidth-1];
66 quadrant[0][1] <= y[bitWidth-1];
67
68 for (i=0;i<depth-1;i=i+1)
69 quadrant[i+1] <= quadrant[i];
70
71 if(rcnt==depth)
72 case (quadrant[depth-1])
73 2'b00 : atanOut <= zo;
74 2'b01 : atanOut <= {1'b1, tmpzero} - $unsigned(zo);
75 2'b10 : atanOut <= negzo; // use intermediate to force sizing
76 default : atanOut <= {1'b1, tmpzero} + $unsigned(zo);
77 endcase
78 end // if
79 end // always
80
81 endmodule
| 6.664238 |
module synCordicSinCos (clk, rst, en, inp, sinout, cosout); // {
18 parameter signed [29:0] xif=128'b0010_0110_1101_1101_0011_1011_0110_10;
23 parameter signed [bitWidth-1:0] xi = xif[29:30-bitWidth];//正弦比例k值
24 parameter signed [bitWidth-1:0] yi = 0;
25 wire signed [angBitWidth-2:0] zo;
27
28 assign argi = inp[angBitWidth-3:0];//四个象限，所以去除高2bit，后面再恢复
29 assign tmpzero = 0;
31 CordicSeq cs (.clk(clk),.rst(rst),.en(en),.xi(xi),.yi(yi),.zi(arg),
xo(cosarg),.yo(sinarg),.zo(zo));
41 assign sel = inp[angBitWidth-1:angBitWidth-2];
42
43 always @( posedge clk) //csc
54 if (en) begin
56 if(rcnt!=depth+1)
57 rcnt <= rcnt+1;
58
59 case(sel)
60 2'b00: begin
62 arg <= {1'b0,argi};
63 csgn[0] <= 0;
64 ssgn[0] <= 0;
65 end
66 2'b01: begin // 校正到第二象限符号，因为现在求的是第一象限角度。
68 arg <= {1'b1,tmpzero} - argi;
69 csgn[0] <= 1;
70 if (argi == 0)
71 ssgn[0] <= 1;
72 else
73 ssgn[0] <= 0;
74 end
75 2'b10: begin // 校正到第三象限符号，因为现在求的是第一象限角度。
77 arg <= {1'b0,argi};
78 csgn[0] <= 1;
79 ssgn[0] <= 1;
80 end
81 default: begin // 校正到第四象限符号，因为现在求的是第一象限角度。
83 arg <= {1'b1,tmpzero} - argi;
84 csgn[0] <= 0;
85 if (argi == 0)
86 ssgn[0] <= 0;
87 else
88 ssgn[0] <= 1;
89 end
90 endcase
92 // propagate the signs
93 for (i=0;i<depth;i=i+1)
94 begin
95 csgn[i+1] <= csgn[i];
96 ssgn[i+1] <= ssgn[i];
97 end // for
99 // record the output
100 if(rcnt==depth+1)
101 begin
102 if (csgn[depth]==0)
103 cosout <= cosarg;
104 else
105 cosout <= -cosarg;
107 if (ssgn[depth]==0)
108 sinout <= sinarg;
109 else
110 sinout <= -sinarg;
111 end
112 else
113 begin
114 cosout <= 0;
115 sinout <= 0;
116 end
117 end // if (rst)...else if (en)
119 end // always @(posedge clk)
121 endmodule
| 7.518259 |
module syncout (
rst,
clk32,
clk_i,
clk_d2,
datain,
Bit_Sync,
dataout
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
input clk_d2;
input clk_i;
input [5:0] datain;
output Bit_Sync;
output [5:0] dataout;
//检测分频器输出的同相支路信号，上升沿产生位同步脉冲
reg clki, sync;
always @(posedge clk32 or posedge rst)
if (rst) begin
sync <= 0;
clki <= 0;
end else begin
clki <= clk_i;
if ((clki == 1'b0) & (clk_i == 1'b1)) sync <= 1'b1;
else sync <= 1'b0;
end
assign Bit_Sync = sync;
//为补偿位同步脉冲在运算过程中产生的延时，根据仿真结果对数据进行移相处理
//使位同步脉冲与接收数据同步
reg clk_d2_d;
reg [5:0] dtem;
always @(posedge clk32 or posedge rst)
if (rst) begin
clk_d2_d <= 0;
dtem <= 0;
end else begin
clk_d2_d <= clk_d2;
if ((clk_d2 == 1'b0) & (clk_d2_d == 1'b1)) dtem <= datain;
end
assign dataout = dtem;
endmodule
| 6.982085 |
module SyncPulse(
sCLK,
sRST,
dCLK,
sEN,
dPulse
);
// source clock ports
input sCLK ;
input sRST ;
input sEN ;
// destination clock ports
input dCLK ;
output dPulse ;
// Flops to hold data
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
reg dSyncPulse;
assign dPulse = dSyncReg2 != dSyncPulse ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
sSyncReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY ! sSyncReg ;
end
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST )
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = 1'b0 ;
dSyncReg1 = 1'b0 ;
dSyncReg2 = 1'b0 ;
dSyncPulse = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
| 6.967198 |
module syncPulses (
clk9MHz,
hSync,
vSync,
hData,
vData,
clk3Hz,
disp,
vgaCount,
lineCount,
start
);
input clk9MHz;
integer vcount, hzcount;
output reg [9:0] vgaCount;
output reg [8:0] lineCount;
reg hData, vData; // horizontal data enable, vertical data enable
integer startCount; // to output 10 black frames at the start
output reg hSync, vSync; // 640 clk9MHz to 1 hSync, 480 hSync to 1 vSync
// OR, timing diagram says
// 41+484 clk9MHz to 1 hSync
// 10+276 hSync to 1 vSync
output hData, vData; // enable signals for data transfer
output reg clk3Hz, disp, start; // character change clock 3 Hz
initial begin
hSync = 0;
vSync = 1;
hData = 0;
vData = 0;
vgaCount = 0;
lineCount = 0;
hzcount = 0;
clk3Hz = 0;
disp = 0;
start = 0;
startCount = 0;
end
always @(posedge clk9MHz) begin
if (~start) begin
disp = 1;
vSync = 0;
startCount = startCount + 1;
if (startCount == 9) start = 1;
end else if (start) begin
// vgaCount counts clock cycles and controls hSync pulses, vgaCount can also be used to determine the horizontal location of the pixel being set
vgaCount = vgaCount + 10'b0000000001;
if (vgaCount == 0) hSync = 0;
if (vgaCount == 41) hSync = 1;
if (vgaCount == 43) hData = 1;
if (vgaCount == 523) // TODO: figure out if this is 523 or 524, in timing diagram it looks like data must be held until rising edge of next cycle
hData = 0;
if (vgaCount == 525) // if vga reaches its cycle
begin
vgaCount = 0; // reset vgaCount
hSync = 0; // invert hSync
lineCount = lineCount + 9'b000000001; // increment lineCount
end
// lineCount controls vSync
if (lineCount == 0) vSync = 0;
if (lineCount == 10) vSync = 1;
if (lineCount == 12) vData = 1;
if (lineCount == 284) // TODO: figure out if this is 284 or 285, in timing diagram it looks like data must be held until rising edge of next cycle
vData = 0;
if (lineCount == 286) begin
lineCount = 0;
vSync = 0;
end
end
// clock for user input
hzcount = hzcount + 1;
if (hzcount == 4000000) begin
clk3Hz = ~clk3Hz;
hzcount = 0;
end
end
endmodule
| 7.057983 |
module syncRAM (
clk,
resetn,
dataIn,
Addr,
CS,
RD,
dataOut
);
// parameters for the width
parameter ADDR = 8;
parameter DATA = 8;
parameter DEPTH = 8;
//ports
input clk;
input resetn;
input [ADDR-1:0] Addr;
input [DATA-1:0] dataIn;
input CS, RD;
output reg [DATA-1:0] dataOut;
//internal variables
reg [DATA-1:0] SRAM[DEPTH-1:0];
always @(posedge clk or negedge resetn) begin
if (CS == 1'b1) begin
if (RD == 1'b0) begin
SRAM[Addr] = dataIn;
end else begin
dataOut = SRAM[Addr];
end
end
end
endmodule
| 8.718308 |
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