code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module c_gate_0_8 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 6.999778 |
module latch_controller_1_8 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_8 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U2 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module select_element_4 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);
HS65_LS_LDLRQX9 false_latch_out_reg (
.RN(n3),
.Q (false),
.GN(sel),
.D (n2)
);
HS65_LS_IVX9 U3 (
.Z(n3),
.A(preset)
);
HS65_LSS_XOR2X6 U4 (
.Z(n1),
.B(false),
.A(\input )
);
HS65_LSS_XOR2X6 U5 (
.Z(n2),
.B(true),
.A(\input )
);
endmodule
| 6.561954 |
module c_gate_0_14 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_18 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.06524 |
module c_gate_0_9 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_9 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.105424 |
module latch_controller_1_9 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_9 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U2 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module switch_output (
/* inputs */
d_in_NW,
d_in_N,
d_in_E,
d_in_W,
d_in_S,
conf,
/* outputs */
d_out,
select_NW, // Is NW input data being used?
select_N,
select_E,
select_W,
select_S
);
input [`PATH_WIDTH:0] d_in_NW;
input [`PATH_WIDTH:0] d_in_N;
input [`PATH_WIDTH:0] d_in_E;
input [`PATH_WIDTH:0] d_in_W;
input [`PATH_WIDTH:0] d_in_S;
input [3:0] conf;
output [`PATH_WIDTH:0] d_out;
output select_NW;
output select_N;
output select_E;
output select_W;
output select_S;
///////////////////////////////////////////
//
// wires
//
//////////////////////////////////////////
wire [`PATH_WIDTH:0] data1;
//////////////////////////////////////////
//
// data mux - first level
//
//////////////////////////////////////////
// At the moment this is a 16->1 MUX
// It can be optimized manually to a 8->1 MUX as there
// are only 5 "real" inputs
// The reason this is not already been done is that the Xilinx
// optimizer does this automatically
assign data1 = (conf[3:0] == 4'b0000 ? {`PATH_WIDTH{1'b0}} : // turned off
conf[3:0] == 4'b0001 ? d_in_NW :
conf[3:0] == 4'b0010 ? d_in_E :
conf[3:0] == 4'b0011 ? d_in_N :
conf[3:0] == 4'b0100 ? d_in_S :
conf[3:0] == 4'b0101 ? d_in_NW :
conf[3:0] == 4'b0110 ? d_in_E :
conf[3:0] == 4'b0111 ? d_in_N :
conf[3:0] == 4'b1000 ? d_in_W :
conf[3:0] == 4'b1001 ? d_in_NW :
conf[3:0] == 4'b1010 ? d_in_E :
conf[3:0] == 4'b1011 ? d_in_N :
conf[3:0] == 4'b1100 ? d_in_S :
conf[3:0] == 4'b1101 ? d_in_NW :
conf[3:0] == 4'b1110 ? d_in_E :
/*conf[3:0] == 4'b1111*/ d_in_N);
//////////////////////////////////////////
//
// data inputs being selected
//
//////////////////////////////////////////
assign select_NW = (conf[3:0] == 4'b0001) |
(conf[3:0] == 4'b0101) |
(conf[3:0] == 4'b1001) |
(conf[3:0] == 4'b1101) |
(conf[3:0] == 4'b1110);
assign select_N = (conf[3:0] == 4'b0011) |
(conf[3:0] == 4'b0111) |
(conf[3:0] == 4'b1011) |
(conf[3:0] == 4'b1101) |
(conf[3:0] == 4'b1111);
assign select_E = (conf[3:0] == 4'b0010) |
(conf[3:0] == 4'b0110) |
(conf[3:0] == 4'b1010) |
(conf[3:0] == 4'b1110) |
(conf[3:0] == 4'b1111);
assign select_W = (conf[3:0] == 4'b1000) |
(conf[3:0] == 4'b1001) |
(conf[3:0] == 4'b1010) |
(conf[3:0] == 4'b1011) |
(conf[3:0] == 4'b1100);
assign select_S = (conf[3:0] == 4'b0100) |
(conf[3:0] == 4'b0101) |
(conf[3:0] == 4'b0110) |
(conf[3:0] == 4'b0111) |
(conf[3:0] == 4'b1100);
//////////////////////////////////////////
//
// data mux - second level
//
//////////////////////////////////////////
assign d_out = data1;
//////////////////////////////////////////
//
//
//
//////////////////////////////////////////
endmodule
| 9.107562 |
module switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [17:0] readdata;
input [1:0] address;
input clk;
input [17:0] in_port;
input reset_n;
wire clk_en;
wire [17:0] data_in;
wire [17:0] read_mux_out;
reg [17:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
| 6.552887 |
module switch_post_top (
input clk,
input rstn,
input o_cell_fifo_wr,
input [ 3:0] o_cell_fifo_sel,
input [127:0] o_cell_fifo_din,
input o_cell_first,
input o_cell_last,
output [ 3:0] o_cell_bp,
input data_fifo_rd0,
output [ 7:0] data_fifo_dout0,
input ptr_fifo_rd0,
output [15:0] ptr_fifo_dout0,
output ptr_fifo_empty0,
input data_fifo_rd1,
output [ 7:0] data_fifo_dout1,
input ptr_fifo_rd1,
output [15:0] ptr_fifo_dout1,
output ptr_fifo_empty1,
input data_fifo_rd2,
output [ 7:0] data_fifo_dout2,
input ptr_fifo_rd2,
output [15:0] ptr_fifo_dout2,
output ptr_fifo_empty2,
input data_fifo_rd3,
output [ 7:0] data_fifo_dout3,
input ptr_fifo_rd3,
output [15:0] ptr_fifo_dout3,
output ptr_fifo_empty3
);
wire o_cell_data_fifo_bp_0;
wire o_cell_data_fifo_bp_1;
wire o_cell_data_fifo_bp_2;
wire o_cell_data_fifo_bp_3;
assign o_cell_bp = {
o_cell_data_fifo_bp_3, o_cell_data_fifo_bp_2, o_cell_data_fifo_bp_1, o_cell_data_fifo_bp_0
};
switch_post post0 (
.clk (clk),
.rstn(rstn),
.o_cell_data_fifo_wr(o_cell_fifo_wr && o_cell_fifo_sel[0]),
.o_cell_data_fifo_din(o_cell_fifo_din),
.o_cell_data_first(o_cell_first),
.o_cell_data_last(o_cell_last),
.o_cell_data_fifo_bp(o_cell_data_fifo_bp_0),
.ptr_fifo_rd(ptr_fifo_rd0),
.ptr_fifo_dout(ptr_fifo_dout0),
.ptr_fifo_empty(ptr_fifo_empty0),
.data_fifo_rd(data_fifo_rd0),
.data_fifo_dout(data_fifo_dout0)
);
switch_post post1 (
.clk (clk),
.rstn(rstn),
.o_cell_data_fifo_wr(o_cell_fifo_wr && o_cell_fifo_sel[1]),
.o_cell_data_fifo_din(o_cell_fifo_din),
.o_cell_data_first(o_cell_first),
.o_cell_data_last(o_cell_last),
.o_cell_data_fifo_bp(o_cell_data_fifo_bp_1),
.ptr_fifo_rd(ptr_fifo_rd1),
.ptr_fifo_dout(ptr_fifo_dout1),
.ptr_fifo_empty(ptr_fifo_empty1),
.data_fifo_rd(data_fifo_rd1),
.data_fifo_dout(data_fifo_dout1)
);
switch_post post2 (
.clk (clk),
.rstn(rstn),
.o_cell_data_fifo_wr(o_cell_fifo_wr && o_cell_fifo_sel[2]),
.o_cell_data_fifo_din(o_cell_fifo_din),
.o_cell_data_first(o_cell_first),
.o_cell_data_last(o_cell_last),
.o_cell_data_fifo_bp(o_cell_data_fifo_bp_2),
.ptr_fifo_rd(ptr_fifo_rd2),
.ptr_fifo_dout(ptr_fifo_dout2),
.ptr_fifo_empty(ptr_fifo_empty2),
.data_fifo_rd(data_fifo_rd2),
.data_fifo_dout(data_fifo_dout2)
);
switch_post post3 (
.clk (clk),
.rstn(rstn),
.o_cell_data_fifo_wr(o_cell_fifo_wr && o_cell_fifo_sel[3]),
.o_cell_data_fifo_din(o_cell_fifo_din),
.o_cell_data_first(o_cell_first),
.o_cell_data_last(o_cell_last),
.o_cell_data_fifo_bp(o_cell_data_fifo_bp_3),
.ptr_fifo_rd(ptr_fifo_rd3),
.ptr_fifo_dout(ptr_fifo_dout3),
.ptr_fifo_empty(ptr_fifo_empty3),
.data_fifo_rd(data_fifo_rd3),
.data_fifo_dout(data_fifo_dout3)
);
endmodule
| 6.77809 |
module switch_pre (
input clk,
input rstn,
input sof,
input dv,
input [ 7:0] din,
output reg [127:0] i_cell_data_fifo_dout,
output reg i_cell_data_fifo_wr,
output reg [ 15:0] i_cell_ptr_fifo_dout,
output reg i_cell_ptr_fifo_wr,
input i_cell_bp
);
reg [7:0] word_num;
reg [4:0] state;
reg [3:0] i_cell_portmap;
always @(posedge clk or negedge rstn)
if (!rstn) begin
word_num <= #2 0;
state <= #2 0;
i_cell_data_fifo_dout <= #2 0;
i_cell_portmap <= #2 0;
i_cell_data_fifo_wr <= #2 0;
i_cell_ptr_fifo_dout <= #2 0;
i_cell_ptr_fifo_wr <= #2 0;
end else begin
i_cell_data_fifo_wr <= #2 0;
i_cell_ptr_fifo_wr <= #2 0;
case (state)
0: begin
word_num <= #2 0;
if (sof & !i_cell_bp) begin
i_cell_data_fifo_dout[127:120] <= #2 din;
i_cell_portmap <= #2 din[3:0];
state <= #2 1;
end
end
1: begin
i_cell_data_fifo_dout[119:112] <= #2 din;
state <= #2 2;
end
2: begin
i_cell_data_fifo_dout[111:104] <= #2 din;
state <= #2 3;
end
3: begin
i_cell_data_fifo_dout[103:96] <= #2 din;
state <= #2 4;
end
4: begin
i_cell_data_fifo_dout[95:88] <= #2 din;
state <= #2 5;
end
5: begin
i_cell_data_fifo_dout[87:80] <= #2 din;
state <= #2 6;
end
6: begin
i_cell_data_fifo_dout[79:72] <= #2 din;
state <= #2 7;
end
7: begin
i_cell_data_fifo_dout[71:64] <= #2 din;
state <= #2 8;
end
8: begin
i_cell_data_fifo_dout[63:56] <= #2 din;
state <= #2 9;
end
9: begin
i_cell_data_fifo_dout[55:48] <= #2 din;
state <= #2 10;
end
10: begin
i_cell_data_fifo_dout[47:40] <= #2 din;
state <= #2 11;
end
11: begin
i_cell_data_fifo_dout[39:32] <= #2 din;
state <= #2 12;
end
12: begin
i_cell_data_fifo_dout[31:24] <= #2 din;
state <= #2 13;
end
13: begin
i_cell_data_fifo_dout[23:16] <= #2 din;
state <= #2 14;
end
14: begin
i_cell_data_fifo_dout[15:8] <= #2 din;
state <= #2 15;
end
15: begin
i_cell_data_fifo_dout[7:0] <= #2 din;
i_cell_data_fifo_wr <= #2 1;
word_num <= #2 word_num + 1;
state <= #2 16;
end
16: begin
if (dv) begin
i_cell_data_fifo_dout[127:120] <= #2 din;
state <= #2 1;
end else begin
i_cell_ptr_fifo_dout <= #2{4'b0, i_cell_portmap[3:0], 2'b0, word_num[7:2]};
i_cell_ptr_fifo_wr <= #2 1;
state <= #2 0;
end
end
endcase
end
endmodule
| 7.423376 |
module: switch_pre
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module switch_pre_tb;
// Inputs
reg clk;
reg rstn;
reg data_sof;
reg data_dv;
reg [7:0] data_in;
reg i_cell_ack;
// Outputs
wire [127:0] i_cell_fifo_dout;
wire i_cell_fifo_wr;
wire [15:0] i_cell_ptr_fifo_dout;
wire i_cell_ptr_fifo_wr;
always #5 clk=~clk;
// Instantiate the Unit Under Test (UUT)
switch_pre uut (
.clk(clk),
.rstn(rstn),
.sof(data_sof),
.dv(data_dv),
.din(data_in),
.i_cell_data_fifo_dout(i_cell_fifo_dout),
.i_cell_data_fifo_wr(i_cell_fifo_wr),
.i_cell_ptr_fifo_dout(i_cell_ptr_fifo_dout),
.i_cell_ptr_fifo_wr(i_cell_ptr_fifo_wr),
.i_cell_bp(1'b0)
);
initial begin
// Initialize Inputs
clk = 0;
rstn = 0;
data_sof = 0;
data_dv = 0;
data_in = 0;
i_cell_ack = 0;
// Wait 100 ns for global reset to finish
#500;
rstn=1;
#500;
// Add stimulus here
send_frame(128,4'b0001);
#100;
send_frame(256,4'b0001);
#100
send_frame(64,4'b0001);
end
task send_frame;
input [11:0] len;
input [3:0] portmap;
integer i;
begin
repeat(1)@(posedge clk);
#2;
for(i=0;i<len;i=i+1)begin
if(i==0) begin
data_sof=1;
data_dv=1;
data_in={len[11:8],portmap[3:0]};
end
else if(i==1) begin
data_sof=0;
data_dv=1;
data_in=len[7:0];
end
else begin
data_in=i[7:0];
end
repeat(1)@(posedge clk);
#2;
end
data_dv=0;
data_in=0;
end
endtask
endmodule
| 6.857429 |
module switch_qc (
input clk,
input rstn,
input [15:0] q_din,
input q_wr,
output q_full,
output ptr_rdy,
input ptr_ack,
output [15:0] ptr_dout
);
reg [15:0] ptr_din;
reg ptr_wr;
reg q_rd;
wire [15:0] q_dout;
wire q_empty;
sfifo_w16_d32 u_ptr_wr_fifo (
.clk(clk),
.rst(!rstn),
.din(q_din[15:0]),
.wr_en(q_wr),
.rd_en(q_rd),
.dout(q_dout),
.full(q_full),
.empty(q_empty),
.data_count()
);
reg [1:0] wr_state;
reg ptr_wr_ack;
always @(posedge clk or negedge rstn)
if (!rstn) begin
ptr_din <= #2 0;
ptr_wr <= #2 0;
q_rd <= #2 0;
wr_state <= #2 0;
end else begin
case (wr_state)
0: begin
if (!q_empty) begin
q_rd <= #2 1;
wr_state <= #2 1;
end
end
1: begin
q_rd <= #2 0;
wr_state <= #2 2;
end
2: begin
ptr_din <= #2 q_dout[15:0];
ptr_wr <= #2 1;
wr_state <= #2 3;
end
3: begin
if (ptr_wr_ack) begin
ptr_wr <= #2 0;
wr_state <= #2 0;
end
end
endcase
end
reg ptr_rd;
reg [15:0] ptr_fifo_din;
reg ptr_rd_ack;
reg [15:0] head;
reg [15:0] tail;
reg [15:0] depth_cell;
reg depth_flag;
reg [15:0] depth_frame;
reg [15:0] ptr_ram_din;
wire [15:0] ptr_ram_dout;
reg ptr_ram_wr;
reg [ 9:0] ptr_ram_addr;
reg [ 3:0] mstate;
always @(posedge clk or negedge rstn)
if (!rstn) begin
mstate <= #2 0;
ptr_ram_wr <= #2 0;
ptr_wr_ack <= #2 0;
head <= #2 0;
tail <= #2 0;
depth_cell <= #2 0;
depth_frame <= #2 0;
ptr_rd_ack <= #2 0;
ptr_ram_din <= #2 0;
ptr_ram_addr <= #2 0;
ptr_fifo_din <= #2 0;
depth_flag <= #2 0;
end else begin
ptr_wr_ack <= #2 0;
ptr_rd_ack <= #2 0;
ptr_ram_wr <= #2 0;
case (mstate)
0: begin
if (ptr_wr) begin
mstate <= #2 1;
end else if (ptr_rd) begin
ptr_fifo_din <= #2 head;
ptr_ram_addr[9:0] <= #2 head[9:0];
mstate <= #2 3;
end
end
1: begin
if (depth_cell[9:0]) begin
ptr_ram_wr <= #2 1;
ptr_ram_addr[9:0] <= #2 tail[9:0];
ptr_ram_din[15:0] <= #2 ptr_din[15:0];
tail <= #2 ptr_din;
end else begin
ptr_ram_wr <= #2 1;
ptr_ram_addr[9:0] <= #2 ptr_din[9:0];
ptr_ram_din[15:0] <= #2 ptr_din[15:0];
tail <= #2 ptr_din;
head <= #2 ptr_din;
end
depth_cell <= #2 depth_cell + 1;
if (ptr_din[15]) begin
depth_flag <= #2 1;
depth_frame <= #2 depth_frame + 1;
end
ptr_wr_ack <= #2 1;
mstate <= #2 2;
end
2: begin
ptr_ram_addr <= #2 tail[9:0];
ptr_ram_din <= #2 tail[15:0];
ptr_ram_wr <= #2 1;
mstate <= #2 0;
end
3: begin
ptr_rd_ack <= #2 1;
mstate <= #2 4;
end
//============================================
//another cycle for ram
//============================================
4: begin
mstate <= #2 5;
end
5: begin
head <= #2 ptr_ram_dout;
depth_cell <= #2 depth_cell - 1;
if (head[15]) begin
depth_frame <= #2 depth_frame - 1;
if (depth_frame > 1) depth_flag <= #2 1;
else depth_flag <= #2 0;
end
mstate <= #2 0;
end
endcase
end
reg [2:0] rd_state;
wire ptr_full;
wire ptr_empty;
assign ptr_rdy = !ptr_empty;
always @(posedge clk or negedge rstn)
if (!rstn) begin
ptr_rd <= #2 0;
rd_state <= #2 0;
end else begin
case (rd_state)
0: begin
if (depth_flag && !ptr_full) begin
rd_state <= #2 1;
ptr_rd <= #2 1;
end
end
1: begin
if (ptr_rd_ack) begin
ptr_rd <= #2 0;
rd_state <= #2 2;
end
end
2: rd_state <= #2 0;
endcase
end
sram_w16_d512 u_ptr_ram (
.clka (clk),
.wea (ptr_ram_wr),
.addra(ptr_ram_addr[8:0]),
.dina (ptr_ram_din),
.douta(ptr_ram_dout)
);
sfifo_ft_w16_d32 u_ptr_fifo0 (
.clk(clk),
.rst(!rstn),
.din(ptr_fifo_din[15:0]),
.wr_en(ptr_rd_ack),
.rd_en(ptr_ack),
.dout(ptr_dout[15:0]),
.full(ptr_full),
.empty(ptr_empty),
.data_count()
);
endmodule
| 6.933098 |
module switch_seg (
input switch0,
input switch1,
input switch2,
input switch3,
output [6:0] seg,
output [3:0] an
);
reg [6:0] seg_temp;
reg an_temp = 4'b1110;
always @(*) begin
if (switch0 == 1) seg_temp = 7'b1000000;
//0
else if (switch1 == 1) seg_temp = 7'b1111001;
//1
else if (switch2 == 1) seg_temp = 7'b0100100;
//2
else if (switch3 == 1) seg_temp = 7'b0110000;
//3
else
seg_temp = 7'b0111111;
end
assign seg = seg_temp;
assign an = an_temp;
endmodule
| 7.298789 |
module switch_sync (
output reg out,
input clk,
input data
);
always @(posedge clk) begin
out <= data;
end
endmodule
| 6.981364 |
module switch_synchronizers (
input wire i_clk,
input wire [3:0] i_switches,
output wire [3:0] o_switches
);
wire w_switch_1;
synchronizer switch_1_sync (
.i_clk(i_clk),
.i_input(i_switches[0]),
.o_input_sync(w_switch_1)
);
wire w_switch_2;
synchronizer switch_2_sync (
.i_clk(i_clk),
.i_input(i_switches[1]),
.o_input_sync(w_switch_2)
);
wire w_switch_3;
synchronizer switch_3_sync (
.i_clk(i_clk),
.i_input(i_switches[2]),
.o_input_sync(w_switch_3)
);
wire w_switch_4;
synchronizer switch_4_sync (
.i_clk(i_clk),
.i_input(i_switches[3]),
.o_input_sync(w_switch_4)
);
assign o_switches = {w_switch_4, w_switch_3, w_switch_2, w_switch_1};
endmodule
| 7.393011 |
module: SWITCH
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SWITCH_tb;
// Inputs
reg x1;
reg x2;
reg x3;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
SWITCH uut (
.x1(x1),
.x2(x2),
.x3(x3),
.y(y)
);
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
#20
x1 = 0;
x2 = 0;
x3 = 1;
#20
x1 = 0;
x2 = 1;
x3 = 0;
#20
x1 = 0;
x2 = 1;
x3 = 1;
#20
x1 = 1;
x2 = 0;
x3 = 0;
#20
x1 = 1;
x2 = 0;
x3 = 1;
#20
x1 = 1;
x2 = 1;
x3 = 0;
#20
x1 = 1;
x2 = 1;
x3 = 1;
#20
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.512897 |
module switch_testBench ();
reg clock;
reg [3:0] SW;
wire [3:0] switchesUp;
wire PWM_pulse;
switch UUT (
.clock(clock),
.SW(SW),
.switchesUp(switchesUp)
);
PWM pwmInst (
.clock(clock),
.enable(1),
.speed(SW),
.PWM_pulse(PWM_pulse)
);
initial begin
clock <= 0;
SW <= 0;
#10 SW <= 1;
#1000001 SW <= 2;
#1000001 SW <= 3;
#1000001 SW <= 4;
#1000001 SW <= 0;
end
// initial
// begin
// SW <= 4'b0001;
// #100
// SW <= 4'b0010;
// #100
// SW <= 4'b0011;
// #100
// SW <= 4'b0100;
// #100
// SW <= 4'b0101;
// #100
// SW <= 4'b0110;
// #100
// SW <= 4'b0111;
// #100
// SW <= 4'b1000;
// #100
// SW <= 4'b1001;
// #100
// SW <= 4'b1010;
// #100
// SW <= 4'b1011;
// #100
// SW <= 4'b1100;
// #100
// SW <= 4'b1101;
// #100
// SW <= 4'b1110;
// #100
// SW <= 4'b1111;
// #100
// SW <= 4'b0110;
// #100
// SW <= 4'b1001;
// #100
// SW <= 4'b0001;
// #100
// SW <= 4'b0000;
// end
always begin
#1 clock = ~clock; //1 tick is equivalent to 10^-8 s (period of 100 MHz)
end
endmodule
| 6.813116 |
module switch_top (
input clk,
input rstn,
input sof,
input dv,
input [7:0] din,
input ptr_fifo_rd0,
input ptr_fifo_rd1,
input ptr_fifo_rd2,
input ptr_fifo_rd3,
input data_fifo_rd0,
input data_fifo_rd1,
input data_fifo_rd2,
input data_fifo_rd3,
output [ 7:0] data_fifo_dout0,
output [ 7:0] data_fifo_dout1,
output [ 7:0] data_fifo_dout2,
output [ 7:0] data_fifo_dout3,
output [15:0] ptr_fifo_dout0,
output [15:0] ptr_fifo_dout1,
output [15:0] ptr_fifo_dout2,
output [15:0] ptr_fifo_dout3,
output ptr_fifo_empty0,
output ptr_fifo_empty1,
output ptr_fifo_empty2,
output ptr_fifo_empty3
);
wire [127:0] i_cell_data_fifo_dout;
wire i_cell_data_fifo_wr;
wire [ 15:0] i_cell_ptr_fifo_dout;
wire i_cell_ptr_fifo_wr;
wire i_cell_bp;
wire o_cell_fifo_wr;
wire [ 3:0] o_cell_fifo_sel;
wire o_cell_first;
wire o_cell_last;
wire [127:0] o_cell_fifo_din;
wire [ 7:0] o_cell_ptr;
wire [ 3:0] o_cell_bp;
switch_pre pre (
.clk (clk),
.rstn(rstn),
.sof(sof),
.dv (dv),
.din(din),
.i_cell_data_fifo_dout(i_cell_data_fifo_dout),
.i_cell_data_fifo_wr(i_cell_data_fifo_wr),
.i_cell_ptr_fifo_dout(i_cell_ptr_fifo_dout),
.i_cell_ptr_fifo_wr(i_cell_ptr_fifo_wr),
.i_cell_bp(i_cell_bp)
);
switch_core core (
.clk (clk),
.rstn(rstn),
.i_cell_data_fifo_din(i_cell_data_fifo_dout),
.i_cell_data_fifo_wr(i_cell_data_fifo_wr),
.i_cell_ptr_fifo_din(i_cell_ptr_fifo_dout),
.i_cell_ptr_fifo_wr(i_cell_ptr_fifo_wr),
.i_cell_bp(i_cell_bp),
.o_cell_fifo_wr(o_cell_fifo_wr),
.o_cell_fifo_sel(o_cell_fifo_sel),
.o_cell_fifo_din(o_cell_fifo_din),
.o_cell_first(o_cell_first),
.o_cell_last(o_cell_last),
.o_cell_bp(o_cell_bp)
);
switch_post_top u_switch_post_top (
.clk (clk),
.rstn(rstn),
.o_cell_fifo_wr(o_cell_fifo_wr),
.o_cell_fifo_sel(o_cell_fifo_sel),
.o_cell_fifo_din(o_cell_fifo_din),
.o_cell_first(o_cell_first),
.o_cell_last(o_cell_last),
.o_cell_bp(o_cell_bp),
.ptr_fifo_rd0(ptr_fifo_rd0),
.ptr_fifo_rd1(ptr_fifo_rd1),
.ptr_fifo_rd2(ptr_fifo_rd2),
.ptr_fifo_rd3(ptr_fifo_rd3),
.data_fifo_rd0(data_fifo_rd0),
.data_fifo_rd1(data_fifo_rd1),
.data_fifo_rd2(data_fifo_rd2),
.data_fifo_rd3(data_fifo_rd3),
.data_fifo_dout0(data_fifo_dout0),
.data_fifo_dout1(data_fifo_dout1),
.data_fifo_dout2(data_fifo_dout2),
.data_fifo_dout3(data_fifo_dout3),
.ptr_fifo_dout0(ptr_fifo_dout0),
.ptr_fifo_dout1(ptr_fifo_dout1),
.ptr_fifo_dout2(ptr_fifo_dout2),
.ptr_fifo_dout3(ptr_fifo_dout3),
.ptr_fifo_empty0(ptr_fifo_empty0),
.ptr_fifo_empty1(ptr_fifo_empty1),
.ptr_fifo_empty2(ptr_fifo_empty2),
.ptr_fifo_empty3(ptr_fifo_empty3)
);
endmodule
| 6.654788 |
module assumes
that the lowest note is the LSB.
----------------------------------------------------------------------------- */
module switch_to_note(
input clk,
input reset,
input scale_button,
input [5:0] root,
input [7:0] switches,
output reg [47:0] notes
);
wire [1:0] scale_counter;
dffre #(.WIDTH(2)) scale_controller(
.clk(clk),
.r(reset),
.en(scale_button || (scale_counter == 2'd3)),
.d(scale_counter + 2'd1),
.q(scale_counter)
);
//NOTE: THE MAPAPING OF SWITCHES MAY NEED TO CHANGE BASED ON THE INPUT ORIENTATION.
always @(*) begin
if (scale_counter == 2'd0) begin
notes[5:0] = switches[0] ? root + 6'd12 : 6'b0;
notes[11:6] = switches[1] ? root + 6'd11 : 6'b0;
notes[17:12] = switches[2] ? root + 6'd9 : 6'b0;
notes[23:18] = switches[3] ? root + 6'd7 : 6'b0;
notes[29:24] = switches[4] ? root + 6'd5 : 6'b0;
notes[35:30] = switches[5] ? root + 6'd4 : 6'b0;
notes[41:36] = switches[6] ? root + 6'd2 : 6'b0;
notes[47:42] = switches[7] ? root + 6'd0 : 6'b0;
end else if (scale_counter == 2'd1) begin
notes[5:0] = switches[0] ? root + 6'd12 : 6'b0;
notes[11:6] = switches[1] ? root + 6'd10 : 6'b0;
notes[17:12] = switches[2] ? root + 6'd8 : 6'b0;
notes[23:18] = switches[3] ? root + 6'd7 : 6'b0;
notes[29:24] = switches[4] ? root + 6'd5 : 6'b0;
notes[35:30] = switches[5] ? root + 6'd3 : 6'b0;
notes[41:36] = switches[6] ? root + 6'd2 : 6'b0;
notes[47:42] = switches[7] ? root + 6'd0 : 6'b0;
end else begin
notes[5:0] = switches[0] ? 6'd0 : 6'b0;
notes[11:6] = switches[1] ? root + 6'd12 : 6'b0;
notes[17:12] = switches[2] ? root + 6'd10 : 6'b0;
notes[23:18] = switches[3] ? root + 6'd7 : 6'b0;
notes[29:24] = switches[4] ? root + 6'd6 : 6'b0;
notes[35:30] = switches[5] ? root + 6'd5 : 6'b0;
notes[41:36] = switches[6] ? root + 6'd3 : 6'b0;
notes[47:42] = switches[7] ? root + 6'd0 : 6'b0;
end
end
endmodule
| 7.427124 |
module switch_to_note_tb ();
reg [ 5:0] root = 6'b0;
reg [ 7:0] switches = 8'b00000000;
wire [47:0] notes;
switch_to_note SWITCH_TO_NOTE (
.root(root),
.switches(switches),
.notes(notes)
);
//TODO: Just print parsed versions of the notes output to make the tests more legible.
initial begin
#5 switches = 8'b10100010;
#5 switches = 8'b10000000;
#5 switches = 8'b00000001;
#5 switches = 8'b00110000;
#5 switches = 8'b11111111;
#40 root = 6'd23;
switches = 8'b10100010;
#5 switches = 8'b10000000;
#5 switches = 8'b00000001;
#5 switches = 8'b00110000;
#5 switches = 8'b11111111;
end
endmodule
| 7.436012 |
module swo (
clk,
out1,
out2
);
input clk;
output out1;
output out2;
reg [31:0] counter;
reg status;
initial begin
counter <= 32'b0;
status <= 1'b0;
end
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter > 300000) begin
status <= !status;
counter <= 32'b0;
end
end
assign out1 = status;
assign out2 = !status;
endmodule
| 6.501376 |
module SWOCapture #(
parameter DONE_CHAR = 8'h04, // Simulation termination character
parameter BUF_SIZE = 80
) (
input wire CLK,
input wire RESETn,
input wire SWO
);
localparam CHAR_CR = 8'h0D;
localparam CHAR_LF = 8'h0A;
//
// Internal Signals
//
wire [ 7:0] w_rx_char;
reg [ 8:0] r_rx_char;
wire char_received;
reg [ 7:0] line_buf [(BUF_SIZE-1):0];
reg [31:0] idx;
integer i;
//
// Receive Shift Register
//
always @(posedge CLK or negedge RESETn)
if (!RESETn) r_rx_char <= {9{1'b1}};
else begin
if (char_received) r_rx_char <= {9{1'b1}};
else r_rx_char <= {SWO, r_rx_char[8:1]};
end
//
// Received Character
//
assign char_received = ~r_rx_char[0];
assign w_rx_char = r_rx_char[8:1];
//
// Message String Output
//
always @(posedge CLK or negedge RESETn)
if (!RESETn) begin
idx = 32'd0;
for (i = 0; i < BUF_SIZE; i = i + 1) line_buf[i] = 8'h00;
end else if (char_received) begin
// Carriage Return or Line Feed
if ((w_rx_char == CHAR_CR) | (w_rx_char == CHAR_LF)) begin
$write("%t [SWO]: ", $time);
for (i = 0; i < idx; i = i + 1) $write("%s", line_buf[i]);
$write("\n");
idx = 32'd0;
end // DONE Signal
else if (w_rx_char == DONE_CHAR) begin
$write("%t [SWO]: Simulation Ended\n", $time);
$stop;
end // Any Other Character
else begin
line_buf[idx] = w_rx_char;
idx = idx + 1;
// Flush buffer if needed
if (idx >= BUF_SIZE) begin
$write("%t [SWO]: ", $time);
for (i = 0; i < BUF_SIZE; i++) $write("%s", line_buf[i]);
$write("\n");
idx = 32'd0;
end
end
end
endmodule
| 6.607799 |
module dff_s (
din,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
reg [SIZE-1:0] q;
`ifdef NO_SCAN
always @(posedge clk) q[SIZE-1:0] <= din[SIZE-1:0];
`else
always @(posedge clk) q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0];
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 7.138281 |
module dff_ns (
din,
clk,
q
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk
output [SIZE-1:0] q; // output
reg [SIZE-1:0] q;
always @(posedge clk) q[SIZE-1:0] <= din[SIZE-1:0];
endmodule
| 6.540346 |
module dffe_s (
din,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// en se out
//------------------
// x 1 sin ; scan dominates
// 1 0 din
// 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk) q[SIZE-1:0] <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
`else
always @(posedge clk) q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 6.980273 |
module dffre_s (
din,
rst,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 1 x x 0 ; reset dominates
// 0 x 1 sin ; scan dominates
// 0 1 0 din
// 0 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk) q[SIZE-1:0] <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]));
`else
always @(posedge clk)
// q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]));
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 7.001438 |
module dffrle_s (
din,
rst_l,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst_l; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 0 x x 0 ; reset dominates
// 1 x 1 sin ; scan dominates
// 1 1 0 din
// 1 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk)
q[SIZE-1:0] <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}});
`else
always @(posedge clk)
// q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 6.660956 |
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0;
input sel1;
input sel2;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
`endif
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
// priority encoding takes care of mutex'ing selects.
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
case ({sel2,sel1,sel0})
3'b001 : dout = in0 ;
3'b010 : dout = in1 ;
3'b100 : dout = in2 ;
3'b000 : dout = {SIZE{1'bx}} ;
3'b011 : dout = {SIZE{1'bx}} ;
3'b101 : dout = {SIZE{1'bx}} ;
3'b110 : dout = {SIZE{1'bx}} ;
3'b111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}};
// two state vs four state modelling will be added.
endcase
endmodule
| 6.938207 |
module sink (
in
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] in;
// Alexey
// `ifdef PITON_PROTO
// As of version 8.2 XST does not remove this module without the
// following additional dead code
wire a;
assign a = |in;
// `endif
endmodule
| 6.752622 |
module dffsl_async_ns (
din,
clk,
set_l,
q
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
input set_l; // set
output [SIZE-1:0] q; // output
reg [SIZE-1:0] q;
// synopsys async_set_reset "set_l"
always @(posedge clk or negedge set_l)
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
endmodule
| 6.557894 |
module dff_s (
din,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
input err_en; // error enable
reg [SIZE-1:0] q;
`ifdef NO_SCAN
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= err_en ? ~din[SIZE-1:0] : din[SIZE-1:0];
end else begin
q[SIZE-1:0] <= din[SIZE-1:0];
end
`else
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0];
end else begin
q[SIZE-1:0] <= err_en? ~((se) ? si[SIZE-1:0] : din[SIZE-1:0]) : ((se) ? si[SIZE-1:0] : din[SIZE-1:0]) ;
end
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 7.138281 |
module dff_ns (
din,
clk,
q,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk
output [SIZE-1:0] q; // output
input err_en; // error enable
reg [SIZE-1:0] q;
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= din[SIZE-1:0];
end else begin
q[SIZE-1:0] <= err_en ? ~din[SIZE-1:0] : din[SIZE-1:0];
end
endmodule
| 6.540346 |
module dffe_s (
din,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
input err_en; // error enable
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// en se out
//------------------
// x 1 sin ; scan dominates
// 1 0 din
// 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= (en) ? din[SIZE-1:0] : q[SIZE-1:0];
end else begin
q[SIZE-1:0] <= err_en? ~((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
end
`else
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
end else begin
q[SIZE-1:0] <= err_en? ~((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
end
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 6.980273 |
module dffre_s (
din,
rst,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
input err_en; // error enable
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 1 x x 0 ; reset dominates
// 0 x 1 sin ; scan dominates
// 0 1 0 din
// 0 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
end else begin
q[SIZE-1:0] <= err_en? ~(rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]));
end
`else
always @(posedge clk)
if (NO_ERR) begin
//q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
end else begin
q[SIZE-1:0] <= err_en? ~(se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]))) : (se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]))) ;
end
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 7.001438 |
module dffrle_s (
din,
rst_l,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst_l; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-output
input err_en; // error enable
reg [SIZE-1:0] q;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 0 x x 0 ; reset dominates
// 1 x 1 sin ; scan dominates
// 1 1 0 din
// 1 0 0 q
//
`ifdef NO_SCAN
always @(posedge clk)
if (NO_ERR) begin
q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}};
end else begin
q[SIZE-1:0] <= err_en? ~(rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}});
end
`else
always @(posedge clk)
if (NO_ERR) begin
//q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
end else begin
// q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
q[SIZE-1:0] <= err_en? ~(se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}})) : (se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}})) ;
end
assign so[SIZE-1:0] = q[SIZE-1:0];
`endif
endmodule
| 6.660956 |
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0;
input sel1;
input sel2;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
`endif
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
// priority encoding takes care of mutex'ing selects.
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
case ({sel2,sel1,sel0})
3'b001 : dout = in0 ;
3'b010 : dout = in1 ;
3'b100 : dout = in2 ;
3'b000 : dout = {SIZE{1'bx}} ;
3'b011 : dout = {SIZE{1'bx}} ;
3'b101 : dout = {SIZE{1'bx}} ;
3'b110 : dout = {SIZE{1'bx}} ;
3'b111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}};
// two state vs four state modelling will be added.
endcase
endmodule
| 6.938207 |
module sink (
in
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] in;
`ifdef FPGA_SYN
// As of version 8.2 XST does not remove this module without the
// following additional dead code
wire a;
assign a = |in;
`endif
endmodule
| 6.752622 |
module dffsl_async_ns (
din,
clk,
set_l,
q,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
input set_l; // set
output [SIZE-1:0] q; // output
input err_en; // error enable
reg [SIZE-1:0] q;
// synopsys async_set_reset "set_l"
always @(posedge clk or negedge set_l)
if (NO_ERR) begin
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
end else begin
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | (err_en?~din[SIZE-1:0] : din[SIZE-1:0] ));
end
endmodule
| 6.557894 |
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk5 ($one_cold ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
in0 or in1 or in2 or in3 or in4)
case ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
5'b11110 : dout = in0 ;
5'b11101 : dout = in1 ;
5'b11011 : dout = in2 ;
5'b10111 : dout = in3 ;
5'b01111 : dout = in4 ;
5'b11111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule
| 6.521486 |
module dp_mux8ds (dout, in0, in1, in2, in3,
in4, in5, in6, in7,
sel0_l, sel1_l, sel2_l, sel3_l,
sel4_l, sel5_l, sel6_l, sel7_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input [SIZE-1:0] in5;
input [SIZE-1:0] in6;
input [SIZE-1:0] in7;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
input sel5_l;
input sel6_l;
input sel7_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk8 ($one_cold ({sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
sel4_l or sel5_l or sel6_l or sel7_l or in4 or in5 or in6 or in7)
case ({sel7_l,sel6_l,sel5_l,sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
8'b11111110 : dout = in0 ;
8'b11111101 : dout = in1 ;
8'b11111011 : dout = in2 ;
8'b11110111 : dout = in3 ;
8'b11101111 : dout = in4 ;
8'b11011111 : dout = in5 ;
8'b10111111 : dout = in6 ;
8'b01111111 : dout = in7 ;
8'b11111111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule
| 6.611255 |
module dp_mux3ds (dout, in0, in1, in2,
sel0_l, sel1_l, sel2_l);
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0_l;
input sel1_l;
input sel2_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk3 ($one_cold ({sel2_l,sel1_l,sel0_l}));
`endif
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
case ({sel2_l,sel1_l,sel0_l})
3'b110 : dout = in0 ;
3'b101 : dout = in1 ;
3'b011 : dout = in2 ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule
| 6.6565 |
module swselect (
input wire adesE, //ѾijM
input [31:0] addressE,
input [7:0] alucontrolE,
input [3:0] memwriteE,
output reg [3:0] memwrite2E
);
always @(*) begin
if (adesE) memwrite2E <= 4'b0000;
else begin
case (alucontrolE)
`EXE_SB_OP: begin
case (addressE[1:0])
// 2'b00: memwrite2E <= 4'b1000;
// 2'b01: memwrite2E <= 4'b0100;
// 2'b10: memwrite2E <= 4'b0010;
// 2'b11: memwrite2E <= 4'b0001;
2'b11: memwrite2E <= 4'b1000;
2'b10: memwrite2E <= 4'b0100;
2'b01: memwrite2E <= 4'b0010;
2'b00: memwrite2E <= 4'b0001;
default: memwrite2E <= 4'b0000;
endcase
end
`EXE_SH_OP: begin
case (addressE[1:0])
2'b00: memwrite2E <= 4'b0011;
2'b10: memwrite2E <= 4'b1100;
default: memwrite2E <= 4'b0000;
endcase
end
`EXE_SW_OP: memwrite2E <= 4'b1111;
default: memwrite2E <= 4'b0000;
endcase
end
end
endmodule
| 6.810139 |
module SW_Set (
CLK,
PREV,
NEXT,
SW
);
input CLK;
input [2:0] PREV;
input [2:0] NEXT;
output reg [2:0] SW = 0;
integer sw_delay = 0;
always @(negedge CLK) begin
if (sw_delay == 0) begin
if (PREV) begin
sw_delay <= 500000;
SW <= SW - PREV;
end else if (NEXT) begin
sw_delay <= 500000;
SW <= SW + NEXT;
end
end else begin
sw_delay <= sw_delay - 1;
end
end
endmodule
| 6.674243 |
module SW_23bit (
in_0,
in_1,
se,
out
);
parameter DATA_WIDTH = 23;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input se;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
wire se;
reg [DATA_WIDTH - 1:0] out;
initial begin
assign out = (se & in_1) | ((~se) & in_0);
end
endmodule
| 6.625967 |
module SW_24 (
in_0,
in_1,
sel,
out
);
parameter DATA_WIDTH = 24;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input sel;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
reg [DATA_WIDTH - 1:0] out;
always @*
case (sel)
0: out = in_0;
1: out = in_1;
endcase
endmodule
| 7.830606 |
module SW_8bit (
in_0,
in_1,
se,
out
);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input se;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
wire se;
reg [DATA_WIDTH - 1:0] out;
initial begin
assign out = (se & in_1) | ((~se) & in_0);
end
endmodule
| 6.801097 |
module sw_alloc_first_arbiter #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PORT_SEL_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH),
parameter TOTAL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM,
parameter PORT_SEL_ARRAY_WIDTH = VC_NUM_PER_PORT * PORT_SEL_BCD_WIDTH,
parameter PORT_CAND_ARRAY_WIDTH = PORT_SEL_WIDTH * PORT_NUM,
parameter ALL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM
) (
input [PORT_SEL_ARRAY_WIDTH-1 : 0] port_selects,
input [VC_NUM_PER_PORT-1 : 0] in_vc_requests,
input [PORT_SEL_WIDTH-1 : 0] port_granted,
output [VC_NUM_PER_PORT-1 : 0] candidate_in_vc,
output [ PORT_SEL_WIDTH-1 : 0] candidate_port,
output [VC_NUM_PER_PORT-1 : 0] in_vc_granted,
output any_vc_granted,
input clk,
input reset
);
`LOG2
localparam PORT_SEL_HOT_ARRAY_WIDTH = VC_NUM_PER_PORT * PORT_SEL_WIDTH;
wire [PORT_SEL_HOT_ARRAY_WIDTH-1 : 0] port_sel_hot_array;
genvar i;
generate
for (i = 0; i < VC_NUM_PER_PORT; i = i + 1'b1) begin : bcd_to_hot_loop
bcd_to_one_hot #(
.BCD_WIDTH(PORT_SEL_BCD_WIDTH),
.ONE_HOT_WIDTH(PORT_SEL_WIDTH)
) the_bcd_to_one_hot (
.bcd_code(port_selects[(i+1)*PORT_SEL_BCD_WIDTH-1 : i*PORT_SEL_BCD_WIDTH]),
.one_hot_code(port_sel_hot_array[(i+1)*PORT_SEL_WIDTH-1 : i*PORT_SEL_WIDTH])
);
end //for i
endgenerate
assign any_vc_granted = |port_granted;
assign in_vc_granted = candidate_in_vc & {VC_NUM_PER_PORT{any_vc_granted}};
one_hot_arbiter #(
.ARBITER_WIDTH(VC_NUM_PER_PORT)
) the_sw_alloc_first_arbiter (
.clk(clk),
.reset(reset),
.request(in_vc_requests),
.grant(candidate_in_vc),
.any_grant()
);
one_hot_mux #(
.IN_WIDTH (PORT_SEL_HOT_ARRAY_WIDTH),
.SEL_WIDTH(VC_NUM_PER_PORT)
) port_sel_mux (
.mux_in(port_sel_hot_array),
.mux_out(candidate_port),
.sel(candidate_in_vc)
);
endmodule
| 8.693202 |
module sw_alloc_second_arbiter #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter ARBITER_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_REQ_WIDTH = PORT_NUM * ARBITER_WIDTH
) (
input [PORT_REQ_WIDTH-1 : 0] port_requests,
output [PORT_REQ_WIDTH-1 : 0] port_granted,
output [ PORT_NUM-1 : 0] any_grants,
input clk,
input reset
);
wire [ARBITER_WIDTH -1 : 0] request[PORT_NUM-1 : 0];
wire [ARBITER_WIDTH -1 : 0] grant [PORT_NUM-1 : 0];
genvar i, j;
generate
for (i = 0; i < PORT_NUM; i = i + 1) begin : arbiter_loop
one_hot_arbiter #(
.ARBITER_WIDTH(ARBITER_WIDTH)
) round_robin_arbiter (
.clk(clk),
.reset(reset),
.request(request[i]),
.grant(grant[i]),
.any_grant(any_grants[i])
);
for (j = 0; j < PORT_NUM; j = j + 1) begin : assignment_loop
if (i < j) begin : jj
assign request[i][j-1] = port_requests[(j*ARBITER_WIDTH)+i];
assign port_granted[(j*ARBITER_WIDTH)+i] = grant[i][j-1];
end else if (i > j) begin : hh
assign request[i][j] = port_requests[(j*ARBITER_WIDTH)+i-1];
assign port_granted[(j*ARBITER_WIDTH)+i-1] = grant[i][j];
end
//if(i==j) wires are left disconnected
end
end //for
endgenerate
endmodule
| 7.437006 |
module SW_Clk_Divide (
clk,
clk_div
);
input clk;
output reg clk_div;
integer count = 0;
always @(posedge clk) begin
if (count == 499999) //to generate 100Hz Signal ie T = 0.01s
count <= 1'b0;
else count <= count + 1'b1;
end
always @(posedge clk) begin
if (count == 499999) clk_div <= ~clk_div;
else clk_div <= clk_div;
end
endmodule
| 6.920851 |
module sw_debounce (
clk,
rst_n,
sw1_n,
sw2_n,
sw3_n,
led_d1,
led_d2,
led_d3
);
input clk; //ʱźţ50MHz
input rst_n; //λźţЧ
input sw1_n, sw2_n, sw3_n; //ͱʾ
output led_d1, led_d2, led_d3; //ܣֱɰ
//---------------------------------------------------------------------------
reg [2:0] key_rst;
always @(posedge clk or negedge rst_n)
if (!rst_n) key_rst <= 3'b111;
else key_rst <= {sw3_n, sw2_n, sw1_n};
reg [2:0] key_rst_r; //ÿʱڵؽlow_swź浽low_sw_r
always @(posedge clk or negedge rst_n)
if (!rst_n) key_rst_r <= 3'b111;
else key_rst_r <= key_rst;
//Ĵkey_rst1Ϊ0ʱled_anֵΪߣάһʱ
wire [ 2:0] key_an = key_rst_r & (~key_rst);
//---------------------------------------------------------------------------
reg [19:0] cnt; //Ĵ
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 20'd0; //첽λ
else if (key_an) cnt <= 20'd0;
else cnt <= cnt + 1'b1;
reg [2:0] low_sw;
always @(posedge clk or negedge rst_n)
if (!rst_n) low_sw <= 3'b111;
else if (cnt == 20'hfffff) //20msֵ浽Ĵlow_sw cnt == 20'hfffff
low_sw <= {sw3_n, sw2_n, sw1_n};
//---------------------------------------------------------------------------
reg [2:0] low_sw_r; //ÿʱڵؽlow_swź浽low_sw_r
always @(posedge clk or negedge rst_n)
if (!rst_n) low_sw_r <= 3'b111;
else low_sw_r <= low_sw;
//Ĵlow_sw1Ϊ0ʱled_ctrlֵΪߣάһʱ
wire [2:0] led_ctrl = low_sw_r[2:0] & (~low_sw[2:0]);
reg d1;
reg d2;
reg d3;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
d1 <= 1'b0;
d2 <= 1'b0;
d3 <= 1'b0;
end else begin //ijֵ仯ʱLEDת
if (led_ctrl[0]) d1 <= ~d1;
if (led_ctrl[1]) d2 <= ~d2;
if (led_ctrl[2]) d3 <= ~d3;
end
assign led_d3 = d1 ? 1'b1 : 1'b0; //LEDת
assign led_d2 = d2 ? 1'b1 : 1'b0;
assign led_d1 = d3 ? 1'b1 : 1'b0;
endmodule
| 6.798414 |
module sw_gen_affine (
clk,
rst,
i_query_length,
i_local,
query,
i_vld,
i_data,
o_vld,
m_result
);
localparam SCORE_WIDTH = 11, N_A = 2'b00, //nucleotide "A"
N_G = 2'b01, //nucleotide "G"
N_T = 2'b10, //nucleotide "T"
N_C = 2'b11, //nucleotide "C"
INS = 1, //insertion penalty
DEL = 1, //deletion penalty
TB_UP = 2'b00, //"UP" traceback pointer
TB_DIAG = 2'b01, //"DIAG" traceback pointer
TB_LEFT = 2'b10; //"LEFT" traceback pointer
parameter LOGLENGTH = 6; //log2(total number of comparison blocks instantiated)
//parameter LENGTH = 1 << LOGLENGTH; //total number of comparison blocks instantiated - query length must be less than this
parameter LENGTH = 48;
input wire rst;
input wire clk;
input wire [1:0] i_data;
input wire i_local; //=1 if local alignment, =0 if global alignment
input wire [LOGLENGTH-1:0] i_query_length; //this is the (length_of_the_actual_query_string - 1) (must be less than the max length value - 0=1 block, 1=2 blocks, etc)
input wire [(LENGTH*2-1):0] query; //this is the actual query sequence - query[1:0] goes into block0, query [3:2] goes into block1, etc.
output wire o_vld;
output wire [SCORE_WIDTH-1:0] m_result;
wire [2*(LENGTH-1)+1:0] data;
input wire i_vld; //master valid signal at start of chain
wire vld[LENGTH-1:0];
wire [SCORE_WIDTH-1:0] right_m[LENGTH-1:0]; //the 'match' matrix cell value array
wire [SCORE_WIDTH-1:0] right_i[LENGTH-1:0]; //the 'indel' matrix cell value array
wire [SCORE_WIDTH-1:0] high_score[LENGTH-1:0]; //the 'current highest score' array
wire [LENGTH-1:0] gap;
wire [LENGTH-1:0] reset;
assign o_vld = vld[i_query_length];
assign m_result = i_local ? high_score[i_query_length] : ((right_m[i_query_length] > right_i[i_query_length]) ? right_m[i_query_length] : right_i[i_query_length]);
//assign query={N_A,N_G,N_T,N_T};
genvar i;
generate
for (i = 0; i < LENGTH; i = i + 1) begin : pe_block
if (i == 0) //first processing element in auto-generated chain
begin: pe_block0
sw_pe_affine pe0 (
.clk(clk),
.i_rst(rst),
.o_rst(reset[i]),
.i_data(i_data[1:0]),
.i_preload(query[1:0]),
.i_left_m(11'b10000000000),
.i_left_i(11'b10000000000),
.i_vld(i_vld),
.i_local(i_local),
.i_high(11'b0),
.o_right_m(right_m[i]),
.o_right_i(right_i[i]),
.o_high(high_score[i]),
.o_vld(vld[i]),
.o_data(data[2*i+1:2*i]),
.start(1'b1)
);
end else //processing elements other than first one
begin : pe_block1
sw_pe_affine pe1 (
.clk(clk),
.i_rst(reset[i-1]),
.o_rst(reset[i]),
.i_data(data[2*(i-1)+1:(i-1)*2]),
.i_preload(query[i*2+1:i*2]),
.i_left_m(right_m[i-1]),
.i_left_i(right_i[i-1]),
.i_local(i_local),
.i_vld(vld[i-1]),
.i_high(high_score[i-1]),
.o_right_m(right_m[i]),
.o_right_i(right_i[i]),
.o_high(high_score[i]),
.o_vld(vld[i]),
.o_data(data[2*(i)+1:2*(i)]),
.start(1'b0)
);
end
end
endgenerate
endmodule
| 7.000366 |
module sw_gen_min (
input wire clk_min,
input wire reset,
output reg [3:0] min_low,
min_high
);
initial begin
min_low = 0;
min_high = 0;
end
always @(posedge clk_min or posedge reset) begin
if (reset) begin
min_low = 0;
min_high = 0;
end else if (min_low == 9) begin
min_low = 0;
if (min_high == 9) begin
min_high = 0;
end else min_high = min_high + 1;
end else min_low = min_low + 1;
end
endmodule
| 7.000059 |
module sw_gen_psec (
input wire clk_psec,
input wire reset,
output reg clk_sec,
output reg [3:0] psec_low,
psec_high
);
initial begin
psec_low = 0;
psec_high = 0;
end
always @(posedge clk_psec or posedge reset) begin
if (reset) begin
psec_low = 0;
psec_high = 0;
end else if (psec_low == 9) begin
psec_low = 0;
clk_sec = 0;
if (psec_high == 9) begin
psec_high = 0; // grow second
clk_sec = 1;
end else psec_high = psec_high + 1;
end else psec_low = psec_low + 1;
end
endmodule
| 7.01611 |
module sw_gen_sec (
input wire clk_sec,
input wire reset,
output reg clk_min,
output reg [3:0] sec_low,
sec_high
);
initial begin
sec_low = 0;
sec_high = 0;
end
always @(posedge clk_sec or posedge reset) begin
if (reset) begin
sec_low = 0;
sec_high = 0;
end else if (sec_low == 9) begin
sec_low = 0;
clk_min = 0;
if (sec_high == 5) begin
sec_high = 0; // grow min
clk_min = 1;
end else sec_high = sec_high + 1;
end else sec_low = sec_low + 1;
end
endmodule
| 7.502251 |
module sw_iterB_i (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
sw_iterB_i_ram sw_iterB_i_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 6.824429 |
module to deal with LEDs and switches
* Copyright (C) 2010 Zeus Gomez Marmolejo <zeus@aluzina.org>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module sw_leds (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input wb_adr_i,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// GPIO inputs/outputs
//output reg [13:0] leds_,
output reg [7:0] leds_,
input [7:0] sw_,
input pb_,
input tick,
output reg nmi_pb
);
// Registers and nets
wire op;
reg tick_old;
reg tick1;
reg nmi_pb_pressed;
reg [2:0] nmi_cnt;
// Continuous assignments
assign op = wb_cyc_i & wb_stb_i;
assign wb_ack_o = op;
assign wb_dat_o = wb_adr_i ? { 8'b00, leds_ }
: { 8'h00, sw_ };
// Behaviour
always @(posedge wb_clk_i)
leds_ <= wb_rst_i ? 8'h0 // 14'h0
//: ((op & wb_we_i & wb_adr_i) ? wb_dat_i[13:0] : leds_);
: ((op & wb_we_i & wb_adr_i) ? wb_dat_i[7:0] : leds_);
always @(posedge wb_clk_i)
begin
tick_old <= tick;
tick1 <= tick & ~tick_old;
end
always @(posedge wb_clk_i)
nmi_pb_pressed <= !pb_;
always @(posedge wb_clk_i)
begin
if (wb_rst_i)
begin
nmi_pb <= 1'b0;
nmi_cnt <= 3'b111;
end
else
begin
if (nmi_cnt == 3'b111)
begin
if (nmi_pb_pressed != nmi_pb)
begin
nmi_pb <= nmi_pb_pressed;
nmi_cnt <= nmi_cnt + 3'b001; // nmi_cnt <= 3'b000;
end
end
else if (tick1)
nmi_cnt <= nmi_cnt + 3'b001;
end
end
endmodule
| 8.872476 |
module sw_maxscore_readRefPacked_0_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 24;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.721326 |
module sw_maxscore_readRefPacked_0 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd24;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
sw_maxscore_readRefPacked_0_ram sw_maxscore_readRefPacked_0_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.721326 |
module sw_mem_sel (
input [31:0] switch_cs,
input [15:0] sw,
input [31:0] data,
output [31:0] data_sel
);
assign data_sel = (switch_cs) ? {16'b0, sw[15:0]} : data;
endmodule
| 7.04254 |
module sw_mux (
adress,
in,
out0,
out1,
out2,
out3,
out4
);
input [3:0] adress;
input [3:0] in;
output [3:0] out0, out1, out2, out3, out4;
wire [3:0] in;
reg [3:0] out0, out1, out2, out3, out4;
always @(adress or in) begin
case (adress)
4'b0001: out1 <= in;
4'b0010: out2 <= in;
4'b0100: out3 <= in;
4'b1000: out4 <= in;
default: out0 <= in;
endcase
end
endmodule
| 8.001779 |
module.
Info: monemi@fkegraduate.utm.my
************************************************************************/
module sw_out#(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PYLD_WIDTH = 32,
parameter FLIT_TYPE_WIDTH = 2,
parameter SW_OUTPUT_REGISTERED = 0, // 1: registered , 0 not registered
parameter PORT_SEL_WIDTH = PORT_NUM-1,//assum that no port whants to send a packet to itself!
parameter VC_ID_WIDTH = VC_NUM_PER_PORT,
parameter FLIT_WIDTH = PYLD_WIDTH+ FLIT_TYPE_WIDTH+VC_ID_WIDTH
)
(
input in_wr_en,
input [FLIT_WIDTH-1 :0] flit_in,
output reg out_wr_en,
output reg [FLIT_WIDTH-1 :0] flit_out,
input clk,
input reset
);
generate
if (SW_OUTPUT_REGISTERED) begin
always @(posedge clk or posedge reset)begin
if(reset)begin
out_wr_en <=1'b0;
flit_out <={FLIT_WIDTH{1'b0}};
end else begin
out_wr_en <= in_wr_en;
flit_out <= flit_in;
end
end//always
end else begin
always @(*)begin
out_wr_en = in_wr_en;
flit_out = flit_in;
end//always
end
endgenerate
endmodule
| 8.401637 |
module sw_p (
input clk,
input rst,
input [3:0] addra,
output reg [31:0] douta,
input [7:0] sw
);
reg [31:0] sw_p_r[0:15];
always @(posedge clk) begin
douta <= sw_p_r[addra];
if (rst) begin
sw_p_r[0] <= 0;
sw_p_r[1] <= 0;
sw_p_r[2] <= 0;
sw_p_r[3] <= 0;
sw_p_r[4] <= 0;
sw_p_r[5] <= 0;
sw_p_r[6] <= 0;
sw_p_r[7] <= 0;
sw_p_r[8] <= 0;
sw_p_r[9] <= 0;
sw_p_r[10] <= 0;
sw_p_r[11] <= 0;
sw_p_r[12] <= 0;
sw_p_r[13] <= 0;
sw_p_r[14] <= 0;
sw_p_r[15] <= 0;
end else begin
sw_p_r[0] <= sw;
end
end
endmodule
| 7.152432 |
module sw_pe_array_proc_element_query_mem_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd2048;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
nlb_gram_ssp #(
.BUS_SIZE_ADDR(11),
.BUS_SIZE_DATA(4),
.GRAM_STYLE(`GRAM_AUTO)
) inst_nlb_gram_ssp (
.clk (clk),
.we (we0),
.addr(address0),
.din (d0),
.dout(q0)
);
endmodule
| 7.184438 |
module sw_pe_array_receive_match_matchBuf (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd5;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
nlb_gram_ssp #(
.BUS_SIZE_ADDR(3),
.BUS_SIZE_DATA(32),
.GRAM_STYLE(`GRAM_AUTO)
) inst_nlb_gram_ssp (
.clk (clk),
.we (we0),
.addr(address0),
.din (d0),
.dout(q0)
);
endmodule
| 6.692945 |
module SW_PE_clk (
input clk,
input reset,
input [2:0] seq1,
input [2:0] seq2,
input [31:0] diag_score,
input [31:0] left_score,
input [31:0] top_score,
output reg [31:0] score
);
parameter match_score = 2;
parameter mismatch_score = 1;
parameter gap_penalty = 1;
wire [31:0] score1, score2, score3, score_wire;
wire [31:0] stemp1, stemp2, stemp3;
assign stemp1 = ((seq1==seq2)?(diag_score+match_score):(diag_score-mismatch_score))&32'b10000000000000000000000000000000;
assign stemp2 = (left_score - gap_penalty) & 32'b10000000000000000000000000000000;
assign stemp3 = (top_score - gap_penalty) & 32'b10000000000000000000000000000000;
assign score1 = (stemp1==8'd0)?((seq1==seq2)?(diag_score+match_score):(diag_score-mismatch_score)):32'd0;
assign score2 = (stemp2 == 8'd0) ? (left_score - gap_penalty) : 32'd0;
assign score3 = (stemp3 == 8'd0) ? (top_score - gap_penalty) : 32'd0;
assign score_wire = ((score1>score2)?((score1>score3)?score1:score3):((score2>score3)?score2:score3));
always @(posedge clk or posedge reset) begin
if (reset) begin
score <= 32'd0;
end else score <= score_wire;
end
endmodule
| 7.174761 |
module sw_pulse (
clk,
rst_n,
sw_en,
sw_out
);
input clk;
input rst_n;
input sw_en;
output sw_out;
reg sw_signal;
reg [19:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 20'b0;
sw_signal <= 1'b1;
end else if (!sw_en) begin
count <= 20'b0;
sw_signal <= 1'b1;
end else if (sw_en) begin
if (!count[19]) begin
count <= count + 1'b1;
sw_signal <= 1'b0;
end else begin
count <= count;
sw_signal <= 1'b1;
end
end else begin
count <= 20'b0;
sw_signal <= 1'b1;
end
end
assign sw_out = sw_signal;
endmodule
| 6.959327 |
module SW_Refresh_Clk (
input Clk,
output reg Clk_Div
);
integer count = 0;
always @(posedge Clk) begin
if (count == 4999) //to generate 10KHz for refresh counter
count <= 1'b0;
else count <= count + 1'b1;
end
always @(posedge Clk) begin
if (count == 4999) Clk_Div <= ~Clk_Div;
else Clk_Div <= Clk_Div;
end
endmodule
| 6.76437 |
modules //
// //
//============================================================================//
// _________ //
// read | | write //
// SW <-----| Reg |<----- Fabric //
// |_________| //
// //
//============================================================================//
bus wb (
//============
// wb inputs
//============
output clk_i,
output rst_i,
output cyc_i,
output stb_i,
output we_i,
output [3:0] sel_i,
output [31:0] adr_i,
output [31:0] dat_i,
//=============
// wb outputs
//=============
input [31:0] dat_o,
input ack_o,
input err_o
);
module sw_reg_r #(
//=============
// parameters
//=============
parameter C_BASEADDR = 32'h00000000,
parameter C_HIGHADDR = 32'h0000000F,
parameter C_WB_DATA_WIDTH = 32,
parameter C_WB_ADDR_WIDTH = 1,
parameter C_BYTE_EN_WIDTH = 4
) (
//===============
// fabric ports
//===============
input fabric_clk,
input fabric_data_in,
slave wb,
);
wire a_match = wb.adr_i >= C_BASEADDR && wb.adr_i <= C_HIGHADDR;
reg [31:0] fabric_data_in_reg;
//==================
// register buffer
//==================
reg [31:0] reg_buffer;
//=============
// wb control
//=============
always @(posedge wb.clk_i)
begin
wb.ack_o <= 1'b0;
if (wb.rst_i)
begin
//
end
else
begin
if (wb.stb_i && wb.cyc_i)
begin
wb.ack_o <= 1'b1;
end
end
end
//==========
// wb read
//==========
always @(*)
begin
if (wb.rst_i)
begin
register_request <= 1'b0;
end
if(~wb.we_i)
begin
case (wb.adr_i[6:2])
// Check if this works, it should depend on the spacings between devices on the bus,
// otherwise just check if the address is in range and dont worry about the case statement
// blah blah
5'h0:
begin
wb.dat_o <= reg_buffer;
end
default:
begin
wb.dat_o <= 32'b0;
end
endcase
end
if (register_readyRR)
begin
register_request <= 1'b0;
end
if (register_readyRR && register_request)
begin
reg_buffer <= fabric_data_in_reg;
end
if (!register_readyRR)
begin
/* always request the buffer */
register_request <= 1'b1;
end
end
//===============
// fabric write
//===============
/* Handshake signal from wb to application indicating new data should be latched */
reg register_request;
reg register_requestR;
reg register_requestRR;
/* Handshake signal from application to wb indicating data has been latched */
reg register_ready;
reg register_readyR;
reg register_readyRR;
always @(posedge fabric_clk)
begin
register_requestR <= register_request;
register_requestRR <= register_requestR;
if (register_requestRR)
begin
register_ready <= 1'b1;
end
if (!register_requestRR)
begin
register_ready <= 1'b0;
end
if (register_requestRR && !register_ready)
begin
register_ready <= 1'b1;
fabric_data_in_reg <= fabric_data_in;
end
end
endmodule
| 8.225128 |
module, and provides and interface //
// to test the module from Python (MyHDL) //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
module sw_reg_r_tb;
//=====================
// local wires & regs
//=====================
reg wb_clk_i;
reg wb_rst_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
reg [3:0] wb_sel_i;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
wire wb_ack_o;
wire wb_err_o;
reg fabric_clk;
wire fabric_data_in;
//=====================================
// instance, "(d)esign (u)nder (t)est"
//=====================================
sw_reg_r #(
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'h0000FFFF)
) dut (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_we_i (wb_we_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.fabric_clk (fabric_clk),
.fabric_data_in (fabric_data_in)
);
//==============
// MyHDL hooks
//==============
`ifdef MYHDL
// define what myhdl takes over
// only if we're running myhdl
initial begin
$from_myhdl(fabric_clk, fabric_data_in, wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_sel_i, wb_adr_i, wb_dat_i);
$to_myhdl(wb_dat_o,wb_ack_o,wb_err_o);
end
`else
//==============
// Initialize
//==============
initial
begin
$dumpvars;
wb_clk_i = 0;
wb_sel_i = 4'hE;
wb_stb_i = 1;
wb_cyc_i = 1;
wb_we_i = 1;
wb_adr_i = 32'h00000000;
wb_dat_i = 32'hEEEEEEEE;
#5
wb_stb_i = 0;
wb_cyc_i = 0;
#5
wb_adr_i = 32'h00000000;
wb_stb_i = 1;
wb_cyc_i = 1;
wb_we_i = 0;
#20 $finish;
end
//=====================
// Simulate the Clock
//=====================
always #1
wb_clk_i = ~wb_clk_i;
`endif
endmodule
| 9.300519 |
module, and provides and interface //
// to test the module from Python (MyHDL) //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
module sw_reg_wr_tb;
//=====================
// local wires & regs
//=====================
reg wb_clk_i;
reg wb_rst_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
reg [3:0] wb_sel_i;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
wire wb_ack_o;
wire wb_err_o;
reg fabric_clk;
wire fabric_data_out;
//=====================================
// instance, "(d)esign (u)nder (t)est"
//=====================================
sw_reg_wr #(
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'h0000FFFF)
) dut (
.wb_rst_i (wb_rst_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.fabric_clk (fabric_clk),
.fabric_data_out (fabric_data_out)
);
//==============
// MyHDL hooks
//==============
`ifdef MYHDL
// define what myhdl takes over
// only if we're running myhdl
initial begin
$from_myhdl(fabric_clk, wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_sel_i, wb_adr_i, wb_dat_i);
$to_myhdl(fabric_data_in, wb_dat_o,wb_ack_o,wb_err_o);
end
`else
//==============
// Initialize
//==============
initial
begin
$dumpvars;
wb_clk_i = 0;
wb_sel_i = 4'hE;
wb_stb_i = 1;
wb_cyc_i = 1;
wb_we_i = 1;
wb_adr_i = 32'h00000000;
wb_dat_i = 32'hEEEEEEEE;
#5
wb_stb_i = 0;
wb_cyc_i = 0;
#5
wb_adr_i = 32'h00000000;
wb_stb_i = 1;
wb_cyc_i = 1;
wb_we_i = 0;
#20 $finish;
end
//=====================
// Simulate the Clock
//=====================
always #1
wb_clk_i = ~wb_clk_i;
`endif
endmodule
| 9.300519 |
module sw_reset #(
parameter WIDTH = 32,
parameter LOG2_RESET_CYCLES = 8
) (
input clk,
input resetn,
// Slave port
input slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slave_readdata,
output slave_waitrequest,
output reg sw_reset_n_out
);
reg sw_reset_n_out_r;
reg sw_reset_n_out_r2;
reg [LOG2_RESET_CYCLES:0] reset_count;
initial // Power up condition
reset_count <= {LOG2_RESET_CYCLES + 1{1'b0}};
always @(posedge clk or negedge resetn)
if (!resetn) reset_count <= {LOG2_RESET_CYCLES + 1{1'b0}};
else if (slave_write) reset_count <= {LOG2_RESET_CYCLES + 1{1'b0}};
else if (!reset_count[LOG2_RESET_CYCLES]) reset_count <= reset_count + 2'b01;
always @(posedge clk) sw_reset_n_out = sw_reset_n_out_r;
// Allow additional stages to get to global clock buffers.
always @(posedge clk) sw_reset_n_out_r2 = reset_count[LOG2_RESET_CYCLES];
always @(posedge clk) sw_reset_n_out_r = sw_reset_n_out_r2;
assign slave_waitrequest = !reset_count[LOG2_RESET_CYCLES];
assign slave_readdata = sw_reset_n_out;
endmodule
| 8.079645 |
module sw_sep_alloc #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PORT_SEL_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH),
parameter TOTAL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM,
parameter PORT_SEL_ARRAY_WIDTH = TOTAL_VC_NUM * PORT_SEL_BCD_WIDTH,
parameter PORT_CAND_ARRAY_WIDTH = PORT_SEL_WIDTH * PORT_NUM,
parameter ALL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM
) (
input [ PORT_SEL_ARRAY_WIDTH-1 : 0] port_selects_array,
input [ ALL_VC_NUM-1 : 0] in_vc_requests_array,
output [ ALL_VC_NUM-1 : 0] candidate_in_vc_array,
output [PORT_CAND_ARRAY_WIDTH-1 : 0] candidate_port_array,
output [ ALL_VC_NUM-1 : 0] in_vc_granted_array,
output [ PORT_NUM-1 : 0] any_vc_granted_array,
output reg [PORT_CAND_ARRAY_WIDTH-1 : 0] crossbar_granted_port_array,
output [PORT_CAND_ARRAY_WIDTH-1 : 0] isw_granted_port_array,
output reg [ PORT_NUM-1 : 0] out_port_wr_en_array,
input clk,
input reset
);
`LOG2
localparam FIRST_ARBITER_PORT_SEL_WIDTH = VC_NUM_PER_PORT * PORT_SEL_BCD_WIDTH;
wire [ PORT_NUM-1 : 0] any_grants;
wire [PORT_CAND_ARRAY_WIDTH-1 : 0] candidate_port_wire;
assign candidate_port_array = candidate_port_wire;
genvar i, j;
generate
for (i = 0; i < PORT_NUM; i = i + 1) begin : first_arbitter_loop
//first arbiters
sw_alloc_first_arbiter #(
.VC_NUM_PER_PORT(VC_NUM_PER_PORT),
.PORT_NUM (PORT_NUM)
) the_sw_alloc_first_arbiter (
.port_selects (port_selects_array [(i+1)*FIRST_ARBITER_PORT_SEL_WIDTH-1 :i*FIRST_ARBITER_PORT_SEL_WIDTH]),
.in_vc_requests(in_vc_requests_array[(i+1)*VC_NUM_PER_PORT-1 : i*VC_NUM_PER_PORT]),
.port_granted(isw_granted_port_array[(i+1)*PORT_SEL_WIDTH-1 : i*PORT_SEL_WIDTH]),
.candidate_in_vc(candidate_in_vc_array[(i+1)*VC_NUM_PER_PORT-1 : i*VC_NUM_PER_PORT]),
.candidate_port(candidate_port_wire[(i+1)*PORT_SEL_WIDTH-1 : i*PORT_SEL_WIDTH]),
.in_vc_granted(in_vc_granted_array[(i+1)*VC_NUM_PER_PORT-1 : i*VC_NUM_PER_PORT]),
.any_vc_granted(any_vc_granted_array[i]),
.clk(clk),
.reset(reset)
);
end //for
endgenerate
//second arbiters
sw_alloc_second_arbiter #(
.VC_NUM_PER_PORT(VC_NUM_PER_PORT),
.PORT_NUM (PORT_NUM)
) the_sw_alloc_second_arbiter (
.port_requests(candidate_port_wire),
.port_granted (isw_granted_port_array),
.any_grants (any_grants),
.clk (clk),
.reset (reset)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
crossbar_granted_port_array <= {PORT_CAND_ARRAY_WIDTH{1'b0}};
out_port_wr_en_array <= {PORT_NUM{1'b0}};
end else begin
crossbar_granted_port_array <= isw_granted_port_array;
out_port_wr_en_array <= any_grants;
end
end //always
endmodule
| 7.357073 |
module sw_top_tb;
parameter PERIOD = 10;
parameter CTSW_DWIDTH = 24;
wire clk_100m;
wire clk_25m;
wire locked;
clk_gen #(
.PERIOD (PERIOD),
.REST_VALUE(1'b0)
) clk_gen_100m (
.clk (clk_100m),
.rstn(locked)
);
reg [CTSW_DWIDTH-1:0] timer_data_l_i;
reg [CTSW_DWIDTH-1:0] timer_data_h_i;
wire timer_done_o;
timer #(
.CTSW_DWIDTH (24),
.C_PULS_DWIDTH(4)
) timer (
.clk(clk_100m),
//----- spi -----//
.timer_data_l_i(timer_data_l_i),
.timer_data_h_i(timer_data_h_i),
//--------------//
.timer_done_o(timer_done_o)
);
initial begin
wait (locked);
#200 begin
timer_data_l_i = {16'd1, 16'd300};
timer_data_h_i = {16'd1, 16'd0};
end
#200 begin
timer_data_l_i = {16'd0, 16'd300};
timer_data_h_i = {16'd0, 16'd0};
end
wait (timer_done_o);
#5000 $stop;
end
endmodule
| 6.894027 |
module SW_to_LEDR (
input [9:0] SW,
output [9:0] LEDR
);
assign LEDR = SW;
endmodule
| 6.830166 |
module sw_wrbck #(
parameter BARHIT = 2,
parameter BARMP = 6'bxxxxxx
) (
input clk,
input rst,
// TRN rx
input [63:0] trn_rd,
input [ 7:0] trn_rrem_n,
input trn_rsof_n,
input trn_reof_n,
input trn_rsrc_rdy_n,
input [ 6:0] trn_rbar_hit_n,
output reg [63:0] sw_ptr
);
`include "includes.v"
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;
localparam s2 = 8'b00000010;
localparam s3 = 8'b00000100;
localparam s4 = 8'b00001000;
localparam s5 = 8'b00010000;
localparam s6 = 8'b00100000;
localparam s7 = 8'b01000000;
localparam s8 = 8'b10000000;
//-------------------------------------------------------
// Local rcv sw_ptr_i
//-------------------------------------------------------
reg [ 7:0] tlp_rx_fsm;
reg [31:0] aux_dw;
reg [63:0] sw_ptr_i;
////////////////////////////////////////////////
// rcv sw_ptr_i
////////////////////////////////////////////////
always @(posedge clk) begin
if (rst) begin // rst
tlp_rx_fsm <= s0;
end else begin // not rst
sw_ptr <= sw_ptr_i;
case (tlp_rx_fsm)
s0: begin
if ((!trn_rsrc_rdy_n) && (!trn_rsof_n) && (!trn_rbar_hit_n[BARHIT])) begin
if (trn_rd[62:56] == `MEM_WR32_FMT_TYPE) begin
tlp_rx_fsm <= s1;
end else if (trn_rd[62:56] == `MEM_WR64_FMT_TYPE) begin
tlp_rx_fsm <= s3;
end
end
end
s1: begin
aux_dw <= trn_rd[31:0];
if (!trn_rsrc_rdy_n) begin
case (trn_rd[39:34])
BARMP: begin
tlp_rx_fsm <= s2;
end
default: begin //other addresses
tlp_rx_fsm <= s0;
end
endcase
end
end
s2: begin
sw_ptr_i[31:0] <= dw_endian_conv(aux_dw);
sw_ptr_i[63:32] <= dw_endian_conv(trn_rd[63:32]);
if (!trn_rsrc_rdy_n) begin
tlp_rx_fsm <= s0;
end
end
s3: begin
if (!trn_rsrc_rdy_n) begin
case (trn_rd[7:2])
BARMP: begin
tlp_rx_fsm <= s4;
end
default: begin //other addresses
tlp_rx_fsm <= s0;
end
endcase
end
end
s4: begin
sw_ptr_i[31:0] <= dw_endian_conv(trn_rd[63:32]);
sw_ptr_i[63:32] <= dw_endian_conv(trn_rd[31:0]);
if (!trn_rsrc_rdy_n) begin
tlp_rx_fsm <= s0;
end
end
default: begin //other TLPs
tlp_rx_fsm <= s0;
end
endcase
end // not rst
end //always
endmodule
| 8.216159 |
module sxrRISC621_addsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [13:0] dataa;
input [13:0] datab;
output cout;
output overflow;
output [13:0] result;
wire sub_wire0;
wire sub_wire1;
wire [13:0] sub_wire2;
wire cout = sub_wire0;
wire overflow = sub_wire1;
wire [13:0] result = sub_wire2[13:0];
lpm_add_sub LPM_ADD_SUB_component (
.add_sub(add_sub),
.dataa(dataa),
.datab(datab),
.cout(sub_wire0),
.overflow(sub_wire1),
.result(sub_wire2)
// synopsys translate_off
, .aclr(),
.cin(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_ADD_SUB_component.lpm_direction = "UNUSED", LPM_ADD_SUB_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_ADD_SUB_component.lpm_width = 14;
endmodule
| 7.169797 |
module sxrRISC621_addsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [13:0] dataa;
input [13:0] datab;
output cout;
output overflow;
output [13:0] result;
endmodule
| 7.169797 |
module sxrRISC621_cache (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [13:0] data;
input wren;
output [13:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [13:0] sub_wire0;
wire [13:0] q = sub_wire0[13:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 14,
altsyncram_component.width_byteena_a = 1;
endmodule
| 8.187166 |
module sxrRISC621_cache (
address,
clock,
data,
wren,
q
);
input [7:0] address;
input clock;
input [13:0] data;
input wren;
output [13:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 8.187166 |
module sxrRISC621_cam (
we_n,
rd_n,
din,
argin,
addrs,
dout,
mbits
);
//----------------------------------------------------------------------------
//-- Declare input and output port types
//----------------------------------------------------------------------------
input we_n, rd_n; // write and read enables
input [7:0] din, argin; // data input and argument input busses
input [1:0] addrs; // address input bus; points to 8 locations
output reg [7:0] dout; // data output
output reg [3:0] mbits; // mbits = match bits
//----------------------------------------------------------------------------
//-- Declare internal memory array
//----------------------------------------------------------------------------
reg [7:0] cam_mem[3:0]; //an array of 2x8 bit locations
//----------------------------------------------------------------------------
//-- The WRITE procedural block.
//-- This enables a new tag value to be written at a specific location,
//-- using a WE, data input and address input busses as with any
//-- other memory.
//-- In the context of a cache, this happens when a new block is
//-- uploaded in the cache.
//----------------------------------------------------------------------------
always @(we_n, din, addrs) begin
if (we_n == 0) cam_mem[addrs] = din;
end
//----------------------------------------------------------------------------
//-- The READ procedural block.
//-- This allows a value at a specific location to be read out,
//-- using a RD, data output and address input busses as with any
//-- other memory.
//-- In the context of a cache, this is not necessary. This functionality
//-- is provided here for reference and debugging purposes.
//----------------------------------------------------------------------------
always @(rd_n, addrs, cam_mem) begin
if (rd_n == 0) dout = cam_mem[addrs];
else dout = 8'bzzzzzzzz;
end
//----------------------------------------------------------------------------
//-- The MATCH procedural block.
//-- This implements the actual CAM function.
//-- An mbit is 1 if the argument value is equal to the content of the
//-- memory location associated with it.
//----------------------------------------------------------------------------
always @(argin, cam_mem) begin
mbits = 4'h0;
if (argin == cam_mem[0]) mbits[0] = 1'b1;
if (argin == cam_mem[1]) mbits[1] = 1'b1;
if (argin == cam_mem[2]) mbits[2] = 1'b1;
if (argin == cam_mem[3]) mbits[3] = 1'b1;
end
endmodule
| 8.187166 |
module sxrRISC621_div (
denom,
numer,
quotient,
remain
);
input [13:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [13:0] remain;
wire [13:0] sub_wire0;
wire [13:0] sub_wire1;
wire [13:0] quotient = sub_wire0[13:0];
wire [13:0] remain = sub_wire1[13:0];
lpm_divide LPM_DIVIDE_component (
.denom(denom),
.numer(numer),
.quotient(sub_wire0),
.remain(sub_wire1),
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
);
defparam LPM_DIVIDE_component.lpm_drepresentation = "SIGNED", LPM_DIVIDE_component.lpm_hint =
"LPM_REMAINDERPOSITIVE=FALSE", LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE", LPM_DIVIDE_component.lpm_widthd = 14,
LPM_DIVIDE_component.lpm_widthn = 14;
endmodule
| 6.784939 |
module sxrRISC621_div (
denom,
numer,
quotient,
remain
);
input [13:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [13:0] remain;
endmodule
| 6.784939 |
module sxrRISC621_vaddsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output cout;
output overflow;
output [6:0] result;
wire sub_wire0;
wire sub_wire1;
wire [6:0] sub_wire2;
wire cout = sub_wire0;
wire overflow = sub_wire1;
wire [6:0] result = sub_wire2[6:0];
lpm_add_sub LPM_ADD_SUB_component (
.add_sub(add_sub),
.dataa(dataa),
.datab(datab),
.cout(sub_wire0),
.overflow(sub_wire1),
.result(sub_wire2)
// synopsys translate_off
, .aclr(),
.cin(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_ADD_SUB_component.lpm_direction = "UNUSED", LPM_ADD_SUB_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_ADD_SUB_component.lpm_representation = "UNSIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_ADD_SUB_component.lpm_width = 7;
endmodule
| 7.25902 |
module sxrRISC621_vaddsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output cout;
output overflow;
output [6:0] result;
endmodule
| 7.25902 |
module SyncFIFO #(
parameter DataWidth = 64,
parameter Deepth = 16
) (
input Clk,
input Rst,
input [DataWidth - 1 : 0] WData,
input WInc,
output WFull,
output reg [DataWidth - 1 : 0] RData,
input RInc,
output REmpty
);
localparam DeepthBit = $clog2(Deepth);
reg [DeepthBit : 0] WritePoint;
reg [DeepthBit : 0] ReadPoint;
//empty or full
assign WFull = ((WritePoint[DeepthBit] != ReadPoint[DeepthBit]) && (WritePoint[DeepthBit - 1 : 0] == ReadPoint[DeepthBit - 1 : 0]));
assign REmpty = (WritePoint == ReadPoint);
//write logic
always @(posedge Clk) begin
if (!Rst) begin
WritePoint <= 'h0;
end else begin
if (WInc && ~WFull) begin
WritePoint <= WritePoint + 1;
end
end
end
//read logic
always @(posedge Clk) begin
if (!Rst) begin
ReadPoint <= 'h0;
end else begin
if (RInc && ~REmpty) begin
ReadPoint <= ReadPoint + 1;
end
end
end
DualPortRam #(
.DataWidth(DataWidth),
.Deepth(Deepth)
) u_DualPortRam (
.WClk (Clk),
.WData(WData),
.WAddr(WritePoint[DeepthBit-1 : 0]),
.WEnc (WInc),
.RClk (Clk),
.RData(RData),
.RAddr(ReadPoint[DeepthBit-1 : 0]),
.REnc (RInc)
);
endmodule
| 9.340894 |
module TOP (
in,
out
);
input [7:0] in;
output [5:0] out;
COUNT_BITS8 count_bits (
.IN(in),
.C (out)
);
endmodule
| 7.097448 |
module Symbol_Lookup (
input wire [2:0] in,
output reg [2:0] out
);
always @* begin
case (in)
3'd0: out <= 3'b000;
3'd1: out <= 3'b100;
3'd2: out <= 3'b010;
3'd3: out <= 3'b001;
3'd4: out <= 3'b110;
3'd5: out <= 3'b011;
3'd6: out <= 3'b111;
3'd7: out <= 3'b101;
default: out <= 3'b000;
endcase
end
endmodule
| 7.846087 |
module Index_Lookup (
input wire [2:0] in,
output reg [2:0] out
);
always @* begin
case (in)
3'b000: out <= 3'd0;
3'b100: out <= 3'd1;
3'b010: out <= 3'd2;
3'b001: out <= 3'd3;
3'b110: out <= 3'd4;
3'b011: out <= 3'd5;
3'b111: out <= 3'd6;
3'b101: out <= 3'd7;
default: out <= 3'd0;
endcase
end
endmodule
| 8.600708 |
module symbolSync #(
parameter SYM_WIDTH = 1, //符号位位宽
parameter INT_WIDTH = 1, //整数部分位宽
parameter DEC_WIDTH = 14 //小数部分位宽
) (
input wire clk,
input wire rstn,
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] InputDataQ,
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] InputDataI,
input wire data_ready,
output wire mk,
output wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] OutputDataQ,
output wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] OutputDataI
);
wire [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] IF2ED_Q, IF2ED_I;
wire [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] ED2LF;
wire [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] LF2TC;
wire [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] uk;
wire ifDataValid, erDataValid, lfdataValid;
InterpolatedFilter #(
.SYM_WIDTH(SYM_WIDTH),
.INT_WIDTH(INT_WIDTH),
.DEC_WIDTH(DEC_WIDTH)
) InterpolatedFilter_u1 (
.clk(clk),
.rstn(rstn),
.data_ready(data_ready),
.symDataQ(InputDataQ),
.symDataI(InputDataI),
.uk(uk),
.data_valid(ifDataValid),
.FilterOutputDataQ(IF2ED_Q),
.FilterOutputDataI(IF2ED_I)
);
//-----------------------------------
ErrDetecer #(
.SYM_WIDTH(SYM_WIDTH),
.INT_WIDTH(INT_WIDTH),
.DEC_WIDTH(DEC_WIDTH)
) ErrDetecer_u1 (
.clk(clk),
.rstn(rstn),
.data_ready(ifDataValid),
.ErrDetecerInputDataQ(IF2ED_Q),
.ErrDetecerInputDataI(IF2ED_I),
.data_valid(erDataValid),
.ErrDetecerOutputData(ED2LF)
);
//-----------------------------------
LoopFilter #(
.SYM_WIDTH(SYM_WIDTH),
.INT_WIDTH(INT_WIDTH),
.DEC_WIDTH(DEC_WIDTH)
) LoopFilter_u1 (
.clk(clk),
.rstn(rstn),
.mk(mk),
.data_ready(erDataValid),
.LoopFilterInputData(ED2LF),
.data_valid(lfdataValid),
.LoopFilterOutputData(LF2TC)
);
//-----------------------------------
TimingControl #(
.SYM_WIDTH(SYM_WIDTH),
.INT_WIDTH(INT_WIDTH),
.DEC_WIDTH(DEC_WIDTH)
) TimingControl_u1 (
.clk(clk),
.rstn(rstn),
.mk(mk),
.data_ready(lfdataValid),
.TimingControlInputData(LF2TC),
.uk(uk)
);
//-----------------------------------
Resample #(
.SYM_WIDTH(SYM_WIDTH),
.INT_WIDTH(INT_WIDTH),
.DEC_WIDTH(DEC_WIDTH)
) Resample_u1 (
.clk(clk),
.rstn(rstn),
.mk(mk),
.ResampleInputDataQ(InputDataQ),
.ResampleInputDataI(InputDataI),
.ResampleOutputDataQ(OutputDataQ),
.ResampleOutputDataI(OutputDataI)
);
endmodule
| 7.961162 |
module symbol_game(answer, submit, clock, counter, difficulty, reset,
out_LEDG, out_LEDR, out_HEX1, out_HEX2, out_HEX3, out_HEX4,
win, lose);
input [17:0] answer;
input submit;
input clock;
input [27:0] counter;
input [1:0] difficulty;
input reset;
output [7:0] out_LEDG;
output [17:0] out_LEDR;
output [7:0] out_HEX1;
output [7:0] out_HEX2;
output [7:0] out_HEX3;
output [7:0] out_HEX4;
output win;
output lose;
wire [17:0] combination;
wire [7:0] symbol;
reg randomize;
reg [2:0] random_indicator;
reg [4:0] Y_Q, Y_D;
initial randomize = 0;
// FSM states
localparam A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011,
E = 3'b100, F = 3'b101, W = 3'b110, L = 3'b111;
// FSM
always @ (*)
begin: state_table
case (Y_Q)
// initialize
A: begin
if (answer == combination) Y_D <= B; // if correct then advance
else Y_D <= L; // else you lose
end
B: begin
if (answer == combination) begin
if (difficulty == 2'b00) Y_D <= W; // win case for easy (2 completions)
else Y_D <= C; // if correct then advance
end
else Y_D <= L; // else you lose
end
C: begin
if (answer == combination) begin
if (difficulty == 2'b01) Y_D <= W; // win case for med (3 completions)
else Y_D <= D; // if correct then advance
end
else Y_D <= L; // else you lose
end
D: begin
if (answer == combination) Y_D <= E; // if correct then advance
else Y_D <= L; // else you lose
end
E: begin
if (answer == combination) Y_D <= W; // win case for hard (5 completions)
else Y_D <= L; // else you lose
end
// win case
W: begin
Y_D <= W;
end
// lose case
L: begin
Y_D <= L;
end
default: Y_D = A;
endcase
end // state_table
// State Registers
always @ (negedge submit)
begin: state_FFs
Y_Q <= Y_D;
end // state_FFS
assign out_LEDG[0] = (Y_Q == A);
assign out_LEDG[1] = (Y_Q == B);
assign out_LEDG[2] = (Y_Q == C);
assign out_LEDG[3] = (Y_Q == D);
assign out_LEDG[4] = (Y_Q == E);
assign out_LEDG[5] = (Y_Q == F);
assign out_LEDG[6] = (Y_Q == W);
assign out_LEDG[7] = (Y_Q == L);
// processes data for module
always @ (*)
begin
// resets randomizer after submission
if (submit == 1'b0) begin
randomize <= 0;
end
// randomizer
if (randomize == 1'b0) begin
random_indicator <= {difficulty[1], difficulty[0], counter[1], counter[0]}; // random 3 bit number
randomize <= 1; // only allow rate to generate once
end
end
// target values
symbol_game_symbol_maker my_symbol(.in(random_indicator), .out(symbol));
symbol_game_combination_maker my_combination(.in(random_indicator), .out(combination));
assign win = (Y_Q == W);
assign lose = (Y_Q == L);
assign out_HEX1 = symbol;
endmodule
| 7.125038 |
module symbol_game_symbol_maker (
in,
out
);
input [2:0] in;
output reg [6:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 7'b1101000;
3'b001: out = 7'b1100010;
3'b010: out = 7'b1010011;
3'b011: out = 7'b1000001;
3'b100: out = 7'b1110100;
3'b101: out = 7'b0110110;
3'b110: out = 7'b0011100;
3'b111: out = 7'b0111010;
default out = 7'b0000000;
endcase
end
endmodule
| 7.223403 |
module symbol_game_combination_maker (
in,
out
);
input [2:0] in;
output reg [17:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 18'b10_0100_0110_1111_0000;
3'b001: out = 18'b01_0110_0001_0100_1101;
3'b010: out = 18'b00_1100_0111_1010_1010;
3'b011: out = 18'b11_0110_0100_1100_1111;
3'b100: out = 18'b00_1000_0110_0001_0100;
3'b101: out = 18'b00_0111_1100_0001_0101;
3'b110: out = 18'b01_1100_0100_1010_0110;
3'b111: out = 18'b10_0110_0001_1100_0111;
default out = 18'b00_0000_0000_0000_0000;
endcase
end
endmodule
| 6.842603 |
module ratedivider (
clock,
reset,
divide,
cout
);
input clock;
input reset;
input [27:0] divide;
output reg cout;
reg [27:0] count; //counts upto divide
initial count = 0;
// new clock based on divide where output flips at divide
always @(posedge clock) begin
if (!reset) begin
if (count == divide) begin
count <= 0;
cout = !cout; // output flip
end else begin
count <= count + 1;
cout <= cout;
end
end else begin
count <= 0;
cout <= 0;
end
end
endmodule
| 8.084012 |
module symbol_top2 (
CLOCK_50,
KEY,
VGA_HS,
VGA_VS,
column,
row,
VGA_B,
VGA_G,
VGA_R,
VGA_CLK,
LEDR
);
input wire CLOCK_50;
input wire [3:0] KEY;
output wire VGA_HS;
output wire VGA_VS;
output wire [9:0] column;
output wire [8:0] row;
output wire [7:0] VGA_B;
output wire [7:0] VGA_G;
output wire [7:0] VGA_R;
output wire [17:0] LEDR;
output wire VGA_CLK;
assign VGA_CLK = clk25_sig;
wire clk100_sig;
wire rstLog_sig;
wire rd_en_sig;
wire wr_en_sig;
wire [31:0] data_bus_sig;
wire clk25_sig;
wire videoon_sig;
wire empty_sig;
wire [23:0] data_pixel_sig;
wire rstVGA_sig;
wire [7:0] blue_sig;
wire [7:0] green_sig;
wire [7:0] red_sig;
wire locked_sig;
wire [3:0] freeslots_sig;
assign rstLog_sig = ~KEY[1];
FIFO b2v_buffer (
.clk(clk100_sig),
.rst(rstLog_sig),
.rd_en(rd_en_sig),
.wr_en(wr_en_sig),
.data_in(data_bus_sig),
.empty(empty_sig),
.data_pixel(data_pixel_sig),
.freeslots(freeslots_sig)
);
FIFO_reader b2v_controller (
.clk100(clk100_sig),
.clk25(clk25_sig),
.rst(rstLog_sig),
.videoon(videoon_sig),
.empty(empty_sig),
.data_pixel(data_pixel_sig),
.rd_en(rd_en_sig),
.rstVGA(rstVGA_sig),
.blue(blue_sig),
.green(green_sig),
.red(red_sig)
);
PixelLogic b2v_dac_interface (
.clk(clk25_sig),
.reset(rstVGA_sig),
.blue(blue_sig),
.green(green_sig),
.red(red_sig),
.hsync(VGA_HS),
.vsync(VGA_VS),
.vga_enabled(videoon_sig),
.b(VGA_B),
.column(column),
.g(VGA_G),
.r(VGA_R),
.row(row)
);
//resetLogic b2v_inst(
// .clkin(clk25_sig),
// .locked(locked_sig),
// .rstSignal(rstLog_sig));
sdram_simulator b2v_inst1 (
.clkin(clk100_sig),
.rst(rstLog_sig),
.freeslots(freeslots_sig),
.wr_en(wr_en_sig),
.data_out(data_bus_sig),
.LEDR(LEDR)
);
pll b2v_pelele (
.inclk0(CLOCK_50),
.areset(~KEY[0]),
.c0(clk100_sig),
.c1(clk25_sig),
.locked(locked_sig)
);
endmodule
| 7.665902 |
module symbol_top_inst (
// wr_en,
CLOCK_50,
// data_in,
KEY,
VGA_HS,
VGA_VS,
column,
// freeslots,
row,
VGA_B,
VGA_G,
VGA_R,
VGA_SYNC_N,
VGA_BLANK_N,
VGA_CLK,
LEDR
);
//input wire wr_en;
input wire CLOCK_50;
//input wire [31:0] data_in;
input wire [3:0] KEY;
output wire VGA_HS;
output wire VGA_VS;
output wire [9:0] column;
//output wire [3:0] freeslots;
output wire [8:0] row;
output wire [7:0] VGA_B;
output wire [7:0] VGA_G;
output wire [7:0] VGA_R;
output wire [17:0] LEDR;
output wire VGA_SYNC_N, VGA_BLANK_N, VGA_CLK;
assign VGA_SYNC_N = 1'b1;
assign VGA_BLANK_N = 1'b1;
symbol_top2 u0 ( // input [0:0] KEY_sig
// .data_in(data_in) , // input [31:0] data_in_sig
.KEY(KEY),
// .wr_en(wr_en) , // input wr_en_sig
.CLOCK_50(CLOCK_50), // input CLOCK_50_sig
.row(row), // output [8:0] row_sig
.column(column), // output [9:0] column_sig
.VGA_R(VGA_R), // output [7:0] VGA_R_sig
.VGA_G(VGA_G), // output [7:0] VGA_G_sig
.VGA_B(VGA_B), // output [7:0] VGA_B_sig
.VGA_HS(VGA_HS), // output VGA_HS_sig
.VGA_VS(VGA_VS), // output VGA_VS_sig
// .freeslots(freeslots) // output [3:0] freeslots_sig
.LEDR(LEDR),
.VGA_CLK(VGA_CLK)
);
endmodule
| 7.137362 |
module symmetric_mem_core #(
parameter RAM_WIDTH = 16,
parameter RAM_ADDR_BITS = 5
)(
input wire clockA,
input wire clockB,
input wire write_enableA,
input wire write_enableB,
input wire [RAM_ADDR_BITS-1:0] addressA,
input wire [RAM_ADDR_BITS-1:0] addressB,
input wire [RAM_WIDTH-1:0] input_dataA,
input wire [RAM_WIDTH-1:0] input_dataB,
output reg [RAM_WIDTH-1:0] output_dataA,
output reg [RAM_WIDTH-1:0] output_dataB
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
`define SIM
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
// (* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] sym_ram [(2**RAM_ADDR_BITS)-1:0];
wire enableA;
wire enableB;
integer begin_address = 0;
integer end_address = 2**RAM_ADDR_BITS)-1;
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the clk wire signal
//------------------------------------------------------------------------------------------------
assign enableA = 1'b1;
assign enableB = 1'b1;
// The forllowing code is only necessary if you wish to initialize the RAM
// contents via an external file (use $readmemb for binary data)
`ifdef SIM
integer i;
initial begin
for(i=0;i<2**RAM_ADDR_BITS;i=i+1)
sym_ram[i] = 'd0;
end
`else
initial
$readmemh("data_file_name", sym_ram, begin_address, end_address);
`endif
always @(posedge clockA)
if (enableA) begin
if (write_enableA)
sym_ram[addressA] <= input_dataA;
output_dataA <= sym_ram[addressA];
end
always @(posedge clockB)
if (enableB) begin
if (write_enableB)
sym_ram[addressB] <= input_dataB;
output_dataB <= sym_ram[addressB];
end
endmodule
| 8.125302 |
module SYMM_MUL4 (
input clk_mul4,
input en_mul4,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
output reg signed [25:0] o11,
o12,
o13,
o14,
output reg signed [25:0] o21,
o22,
o23,
o24,
output reg signed [25:0] o31,
o32,
o33,
o34,
output reg signed [25:0] o41,
o42,
o43,
o44,
output signed [25:0] o11_2,
o12_2,
o13_2,
o14_2,
output signed [25:0] o21_2,
o22_2,
o23_2,
o24_2,
output signed [25:0] o31_2,
o32_2,
o33_2,
o34_2,
output signed [25:0] o41_2,
o42_2,
o43_2,
o44_2
);
reg [51:0]
dot11,
dot12,
dot13,
dot14,
dot21,
dot22,
dot23,
dot24,
dot31,
dot32,
dot33,
dot34,
dot41,
dot42,
dot43,
dot44;
assign o11_2 = dot11[38:13];
assign o12_2 = dot12[38:13];
assign o13_2 = dot13[38:13];
assign o14_2 = dot14[38:13];
assign o21_2 = dot21[38:13];
assign o22_2 = dot22[38:13];
assign o23_2 = dot23[38:13];
assign o24_2 = dot24[38:13];
assign o31_2 = dot31[38:13];
assign o32_2 = dot32[38:13];
assign o33_2 = dot33[38:13];
assign o34_2 = dot34[38:13];
assign o41_2 = dot41[38:13];
assign o42_2 = dot42[38:13];
assign o43_2 = dot43[38:13];
assign o44_2 = dot44[38:13];
always @(posedge clk_mul4) begin
if (en_mul4) begin
o11 <= i11;
o12 <= i12;
o13 <= i13;
o14 <= i14;
o21 <= i21;
o22 <= i22;
o23 <= i23;
o24 <= i24;
o31 <= i31;
o32 <= i32;
o33 <= i33;
o34 <= i34;
o41 <= i41;
o42 <= i42;
o43 <= i43;
o44 <= i44;
dot11 <= i11 * i11 + i12 * i12 + i13 * i13 + i14 * i14;
dot12 <= i11 * i21 + i12 * i22 + i13 * i23 + i14 * i24;
dot13 <= i11 * i31 + i12 * i32 + i13 * i33 + i14 * i34;
dot14 <= i11 * i41 + i12 * i42 + i13 * i43 + i14 * i44;
dot21 <= i21 * i11 + i22 * i12 + i23 * i13 + i24 * i14;
dot22 <= i21 * i21 + i22 * i22 + i23 * i23 + i24 * i24;
dot23 <= i21 * i31 + i22 * i32 + i23 * i33 + i24 * i34;
dot24 <= i21 * i41 + i22 * i42 + i23 * i43 + i24 * i44;
dot31 <= i31 * i11 + i32 * i12 + i33 * i13 + i34 * i14;
dot32 <= i31 * i21 + i32 * i22 + i33 * i23 + i34 * i24;
dot33 <= i31 * i31 + i32 * i32 + i33 * i33 + i34 * i34;
dot34 <= i31 * i41 + i32 * i42 + i33 * i43 + i34 * i44;
dot41 <= i41 * i11 + i42 * i12 + i43 * i13 + i44 * i14;
dot42 <= i41 * i21 + i42 * i22 + i43 * i23 + i44 * i24;
dot43 <= i41 * i31 + i42 * i32 + i43 * i33 + i44 * i34;
dot44 <= i41 * i41 + i42 * i42 + i43 * i43 + i44 * i44;
end else begin
// o11 <= i11; o12 <= i12; o13 <= i13; o14 <= i14;
// o21 <= i21; o22 <= i22; o23 <= i23; o24 <= i24;
// o31 <= i31; o32 <= i32; o33 <= i33; o34 <= i34;
// o41 <= i41; o42 <= i42; o43 <= i43; o44 <= i44;
// dot11 <= 0; dot12 <= 0; dot13 <= 0; dot14 <= 0;
// dot21 <= 0; dot22 <= 0; dot23 <= 0; dot24 <= 0;
// dot31 <= 0; dot32 <= 0; dot33 <= 0; dot34 <= 0;
// dot41 <= 0; dot42 <= 0; dot43 <= 0; dot44 <= 0;
end
end
endmodule
| 6.644102 |
module SYMM_SELECT (
input clk_sel,
input en_sel,
input select,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed [25:0] i11_2,
i12_2,
i13_2,
i14_2,
input signed [25:0] i21_2,
i22_2,
i23_2,
i24_2,
input signed [25:0] i31_2,
i32_2,
i33_2,
i34_2,
input signed [25:0] i41_2,
i42_2,
i43_2,
i44_2,
output reg signed [25:0] o11,
o12,
o13,
o14,
output reg signed [25:0] o21,
o22,
o23,
o24,
output reg signed [25:0] o31,
o32,
o33,
o34,
output reg signed [25:0] o41,
o42,
o43,
o44
);
always @(posedge clk_sel) begin
if (en_sel) begin
if (!select) begin
o11 <= i11;
o12 <= i12;
o13 <= i13;
o14 <= i14;
o21 <= i21;
o22 <= i22;
o23 <= i23;
o24 <= i24;
o31 <= i31;
o32 <= i32;
o33 <= i33;
o34 <= i34;
o41 <= i41;
o42 <= i42;
o43 <= i43;
o44 <= i44;
end else begin
o11 <= i11_2;
o12 <= i12_2;
o13 <= i13_2;
o14 <= i14_2;
o21 <= i21_2;
o22 <= i22_2;
o23 <= i23_2;
o24 <= i24_2;
o31 <= i31_2;
o32 <= i32_2;
o33 <= i33_2;
o34 <= i34_2;
o41 <= i41_2;
o42 <= i42_2;
o43 <= i43_2;
o44 <= i44_2;
end
end else begin
// o11 <= i11; o12 <= i12; o13 <= i13; o14 <= i14;
// o21 <= i21; o22 <= i22; o23 <= i23; o24 <= i24;
// o31 <= i31; o32 <= i32; o33 <= i33; o34 <= i34;
// o41 <= i41; o42 <= i42; o43 <= i43; o44 <= i44;
end
end
endmodule
| 6.698418 |
module SYMM_SUB (
input clk_sub,
input en_sub,
input signed [25:0] i1_11,
i1_12,
i1_13,
i1_14,
input signed [25:0] i1_21,
i1_22,
i1_23,
i1_24,
input signed [25:0] i1_31,
i1_32,
i1_33,
i1_34,
input signed [25:0] i1_41,
i1_42,
i1_43,
i1_44,
input signed [25:0] i2_11,
i2_12,
i2_13,
i2_14,
input signed [25:0] i2_21,
i2_22,
i2_23,
i2_24,
input signed [25:0] i2_31,
i2_32,
i2_33,
i2_34,
input signed [25:0] i2_41,
i2_42,
i2_43,
i2_44,
output reg signed [25:0] o11,
o12,
o13,
o14,
output reg signed [25:0] o21,
o22,
o23,
o24,
output reg signed [25:0] o31,
o32,
o33,
o34,
output reg signed [25:0] o41,
o42,
o43,
o44
);
always @(posedge clk_sub) begin
if (en_sub) begin
o11 <= i1_11 - i2_11;
o12 <= i1_12 - i2_12;
o13 <= i1_13 - i1_13;
o14 <= i1_14 - i1_14;
o21 <= i1_21 - i2_21;
o22 <= i1_22 - i2_22;
o23 <= i1_23 - i1_23;
o24 <= i1_24 - i1_24;
o31 <= i1_31 - i2_31;
o32 <= i1_32 - i2_32;
o33 <= i1_33 - i1_33;
o34 <= i1_34 - i1_34;
o41 <= i1_41 - i2_41;
o42 <= i1_42 - i2_42;
o43 <= i1_43 - i1_43;
o44 <= i1_44 - i1_44;
end else begin
o11 <= i1_11;
o12 <= i1_12;
o13 <= i1_13;
o14 <= i1_14;
o21 <= i1_21;
o22 <= i1_22;
o23 <= i1_23;
o24 <= i1_24;
o31 <= i1_31;
o32 <= i1_32;
o33 <= i1_33;
o34 <= i1_34;
o41 <= i1_41;
o42 <= i1_42;
o43 <= i1_43;
o44 <= i1_44;
end
end
endmodule
| 6.5141 |
module SYMM_TEST (
input clk_test,
input en_test,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed [25:0] i11_2,
i12_2,
i13_2,
i14_2,
input signed [25:0] i21_2,
i22_2,
i23_2,
i24_2,
input signed [25:0] i31_2,
i32_2,
i33_2,
i34_2,
input signed [25:0] i41_2,
i42_2,
i43_2,
i44_2,
output reg signed [25:0] o11,
o12,
o13,
o14,
output reg signed [25:0] o21,
o22,
o23,
o24,
output reg signed [25:0] o31,
o32,
o33,
o34,
output reg signed [25:0] o41,
o42,
o43,
o44,
output reg isOrth
);
wire signed [29:0] orthtest;
assign orthtest = i11_2 + i12_2 + i13_2 + i14_2
+ i21_2 + i22_2 + i23_2 + i24_2
+ i31_2 + i32_2 + i33_2 + i34_2
+ i41_2 + i42_2 + i43_2 + i44_2;
always @(posedge clk_test) begin
if (en_test) begin
o11 <= i11;
o12 <= i12;
o13 <= i13;
o14 <= i14;
o21 <= i21;
o22 <= i22;
o23 <= i23;
o24 <= i24;
o31 <= i31;
o32 <= i32;
o33 <= i33;
o34 <= i34;
o41 <= i41;
o42 <= i42;
o43 <= i43;
o44 <= i44;
if (orthtest <= 30'd1) isOrth <= 1;
else isOrth <= 0;
end else begin
// o11 <= i11; o12 <= i12; o13 <= i13; o14 <= i14;
// o21 <= i21; o22 <= i22; o23 <= i23; o24 <= i24;
// o31 <= i31; o32 <= i32; o33 <= i33; o34 <= i34;
// o41 <= i41; o42 <= i42; o43 <= i43; o44 <= i44;
isOrth <= 0;
end
end
endmodule
| 6.830955 |
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