code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module swap_reg_file_tb ();
localparam ADDR_WIDTH = 7;
localparam DATA_WIDTH = 8;
reg clk, reset_n;
reg we;
reg [ADDR_WIDTH - 1:0] address_w, address_r;
reg [DATA_WIDTH - 1:0] data_w;
wire [DATA_WIDTH - 1:0] data_r;
reg [ADDR_WIDTH - 1:0] address_A, address_B;
reg swap;
integer i;
// Instantiate unit under test
swap_reg_file #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) uut (
.clk(clk),
.reset_n(reset_n),
.we(we),
.address_w(address_w),
.address_r(address_r),
.data_w(data_w),
.data_r(data_r),
.address_A(address_A),
.address_B(address_B),
.swap(swap)
);
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
initial begin
// issue a quick reset for 2 ns
reset_n = 1'b0;
#2 reset_n = 1'b1;
swap = 1'b0;
// fill locations 20 to 30 with some numbers
for (i = 20; i < 30; i = i + 1) begin
@(negedge clk);
address_w = i;
data_w = i;
we = 1'b1;
end
we = 1'b0;
// Swap 2 locations several times
@(negedge clk) address_A = 'd22;
address_B = 'd28;
swap = 1'b1;
repeat (3) @(negedge clk);
swap = 1'b0;
#25 $stop;
end
endmodule
| 7.494731 |
module swap_tb ();
reg clk, rst, load;
reg [3:0] data_in0, data_in1, data_in2, data_in3, data_in4, data_in5, data_in6, data_in7;
wire [3:0] data_out0, data_out1, data_out2, data_out3, data_out4, data_out5, data_out6, data_out7;
initial begin
#0 rst = 0;
#0 clk = 0;
#0 load = 0;
#5 data_in0 = 8;
data_in1 = 7;
data_in2 = 6;
data_in3 = 5;
data_in4 = 4;
data_in5 = 3;
data_in6 = 2;
data_in7 = 1;
#11 rst = 1;
#20 load = 1;
//#15 load=0;
#400 $finish;
end
swap i1 (
.clk(clk),
.rst(rst),
.load(load),
.data_in0(data_in0),
.data_in1(data_in1),
.data_in2(data_in2),
.data_in3(data_in3),
.data_in4(data_in4),
.data_in5(data_in5),
.data_in6(data_in6),
.data_in7(data_in7),
.data_out0(data_out0),
.data_out1(data_out1),
.data_out2(data_out2),
.data_out3(data_out3),
.data_out4(data_out4),
.data_out5(data_out5),
.data_out6(data_out6),
.data_out7(data_out7)
);
always #5 clk = ~clk;
endmodule
| 7.589824 |
module swBUF (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire empty = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
wire full = sub_wire2;
scfifo scfifo_component (
.rdreq(rdreq),
.sclr(sclr),
.clock(clock),
.wrreq(wrreq),
.data(data),
.empty(sub_wire0),
.q(sub_wire1),
.full(sub_wire2)
// synopsys translate_off
, .aclr(),
.almost_empty(),
.almost_full(),
.usedw()
// synopsys translate_on
);
defparam scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix II", scfifo_component.lpm_numwords = 4096,
scfifo_component.lpm_showahead = "OFF", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32, scfifo_component.lpm_widthu = 12,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 7.116942 |
module swBUF (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
endmodule
| 7.116942 |
module swDac #(
parameter width = 4,
sample_time = 128 /*Default 32768 Hz*/
) (
input clk,
input [width-1:0] left,
input [width-1:0] right
);
fixedTimer #(sample_time) timer (
clk,
sampleClk
);
initial $display("%d %d", width, sample_time); // begin with params so we can interpret the file
always @(posedge sampleClk) begin
$display("%d %d %d", 0 /*should be time*/, left, right);
end
endmodule
| 6.674944 |
module Swept (
input i_clk,
output reg [3:0] o_Row
);
reg [1:0] r_count = 0;
always @(posedge i_clk) begin
case (r_count)
2'b00: o_Row <= 4'b1000;
2'b01: o_Row <= 4'b0100;
2'b10: o_Row <= 4'b0010;
2'b11: o_Row <= 4'b0001;
endcase
r_count <= r_count + 1;
end
endmodule
| 6.620203 |
module SevSegDisplays_Controller (
input wire clk,
input wire rst_n,
input wire [ 7:0] Enables_Reg,
input wire [31:0] Digits_Reg,
output wire [ 7:0] AN,
output wire [ 6:0] Digits_Bits
);
wire [(COUNT_MAX-1):0] countSelection;
wire [3:0] DecNumber;
wire overflow_o_count;
SevenSegDecoder SevSegDec (
.data(DecNumber),
.seg (Digits_Bits)
);
counter #(COUNT_MAX) counter20 (
clk,
~rst_n,
1'b0,
1'b1,
1'b0,
1'b0,
16'b0,
countSelection,
overflow_o_count
);
wire [7:0][7:0] enable;
assign enable[0] = (Enables_Reg | 8'hfe);
assign enable[1] = (Enables_Reg | 8'hfd);
assign enable[2] = (Enables_Reg | 8'hfb);
assign enable[3] = (Enables_Reg | 8'hf7);
assign enable[4] = (Enables_Reg | 8'hef);
assign enable[5] = (Enables_Reg | 8'hdf);
assign enable[6] = (Enables_Reg | 8'hbf);
assign enable[7] = (Enables_Reg | 8'h7f);
SevSegMux #(
.DATA_WIDTH(8),
.N_IN(8)
) Select_Enables (
.IN_DATA(enable),
.OUT_DATA(AN),
.SEL(countSelection[(COUNT_MAX-1):(COUNT_MAX-3)])
);
wire [7:0][3:0] digits_concat;
assign digits_concat[0] = Digits_Reg[3:0];
assign digits_concat[1] = Digits_Reg[7:4];
assign digits_concat[2] = Digits_Reg[11:8];
assign digits_concat[3] = Digits_Reg[15:12];
assign digits_concat[4] = Digits_Reg[19:16];
assign digits_concat[5] = Digits_Reg[23:20];
assign digits_concat[6] = Digits_Reg[27:24];
assign digits_concat[7] = Digits_Reg[31:28];
SevSegMux #(
.DATA_WIDTH(4),
.N_IN(8)
) Select_Digits (
.IN_DATA(digits_concat),
.OUT_DATA(DecNumber),
.SEL(countSelection[(COUNT_MAX-1):(COUNT_MAX-3)])
);
endmodule
| 6.733215 |
module SevenSegDecoder (
input wire [3:0] data,
output reg [6:0] seg
);
always @(*)
case (data)
// abc_defg
4'h0: seg = 7'b000_0001;
4'h1: seg = 7'b100_1111;
4'h2: seg = 7'b001_0010;
4'h3: seg = 7'b000_0110;
4'h4: seg = 7'b100_1100;
4'h5: seg = 7'b010_0100;
4'h6: seg = 7'b010_0000;
4'h7: seg = 7'b000_1111;
4'h8: seg = 7'b000_0000;
4'h9: seg = 7'b000_1100;
4'ha: seg = 7'b000_1000;
4'hb: seg = 7'b110_0000;
4'hc: seg = 7'b111_0010;
4'hd: seg = 7'b100_0010;
4'he: seg = 7'b011_0000;
4'hf: seg = 7'b011_1000;
default: seg = 7'b111_1111;
endcase
endmodule
| 7.177629 |
module SevSegMux #(
parameter DATA_WIDTH = 64,
parameter N_IN = 16,
parameter SEL_WIDTH = $clog2(N_IN)
) (
input wire [ N_IN-1:0][DATA_WIDTH-1:0] IN_DATA,
output wire [DATA_WIDTH-1:0] OUT_DATA,
input wire [ SEL_WIDTH-1:0] SEL
);
assign OUT_DATA = IN_DATA[SEL];
endmodule
| 9.048564 |
module rvclkhdr (
en,
clk,
scan_mode,
l1clk
);
input en;
input clk;
input scan_mode;
output l1clk;
wire l1clk;
clockhdr rvclkhdr (
.TE(scan_mode),
.E (en),
.CP(clk),
.Q (l1clk)
);
endmodule
| 6.611808 |
module rvdff_WIDTH1 (
din,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input clk;
input rst_l;
wire N0;
reg [0:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[0] <= 1'b0;
end else if (1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
| 6.586933 |
module rvdffsc_WIDTH1 (
din,
en,
clear,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input en;
input clear;
input clk;
input rst_l;
wire [0:0] dout, din_new;
wire N0, N1, N2, N3, N4;
rvdff_WIDTH1 dffsc (
.din (din_new[0]),
.clk (clk),
.rst_l(rst_l),
.dout (dout[0])
);
assign N3 = (N0) ? din[0] : (N1) ? dout[0] : 1'b0;
assign N0 = en;
assign N1 = N2;
assign N2 = ~en;
assign din_new[0] = N4 & N3;
assign N4 = ~clear;
endmodule
| 6.581838 |
module rvdffs_WIDTH4 (
din,
en,
clk,
rst_l,
dout
);
input [3:0] din;
output [3:0] dout;
input en;
input clk;
input rst_l;
wire [3:0] dout;
wire N0, N1, n_0_net__3_, n_0_net__2_, n_0_net__1_, n_0_net__0_, N2;
rvdff_WIDTH4 dffs (
.din ({n_0_net__3_, n_0_net__2_, n_0_net__1_, n_0_net__0_}),
.clk (clk),
.rst_l(rst_l),
.dout (dout)
);
assign {n_0_net__3_, n_0_net__2_, n_0_net__1_, n_0_net__0_} = (N0) ? din : (N1) ? dout : 1'b0;
assign N0 = en;
assign N1 = N2;
assign N2 = ~en;
endmodule
| 6.583077 |
module rvbtb_addr_hash (
pc,
hash
);
input [31:1] pc;
output [5:4] hash;
wire [5:4] hash;
wire N0, N1;
assign hash[5] = N0 ^ pc[9];
assign N0 = pc[5] ^ pc[7];
assign hash[4] = N1 ^ pc[8];
assign N1 = pc[4] ^ pc[6];
endmodule
| 7.670784 |
module rvbtb_tag_hash (
pc,
hash
);
input [31:1] pc;
output [8:0] hash;
wire [8:0] hash;
assign hash[8] = pc[23] ^ pc[14];
assign hash[7] = pc[22] ^ pc[13];
assign hash[6] = pc[21] ^ pc[12];
assign hash[5] = pc[20] ^ pc[11];
assign hash[4] = pc[19] ^ pc[10];
assign hash[3] = pc[18] ^ pc[9];
assign hash[2] = pc[17] ^ pc[8];
assign hash[1] = pc[16] ^ pc[7];
assign hash[0] = pc[15] ^ pc[6];
endmodule
| 6.629617 |
module rvdffe_WIDTH48 (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
input [47:0] din;
output [47:0] dout;
input en;
input clk;
input rst_l;
input scan_mode;
wire [47:0] dout;
wire l1clk;
rvclkhdr genblock_clkhdr (
.en(en),
.clk(clk),
.scan_mode(scan_mode),
.l1clk(l1clk)
);
rvdff_WIDTH48 genblock_dff (
.din (din),
.clk (l1clk),
.rst_l(rst_l),
.dout (dout)
);
endmodule
| 6.571079 |
module rvdff_WIDTH8 (
din,
clk,
rst_l,
dout
);
input [7:0] din;
output [7:0] dout;
input clk;
input rst_l;
wire N0;
reg [7:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[7] <= 1'b0;
end else if (1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[6] <= 1'b0;
end else if (1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[5] <= 1'b0;
end else if (1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[4] <= 1'b0;
end else if (1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[3] <= 1'b0;
end else if (1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[2] <= 1'b0;
end else if (1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[1] <= 1'b0;
end else if (1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[0] <= 1'b0;
end else if (1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
| 6.58784 |
module rvdffe_WIDTH8 (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
input [7:0] din;
output [7:0] dout;
input en;
input clk;
input rst_l;
input scan_mode;
wire [7:0] dout;
wire l1clk;
rvclkhdr genblock_clkhdr (
.en(en),
.clk(clk),
.scan_mode(scan_mode),
.l1clk(l1clk)
);
rvdff_WIDTH8 genblock_dff (
.din (din),
.clk (l1clk),
.rst_l(rst_l),
.dout (dout)
);
endmodule
| 6.62585 |
module rveven_paritycheck (
data_in,
parity_in,
parity_err
);
input [15:0] data_in;
input parity_in;
output parity_err;
wire parity_err, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14;
assign parity_err = N14 ^ parity_in;
assign N14 = N13 ^ data_in[0];
assign N13 = N12 ^ data_in[1];
assign N12 = N11 ^ data_in[2];
assign N11 = N10 ^ data_in[3];
assign N10 = N9 ^ data_in[4];
assign N9 = N8 ^ data_in[5];
assign N8 = N7 ^ data_in[6];
assign N7 = N6 ^ data_in[7];
assign N6 = N5 ^ data_in[8];
assign N5 = N4 ^ data_in[9];
assign N4 = N3 ^ data_in[10];
assign N3 = N2 ^ data_in[11];
assign N2 = N1 ^ data_in[12];
assign N1 = N0 ^ data_in[13];
assign N0 = data_in[15] ^ data_in[14];
endmodule
| 7.582388 |
module rveven_paritygen_WIDTH16 (
data_in,
parity_out
);
input [15:0] data_in;
output parity_out;
wire parity_out, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13;
assign parity_out = N13 ^ data_in[0];
assign N13 = N12 ^ data_in[1];
assign N12 = N11 ^ data_in[2];
assign N11 = N10 ^ data_in[3];
assign N10 = N9 ^ data_in[4];
assign N9 = N8 ^ data_in[5];
assign N8 = N7 ^ data_in[6];
assign N7 = N6 ^ data_in[7];
assign N6 = N5 ^ data_in[8];
assign N5 = N4 ^ data_in[9];
assign N4 = N3 ^ data_in[10];
assign N3 = N2 ^ data_in[11];
assign N2 = N1 ^ data_in[12];
assign N1 = N0 ^ data_in[13];
assign N0 = data_in[15] ^ data_in[14];
endmodule
| 7.582388 |
module rvdff_WIDTH18 (
din,
clk,
rst_l,
dout
);
input [17:0] din;
output [17:0] dout;
input clk;
input rst_l;
wire N0;
reg [17:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[17] <= 1'b0;
end else if (1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[16] <= 1'b0;
end else if (1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[15] <= 1'b0;
end else if (1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[14] <= 1'b0;
end else if (1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[13] <= 1'b0;
end else if (1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[12] <= 1'b0;
end else if (1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[11] <= 1'b0;
end else if (1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[10] <= 1'b0;
end else if (1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[9] <= 1'b0;
end else if (1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[8] <= 1'b0;
end else if (1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[7] <= 1'b0;
end else if (1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[6] <= 1'b0;
end else if (1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[5] <= 1'b0;
end else if (1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[4] <= 1'b0;
end else if (1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[3] <= 1'b0;
end else if (1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[2] <= 1'b0;
end else if (1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[1] <= 1'b0;
end else if (1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[0] <= 1'b0;
end else if (1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
| 6.563022 |
module rvdff_WIDTH20 (
din,
clk,
rst_l,
dout
);
input [19:0] din;
output [19:0] dout;
input clk;
input rst_l;
wire N0;
reg [19:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[19] <= 1'b0;
end else if (1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[18] <= 1'b0;
end else if (1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[17] <= 1'b0;
end else if (1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[16] <= 1'b0;
end else if (1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[15] <= 1'b0;
end else if (1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[14] <= 1'b0;
end else if (1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[13] <= 1'b0;
end else if (1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[12] <= 1'b0;
end else if (1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[11] <= 1'b0;
end else if (1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[10] <= 1'b0;
end else if (1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[9] <= 1'b0;
end else if (1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[8] <= 1'b0;
end else if (1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[7] <= 1'b0;
end else if (1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[6] <= 1'b0;
end else if (1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[5] <= 1'b0;
end else if (1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[4] <= 1'b0;
end else if (1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[3] <= 1'b0;
end else if (1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[2] <= 1'b0;
end else if (1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[1] <= 1'b0;
end else if (1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[0] <= 1'b0;
end else if (1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
| 6.72609 |
module rvdffs_WIDTH8 (
din,
en,
clk,
rst_l,
dout
);
input [7:0] din;
output [7:0] dout;
input en;
input clk;
input rst_l;
wire [7:0] dout;
wire N0,N1,n_0_net__7_,n_0_net__6_,n_0_net__5_,n_0_net__4_,n_0_net__3_,n_0_net__2_,
n_0_net__1_,n_0_net__0_,N2;
rvdff_WIDTH8 dffs (
.din({
n_0_net__7_,
n_0_net__6_,
n_0_net__5_,
n_0_net__4_,
n_0_net__3_,
n_0_net__2_,
n_0_net__1_,
n_0_net__0_
}),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
assign { n_0_net__7_, n_0_net__6_, n_0_net__5_, n_0_net__4_, n_0_net__3_, n_0_net__2_, n_0_net__1_, n_0_net__0_ } = (N0)? din :
(N1)? dout : 1'b0;
assign N0 = en;
assign N1 = N2;
assign N2 = ~en;
endmodule
| 6.635246 |
module cmp_and_mux_ID_BITS8_INTPRIORITY_BITS4 (
a_id,
a_priority,
b_id,
b_priority,
out_id,
out_priority
);
input [7:0] a_id;
input [3:0] a_priority;
input [7:0] b_id;
input [3:0] b_priority;
output [7:0] out_id;
output [3:0] out_priority;
wire [7:0] out_id;
wire [3:0] out_priority;
wire N0, N1, a_is_lt_b, N2;
assign a_is_lt_b = a_priority < b_priority;
assign out_id = (N0) ? b_id : (N1) ? a_id : 1'b0;
assign N0 = a_is_lt_b;
assign N1 = N2;
assign out_priority = (N0) ? b_priority : (N1) ? a_priority : 1'b0;
assign N2 = ~a_is_lt_b;
endmodule
| 7.470804 |
module rvdffsc_WIDTH2 (
din,
en,
clear,
clk,
rst_l,
dout
);
input [1:0] din;
output [1:0] dout;
input en;
input clear;
input clk;
input rst_l;
wire [1:0] dout, din_new;
wire N0, N1, N2, N3, N4, N5;
rvdff_WIDTH2 dffsc (
.din (din_new),
.clk (clk),
.rst_l(rst_l),
.dout (dout)
);
assign {N4, N3} = (N0) ? din : (N1) ? dout : 1'b0;
assign N0 = en;
assign N1 = N2;
assign N2 = ~en;
assign din_new[1] = N5 & N4;
assign N5 = ~clear;
assign din_new[0] = N5 & N3;
endmodule
| 6.581838 |
module rveven_paritygen_WIDTH20 (
data_in,
parity_out
);
input [19:0] data_in;
output parity_out;
wire parity_out, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
assign parity_out = N17 ^ data_in[0];
assign N17 = N16 ^ data_in[1];
assign N16 = N15 ^ data_in[2];
assign N15 = N14 ^ data_in[3];
assign N14 = N13 ^ data_in[4];
assign N13 = N12 ^ data_in[5];
assign N12 = N11 ^ data_in[6];
assign N11 = N10 ^ data_in[7];
assign N10 = N9 ^ data_in[8];
assign N9 = N8 ^ data_in[9];
assign N8 = N7 ^ data_in[10];
assign N7 = N6 ^ data_in[11];
assign N6 = N5 ^ data_in[12];
assign N5 = N4 ^ data_in[13];
assign N4 = N3 ^ data_in[14];
assign N3 = N2 ^ data_in[15];
assign N2 = N1 ^ data_in[16];
assign N1 = N0 ^ data_in[17];
assign N0 = data_in[19] ^ data_in[18];
endmodule
| 7.582388 |
module rveven_paritycheck_WIDTH20 (
data_in,
parity_in,
parity_err
);
input [19:0] data_in;
input parity_in;
output parity_err;
wire parity_err,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18;
assign parity_err = N18 ^ parity_in;
assign N18 = N17 ^ data_in[0];
assign N17 = N16 ^ data_in[1];
assign N16 = N15 ^ data_in[2];
assign N15 = N14 ^ data_in[3];
assign N14 = N13 ^ data_in[4];
assign N13 = N12 ^ data_in[5];
assign N12 = N11 ^ data_in[6];
assign N11 = N10 ^ data_in[7];
assign N10 = N9 ^ data_in[8];
assign N9 = N8 ^ data_in[9];
assign N8 = N7 ^ data_in[10];
assign N7 = N6 ^ data_in[11];
assign N6 = N5 ^ data_in[12];
assign N5 = N4 ^ data_in[13];
assign N4 = N3 ^ data_in[14];
assign N3 = N2 ^ data_in[15];
assign N2 = N1 ^ data_in[16];
assign N1 = N0 ^ data_in[17];
assign N0 = data_in[19] ^ data_in[18];
endmodule
| 7.582388 |
module switch_register (
input qclk, // 20MHz
// the bus
input [12:0] RAL, // latched address
input RBS7,
input [15:0] RDL, // data lines
output [15:0] TDL,
// control lines
input [17:0] addr, // default should be 777570
output addr_match,
input assert_vector,
input write_pulse
);
//
// QBUS Interface
//
reg [15:0] switch_register = 16'o0777;
assign addr_match = ((RBS7 == 1) && // I/O page
(RAL[12:0] == addr[12:0])); // my address
assign TDL = switch_register;
// write register
always @(posedge qclk) begin
// write data to register
if (addr_match && write_pulse) begin
switch_register <= RDL;
end
end
endmodule
| 7.57998 |
module Switch ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [1:0] io_i0, // @[:@6.4]
input io_i1, // @[:@6.4]
output io_out // @[:@6.4]
);
assign io_out = io_i1; // @[Switch.scala 30:10:@40.4]
endmodule
| 6.71488 |
module switch (
input [63:0] p0,
input [63:0] p1,
input [63:0] p2,
input [63:0] p3,
input [63:0] p4,
input [63:0] p5,
input [63:0] p6,
input [63:0] p7,
input [63:0] p8,
input [63:0] p9,
input [63:0] p10,
input [63:0] p11,
input [63:0] p12,
input [63:0] p13,
input [63:0] p14,
input [63:0] p15,
input [63:0] p16,
output [16:0] out1,
output [16:0] out2,
output [16:0] out3,
output [16:0] out4,
output [16:0] out5,
output [16:0] out6,
output [16:0] out7,
output [16:0] out8,
output [16:0] out9,
output [16:0] out10,
output [16:0] out11,
output [16:0] out12,
output [16:0] out13,
output [16:0] out14,
output [16:0] out15,
output [16:0] out16,
output [16:0] out17,
output [16:0] out18,
output [16:0] out19,
output [16:0] out20,
output [16:0] out21,
output [16:0] out22,
output [16:0] out23,
output [16:0] out24,
output [16:0] out25,
output [16:0] out26,
output [16:0] out27,
output [16:0] out28,
output [16:0] out29,
output [16:0] out30,
output [16:0] out31,
output [16:0] out32,
output [16:0] out33,
output [16:0] out34,
output [16:0] out35,
output [16:0] out36,
output [16:0] out37,
output [16:0] out38,
output [16:0] out39,
output [16:0] out40,
output [16:0] out41,
output [16:0] out42,
output [16:0] out43,
output [16:0] out44,
output [16:0] out45,
output [16:0] out46,
output [16:0] out47,
output [16:0] out48,
output [16:0] out49,
output [16:0] out50,
output [16:0] out51,
output [16:0] out52,
output [16:0] out53,
output [16:0] out54,
output [16:0] out55,
output [16:0] out56,
output [16:0] out57,
output [16:0] out58,
output [16:0] out59,
output [16:0] out60,
output [16:0] out61,
output [16:0] out62,
output [16:0] out63,
output [16:0] out64
);
wire [16:0] part_res[63:0];
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin : switch
assign part_res[i] = {
p16[i],
p15[i],
p14[i],
p13[i],
p12[i],
p11[i],
p10[i],
p9[i],
p8[i],
p7[i],
p6[i],
p5[i],
p4[i],
p3[i],
p2[i],
p1[i],
p0[i]
};
end
endgenerate
assign out1 = part_res[0];
assign out2 = part_res[1];
assign out3 = part_res[2];
assign out4 = part_res[3];
assign out5 = part_res[4];
assign out6 = part_res[5];
assign out7 = part_res[6];
assign out8 = part_res[7];
assign out9 = part_res[8];
assign out10 = part_res[9];
assign out11 = part_res[10];
assign out12 = part_res[11];
assign out13 = part_res[12];
assign out14 = part_res[13];
assign out15 = part_res[14];
assign out16 = part_res[15];
assign out17 = part_res[16];
assign out18 = part_res[17];
assign out19 = part_res[18];
assign out20 = part_res[19];
assign out21 = part_res[20];
assign out22 = part_res[21];
assign out23 = part_res[22];
assign out24 = part_res[23];
assign out25 = part_res[24];
assign out26 = part_res[25];
assign out27 = part_res[26];
assign out28 = part_res[27];
assign out29 = part_res[28];
assign out30 = part_res[29];
assign out31 = part_res[30];
assign out32 = part_res[31];
assign out33 = part_res[32];
assign out34 = part_res[33];
assign out35 = part_res[34];
assign out36 = part_res[35];
assign out37 = part_res[36];
assign out38 = part_res[37];
assign out39 = part_res[38];
assign out40 = part_res[39];
assign out41 = part_res[40];
assign out42 = part_res[41];
assign out43 = part_res[42];
assign out44 = part_res[43];
assign out45 = part_res[44];
assign out46 = part_res[45];
assign out47 = part_res[46];
assign out48 = part_res[47];
assign out49 = part_res[48];
assign out50 = part_res[49];
assign out51 = part_res[50];
assign out52 = part_res[51];
assign out53 = part_res[52];
assign out54 = part_res[53];
assign out55 = part_res[54];
assign out56 = part_res[55];
assign out57 = part_res[56];
assign out58 = part_res[57];
assign out59 = part_res[58];
assign out60 = part_res[59];
assign out61 = part_res[60];
assign out62 = part_res[61];
assign out63 = part_res[62];
assign out64 = part_res[63];
endmodule
| 6.864438 |
module SwitchAsyncFIFO (
inReset,
iWClk,
iWEn,
ivDataIn,
qWFull,
qvWCount,
iRClk,
iREn,
ovDataOut,
qREmpty,
qvRNumberLeft
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input inReset;
input iWClk;
input iWEn;
input [pWordWidth-1:0] ivDataIn;
output qWFull;
output [pDepthWidth:0] qvWCount;
input iRClk;
input iREn;
output [pWordWidth-1:0] ovDataOut;
output qREmpty;
output [pDepthWidth:0] qvRNumberLeft;
wire inReset;
wire iWClk;
wire iWEn;
wire [pWordWidth-1:0] ivDataIn;
wire qWFull;
wire [pDepthWidth:0] qvWCount;
wire iRClk;
wire iREn;
wire [pWordWidth-1:0] ovDataOut;
wire qREmpty;
wire [pDepthWidth:0] qvRNumberLeft;
wire MemWEn;
wire [pDepthWidth-1:0] vWriteAddr;
wire [pDepthWidth-1:0] vReadAddr;
wire [pWordWidth-1:0] MemDataOut;
DualPortRAM_ASYN #(pDepthWidth, pWordWidth) Fifo_Storage (
// Generic synchronous two-port RAM interface
.WriteClock(iWClk),
.MemWEn (MemWEn),
.MemWAddr (vWriteAddr),
.MemDataIn (ivDataIn),
.ReadClock (iRClk),
.MemRAddr (vReadAddr),
.MemDataOut(MemDataOut)
);
FifoControl_ASYN #(pDepthWidth, pWordWidth) Fifo_Controller (
.inReset (inReset),
.WriteClock (iWClk),
.iWEn (iWEn),
.MemWEn (MemWEn),
.vWAddr (vWriteAddr),
.qWFull (qWFull),
.qvWCount (qvWCount),
.ReadClock (iRClk),
.iREn (iREn),
.vRAddr (vReadAddr),
.qREmpty (qREmpty),
.MemDataOut (MemDataOut),
.qvDataOut (ovDataOut),
.qvRNumberLeft(qvRNumberLeft)
);
endmodule
| 8.02377 |
module DualPortRAM_ASYN (
// Generic synchronous two-port RAM interface
WriteClock,
MemWEn,
MemWAddr,
MemDataIn,
ReadClock,
MemRAddr,
MemDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interface
input WriteClock;
input MemWEn;
input MemWAddr;
input MemDataIn;
input ReadClock;
input [pDepthWidth-1:0] MemRAddr;
output [pWordWidth-1:0] MemDataOut;
wire WriteClock;
wire MemWEn;
wire [pDepthWidth-1:0] MemWAddr;
wire [pWordWidth-1:0] MemDataIn;
wire ReadClock;
wire [pDepthWidth-1:0] MemRAddr;
wire [pWordWidth-1:0] MemDataOut;
reg [pWordWidth-1:0] mem[(1<<pDepthWidth)-1:0] /*synthesis syn_ramstyle="no_rw_check"*/;
// RAM read and write
// a port for write
always @(posedge WriteClock) if (MemWEn) mem[MemWAddr] <= MemDataIn;
// RAM read and write
//b for read
/* registered address */
reg [pDepthWidth-1:0] qvRAddr;
always @(posedge ReadClock) qvRAddr <= MemRAddr;
assign MemDataOut = mem[qvRAddr];
endmodule
| 8.984598 |
module or connected to the CODEC Core to
// form a complete SpaceWire Routing Switch (Router).
//Origin: SpaceWire Std - Draft-1(Clause 9/10) of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee
//-- TODO: make the rtl faster
////////////////////////////////////////////////////////////////////////////////////
//
/*synthesize translate_off*/
`timescale 1ns/10ps
/*synthesize translate_on */
`define reset 1 // WISHBONE standard reset
`define TOOL_NOTSUP_PORT_ARRAY //if the tools not support port array declaration
module SwitchCore #(parameter DW=10,PORTNUM=16,GPIO_NUM=3) // Actual 17 ==16 +1(external port)
( // Input data interface
output[PORTNUM-1:0] full_o,
`ifdef TOOL_NOTSUP_PORT_ARRAY
output [DW-1:0] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,
dout8,dout9,dout10,dout11,dout12,dout13,dout14,dout15, // Note that these is physical order.
input [DW-1:0] din0,din1,din2,din3,din4,din5,din6,din7, // eg. dout0 is routing logical port1
din8,din9,din10,din11,din12,din13,din14,din15, // because port0 is reserved for config
`else
output [DW-1:0] dout [PORTNUM-1:0],
input [DW-1:0] din [PORTNUM-1:0],
`endif
input [PORTNUM-1:0] wr_i,
// Output data interface
output [PORTNUM-1:0] empty_o,
input rd_i,
input active_i,
// GPIO ports
inout [GPIO_NUM-1:0] GPIO,
// global signal input
input reset, gclk // approximate 120Mhz, could also drive Xilinx gigabit transceiver.
);
// parameter ;
////////////////////
// Instantiation
//
SwitchMatrix #() inst_SwitchMatrix (
);
// 16 inputs Line Schedulers
// 1 scheduler is responsible to 1 input line, distribute data into one column
generate
begin:GEN_LSers
genvar i, k;
for (i=0; i<PORTNUM; i=i+1) // i : each column
begin
for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)
begin
LSer #() inst_LSer
( .ld_SelColumn_o( ld_SelColumn ),
.empty_i(CellEmpty[i][k] ), // one-hot input
.Aempty_i(CellAfull[i][k]), // one-hot
.addr_o( ScheOut[i] ),
.reset(reset)
.gclk(gclk)
);
end // end lines in a column
end // end columns
end
endgenerate
endmodule
| 8.201424 |
module SwitchData (
datainm,
datainf,
dataout,
clk,
rst_n,
over,
overout
);
input clk, rst_n, over;
input [31:0] datainm, datainf;
output overout;
output [31:0] dataout;
reg [31:0] dataout;
reg overout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dataout <= 16'd0;
end else if (over == 1) begin
if ((datainf > (datainm - 256)) && (datainf < (datainm + 256))) begin
dataout <= datainf;
end else begin
dataout <= datainm;
end
overout <= 1;
end else begin
dataout <= dataout;
overout <= 0;
end
end
endmodule
| 8.580228 |
module SwitchDB (
CLK,
SW,
ACLR_L,
SWDB
);
input CLK, SW, ACLR_L;
output reg SWDB;
wire aclr_i;
reg [1:0] Q_CURR;
parameter [1:0] SW_OFF = 2'b00; //Symbolic state definitions; Simple binary counting order
parameter [1:0] SW_EDGE = 2'b01;
parameter [1:0] SW_VERF = 2'b10;
parameter [1:0] SW_HOLD = 2'b11;
assign aclr_i = ~ACLR_L;
//State Memory
always @(posedge CLK or posedge aclr_i) begin
SWDB <= 1'b0; //SWDB is defaulted to 0
if (aclr_i) begin
Q_CURR <= SW_OFF;
end else begin
case (Q_CURR) //Set of cases that relate directly to State Diagram in Lab 3 Handout
SW_OFF:
if (SW) begin
Q_CURR <= SW_EDGE;
end else begin
Q_CURR <= SW_OFF;
end
SW_EDGE:
if (SW) begin
Q_CURR <= SW_VERF;
SWDB <= 1'b1; //Debounced signal only high when current state is SW_VERF
end else begin
Q_CURR <= SW_OFF;
end
SW_VERF: Q_CURR <= SW_HOLD;
SW_HOLD:
if (SW) begin
Q_CURR <= SW_HOLD;
end else begin
Q_CURR <= SW_OFF;
end
endcase
end
end
endmodule
| 8.192784 |
module switchDebouncer #(
parameter integer N = 16
) (
output reg switchOut,
input switchIn,
input clk
);
wire rst, add;
reg dFF1, dFF2;
reg [N-1:0] timeReg, nextReg;
assign rst = dFF1 ^ dFF2;
assign add = ~timeReg[N-1];
always @(rst, add, timeReg) begin
case ({
rst, add
})
2'b00: nextReg <= timeReg;
2'b01: nextReg <= timeReg + 1;
default: nextReg <= {N{1'b0}};
endcase
end
always @(posedge clk) begin
dFF1 <= switchIn;
dFF2 <= dFF1;
timeReg <= nextReg;
end
always @(posedge clk) begin
if (timeReg[N-1] == 1'b1) switchOut <= dFF2;
else switchOut <= switchOut;
end
endmodule
| 6.935528 |
module SwitchDriver (
switclk,
switchrst,
switchread,
switchctl,
switchaddr,
switchrdata,
switch_input
);
input switclk; // ʱź
input switchrst; // λź
input switchctl; // memorioswitchƬ !!!!!!!!!!
input [1:0] switchaddr; // switchģĵ??Ͷ !!!!!!!!!!!!!!!
input switchread; // controller
output [15:0] switchrdata; // ͵CPUIJ뿪???ע???ֻ16??
input [23:0] switch_input; // Ӱ϶24λ
reg [15:0] switchrdata;
always @(negedge switclk or posedge switchrst) begin
if (switchrst) begin
switchrdata <= 0;
end else if (switchctl && switchread) begin
if (switchaddr == 2'b00)
switchrdata[15:0] <= switch_input[15:0]; // data output,lower 16 bits non-extended
else if (switchaddr == 2'b10)
switchrdata[15:0] <= {
8'h00, switch_input[23:16]
}; //data output, upper 8 bits extended with zero
else switchrdata <= switchrdata;
end else begin
switchrdata <= switchrdata;
end
end
endmodule
| 7.534764 |
module SwitchEmu (
input clk,
input pulse_in,
output pulse_out
);
reg pulse_out_i = 1'b0;
reg [23:0] cnt_i = 24'h0;
assign pulse_out = pulse_out_i;
parameter Idle_st = 3'b001;
parameter Start_st = 3'b010;
parameter SwitchOn_st = 3'b100;
reg [2:0] st = Idle_st;
always @(posedge clk)
case (st)
Idle_st: begin
cnt_i <= 24'h0;
pulse_out_i <= 1'b0;
if (pulse_in) st <= Start_st;
else st <= Idle_st;
end
Start_st: begin
cnt_i <= 24'h0;
pulse_out_i <= 1'b0;
if (pulse_in) st <= Start_st;
else st <= SwitchOn_st;
end
SwitchOn_st: begin
cnt_i <= cnt_i + 24'h1;
pulse_out_i <= 1'b1;
if (cnt_i[23])
//if(cnt_i[8]) //For simulation
st <= Idle_st;
else st <= SwitchOn_st;
end
default: begin
cnt_i <= 24'h0;
pulse_out_i <= 1'b0;
st <= Idle_st;
end
endcase
endmodule
| 7.227526 |
module SwitchEncoder (
input [4:0] sw,
output reg [6:0] seg7
);
always @(sw)
if (sw == 5'b00001) seg7 = 7'h40;
else if (sw == 5'b00001) seg7 = 7'h79;
else if (sw == 5'b00100) seg7 = 7'h24;
else if (sw == 5'b01000) seg7 = 7'h30;
else if (sw == 5'b10000) seg7 = 7'h19;
else seg7 = 7'h7E;
endmodule
| 6.676161 |
module SwitchesToLEDs (
input i_Switch_1,
input i_Switch_2,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
);
assign o_LED_1 = i_Switch_1 & i_Switch_2; // AND gate
assign o_LED_2 = i_Switch_1 | i_Switch_2; // OR gate
assign o_LED_3 = ~(i_Switch_1 & i_Switch_2); // NAND gate
assign o_LED_4 = i_Switch_1 ^ i_Switch_2; // XOR gate
endmodule
| 7.42013 |
module SwitchesToLEDs_tb;
reg i_Switch_1;
reg i_Switch_2;
wire o_LED_1;
wire o_LED_2;
wire o_LED_3;
wire o_LED_4;
// Instantiating module to test
SwitchesToLEDs uut (
.i_Switch_1(i_Switch_1),
.i_Switch_2(i_Switch_2),
.o_LED_1(o_LED_1),
.o_LED_2(o_LED_2),
.o_LED_3(o_LED_3),
.o_LED_4(o_LED_4)
);
initial begin
// Define testbench behaviour
$dumpfile("SwitchesToLEDs_tb.vcd");
$dumpvars(0, SwitchesToLEDs_tb);
// Test conditions
for (integer i = 0; i < 4; i = i + 1) begin
{i_Switch_1, i_Switch_2} = i;
#10;
end
$display("Test completed!");
end
endmodule
| 7.42013 |
module switches_bus (
input sw0,
input sw1,
input sw2,
input sw3,
input sw4,
input sw5,
input sw6,
input sw7,
output [7:0] bus
);
assign bus[0] = sw0;
assign bus[1] = sw1;
assign bus[2] = sw2;
assign bus[3] = sw3;
assign bus[4] = sw4;
assign bus[5] = sw5;
assign bus[6] = sw6;
assign bus[7] = sw7;
endmodule
| 6.842316 |
module SwitchFreq (
select,
CLK,
clk
);
input select;
input CLK;
output reg clk;
wire clk1, clk2;
//assign clk = CLK;
divider_ #(2) divider1 (
.clk(CLK),
.parameterN(1),
.clk_N(clk1)
);
divider_ #(1000000) divider2 (
.clk(CLK),
.parameterN(1),
.clk_N(clk2)
);
always @(posedge CLK) begin
if (select) clk <= clk1;
else clk <= clk2;
end
endmodule
| 7.314714 |
module divider_ #(
parameter N = 100_000
) (
clk,
parameterN,
clk_N
);
input clk; // ϵͳʱ
input [3:0] parameterN; //Ƶ
output reg clk_N; // Ƶʱ
reg [31:0] counter; /* ͨʵַƵ
0(N/2-1)ʱ
ʱӷת */
initial begin
counter = 0;
clk_N = 0;
end
always @(posedge clk) begin // ʱ
if (counter == N * parameterN / 2 - 1) begin
counter = 0;
clk_N = ~clk_N;
end else counter = counter + 1;
end
endmodule
| 7.117642 |
module M_Median_Filter (
Clk,
Rst,
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
New_X0_P,
New_X1_P,
New_X2_P,
New_X3_P,
New_X4_P,
New_X5_P,
New_X6_P,
New_X7_P,
New_X8_P,
New_X0_S,
New_X1_S,
New_X2_S,
New_X3_S,
New_X4_S,
New_X5_S,
New_X6_S,
New_X7_S,
New_X8_S
);
input Clk, Rst;
input [7:0] X0, X1, X2, X3, X4, X5, X6, X7, X8;
output [7:0]New_X0_P,New_X1_P,New_X2_P,New_X3_P,New_X4_P,New_X5_P,New_X6_P,New_X7_P,New_X8_P;
output [7:0]New_X0_S,New_X1_S,New_X2_S,New_X3_S,New_X4_S,New_X5_S,New_X6_S,New_X7_S,New_X8_S;
wire [7:0] MV;
wire FS_0,FS_1,FS_2,FS_3,FS_4,FS_5,FS_6,FS_7,FS_8; // FS Value = 1 means Salt Noise Detected
wire FP_0,FP_1,FP_2,FP_3,FP_4,FP_5,FP_6,FP_7,FP_8; // FP Value = 1 means Pepper Noise Detected
wire [7:0] N_X0_P, N_X1_P, N_X2_P, N_X3_P, N_X4_P, N_X5_P, N_X6_P, N_X7_P, N_X8_P;
wire [7:0] N_X0_S, N_X1_S, N_X2_S, N_X3_S, N_X4_S, N_X5_S, N_X6_S, N_X7_S, N_X8_S;
wire [7:0] X4_MV;
wire [7:0] W0, W1, W2, W3, W4, W5, W6, W7, W8;
rof Sorting_Module (
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
MV,
W0,
W1,
W2,
W3,
W4,
W5,
W6,
W7,
W8
);
assign X4_MV = MV;
Main_Noise_Detector Noise_Detector (
X0,
X1,
X2,
X3,
X4_MV,
X5,
X6,
X7,
X8,
FS_0,
FS_1,
FS_2,
FS_3,
FS_4,
FS_5,
FS_6,
FS_7,
FS_8,
FP_0,
FP_1,
FP_2,
FP_3,
FP_4,
FP_5,
FP_6,
FP_7,
FP_8
);
M_Main_Noise_Removal Salt_Noise_Removal (
Clk,
X0,
X1,
X2,
X3,
X4_MV,
X5,
X6,
X7,
X8,
MV,
FS_0,
FS_1,
FS_2,
FS_3,
FS_4,
FS_5,
FS_6,
FS_7,
FS_8,
N_X0_S,
N_X1_S,
N_X2_S,
N_X3_S,
N_X4_S,
N_X5_S,
N_X6_S,
N_X7_S,
N_X8_S
);
Main_Switching_Stage Switching_Salt (
Clk,
Rst,
N_X0_S,
N_X1_S,
N_X2_S,
N_X3_S,
N_X4_S,
N_X5_S,
N_X6_S,
N_X7_S,
N_X8_S,
MV,
New_X0_S,
New_X1_S,
New_X2_S,
New_X3_S,
New_X4_S,
New_X5_S,
New_X6_S,
New_X7_S,
New_X8_S
);
M_Main_Noise_Removal Pepper_Noise_Removal (
Clk,
X0,
X1,
X2,
X3,
X4_MV,
X5,
X6,
X7,
X8,
MV,
FP_0,
FP_1,
FP_2,
FP_3,
FP_4,
FP_5,
FP_6,
FP_7,
FP_8,
N_X0_P,
N_X1_P,
N_X2_P,
N_X3_P,
N_X4_P,
N_X5_P,
N_X6_P,
N_X7_P,
N_X8_P
);
Main_Switching_Stage Switching_Peper (
Clk,
Rst,
N_X0_P,
N_X1_P,
N_X2_P,
N_X3_P,
N_X4_P,
N_X5_P,
N_X6_P,
N_X7_P,
N_X8_P,
MV,
New_X0_P,
New_X1_P,
New_X2_P,
New_X3_P,
New_X4_P,
New_X5_P,
New_X6_P,
New_X7_P,
New_X8_P
);
endmodule
| 6.835633 |
module M_Switching_Stage (
Clk,
Reset,
CV,
MV,
XX
);
input Clk, Reset;
input [7:0] CV, MV;
output [7:0] XX;
wire [7:0] AD;
wire F;
M_Thershold_Value SD0 (
Clk,
Reset,
CV,
MV,
AD
);
M_Thershold_Detector SD1 (
Clk,
AD,
F
);
Mux_2X1 SD2 (
MV,
CV,
F,
XX
);
endmodule
| 7.081628 |
module switching_generator //the switching generator
#(
parameter N,
M
) (
clk,
seed,
set,
out
);
input clk;
input set;
input [0:N + 3 * M - 1] seed;
output out;
reg [0:M * M - 1] M1;
reg [0:M * M - 1] M2;
wire [0:M * M - 1] data_trans_seed1;
wire [0:M * M - 1] data_trans_seed2;
wire data_ctrl;
matrix_power #(M, M) mp1 (
M1,
seed[N+M:N+2*M-1],
data_trans_seed1
);
matrix_power #(M, M) mp2 (
M2,
seed[N+2*M:N+3*M-1],
data_trans_seed2
);
control_unit #(N) cu_inst (
clk,
seed[0:N-1],
set,
data_ctrl
);
data_unit #(M) du_inst (
clk,
data_ctrl,
seed[N:N+M-1],
data_trans_seed1,
data_trans_seed2,
set,
out
);
endmodule
| 7.403493 |
module switching_latch (
input clk, // the system clock
input int_clk, // the interupt clock domain
input reset_n,
input trigger,
input ack,
output reg out
);
reg ack_clk_1; // Doing a 3 stage sync between the clock domains - Fuck I hate these.......
// But this "should" help with different clocks on both sides.
reg interupt_int_clk_1;
always @(posedge int_clk or negedge reset_n) begin
if (~reset_n) begin
interupt_int_clk_1 <= 'b0;
end else begin
if (trigger) interupt_int_clk_1 <= 1'b1;
else if (out) interupt_int_clk_1 <= 1'b0;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
out <= 'b0;
end else begin
if (interupt_int_clk_1) out <= 1'b1;
else if (ack) out <= 1'b0;
end
end
endmodule
| 8.237858 |
module SwitchInterface (
clk,
reset,
FirstScreen,
GameScreen,
Player1Wins,
Player2Wins,
sw,
color,
port_id,
write_strobe,
out_port,
in_port,
interrupt,
interrupt_ack,
player_screen,
led,
reset_plyrScrn,
mode
);
//inputs
input clk, reset;
input [11:0] FirstScreen;
input [11:0] GameScreen;
input [11:0] Player1Wins;
input [11:0] Player2Wins;
input [1:0] sw; // keyboard input
output reg [11:0] color;
input [7:0] port_id; // IO's for picoblaze
input write_strobe;
input [7:0] out_port;
output reg [7:0] in_port;
output reg interrupt;
input interrupt_ack;
input [1:0] player_screen; // selector for player 1 or 2 win screen
output reg [7:0] led;
output reg reset_plyrScrn; // resets player_screen signal
output [1:0] mode;
reg [1:0] screenout; // screen selector
assign mode = screenout; // Which mode for screen
//////////////// Interrupt acknowledg handler ////////////////////////////
always @(posedge clk) begin
if (interrupt_ack) interrupt <= 1'b0;
else if (player_screen > 2'd0 || sw > 2'd0) // player_screen changes or keyboard input changes, intiate interrupt
interrupt <= 1'b1;
else interrupt <= interrupt;
end
///////////////// IO's to Picoblaze //////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
color <= FirstScreen;
end else if (write_strobe) begin
case (port_id)
8'h02: led[7:0] <= out_port; //port address for lower 8 LED's
8'h03:
if (out_port >= 1'd1) screenout <= 2'b01; // game_screen selected
else color <= color;
8'h04:
if (out_port >= 1'd1) screenout <= 2'b10; // Player 1 wins selected
else color <= color;
8'h05:
if (out_port >= 1'd1) screenout <= 2'b11; // player 2 wins selected
else color <= color;
8'h06:
if (out_port >= 1'd1) screenout <= 2'b00; // First Screen selected
else screenout <= screenout;
default: color <= color;
endcase
end else begin
case (port_id)
8'h00: in_port <= sw; //port address for sw selected
8'h01: in_port <= player_screen; //port address for player_screen selected
default: ;
endcase
end
case (screenout)
2'b00: begin
reset_plyrScrn <= 1'd0; // first screen output
color <= FirstScreen;
end
2'b01: begin
reset_plyrScrn <= 1'd0; // game screen output
color <= GameScreen;
end
2'b10: begin
color <= Player1Wins; // Player 1 wins output
reset_plyrScrn <= 1'd1;
end
2'b11: begin
color <= Player2Wins; // Player 2 wins output
reset_plyrScrn <= 1'd1;
end
endcase
end
endmodule
| 7.571517 |
module SwitchPeripheral (
input CLK,
input RESET,
inout [7:0] BUS_DATA,
input [7:0] BUS_ADDR,
input BUS_WE,
input SWITCH_IN
);
parameter [7:0] SwitchBaseAddress = 8'hA8;
//Tristate
reg [7:0] Out;
reg SwitchBusWE;
//Only place data on the bus if the processor is NOT writing, and it is addressing the correct address
assign BUS_DATA = (SwitchBusWE) ? Out : 8'hZZ;
// Write to bus
always @(posedge CLK) begin
if (BUS_ADDR == SwitchBaseAddress) begin
if (BUS_WE) SwitchBusWE <= 1'b0;
else SwitchBusWE <= 1'b1;
end else SwitchBusWE <= 1'b0;
Out <= SWITCH_IN ? 8'h01 : 8'h00;
end
endmodule
| 8.73452 |
module SwitchReverseSignal (
SwiReverse,
KeySwi,
clk,
EditMode,
reset
);
output reg SwiReverse;
input KeySwi, clk, EditMode, reset;
reg [31:0] count;
reg [ 2:0] count2;
always @(posedge clk, negedge KeySwi, negedge reset) begin
if (~reset) begin
count <= 0;
count2 <= 0;
SwiReverse <= 0;
end else if (~KeySwi) begin
if (EditMode == 0) begin
count <= 0;
count2 <= 0;
end else begin
count <= 49_999_999 ? 0 : count + 1;
count2 <= (count < 49_999_999 || count2 == 2) ? count2 : count2 + 3'd1;
end
end else begin
count <= 0;
count2 <= 0;
SwiReverse <= count2 == 2 ? SwiReverse + 1'b1 : SwiReverse;
end
end
endmodule
| 6.989813 |
module SwitchSyncFIFO (
nReset,
iClk,
iWEn,
ivDataIn,
iREn,
ovDataOut,
qEmpty,
qFull,
qvCount
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input nReset;
input iClk;
input iWEn;
input [pWordWidth-1:0] ivDataIn;
input iREn;
output [pWordWidth-1:0] ovDataOut;
output qEmpty;
output qFull;
output [pDepthWidth:0] qvCount;
wire nReset;
wire iClk;
wire iWEn;
wire [pWordWidth-1:0] ivDataIn;
wire iREn;
wire [pWordWidth-1:0] ovDataOut_i;
wire qEmpty;
wire qFull;
wire [pDepthWidth:0] qvCount;
wire MemWEn;
wire MemREn;
wire [pDepthWidth-1:0] vWriteAddr;
wire [pDepthWidth-1:0] vReadAddr;
DualPortRAM #(pDepthWidth, pWordWidth) Fifo_Storage // Generic synchronous two-port RAM interface
(
.clock ( iClk ) ,
.MemWEn ( MemWEn ) ,
.qvWAddr ( vWriteAddr ) ,
.vDataIn ( ivDataIn ) ,
.qvRAddr ( vReadAddr ) ,
.vDataOut ( ovDataOut_i )
);
reg [pWordWidth-1:0] ovDataOut;
always @(posedge iClk)
if (MemREn) ovDataOut <= ovDataOut_i;
else ovDataOut <= 0;
FifoControl #(pDepthWidth) Fifo_Ctrl (
.Reset ( nReset ) ,
.clock ( iClk ) ,
.iWEn ( iWEn ) ,
.MemWEn ( MemWEn ) ,
.MemREn (MemREn),
.qvWAddr ( vWriteAddr ) ,
.iREn ( iREn ) ,
.qvRAddr ( vReadAddr ) ,
.qEmpty ( qEmpty ) ,
.qFull ( qFull ) ,
.qvCount ( qvCount )
);
endmodule
| 8.40197 |
module DualPortRAM (
clock,
MemWEn,
qvWAddr,
vDataIn,
qvRAddr,
vDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interface
input clock; // clock
input MemWEn; // write enable input
input [pDepthWidth-1:0] qvWAddr; // write address bus
input [pWordWidth-1:0] vDataIn; // input data bus
input [pDepthWidth-1:0] qvRAddr; // read address bus
output [pWordWidth-1:0] vDataOut; // output data bus
// Generic two-port synchronous RAM model
// Generic RAM's registers and wires
reg [pWordWidth-1:0] mem[(1<<pDepthWidth)-1:0] /*synthesis syn_ramstyle="no_rw_check"*/;
always @(posedge clock) if (MemWEn) mem[qvWAddr] <= vDataIn;
assign vDataOut = mem[qvRAddr];
endmodule
| 8.237962 |
module switch_2_tb();
localparam period = 2;
localparam max_test = 2000;
integer test_idx;
reg clk_r;
reg rst_r;
wire
fabric #(
.DATA_SIZE(4),
.ADDR_SIZE(1),
.ADDR(0),
.NODES_NUM(2),
.PACKS_TO_GEN(10),
.MAX_PACK_LEN(10)
) IP0 (
.clk (clk_r),
.a_rst (rst_r),
.data_i (data_ip_in [i]),
.data_o (data_ip_out[i]),
.out_w (out_w_ip_sw[i]),
.in_r (in_r_ip_sw [i]),
.out_r (out_r_ip_sw[i]),
.in_w (in_w_ip_sw [i])
);
fabric #(
.DATA_SIZE(4),
.ADDR_SIZE(1),
.ADDR(1),
.NODES_NUM(2),
.PACKS_TO_GEN(10),
.MAX_PACK_LEN(10)
) IP1 (
);
switch #(
) sw0 (
);
switch #(
) sw1 (
);
initial
begin
clk_r = 1'b0;
forever
#(period/2) clk_r = ~clk_r;
end
initial
begin
test_idx = 0;
rst_r = 1'b1;
#(10) rst_r = 1'b0;
end
always @(posedge clk_r)
begin
// if (test_idx == 10)
// $stop;
if (test_idx == max_test)
begin
$display("Test has been finished");
$finish;
end
test_idx = test_idx + 1;
end
endmodule
| 6.820912 |
module switch_4x4_tb ();
reg clk, rst;
always #25 clk = ~clk;
reg [31:0] input_word_1, input_word_2, input_word_3, input_word_4;
// wire [32:0] to_output_buf_1, to_output_buf_2, to_output_buf_3, to_output_buf_4;
switch_4x4 switch_4x4_instance (
.clk(clk),
.rst(rst),
.input_1(input_word_1),
.input_2(input_word_2),
.input_3(input_word_3),
.input_4(input_word_4)
);
initial begin
$dumpfile("switch_4x4_test.vcd");
$dumpvars(0, switch_4x4_tb);
#0 clk = 1'b0;
rst = 1'b1;
#20 rst = 1'b0;
input_word_1[31:24] = 8'd3;
input_word_1[23:8] = 16'd5;
input_word_1[7:0] = 8'd1;
#50 input_word_1 = 32'd32;
#50 input_word_1 = 32'd10;
#50 input_word_1 = 32'd7;
#50 input_word_1 = 32'd128;
#50 input_word_1 = 32'd200;
#50 input_word_1 = 32'd0;
input_word_2[31:24] = 8'd1;
input_word_2[23:8] = 16'd3;
input_word_2[7:0] = 8'd2;
#50 input_word_2 = 32'd119;
#50 input_word_2 = 32'd78;
#50 input_word_2 = 32'd43;
#600 $finish;
$display("tested");
end
endmodule
| 6.74646 |
module SWITCH_BCD (
CLK,
RESET,
DIP,
SEGMENT,
ENABLE
);
input CLK;
input RESET;
input [7:0] DIP;
output [7:0] SEGMENT;
output [5:0] ENABLE;
reg [23:0] DIVID;
reg [ 7:0] BCD;
reg [ 5:0] ENABLE;
reg [ 7:0] SEGMENT;
reg [ 3:0] DECODE;
wire [ 7:0] DIP1;
always @(posedge CLK or negedge RESET) begin
if (!RESET) DIVID <= 24'h000000;
else DIVID <= DIVID + 1'b1;
end
assign COUNT_CLK = DIVID[23];
assign SCAN_CLK = DIVID[11];
assign DIP1[3:0] = (DIP[3:0] > 4'h9) ? 4'h0 : DIP[3:0];
assign DIP1[7:4] = (DIP[7:4] > 4'h9) ? 4'h0 : DIP[7:4];
always @(posedge COUNT_CLK or negedge RESET) begin
begin
if (!RESET) BCD <= DIP1;
else begin
BCD <= BCD + 1'b1;
if (BCD[3:0] == 4'h9) begin
BCD[3:0] <= 4'h0;
BCD[7:4] <= BCD[7:4] + 1'b1;
end
if (BCD == 8'h99) BCD <= DIP1;
end
end
end
always @(posedge SCAN_CLK or negedge RESET) begin
if (!RESET) ENABLE <= 6'b111110;
else ENABLE <= {4'b1111, ENABLE[0], ENABLE[1]};
end
always @(ENABLE or BCD) begin
case (ENABLE)
6'b111110: DECODE = BCD[3:0];
default: DECODE = BCD[7:4];
endcase
end
always @(DECODE) begin
case (DECODE)
4'h0: SEGMENT = 8'b11000000;
4'h1: SEGMENT = 8'b11111001;
4'h2: SEGMENT = 8'b10100100;
4'h3: SEGMENT = 8'b10110000;
4'h4: SEGMENT = 8'b10011001;
4'h5: SEGMENT = 8'b10010010;
4'h6: SEGMENT = 8'b10000010;
4'h7: SEGMENT = 8'b11111000;
4'h8: SEGMENT = 8'b10000000;
4'h9: SEGMENT = 8'b10010000;
default: SEGMENT = 8'b11111111;
endcase
end
endmodule
| 7.05735 |
module Switch_Board (
input i_Clk,
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output [3:0] o_Buttons
);
reg [3:0] r_Buttons = 4'b0000;
reg r_Any_Switch = 1'b0;
wire w_Any_Switch;
wire w_Any_Switch_Filtered;
r_Any_Switch = i_Switch_1 || i_Switch_2 || i_Switch_3 || i_Switch_4;
// Debounce Filter
Debounce_Switch Debounce_Switch_1 (
.i_Clk(i_Clk),
.i_Switch(w_Any_Switch),
.o_Switch(w_Any_Switch_Filtered)
);
always @ (posedge i_Clk) begin
r_Any_Switch <= w_Any_Switch;
// Only output on the positive edge of button press
if (r_Any_Switch === 1'b0 && w_Any_Switch === 1'b1) begin
r_Buttons <= {i_Switch_1, i_Switch_2, i_Switch_3, i_Switch_4};
end else begin
r_Buttons <= 4'b0000;
end
end
assign o_Buttons = r_Buttons;
endmodule
| 7.345207 |
module switch_box_connector #(
parameter W0 = 5,
parameter W1 = 7
) (
input [W0-1:0] data0_in,
output [W0-1:0] data0_out,
input [W1-1:0] data1_in,
output [W1-1:0] data1_out
);
genvar i, j;
generate
for (i = 0; i < W0; i = i + 1) begin
assign data0_out[i] = data1_in[i%W1];
end
for (i = 0; i < W1; i = i + 1) begin
assign data1_out[i] = data0_in[i%W0];
end
endgenerate
endmodule
| 6.803101 |
module switch_box_connector_tb;
localparam W0 = 3;
localparam W1 = 10;
reg clk = 0;
always #10 clk = ~clk;
reg [W0-1:0] d0_in;
wire [W0-1:0] d0_out;
reg [W1-1:0] d1_in;
wire [W1-1:0] d1_out;
switch_box_connector #(
.W0(W0),
.W1(W1)
) dut (
.data0_in (d0_in),
.data1_in (d1_in),
.data0_out(d0_out),
.data1_out(d1_out)
);
integer count = 0;
wire [W0-1:0] valid0;
wire [W1-1:0] valid1;
genvar k;
generate
for (k = 0; k < W0; k = k + 1) begin
assign valid0[k] = d0_out[k] == d1_in[k%W1];
end
for (k = 0; k < W1; k = k + 1) begin
assign valid1[k] = d1_out[k] == d0_in[k%W0];
end
endgenerate
always @(posedge clk) begin
if (!(&valid0)) count = count + 1;
if (!(&valid1)) count = count + 1;
end
integer i;
initial begin
for (i = 0; i < 100; i = i + 1) begin
@(negedge clk);
d0_in = $random;
d1_in = $random;
end
@(negedge clk);
if (count == 0) $display("PASS");
else $display("FAIL %d", count);
$finish;
end
endmodule
| 6.803101 |
module Switch_Counter (
input i_Clk,
input i_Reset,
input i_Switch,
output [3:0] o_Nibble
);
reg r_Switch = 1'b0;
reg [3:0] r_Nibble = 4'h0;
always @(posedge i_Clk) begin
r_Switch <= i_Switch;
if (i_Reset) begin
r_Nibble <= 0;
end else if ((i_Switch == 1'b1) && (r_Switch == 1'b0)) begin
// Rising edge of i_Switch
if (r_Nibble == 9) r_Nibble <= 0;
else r_Nibble <= r_Nibble + 1;
end
end
assign o_Nibble = r_Nibble;
endmodule
| 6.569469 |
module SWITCH_DEBOUNCER #(
parameter BITS_NUM = 4,
parameter REPEAT_PRESC_CNT_MODULO = 100,
parameter REPEAT_START_DELAY = REPEAT_PRESC_CNT_MODULO - 1
) (
input CLK,
input CLR,
input CE,
input REP_CE,
input S_IN,
output KEY_EN,
output KEY_UP
);
reg [BITS_NUM-1:0] P_OUT;
wire repeat_presc_cnt_ceo;
wire key_up_loc;
wire key_up_repeat;
// Preskaler generatora repetycji.
DOWN_CNT #(
.MODULO (REPEAT_PRESC_CNT_MODULO),
.INIT_VAL(REPEAT_START_DELAY)
) repeat_presc_cnt (
.CLK(CLK),
.CLR(key_up_loc), // Resetowanie preskalera po nacisnieciu przycisku
.CE(REP_CE),
.CEO(repeat_presc_cnt_ceo)
);
always @(posedge CLK or posedge CLR) begin
if (CLR) P_OUT <= {BITS_NUM{1'b0}};
else begin
if (CE)
P_OUT <= {P_OUT[BITS_NUM-2:0], S_IN}; // Rejestr przesuwny do filtracji drgania stykow.
end
end
// Detekcja nacisniecia przycisku.
assign key_up_loc = ((&P_OUT[BITS_NUM-2:0]) & ~P_OUT[BITS_NUM-1] & CE);
// Sygnal repetycji.
assign key_up_repeat = ((&P_OUT[BITS_NUM-1:0]) & repeat_presc_cnt_ceo);
// Wypracowanie sygnalow wyjsciowych.
assign KEY_UP = (key_up_loc | key_up_repeat);
assign KEY_EN = (&P_OUT[BITS_NUM-1:0]);
endmodule
| 7.65145 |
module switch_decoder (
input [1:0] in,
output reg [3:0] out
);
always @* begin
case (in)
0: out = 4'b0001;
1: out = 4'b0010;
2: out = 4'b0100;
3: out = 4'b1000;
endcase
end
endmodule
| 7.014339 |
module switch_detect (
input CLK,
input RST,
input switch_in,
output detected
);
//Definition for Variables in the module
wire timer_on;
wire timer_start;
//Load other module(s)
edge_detect E1 (
.CLK(CLK),
.RST(RST),
.input_signal(switch_in),
.enable(~timer_on),
.detected(detected)
);
timer_20ms T1 (
.clk(CLK),
.RST(RST),
.start(timer_start),
.on(timer_on)
);
//Logical
assign timer_start = detected;
endmodule
| 7.889888 |
module, 2 ns period
switch_on: swith pushed on
------------------------------------------------------
History:
01-21-2016: First Version by Garfield
***********************************************/
`timescale 1 ns/100 ps
//Simulation time assignment
//Insert the modules
module switch_detect_press_test;
//defination for Variables
reg clk;
wire switch_in1, switch_in2;
wire switch_in;
reg[1:0] switch;
reg clk_switch;
reg switch_on;
reg reset;
wire detected;
wire[7:0] counter;
//Result for verification
//Connection to the modules
switch_short S1(.clk(clk_switch), .switch_on(switch_on),
.switch_out(switch_in1));
switch_long S2(.clk(clk_switch), .switch_on(switch_on),
.switch_out(switch_in2));
switch_detect_press S3 ( .CLK(clk), .RST(reset),
.switch_in(switch_in),
.detected(detected), .counter(counter)
);
begin
assign switch_in = (switch == 2'h1) ? (switch_in1) :
( (switch == 2'h2) ? (switch_in2) :(1'b1) );
//switch_on operation
initial
begin
switch_on = 1;
//Reset enable
#100 switch_on = 0;
//On in 100 ns
#20 switch_on = 1;
#30_000_000 #100 switch_on = 0;
//2nd switch on after 30ms
#20 switch_on = 1;
end
//switch_in operation
initial
begin
switch = 2'h1;
#30_000_000 switch = 2'h2;
//2nd switch on after 30ms
#50_000_000 switch<= 2'h0;
//2nd switch off after 50ms
end
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#100 clk = !clk;
//Reverse the clock in each 100ns
end
end
//Clock generation
initial
begin
clk_switch = 0;
//Reset
forever
begin
#1 clk_switch = !clk_switch;
//Reverse the clock in each 1ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
end
endmodule
| 6.753859 |
module, 2 ns period
switch_on: swith pushed on
------------------------------------------------------
History:
01-21-2016: First Version by Garfield
***********************************************/
`timescale 1 ns/100 ps
//Simulation time assignment
//Insert the modules
module switch_detect_test;
//defination for Variables
reg clk;
wire switch_in;
reg clk_switch;
reg switch_on;
reg reset;
wire detected;
//Result for verification
//Connection to the modules
switch S1(.clk(clk_switch), .switch_on(switch_on),
.switch_out(switch_in));
switch_detect S2 ( .CLK(clk), .RST(reset),
.switch_in(switch_in),
.detected(detected)
);
begin
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#100 clk = !clk;
//Reverse the clock in each 100ns
end
end
//Clock generation
initial
begin
clk_switch = 0;
//Reset
forever
begin
#1 clk_switch = !clk_switch;
//Reverse the clock in each 1ns
end
end
//Switch on simulation
initial
begin
switch_on = 1'b0;
//Reset
forever
begin
#200 switch_on = 1'b1;
#2 switch_on = 1'b0;
#200_000_000 switch_on = 1'b1;
//switch on per 200ms+
end
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
endmodule
| 6.753859 |
module switch_display (
input wire [3:0] KEY,
output wire [3:0] DIG,
output [7:0] SEG
);
// Atribuicao para os digitos do display de 7 segmentos
assign DIG = 4'b1110;
// Variavel com os dados a serem inseridos no display de 7 segmentos
reg [7:0] data_r;
always @(KEY) begin
case (KEY)
4'b1111: data_r = 8'b1100_0000; // 0
4'b1110: data_r = 8'b1111_1001; // 1
4'b1101: data_r = 8'b1010_0100; // 2
4'b1100: data_r = 8'b1011_0000; // 3
4'b1011: data_r = 8'b1001_1001; // 4
4'b1010: data_r = 8'b1001_0010; // 5
4'b1001: data_r = 8'b1000_0010; // 6
4'b1000: data_r = 8'b1111_1000; // 7
4'b0111: data_r = 8'b1000_0000; // 8
4'b0110: data_r = 8'b1001_0000; // 9
4'b0101: data_r = 8'b1000_1000; // A
4'b0100: data_r = 8'b1000_0011; // b
4'b0011: data_r = 8'b1100_0110; // C
4'b0010: data_r = 8'b1010_0001; // d
4'b0001: data_r = 8'b1000_0110; // E
4'b0000: data_r = 8'b1000_1110; // F
default: data_r = 8'b1111_1111; // OFF
endcase
end
// Escrever o conteudo de 'data_r' nos segmentos do display:
assign SEG = data_r;
endmodule
| 9.366303 |
module switch_driver (
input wire clk,
input wire [23:0] switch,
output reg [31:0] switch_data
);
always @(posedge clk) begin
switch_data <= switch;
end
endmodule
| 7.702861 |
module SWITCH_INPUT (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HREADY,
input wire HSEL,
output wire HREADYOUT,
output reg [31:0] HRDATA,
output wire SWITCH_IRQ,
input wire [14:0] SWITCH
);
reg rHSEL;
reg rHWRITE;
reg [1:0] rHTRANS;
reg [14:0] switch_reg;
// sequential part
assign SWITCH_IRQ = (switch_reg == SWITCH) ? 0 : 1;
assign HREADYOUT = 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
switch_reg <= 14'h0000;
end else begin
if (HSEL & !HWRITE) begin
HRDATA <= SWITCH;
switch_reg <= SWITCH;
end
end
end
endmodule
| 6.710742 |
module switch_key_ctrl (
input clk,
input reset,
input [3:0] keys,
input [3:0] switches,
output flipped,
output [7:0] readdata
);
wire [7:0] switch_key = {switches, keys};
reg [7:0] switch_key_reg;
reg [7:0] switch_key_flipped;
assign readdata = switch_key_reg;
assign flipped = (switch_key_flipped != 8'd0);
always @(posedge clk) begin
if (reset) begin
switch_key_reg <= 8'h0f;
switch_key_flipped <= 8'd0;
end else begin
switch_key_reg <= switch_key;
switch_key_flipped <= switch_key_reg ^ switch_key;
end
end
endmodule
| 7.625779 |
module switch_map (
output [31:0] data,
input [31:0] addr,
input [11:0] sw
);
assign en = addr[31:4] == 28'h0000ffe;
assign data = (en) ? {28'b0, data_out} : 32'bz;
reg [3:0] data_out;
always @(addr) begin
case (addr[3:0])
4'h0: data_out = sw[3:0];
4'h4: data_out = sw[7:4];
4'h8: data_out = sw[11:8];
endcase
end
endmodule
| 7.504168 |
module Switch_Matrix (
in,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7
, sel8,
sel9,
sel10,
sel11,
sel12,
sel13,
sel14,
sel15,
out
);
input [15:0] in;
input [3:0] sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7;
input [3:0] sel8, sel9, sel10, sel11, sel12, sel13, sel14, sel15;
output [15:0] out;
wire vcc;
assign vcc = 1'b1;
IO_cell output_0 (
.in (in),
.sel(sel0),
.oe (vcc),
.out(out[0])
);
IO_cell output_1 (
.in (in),
.sel(sel1),
.oe (vcc),
.out(out[1])
);
IO_cell output_2 (
.in (in),
.sel(sel2),
.oe (vcc),
.out(out[2])
);
IO_cell output_3 (
.in (in),
.sel(sel3),
.oe (vcc),
.out(out[3])
);
IO_cell output_4 (
.in (in),
.sel(sel4),
.oe (vcc),
.out(out[4])
);
IO_cell output_5 (
.in (in),
.sel(sel5),
.oe (vcc),
.out(out[5])
);
IO_cell output_6 (
.in (in),
.sel(sel6),
.oe (vcc),
.out(out[6])
);
IO_cell output_7 (
.in (in),
.sel(sel7),
.oe (vcc),
.out(out[7])
);
IO_cell output_8 (
.in (in),
.sel(sel8),
.oe (vcc),
.out(out[8])
);
IO_cell output_9 (
.in (in),
.sel(sel9),
.oe (vcc),
.out(out[9])
);
IO_cell output_10 (
.in (in),
.sel(sel10),
.oe (vcc),
.out(out[10])
);
IO_cell output_11 (
.in (in),
.sel(sel11),
.oe (vcc),
.out(out[11])
);
IO_cell output_12 (
.in (in),
.sel(sel12),
.oe (vcc),
.out(out[12])
);
IO_cell output_13 (
.in (in),
.sel(sel13),
.oe (vcc),
.out(out[13])
);
IO_cell output_14 (
.in (in),
.sel(sel14),
.oe (vcc),
.out(out[14])
);
IO_cell output_15 (
.in (in),
.sel(sel15),
.oe (vcc),
.out(out[15])
);
endmodule
| 6.632007 |
module switch_mode (
input wire clk,
input wire clkps2,
input wire dataps2,
output reg mode,
output reg vga,
output reg sdtest,
output reg flashtest,
output reg memtestf,
output reg memtests,
output reg mousetest,
output reg sdramtest,
output reg serialtest,
output reg hidetextwindow
);
wire key_event, released, extended;
wire [7:0] scancode;
ps2_port teclado (
.clk(clk), // se recomienda 1 MHz <= clk <= 600 MHz
.enable_rcv(1'b1), // habilitar la maquina de estados de recepcion
.kb_or_mouse(1'b0),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(key_event), // a 1 durante 1 clk para indicar nueva tecla recibida
.scancode(scancode), // make o breakcode de la tecla
.released(released), // soltada=1, pulsada=0
.extended(extended) // extendida=1, no extendida=0
);
initial begin
mode = 1'b1;
vga = 1'b1;
sdtest = 1'b0;
serialtest = 1'b0;
flashtest = 1'b0;
mousetest = 1'b0;
sdramtest = 1'b0;
hidetextwindow = 1'b0;
memtestf = 1'b0;
memtests = 1'b0;
end
always @(posedge clk) begin
sdtest <= 1'b0;
flashtest <= 1'b0;
mousetest <= 1'b0;
sdramtest <= 1'b0;
serialtest <= 1'b0;
memtestf <= 1'b0;
memtests <= 1'b0;
if (key_event == 1'b1) begin
if (scancode == 8'h29 && extended == 1'b0) // tecla SPACE
hidetextwindow <= ~released;
else if (extended == 1'b0 && released == 1'b1) begin
case (scancode)
8'h16, 8'h69: begin // tecla 1
mode <= 1'b0;
vga <= 1'b0;
end
8'h1E, 8'h72: begin // tecla 2
mode <= 1'b1;
vga <= 1'b0;
end
8'h26, 8'h7A: begin // tecla 3
mode <= 1'b1;
vga <= 1'b1;
end
8'h25,8'h6B: sdramtest <= 1'b1; // tecla 4
8'h2E,8'h73,8'h76: sdtest <= 1'b1; // tecla 5
8'h36,8'h74: flashtest <= 1'b1; // tecla 6
8'h3D,8'h6C: mousetest <= 1'b1; // tecla 7
//8'h3E,8'h75: serialtest <= 1'b1; // tecla 8
8'h3E, 8'h75: begin // tecla 8
memtestf <= 1'b1;
end
8'h46, 8'h7D: begin // tecla 9
memtests <= 1'b1;
end
endcase
end
end
end
endmodule
| 7.025622 |
module switch_mux (
input in0,
input in1,
input in2,
input in3,
input [1:0] sel,
output reg out
);
always @(in0 or in1 or in2 or in3 or sel)
case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
default: out = 2'b00;
endcase
endmodule
| 8.756739 |
module c_gate_0_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.08672 |
module latch_controller_1_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n1;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_0 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_5 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_5 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U4 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.033274 |
module latch_controller_1_5 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_5 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.046409 |
module latch_controller_1_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_4 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.34217 |
module latch_controller_1_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_3 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module sr_latch_0_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.553251 |
module c_gate_0_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.222928 |
module latch_controller_1_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_2 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 6.95665 |
module latch_controller_1_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_1 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_1_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.390817 |
module latch_controller_0_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n2;
assign Rout = Aout;
c_gate_1_0 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_1_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.498178 |
module latch_controller_0_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_1 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.665385 |
module c_gate_1_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.741961 |
module latch_controller_0_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_2 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_3 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.608477 |
module c_gate_1_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.685153 |
module latch_controller_0_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_3 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_4 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.598887 |
module c_gate_1_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.541928 |
module latch_controller_0_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_4 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module c_gate_0_6 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.291887 |
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