code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sum_rest_disp_p1 (
input [3:0] a,
input [3:0] b,
input sum_rest,
input clk,
output [6:0] disp,
output [3:0] transistor
);
wire [6:0] count;
wire [3:0] out;
wire [3:0] co;
wire mux_disp;
adder_subs i_adder_subs (
.a (a),
.b (b),
.sel(sum_rest),
.s (out),
.co (co[0])
);
decoder_7seg_4b i_decoder (
.in (mux_disp),
.out(disp)
);
soft_gtv i_soft_gtv (
.rst(0),
.clk(clk),
.spd_btn(0),
.mode(0),
.evnt(0),
.count(count)
);
mux_4_1_4b i_mux (
.a (a),
.b (b),
.c (co),
.d (out),
.sel(count[1:0]),
.z (mux_disp)
);
one_cold_2b_coder i_one_cold (
.en (1'b1),
.din (count[1:0]),
.dout(transistor)
);
endmodule
| 7.106596 |
module sum_sync_mem #(
parameter AWIDTH = 10,
parameter DWIDTH = 32,
parameter DEPTH = 1024,
parameter MEM_INIT_HEX_FILE = ""
) (
input clk,
input reset,
output done,
input [31:0] size,
output [31:0] sum
);
// TODO: Fill in the remaining logic to compute the sum of memory data from 0 to 'size'
// Note that in this case, memory read takes one cycle
wire [AWIDTH-1:0] rom_addr;
wire [DWIDTH-1:0] rom_rdata;
SYNC_ROM #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH),
.MEM_INIT_HEX_FILE(MEM_INIT_HEX_FILE)
) rom (
.addr(rom_addr),
.q(rom_rdata),
.clk(clk)
);
wire [31:0] index_reg_val, index_reg_next;
wire index_reg_rst, index_reg_ce;
REGISTER_R_CE #(
.N(32)
) index_reg (
.q (index_reg_val),
.d (index_reg_next),
.ce (index_reg_ce),
.rst(index_reg_rst),
.clk(clk)
);
wire [31:0] sum_reg_val, sum_reg_next;
wire sum_reg_rst, sum_reg_ce;
REGISTER_R_CE #(
.N(32)
) sum_reg (
.q (sum_reg_val),
.d (sum_reg_next),
.ce (sum_reg_ce),
.rst(sum_reg_rst),
.clk(clk)
);
endmodule
| 8.4127 |
module sum_sync_mem_tb ();
localparam AWIDTH = 10;
localparam DWIDTH = 32;
localparam DEPTH = 1024;
reg clk;
initial clk = 0;
always #(4) clk <= ~clk;
reg reset;
reg [31:0] size;
wire [DWIDTH-1:0] sum;
wire done;
sum_sync_mem #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH),
.MEM_INIT_HEX_FILE("sync_mem_init_hex.mif")
) dut (
.clk (clk),
.reset(reset),
.done (done),
.size (size),
.sum (sum)
);
// "Software" version
reg [31:0] test_vector[DEPTH-1:0];
integer sw_sum = 0;
integer i;
initial begin
#0;
$readmemh("sync_mem_init_hex.mif", test_vector);
#1; // advance one tick to make sure sw_sum get updated
for (i = 0; i < size; i = i + 1) begin
sw_sum = sw_sum + test_vector[i];
end
end
reg [31:0] cycle_cnt;
always @(posedge clk) begin
cycle_cnt <= cycle_cnt + 1;
if (done) begin
$display("At time %d, sum = %d, sw_sum = %d, done = %d, number of cycles = %d", $time, sum,
sw_sum, done, cycle_cnt);
if (sum == sw_sum) $display("TEST PASSED!");
else $display("TEST FAILED!");
$finish();
end
end
initial begin
#0;
reset = 0;
size = 1024;
cycle_cnt = 0;
repeat (10) @(posedge clk);
reset = 1;
@(posedge clk);
reset = 0;
repeat (5 * DEPTH) @(posedge clk);
$display("Timeout");
$finish();
end
endmodule
| 7.602181 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module sum_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[15:0] sum;
wire overflow;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
sum S1( .CLK(clk), .RST(reset),.data(out_num),
.sum(sum),.overflow_flag(overflow) );
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module P_to_BCD_8bit (
input [7:0] P,
output reg [3:0] BCD0,
BCD1,
BCD2
);
reg [7:0] PVar;
reg [3:0] B0, B1, B2;
always @(P) begin
PVar = P;
B0 = PVar % 8'b0000_1010;
PVar = PVar / 8'b0000_1010;
B1 = PVar % 8'b0000_1010;
PVar = PVar / 8'b0000_1010;
B2 = PVar;
BCD0 = B0;
BCD1 = B1;
BCD2 = B2;
end
endmodule
| 7.301694 |
module moduleName (
input clk,
input rst_n,
input vld,
input [15:0] data_in,
output reg [23:0] sum,
output reg done,
);
reg [23:0] sum_all;
reg vld_d1;
wire fallen_vld;
reg fallen_vld_d1;
reg [15:0] max;
reg [15:0] min;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sum_all <= 'd0;
else if(vld)
sum_all <= sum_all + {8'd0, data_in};
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
vld_d1 <= 'd0;
else
vld_d1 <= vld;
end
assign fallen_vld = !vld & vld_d1;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
fallen_vld_d1 <= 'd0;
else
fallen_vld_d1 <= fallen_vld;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
max <= 16'h0;
else if(vld & (data_in > max))
max <= data_in;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
min <= 16'hffff;
else if(vld & (data_in < min))
min <= data_in;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sum <= 'd0;
else if(fallen_vld)
sum <= sum_all - max;
else if(fallen_vld_d1)
sum <= sum - min;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
done <= 'd0;
else if(fallen_vld_d1)
done <= 1'd1;
else
done <= 'd0;
end
endmodule
| 8.443212 |
module inv (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.812163 |
module tri_inv (
input A,
input S,
output reg Y
);
always @(*) begin
if (S == 1'b0) begin
Y <= 1'bz;
end else begin
Y <= ~A;
end
end
endmodule
| 7.509959 |
module buffer (
input A,
output Y
);
assign Y = A;
endmodule
| 6.861394 |
module nand2 (
input A,
input B,
output Y
);
assign Y = ~(A & B);
endmodule
| 7.360689 |
module nor2 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.781479 |
module xor2 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.782532 |
module imux2 (
input A,
input B,
input S,
output Y
);
assign Y = ~(S ? A : B);
endmodule
| 9.412521 |
module dff (
input CLK,
input D,
input RESET,
input PRESET,
output reg Q,
output reg QN
);
always @(CLK or RESET or PRESET) begin
if (RESET) begin
Q <= 1'b0;
QN <= 1'b1;
end else if (PRESET) begin
Q <= 1'b1;
QN <= 1'b0;
end else if (CLK) begin
Q <= D;
QN <= ~D;
end
end
endmodule
| 7.174483 |
module aoi211 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A & B) | C);
endmodule
| 8.072296 |
module oai211 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A | B) & C);
endmodule
| 8.027893 |
module fulladder (
input A,
input B,
input CI,
output CO,
output Y
);
assign Y = (A ^ B) ^ CI;
assign CO = ((A & B) | (B & CI)) | (CI & A);
endmodule
| 7.454465 |
module superOS (
clk_clk,
led_export,
reset_reset_n
);
input clk_clk;
output [7:0] led_export;
input reset_reset_n;
endmodule
| 6.727399 |
module superOS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.202128 |
module superOS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
superOS_jtag_uart_sim_scfifo_w the_superOS_jtag_uart_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.202128 |
module superOS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.202128 |
module superOS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
superOS_jtag_uart_sim_scfifo_r the_superOS_jtag_uart_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.202128 |
module superOS_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "superOS_memory.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.982809 |
module arithmetic_logic_unit (
op,
alu1,
alu2,
bus
);
input [2:0] op;
input [15:0] alu1;
input [15:0] alu2;
output [15:0] bus;
assign bus = (op == `ADD) ? alu1 + alu2 : (op == `NAND) ? ~(alu1 & alu2) : alu2;
endmodule
| 6.612484 |
module IFID (
clk,
reset,
IFID_we,
IFID_instr__in,
IFID_pc__in,
IFID_instr__out,
IFID_pc__out
);
input clk, reset, IFID_we;
input [15:0] IFID_instr__in, IFID_pc__in;
output [15:0] IFID_instr__out, IFID_pc__out;
wire clk_A, clk_B, clk_C, clk_D, clk_E, clk_F, clk_G, clk_H,
res_A, res_B, res_C, res_D, res_E, res_F, res_G, res_H;
buf cA (
clk_A, clk
), cB (
clk_B, clk
), cC (
clk_C, clk
), cD (
clk_D, clk
), cE (
clk_E, clk
), cF (
clk_F, clk
), cG (
clk_G, clk
), cH (
clk_H, clk
), rA (
res_A, reset
), rB (
res_B, reset
), rC (
res_C, reset
), rD (
res_D, reset
), rE (
res_E, reset
), rF (
res_F, reset
), rG (
res_G, reset
), rH (
res_H, reset
);
registerX #(16) IFID_instr (
.reset(res_A),
.clk(clk_A),
.out(IFID_instr__out),
.in(IFID_instr__in),
.we(IFID_we)
);
registerX #(16) IFID_pc (
.reset(res_B),
.clk(clk_B),
.out(IFID_pc__out),
.in(IFID_pc__in),
.we(IFID_we)
);
endmodule
| 8.278578 |
module IDEX (
clk,
reset,
IDEX_op0__in,
IDEX_op1__in,
IDEX_op2__in,
IDEX_op__in,
IDEX_rT__in,
IDEX_x__in,
IDEX_pc__in,
IDEX_op0__out,
IDEX_op1__out,
IDEX_op2__out,
IDEX_op__out,
IDEX_rT__out,
IDEX_x__out,
IDEX_pc__out
);
input clk, reset;
input [15:0] IDEX_op0__in, IDEX_op1__in, IDEX_op2__in;
input [2:0] IDEX_op__in;
input [2:0] IDEX_rT__in;
output [15:0] IDEX_op0__out, IDEX_op1__out, IDEX_op2__out;
output [2:0] IDEX_op__out;
input [2:0] IDEX_rT__out;
input [15:0] IDEX_pc__in;
input IDEX_x__in;
output [15:0] IDEX_pc__out;
output IDEX_x__out;
wire clk_A, clk_B, clk_C, clk_D, clk_E, clk_F, clk_G, clk_H,
res_A, res_B, res_C, res_D, res_E, res_F, res_G, res_H;
buf cA (
clk_A, clk
), cB (
clk_B, clk
), cC (
clk_C, clk
), cD (
clk_D, clk
), cE (
clk_E, clk
), cF (
clk_F, clk
), cG (
clk_G, clk
), cH (
clk_H, clk
), rA (
res_A, reset
), rB (
res_B, reset
), rC (
res_C, reset
), rD (
res_D, reset
), rE (
res_E, reset
), rF (
res_F, reset
), rG (
res_G, reset
), rH (
res_H, reset
);
registerX #(16) IDEX_op0 (
.reset(res_A),
.clk(clk_A),
.out(IDEX_op0__out),
.in(IDEX_op0__in),
.we(1'd1)
);
registerX #(16) IDEX_op1 (
.reset(res_B),
.clk(clk_B),
.out(IDEX_op1__out),
.in(IDEX_op1__in),
.we(1'd1)
);
registerX #(16) IDEX_op2 (
.reset(res_C),
.clk(clk_C),
.out(IDEX_op2__out),
.in(IDEX_op2__in),
.we(1'd1)
);
registerX #(3) IDEX_op (
.reset(res_D),
.clk(clk_D),
.out(IDEX_op__out),
.in(IDEX_op__in),
.we(1'd1)
);
registerX #(3) IDEX_rT (
.reset(res_E),
.clk(clk_E),
.out(IDEX_rT__out),
.in(IDEX_rT__in),
.we(1'd1)
);
registerX #(1) IDEX_x (
.reset(res_F),
.clk(clk_F),
.out(IDEX_x__out),
.in(IDEX_x__in),
.we(1'd1)
);
registerX #(16) IDEX_pc (
.reset(res_G),
.clk(clk_G),
.out(IDEX_pc__out),
.in(IDEX_pc__in),
.we(1'd1)
);
endmodule
| 6.523922 |
module EXMEM (
clk,
reset,
EXMEM_stdata__in,
EXMEM_ALUout__in,
EXMEM_op__in,
EXMEM_rT__in,
EXMEM_x__in,
EXMEM_pc__in,
EXMEM_stdata__out,
EXMEM_ALUout__out,
EXMEM_op__out,
EXMEM_rT__out,
EXMEM_x__out,
EXMEM_pc__out
);
input clk, reset;
input [15:0] EXMEM_stdata__in, EXMEM_ALUout__in;
input [2:0] EXMEM_op__in;
input [2:0] EXMEM_rT__in;
output [15:0] EXMEM_stdata__out, EXMEM_ALUout__out;
output [2:0] EXMEM_op__out;
input [2:0] EXMEM_rT__out;
input [15:0] EXMEM_pc__in;
input EXMEM_x__in;
output [15:0] EXMEM_pc__out;
output EXMEM_x__out;
wire clk_A, clk_B, clk_C, clk_D, clk_E, clk_F, clk_G, clk_H,
res_A, res_B, res_C, res_D, res_E, res_F, res_G, res_H;
buf cA (
clk_A, clk
), cB (
clk_B, clk
), cC (
clk_C, clk
), cD (
clk_D, clk
), cE (
clk_E, clk
), cF (
clk_F, clk
), cG (
clk_G, clk
), cH (
clk_H, clk
), rA (
res_A, reset
), rB (
res_B, reset
), rC (
res_C, reset
), rD (
res_D, reset
), rE (
res_E, reset
), rF (
res_F, reset
), rG (
res_G, reset
), rH (
res_H, reset
);
registerX #(16) EXMEM_stdata (
.reset(res_A),
.clk(clk_A),
.out(EXMEM_stdata__out),
.in(EXMEM_stdata__in),
.we(1'd1)
);
registerX #(16) EXMEM_ALUout (
.reset(res_B),
.clk(clk_B),
.out(EXMEM_ALUout__out),
.in(EXMEM_ALUout__in),
.we(1'd1)
);
registerX #(3) EXMEM_op (
.reset(res_C),
.clk(clk_C),
.out(EXMEM_op__out),
.in(EXMEM_op__in),
.we(1'd1)
);
registerX #(3) EXMEM_rT (
.reset(res_D),
.clk(clk_D),
.out(EXMEM_rT__out),
.in(EXMEM_rT__in),
.we(1'd1)
);
registerX #(1) EXMEM_x (
.reset(res_E),
.clk(clk_E),
.out(EXMEM_x__out),
.in(EXMEM_x__in),
.we(1'd1)
);
registerX #(16) EXMEM_pc (
.reset(res_F),
.clk(clk_F),
.out(EXMEM_pc__out),
.in(EXMEM_pc__in),
.we(1'd1)
);
endmodule
| 6.790538 |
module SuperTopEntity ( // Inputs
input CLOCK // clock
, input RESET // asynchronous reset: active high
, input RX
, input SDO
, input BUTRST
// Output
, output wire MANRST
, output wire TX
, output wire [6:0] LED
, output wire CLK_OUT
, output wire [2:0] C1
, output wire [2:0] C2
, output wire [3:0] DATA
, output wire LAT
, output wire OE
, output wire CS_AG
, output wire CS_M
, output wire CS_ALT
, output wire SDI
, output wire SCK
, output wire INT
, output wire DRDY_M
, output wire PM1_0
, output wire PM1_2
, output wire PM1_5
, output wire PM1_7
);
wire LOCALRESET;
reg [3:0] counter;
reg DCLOCK;
assign LOCALRESET = RESET | BUTRST;
TopEntity main (
.CLOCK(DCLOCK),
.RESET(LOCALRESET),
.RX(RX),
.SDO(SDO),
.LED(LED),
.TX(TX),
.MANRST(MANRST),
.CS_AG(CS_AG),
.CS_M(CS_M),
.CS_ALT(CS_ALT),
.SDI(SDI),
.SCK(SCK),
.INT(INT),
.DRDY_M(DRDY_M),
.PM1_0(PM1_0),
.PM1_2(PM1_2),
.PM1_5(PM1_5),
.PM1_7(PM1_7),
.CLK_OUT(CLK_OUT),
.C1(C1),
.C2(C2),
.DATA(DATA),
.LAT(LAT),
.OE(OE)
);
always @(posedge CLOCK) begin
if (counter == 4) begin
counter <= 0;
DCLOCK <= !DCLOCK;
end else counter <= counter + 1;
end
initial begin
counter <= 15;
DCLOCK <= 0;
end
endmodule
| 7.49293 |
module super_display (
input clk,
input rst,
input [3:0] sel_in,
input [15:0] dat,
output [3:0] sel,
output [7:0] c
);
//reg [15:0] data;
integer counter;
reg [3:0] temp_data;
reg [3:0] temp_sel;
reg [1:0] state;
parameter freq = 10000000;
localparam bond = freq / 1000;
always @(posedge clk) begin
if (rst) begin
counter <= 0;
state <= 0;
//data[15:0] <= 16'h1034;
end else begin
counter <= counter + 1'b1;
if (counter == bond) begin
counter <= 0;
state <= state + 2'b1;
end
end
end
always @(*) begin
case (state[1:0])
2'b00: begin
temp_sel[3:0] <= 4'b1110;
temp_data[3:0] <= dat[3:0];
end
2'b01: begin
temp_sel[3:0] <= 4'b1101;
temp_data[3:0] <= dat[7:4];
end
3'b10: begin
temp_sel[3:0] <= 4'b1011;
temp_data[3:0] <= dat[11:8];
end
4'b11: begin
temp_sel[3:0] <= 4'b0111;
temp_data[3:0] <= dat[15:12];
end
endcase
end
assign sel[3:0] = temp_sel[3:0] | ~sel_in[3:0];
display display1 (
.d(temp_data[3:0]),
.c(c[7:0])
);
endmodule
| 8.32471 |
module display_HEX (
input [3:0] S,
output [6:0] H
);
assign H[0] = ~S[3]&~S[2]&~S[1]&S[0] | ~S[3]&S[2]&~S[1]&~S[0] | S[3]&~S[2]&S[1]&S[0] | S[3]&S[2]&~S[1]&S[0];
assign H[1] = ~S[3]&S[2]&~S[1]&S[0] | ~S[3]&S[2]&S[1]&~S[0] | S[3]&~S[2]&S[1]&S[0] | S[3]&S[2]&~S[1]&~S[0] | S[3]&S[2]&S[1];
assign H[2] = ~S[3] & ~S[2] & S[1] & ~S[0] | S[3] & S[2] & ~S[1] & ~S[0] | S[3] & S[2] & S[1];
assign H[3] = ~S[3]&~S[2]&~S[1]&S[0] | ~S[3]&S[2]&~S[1]&~S[0] | ~S[3]&S[2]&S[1]&S[0] | S[3]&~S[2]&~S[1]&S[0] | S[3]&~S[2]&S[1]&~S[0] | S[3]&S[2]&S[1]&S[0];
assign H[4] = ~S[3]&S[2]&~S[1] | ~S[3]&~S[2]&S[0] | ~S[3]&S[2]&S[1]&S[0] | S[3]&~S[2]&~S[1]&S[0];
assign H[5] = ~S[3]&~S[2]&S[0] | ~S[3]&~S[2]&S[1]&~S[0] | ~S[3]&S[2]&S[1]&S[0] | S[3]&S[2]&~S[1]&S[0];
assign H[6] = ~S[3] & ~S[2] & ~S[1] | ~S[3] & S[2] & S[1] & S[0] | S[3] & S[2] & ~S[1] & ~S[0];
endmodule
| 6.533988 |
module super_stop_watch_test (
output [3:0] en0,
en1,
output [7:0] sseg0,
sseg1,
input [31:0] show_data,
input clk
);
scan_hex_led_disp scan_hex_led_disp_unit0 (
.clk(clk),
.reset(1'b0),
.hex3(show_data[15:12]),
.hex2(show_data[11:8]),
.hex1(show_data[7:4]),
.hex0(show_data[3:0]),
.dp(4'b0100),
.en(en0),
.sseg(sseg0)
);
scan_hex_led_disp scan_hex_led_disp_unit1 (
.clk(clk),
.reset(1'b0),
.hex3(show_data[31:28]),
.hex2(show_data[27:24]),
.hex1(show_data[23:20]),
.hex0(show_data[19:16]),
.dp(4'b0101),
.en(en1),
.sseg(sseg1)
);
endmodule
| 6.815538 |
module super_top_level (
input clk,
input btns,
input btnu,
input btnl,
input btnd,
input btnr,
input rst,
input [3:0] sw,
input SDI,
output [7:0] Led,
output [2:0] vgaRed,
output [2:0] vgaGreen,
output [2:1] vgaBlue,
output Hsync,
output Vsync,
output SDO,
SS,
SCLK,
output [15:0] x_final,
y_final,
z_final,
output [3:0] an,
output [6:0] seg,
inout [3:0] JA,
output [7:0] toLEDs
);
wire [9:0] w_feed_x, w_feed_y, w_feed_z;
top_level degreeFeed (
.JA(JA),
.SDI(SDI),
.SDO(SDO),
.SS(SS),
.SCLK(SCLK),
.x_final(x_final),
.y_final(y_final),
.z_final(z_final),
.clk(clk),
.rst(rst),
.sw(sw),
.an(an),
.seg(seg)
);
draw_lines_top drawLine (
.clk(clk),
.btns(btns),
.btnu(btnu),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.x_feed(x_final),
.y_feed(y_final),
.z_feed(z_final),
.Led(Led),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue),
.Hsync(Hsync),
.Vsync(Vsync),
.toLEDs(toLEDs)
);
endmodule
| 7.502277 |
module test;
supply0 gnd;
supply1 vdd;
initial begin
#1;
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
| 6.553995 |
module test;
supply0 gnd;
supply1 vdd;
// These should drop away as meaningless.
assign gnd = 1;
assign vdd = 0;
initial begin
#1
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
| 6.553995 |
module rom2764 #(
parameter INIT_FILE = "rom.txt"
) (
input clk,
input [12:0] addr,
output reg [7:0] data
);
reg [7:0] mem[0:8191];
always @(posedge clk) data <= mem[addr];
initial begin
$readmemh(INIT_FILE, mem);
end
endmodule
| 7.756638 |
module dprom2764 (
input a_clk,
input [12:0] a_addr,
output reg [7:0] a_data,
input b_clk,
b_we,
input [12:0] b_addr,
input [7:0] b_data
);
reg [7:0] mem[0:8191];
always @(posedge a_clk) a_data <= mem[a_addr];
always @(posedge b_clk) if (b_we) mem[b_addr] <= b_data;
endmodule
| 7.213826 |
module sram (
input clk,
input we,
input [10:0] addr,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem[0:2047];
always @(posedge clk) begin
if (we) mem[addr] <= din;
else dout <= mem[addr];
end
endmodule
| 7.547687 |
module moram (
input clk,
input we,
cs,
input [7:0] addr,
input [3:0] din,
output reg [3:0] dout
);
reg [3:0] mem[0:255];
always @(posedge clk) begin
if (we & cs) mem[addr] <= din;
else dout <= mem[addr];
end
endmodule
| 7.193837 |
module cram82S09 (
input clk,
input we,
input [4:0] addr,
input [8:0] din,
output reg [8:0] dout
);
reg [8:0] mem[0:31];
always @(posedge clk) begin
if (we) mem[addr] <= din;
else dout <= mem[addr];
end
initial begin
$readmemh("cram.rom", mem); // initial colors at boot
end
endmodule
| 7.026823 |
module PokeyW (
input clk,
input ce,
input rst_n,
input [3:0] ad,
input cs,
input we,
input [7:0] data_to_pokey,
output [7:0] data_from_pokey,
output [5:0] snd,
input [7:0] p
);
wire [3:0] ch0, ch1, ch2, ch3;
pokey core (
.reset_n(rst_n),
.clk(clk),
.ce(ce),
.addr(ad),
.data_in(data_to_pokey),
.data_out(data_from_pokey),
.wr_en(we & cs),
.enable_179(1'b1),
.pot_in(~p),
.channel_0_out(ch0),
.channel_1_out(ch1),
.channel_2_out(ch2),
.channel_3_out(ch3)
);
assign snd = {2'b00, ch0} + {2'b00, ch1} + {2'b00, ch2} + {2'b00, ch3};
endmodule
| 7.366478 |
module LETA (
input clk,
reset_n,
input X1,
Y1,
X2,
Y2,
X3,
Y3,
X4,
Y4,
input [1:0] addr,
output reg [7:0] data
);
wire [7:0] data1, data2, data3, data4;
quad_decoder qd1 (
.clk(clk),
.reset_n(reset_n),
.A(X1),
.B(Y1),
.count(data1)
);
quad_decoder qd2 (
.clk(clk),
.reset_n(reset_n),
.A(X2),
.B(Y2),
.count(data2)
);
quad_decoder qd3 (
.clk(clk),
.reset_n(reset_n),
.A(X3),
.B(Y3),
.count(data3)
);
quad_decoder qd4 (
.clk(clk),
.reset_n(reset_n),
.A(X4),
.B(Y4),
.count(data4)
);
always @(posedge clk) begin
case (addr)
2'b00: data = data1;
2'b01: data = data2;
2'b10: data = data3;
2'b11: data = data4;
endcase
end
endmodule
| 6.640609 |
module surf4_debug(
input wbc_clk_i,
input clk0_i,
input clk1_i,
`WBM_NAMED_PORT(wbvio, 32, 20, 4),
input [70:0] wbc_debug_i,
input [70:0] ice_debug_i,
input [70:0] lab4_i2c_debug_i,
input [23:0] i2c_debug_i,
input [70:0] rfp_debug_i,
output [7:0] global_debug_o
);
reg [70:0] ila0_debug = {71{1'b0}};
reg [70:0] ila1_debug = {71{1'b0}};
wire [63:0] vio_sync_in;
wire [47:0] vio_sync_out;
wire [31:0] bridge_dat_o = vio_sync_in[0 +: 32];
wire [19:0] bridge_adr_o = vio_sync_in[32 +: 20];
wire bridge_we_o = vio_sync_in[52];
wire bridge_go_o = vio_sync_in[53];
wire bridge_lock_o = vio_sync_in[54];
// vio_sync_in[63:54] are available for debug multiplexing
wire [1:0] ila0_sel = vio_sync_in[56:55];
wire [31:0] bridge_dat_i;
wire bridge_done_i;
wire bridge_err_i;
assign vio_sync_out[0 +: 32] = bridge_dat_i;
assign vio_sync_out[32] = bridge_done_i;
assign vio_sync_out[33] = bridge_err_i;
// vio_sync_out[47:34] are available for... something
wbvio_bridge u_bridge(.clk_i(wbc_clk_i),.rst_i(1'b0),
.wbvio_dat_i(bridge_dat_o),
.wbvio_adr_i(bridge_adr_o),
.wbvio_we_i(bridge_we_o),
.wbvio_go_i(bridge_go_o),
.wbvio_lock_i(bridge_lock_o),
.wbvio_dat_o(bridge_dat_i),
.wbvio_done_o(bridge_done_i),
.wbvio_err_o(bridge_err_i),
.cyc_o(wbvio_cyc_o),
.stb_o(wbvio_stb_o),
.we_o(wbvio_we_o),
.dat_i(wbvio_dat_i),
.dat_o(wbvio_dat_o),
.adr_o(wbvio_adr_o),
.ack_i(wbvio_ack_i),
.err_i(wbvio_err_i),
.rty_i(wbvio_rty_i)
);
always @(posedge clk0_i) begin
if (ila0_sel[1:0] == 2'b01) ila0_debug <= rfp_debug_i;
else if (ila0_sel[1:0] == 2'b11) begin
ila0_debug[50:0] <= lab4_i2c_debug_i[50:0];
ila0_debug[51] <= i2c_debug_i[0];
ila0_debug[52] <= i2c_debug_i[12];
ila0_debug[53] <= i2c_debug_i[1];
ila0_debug[54] <= i2c_debug_i[13];
end
else ila0_debug <= wbc_debug_i;
end
always @(posedge clk1_i) begin
ila1_debug <= ice_debug_i;
end
wire [35:0] vio_control;
wire [35:0] ila0_control;
wire [35:0] ila1_control;
surf4_icon u_icon(.CONTROL0(vio_control),.CONTROL1(ila0_control),.CONTROL2(ila1_control));
surf4_ila u_ila0(.CONTROL(ila0_control),.CLK(clk0_i),.TRIG0(ila0_debug));
surf4_ila u_ila1(.CONTROL(ila1_control),.CLK(clk1_i),.TRIG0(ila1_debug));
surf4_vio u_vio(.CONTROL(vio_control),.CLK(wbc_clk_i),.SYNC_IN(vio_sync_out),.SYNC_OUT(vio_sync_in),
.ASYNC_OUT(global_debug_o));
endmodule
| 7.414675 |
module surf4_hk_collector(
input clk_i,
input rst_i,
`WBS_NAMED_PORT(wbsc, 32, 16, 4),
`WBM_NAMED_PORT(wbmc, 32, 20, 4),
input pps_i,
// external ports (MGT_1V/MGT_VTT)
input MGT1V_P,
input MGT1V_N,
input MGT1P2_P,
input MGT1P2_N
);
// The HK collector handles housekeeping stuff. It's called a
// "collector" because a PicoBlaze processor will read all of the
// housekeeping from all of the modules (and the internal XADC stuff)
// and write them into a housekeeping buffer which can be DMA'd either
// to the TURF or to the PCI bus.
// First simple sketch: connect the XADC block to the WISHBONE bus.
// We have a 14-bit 32-bit address space [15:2]. Reserve
// address [15:9] = 7'h00 for random control registers or something.
// Probably also allow for reprogramming the PicoBlaze
// via the control bus.
// address [15:9] = 7'h01 for the XADC.
// address [15:9] = 7'h08-7'h7F for the housekeeping buffer.
wire sel_control = (wbsc_adr_i[15:9] == 7'h00);
wire sel_xadc = (wbsc_adr_i[15:9] == 7'h01);
wire sel_buffer = (wbsc_adr_i[15:9] == 7'h02);
wire [15:0] xadc_data_in = wbsc_dat_i[15:0];
wire [15:0] xadc_data_out;
wire [6:0] xadc_addr = wbsc_adr_i[8:2];
wire xadc_en;
wire xadc_we;
wire xadc_ack;
assign xadc_en = (wbsc_cyc_i && wbsc_stb_i && sel_control);
assign xadc_we = wbsc_we_i;
wire [15:0] xadc_vaux_p;
assign xadc_vaux_p[15:11] = {5{1'b0}};
assign xadc_vaux_p[10] = MGT1P2_P;
assign xadc_vaux_p[9:0] = {10{1'b0}};
wire [15:0] xadc_vaux_n;
assign xadc_vaux_n[15:11] = {5{1'b0}};
assign xadc_vaux_n[10] = MGT1P2_N;
assign xadc_vaux_n[9:0] = {10{1'b0}};
XADC u_xadc(.DADDR(xadc_addr),
.DCLK(clk_i),
.DEN(xadc_en),
.DI(xadc_data_in),
.DO(xadc_data_out),
.RESET(rst_i),
.DRDY(xadc_ack),
.DWE(xadc_we),
.VP(MGT1V_P),
.VN(MGT1V_N),
.VAUXP(xadc_vaux_p),
.VAUXN(xadc_vaux_n));
// Control register section.
wire [31:0] ctrl_dat_o;
wire ctrl_ack;
// just kill it for now
assign ctrl_dat_o = {32{1'b0}};
assign ctrl_ack = wbsc_cyc_i && wbsc_stb_i && sel_control;
// Buffer section
wire [31:0] buf_dat_o;
wire buf_ack;
// just kill it for now
assign buf_dat_o = {32{1'b0}};
assign buf_ack = wbsc_cyc_i && wbsc_stb_i && sel_control;
///////////////////////////////////////////////
// WISHBONE slave port muxing.
///////////////////////////////////////////////
reg [31:0] wbsc_dat_out_muxed;
reg wbsc_ack_muxed;
always @(*) begin
if (sel_control) wbsc_dat_out_muxed <= ctrl_dat_o;
else if (sel_xadc) wbsc_dat_out_muxed <= xadc_data_out;
else wbsc_dat_out_muxed <= buf_dat_o;
end
always @(*) begin
if (sel_control) wbsc_ack_muxed <= ctrl_ack;
else if (sel_xadc) wbsc_ack_muxed <= xadc_ack;
else wbsc_ack_muxed <= buf_ack;
end
assign wbsc_dat_o = wbsc_dat_out_muxed;
assign wbsc_ack_o = wbsc_ack_muxed;
assign wbsc_err_o = 0;
assign wbsc_rty_o = 0;
///////////////////////////////////////////////
// WISHBONE master port.
///////////////////////////////////////////////
// Just kill it for now.
`WB_KILL(wbmc, 32, 20, 4);
endmodule
| 9.000491 |
module: surf4_id_ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "wishbone.vh"
module surf4_id_ctrl_tb;
// Inputs
reg clk_i;
reg rst_i;
`WB_DEFINE(wb, 32, 16, 4);
wire pci_interrupt_o;
wire [30:0] interrupt_i;
wire pps_o;
wire pps_sysclk_o;
wire ext_trig_o;
wire ext_trig_sysclk_o;
wire [11:0] internal_led_i;
reg PPS = 0;
reg EXT_TRIG = 0;
wire MOSI;
reg MISO = 0;
wire CS_B;
wire ICE40_RESET;
wire [3:0] LED;
wire FP_LED;
reg LOCAL_CLK = 0;
wire LOCAL_OSC_EN;
wire FPGA_SST_SEL;
wire FPGA_SST;
reg FPGA_TURF_SST = 0;
// Instantiate the Unit Under Test (UUT)
surf4_id_ctrl uut (
.clk_i(clk_i),
.rst_i(rst_i),
`WBS_CONNECT(wb, wb),
.pci_interrupt_o(pci_interrupt_o),
.interrupt_i(interrupt_i),
.pps_o(pps_o),
.pps_sysclk_o(pps_sysclk_o),
.ext_trig_o(ext_trig_o),
.ext_trig_sysclk_o(ext_trig_sysclk_o),
.internal_led_i(internal_led_i),
.PPS(PPS),
.EXT_TRIG(EXT_TRIG),
.MOSI(MOSI),
.MISO(MISO),
.CS_B(CS_B),
.ICE40_RESET(ICE40_RESET),
.LED(LED),
.FP_LED(FP_LED),
.LOCAL_CLK(LOCAL_CLK),
.LOCAL_OSC_EN(LOCAL_OSC_EN),
.FPGA_SST_SEL(FPGA_SST_SEL),
.FPGA_SST(FPGA_SST),
.FPGA_TURF_SST(FPGA_TURF_SST)
);
always begin
#15 clk_i = ~clk_i;
end
initial begin
// Initialize Inputs
clk_i = 0;
rst_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@(posedge clk_i);
end
endmodule
| 7.482888 |
module surf5_debug(
input wbc_clk_i,
input clk0_i,
input clk1_i,
input clk_big_i,
`WBM_NAMED_PORT(wbvio, 32, 20, 4),
input [70:0] clk0_debug0_i,
input [70:0] clk0_debug1_i,
input [70:0] clk0_debug2_i,
input [70:0] clk0_debug3_i,
input [70:0] clk1_debug_i,
input [14:0] clk_big_debug_i,
output [7:0] global_debug_o,
input [7:0] global_debug_i
);
wire [70:0] ila0_debug_vec[3:0];
assign ila0_debug_vec[0] = clk0_debug0_i;
assign ila0_debug_vec[1] = clk0_debug1_i;
assign ila0_debug_vec[2] = clk0_debug2_i;
assign ila0_debug_vec[3] = clk0_debug3_i;
reg [70:0] ila0_debug = {71{1'b0}};
reg [70:0] ila1_debug = {71{1'b0}};
wire [63:0] vio_sync_in;
wire [47:0] vio_sync_out;
wire [31:0] bridge_dat_o = vio_sync_in[0 +: 32];
wire [19:0] bridge_adr_o = vio_sync_in[32 +: 20];
wire bridge_we_o = vio_sync_in[52];
wire bridge_go_o = vio_sync_in[53];
wire bridge_lock_o = vio_sync_in[54];
// vio_sync_in[63:54] are available for debug multiplexing
wire [1:0] ila0_sel = vio_sync_in[56:55];
wire [31:0] bridge_dat_i;
wire bridge_done_i;
wire bridge_err_i;
assign vio_sync_out[0 +: 32] = bridge_dat_i;
assign vio_sync_out[32] = bridge_done_i;
assign vio_sync_out[33] = bridge_err_i;
// vio_sync_out[47:34] are available for... something
assign vio_sync_out[47:40] = global_debug_i;
wbvio_bridge u_bridge(.clk_i(wbc_clk_i),.rst_i(1'b0),
.wbvio_dat_i(bridge_dat_o),
.wbvio_adr_i(bridge_adr_o),
.wbvio_we_i(bridge_we_o),
.wbvio_go_i(bridge_go_o),
.wbvio_lock_i(bridge_lock_o),
.wbvio_dat_o(bridge_dat_i),
.wbvio_done_o(bridge_done_i),
.wbvio_err_o(bridge_err_i),
.cyc_o(wbvio_cyc_o),
.stb_o(wbvio_stb_o),
.we_o(wbvio_we_o),
.dat_i(wbvio_dat_i),
.dat_o(wbvio_dat_o),
.adr_o(wbvio_adr_o),
.ack_i(wbvio_ack_i),
.err_i(wbvio_err_i),
.rty_i(wbvio_rty_i)
);
always @(posedge clk0_i) begin
ila0_debug <= ila0_debug_vec[ila0_sel[1:0]];
end
always @(posedge clk1_i) begin
ila1_debug <= clk1_debug_i;
end
wire [35:0] vio_control;
wire [35:0] ila0_control;
wire [35:0] ila1_control;
wire [35:0] big_ila_control;
surf5_icon u_icon(.CONTROL0(vio_control),.CONTROL1(ila0_control),.CONTROL2(ila1_control),.CONTROL3(big_ila_control));
surf5_ila u_ila0(.CONTROL(ila0_control),.CLK(clk0_i),.TRIG0(ila0_debug));
surf5_ila u_ila1(.CONTROL(ila1_control),.CLK(clk1_i),.TRIG0(ila1_debug));
surf5_big_ila u_big_ila(.CONTROL(big_ila_control),.CLK(clk_big_i),.TRIG0(clk_big_debug_i));
surf5_vio u_vio(.CONTROL(vio_control),.CLK(wbc_clk_i),.SYNC_IN(vio_sync_out),.SYNC_OUT(vio_sync_in),
.ASYNC_OUT(global_debug_o));
endmodule
| 7.59826 |
module surf5_phase_scanner(
input clk_i,
input rst_i,
`WBS_NAMED_PORT(wb, 32, 1, 4),
output ps_en_o,
output ps_incdec_o,
input ps_done_i,
input sync_i,
input clk_ps_i,
inout sync_mon_io,
input [11:0] MONTIMING_B,
output [11:0] montiming_q_o,
output sync_q_o,
output scan_valid_o,
output scan_done_o
);
// simple phase scanner, no picoblaze, just ChipScope
// Our clock is 12.5 MHz, or 1/80th of the input clock of 1 GHz.
// There are 56 steps, so that means we have 4480 steps.
localparam [12:0] PHASE_SCAN_STEPS = 4480;
reg [12:0] phase_step_count = {13{1'b0}};
wire sync_mon_o = sync_i;
wire sync_mon_i = sync_mon_io;
reg sync_mon_disable = 0;
assign sync_mon_io = (sync_mon_disable) ? 1'bZ : sync_mon_o;
wire do_ce_clk;
wire done_ce_clk;
reg latched_clkps = 0;
wire ce_clkps;
wire [11:0] montiming_b_q_clkps;
wire sync_q_clkps;
reg [11:0] montiming_b_q_clk = {12{1'b0}};
reg sync_q_clk = 0;
(* IOB = "TRUE" *)
FDRE #(.INIT(1'b0)) u_sync_q(.D(sync_mon_i),.CE(ce_clkps),.C(clk_ps_i),.Q(sync_q_clkps),.R(1'b0));
generate
genvar i;
for (i=0;i<12;i=i+1) begin : MONTIMING
(* IOB = "TRUE" *)
FDRE #(.INIT(1'b1)) u_montiming_b_q(.D(MONTIMING_B[i]),.CE(ce_clkps),.C(clk_ps_i),.Q(montiming_b_q_clkps[i]),.R(1'b0));
end
endgenerate
flag_sync u_do_ce(.in_clkA(do_ce_clk),.clkA(clk_i),.out_clkB(ce_clkps),.clkB(clk_ps_i));
flag_sync u_done_ce(.in_clkA(latched_clkps),.clkA(clk_ps_i),.out_clkB(done_ce_clk),.clkB(clk_i));
always @(posedge clk_ps_i) begin
latched_clkps <= ce_clkps;
end
reg free_scan = 0;
reg latched_clk = 0;
localparam FSM_BITS = 3;
localparam [FSM_BITS-1:0] IDLE = 0;
localparam [FSM_BITS-1:0] PS_INC = 1;
localparam [FSM_BITS-1:0] PS_WAIT = 2;
localparam [FSM_BITS-1:0] DO_LATCH = 3;
localparam [FSM_BITS-1:0] LATCH_WAIT = 4;
localparam [FSM_BITS-1:0] DONE = 5;
reg [FSM_BITS-1:0] state = IDLE;
always @(posedge clk_i) begin
latched_clk <= done_ce_clk;
if (done_ce_clk) begin
montiming_b_q_clk <= montiming_b_q_clkps;
sync_q_clk <= sync_q_clkps;
end
if (wb_cyc_i && wb_stb_i && !wb_adr_i && wb_we_i) begin
free_scan <= wb_dat_i[0];
sync_mon_disable <= wb_dat_i[1];
end
case (state)
IDLE: if (free_scan) state <= PS_INC;
PS_INC: state <= PS_WAIT;
PS_WAIT: if (ps_done_i) state <= DO_LATCH;
DO_LATCH: state <= LATCH_WAIT;
LATCH_WAIT: if (done_ce_clk) begin
if (phase_step_count == PHASE_SCAN_STEPS-1) state <= DONE;
else state <= PS_INC;
end
DONE: state <= IDLE;
endcase
if (state == DONE) phase_step_count <= {13{1'b0}};
else if (state == LATCH_WAIT && done_ce_clk) phase_step_count <= phase_step_count + 1;
end
assign scan_done_o = (state == DONE);
assign scan_valid_o = (latched_clk);
assign montiming_q_o = ~montiming_b_q_clk;
assign sync_q_o = sync_q_clk;
assign ps_en_o = (state == PS_INC);
assign ps_incdec_o = (state == PS_INC);
assign do_ce_clk = (state == DO_LATCH);
endmodule
| 7.585902 |
module suspicious_object_detector (
input clk,
input resetn,
input i2c_config_done,
input capture_pixel,
input [16:0] capture_addr,
input capture_wren,
input [15:0] detection_thres,
input [15:0] static_thres,
input [15:0] suspicion_thres,
input start_capture,
output obj_detected,
output susp_obj_detected,
output [ 7:0] prev_diff_pixel8,
output [ 7:0] ref_pixel8,
output [15:0] suspicion_out
);
parameter FRAME_SIZE = 76800;
// FSM Connections
wire resetn_datapath;
wire [16:0] ref_addr, diff_addr;
wire ref_wren, ref_bram_enable, diff_wren, diff_bram_enable, init_done, frame_start;
// Output of diff BRAM
wire prev_diff_out;
// Output of ref BRAM
wire ref_pixel_out;
// Output to parent module for debugging. Pad one-bit b/w bit to 8-bits
assign prev_diff_pixel8 = {8{prev_diff_out}};
assign ref_pixel8 = {8{ref_pixel_out}};
wire [9:0] frame_count;
obj_det_control #(
.FRAME_SIZE(FRAME_SIZE)
) obj_det_control_inst (
.clk (clk),
.resetn (resetn),
.i2c_config_done (i2c_config_done),
.capture_addr (capture_addr),
.capture_wren (capture_wren),
.resetn_datapath (resetn_datapath),
.ref_addr (ref_addr),
.ref_wren (ref_wren),
.ref_bram_enable (ref_bram_enable),
.diff_addr (diff_addr),
.diff_wren (diff_wren),
.diff_bram_enable(diff_bram_enable),
.init_done (init_done),
.frame_start (frame_start),
.frame_count (frame_count),
.start_capture (start_capture)
);
obj_det_datapath obj_det_datapath_inst (
.pixel_clk (clk),
.init_done (init_done),
.resetn (resetn_datapath),
.pixel_in (capture_pixel),
.frame_start (frame_start),
.ref_addr (ref_addr),
.ref_wren (ref_wren),
.ref_bram_enable (ref_bram_enable),
.diff_addr (diff_addr),
.diff_wren (diff_wren),
.diff_bram_enable (diff_bram_enable),
.object_thres (detection_thres),
.static_thres (static_thres),
.suspicion_thres (suspicion_thres),
.object_detected (obj_detected),
.suspicion_detected(susp_obj_detected),
.prev_pixel_out (prev_diff_out),
.ref_pixel_out (ref_pixel_out),
.frame_count (frame_count),
.suspicion_out (suspicion_out)
);
endmodule
| 7.107474 |
module testbench;
reg clk_sys;
reg rst_n;
reg state_start;
reg [3:0] dump_sustain_data;
reg clk_10k;
initial begin
rst_n = 1'b0;
state_start = 1'b0;
dump_sustain_data = 4'd0;
clk_sys = 1'b0;
clk_10k = 1'b0;
end
initial begin
#500000 rst_n = 1'b1;
state_start = 1'b1;
dump_sustain_data = 4'd6;
#5000000 state_start = 1'b0;
end
always #50000 clk_10k <= !clk_10k;
always #5 clk_sys <= !clk_sys;
dump_sustain_timer dump_sustain_timer_0 (
.clk_sys(clk_sys),
.rst_n(rst_n),
.state_start(state_start),
.dump_sustain_data(dump_sustain_data),
.clk_10k(clk_10k),
.start(start)
);
endmodule
| 7.015571 |
module suTwosComp #(
parameter DATA_WIDTH = 8
) (
X_parallel,
enable,
reset,
Clk,
X_pos
);
input [DATA_WIDTH-1:0] X_parallel;
input enable, reset, Clk;
output [DATA_WIDTH-1:0] X_pos;
reg [DATA_WIDTH-1:0] X_pos;
always @(posedge Clk or posedge reset)
if (reset) begin //non-blocking statements
X_pos = {DATA_WIDTH{1'b0}};
end else if (enable) begin
if (X_parallel[DATA_WIDTH-1] == 1'b1) begin //Input is negative number
X_pos = ~X_parallel;
X_pos = X_pos + 1'b1; //Take 2's complement
end else if (X_parallel[DATA_WIDTH-1] == 1'b0) begin //Input is positive number
X_pos = X_parallel; //echo input
end
end
endmodule
| 6.798455 |
module check_par (
clk,
parity,
data
);
input clk, parity;
input [31:0] data;
property p_check_par;
@(posedge clk) (^(data ^ parity)) == 1'b0;
endproperty
a_check_par :
assert property (p_check_par);
endmodule
| 7.129536 |
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, signal;
default clocking @(posedge clk);
endclocking
initial forever #10 clk = !clk;
realtime duration = 45.0ns;
property glitch_p;
realtime first_change;
// realtime duration = 10;
@(signal) // pos and neg edge
// detecting every 2 changes duration
(1,
first_change = $realtime
) |=> (($realtime - first_change) >= duration); // [*1:$];
endproperty
ap_glitch_p :
assert property (glitch_p);
always_ff @(posedge clk) begin
end
initial begin
repeat (200) begin
@(posedge clk);
if (!randomize(
signal
) with {
signal dist {
1'b1 := 1,
1'b0 := 3
};
b dist {
1'b1 := 1,
1'b0 := 2
};
})
`uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
| 7.408481 |
module svca (
in,
cv,
signal_out
); //
parameter WIDTH = 8; //
input wire [(WIDTH-1):0] in, cv;
output wire [(WIDTH-1):0] signal_out;
wire signed [(WIDTH):0] s_in = in - 8'd128; // 0..255 -> signed -128..127
wire signed [(WIDTH):0] s_cv = cv;
wire signed [(WIDTH*2):0] result_s = s_in * s_cv;
wire signed [(WIDTH*2):0] result_ss = result_s >>> 8;
wire [(WIDTH*2):0] result_sss = result_ss + 8'd128;
assign signal_out = result_sss[(WIDTH-1):0];
endmodule
| 7.466967 |
module SVC_Vote_mux_104_bkb #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [7 : 0] din4,
input [7 : 0] din5,
input [7 : 0] din6,
input [7 : 0] din7,
input [7 : 0] din8,
input [7 : 0] din9,
input [3 : 0] din10,
output [7 : 0] dout
);
// puts internal signals
wire [3 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
wire [7 : 0] mux_1_2;
wire [7 : 0] mux_1_3;
wire [7 : 0] mux_1_4;
// level 2 signals
wire [7 : 0] mux_2_0;
wire [7 : 0] mux_2_1;
wire [7 : 0] mux_2_2;
// level 3 signals
wire [7 : 0] mux_3_0;
wire [7 : 0] mux_3_1;
// level 4 signals
wire [7 : 0] mux_4_0;
assign sel = din10;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = (sel[0] == 0) ? din8 : din9;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 7.186634 |
module SVD_interface_tb ();
reg clk;
reg rst;
reg we;
reg oe;
reg [4:0] data_i;
reg [1:0] element_sel;
wire ready;
wire [7:0] data_o_UV;
wire [6:0] data_o_S;
SVD_interface svd (
.clk(clk),
.rst(rst),
.we(we),
.oe(oe),
.data_i(data_i),
.element_sel(element_sel),
.ready(ready),
.data_o_UV(data_o_UV),
.data_o_S(data_o_S)
);
initial begin
$dumpfile("SVD_interface.fsdb");
$dumpvars;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
#0;
rst = 1'd1;
clk = 1'd1;
we = 1'd0;
oe = 1'd0;
data_i = 10'd0;
element_sel = 2'd0;
#(`CYCLE) rst = 1'd0;
#(`CYCLE) rst = 1'd1;
#(`CYCLE) we = 1'd1;
#(`CYCLE) data_i = 5'b011_00; // 43
#(`CYCLE) data_i = 5'b00101;
#(`CYCLE) element_sel = 2'd1;
data_i = 5'b001_00; // -31
#(`CYCLE) data_i = 5'b11100;
#(`CYCLE) element_sel = 2'd2;
data_i = 5'b000_00; // -56
#(`CYCLE) data_i = 5'b11001;
#(`CYCLE) element_sel = 2'd3;
data_i = 5'b100_00; // -28
#(`CYCLE) data_i = 5'b11100;
#(`CYCLE) data_i = 5'd0;
element_sel = 2'd0;
we = 1'd0;
#(50 * `CYCLE);
oe = 1'd1;
element_sel = 2'd0;
#(3 * `CYCLE) element_sel = 2'd1;
#(2 * `CYCLE) element_sel = 2'd2;
#(2 * `CYCLE) element_sel = 2'd3;
#(2 * `CYCLE) element_sel = 2'd0;
oe = 1'd0;
#(20 * `CYCLE);
$finish;
end
endmodule
| 7.25109 |
module SVD_tb ();
reg clk;
reg rst;
reg we;
reg oe;
reg [4:0] data_i;
reg [1:0] element_sel;
wire ready;
wire [7:0] data_o_UV;
wire [6:0] data_o_S;
SVD svd (
.clk(clk),
.rst(rst),
.we(we),
.oe(oe),
.data_i(data_i),
.element_sel(element_sel),
.ready(ready),
.data_o_UV(data_o_UV),
.data_o_S(data_o_S)
);
`ifdef SDF
initial $sdf_annotate(`SDFFILE, SVD);
`endif
initial begin
$dumpfile("SVD.fsdb");
$dumpvars;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
#0;
rst = 1'd1;
clk = 1'd1;
we = 1'd0;
oe = 1'd0;
data_i = 10'd0;
element_sel = 2'd0;
#(`CYCLE) rst = 1'd0;
#(`CYCLE) rst = 1'd1;
#(`CYCLE) we = 1'd1;
#(`CYCLE) data_i = 5'b011_00; // 43
#(`CYCLE) data_i = 5'b00101;
#(`CYCLE) element_sel = 2'd1;
data_i = 5'b001_00; // -31
#(`CYCLE) data_i = 5'b11100;
#(`CYCLE) element_sel = 2'd2;
data_i = 5'b000_00; // -56
#(`CYCLE) data_i = 5'b11001;
#(`CYCLE) element_sel = 2'd3;
data_i = 5'b100_00; // -28
#(`CYCLE) data_i = 5'b11100;
#(`CYCLE) data_i = 5'd0;
element_sel = 2'd0;
we = 1'd0;
#(50 * `CYCLE);
oe = 1'd1;
element_sel = 2'd0;
#(3 * `CYCLE) element_sel = 2'd1;
#(2 * `CYCLE) element_sel = 2'd2;
#(2 * `CYCLE) element_sel = 2'd3;
#(2 * `CYCLE) element_sel = 2'd0;
oe = 1'd0;
#(20 * `CYCLE);
$finish;
end
endmodule
| 7.039789 |
module video (
output [15:0] RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0] PIXADDR,
input [7:0] PIXDATA,
input PixClock
);
//reg [15:0]COLOR;
reg [7:0] SHIFT;
assign RGB = {
wCOLOR[15:11], // RED:5
wCOLOR[10:5], // GREEN:6
wCOLOR[4:0] // BLUE:5
};
/*
1328 806
640x480 => pix = 4x4 => 256x192
horizontal line [ 0 ] [ 1024 ] [ 0 ] => [0][512x2][0]
vertical line [ 0 ] [ 768 ] [ 0 ] => [128][256x2][128]
*/
/* --- 1024x768 --- */
wire [10:0] HFrontPorch = 24;
wire [10:0] HBackPorch = 144;
wire [10:0] LeftBorder = 0;
wire [10:0] HAddrVideo = LeftBorder + 1024;
wire [10:0] RightBorder = HAddrVideo + 0;
wire [10:0] HTotalTime = 1328;
wire [10:0] HSyncStartTime = 1048;
wire [9:0] VBackPorch = 28;
wire [9:0] TopBorder = VBackPorch + 128;
wire [9:0] VAddrVideo = TopBorder + 512;
wire [9:0] BottomBorder = VAddrVideo + 128;
wire [9:0] VTotalTime = 806;
wire [9:0] VSyncStartTime = 771;
/* --- 11bit (0...1328) 10bit (0...806) --- */
reg [10:0] hcnt = 0;
reg [9:0] vcnt = 0;
/* --
1024 x 768 2 ( 44 ) - 256x192
-- */
reg [9:0] colcnt = 0; // 0..1023 - 10 bit
reg [8:0] rowcnt = 0; // 0..511 - 9 bit
wire H_SYNC = (hcnt == HSyncStartTime);
wire wVBackPorch = (vcnt < VBackPorch) ? 1'b0 : 1'b1;
reg SelHSh = 1'b0;
/* */
wire [1:0]SelVSh =
(vcnt < VBackPorch)? 2'b00 :
(vcnt < TopBorder)? 2'b01 :
(vcnt < VAddrVideo)? 2'b11 :
(vcnt < BottomBorder)? 2'b01 : 2'b00;
/*
wire [1:0]SelHSh =
(hcnt < HBackPorch)? 2'b00 :
(hcnt < LeftBorder)? 2'b01 :
(hcnt < HAddrVideo)? 2'b11 :
(hcnt < RightBorder)? 2'b01 : 2'b00;
*/
/*
RAM4K - 24Kb - 15
colcnt/2 = 4
*/
`define Border 16'h1
`define BLANK 16'h0
// (0..511 row)/2 (0..1023 byte)/2
assign PIXADDR = {rowcnt[8:1], colcnt[9:4]};
wire pixreq = (colcnt[3:0] == 4'b0000);
wire [15:0] PIXCOLOR = (SHIFT[7]) ? 16'h03E0 : 16'd0;
wire [15:0]wCOLOR =
({SelVSh,SelHSh} == 4'b001)? `BLANK :
({SelVSh,SelHSh} == 4'b011)? `BLANK :
({SelVSh,SelHSh} == 4'b111)? `BLANK :
({SelVSh,SelHSh} == 4'b110)? PIXCOLOR : `BLANK;
/* --- --- */
//reg VPorchSYNC = 1'b0;
//assign VPorch = VPorchSYNC;
reg [1:0] Req = 2'b00;
always @(posedge PixClock) begin
// COLOR <= wCOLOR;
Req <= {Req[0], pixreq};
if (!colcnt[0]) SHIFT[7:0] <= (Req) ? PIXDATA[7:0] : {SHIFT[6:0], 1'b0};
if (vcnt == VTotalTime) begin
VSync <= 1'b1;
vcnt <= 0;
rowcnt <= 0;
end else begin
if (vcnt == VSyncStartTime) VSync <= 1'b0;
vcnt <= vcnt + H_SYNC;
end
// Front edge Sync
if ((hcnt == HSyncStartTime) | (hcnt == (HTotalTime - HBackPorch))) HSync <= !HSync;
if ((hcnt == HAddrVideo) | (hcnt == HTotalTime)) SelHSh <= !SelHSh;
if (hcnt == HTotalTime) begin
hcnt <= 0;
colcnt <= 0;
if (vcnt > TopBorder) begin
rowcnt <= rowcnt + 1'b1;
end
end else begin
hcnt <= hcnt + 1'b1;
end
if ({SelVSh, SelHSh} == 3'b110) colcnt <= colcnt + 1'b1;
end
endmodule
| 6.925225 |
module video (
output [8:0] RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0] PIXADDR,
input [7:0] PIXDATA,
input PixClock
);
//reg [15:0]COLOR;
reg [7:0] SHIFT;
assign RGB = {
wCOLOR[8:6], // RED:5
wCOLOR[5:3], // GREEN:6
wCOLOR[2:0] // BLUE:5
};
/*
1328 806
640x480 => pix = 4x4 => 256x192
horizontal line [ 0 ] [ 1024 ] [ 0 ] => [0][512x2][0]
vertical line [ 0 ] [ 768 ] [ 0 ] => [128][256x2][128]
*/
/* --- 1024x768 --- */
wire [10:0] HFrontPorch = 24;
wire [10:0] HBackPorch = 144;
wire [10:0] LeftBorder = 0;
wire [10:0] HAddrVideo = LeftBorder + 1024;
wire [10:0] RightBorder = HAddrVideo + 0;
wire [10:0] HTotalTime = 1328;
wire [10:0] HSyncStartTime = 1048;
wire [9:0] VBackPorch = 28;
wire [9:0] TopBorder = VBackPorch + 128;
wire [9:0] VAddrVideo = TopBorder + 512;
wire [9:0] BottomBorder = VAddrVideo + 128;
wire [9:0] VTotalTime = 806;
wire [9:0] VSyncStartTime = 771;
/* --- 11bit (0...1328) 10bit (0...806) --- */
reg [10:0] hcnt = 0;
reg [9:0] vcnt = 0;
/* --
1024 x 768 2 ( 44 ) - 256x192
-- */
reg [9:0] colcnt = 0; // 0..1023 - 10 bit
reg [8:0] rowcnt = 0; // 0..511 - 9 bit
wire H_SYNC = (hcnt == HSyncStartTime);
wire wVBackPorch = (vcnt < VBackPorch) ? 1'b0 : 1'b1;
reg SelHSh = 1'b0;
/* */
wire [1:0]SelVSh =
(vcnt < VBackPorch)? 2'b00 :
(vcnt < TopBorder)? 2'b01 :
(vcnt < VAddrVideo)? 2'b11 :
(vcnt < BottomBorder)? 2'b01 : 2'b00;
/*
wire [1:0]SelHSh =
(hcnt < HBackPorch)? 2'b00 :
(hcnt < LeftBorder)? 2'b01 :
(hcnt < HAddrVideo)? 2'b11 :
(hcnt < RightBorder)? 2'b01 : 2'b00;
*/
/*
RAM4K - 24Kb - 15
colcnt/2 = 4
*/
`define Border 9'h1
`define BLANK 9'h0
// (0..511 row)/2 (0..1023 byte)/2
assign PIXADDR = {rowcnt[8:1], colcnt[9:4]};
wire pixreq = (colcnt[3:0] == 4'b0000);
wire [8:0] PIXCOLOR = (SHIFT[7]) ? 16'h03E0 : 16'd0;
wire [8:0]wCOLOR =
({SelVSh,SelHSh} == 4'b001)? `BLANK :
({SelVSh,SelHSh} == 4'b011)? `BLANK :
({SelVSh,SelHSh} == 4'b111)? `BLANK :
({SelVSh,SelHSh} == 4'b110)? PIXCOLOR : `BLANK;
/* --- --- */
//reg VPorchSYNC = 1'b0;
//assign VPorch = VPorchSYNC;
reg [1:0] Req = 2'b00;
always @(posedge PixClock) begin
// COLOR <= wCOLOR;
Req <= {Req[0], pixreq};
if (!colcnt[0]) SHIFT[7:0] <= (Req) ? PIXDATA[7:0] : {SHIFT[6:0], 1'b0};
if (vcnt == VTotalTime) begin
VSync <= 1'b1;
vcnt <= 0;
rowcnt <= 0;
end else begin
if (vcnt == VSyncStartTime) VSync <= 1'b0;
vcnt <= vcnt + H_SYNC;
end
// Front edge Sync
if ((hcnt == HSyncStartTime) | (hcnt == (HTotalTime - HBackPorch))) HSync <= !HSync;
if ((hcnt == HAddrVideo) | (hcnt == HTotalTime)) SelHSh <= !SelHSh;
if (hcnt == HTotalTime) begin
hcnt <= 0;
colcnt <= 0;
if (vcnt > TopBorder) begin
rowcnt <= rowcnt + 1'b1;
end
end else begin
hcnt <= hcnt + 1'b1;
end
if ({SelVSh, SelHSh} == 3'b110) colcnt <= colcnt + 1'b1;
end
endmodule
| 6.925225 |
module TopModule (
input logic clk,
input logic rst,
input logic [1:0] sig,
input logic flip,
output logic [15:0] passThrough,
output logic [21:0] outOther,
output logic [1:0] sig_out
);
logic MyInterfaceInstance_setting;
logic [3:0] MyInterfaceInstance_other_setting;
logic [1:0] MyInterfaceInstance_mysig_out;
SubModule1 u_SubModule1 (
.clk(clk),
.rst(rst),
.u_MyInterface_setting(MyInterfaceInstance_setting),
.u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
.u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
.outOther(outOther),
.passThrough(passThrough),
.sig(sig)
);
assign sig_out = MyInterfaceInstance_mysig_out;
assign MyInterfaceInstance_setting = flip;
endmodule
| 6.503818 |
module SubModule1 (
input logic clk,
input logic rst,
input logic u_MyInterface_setting,
output logic [3:0] u_MyInterface_other_setting,
output logic [1:0] u_MyInterface_mysig_out,
output logic [21:0] outOther,
input logic [1:0] sig,
output logic [15:0] passThrough
);
always @(posedge clk or posedge rst)
if (rst) u_MyInterface_mysig_out <= 0;
else begin
if (u_MyInterface_setting) u_MyInterface_mysig_out <= sig;
else u_MyInterface_mysig_out <= ~sig;
end
logic MyInterfaceInstanceInSub_setting;
logic [21:0] MyInterfaceInstanceInSub_other_setting;
logic [1:0] MyInterfaceInstanceInSub_mysig_out;
SubModule2 u_SubModule2 (
.clk(clk),
.rst(rst),
.u_MyInterfaceInSub2_setting(u_MyInterface_setting),
.u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
.u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
.u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
.u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
.u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
.passThrough(passThrough)
);
assign outOther = MyInterfaceInstanceInSub_other_setting;
assign MyInterfaceInstanceInSub_setting = 0;
assign MyInterfaceInstanceInSub_mysig_out = sig;
endmodule
| 6.770638 |
module TopModule (
input logic clk,
input logic rst,
input logic [1:0] sig,
input logic flip,
output logic [15:0] passThrough,
output logic [21:0] outOther,
input logic interfaceInstanceAtTop_setting,
output logic [2:0] interfaceInstanceAtTop_other_setting,
output logic [1:0] interfaceInstanceAtTop_mysig_out,
output logic [15:0] interfaceInstanceAtTop_passThrough,
output logic [1:0] sig_out
);
logic MyInterfaceInstance_setting;
logic [3:0] MyInterfaceInstance_other_setting;
logic [1:0] MyInterfaceInstance_mysig_out;
SubModule1 u_SubModule1 (
.clk(clk),
.rst(rst),
.u_MyInterface_setting(MyInterfaceInstance_setting),
.u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
.u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
.u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
.u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
.u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
.u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
.outOther(outOther),
.passThrough(passThrough),
.sig(sig)
);
assign sig_out = MyInterfaceInstance_mysig_out;
assign MyInterfaceInstance_setting = flip;
endmodule
| 6.503818 |
module SubModule1 (
input logic clk,
input logic rst,
input logic u_MyInterface_setting,
output logic [3:0] u_MyInterface_other_setting,
output logic [1:0] u_MyInterface_mysig_out,
output logic [21:0] outOther,
input logic [1:0] sig,
input logic u_MyInterfaceFromTop_setting,
output logic [2:0] u_MyInterfaceFromTop_other_setting,
output logic [1:0] u_MyInterfaceFromTop_mysig_out,
output logic [14:0] u_MyInterfaceFromTop_passThrough,
output logic [15:0] passThrough
);
always @(posedge clk or posedge rst)
if (rst) u_MyInterface_mysig_out <= 0;
else begin
if (u_MyInterface_setting) u_MyInterface_mysig_out <= sig;
else u_MyInterface_mysig_out <= ~sig;
end
logic MyInterfaceInstanceInSub_setting;
logic [21:0] MyInterfaceInstanceInSub_other_setting;
logic [1:0] MyInterfaceInstanceInSub_mysig_out;
assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20;
SubModule2 u_SubModule2 (
.clk(clk),
.rst(rst),
.u_MyInterfaceInSub2_setting(u_MyInterface_setting),
.u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
.u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
.u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
.u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
.u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
.passThrough(passThrough)
);
assign outOther = MyInterfaceInstanceInSub_other_setting;
assign MyInterfaceInstanceInSub_setting = 0;
assign MyInterfaceInstanceInSub_mysig_out = sig;
endmodule
| 6.770638 |
module svm_detection_test_v;
// Inputs
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] x;
reg data_valid;
reg clk;
reg reset;
// Outputs
wire [`SVM_CLASS_WIDTH - 1:0] class;
wire ready;
wire new_result;
reg error;
// Instantiate the Unit Under Test (UUT)
svm_detection uut (
.x(x),
.data_valid(data_valid),
.clk(clk),
.reset(reset),
.class(class),
.ready(ready),
.new_result(new_result)
);
// Initialize the memory with test vectors and classes
reg [`SVM_CLASS_WIDTH-1:0] ref_classes [0:`CLASS_TEST_COUNT-1];
initial begin
$readmemh({`PROJ_CONFIG_DIR, "svm_parameters.test.classes.list"}, ref_classes);
end
generate
genvar i;
for (i = 0; i < `SVM_PARAM_COUNT; i = i + 1) begin: ref
reg [`SVM_PARAM_WIDTH-1:0] vectors [0:`CLASS_TEST_COUNT-1];
initial begin: init_param
reg [1:8 * 100] memory_name;
$sformat(memory_name, "svm_parameters.test.vectors.%1d.list", i);
$readmemh({`PROJ_CONFIG_DIR, memory_name}, vectors);
end
end
endgenerate
initial begin
// Initialize Inputs
clk = 1;
reset = 1;
#2000;
reset = 0;
end
// Reference ROM management
reg [`CLASS_TEST_WIDTH-1:0] input_counter;
reg [`CLASS_TEST_WIDTH-1:0] output_counter;
wire input_enable;
wire output_enable;
reg [`SVM_CLASS_WIDTH-1:0] output_ref;
always @(posedge clk) begin
if (output_enable)
output_ref <= ref_classes[output_counter];
end
generate
for (i = 0; i < `SVM_PARAM_COUNT; i = i + 1) begin: params_read
always @(posedge clk) begin
if (input_enable)
x[(i+1) * `SVM_PARAM_WIDTH - 1 : i * `SVM_PARAM_WIDTH] <= ref[i].vectors[input_counter];
end
end
endgenerate
// Control
assign input_enable = 1;
assign output_enable = 1;
always @(posedge clk) begin
if (reset) begin
input_counter <= 0;
output_counter <= 0;
error <= 0;
end else begin
if (ready && !data_valid) begin
input_counter <= (input_counter + 1) % `CLASS_TEST_COUNT;
data_valid <= 1;
end else begin
data_valid <= 0;
end
if (new_result) begin
output_counter <= (output_counter + 1) % `CLASS_TEST_COUNT;
error <= error || (output_ref != class);
end
end
end
always begin
#5 clk = ~clk;
end
endmodule
| 6.971674 |
module
`timescale 1ns / 1ps
`include "../config/svm_parameters.v"
module svm_kernel_test;
// Inputs
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] x;
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] sv;
reg [`SVM_CLASS_WIDTH - 1:0] sv_class;
reg [(`SVM_COEF_WIDTH_INT + `SVM_COEF_WIDTH_FRAC) * (`SVM_CLASS_COUNT - 1) - 1:0] coef;
reg [`SVM_COEF_SIGN_WIDTH * (`SVM_CLASS_COUNT - 1) - 1:0] coef_sign;
reg new_computation;
reg clk;
reg reset;
reg data_valid;
// Outputs
wire [(`SVM_DISTANCE_WIDTH_INT + `SVM_DISTANCE_WIDTH_FRAC) * (`SVM_DECISION_COUNT) - 1:0] distance;
// Instantiate the Unit Under Test (UUT)
`ifdef SVM_KERNEL_TYPE_RBF
// RBF kernel computation
svm_kernel_rbf uut (
.x(x),
.sv(sv),
.sv_class(sv_class),
.coef_ln(coef),
.coef_sign(coef_sign),
.new_computation(new_computation),
.data_valid(data_valid),
.clk(clk),
.reset(reset),
.distance(distance)
);
`endif
`ifdef SVM_KERNEL_TYPE_CORDIC
// CORDIC kernel computation
svm_kernel_cordic uut (
.x(x),
.sv(sv),
.sv_class(sv_class),
.coef_scaled(coef),
.coef_sign(coef_sign),
.new_computation(new_computation),
.data_valid(data_valid),
.clk(clk),
.reset(reset),
.distance(distance)
);
`endif
// Clock
always begin
#5 clk = ~clk;
end
// Initialize Inputs
initial begin
x = 0;
sv = 0;
sv_class = 0;
coef = 0;
coef_sign = 0;
clk = 1;
reset = 1;
data_valid = 0;
new_computation = 0;
// Wait for global reset to finish
#2000;
reset = 0;
// Wait before enable
#100;
// Constant value
data_valid = 1;
x = {`SVM_PARAM_WIDTH'd45, `SVM_PARAM_WIDTH'd1200, `SVM_PARAM_WIDTH'd128};
sv = {`SVM_PARAM_WIDTH'd50, `SVM_PARAM_WIDTH'd1180, `SVM_PARAM_WIDTH'd120};
sv_class = 3'd0;
coef = {-14'sd25, 14'sd0, 14'sd18, 14'sd1258};
coef_sign = {1'b1, 1'b0, 1'b1, 1'b1};
// Other constant value
#10
x = {`SVM_PARAM_WIDTH'd1020, `SVM_PARAM_WIDTH'd182, `SVM_PARAM_WIDTH'd0};
sv = {`SVM_PARAM_WIDTH'd950, `SVM_PARAM_WIDTH'd350, `SVM_PARAM_WIDTH'd120};
sv_class = 3'd2;
coef = {14'sd4587, 14'sd12, -14'sd5269, 14'sd0};
coef_sign = {1'b1, 1'b1, 1'b1, 1'b0};
// Disable
#10
data_valid = 0;
x = 0;
sv = 0;
sv_class = 0;
coef = 0;
end
endmodule
| 6.608387 |
module svo_pong
//
// a clone of the Atari 1972 game PONG. this is implemented as a video
// filter with enable input. when enabled it will overlay the game on the
// video stream. connect .auto_btn with .btn to let the game play against
// itself.
// ----------------------------------------------------------------------
module svo_pong #( `SVO_DEFAULT_PARAMS ) (
input clk, resetn, resetn_game, enable,
input [3:0] btn,
output [3:0] auto_btn,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
output in_axis_tready,
input [SVO_BITS_PER_PIXEL-1:0] in_axis_tdata,
input [0:0] in_axis_tuser,
// output stream
// tuser[0] ... start of frame
output out_axis_tvalid,
input out_axis_tready,
output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
output [0:0] out_axis_tuser
);
`SVO_DECLS
wire [11:0] p1_pos, p2_pos;
wire [6:0] p1_points, p2_points;
wire [11:0] puck_x, puck_y;
wire flash;
svo_pong_control #( `SVO_PASS_PARAMS ) svo_pong_control (
.clk(clk),
.resetn(resetn && resetn_game),
.enable(in_axis_tvalid && in_axis_tready && in_axis_tuser && enable),
.btn(btn),
.auto_btn(auto_btn),
.flash(flash),
.p1_pos(p1_pos),
.p2_pos(p2_pos),
.p1_points(p1_points),
.p2_points(p2_points),
.puck_x(puck_x),
.puck_y(puck_y)
);
svo_pong_video #( `SVO_PASS_PARAMS ) svo_pong_video (
.clk(clk),
.resetn(resetn),
.enable(enable),
.flash(flash),
.p1_pos(p1_pos),
.p2_pos(p2_pos),
.p1_points(p1_points),
.p2_points(p2_points),
.puck_x(puck_x),
.puck_y(puck_y),
.in_axis_tvalid(in_axis_tvalid),
.in_axis_tready(in_axis_tready),
.in_axis_tdata(in_axis_tdata),
.in_axis_tuser(in_axis_tuser),
.out_axis_tvalid(out_axis_tvalid),
.out_axis_tready(out_axis_tready),
.out_axis_tdata(out_axis_tdata),
.out_axis_tuser(out_axis_tuser)
);
endmodule
| 7.003866 |
module svo_axis_pipe
//
// this core is a simple helper for creating video pipeline cores with
// an axi stream interface.
// ----------------------------------------------------------------------
module svo_axis_pipe #(
parameter TDATA_WIDTH = 8,
parameter TUSER_WIDTH = 1
) (
input clk, resetn,
// axis input stream
input in_axis_tvalid,
output in_axis_tready,
input [TDATA_WIDTH-1:0] in_axis_tdata,
input [TUSER_WIDTH-1:0] in_axis_tuser,
// axis output stream
output out_axis_tvalid,
input out_axis_tready,
output [TDATA_WIDTH-1:0] out_axis_tdata,
output [TUSER_WIDTH-1:0] out_axis_tuser,
// pipeline i/o
output [TDATA_WIDTH-1:0] pipe_in_tdata,
input [TDATA_WIDTH-1:0] pipe_out_tdata,
output [TUSER_WIDTH-1:0] pipe_in_tuser,
input [TUSER_WIDTH-1:0] pipe_out_tuser,
output pipe_in_tvalid,
input pipe_out_tvalid,
output pipe_enable
);
reg tvalid_q0, tvalid_q1;
reg [TDATA_WIDTH-1:0] tdata_q0, tdata_q1;
reg [TUSER_WIDTH-1:0] tuser_q0, tuser_q1;
assign in_axis_tready = !tvalid_q1;
assign out_axis_tvalid = tvalid_q0 || tvalid_q1;
assign out_axis_tdata = tvalid_q1 ? tdata_q1 : tdata_q0;
assign out_axis_tuser = tvalid_q1 ? tuser_q1 : tuser_q0;
assign pipe_enable = in_axis_tvalid && in_axis_tready;
assign pipe_in_tdata = in_axis_tdata;
assign pipe_in_tuser = in_axis_tuser;
assign pipe_in_tvalid = in_axis_tvalid;
always @(posedge clk) begin
if (!resetn) begin
tvalid_q0 <= 0;
tvalid_q1 <= 0;
end else begin
if (pipe_enable) begin
tdata_q0 <= pipe_out_tdata;
tdata_q1 <= tdata_q0;
tuser_q0 <= pipe_out_tuser;
tuser_q1 <= tuser_q0;
tvalid_q0 <= pipe_out_tvalid;
tvalid_q1 <= tvalid_q0 && !out_axis_tready;
end else if (out_axis_tready) begin
if (tvalid_q1)
tvalid_q1 <= 0;
else
tvalid_q0 <= 0;
end
end
end
endmodule
| 7.843568 |
module svo_buf
//
// just a buffer that adds an other ff layer to the stream.
// ----------------------------------------------------------------------
module svo_buf #(
parameter TUSER_WIDTH = 1,
`SVO_DEFAULT_PARAMS
) (
input clk, resetn,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
output in_axis_tready,
input [SVO_BITS_PER_PIXEL-1:0] in_axis_tdata,
input [TUSER_WIDTH-1:0] in_axis_tuser,
// output stream
// tuser[0] ... start of frame
output out_axis_tvalid,
input out_axis_tready,
output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
output [TUSER_WIDTH-1:0] out_axis_tuser
);
`SVO_DECLS
wire [SVO_BITS_PER_PIXEL-1:0] pipe_in_tdata;
reg [SVO_BITS_PER_PIXEL-1:0] pipe_out_tdata;
wire [TUSER_WIDTH-1:0] pipe_in_tuser;
reg [TUSER_WIDTH-1:0] pipe_out_tuser;
wire pipe_in_tvalid;
reg pipe_out_tvalid;
wire pipe_enable;
always @(posedge clk) begin
if (!resetn) begin
pipe_out_tvalid <= 0;
end else
if (pipe_enable) begin
pipe_out_tdata <= pipe_in_tdata;
pipe_out_tuser <= pipe_in_tuser;
pipe_out_tvalid <= pipe_in_tvalid;
end
end
svo_axis_pipe #(
.TDATA_WIDTH(SVO_BITS_PER_PIXEL),
.TUSER_WIDTH(TUSER_WIDTH)
) svo_axis_pipe (
.clk(clk),
.resetn(resetn),
.in_axis_tvalid(in_axis_tvalid),
.in_axis_tready(in_axis_tready),
.in_axis_tdata(in_axis_tdata),
.in_axis_tuser(in_axis_tuser),
.out_axis_tvalid(out_axis_tvalid),
.out_axis_tready(out_axis_tready),
.out_axis_tdata(out_axis_tdata),
.out_axis_tuser(out_axis_tuser),
.pipe_in_tdata(pipe_in_tdata),
.pipe_out_tdata(pipe_out_tdata),
.pipe_in_tuser(pipe_in_tuser),
.pipe_out_tuser(pipe_out_tuser),
.pipe_in_tvalid(pipe_in_tvalid),
.pipe_out_tvalid(pipe_out_tvalid),
.pipe_enable(pipe_enable)
);
endmodule
| 7.290203 |
module svo_dim
//
// this core dims the video data (half each r/g/b sample value) when
// the enable input is high. it is also a nice demo of how to create
// simple pipelines that integrate with axi4 streams.
// ----------------------------------------------------------------------
module svo_dim #( `SVO_DEFAULT_PARAMS ) (
input clk, resetn, enable,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
output in_axis_tready,
input [SVO_BITS_PER_PIXEL-1:0] in_axis_tdata,
input [0:0] in_axis_tuser,
// output stream
// tuser[0] ... start of frame
output out_axis_tvalid,
input out_axis_tready,
output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
output [0:0] out_axis_tuser
);
`SVO_DECLS
wire [SVO_BITS_PER_PIXEL-1:0] pipe_in_tdata;
reg [SVO_BITS_PER_PIXEL-1:0] pipe_out_tdata;
wire pipe_in_tuser;
reg pipe_out_tuser;
wire pipe_in_tvalid;
reg pipe_out_tvalid;
wire pipe_enable;
always @(posedge clk) begin
if (!resetn) begin
pipe_out_tvalid <= 0;
end else
if (pipe_enable) begin
pipe_out_tdata <= enable ? svo_rgba(svo_r(pipe_in_tdata) >> 1, svo_g(pipe_in_tdata) >> 1, svo_b(pipe_in_tdata) >> 1, svo_a(pipe_in_tdata)) : pipe_in_tdata;
pipe_out_tuser <= pipe_in_tuser;
pipe_out_tvalid <= pipe_in_tvalid;
end
end
svo_axis_pipe #(
.TDATA_WIDTH(SVO_BITS_PER_PIXEL),
.TUSER_WIDTH(1)
) svo_axis_pipe (
.clk(clk),
.resetn(resetn),
.in_axis_tvalid(in_axis_tvalid),
.in_axis_tready(in_axis_tready),
.in_axis_tdata(in_axis_tdata),
.in_axis_tuser(in_axis_tuser),
.out_axis_tvalid(out_axis_tvalid),
.out_axis_tready(out_axis_tready),
.out_axis_tdata(out_axis_tdata),
.out_axis_tuser(out_axis_tuser),
.pipe_in_tdata(pipe_in_tdata),
.pipe_out_tdata(pipe_out_tdata),
.pipe_in_tuser(pipe_in_tuser),
.pipe_out_tuser(pipe_out_tuser),
.pipe_in_tvalid(pipe_in_tvalid),
.pipe_out_tvalid(pipe_out_tvalid),
.pipe_enable(pipe_enable)
);
endmodule
| 6.968906 |
module svo_overlay
//
// overlay one video stream ontop of another one
// ----------------------------------------------------------------------
module svo_overlay #( `SVO_DEFAULT_PARAMS ) (
input clk, resetn, enable,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
output in_axis_tready,
input [SVO_BITS_PER_PIXEL-1:0] in_axis_tdata,
input [0:0] in_axis_tuser,
// overlay stream
// tuser[0] ... start of frame
// tuser[1] ... use overlay pixel
input over_axis_tvalid,
output over_axis_tready,
input [SVO_BITS_PER_PIXEL-1:0] over_axis_tdata,
input [1:0] over_axis_tuser,
// output stream
// tuser[0] ... start of frame
output out_axis_tvalid,
input out_axis_tready,
output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
output [0:0] out_axis_tuser
);
`SVO_DECLS
wire buf_in_axis_tvalid;
wire buf_in_axis_tready;
wire [SVO_BITS_PER_PIXEL-1:0] buf_in_axis_tdata;
wire [0:0] buf_in_axis_tuser;
wire buf_over_axis_tvalid;
wire buf_over_axis_tready;
wire [SVO_BITS_PER_PIXEL-1:0] buf_over_axis_tdata;
wire [1:0] buf_over_axis_tuser;
wire buf_out_axis_tvalid;
wire buf_out_axis_tready;
wire [SVO_BITS_PER_PIXEL-1:0] buf_out_axis_tdata;
wire [0:0] buf_out_axis_tuser;
// -------------------------------------------------------------------
wire active = buf_in_axis_tvalid && buf_over_axis_tvalid;
wire skip_in = !buf_in_axis_tuser[0] && buf_over_axis_tuser[0];
wire skip_over = buf_in_axis_tuser[0] && !buf_over_axis_tuser[0];
assign buf_in_axis_tready = active && (skip_in || (!skip_over && buf_out_axis_tready));
assign buf_over_axis_tready = active && (skip_over || (!skip_in && buf_out_axis_tready));
assign buf_out_axis_tvalid = active && !skip_in && !skip_over;
assign buf_out_axis_tdata = enable && buf_over_axis_tuser[1] ? buf_over_axis_tdata : buf_in_axis_tdata;
assign buf_out_axis_tuser = enable && buf_over_axis_tuser[1] ? buf_over_axis_tuser : buf_in_axis_tuser;
// -------------------------------------------------------------------
svo_buf #( `SVO_PASS_PARAMS ) svo_buf_in (
.clk(clk), .resetn(resetn),
.in_axis_tvalid(in_axis_tvalid),
.in_axis_tready(in_axis_tready),
.in_axis_tdata(in_axis_tdata),
.in_axis_tuser(in_axis_tuser),
.out_axis_tvalid(buf_in_axis_tvalid),
.out_axis_tready(buf_in_axis_tready),
.out_axis_tdata(buf_in_axis_tdata),
.out_axis_tuser(buf_in_axis_tuser)
);
svo_buf #( .TUSER_WIDTH(2), `SVO_PASS_PARAMS ) svo_buf_over (
.clk(clk), .resetn(resetn),
.in_axis_tvalid(over_axis_tvalid),
.in_axis_tready(over_axis_tready),
.in_axis_tdata(over_axis_tdata),
.in_axis_tuser(over_axis_tuser),
.out_axis_tvalid(buf_over_axis_tvalid),
.out_axis_tready(buf_over_axis_tready),
.out_axis_tdata(buf_over_axis_tdata),
.out_axis_tuser(buf_over_axis_tuser)
);
svo_buf #( `SVO_PASS_PARAMS ) svo_buf_out (
.clk(clk), .resetn(resetn),
.in_axis_tvalid(buf_out_axis_tvalid),
.in_axis_tready(buf_out_axis_tready),
.in_axis_tdata(buf_out_axis_tdata),
.in_axis_tuser(buf_out_axis_tuser),
.out_axis_tvalid(out_axis_tvalid),
.out_axis_tready(out_axis_tready),
.out_axis_tdata(out_axis_tdata),
.out_axis_tuser(out_axis_tuser)
);
endmodule
| 6.882282 |
module SVPWM (
iClk,
iRst_n,
iModulate_en,
iValpha,
iVbeta,
oPWM_u,
oPWM_v,
oPWM_w,
oModulate_done
);
input wire iClk;
input wire iRst_n;
input wire iModulate_en;
input wire [15:0] iValpha, iVbeta;
output wire oPWM_u, oPWM_v, oPWM_w;
output wire oModulate_done;
wire [2:0] nsector;
wire [15:0] nv1, nv2, nv3;
wire nic_done, nas_done, ncw_done;
wire [11:0] nccr_a, nccr_b, nccr_c;
Inv_Clark inv_clark (
.iClk(iClk),
.iRst_n(iRst_n),
.iIC_en(iModulate_en),
.iValpha(iValpha),
.iVbeta(iVbeta),
.oV1(nv1),
.oV2(nv2),
.oV3(nv3),
.oIC_done(nic_done)
);
SVPWM_Analyse_Sector svpwm_analyse_sector (
.iClk(iClk),
.iRst_n(iRst_n),
.iAS_en(nic_done),
.iA(!nv1[15]),
.iB(!nv2[15]),
.iC(!nv3[15]),
.oSector(nsector),
.oAS_done(nas_done)
);
SVPWM_Calculate_Workingtime svpwm_calculate_workingtime (
.iClk(iClk),
.iRst_n(iRst_n),
.iCW_en(nas_done),
.iSector(nsector),
.iV1(nv1),
.iV2(nv2),
.iV3(nv3),
.oCCR_a(nccr_a),
.oCCR_b(nccr_b),
.oCCR_c(nccr_c),
.oCW_done(ncw_done)
);
SVPWM_Modulate_PWM svpwm_modulate_pwm (
.iClk(iClk),
.iRst_n(iRst_n),
.iMP_en(ncw_done),
.iCCR_a(nccr_a),
.iCCR_b(nccr_b),
.iCCR_c(nccr_c),
.oPWM_u(oPWM_u),
.oPWM_v(oPWM_v),
.oPWM_w(oPWM_w),
.oMP_done(oModulate_done)
);
endmodule
| 6.694093 |
module SVPWM_Analyse_Sector (
iClk,
iRst_n,
iAS_en,
iA,
iB,
iC,
oSector,
oAS_done
);
input wire iClk;
input wire iRst_n;
input wire iAS_en;
input wire iA, iB, iC;
output reg [2:0] oSector;
output reg oAS_done;
localparam Sector_1 = 3'd1;
localparam Sector_2 = 3'd2;
localparam Sector_3 = 3'd3;
localparam Sector_4 = 3'd4;
localparam Sector_5 = 3'd5;
localparam Sector_6 = 3'd6;
localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b11;
localparam S3 = 2'b10;
reg [1:0] state;
reg nas_en_pre_state;
reg [2:0] ntemp_a, ntemp_b, ntemp_c, nN;
always @(posedge iClk or negedge iRst_n) begin
if (!iRst_n) begin
nas_en_pre_state <= 1'b0;
end else begin
nas_en_pre_state <= iAS_en;
end
end
always @(posedge iClk or negedge iRst_n) begin
if (!iRst_n) begin
state <= S0;
ntemp_a <= 3'd0;
ntemp_b <= 3'd0;
ntemp_c <= 3'd0;
nN <= 3'd0;
oAS_done <= 1'b0;
oSector <= 3'd0;
end else begin
case (state)
S0: begin
if ((!nas_en_pre_state) & iAS_en) begin
ntemp_a <= iA;
ntemp_b <= iB;
ntemp_c <= iC;
state <= S1;
end else begin
ntemp_a <= 3'd0;
ntemp_b <= 3'd0;
ntemp_c <= 3'd0;
oAS_done <= 1'b0;
state <= state;
end
end
S1: begin
nN <= ntemp_a + (ntemp_b << 1) + (ntemp_c << 2);
state <= S2;
end
S2: begin
case (nN)
3'd1: oSector <= Sector_2;
3'd2: oSector <= Sector_6;
3'd3: oSector <= Sector_1;
3'd4: oSector <= Sector_4;
3'd5: oSector <= Sector_3;
3'd6: oSector <= Sector_5;
default: ;
endcase
oAS_done <= 1'b1;
state <= S0;
end
default: state <= S0;
endcase
end
end
endmodule
| 7.994209 |
module wrapper_norm_corr_20 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10,
corr_out_11,
corr_out_12,
corr_out_13,
corr_out_14,
corr_out_15,
corr_out_16,
corr_out_17,
corr_out_18,
corr_out_19,
corr_out_20
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
output [2 * sh_reg_w - 1:0] corr_out_6;
wire [2 * sh_reg_w - 1:0] corr_out_6;
output [2 * sh_reg_w - 1:0] corr_out_7;
wire [2 * sh_reg_w - 1:0] corr_out_7;
output [2 * sh_reg_w - 1:0] corr_out_8;
wire [2 * sh_reg_w - 1:0] corr_out_8;
output [2 * sh_reg_w - 1:0] corr_out_9;
wire [2 * sh_reg_w - 1:0] corr_out_9;
output [2 * sh_reg_w - 1:0] corr_out_10;
wire [2 * sh_reg_w - 1:0] corr_out_10;
output [2 * sh_reg_w - 1:0] corr_out_11;
wire [2 * sh_reg_w - 1:0] corr_out_11;
output [2 * sh_reg_w - 1:0] corr_out_12;
wire [2 * sh_reg_w - 1:0] corr_out_12;
output [2 * sh_reg_w - 1:0] corr_out_13;
wire [2 * sh_reg_w - 1:0] corr_out_13;
output [2 * sh_reg_w - 1:0] corr_out_14;
wire [2 * sh_reg_w - 1:0] corr_out_14;
output [2 * sh_reg_w - 1:0] corr_out_15;
wire [2 * sh_reg_w - 1:0] corr_out_15;
output [2 * sh_reg_w - 1:0] corr_out_16;
wire [2 * sh_reg_w - 1:0] corr_out_16;
output [2 * sh_reg_w - 1:0] corr_out_17;
wire [2 * sh_reg_w - 1:0] corr_out_17;
output [2 * sh_reg_w - 1:0] corr_out_18;
wire [2 * sh_reg_w - 1:0] corr_out_18;
output [2 * sh_reg_w - 1:0] corr_out_19;
wire [2 * sh_reg_w - 1:0] corr_out_19;
output [2 * sh_reg_w - 1:0] corr_out_20;
wire [2 * sh_reg_w - 1:0] corr_out_20;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_20 corr_20_inst (
.clk(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5),
.corr_out_6(corr_out_6),
.corr_out_7(corr_out_7),
.corr_out_8(corr_out_8),
.corr_out_9(corr_out_9),
.corr_out_10(corr_out_10),
.corr_out_11(corr_out_11),
.corr_out_12(corr_out_12),
.corr_out_13(corr_out_13),
.corr_out_14(corr_out_14),
.corr_out_15(corr_out_15),
.corr_out_16(corr_out_16),
.corr_out_17(corr_out_17),
.corr_out_18(corr_out_18),
.corr_out_19(corr_out_19),
.corr_out_20(corr_out_20)
);
endmodule
| 6.699338 |
module wrapper_norm_corr_10 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
output [2 * sh_reg_w - 1:0] corr_out_6;
wire [2 * sh_reg_w - 1:0] corr_out_6;
output [2 * sh_reg_w - 1:0] corr_out_7;
wire [2 * sh_reg_w - 1:0] corr_out_7;
output [2 * sh_reg_w - 1:0] corr_out_8;
wire [2 * sh_reg_w - 1:0] corr_out_8;
output [2 * sh_reg_w - 1:0] corr_out_9;
wire [2 * sh_reg_w - 1:0] corr_out_9;
output [2 * sh_reg_w - 1:0] corr_out_10;
wire [2 * sh_reg_w - 1:0] corr_out_10;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_10 corr_5_inst (
.clk(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5),
.corr_out_6(corr_out_6),
.corr_out_7(corr_out_7),
.corr_out_8(corr_out_8),
.corr_out_9(corr_out_9),
.corr_out_10(corr_out_10)
);
endmodule
| 6.699338 |
module wrapper_norm_corr_5_seq (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm_seq norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm_seq norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_5_seq corr_5_inst (
.tm3_clk_v0(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5)
);
endmodule
| 6.699338 |
module wrapper_corr_5_seq (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input tm3_clk_v0;
input wen;
input [7:0] d_l_1;
input [7:0] d_l_2;
input [7:0] d_r_1;
input [7:0] d_r_2;
output [15:0] corr_out_0;
reg [15:0] corr_out_0;
output [15:0] corr_out_1;
reg [15:0] corr_out_1;
output [15:0] corr_out_2;
reg [15:0] corr_out_2;
output [15:0] corr_out_3;
reg [15:0] corr_out_3;
output [15:0] corr_out_4;
reg [15:0] corr_out_4;
output [15:0] corr_out_5;
reg [15:0] corr_out_5;
wire [sh_reg_w - 1:0] out_r1;
wire [sh_reg_w - 1:0] out_01;
wire [sh_reg_w - 1:0] out_11;
wire [sh_reg_w - 1:0] out_21;
wire [sh_reg_w - 1:0] out_31;
wire [sh_reg_w - 1:0] out_41;
wire [sh_reg_w - 1:0] out_51;
wire [sh_reg_w - 1:0] out_r2;
wire [sh_reg_w - 1:0] out_02;
wire [sh_reg_w - 1:0] out_12;
wire [sh_reg_w - 1:0] out_22;
wire [sh_reg_w - 1:0] out_32;
wire [sh_reg_w - 1:0] out_42;
wire [sh_reg_w - 1:0] out_52;
wire [2 * sh_reg_w - 1:0] corr_out_0_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_1_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_2_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_3_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_4_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_5_tmp;
sh_reg inst_sh_reg_r_1 (
tm3_clk_v0,
wen,
d_r_1,
d_r_2,
out_r1,
out_r2
);
sh_reg inst_sh_reg_0 (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
out_01,
out_02
);
sh_reg inst_sh_reg_1 (
tm3_clk_v0,
wen,
out_01,
out_02,
out_11,
out_12
);
sh_reg inst_sh_reg_2 (
tm3_clk_v0,
wen,
out_11,
out_12,
out_21,
out_22
);
sh_reg inst_sh_reg_3 (
tm3_clk_v0,
wen,
out_21,
out_22,
out_31,
out_32
);
sh_reg inst_sh_reg_4 (
tm3_clk_v0,
wen,
out_31,
out_32,
out_41,
out_42
);
sh_reg inst_sh_reg_5 (
tm3_clk_v0,
wen,
out_41,
out_42,
out_51,
out_52
);
corr_seq inst_corr_0 (
tm3_clk_v0,
wen,
out_01,
out_02,
out_r1,
out_r2,
corr_out_0_tmp
);
corr_seq inst_corr_1 (
tm3_clk_v0,
wen,
out_11,
out_12,
out_r1,
out_r2,
corr_out_1_tmp
);
corr_seq inst_corr_2 (
tm3_clk_v0,
wen,
out_21,
out_22,
out_r1,
out_r2,
corr_out_2_tmp
);
corr_seq inst_corr_3 (
tm3_clk_v0,
wen,
out_31,
out_32,
out_r1,
out_r2,
corr_out_3_tmp
);
corr_seq inst_corr_4 (
tm3_clk_v0,
wen,
out_41,
out_42,
out_r1,
out_r2,
corr_out_4_tmp
);
corr_seq inst_corr_5 (
tm3_clk_v0,
wen,
out_51,
out_52,
out_r1,
out_r2,
corr_out_5_tmp
);
always @(posedge tm3_clk_v0) begin
if (wen == 1'b1) begin
corr_out_0 <= corr_out_0_tmp;
corr_out_1 <= corr_out_1_tmp;
corr_out_2 <= corr_out_2_tmp;
corr_out_3 <= corr_out_3_tmp;
corr_out_4 <= corr_out_4_tmp;
corr_out_5 <= corr_out_5_tmp;
end else begin
corr_out_0 <= corr_out_0;
corr_out_1 <= corr_out_1;
corr_out_2 <= corr_out_2;
corr_out_3 <= corr_out_3;
corr_out_4 <= corr_out_4;
corr_out_5 <= corr_out_5;
end
end
endmodule
| 6.720326 |
module wrapper_norm_seq (
clk,
nd,
din_1,
din_2,
dout_1,
dout_2
);
parameter sh_reg_w = 4'b1000;
input clk;
input nd;
input [15:0] din_1;
input [15:0] din_2;
output [sh_reg_w - 1:0] dout_1;
wire [sh_reg_w - 1:0] dout_1;
output [sh_reg_w - 1:0] dout_2;
wire [sh_reg_w - 1:0] dout_2;
reg [15:0] din_1_reg;
reg [15:0] din_2_reg;
reg [15:0] din_1_tmp1;
reg [15:0] din_2_tmp1;
reg [15:0] din_1_tmp2;
reg [15:0] din_2_tmp2;
reg [15:0] addin_1;
reg [15:0] addin_2;
reg [16:0] add_out;
my_wrapper_divider my_div_inst_1 (
nd,
clk,
din_1_tmp2,
add_out,
dout_1
);
my_wrapper_divider my_div_inst_2 (
nd,
clk,
din_2_tmp2,
add_out,
dout_2
);
always @(posedge clk) begin
if (nd == 1'b1) begin
din_1_reg <= din_1;
din_2_reg <= din_2;
end else begin
din_1_reg <= din_1_reg;
din_2_reg <= din_2_reg;
end
din_1_tmp1 <= din_1_reg;
din_1_tmp2 <= din_1_tmp1;
din_2_tmp1 <= din_2_reg;
din_2_tmp2 <= din_2_tmp1;
if ((din_1_reg[15]) == 1'b0) begin
addin_1 <= din_1_reg;
end else begin
addin_1 <= 16'b0000000000000000 - din_1_reg;
end
if ((din_2_reg[15]) == 1'b0) begin
addin_2 <= din_2_reg + 16'b0000000000000001;
end else begin
addin_2 <= 16'b0000000000000001 - din_2_reg;
end
add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2});
end
endmodule
| 6.699338 |
module my_wrapper_divider (
rst,
clk,
data_in_a,
data_in_b,
data_out
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
parameter S4 = 2'b11;
input rst;
input clk;
input [INPUT_WIDTH_A-1:0] data_in_a;
input [INPUT_WIDTH_B-1:0] data_in_b;
output [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] Remainder;
reg start, LA, EB;
wire Done;
reg [1:0] y, Y;
my_divider my_divider_inst (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
always @(posedge clk or negedge rst) begin
if (rst == 0) y <= S1;
else y <= Y;
end
always @(y) begin
case (y)
S1: begin
LA = 0;
EB = 0;
start = 0;
Y = S2;
end
S2: begin
LA = 1;
EB = 1;
start = 0;
Y = S3;
end
S3: begin
LA = 0;
EB = 0;
start = 1;
Y = S4;
end
S4: begin
LA = 0;
EB = 0;
start = 0;
if (Done == 1'b1) begin
Y = S1;
end else begin
Y = S4;
end
end
endcase
end
endmodule
| 7.258611 |
module my_divider (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter LOGN = 3'b100;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
input clk;
input [INPUT_WIDTH_A-1:0] data_in_a;
input [INPUT_WIDTH_B-1:0] data_in_b;
input rst;
input start;
input LA;
input EB;
output [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] data_out;
output [OUTPUT_WIDTH-1:0] Remainder;
reg [OUTPUT_WIDTH-1:0] Remainder;
output Done;
reg Done;
wire Cout, zero;
wire [INPUT_WIDTH_A-1:0] Sum;
reg [1:0] y, Y;
reg [LOGN-1:0] Count;
reg EA, Rsel, LR, ER, ER0, LC, EC;
reg [INPUT_WIDTH_B-1:0] RegB;
reg [INPUT_WIDTH_A-1:0] DataA;
reg ff0;
always @(start or y or zero) begin
case (y)
S1: begin
if (start == 0) Y = S1;
else Y = S2;
end
S2: begin
if (zero == 0) Y = S2;
else Y = S3;
end
S3: begin
if (start == 1) Y = S3;
else Y = S1;
end
default: begin
Y = 2'b00;
end
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 0) y <= S1;
else y <= Y;
end
always @(y or start or Cout or zero) begin
case (y)
S1: begin
LC = 1;
ER = 1;
EC = 0;
Rsel = 0;
Done = 0;
if (start == 0) begin
LR = 1;
ER0 = 1;
EA = 0;
end else begin
LR = 0;
EA = 1;
ER0 = 1;
end
end
S2: begin
LC = 0;
ER = 1;
Rsel = 1;
Done = 0;
ER0 = 1;
EA = 1;
if (Cout) LR = 1;
else LR = 0;
if (zero == 0) EC = 1;
else EC = 0;
end
S3: begin
Done = 1;
LR = 0;
LC = 0;
ER = 0;
EC = 0;
Rsel = 0;
ER0 = 0;
EA = 0;
end
default: begin
Done = 0;
LR = 0;
LC = 0;
ER = 0;
EC = 0;
Rsel = 0;
ER0 = 0;
EA = 0;
end
endcase
end
always @(posedge clk) begin
if (rst == 1) begin
RegB <= 0;
Remainder <= 0;
DataA <= 0;
ff0 <= 0;
Count <= 0;
end else begin
if (EB == 1) begin
RegB <= data_in_b;
end else begin
RegB <= RegB;
end
if (LR == 1) begin
Remainder <= Rsel ? Sum : 0;
end else if (ER == 1) begin
Remainder <= (Remainder << 1) | ff0;
end else begin
Remainder <= Remainder;
end
if (LA == 1) begin
DataA <= data_in_a;
end else if (EA == 1) begin
DataA <= (DataA << 1) | Cout;
end else begin
DataA <= DataA;
end
if (ER0 == 1) begin
ff0 <= DataA[INPUT_WIDTH_A-1];
end else begin
ff0 <= 0;
end
if (LC == 1) begin
Count <= 0;
end else if (EC == 1) begin
Count <= Count + 1;
end else begin
Count <= Count;
end
end
end
assign zero = (Count == 0);
assign Sum = {Remainder, ff0} + (~RegB + 1);
assign Cout = Sum[INPUT_WIDTH_A-1:0];
assign data_out = DataA;
endmodule
| 7.482014 |
module my_fir_f1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=29,101,-15,-235,-15,101,29;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_b) +
(n_delay_reg1 * `COEF1_b) +
(n_delay_reg2 * `COEF2_b) +
(n_delay_reg3 * `COEF3_b) +
(n_delay_reg4 * `COEF4_b) +
(n_delay_reg5 * `COEF5_b) +
(n_delay_reg6 * `COEF6_b);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.162286 |
module my_fir_f2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_c) +
(n_delay_reg1 * `COEF1_c) +
(n_delay_reg2 * `COEF2_c) +
(n_delay_reg3 * `COEF3_c) +
(n_delay_reg4 * `COEF4_c) +
(n_delay_reg5 * `COEF5_c) +
(n_delay_reg6 * `COEF6_c);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.093413 |
module my_fir_f3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-12,-77,-148,0,148,77,12;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_d) +
(n_delay_reg1 * `COEF1_d) +
(n_delay_reg2 * `COEF2_d) +
(n_delay_reg4 * `COEF4_d) +
(n_delay_reg5 * `COEF5_d) +
(n_delay_reg6 * `COEF6_d);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.589128 |
module my_fir_h1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-15,25,193,0,-193,-25,15;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_1) +
(n_delay_reg1 * `COEF1_1) +
(n_delay_reg2 * `COEF2_1) +
(n_delay_reg4 * `COEF4_1) +
(n_delay_reg5 * `COEF5_1) +
(n_delay_reg6 * `COEF6_1);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.258261 |
module my_fir_h2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_2) +
(n_delay_reg1 * `COEF1_2) +
(n_delay_reg2 * `COEF2_2) +
(n_delay_reg3 * `COEF3_2) +
(n_delay_reg4 * `COEF4_2) +
(n_delay_reg5 * `COEF5_2) +
(n_delay_reg6 * `COEF6_2);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.118788 |
module my_fir_h3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_3) +
(n_delay_reg1 * `COEF1_3) +
(n_delay_reg2 * `COEF2_3) +
(n_delay_reg4 * `COEF4_3) +
(n_delay_reg5 * `COEF5_3) +
(n_delay_reg6 * `COEF6_3);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.61466 |
module my_fir_h4 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [WIDTH - 1:0] n_delay_reg1;
reg [WIDTH - 1:0] n_delay_reg2;
reg [WIDTH - 1:0] n_delay_reg3;
reg [WIDTH - 1:0] n_delay_reg4;
reg [WIDTH - 1:0] n_delay_reg5;
reg [WIDTH - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_4) +
(n_delay_reg1 * `COEF1_4) +
(n_delay_reg2 * `COEF2_4) +
(n_delay_reg4 * `COEF4_4) +
(n_delay_reg5 * `COEF5_4) +
(n_delay_reg6 * `COEF6_4);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.756091 |
module dff1 (
output bit_t q,
input bit_t,
d,
clk,
resetb
);
always_ff @(posedge clk, negedge resetb) begin
if (!resetb) q <= 0;
else q <= d;
end
endmodule
| 6.627306 |
module mux3c (
output reg y,
input [1:0] sel,
input a,
b,
c
);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule
| 7.807275 |
module wb_env_top_mod ();
logic clk;
logic rst;
// Clock Generation
parameter sim_cycle = 10;
// Reset Delay Parameter
parameter rst_delay = 10;
initial begin
clk = 0;
#10;
forever clk = #(sim_cycle / 2) ~clk;
#10000 $finish;
end
wb_master_if mast_if (
clk,
rst
);
wb_slave_if slave_if (
clk,
rst
);
wb_env_tb_mod test ();
dut dut (
mast_if,
slave_if
);
//Driver reset depending on rst_delay
initial begin
clk = 0;
rst = 0;
#5 rst = 1;
repeat (rst_delay) @(clk);
rst = 1'b0;
@(clk);
end
endmodule
| 7.074495 |
module sw6 (
input [7:0] a,
output reg [2:0] y
);
// With 1 volt/step, step size is approximately 51/volt.
// Thresholds pick the midpoints between voltage ranges.
localparam THRESHOLD_0_1 = 26; // 0-1 volts
localparam THRESHOLD_1_2 = 76; // 1-2 volts
localparam THRESHOLD_2_3 = 127; // 2-3 volts
localparam THRESHOLD_3_4 = 178; // 3-4 volts
localparam THRESHOLD_4_5 = 230; // 4-5 volts
always @(a)
if (a < THRESHOLD_0_1) y = 3'b000;
else if (a < THRESHOLD_1_2) y = 3'b001;
else if (a < THRESHOLD_2_3) y = 3'b010;
else if (a < THRESHOLD_3_4) y = 3'b011;
else if (a < THRESHOLD_4_5) y = 3'b100;
else y = 3'b101;
endmodule
| 6.65049 |
module SW7seg (
SW,
HEX0
);
input [3:0] SW;
output [6:0] HEX0;
// Your code for Phase 2 goes here. Be sure to check the Slide Set 2 notes,
// since one of the slides almost gives away the answer here. I wrote this as
// a single combinational always block containing a single case statement, but
// there are other ways to do it.
always_comb
case (SW)
4'b0000: HEX0 = 7'b1111111; // 0: blank
4'b0001: HEX0 = 7'b0001000; // 1: Ace
4'b0010: HEX0 = 7'b0100100; // 2
4'b0011: HEX0 = 7'b0110000; // 3
4'b0100: HEX0 = 7'b0011001; // 4
4'b0101: HEX0 = 7'b0010010; // 5
4'b0110: HEX0 = 7'b0000010; // 6
4'b0111: HEX0 = 7'b1111000; // 7
4'b1000: HEX0 = 7'b0000000; // 8
4'b1001: HEX0 = 7'b0010000; // 9
4'b1010: HEX0 = 7'b1000000; // 10
4'b1011: HEX0 = 7'b1100001; // Jack
4'b1100: HEX0 = 7'b0011000; // Queen
4'b1101: HEX0 = 7'b0001001; // King
default: HEX0 = 7'b1111111; // default: blank
endcase
endmodule
| 8.016256 |
module SwAlloc2x1 (
input wire clk,
input wire rstn,
input wire ValidA_i,
input wire [31:0] DataA_i,
output wire ReadyA_o,
input wire ValidB_i,
input wire [31:0] DataB_i,
output wire ReadyB_o,
input wire FifoFull_i,
output wire [31:0] FifoWrData_o,
output wire FifoWr_o
);
wire [1:0] FlitTpye;
assign FlitTpye = FifoWrData_o[31:30];
wire HeadFlit, TailFlit;
assign HeadFlit = FlitTpye == 2'b00;
assign TailFlit = FlitTpye == 2'b11;
wire [1:0] Grant;
assign Grant = ValidA_i ? 2'b01 : (ValidB_i ? 2'b10 : 2'b00);
reg Occupy = 1'b0;
reg [1:0] GrantReg = 2'b00;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
Occupy <= 1'b0;
GrantReg <= 2'b00;
end else begin
if (Occupy) begin
if (FifoWr_o & TailFlit) begin
Occupy <= 1'b0;
end
end else begin
if (FifoWr_o & HeadFlit) begin
Occupy <= 1'b1;
GrantReg <= Grant;
end
end
end
end
assign FifoWr_o = ~FifoFull_i & (
(ValidA_i & ((Occupy & GrantReg[0]) | (~Occupy & Grant[0]))) |
(ValidB_i & ((Occupy & GrantReg[1]) | (~Occupy & Grant[1]))) );
assign FifoWrData_o = (DataA_i & {32{(Occupy & GrantReg[0]) | (~Occupy & Grant[0])}}) |
(DataB_i & {32{(Occupy & GrantReg[1]) | (~Occupy & Grant[1])}}) ;
assign ReadyA_o = ~FifoFull_i & ((Occupy & GrantReg[0]) | (~Occupy & Grant[0]));
assign ReadyB_o = ~FifoFull_i & ((Occupy & GrantReg[1]) | (~Occupy & Grant[1]));
endmodule
| 7.324019 |
module SwAlloc3x1 (
input wire clk,
input wire rstn,
input wire ValidA_i,
input wire [31:0] DataA_i,
output wire ReadyA_o,
input wire ValidB_i,
input wire [31:0] DataB_i,
output wire ReadyB_o,
input wire ValidC_i,
input wire [31:0] DataC_i,
output wire ReadyC_o,
input wire FifoFull_i,
output wire [31:0] FifoWrData_o,
output wire FifoWr_o
);
wire [1:0] FlitTpye;
assign FlitTpye = FifoWrData_o[31:30];
wire HeadFlit, TailFlit;
assign HeadFlit = FlitTpye == 2'b00;
assign TailFlit = FlitTpye == 2'b11;
wire [2:0] Grant;
assign Grant = ValidA_i ? 3'b001 : (ValidB_i ? 3'b010 : (ValidC_i ? 3'b100 : 3'b000));
reg Occupy = 1'b0;
reg [2:0] GrantReg = 3'b000;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
Occupy <= 1'b0;
GrantReg <= 3'b000;
end else begin
if (Occupy) begin
if (FifoWr_o & TailFlit) begin
Occupy <= 1'b0;
end
end else begin
if (FifoWr_o & HeadFlit) begin
Occupy <= 1'b1;
GrantReg <= Grant;
end
end
end
end
assign FifoWr_o = ~FifoFull_i & (
(ValidA_i & ((Occupy & GrantReg[0]) | (~Occupy & Grant[0]))) |
(ValidB_i & ((Occupy & GrantReg[1]) | (~Occupy & Grant[1]))) |
(ValidC_i & ((Occupy & GrantReg[2]) | (~Occupy & Grant[2]))) );
assign FifoWrData_o = (DataA_i & {32{(Occupy & GrantReg[0]) | (~Occupy & Grant[0])}}) |
(DataB_i & {32{(Occupy & GrantReg[1]) | (~Occupy & Grant[1])}}) |
(DataC_i & {32{(Occupy & GrantReg[2]) | (~Occupy & Grant[2])}}) ;
assign ReadyA_o = ~FifoFull_i & ((Occupy & GrantReg[0]) | (~Occupy & Grant[0]));
assign ReadyB_o = ~FifoFull_i & ((Occupy & GrantReg[1]) | (~Occupy & Grant[1]));
assign ReadyC_o = ~FifoFull_i & ((Occupy & GrantReg[2]) | (~Occupy & Grant[2]));
endmodule
| 7.455022 |
module swap (
input a,
b,
output x,
y
);
assign x = a ^ (a ^ b);
assign y = b ^ (a ^ b);
endmodule
| 8.099526 |
modules.
//
// Params: None
//------------------------------------------------------------------------------
module SwapController(
input clock,
input reset,
output reg swap,
input swap_ack,
output reg bg_start,
input bg_start_ack,
input bg_done,
output reg bg_done_ack);
reg bg_done_ack_r;
wire bg_done_edge;
assign bg_done_edge = bg_done_ack & ~bg_done_ack_r;
always @(posedge clock) begin
if(reset) begin
swap <= 1'b0;
bg_start <= 1'b1;
bg_done_ack <= 1'b0;
bg_done_ack_r <= 1'b0;
end else begin
if(bg_start & bg_start_ack)
bg_start <= 1'b0;
else if(swap & swap_ack)
bg_start <= 1'b1;
// Synchronize ack
bg_done_ack <= bg_done;
bg_done_ack_r <= bg_done_ack;
if(swap & swap_ack)
swap <= 1'b0;
else if (bg_done_edge)
swap <= 1'b1;
end
end
endmodule
| 6.877912 |
module performs the swap logic in each round.
module Swapper(
input [31:0] i_LPT,
input [31:0] i_RPT,
output [31:0] o_LPT,
output [31:0] o_RPT
);
assign o_LPT = i_RPT;
assign o_RPT = i_LPT;
endmodule
| 7.634754 |
module swap_data (
a_input,
b_input,
out_sel,
swap_en,
data_out
);
/**
* SWAP DATA REGISTER FILE - swap_data.v
*Inputs:
* -a_input (32bits): Data to be swapped from RS
* -b_input (32bits): Data to be swapped from RT
* -out_sel 1 bit: choose which register to output to multiplexer. multiplexer inputs into rf
* 0 -> swap rs; 1-> swap rt
*OUTPUTS:
* -data_out (32bits): Data chosen to be swapped
*/
input [31:0] a_input;
input [31:0] b_input;
input out_sel;
input swap_en;
reg [31:0] a_reg;
reg [31:0] b_reg;
output [31:0] data_out;
reg [31:0] data_out;
always @(out_sel) begin
if (out_sel == 1'b1) begin
assign data_out = b_reg;
end
if (out_sel == 1'b0) begin
assign data_out = a_reg;
end
end
always @(swap_en) begin
if (swap_en == 1) begin
a_reg <= a_input;
b_reg <= b_input;
end
end
endmodule
| 8.022415 |
module swap_endian #(
parameter UNIT_WIDTH = 8,
parameter UNIT_COUNT = 4
) (
input wire [(UNIT_WIDTH*UNIT_COUNT)-1:0] src,
output reg [(UNIT_WIDTH*UNIT_COUNT)-1:0] dst
);
integer i;
always @* begin
for (i = 0; i < UNIT_COUNT; i = i + 1) begin
dst[(i*UNIT_WIDTH)+:UNIT_WIDTH] = src[((UNIT_COUNT-i)*UNIT_WIDTH-1)-:UNIT_WIDTH];
end
end
endmodule
| 6.594776 |
module swap_endianness #(
parameter WIDTH = 32
) (
input wire [WIDTH-1 : 0] in_vect,
output wire [WIDTH-1 : 0] out_vect
);
localparam WIDTH_BYTES = WIDTH / 8;
generate
genvar i;
for (i = 0; i < WIDTH_BYTES; i = i + 1) begin
assign out_vect[i*8+:8] = in_vect[(WIDTH-1)-(i*8)-:8];
end
endgenerate
endmodule
| 6.877557 |
module swap_fsm (
input clk,
reset_n,
input swap,
output w,
output [1:0] sel
);
reg [1:0] state_reg, state_next;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
// Sequential state register
always @(posedge clk, negedge reset_n) begin
if (~reset_n) state_reg <= s0;
else state_reg <= state_next;
end
// Next state logic
always @(*) begin
state_next = state_reg;
case (state_reg)
s0: if (~swap) state_next = s0;
else state_next = s1;
s1: state_next = s2;
s2: state_next = s3;
s3: state_next = s0;
default: state_next = s0;
endcase
end
// output logic
assign sel = state_reg;
assign w = (state_reg != s0);
endmodule
| 7.249526 |
module swap_reg (
a_input,
b_input,
out_sel,
data_out
);
/**
* SWAP REG REGISTER FILE - swap_reg.v
*Inputs:
* -a_input (4bits): Address of RS
* -b_input (4bits): Address of RT
* -out_sel 1 bit: choose which register to output to multiplexer. multiplexer inputs into rf
* 0 -> swap rs; 1-> swap rt
*OUTPUTS:
* -data_out (4bits): Address of register to be swapped
*/
input [3:0] a_input;
input [3:0] b_input;
input out_sel;
output [3:0] data_out;
reg [3:0] data_out;
always @(a_input, b_input, out_sel) begin
if (out_sel == 1'b0) begin
data_out <= b_input;
end
if (out_sel == 1'b1) begin
data_out <= a_input;
end
end
endmodule
| 7.24337 |
module swap_reg_file #(
parameter ADDR_WIDTH = 7,
DATA_WIDTH = 8
) (
input clk,
reset_n,
input we,
input [ADDR_WIDTH - 1:0] address_w,
address_r,
input [DATA_WIDTH - 1:0] data_w,
output [DATA_WIDTH - 1:0] data_r,
// inputs for swap functionality
input [ADDR_WIDTH - 1:0] address_A,
address_B,
input swap
);
wire [1:0] sel;
wire w;
wire [ADDR_WIDTH - 1:0] MUX_READ_f, MUX_WRITE_f;
reg_file #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) REG_FILE (
.clk(clk),
.we(w ? 1'b1 : we),
.address_w(MUX_WRITE_f),
.address_r(MUX_READ_f),
.data_w(w ? data_r : data_w),
.data_r(data_r)
);
swap_fsm FSM0 (
.clk(clk),
.reset_n(reset_n),
.swap(swap),
.w(w),
.sel(sel)
);
mux_4x1_nbit #(
.N(ADDR_WIDTH)
) MUX_READ (
.w0(address_r),
.w1(address_A),
.w2(address_B),
.w3('b0),
.s (sel),
.f (MUX_READ_f)
);
mux_4x1_nbit #(
.N(ADDR_WIDTH)
) MUX_WRITE (
.w0(address_w),
.w1('b0),
.w2(address_A),
.w3(address_B),
.s (sel),
.f (MUX_WRITE_f)
);
endmodule
| 7.494731 |
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