code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module subr (
input a,
input b,
input c,
output diff,
output borr
);
wire anot;
assign anot = (~a);
assign diff = (a ^ b ^ c);
assign borr = (anot & b) | (b & c) | (c & anot);
endmodule
| 8.270388 |
module subractor #(
parameter dataIN_width = 4
) (
input [dataIN_width - 1 : 0] A,
B,
output reg [ dataIN_width -1 : 0] C
);
always @(A, B) C <= A - B;
endmodule
| 6.544854 |
module TB_SUBREG_TIM_DIV #(
parameter C_C = 10.0
) ();
reg CK;
initial begin
CK <= 1'b1;
forever begin
#(C_C / 2);
CK <= ~CK;
end
end
reg XARST;
initial begin
XARST <= 1'b1;
#(0.1 * C_C);
XARST <= 1'b0;
#(2.1 * C_C);
XARST <= 1'b1;
end
assign ENCBIN_XDIRECT_i = 1'b1; //
SUBREG_TIM_DIV #(
.C_PERIOD_W(3) // Hz
) SUBREG_TIM_DIV (
.CK_i (CK)
, .XARST_i (XARST)
, .PERIOD_i (7)
, .PULSE_N_i(3)
, .EN_CK_o (EN_CK_o)
);
integer TB_CTR;
initial begin
TB_CTR <= 'd0;
repeat (100) begin
repeat (100) @(posedge CK);
TB_CTR <= TB_CTR + 1;
end
$stop;
end
integer CK_CTR;
always @(posedge CK or negedge XARST)
if (~XARST) CK_CTR <= 'd0;
else if (EN_CK_o) CK_CTR <= CK_CTR + 'd1;
endmodule
| 6.817315 |
module subsampling #(
parameter XI_SUBSAMPLE = 1,
parameter YI_SUBSAMPLE = 1,
parameter XO_SUBSAMPLE = 2,
parameter YO_SUBSAMPLE = 2,
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter COLOR_PRECISION = 8,
parameter REGISTER = "YES"
) (
input i_arst,
input i_sysclk,
input i_we,
input [COLOR_PRECISION-1:0] i_color,
output o_we,
output [COLOR_PRECISION-1:0] o_color
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i = 0; 2 ** i < val; i = i + 1) log2 = i + 1;
end
endfunction
wire w_x_subsample;
wire w_y_subsample;
wire [log2(MCU_WIDTH)-1:0] w_mcu_width;
wire [log2(MCU_HEIGHT)-1:0] w_mcu_height;
reg r_x_1P;
reg r_y_1P;
reg [log2(MCU_WIDTH)-1:0] r_w_1P;
reg [log2(MCU_HEIGHT)-1:0] r_h_1P;
reg r_we_1P;
reg [COLOR_PRECISION-1:0] r_color_1P;
wire w_we_0P;
wire [COLOR_PRECISION-1:0] w_color_0P;
assign w_x_subsample = XO_SUBSAMPLE / XI_SUBSAMPLE - 1'b1;
assign w_y_subsample = YO_SUBSAMPLE / YI_SUBSAMPLE - 1'b1;
assign w_mcu_width = MCU_WIDTH - 1'b1;
assign w_mcu_height = MCU_HEIGHT - 1'b1;
assign w_we_0P = (r_y_1P == 1'b0 && r_x_1P == 1'b0) ? i_we : 1'b0;
assign w_color_0P = i_color;
always @(posedge i_arst or posedge i_sysclk) begin
if (i_arst) begin
r_x_1P <= 1'b0;
r_y_1P <= 1'b0;
r_w_1P <= {log2(MCU_WIDTH) {1'b0}};
r_h_1P <= {log2(MCU_HEIGHT) {1'b0}};
r_we_1P <= 1'b0;
r_color_1P <= {COLOR_PRECISION{1'b0}};
end else begin
if (i_we) begin
r_x_1P <= r_x_1P + 1'b1;
r_w_1P <= r_w_1P + 1'b1;
if (r_x_1P == w_x_subsample) r_x_1P <= 1'b0;
if (r_w_1P == w_mcu_width) begin
r_w_1P <= {log2(MCU_WIDTH) {1'b0}};
r_y_1P <= r_y_1P + 1'b1;
r_h_1P <= r_h_1P + 1'b1;
if (r_y_1P == w_y_subsample) r_y_1P <= 1'b0;
if (r_h_1P == w_mcu_height) r_h_1P <= {log2(MCU_HEIGHT) {1'b0}};
end
end
r_we_1P <= w_we_0P;
r_color_1P <= w_color_0P;
end
end
generate
if (REGISTER == "YES") begin
assign o_we = r_we_1P;
assign o_color = r_color_1P;
end else begin
assign o_we = w_we_0P;
assign o_color = w_color_0P;
end
endgenerate
endmodule
| 6.78233 |
module subservient #( //Memory parameters
parameter memsize = 512,
parameter aw = $clog2(memsize),
//Enable CSR + interrupts
parameter WITH_CSR = 0
) (
input wire i_clk,
input wire i_rst,
//SRAM interface
output wire [aw-1:0] o_sram_waddr,
output wire [7:0] o_sram_wdata,
output wire o_sram_wen,
output wire [aw-1:0] o_sram_raddr,
input wire [7:0] i_sram_rdata,
output wire o_sram_ren,
//Debug interface
input wire i_debug_mode,
input wire [31:0] i_wb_dbg_adr,
input wire [31:0] i_wb_dbg_dat,
input wire [3:0] i_wb_dbg_sel,
input wire i_wb_dbg_we,
input wire i_wb_dbg_stb,
output wire [31:0] o_wb_dbg_rdt,
output wire o_wb_dbg_ack,
//External I/O
output wire o_gpio
);
wire [31:0] wb_core_adr;
wire [31:0] wb_core_dat;
wire [3:0] wb_core_sel;
wire wb_core_we;
wire wb_core_stb;
wire [31:0] wb_core_rdt;
wire wb_core_ack;
wire wb_gpio_rdt;
assign wb_core_rdt = {31'd0, wb_gpio_rdt};
subservient_gpio gpio (
.i_wb_clk(i_clk),
.i_wb_rst(i_rst),
.i_wb_dat(wb_core_dat[0]),
.i_wb_we (wb_core_we),
.i_wb_stb(wb_core_stb),
.o_wb_rdt(wb_gpio_rdt),
.o_wb_ack(wb_core_ack),
.o_gpio (o_gpio)
);
subservient_core #(
.memsize (memsize),
.WITH_CSR(WITH_CSR)
) core (
.i_clk (i_clk),
.i_rst (i_rst),
.i_timer_irq(1'b0),
//SRAM interface
.o_sram_waddr(o_sram_waddr),
.o_sram_wdata(o_sram_wdata),
.o_sram_wen (o_sram_wen),
.o_sram_raddr(o_sram_raddr),
.i_sram_rdata(i_sram_rdata),
.o_sram_ren (o_sram_ren),
//Debug interface
.i_debug_mode(i_debug_mode),
.i_wb_dbg_adr(i_wb_dbg_adr),
.i_wb_dbg_dat(i_wb_dbg_dat),
.i_wb_dbg_sel(i_wb_dbg_sel),
.i_wb_dbg_we (i_wb_dbg_we),
.i_wb_dbg_stb(i_wb_dbg_stb),
.o_wb_dbg_rdt(o_wb_dbg_rdt),
.o_wb_dbg_ack(o_wb_dbg_ack),
//Peripheral interface
.o_wb_adr(wb_core_adr),
.o_wb_dat(wb_core_dat),
.o_wb_sel(wb_core_sel),
.o_wb_we (wb_core_we),
.o_wb_stb(wb_core_stb),
.i_wb_rdt(wb_core_rdt),
.i_wb_ack(wb_core_ack)
);
endmodule
| 8.153472 |
module subservient_debug_switch ( //Debug selector
input wire i_debug_mode,
//Debug interface
input wire [31:0] i_wb_dbg_adr,
input wire [31:0] i_wb_dbg_dat,
input wire [ 3:0] i_wb_dbg_sel,
input wire i_wb_dbg_we,
input wire i_wb_dbg_stb,
output wire [31:0] o_wb_dbg_rdt,
output wire o_wb_dbg_ack,
//Data bus interface towards CPU
input wire [31:0] i_wb_dbus_adr,
input wire [31:0] i_wb_dbus_dat,
input wire [ 3:0] i_wb_dbus_sel,
input wire i_wb_dbus_we,
input wire i_wb_dbus_stb,
output wire [31:0] o_wb_dbus_rdt,
output wire o_wb_dbus_ack,
//Data bus interface towards memory/peripherals
output wire [31:0] o_wb_mux_adr,
output wire [31:0] o_wb_mux_dat,
output wire [ 3:0] o_wb_mux_sel,
output wire o_wb_mux_we,
output wire o_wb_mux_stb,
input wire [31:0] i_wb_mux_rdt,
input wire i_wb_mux_ack
);
assign o_wb_dbg_rdt = i_wb_mux_rdt;
assign o_wb_dbg_ack = i_wb_mux_ack & i_debug_mode;
assign o_wb_dbus_rdt = i_wb_mux_rdt;
assign o_wb_dbus_ack = i_wb_mux_ack & !i_debug_mode;
assign o_wb_mux_adr = i_debug_mode ? i_wb_dbg_adr : i_wb_dbus_adr;
assign o_wb_mux_dat = i_debug_mode ? i_wb_dbg_dat : i_wb_dbus_dat;
assign o_wb_mux_sel = i_debug_mode ? i_wb_dbg_sel : i_wb_dbus_sel;
assign o_wb_mux_we = i_debug_mode ? i_wb_dbg_we : i_wb_dbus_we;
assign o_wb_mux_stb = i_debug_mode ? i_wb_dbg_stb : i_wb_dbus_stb;
endmodule
| 8.522888 |
module subservient_fpga (
input wire i_clk,
input wire i_rst,
output wire q
);
parameter memfile = "hello.hex";
parameter memsize = 1024;
localparam aw = $clog2(memsize);
wire clk;
wire rst;
wire [aw-1:0] sram_waddr;
wire [ 7:0] sram_wdata;
wire sram_wen;
wire [aw-1:0] sram_raddr;
wire [ 7:0] sram_rdata;
wire sram_ren;
subservient_fpga_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(i_rst),
.o_clk(clk),
.o_rst(rst)
);
subservient_generic_ram #(
.depth (memsize),
.memfile(memfile)
) memory (
.i_clk (clk),
.i_rst (rst),
.i_waddr(sram_waddr),
.i_wdata(sram_wdata),
.i_wen (sram_wen),
.i_raddr(sram_raddr),
.o_rdata(sram_rdata),
.i_ren (sram_ren)
);
subservient #(
.memsize (memsize),
.WITH_CSR(0)
) dut ( // Clock & reset
.i_clk(clk),
.i_rst(rst),
//SRAM interface
.o_sram_waddr(sram_waddr),
.o_sram_wdata(sram_wdata),
.o_sram_wen (sram_wen),
.o_sram_raddr(sram_raddr),
.i_sram_rdata(sram_rdata),
.o_sram_ren (sram_ren),
//Debug interface
.i_debug_mode(1'b0),
.i_wb_dbg_adr(32'd0),
.i_wb_dbg_dat(32'd0),
.i_wb_dbg_sel(4'd0),
.i_wb_dbg_we (1'd0),
.i_wb_dbg_stb(1'd0),
.o_wb_dbg_rdt(),
.o_wb_dbg_ack(),
// External I/O
.o_gpio(q)
);
endmodule
| 7.119097 |
module subservient_fpga_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
assign o_clk = i_clk;
always @(posedge i_clk) o_rst <= i_rst;
endmodule
| 7.119097 |
module subservient_generic_ram #(
parameter depth = 0,
parameter aw = $clog2(depth),
parameter memfile = ""
) (
input wire i_clk,
input wire i_rst,
//SRAM interface
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata,
input wire i_ren
);
reg [7:0] mem[0:depth-1] /* verilator public */;
always @(posedge i_clk) begin
if (i_wen) mem[i_waddr] <= i_wdata;
o_rdata <= i_ren ? mem[i_raddr] : 8'bx;
end
initial
if (|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
endmodule
| 8.499675 |
module subservient_gpio (
input wire i_wb_clk,
input wire i_wb_rst,
input wire i_wb_dat,
input wire i_wb_we,
input wire i_wb_stb,
output reg o_wb_rdt,
output reg o_wb_ack,
output reg o_gpio
);
always @(posedge i_wb_clk) begin
o_wb_rdt <= o_gpio;
if (i_wb_stb & i_wb_we) o_gpio <= i_wb_dat;
o_wb_ack <= i_wb_stb & !o_wb_ack;
if (i_wb_rst) begin
o_wb_ack <= 1'b0;
o_gpio <= 1'b0;
end
end
endmodule
| 8.499675 |
module subservient_fpga_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKFBOUT_MULT(16),
.CLKOUT0_DIVIDE(50),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(o_clk), //100MHz*16/50 = 32 MHz
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(!i_rst),
.CLKFBIN(clkfb)
);
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule
| 7.119097 |
module subservient_openram_if (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
output wire csb0,
output wire web0,
output wire [3:0] wmask0,
output wire [aw-3:0] addr0,
output wire [32:0] din0,
input wire [32:0] dout0,
input la_data_in,
output io_out,
output io_oeb,
output [2:0] irq
);
localparam memsize = 1024;
localparam aw = $clog2(memsize);
wire [aw-1:0] sram_waddr;
wire [7:0] sram_wdata;
wire sram_wen;
wire [aw-1:0] sram_raddr;
wire [7:0] sram_rdata;
wire sram_ren;
assign io_oeb = wb_rst_i;
assign irq = 3'b000;
//Adapt the 8-bit SRAM interface from subservient to the 32-bit OpenRAM instance
sram_width_converter sram_width_converter (
.i_clk (wb_clk_i),
//8-bit Subservient interface
.i_sram_waddr (sram_waddr),
.i_sram_wdata (sram_wdata),
.i_sram_wen (sram_wen),
.i_sram_raddr (sram_raddr),
.o_sram_rdata (sram_rdata),
.i_sram_ren (sram_ren),
//32-bit OpenRAM interface
.o_csb0 (csb0),
.o_web0 (web0),
.o_wmask0 (wmask0),
.o_addr0 (addr0),
.o_din0 (din0),
.i_dout0 (dout0)
);
subservient #(
.memsize(memsize),
.aw(aw)
) subservient_inst ( // Clock & reset
.i_clk (wb_clk_i),
.i_rst (wb_rst_i),
//SRAM interface
.o_sram_waddr (sram_waddr),
.o_sram_wdata (sram_wdata),
.o_sram_wen (sram_wen),
.o_sram_raddr (sram_raddr),
.i_sram_rdata (sram_rdata),
.o_sram_ren (sram_ren),
//Debug interface
.i_debug_mode (~la_data_in),
.i_wb_dbg_adr (wbs_adr_i),
.i_wb_dbg_dat (wbs_dat_i),
.i_wb_dbg_sel (wbs_sel_i),
.i_wb_dbg_we (wbs_we_i),
.i_wb_dbg_stb (wbs_stb_i),
.o_wb_dbg_rdt (wbs_dat_o),
.o_wb_dbg_ack (wbs_ack_o),
// External I/O
.o_gpio (io_out)
);
endmodule
| 9.413267 |
module subservient_ram #( //Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth)
) (
input wire i_clk,
input wire i_rst,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output wire [7:0] o_rdata,
input wire i_ren,
output wire [aw-1:0] o_sram_waddr,
output wire [7:0] o_sram_wdata,
output wire o_sram_wen,
output wire [aw-1:0] o_sram_raddr,
input wire [7:0] i_sram_rdata,
output wire o_sram_ren,
input wire [aw-1:2] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_stb,
output wire [31:0] o_wb_rdt,
output reg o_wb_ack
);
reg [aw-1:0] rf_waddr_r;
reg [7:0] rf_wdata_r;
reg rf_wen_r;
reg [1:0] bsel;
wire wb_en = i_wb_stb & !rf_wen_r & !o_wb_ack;
wire wb_we = i_wb_we & i_wb_sel[bsel];
assign o_sram_waddr = wb_en ? {i_wb_adr[aw-1:2], bsel} : rf_waddr_r;
assign o_sram_wdata = wb_en ? i_wb_dat[bsel*8+:8] : rf_wdata_r;
assign o_sram_wen = wb_en ? wb_we : rf_wen_r;
assign o_sram_raddr = wb_en ? {i_wb_adr[aw-1:2], bsel} : i_raddr;
assign o_sram_ren = wb_en ? !i_wb_we : i_ren;
reg [23:0] wb_rdt;
assign o_wb_rdt = {i_sram_rdata, wb_rdt};
reg regzero;
always @(posedge i_clk) begin
rf_waddr_r <= i_waddr;
rf_wdata_r <= i_wdata;
rf_wen_r <= i_wen;
if (wb_en) bsel <= bsel + 2'd1;
o_wb_ack <= wb_en & &bsel;
if (bsel == 2'b01) wb_rdt[7:0] <= i_sram_rdata;
if (bsel == 2'b10) wb_rdt[15:8] <= i_sram_rdata;
if (bsel == 2'b11) wb_rdt[23:16] <= i_sram_rdata;
if (i_rst) begin
bsel <= 2'd0;
o_wb_ack <= 1'b0;
end
regzero <= &i_raddr[aw-1:2];
end
assign o_rdata = regzero ? 8'd0 : i_sram_rdata;
endmodule
| 7.296578 |
module subservient_rf_ram_if #(
parameter width = 8,
parameter reset_strategy = "MINI",
parameter csr_regs = 4,
parameter depth = 32 * (32 + csr_regs) / width,
parameter l2w = $clog2(width)
) (
//SERV side
input wire i_clk,
input wire i_rst,
input wire i_wreq,
input wire i_rreq,
output wire o_ready,
input wire [$clog2(32+csr_regs)-1:0] i_wreg0,
input wire [$clog2(32+csr_regs)-1:0] i_wreg1,
input wire i_wen0,
input wire i_wen1,
input wire i_wdata0,
input wire i_wdata1,
input wire [$clog2(32+csr_regs)-1:0] i_rreg0,
input wire [$clog2(32+csr_regs)-1:0] i_rreg1,
output wire o_rdata0,
output wire o_rdata1,
//RAM side
output wire [ $clog2(depth)-1:0] o_waddr,
output wire [ width-1:0] o_wdata,
output wire o_wen,
output wire [ $clog2(depth)-1:0] o_raddr,
input wire [ width-1:0] i_rdata,
output wire o_ren
);
reg rgnt;
assign o_ready = rgnt | i_wreq;
reg [ 4:0] rcnt;
/*
********** Write side ***********
*/
wire [ 4:0] wcnt;
reg [width-2:0] wdata0_r;
reg [width-1:0] wdata1_r;
reg wen0_r;
reg wen1_r;
wire wtrig0;
wire wtrig1;
generate
if (width == 2) begin
assign wtrig0 = ~wcnt[0];
assign wtrig1 = wcnt[0];
end else begin
reg wtrig0_r;
always @(posedge i_clk) wtrig0_r <= wtrig0;
assign wtrig0 = (wcnt[l2w-1:0] == {{l2w - 1{1'b1}}, 1'b0});
assign wtrig1 = wtrig0_r;
end
endgenerate
assign o_wdata = wtrig1 ? wdata1_r : {i_wdata0, wdata0_r};
wire [$clog2(32+csr_regs)-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0;
generate
if (width == 32) assign o_waddr = wreg;
else assign o_waddr = {wreg, wcnt[4:l2w]};
endgenerate
assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r);
generate
if (width > 2) always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]};
else always @(posedge i_clk) wdata0_r <= i_wdata0;
endgenerate
assign wcnt = rcnt - 3;
always @(posedge i_clk) begin
wen0_r <= i_wen0;
wen1_r <= i_wen1;
wdata1_r <= {i_wdata1, wdata1_r[width-1:1]};
end
/*
********** Read side ***********
*/
wire rtrig0;
reg rtrig1;
wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
generate
if (width == 32) assign o_raddr = rreg;
else assign o_raddr = {rreg, rcnt[4:l2w]};
endgenerate
reg [width-1:0] rdata0;
reg [width-2:0] rdata1;
reg rgate;
reg rvalid;
assign o_rdata0 = rvalid & rdata0[0];
assign o_rdata1 = rvalid & (rtrig1 ? i_rdata[0] : rdata1[0]);
assign rtrig0 = (rcnt[l2w-1:0] == 1);
assign o_ren = rgate & ((rcnt[l2w-1:0] == 0) | rtrig0);
reg rreq_r;
generate
if (width > 2)
always @(posedge i_clk) begin
rdata1 <= {1'b0, rdata1[width-2:1]}; //Optimize?
if (rtrig1) rdata1[width-2:0] <= i_rdata[width-1:1];
end
else always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
endgenerate
always @(posedge i_clk) begin
if (o_ready) rvalid <= rgate;
if (&rcnt) rgate <= 1'b0;
else if (i_rreq) rgate <= 1'b1;
rtrig1 <= rtrig0;
rcnt <= rcnt + 5'd1;
if (i_rreq) rcnt <= 5'd0;
if (i_wreq) rcnt <= 5'd2;
rreq_r <= i_rreq;
rgnt <= rreq_r;
rdata0 <= {1'b0, rdata0[width-1:1]};
if (rtrig0) rdata0 <= i_rdata;
if (i_rst) begin
if (reset_strategy != "NONE") begin
rgate <= 1'b0;
rcnt <= 5'd2;
rgnt <= 1'b0;
rreq_r <= 1'b0;
end
end
end
endmodule
| 7.296578 |
module subservient_tb;
parameter memfile = "";
parameter memsize = 8192;
parameter with_csr = 0;
parameter aw = $clog2(memsize);
reg clk = 1'b0;
reg rst = 1'b1;
wire [aw-1:0] sram_waddr;
wire [7:0] sram_wdata;
wire sram_wen;
wire [aw-1:0] sram_raddr;
wire [7:0] sram_rdata;
wire sram_ren;
//Debug interface
reg debug_mode;
reg [31:0] wb_dbg_adr;
reg [31:0] wb_dbg_dat;
reg [3:0] wb_dbg_sel;
reg wb_dbg_we;
reg wb_dbg_stb = 1'b0;
wire [31:0] wb_dbg_rdt;
wire wb_dbg_ack;
wire q;
always #5 clk <= !clk;
initial #62 rst <= 1'b0;
vlog_tb_utils vtu ();
integer baudrate = 0;
initial begin
if ($value$plusargs("uart_baudrate=%d", baudrate))
$display("UART decoder using baud rate %0d", baudrate);
else forever @(q) $display("%0t output o_gpio is %s", $time, q ? "ON" : "OFF");
end
reg [1023:0] firmware_file;
integer idx = 0;
reg [7:0] mem[0:memsize-1];
task wb_dbg_write32(input [31:0] adr, input [31:0] dat);
begin
@(posedge clk) begin
wb_dbg_adr <= adr;
wb_dbg_dat <= dat;
wb_dbg_sel <= 4'b1111;
wb_dbg_we <= 1'b1;
wb_dbg_stb <= 1'b1;
end
while (!wb_dbg_ack) @(posedge clk);
wb_dbg_stb <= 1'b0;
end
endtask
reg [31:0] tmp_dat;
integer adr;
reg [1:0] bsel;
initial begin
$display("Setting debug mode");
debug_mode <= 1'b1;
if ($value$plusargs("firmware=%s", firmware_file)) begin
$display("Writing %0s to SRAM", firmware_file);
$readmemh(firmware_file, mem);
end else $display("No application to load. SRAM will be empty");
repeat (10) @(posedge clk);
//Write full 32-bit words
while ((mem[idx] !== 8'bxxxxxxxx) && (idx < memsize)) begin
adr = (idx >> 2) * 4;
bsel = idx[1:0];
tmp_dat[bsel*8+:8] = mem[idx];
if (bsel == 2'd3) wb_dbg_write32(adr, tmp_dat);
idx = idx + 1;
end
//Zero-pad final word if required
if (idx[1:0]) begin
adr = (idx >> 2) * 4;
bsel = idx[1:0];
if (bsel == 1) tmp_dat[31:8] = 24'd0;
if (bsel == 2) tmp_dat[31:16] = 16'd0;
if (bsel == 3) tmp_dat[31:24] = 8'd0;
wb_dbg_write32(adr, tmp_dat);
end
repeat (10) @(posedge clk);
$display("Done writing %0d bytes to SRAM. Turning off debug mode", idx);
debug_mode <= 1'b0;
end
uart_decoder uart_decoder (
baudrate,
q
);
subservient_generic_ram #(
.depth(memsize)
) memory (
.i_clk (clk),
.i_rst (rst),
.i_waddr(sram_waddr),
.i_wdata(sram_wdata),
.i_wen (sram_wen),
.i_raddr(sram_raddr),
.o_rdata(sram_rdata),
.i_ren (sram_ren)
);
//Note: This should probably be a proper assert instead
always @(posedge clk)
if (sram_ren & sram_wen)
$display("$0t Error: Simultaneous SRAM read and write", $time);
subservient #(
.memsize (memsize),
.WITH_CSR(with_csr)
) dut ( // Clock & reset
.i_clk(clk),
.i_rst(rst),
//SRAM interface
.o_sram_waddr(sram_waddr),
.o_sram_wdata(sram_wdata),
.o_sram_wen (sram_wen),
.o_sram_raddr(sram_raddr),
.i_sram_rdata(sram_rdata),
.o_sram_ren (sram_ren),
//Debug interface
.i_debug_mode(debug_mode),
.i_wb_dbg_adr(wb_dbg_adr),
.i_wb_dbg_dat(wb_dbg_dat),
.i_wb_dbg_sel(wb_dbg_sel),
.i_wb_dbg_we (wb_dbg_we),
.i_wb_dbg_stb(wb_dbg_stb),
.o_wb_dbg_rdt(wb_dbg_rdt),
.o_wb_dbg_ack(wb_dbg_ack),
// External I/O
.o_gpio(q)
);
endmodule
| 7.118656 |
module subservient_wrapped (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
input la_data_in,
output io_out,
output io_oeb,
output [2:0] irq
);
localparam memsize = 1024;
localparam aw = $clog2(memsize);
wire [aw-1:0] sram_waddr;
wire [ 7:0] sram_wdata;
wire sram_wen;
wire [aw-1:0] sram_raddr;
wire [ 7:0] sram_rdata;
wire sram_ren;
wire csb0;
wire web0;
wire [ 3:0] wmask0;
wire [aw-3:0] addr0;
wire [ 32:0] din0;
wire [ 32:0] dout0;
assign io_oeb = wb_rst_i;
assign irq = 3'b000;
sky130_sram_1kbyte_1rw_32x256_8 #(
.VERBOSE(0)
) sram (
.clk0 (wb_clk_i),
.csb0 (csb0),
.web0 (web0),
.wmask0 (wmask0),
.spare_wen0(1'b0),
.addr0 ({1'b0, addr0}),
.din0 (din0),
.dout0 (dout0)
);
//Adapt the 8-bit SRAM interface from subservient to the 32-bit OpenRAM instance
sram_width_converter sram_width_converter (
.i_clk (wb_clk_i),
//8-bit Subservient interface
.i_sram_waddr (sram_waddr),
.i_sram_wdata (sram_wdata),
.i_sram_wen (sram_wen),
.i_sram_raddr (sram_raddr),
.o_sram_rdata (sram_rdata),
.i_sram_ren (sram_ren),
//32-bit OpenRAM interface
.o_csb0 (csb0),
.o_web0 (web0),
.o_wmask0 (wmask0),
.o_addr0 (addr0),
.o_din0 (din0),
.i_dout0 (dout0)
);
subservient #(
.memsize(memsize),
.aw(aw)
) subservient_inst (
// Clock & reset
.i_clk(wb_clk_i),
.i_rst(wb_rst_i),
//SRAM interface
.o_sram_waddr(sram_waddr),
.o_sram_wdata(sram_wdata),
.o_sram_wen (sram_wen),
.o_sram_raddr(sram_raddr),
.i_sram_rdata(sram_rdata),
.o_sram_ren (sram_ren),
//Debug interface
.i_debug_mode(~la_data_in),
.i_wb_dbg_adr(wbs_adr_i),
.i_wb_dbg_dat(wbs_dat_i),
.i_wb_dbg_sel(wbs_sel_i),
.i_wb_dbg_we (wbs_we_i),
.i_wb_dbg_stb(wbs_stb_i),
.o_wb_dbg_rdt(wbs_dat_o),
.o_wb_dbg_ack(wbs_ack_o),
// External I/O
.o_gpio(io_out)
);
endmodule
| 6.642427 |
module subservient_wrapper_tb;
parameter memfile = "";
parameter memsize = 512;
parameter with_csr = 0;
parameter aw = $clog2(memsize);
reg clk = 1'b0;
reg rst = 1'b1;
wire PWR = 1'b1;
wire GND = 1'b0;
//Debug interface
reg la_data_in;
reg [31:0] wbs_adr_i;
reg [31:0] wbs_dat_i;
reg [ 3:0] wbs_sel_i;
reg wbs_we_i;
reg wbs_stb_i = 1'b0;
wire [31:0] wbs_dat_o;
wire wbs_ack_o;
wire io_out;
always #5 clk <= !clk;
initial #62 rst <= 1'b0;
vlog_tb_utils vtu ();
integer baudrate = 0;
initial begin
if ($value$plusargs("uart_baudrate=%d", baudrate))
$display("UART decoder using baud rate %0d", baudrate);
else forever @(io_out) $display("%0t output o_gpio is %s", $time, io_out ? "ON" : "OFF");
end
reg [1023:0] firmware_file;
integer idx = 0;
reg [7:0] mem[0:memsize-1];
task wb_dbg_write32(input [31:0] adr, input [31:0] dat);
begin
@(posedge clk) begin
wbs_adr_i <= adr;
wbs_dat_i <= dat;
wbs_sel_i <= 4'b1111;
wbs_we_i <= 1'b1;
wbs_stb_i <= 1'b1;
end
while (!wbs_ack_o) @(posedge clk);
wbs_stb_i <= 1'b0;
end
endtask
reg [31:0] tmp_dat;
integer adr;
reg [1:0] bsel;
initial begin
$display("Setting debug mode");
la_data_in <= 1'b0;
if ($value$plusargs("firmware=%s", firmware_file)) begin
$display("Writing %0s to SRAM", firmware_file);
$readmemh(firmware_file, mem);
end else $display("No application to load. SRAM will be empty");
repeat (10) @(posedge clk);
//Write full 32-bit words
while ((mem[idx] !== 8'bxxxxxxxx) && (idx < memsize)) begin
adr = (idx >> 2) * 4;
bsel = idx[1:0];
tmp_dat[bsel*8+:8] = mem[idx];
if (bsel == 2'd3) wb_dbg_write32(adr, tmp_dat);
idx = idx + 1;
end
//Zero-pad final word if required
if (idx[1:0]) begin
adr = (idx >> 2) * 4;
bsel = idx[1:0];
if (bsel == 1) tmp_dat[31:8] = 24'd0;
if (bsel == 2) tmp_dat[31:16] = 16'd0;
if (bsel == 3) tmp_dat[31:24] = 8'd0;
wb_dbg_write32(adr, tmp_dat);
end
repeat (10) @(posedge clk);
$display("Done writing %0d bytes to SRAM. Turning off debug mode", idx);
la_data_in <= 1'b1;
end
uart_decoder uart_decoder (
baudrate,
io_out
);
subservient_wrapped dut (
`ifdef USE_POWER_PINS
.vccd1(PWR),
.vssd1(GND),
`endif
// Clock & reset
.wb_clk_i(clk),
.wb_rst_i(rst),
//Debug interface
.la_data_in(la_data_in),
.wbs_adr_i (wbs_adr_i),
.wbs_dat_i (wbs_dat_i),
.wbs_sel_i (wbs_sel_i),
.wbs_we_i (wbs_we_i),
.wbs_stb_i (wbs_stb_i),
.wbs_dat_o (wbs_dat_o),
.wbs_ack_o (wbs_ack_o),
// External I/O
.io_out(io_out)
);
endmodule
| 6.642427 |
module dec8 (
input wire en, // habilitación (enable) activo en bajo
input wire [2:0] i, // entradas
output reg [7:0] o // salidas
/* Recuerda: para cada puerto de entrada o salida, el compilador define
* una señal tipo 'wire' del mismo nombre. El tipo de señal puede
* cambiarse declarándola explícitamente. Aquí se declara 'o' como reg
* ya que va a emplearse como variable en un proceso 'always'. */
);
always @(en, i) begin
if (en == 1) o = 8'h00; // decodificador deshabilitado
else begin
case (i)
/* Empleamos formato hexadecimal para "i" y binario
* para "o" para facilitar la interpretación del
* código. "_" es un separador opcional que facilita
* la lectura de literales largos */
3'h0: o = 8'b0000_0001;
3'h1: o = 8'b0000_0010;
3'h2: o = 8'b0000_0100;
3'h3: o = 8'b0000_1000;
3'h4: o = 8'b0001_0000;
3'h5: o = 8'b0010_0000;
3'h6: o = 8'b0100_0000;
/* Es una buena costumbre usar "default" para el
* último caso, aunque sea conocido, de esta forma
* nos aseguramos de considerar todos los casos */
default: o = 8'b10000000;
endcase
end
end
endmodule
| 6.847764 |
module mux8_1 (
input wire [2:0] sel, // entradas de selección
input wire [7:0] in, // entradas de datos
output reg out // salida
);
always @(sel, in)
/* La forma más directa de describir un multiplexor es mediante
* un bloque 'case'. */
case (sel)
3'h0: out = in[0];
3'h1: out = in[1];
3'h2: out = in[2];
3'h3: out = in[3];
3'h4: out = in[4];
3'h5: out = in[5];
3'h6: out = in[6];
default: out = in[7];
endcase
endmodule
| 7.497332 |
module cod8 (
input wire [7:0] in, // entradas
output reg [2:0] out, // salida condificada
output reg e // salida de error (1-ninguna entrada activa)
);
always @(in) begin
/* 'e' valdrá cero salvo que alguna condición posterior
* cambie su valor */
e = 0;
/* 'case' también es una buena forma de describir el
* codificador porque la decisión se toma en función de una
* única señal (in). 'casex' es como 'case' pero trata valores
* desconocidos ('x') como inespecificaciones, lo que permite
* expresar de forma muy compacta las comparaciones. */
casex (in)
8'b1xxxxxxx: out = 3'h7;
8'b01xxxxxx: out = 3'h6;
8'b001xxxxx: out = 3'h5;
8'b0001xxxx: out = 3'h4;
8'b00001xxx: out = 3'h3;
8'b000001xx: out = 3'h2;
8'b0000001x: out = 3'h1;
8'b00000001: out = 3'h0;
default: begin // ninguna entrada activa
out = 3'h0;
e = 1;
end
endcase
end
endmodule
| 8.604602 |
module comp4 (
input wire [3:0] a, // número a
input wire [3:0] b, // número b
input wire g0, // entradas para conexión en cascada
input wire e0, // y salidas de la comparación
input wire l0, // si a > b => (g,e,l) = (1,0,0)
output reg g, // si a < b => (g,e,l) = (0,0,1)
output reg e, // si a = b => (g,e,l) = (g0,e0,l0)
output reg l
);
/* Obsérvese cómo se ha empleado el operador de concatenación '{...}'
* que combina varios vectores para formar un vector mayor. Aquí se ha
* empleado para hacer más claras y compactas las asignaciones de
* valores a 'g', 'e' y 'l'. */
always @(a, b, g0, e0, l0) begin
if (a > b) {g, e, l} = 3'b100;
else if (a < b) {g, e, l} = 3'b001;
else {g, e, l} = {g0, e0, l0};
end
endmodule
| 7.171488 |
module info ();
initial begin
$display("Seleccione un banco de pruebas definiendo una ", "de las siguientes macros:");
$display(" TEST_DEC: decodificador");
$display(" TEST_MUX: multiplexor");
$display(" TEST_COD: codificador de prioridad");
$display(" TEST_COMP: comparador de magnitudes");
$display(" SEED: semilla para patrones aleatorios ", "(opcional)");
$display(" NP: numero de patrones a aplicar (opcional)");
$display("Ejemplos:");
$display(" iverilog -DTEST_DEC subsistemas.v");
$display(" iverilog -DTEST_COMP -DNP=200 subsistemas.v");
$finish;
end
endmodule
| 7.219665 |
module: subErrCtrlSplitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module subSplitter_tb;
// Inputs
reg [0:0] err_ctrl;
// Outputs
wire [0:0] sub_err_ctrl;
// Instantiate the Unit Under Test (UUT)
subErrCtrlSplitter uut (
.err_ctrl(err_ctrl),
.sub_err_ctrl(sub_err_ctrl)
);
initial begin
// Initialize Inputs
err_ctrl = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.391929 |
module switching_latch (
input clk, // the system clock
input int_clk, // the interupt clock domain
input reset_n,
input trigger,
input ack,
output reg out
);
reg ack_clk_1; // Doing a 3 stage sync between the clock domains - Fuck I hate these.......
// But this "should" help with different clocks on both sides.
reg interupt_int_clk_1;
always @(posedge int_clk or negedge reset_n) begin
if (~reset_n) begin
interupt_int_clk_1 <= 'b0;
end else begin
if (trigger) interupt_int_clk_1 <= 1'b1;
else if (out) interupt_int_clk_1 <= 1'b0;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
out <= 'b0;
end else begin
if (interupt_int_clk_1) out <= 1'b1;
else if (ack) out <= 1'b0;
end
end
endmodule
| 8.237858 |
module clock_reg_latch #(
parameter data_size = 32
) (
input write_clk, // the APF clock
input read_clk, // the system clock
input reset_n,
input write_trigger,
input [data_size-1:0] write_data_in,
output reg [data_size-1:0] read_data_out
);
reg [data_size-1:0] write_reg_triggered;
always @(posedge write_clk or negedge reset_n) begin
if (~reset_n) begin
write_reg_triggered <= 'b0;
end else begin
if (write_trigger) write_reg_triggered <= write_data_in;
end
end
reg [data_size-1:0] read_data_clocked_1, read_data_clocked_2;
always @(posedge read_clk or negedge reset_n) begin
if (~reset_n) begin
read_data_clocked_1 <= 'b0;
read_data_clocked_2 <= 'b0;
read_data_out <= 'b0;
end else begin
read_data_clocked_1 <= write_reg_triggered;
read_data_clocked_2 <= read_data_clocked_1;
read_data_out <= read_data_clocked_2;
end
end
endmodule
| 7.962295 |
module timer_core (
input clk_sys,
input millisecond_counter_reset,
output reg [31:0] millisecond_counter,
output reg [31:0] millisecond_tick,
output reg [31:0] millisecond_real,
input [31:0] sysclk_frequency,
input [31:0] interupt_counter,
output reg interupt_output
);
// Timer for the cpu to make sure things are in time
reg timer_tick;
always @(posedge clk_sys or posedge millisecond_counter_reset) begin
if (millisecond_counter_reset) begin
millisecond_tick <= 'd0;
millisecond_counter <= 'd0;
interupt_output <= 'd0;
millisecond_real <= 'd0;
end else begin
millisecond_tick <= millisecond_tick + 1;
millisecond_real <= millisecond_real + 1;
if (millisecond_tick == sysclk_frequency) begin
if (millisecond_counter >= interupt_counter) begin
interupt_output <= |{interupt_counter};
end
millisecond_counter <= millisecond_counter + 1;
millisecond_tick <= 'h00000;
end
end
end
endmodule
| 6.564985 |
module sub_byte (
in_key,
out_key
);
input [0:127] in_key;
output [0:127] out_key;
sbox sb1 (
in_key[0:3],
in_key[4:7],
out_key[0:7]
);
sbox sb2 (
in_key[8:11],
in_key[12:15],
out_key[8:15]
);
sbox sb3 (
in_key[16:19],
in_key[20:23],
out_key[16:23]
);
sbox sb4 (
in_key[24:27],
in_key[28:31],
out_key[24:31]
);
sbox sb5 (
in_key[32:35],
in_key[36:39],
out_key[32:39]
);
sbox sb6 (
in_key[40:43],
in_key[44:47],
out_key[40:47]
);
sbox sb7 (
in_key[48:51],
in_key[52:55],
out_key[48:55]
);
sbox sb8 (
in_key[56:59],
in_key[60:63],
out_key[56:63]
);
sbox sb9 (
in_key[64:67],
in_key[68:71],
out_key[64:71]
);
sbox sb10 (
in_key[72:75],
in_key[76:79],
out_key[72:79]
);
sbox sb11 (
in_key[88:91],
in_key[92:95],
out_key[88:95]
);
sbox sb12 (
in_key[80:83],
in_key[84:87],
out_key[80:87]
);
sbox sb13 (
in_key[96:99],
in_key[100:103],
out_key[96:103]
);
sbox sb14 (
in_key[104:107],
in_key[108:111],
out_key[104:111]
);
sbox sb15 (
in_key[112:115],
in_key[116:119],
out_key[112:119]
);
sbox sb16 (
in_key[120:123],
in_key[124:127],
out_key[120:127]
);
endmodule
| 7.059994 |
module seq_detector (
//Control signals
input clk, //Positive edge triggered.
input areset, //Reset all in 1
//Data signals
input seq,
output detected
);
//Declare your variables here.
/*parameter[1:0] S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10;
*/
reg [1:0] state = 2'b00;
always @(posedge clk or posedge areset) begin
//Write your code here.
if (areset) begin
state <= 2'b00;
end else begin
case (state)
2'b00: begin
if (seq == 0) begin
state <= 2'b01;
end else begin
state <= 2'b00;
end
end
2'b01: begin
if (seq == 1) begin
state <= 2'b10;
end else begin
state <= 2'b01;
end
end
2'b10: begin
if (seq == 0) begin
state <= 2'b01;
end else begin
state <= 2'b00;
end
end
default: begin
state <= 2'b00;
end
endcase
end
end
//You may write some wiring code here.
assign detected = (state == 2'b10) & (!seq);
endmodule
| 7.041455 |
module substract (
a,
b,
c
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter IWIDTH = 64;
parameter HiddenNeuron = 16;
parameter x = 4;
parameter Layer = 3;
input signed [DWIDTH-1:0] a;
input signed [DWIDTH-1:0] b;
output signed [DWIDTH-1:0] c;
assign c = a - b;
endmodule
| 6.706886 |
module Substraction (
flag_ex,
ans_tmp,
A,
B
);
input [7:0] A, B;
output wire [3:0] flag_ex;
output wire [7:0] ans_tmp;
add_sub_8bit Add (
flag_ex[2],
ans_tmp,
flag_ex[0],
A,
B,
1'b1
);
assign flag_ex[1] = ~(|ans_tmp);
assign flag_ex[3] = ^(ans_tmp);
endmodule
| 7.172059 |
module Substractor_1Bit (
//define inputs
input _subInA,
_subInB,
_subBin,
//define ouputs
output _differenceOut,
_borrowOut
);
reg _diffReg, _borrowReg;
assign _differenceOut = ({_subInA,_subInB} == 2'b00) ? _subBin:
({_subInA,_subInB} == 2'b01) ? (~_subBin):
({_subInA,_subInB} == 2'b10) ? (~_subBin):
({_subInA,_subInB} == 2'b11) ? _subBin: 2'b00;
assign _borrowOut = ({_subInA,_subInB} == 2'b00) ? _subBin:
({_subInA,_subInB} == 2'b01) ? 1'b1:
({_subInA,_subInB} == 2'b10) ? 1'b0:
({_subInA,_subInB} == 2'b11) ? _subBin: 2'b00;
endmodule
| 6.786421 |
module Substractor_4bit (
//define inputs
input [7:0] _subInA,
_subInB,
input _subBin,
//define outputs
output [7:0] _differenceOut,
output _borrowOut
);
wire [7:0] _bOut;
Substractor_1Bit M0 (
_subInA[0],
_subInB[0],
_subBin,
_differenceOut[0],
_bOut[0]
);
Substractor_1Bit M1 (
_subInA[1],
_subInB[1],
_bOut[0],
_differenceOut[1],
_bOut[1]
);
Substractor_1Bit M2 (
_subInA[2],
_subInB[2],
_bOut[1],
_differenceOut[2],
_bOut[2]
);
Substractor_1Bit M3 (
_subInA[3],
_subInB[3],
_bOut[2],
_differenceOut[3],
_bOut[3]
);
Substractor_1Bit M4 (
_subInA[4],
_subInB[4],
_bOut[3],
_differenceOut[4],
_bOut[4]
);
Substractor_1Bit M5 (
_subInA[5],
_subInB[5],
_bOut[4],
_differenceOut[5],
_bOut[5]
);
Substractor_1Bit M6 (
_subInA[6],
_subInB[6],
_bOut[5],
_differenceOut[6],
_bOut[6]
);
Substractor_1Bit M7 (
_subInA[7],
_subInB[7],
_bOut[6],
_differenceOut[7],
_bOut[7]
);
assign _borrowOut = _bOut[7];
endmodule
| 7.138275 |
module subsystem_v1_0 #(
// Users to add parameters here
parameter integer SIZE = 4,
parameter integer MAX_WORD_LENGTH = 32,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
subsystem_v1_0_S00_AXI #(
.SIZE(SIZE),
.MAX_WORD_LENGTH(MAX_WORD_LENGTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) subsystem_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.503653 |
module subtract (
a,
b,
result
);
parameter WIDTH = 8;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] result;
wire [WIDTH-1:0] inv_b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
inv1$(
inv_b[i], b[i]
);
end
endgenerate
slow_addr_cin#(
.WIDTH(WIDTH)
) (
a, inv_b, result, nc, 1'b1
);
endmodule
| 7.409159 |
module slow_addr_cin (
a,
b,
out,
carry,
cin
);
parameter WIDTH = 64;
input cin;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] out;
output carry;
wire [WIDTH-1:0] carry_vec;
genvar i;
generate
if (WIDTH == 1) begin
full_addr fa (
a,
b,
out,
1'b0,
carry
);
end else begin
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
full_addr fa (
a[i],
b[i],
out[i],
cin,
carry_vec[i]
);
end else begin
full_addr fa (
a[i],
b[i],
out[i],
carry_vec[i-1],
carry_vec[i]
);
end
end
end
endgenerate
assign carry = carry_vec[WIDTH-1];
endmodule
| 7.756084 |
module subtracter (
S,
A,
B,
CarryIn
);
input [31:0] A, B;
input CarryIn;
output [31:0] S;
wire [31:0] noted;
noter N (
noted,
B
);
adder ADD (
S,
A,
noted,
CarryIn
);
endmodule
| 6.924494 |
module subtracter_32 (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
wire [31:0] a;
wire carry;
not_32 NOT (
a,
in2
);
full_adder_32 FA (
out,
carry,
in1,
a,
1'b1
);
endmodule
| 7.076294 |
module subtraction (
a,
b,
c
);
// bit depth
localparam BIT_DEPTH = 14;
input wire [BIT_DEPTH-1:0] a, b;
output wire [BIT_DEPTH:0] c;
pos_sub #(BIT_DEPTH, BIT_DEPTH) SUB (
a,
b,
c
);
endmodule
| 8.183545 |
module subtra (
a,
b,
cin,
o,
signbit
);
input [255:0] a, b;
input cin;
output [255:0] o;
output signbit;
wire [255:0] r, f, i;
wire carryout;
twoscomplement w (
b,
r
);
fullmodu q (
a,
r,
1'b0,
f,
carryout
);
twoscomplement e (
f,
i
);
mux1 p (
o,
f,
i,
carryout
);
muxonebit y (
signbit,
1'b1,
1'b0,
carryout
);
endmodule
| 6.662515 |
module twoscomplement (
f,
i
);
input [255:0] f;
output [255:0] i;
assign i = (~f) + 1'b1;
endmodule
| 7.994634 |
module fulladder (
X,
Y,
Ci,
S,
Co
);
input X, Y, Ci;
output S, Co;
wire w1, w2, w3;
//Structural code for one bit full adder
xor G1 (w1, X, Y);
xor G2 (S, w1, Ci);
and G3 (w2, w1, Ci);
and G4 (w3, X, Y);
or G5 (Co, w2, w3);
endmodule
| 7.454465 |
module rippe_adder (
X,
Y,
Cin,
S,
co
);
input [7:0] X, Y;
output [7:0] S;
output co;
input Cin;
wire w1, w2, w3, w4, w5, w6, w7;
//instantiating 4 1-bit full adders in Verilog
fulladder u1 (
X[0],
Y[0],
Cin,
S[0],
w1
);
fulladder u2 (
X[1],
Y[1],
w1,
S[1],
w2
);
fulladder u3 (
X[2],
Y[2],
w2,
S[2],
w3
);
fulladder u4 (
X[3],
Y[3],
w3,
S[3],
w4
);
fulladder u5 (
X[4],
Y[4],
w4,
S[4],
w5
);
fulladder u6 (
X[5],
Y[5],
w5,
S[5],
w6
);
fulladder u7 (
X[6],
Y[6],
w6,
S[6],
w7
);
fulladder u8 (
X[7],
Y[7],
w7,
S[7],
co
);
endmodule
| 7.974568 |
module SubtractOperation (
input [11:0] lhs,
input [11:0] rhs,
output [11:0] result,
output overflow
);
assign overflow = lhs < rhs;
assign result = lhs - rhs;
endmodule
| 7.126781 |
module subtractor_nb (
A,
B,
SUB,
sign_flag,
Co
);
parameter n = 32;
input signed [n-1:0] A, B;
output signed [n-1:0] SUB;
output sign_flag;
output Co;
rca_nb subtr (
.a (A),
.b (~B),
.cin(32'b0000000000000000_0000000000000001),
.sum(SUB),
.co (Co)
);
comparator_nb neg (
.A (A),
.B (B),
.EQ(),
.LT(sign_flag),
.GT()
);
endmodule
| 7.15584 |
module Subtractor_8Bit (
input [7:0] A,
input [7:0] B,
output [7:0] D,
output Bout
);
wire [7:0] w;
HalfSubtractor H1 (
A[0],
B[0],
D[0],
w[0]
);
FullSubtractor F1 (
A[1],
B[1],
w[0],
D[1],
w[1]
);
FullSubtractor F2 (
A[2],
B[2],
w[1],
D[2],
w[2]
);
FullSubtractor F3 (
A[3],
B[3],
w[2],
D[3],
w[3]
);
FullSubtractor F4 (
A[4],
B[4],
w[3],
D[4],
w[4]
);
FullSubtractor F5 (
A[5],
B[5],
w[4],
D[5],
w[5]
);
FullSubtractor F6 (
A[6],
B[6],
w[5],
D[6],
w[6]
);
FullSubtractor F7 (
A[7],
B[7],
w[6],
D[7],
w[7]
);
assign Bout = w[7];
endmodule
| 6.897715 |
module sub_16_bit (
input1,
input2,
answer
);
parameter N = 16;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire M;
wire [N-1:0] temp;
wire [N-1:0] carry;
assign M = 1;
genvar i;
for (i = 0; i < N; i = i + 1) begin
assign temp[i] = input2[i] ^ M;
end
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
full_adder f (
input1[0],
temp[0],
M,
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
temp[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 6.856011 |
module Subtractor_2_input (
p_sub,
q_sub,
p,
q
);
parameter size = 4;
output [(size-1):0] p_sub;
output [(size-1):0] q_sub;
input [(size-1):0] p;
input [(size-1):0] q;
assign p_sub = p - 1;
assign q_sub = q - 1;
endmodule
| 6.954463 |
module subtractor_4bit (
a,
b,
diff,
sgn
);
input [3:0] a, b; //a is the minuend, b is the subtrahend
output [3:0] diff;
output sgn; //sign of result, 1 for '+'ve no. and 0 for '-'ve no.
wire boutin; //generated borrow, which is to be ignored /***********/
wire [3:0] b_bar; //complimenting the subtrahend
wire [2:0] boin; //internal borrows generated in stage 1
wire bin = 1'b1; //input borrow for stage 1 adder
wire cin1 = 1'b0; //input carry for stage 2 adder
wire [3:0] diffin; //output of stage 1 adder
wire [3:0] b1; //augend to stage 2 addder (s5)
wire [3:0] diffin1; //addend to stage 2 addder (s5)
//performing the 1st stage of subtraction
not (b_bar[0], b[0]); //complimenting each bit of subtrahend to get its 1's compliment
adder_1bit s1 (
a[0],
b_bar[0],
bin,
diffin[0],
boin[0]
); //b_bar is converted to 2's compliment form due to input carry as 1 to the adder
//then performing the addition
not (b_bar[1], b[1]);
adder_1bit s2 (
a[1],
b_bar[1],
boin[0],
diffin[1],
boin[1]
);
not (b_bar[2], b[2]);
adder_1bit s3 (
a[2],
b_bar[2],
boin[1],
diffin[2],
boin[2]
);
not (b_bar[3], b[3]);
adder_1bit s4 (
a[3],
b_bar[3],
boin[2],
diffin[3],
boutin
);
// if output carry (boutin) of stage 1 adder is 1, then the result is +ve and the carry is to be neglectted
// if output carry (boutin) of stage 1 adder is 0, then the result is -ve and is in 2's compliment form
// xnor gate will work as a not gate if the boutin is 0, and we wil get the 1's compliment of diffin
xnor (diffin1[0], boutin, diffin[0]);
xnor (diffin1[1], boutin, diffin[1]);
xnor (diffin1[2], boutin, diffin[2]);
xnor (diffin1[3], boutin, diffin[3]);
not (b1[0], boutin);
assign sgn = b1[0];
assign b1[3:1] = 3'b0;
// diffin1 is the 1's compliment of diffin
// if boutin is 0, adding 0001 to diffin1(complimented by xnor) to get the 2's compliment of diffin
// if boutin is 1, adding 0000 to diffin1(not complimentedby xnor) so that we get the direct result diffin
//diffin1 acts as addend to the stage 2 4bit adder (s5)
adder_4bit s5 (
diffin1,
b1,
cin1,
diff,
bout
);
endmodule
| 7.028549 |
module regN (
reset,
CLK,
D,
Q
);
input reset;
input CLK;
parameter N = 8;
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset) Q = 0;
else Q = D;
endmodule
| 7.765402 |
module subtractor_full (
minuend,
subtrahend,
inborrow,
diff,
outborrow
);
input minuend, subtrahend, inborrow;
/*
`inborrow` is the bit that tells us whether the previous operation required a BORROW or not. This information is impactful for the outputs of the current operation.
inborrow = 0 means the previous operation did NOT require a BORROW. In this case, the operation would BEHAVE like in the case of HALF ADDER
inborrow = 1 means the previous operation did require a BORROW, so we would add 1 to the subtrahend in order to represent this.
*/
output diff, outborrow;
//* Data-flow modelling
assign diff = minuend ^ subtrahend ^ inborrow;
assign outborrow = ((~(minuend ^ subtrahend)) & inborrow) + ((~minuend) & subtrahend);
endmodule
| 7.458539 |
module testbenchforhalfsubtractor;
reg minuend, subtrahend;
wire diff, outborrow;
subtractor_half wire_driver (
minuend,
subtrahend,
diff,
outborrow
);
// We name the instance of the module as `wire_driver` since it is DRIVING the values of the wires `diff` and `outborrow`.
//* Behavioral Modelling
initial begin
minuend = 1'b0;
subtrahend = 1'b0;
#20 minuend = 1'b0;
subtrahend = 1'b1;
#20 minuend = 1'b1;
subtrahend = 1'b0;
#20 minuend = 1'b1;
subtrahend = 1'b1;
#20 $finish;
end
endmodule
| 7.057029 |
module subtract_10_5_bits (
input [4:0] x,
output [3:0] A
);
assign A = x - 10;
endmodule
| 7.42961 |
module subtract_512 (
in_1,
in_2,
out
);
input [40:0] in_1;
input [40:0] in_2;
output [40:0] out;
assign out[40:0] = in_1[40:0] - in_2[40:0];
endmodule
| 7.267621 |
module add_8bit (
a,
b,
c_in,
s,
c_out
);
input [7:0] a;
input [7:0] b;
input c_in;
output [7:0] s;
output c_out;
wire [6:0] c;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(s[0]),
.c_out(c[0])
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.c_in(c[0]),
.s(s[1]),
.c_out(c[1])
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.c_in(c[1]),
.s(s[2]),
.c_out(c[2])
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.c_in(c[2]),
.s(s[3]),
.c_out(c[3])
);
full_adder fa4 (
.a(a[4]),
.b(b[4]),
.c_in(c[3]),
.s(s[4]),
.c_out(c[4])
);
full_adder fa5 (
.a(a[5]),
.b(b[5]),
.c_in(c[4]),
.s(s[5]),
.c_out(c[5])
);
full_adder fa6 (
.a(a[6]),
.b(b[6]),
.c_in(c[5]),
.s(s[6]),
.c_out(c[6])
);
full_adder fa7 (
.a(a[7]),
.b(b[7]),
.c_in(c[6]),
.s(s[7]),
.c_out(c_out)
);
endmodule
| 6.573601 |
module subtract_8bit (
a,
b,
b_in,
d,
b_out
);
input [7:0] a;
input [7:0] b;
input b_in;
output [7:0] d;
output b_out;
wire [7:0] twos_comp;
wire c_out;
add_8bit rca0 (
.a(~b),
.b(8'b00000001),
.c_in(1'b0),
.s(twos_comp),
.c_out(c_out)
);
add_8bit rca1 (
.a(a),
.b(twos_comp),
.c_in(b_in),
.s(d),
.c_out(b_out)
);
endmodule
| 6.606639 |
module subtract_8bit_tb;
reg [7:0] a;
reg [7:0] b;
reg b_in;
wire [7:0] d;
wire b_out;
subtract_8bit uut (
.a(a),
.b(b),
.b_in(b_in),
.d(d),
.b_out(b_out)
);
initial begin
$dumpfile("subtract_8bit_tb.vcd");
$dumpvars(0, subtract_8bit_tb);
a = 8'b00000001;
b = 8'b00000001;
b_in = 1'b0;
#10 a = 8'b00000011;
b = 8'b00000101;
b_in = 1'b1;
#10 a = 8'b00000001;
b = 8'b00000001;
b_in = 1'b1;
#10 a = 8'b00000010;
b = 8'b00000011;
b_in = 1'b0;
#10 a = 8'b10000001;
b = 8'b10000001;
b_in = 1'b0;
#10 a = 8'b00011001;
b = 8'b00110001;
b_in = 1'b0;
#10 a = 8'b00110001;
b = 8'b00011001;
b_in = 1'b0;
#10 a = 8'b00000011;
b = 8'b00000011;
b_in = 1'b1;
#10 a = 8'b11111111;
b = 8'b00000001;
b_in = 1'b0;
#10 a = 8'b11111111;
b = 8'b00000000;
b_in = 1'b1;
#10 a = 8'b11111111;
b = 8'b11111111;
b_in = 1'b0;
end
endmodule
| 6.606639 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module subtract_module(Clk, data_in, reset, enable, textOut, next, done);
input Clk;
input [7:0] data_in;
input reset;
input enable;
input next;
output reg [8*32:0] textOut;
output reg done;
reg [7:0] data_out;
reg [7:0] input_A, input_B;
reg [4:0] state;
localparam
START = 5'b00001,
LOAD_A = 5'b00010,
LOAD_B = 5'b00100,
CALCULATE = 5'b01000,
DONE = 5'b10000;
always @(posedge Clk, posedge reset)
begin
//if (!enable)
//begin
//end
//else
//begin
if (reset)
begin
state <= START;
end
else
begin
case (state)
START:
begin
textOut = "Subtraction Subs 2 Numbers ";
input_A <= 0;
input_B <= 0;
done <= 0;
data_out <= 0;
if (next && enable)
state <= LOAD_A;
end
LOAD_A:
begin
textOut = "Input 1st # Then Press Btnc ";
if (next)
begin
input_A <= data_in;
state <= LOAD_B;
end
end
LOAD_B:
begin
textOut = "Input 2nd # Then Press Btnc ";
if (next)
begin
input_B <= data_in;
state <= CALCULATE;
end
end
CALCULATE:
begin
if (input_A >= input_B)
data_out <= input_A - input_B;
else
data_out <= input_B - input_A;
textOut = "Calculating... ";
if (next)
state <= DONE;
end
DONE:
begin
textOut = {"The Diff is: ", (input_B>input_A?"-":" "),bin2x(data_out[7:4]), bin2x(data_out[3:0]), " "};
done <= 1;
end
endcase
end
//end
end
function [7:0] bin2x;
input [3:0] data;
begin
case (data)
4'h0: bin2x = "0";4'h1: bin2x = "1";4'h2: bin2x = "2";4'h3: bin2x = "3";
4'h4: bin2x = "4";4'h5: bin2x = "5";4'h6: bin2x = "6";4'h7: bin2x = "7";
4'h8: bin2x = "8";4'h9: bin2x = "9";4'hA: bin2x = "A";4'hB: bin2x = "B";
4'hC: bin2x = "C";4'hD: bin2x = "D";4'hE: bin2x = "E";4'hF: bin2x = "F";
default:bin2x = "0";
endcase
end
endfunction
endmodule
| 7.088073 |
module notGate (
s,
x
);
output s;
input x;
nand NAND1 (s, x, x);
endmodule
| 8.310861 |
module andGate (
s,
x,
y
);
output s0, s;
input x, y;
wire s, s0;
nand NAND1 (s, x, y);
notGate NOT1_NAND1 (
s0,
s
);
endmodule
| 9.12182 |
module orGate (
s0,
x,
y
);
output s0, sX, sY;
input x, y;
wire s0, sX, sY;
notGate NOT1 (
sX,
x
);
notGate NOT2 (
sY,
y
);
nand NAND1 (s0, sX, sY);
endmodule
| 7.703609 |
module saida1 (
s,
x,
y
);
output s1, s2, s;
input x, y;
wire s;
notGate NOT1 (
s1,
x
);
nand NAND1 (s2, s1, y);
notGate NOT2 (
s,
s2
);
endmodule
| 6.784364 |
module meiaDiferenca1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 8.132121 |
module diferenca_2bits (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1, s2, saida0, saida1;
wire saida0, saida1;
diferencaCompleta DIFERENCACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
diferencaCompleta DIFERENCACOMPLETA2 (
s1,
s2,
a1,
b1,
saida0
);
endmodule
| 7.053639 |
module notGate (
s,
a
);
output s;
input a;
nand NAND1 (s, a, a);
endmodule
| 8.310861 |
module andGate (
s,
a,
b
);
output s0, s;
input a, b;
wire s, s0;
nand NAND1 (s, a, b);
notGate NOT1_NAND1 (
s0,
s
);
endmodule
| 9.12182 |
module orGate (
s0,
a,
b
);
output s0, sA, sB;
input a, b;
wire s0, sA, sB;
notGate NOT1 (
sA,
a
);
notGate NOT2 (
sB,
b
);
nand NAND1 (s0, sA, sB);
endmodule
| 7.703609 |
module saida1 (
s,
a,
b
);
output s1, s2, s;
input a, b;
wire s;
notGate NOT1 (
s1,
a
);
nand NAND1 (s2, s1, b);
notGate NOT2 (
s,
s2
);
endmodule
| 6.784364 |
module meiaDiferenca1 (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
a,
b
);
saida1 S1 (
s1,
a,
b
);
endmodule
| 8.132121 |
module subtree_212_wrapper #(
parameter num_leaves = 32,
parameter payload_sz = 43,
parameter p_sz = 49,
parameter addr = 2'b00,
parameter level = 2
) (
input [p_sz-1:0] leaf_0_in,
input [p_sz-1:0] leaf_1_in,
input [p_sz-1:0] leaf_2_in,
input [p_sz-1:0] leaf_3_in,
input [p_sz-1:0] leaf_4_in,
input [p_sz-1:0] leaf_5_in,
input [p_sz-1:0] leaf_6_in,
input [p_sz-1:0] leaf_7_in,
output [p_sz-1:0] leaf_0_out,
output [p_sz-1:0] leaf_1_out,
output [p_sz-1:0] leaf_2_out,
output [p_sz-1:0] leaf_3_out,
output [p_sz-1:0] leaf_4_out,
output [p_sz-1:0] leaf_5_out,
output [p_sz-1:0] leaf_6_out,
output [p_sz-1:0] leaf_7_out,
output resend_0,
output resend_1,
output resend_2,
output resend_3,
output resend_4,
output resend_5,
output resend_6,
output resend_7,
input [2*2*p_sz-1:0] bus_i,
output [2*2*p_sz-1:0] bus_o,
input clk,
input reset
);
subtree_212 #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.p_sz(p_sz),
.addr(addr),
.level(level)
) u0 (
.clk(clk),
.reset(reset),
.pe_interface({
leaf_7_in, leaf_6_in, leaf_5_in, leaf_4_in, leaf_3_in, leaf_2_in, leaf_1_in, leaf_0_in
}),
.interface_pe({
leaf_7_out,
leaf_6_out,
leaf_5_out,
leaf_4_out,
leaf_3_out,
leaf_2_out,
leaf_1_out,
leaf_0_out
}),
.resend({resend_7, resend_6, resend_5, resend_4, resend_3, resend_2, resend_1, resend_0}),
.bus_i(bus_i),
.bus_o(bus_o)
);
endmodule
| 7.441331 |
module SUBT_32Bits (
input wire [31:0] A, //ENTRADA A
input wire [31:0] B, //ENTRADA B
output wire [31:0] Y //SALIDA Y
);
assign Y = A - B; //RESTA DE ENTRADAS
endmodule
| 8.641194 |
module SUBU (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output reg carry
);
always @(*) begin
if (a < b) carry = 1;
else carry = 0;
end
assign r = a - b;
endmodule
| 6.97686 |
module reg32 (
input [31:0] in,
clk,
rst,
output reg [31:0] out
);
reg [31:0] mem;
always @(posedge clk) // trigger on rising clk
begin
if (rst) mem = 32'd0;
else mem = in;
out = mem;
end
endmodule
| 7.501717 |
module twomux32 (input [31:0]a, [31:0]b, sel, output reg [31:0]out);
always @(*)
begin
case(sel)
1'd0: out = a;
1'd1: out = b;
default: out = 32'bx;
endcase
end
endmodule
| 7.441983 |
module twomux16 (input [15:0]a, [15:0]b, sel, clk, output reg [15:0]out);
always @(*)
begin
case (sel)
1'd0: out = a;
1'd1: out = b;
default: out = 16'bx;
endcase
end
endmodule
| 7.137584 |
module SUB_ #(
parameter N = 8,
M = N
) ( // N >= M
input [N-1:0] A,
input [M-1:0] B,
output [ N:0] O
);
assign {CO, S} = A - B;
endmodule
| 6.980838 |
module sub_254 (
input wire clk,
input wire rst,
input wire [253 : 0] sub_in0,
input wire [253 : 0] sub_in1,
output reg [253 : 0] sub_out
);
always @(posedge clk)
if (rst) begin
sub_out <= 254'b0;
end else begin
sub_out <= sub_in0 - sub_in1;
end
endmodule
| 7.768499 |
module sub_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa - datab;
assign overflow = computation[32];
assign result = computation[31:0];
endmodule
| 7.033184 |
module sub_32b_testbench ();
reg [31:0] A;
reg [31:0] B;
reg C_in;
wire [31:0] O;
wire C_out;
wire V;
sub_32b sub32tb (
O,
V,
C_out,
A,
B,
C_in
);
initial begin
C_in = 1'b0;
A = 32'b00000000000000000000000000000010;
B = 32'b00000000000000000000000000000001;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000010;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000100000000000000001;
B = 32'b00000000100000000000000000000001;
#`DELAY;
A = 32'b10000000000000000000000000000001;
B = 32'b10000000000000000000000000000010;
#`DELAY;
A = 32'b10000010000000000000000000000000;
B = 32'b10000000000000000000100000000001;
#`DELAY;
A = 32'b00000000000100000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b10000000010000000000000000000001;
B = 32'b00000000000000000000000000000001;
#`DELAY;
C_in = 1'b1;
A = 32'b00000000000000000000000000000010;
B = 32'b00000000000000000000000000000001;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000010;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000100000000000000001;
B = 32'b00000000100000000000000000000001;
#`DELAY;
A = 32'b10000000000000000000000000000001;
B = 32'b10000000000000000000000000000010;
#`DELAY;
A = 32'b10000010000000000000000000000000;
B = 32'b10000000000000000000100000000001;
#`DELAY;
A = 32'b00000000000100000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b10000000010000000000000000000001;
B = 32'b00000000000000000000000000000001;
#`DELAY;
end
initial begin
$monitor("time = %2d,C_in = %1b, A = %32b, B = %32b, R = %32b, C_out = %1b, V = %1b ", $time,
C_in, A, B, O, C_out, V);
end
endmodule
| 6.636855 |
module sub_32_bit (
input wire [31:0] Ra,
input wire [31:0] Rb,
input wire cin,
output wire [31:0] sum,
output wire cout
);
wire [31:0] tempValue;
negate_32_bit negate (
.Ra(Rb),
.Rz(tempValue)
);
add_32_bit add (
.Ra (Ra),
.Rb (tempValue),
.cin (cin),
.sum (sum),
.cout(cout)
);
endmodule
| 7.502319 |
module SUB_64 (
diff,
a,
b
);
parameter n = 64;
input signed [n-1:0] a, b;
output signed [n-1:0] diff;
wire signed [n-1:0] b1; // 1s completement of b
wire signed [n-1:0] b2; // 2s comp of b
wire signed [n-1:0] dummy; // random dummy variables
wire signed [n-1:0] dummy2;
NOT_64 g1 (
b1,
b
); // generating the 1s complement using 64 bit NOT operation
ADD_64 g2 (
b2,
dummy,
b1,
64'b1
); // generating 2s complement by adding 1 to the 1s complement using 64 bit adder
ADD_64 g3 (
diff,
dummy2,
a,
b2
); // adding the 2s complement to a in order to obtain a - b
endmodule
| 6.881718 |
module sub_8bit (
a,
b,
result_sub1
); // test bench
// signals used in test bench (the interconnections)
input [7:0] a; // so bi tru
input [7:0] b; // so tru
output [8:0] result_sub1;
wire [8:0] cout;
// tang 1: khoi tru
//
// a,b,t,c_in,r,q
cas_1bit bit03 (
a[0],
b[0],
1'b1,
1'b1,
result_sub1[0],
cout[0]
);
cas_1bit bit04 (
a[1],
b[1],
1'b1,
cout[0],
result_sub1[1],
cout[1]
);
cas_1bit bit05 (
a[2],
b[2],
1'b1,
cout[1],
result_sub1[2],
cout[2]
);
cas_1bit bit06 (
a[3],
b[3],
1'b1,
cout[2],
result_sub1[3],
cout[3]
);
cas_1bit bit07 (
a[4],
b[4],
1'b1,
cout[3],
result_sub1[4],
cout[4]
);
cas_1bit bit08 (
a[5],
b[5],
1'b1,
cout[4],
result_sub1[5],
cout[5]
);
cas_1bit bit09 (
a[6],
b[6],
1'b1,
cout[5],
result_sub1[6],
cout[6]
);
cas_1bit bit00 (
a[7],
b[7],
1'b1,
cout[6],
result_sub1[7],
cout[7]
);
cas_1bit bit01 (
1'b0,
1'b0,
1'b1,
cout[7],
result_sub1[8],
cout[8]
);
endmodule
| 7.534545 |
module SUB_AB #(
parameter WIDTH3 = 8
) (
A,
B,
OUT
);
input [WIDTH3-1:0] A, B;
output [WIDTH3-1:0] OUT;
assign OUT = A - B;
endmodule
| 7.30172 |
module sub_ALU (
a,
b,
c_in,
diff,
c_out
);
input a, b;
input c_in;
output diff;
output c_out;
wire b_not;
not_ALU notb (
.in (b),
.out(b_not)
);
FA_str subt (
c_out,
diff,
a,
b_not,
c_in
);
endmodule
| 8.011854 |
module Sub_BIST (
rst,
clk,
wrt_addrs,
rd_addrs,
wrt_dat,
wrt_en,
button,
rd_data,
led_out
);
input rst;
input clk;
input [9:0] wrt_addrs;
input [9:0] rd_addrs;
input [7:0] wrt_dat;
input wrt_en;
input button;
output wire [7:0] rd_data;
output reg [7:0] led_out;
reg [7:0] extra_bytes;
reg check_if_fail;
reg [9:0] def_addrs;
wire rd_sel;
wire cur_tst_state;
wire tst_pass;
wire tst_fail;
wire [7:0] ram_rd_data;
wire [9:0] ram_rd_addrs;
wire [9:0] ram_wrt_addrs;
wire [7:0] ram_wrt_dat;
wire ram_wrt_en;
wire bist_wrt_en;
RAM ram (
clk,
ram_rd_addrs,
ram_wrt_addrs,
ram_wrt_en,
ram_wrt_dat,
ram_rd_data
);
wire clk_div;
Clock_div Divide (
clk,
clk_div
);
wire nextcount;
wire nextpat;
wire resetpat;
wire resetcount;
wire [8:0] pattern;
wire [10:0] counter;
wire error;
Pattern Pat_Gen (
clk_div,
resetcount,
resetpat,
nextpat,
nextcount,
error,
pattern,
counter
);
wire tst_count;
BIST_controller Control (
rst,
clk_div,
error,
pattern[8],
counter[10],
nextpat,
nextcount,
cur_tst_state,
tst_pass,
tst_fail,
resetcount,
resetpat,
tst_count
);
//Multiplexer #(10) Read_address(clk,rd_addrs,counter[9:0],cur_tst_state,ram_rd_addrs);
assign ram_rd_addrs = cur_tst_state ? counter[9:0] : rd_addrs;
//Multiplexer #(10) Write_address(clk,wrt_addrs, counter[9:0], cur_tst_state , ram_wrt_addrs);
assign ram_wrt_addrs = cur_tst_state ? counter[9:0] : wrt_addrs;
//Multiplexer #(8) Write_data (clk,wrt_dat, pattern [7:0] , cur_tst_state , ram_wrt_dat );
assign ram_wrt_dat = cur_tst_state ? pattern[7:0] : wrt_dat;
// assign ram_wrt_en = (wrt_en & ~cur_tst_state) | (bist_wrt_en & cur_tst_state );
assign ram_wrt_en = cur_tst_state ? bist_wrt_en : wrt_en;
assign error = ~(pattern[7:0] == rd_data);
assign bist_wrt_en = clk_div & cur_tst_state;
assign rd_sel = check_if_fail & (ram_rd_addrs == def_addrs);
Multiplexer #(8) Read_data (
clk,
ram_rd_data,
extra_bytes,
rd_sel,
rd_data
);
always @(posedge clk) begin
if (rst) check_if_fail = 0;
else if (~cur_tst_state & tst_fail & tst_count) begin
check_if_fail <= 1;
def_addrs <= counter;
end
if (check_if_fail) begin
if ((ram_wrt_addrs == def_addrs) & ram_wrt_en) extra_bytes <= ram_wrt_dat;
end
if (button) begin
led_out <= counter[7:0];
end else begin
led_out[7:4] <= 0;
led_out[3] <= check_if_fail;
led_out[2] <= tst_fail;
led_out[1] <= tst_pass;
led_out[0] <= cur_tst_state;
end
end
/* always@(posedge clk )
begin
if (button)begin
led_out <= counter[7:0];
end
else begin
led_out[7:3] <= 0;
led_out[2] <= tst_fail;
led_out[1] <= tst_pass;
led_out[0] <= cur_tst_state;
end
end*/
endmodule
| 6.747637 |
module sub_byte (
input [127:0] subByteInput,
input startTransition,
input clock,
output [127:0] subByteOutput
);
genvar twoBytes;
generate
for (twoBytes = 0; twoBytes < 128; twoBytes = twoBytes + 8) begin : subByte
s_box subValue (
.inputValue(subByteInput[twoBytes+:8]),
.sboxOutput(subByteOutput[twoBytes+:8])
);
end
endgenerate
endmodule
| 7.059994 |
module sub_bytes (
in,
out
);
input [16*8-1 : 0] in;
output [16*8-1 : 0] out;
wire [16*8-1 : 0] out;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : sb
sbox s (
.in (in[8*i+7:8*i]),
.out(out[8*i+7:8*i])
);
end
endgenerate
endmodule
| 6.930515 |
module inv_sub_bytes (
in,
out
);
input [16*8-1 : 0] in;
output [16*8-1 : 0] out;
wire [16*8-1 : 0] out;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : sb
inv_sbox s (
.in (in[8*i+7:8*i]),
.out(out[8*i+7:8*i])
);
end
endgenerate
endmodule
| 6.81424 |
module is a test bench for the sub_byte. The output of test bench is
// a pass or fail results passed on the obtained values.
`timescale 1ns / 100ps
module sub_byte_tb;
reg startTransition;
reg clock50MHz;
reg [127:0] inputValue;
reg [127:0] expectedValue;
wire [127:0] outputValue;
sub_byte dut(
.subByteInput (inputValue),
.clock (clock50MHz),
.startTransition (startTransition),
.subByteOutput (outputValue)
);
// Creating the prameters required for the 50MHz clock, and the stoppage of the test bench.
localparam NUM_CYCLES = 20000;
localparam CLOCK_FREQ = 50000000;
real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;
integer half_cycle = 0;
initial begin
// Set input and expected values
expectedValue = 128'ha2c792a02baf939fcb302feb20abc063;
inputValue = 128'h1a3174470b1b226e59084e3c540e1f00;
startTransition = 0;
clock50MHz = 0;
end
initial begin
// Wait 500 clock cylces before setting the startTransition high.
repeat(500) @ (posedge clock50MHz);
startTransition = 1;
end
always begin
#(HALF_CLOCK_PERIOD);
clock50MHz = ~clock50MHz;
half_cycle = half_cycle + 1;
if (half_cycle == (2 * NUM_CYCLES)) begin
// Comparing the acquired outputs with the expected outputs and printing
// the corresponding message depending on the results.
if (outputValue != expectedValue) begin
$display("Fail \n \n",
"For the following inputs: \n",
"Input Value: %h \n \n", inputValue,
"Expected output: \n",
"Output Value: %h \n \n", expectedValue,
"Aquired output: \n",
"Output Value: %h \n", outputValue
);
end
if (outputValue == expectedValue) begin
$display("Pass \n \n",
"For the following inputs: \n",
"Input Value: %h \n \n", inputValue,
"Aquired output: \n",
"Output Value: %h \n \n", outputValue
);
end
// Stop simulation test
$stop;
end
end
endmodule
| 6.595812 |
module SUB_CLA_2 (
iG,
iP,
iC,
oG,
oP,
oC
);
input [1:0] iG, iP;
input iC;
output oG, oP;
output [2:0] oC;
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oG = iG[1] | (iP[1] & iG[0]);
assign oP = iP[1] & iP[0];
assign oC[2] = oG | (oP & oC[0]);
endmodule
| 7.185222 |
module SUB_CLA_24 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [23:0] iA, iB;
input iC;
output [23:0] oS;
output oG, oP, oC;
wire [2:0] G, P, C;
SUB_CLA_8 sub0 (
.iA(iA[7:0]),
.iB(iB[7:0]),
.iC(C[0]),
.oS(oS[7:0]),
.oG(G[0]),
.oP(P[0]),
.oC()
);
SUB_CLA_8 sub1 (
.iA(iA[15:8]),
.iB(iB[15:8]),
.iC(C[1]),
.oS(oS[15:8]),
.oG(G[1]),
.oP(P[1]),
.oC()
);
SUB_CLA_8 sub2 (
.iA(iA[23:16]),
.iB(iB[23:16]),
.iC(C[2]),
.oS(oS[23:16]),
.oG(G[2]),
.oP(P[2]),
.oC()
);
CLA_3 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 7.790524 |
module SUB_CLA_4 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [3:0] iA, iB;
input iC;
output [3:0] oS;
output oG, oP, oC;
wire [3:0] G, P, C;
assign G = (~iA) & iB;
assign P = iA ^~ iB;
CLA_4 ADD_CLA_4_ (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
assign oS = iA ^ iB ^ C;
endmodule
| 7.222282 |
module SUB_CLA_8 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [7:0] iA, iB;
input iC;
output [7:0] oS;
output oG, oP, oC;
wire [1:0] G, P, C;
SUB_CLA_4 sub0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0]),
.oC()
);
SUB_CLA_4 sub1 (
.iA(iA[7:4]),
.iB(iB[7:4]),
.iC(C[1]),
.oS(oS[7:4]),
.oG(G[1]),
.oP(P[1]),
.oC()
);
CLA_2 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 8.464706 |
module SUB_CLA_8_tb ();
reg [7:0] iA, iB;
reg iC;
wire [7:0] oS;
wire oG, oP, oC;
SUB_CLA_8 SUB_CLA_8_ (
.iA(iA),
.iB(iB),
.iC(iC),
.oS(oS),
.oG(oG),
.oP(oP),
.oC(oC)
);
initial begin
#0;
iA = 8'd125;
iB = 8'd11;
iC = 1'b0;
#10;
iA = 8'd127;
iB = 8'd105;
iC = 1'b1;
#10;
iA = 8'b11111111;
iB = 8'b11111111;
iC = 1'b1;
end
endmodule
| 6.723066 |
module sub_control_ID_EX_stage (
input signal_sub,
input clock,
output reg out_sub_control_reg
);
always @(posedge clock) out_sub_control_reg = signal_sub;
endmodule
| 6.703082 |
module sub_deparser #(
parameter C_PKT_VEC_WIDTH = (6 + 4 + 2) * 8 * 8 + 20 * 5 + 256,
parameter C_PARSE_ACT_LEN = 6 // only 6 bits are used here
) (
input clk,
input aresetn,
input parse_act_valid,
input [C_PARSE_ACT_LEN-1:0] parse_act,
input [C_PKT_VEC_WIDTH-1:0] phv_in,
output reg val_out_valid,
output reg [47:0] val_out,
output reg [ 1:0] val_out_type
);
localparam PHV_2B_START_POS = 0 + 5 * 20 + 256;
localparam PHV_4B_START_POS = 16 * 8 + 5 * 20 + 256;
localparam PHV_6B_START_POS = 16 * 8 + 32 * 8 + 5 * 20 + 256;
reg val_out_valid_nxt;
reg [47:0] val_out_nxt;
reg [1:0] val_out_type_nxt;
always @(*) begin
val_out_valid_nxt = 0;
val_out_nxt = 0;
val_out_type_nxt = 0;
if (parse_act_valid) begin
val_out_valid_nxt = 1;
case ({
parse_act[5:4], parse_act[0]
})
// 2B
3'b011: begin
val_out_type_nxt = 2'b01;
case (parse_act[3:1])
3'd0: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*0+:16];
3'd1: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*1+:16];
3'd2: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*2+:16];
3'd3: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*3+:16];
3'd4: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*4+:16];
3'd5: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*5+:16];
3'd6: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*6+:16];
3'd7: val_out_nxt[15:0] = phv_in[PHV_2B_START_POS+16*7+:16];
endcase
end
// 4B
3'b101: begin
val_out_type_nxt = 2'b10;
case (parse_act[3:1])
3'd0: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*0+:32];
3'd1: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*1+:32];
3'd2: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*2+:32];
3'd3: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*3+:32];
3'd4: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*4+:32];
3'd5: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*5+:32];
3'd6: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*6+:32];
3'd7: val_out_nxt[31:0] = phv_in[PHV_4B_START_POS+32*7+:32];
endcase
end
// 6B
3'b111: begin
val_out_type_nxt = 2'b11;
case (parse_act[3:1])
3'd0: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*0+:48];
3'd1: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*1+:48];
3'd2: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*2+:48];
3'd3: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*3+:48];
3'd4: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*4+:48];
3'd5: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*5+:48];
3'd6: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*6+:48];
3'd7: val_out_nxt[47:0] = phv_in[PHV_6B_START_POS+48*7+:48];
endcase
end
endcase
end
end
always @(posedge clk) begin
if (~aresetn) begin
val_out_valid <= 0;
val_out <= 0;
val_out_type <= 0;
end else begin
val_out_valid <= val_out_valid_nxt;
val_out <= val_out_nxt;
val_out_type <= val_out_type_nxt;
end
end
endmodule
| 6.769988 |
module sub_edge_sum (
input clk,
input rst,
input [5:0] din,
output reg [4:0] sum_position_tmp,
output reg [2:0] num_edge_tmp
);
always @(posedge clk or posedge rst) begin
if (rst) begin
sum_position_tmp <= 0;
num_edge_tmp <= 0;
end else begin
sum_position_tmp = din[0]*1 + din[1]*2 + din[2]*3 + din[3]*4 + din[4]*5 + din[5]*6;
num_edge_tmp = din[0] + din[1] + din[2] + din[3] + din[4] + din[5];
end
end
endmodule
| 6.587314 |
module sub_fast (
input clk,
input [31:0] a,
input [31:0] b,
output [31:0] res
);
floating_point_5 sub_core (
.aclk (clk), // input wire aclk
.s_axis_a_tvalid ('b1), // input wire s_axis_a_tvalid
.s_axis_a_tready (s_axis_a_tready), // output wire s_axis_a_tready
.s_axis_a_tdata (a), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid ('b1), // input wire s_axis_b_tvalid
.s_axis_b_tready (s_axis_b_tready), // output wire s_axis_b_tready
.s_axis_b_tdata (b), // input wire [31 : 0] s_axis_b_tdata
.m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid
.m_axis_result_tready('b1), // input wire m_axis_result_tready
.m_axis_result_tdata (res) // output wire [31 : 0] m_axis_result_tdata
);
endmodule
| 6.640754 |
module sub_full (
S,
C_out,
A,
B,
C_in
);
input A, B, C_in;
output S, C_out;
wire temp_S, first_C_out, second_C_out;
sub_half first_S (
temp_S,
first_C_out,
A,
B
);
sub_half second_S (
S,
second_C_out,
temp_S,
C_in
);
or final_C_out (C_out, second_C_out, first_C_out);
endmodule
| 6.80851 |
module sub_func (
X,
Y,
diff,
overflow
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] dif;
output wire overflow;
wire if_do = 0; //this here means we will invert, because this follows op_code[0] for substraction, which is 0
wire Y_prime;
twos_complement inverter (
.X(Y),
.if_do(if_do),
.Y(Y_prime)
);
add_rca_32_bit adder (
.X (X),
.Y (Y_prime),
.ci (ci),
.sum(sum),
.co (overflow)
);
endmodule
| 7.213675 |
module sub_half (
S,
C,
A,
B
);
input A, B;
output S, C;
wire Anot;
xor (S, A, B);
not (Anot, A);
and (C, Anot, B);
endmodule
| 7.152518 |
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