code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module st_weight_addr_gen_Muxi0u16u1_4_7 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_8 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_9 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxu6i32u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input ctrl1;
output [5:0] out1;
wire [5:0] asc001;
reg [5:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = 6'B100000;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxu6i32u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input ctrl1;
output [5:0] out1;
wire [5:0] asc001;
reg [5:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = 6'B100000;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxu6i32u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input ctrl1;
output [5:0] out1;
wire [5:0] asc001;
reg [5:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = 6'B100000;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_12 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Nei1u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_NotEQ_16Ux1U_1U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_10 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_11 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_2 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_3 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_5 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_6 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_7 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_8 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Not_1U_1U_4_9 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_10 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_5 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_6 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_7 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_8 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_17_4_9 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_2_20_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_21_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_21_4_0 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_22_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_22_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_22_4_0 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_N_Mux_16_3_22_4_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4;
input [13:0] in3;
input [14:0] in2;
input [7:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 =
-{ctrl1 == 8'B00000100} & in3 |
-{ctrl1 == 8'B00000010} & in2 |
-{ctrl1[1:0] == 2'B01} & in4 |
-{{ctrl1[2], ctrl1[0]} == 2'B01} & in4 |
-{ctrl1[2:1] == 2'B00} & in4 |
-{ctrl1[2:1] == 2'B11} & in4 |
-{ctrl1[3] == 1'B1} & in4 |
-{ctrl1[4] == 1'B1} & in4 |
-{ctrl1[5] == 1'B1} & in4 |
-{ctrl1[6] == 1'B1} & in4 |
-{ctrl1[7] == 1'B1} & in4 ;
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Or_1Ux1U_1U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi1u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi32u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi32u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
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