code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_weight_addr_gen_Subi32u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_12 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_13 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi32u16_4_14 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_15 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module for the st_weight_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************************************************************************/
`timescale 1 ps / 1 ps
module st_weight_addr_gen_vlwrapper(
clk,
rstn,
stop,
start,
start_rising,
feature_width,
feature_height,
feature_channel,
out_feature_width,
out_feature_height,
out_feature_channel,
filter_width,
filter_height,
filter_channel,
stride_x,
stride_y,
pad_top_size,
pad_bottom_size,
pad_left_size,
pad_right_size,
read_weight_base_addr,
st_weight_addr,
st_weight_addr_valid,
st_weight_data_valid,
cache_en
);
input clk;
input rstn;
input stop;
input [7:0] start;
input start_rising;
input [15:0] feature_width;
input [15:0] feature_height;
input [15:0] feature_channel;
input [15:0] out_feature_width;
input [15:0] out_feature_height;
input [15:0] out_feature_channel;
input [15:0] filter_width;
input [15:0] filter_height;
input [15:0] filter_channel;
input [7:0] stride_x;
input [7:0] stride_y;
input [7:0] pad_top_size;
input [7:0] pad_bottom_size;
input [7:0] pad_left_size;
input [7:0] pad_right_size;
input [31:0] read_weight_base_addr;
output [31:0] st_weight_addr;
reg[31:0] st_weight_addr;
wire [31:0] m_st_weight_addr;
output st_weight_addr_valid;
reg st_weight_addr_valid;
wire m_st_weight_addr_valid;
output st_weight_data_valid;
reg st_weight_data_valid;
wire m_st_weight_data_valid;
output cache_en;
reg cache_en;
wire m_cache_en;
// Instantiate the Verilog module that instantiates the SystemC module
st_weight_addr_gen_type_wrapper st_weight_addr_gen_sc(
.clk(clk),
.rstn(rstn),
.stop(stop),
.start(start),
.start_rising(start_rising),
.feature_width(feature_width),
.feature_height(feature_height),
.feature_channel(feature_channel),
.out_feature_width(out_feature_width),
.out_feature_height(out_feature_height),
.out_feature_channel(out_feature_channel),
.filter_width(filter_width),
.filter_height(filter_height),
.filter_channel(filter_channel),
.stride_x(stride_x),
.stride_y(stride_y),
.pad_top_size(pad_top_size),
.pad_bottom_size(pad_bottom_size),
.pad_left_size(pad_left_size),
.pad_right_size(pad_right_size),
.read_weight_base_addr(read_weight_base_addr),
.st_weight_addr(m_st_weight_addr),
.st_weight_addr_valid(m_st_weight_addr_valid),
.st_weight_data_valid(m_st_weight_data_valid),
.cache_en(m_cache_en)
);
// Always blocks for non-blocking assignments of type_wrapper outputs to
// Verilog Verificatoin wrapper outputs.
always @(m_st_weight_addr)
begin
st_weight_addr <= m_st_weight_addr;
end
always @(m_st_weight_addr_valid)
begin
st_weight_addr_valid <= m_st_weight_addr_valid;
end
always @(m_st_weight_data_valid)
begin
st_weight_data_valid <= m_st_weight_data_valid;
end
always @(m_cache_en)
begin
cache_en <= m_cache_en;
end
endmodule
| 7.408523 |
module BRAM (
clk,
add,
data_in,
data_out,
cs,
we,
oe
);
// parameters
parameter varWIDTH = 32; // number of bits in a word
parameter ADD_WIDTH = 10; // number of bits in the address
parameter PIPE_WIDTH = 16; // number of words in the output
// inputs
input clk, cs, we;
input [PIPE_WIDTH-1:0] oe;
input [varWIDTH-1:0] data_in;
input [ADD_WIDTH-1:0] add;
// outputs
output [varWIDTH*PIPE_WIDTH-1:0] data_out;
// internal signals
wire [ADD_WIDTH-$clog2(PIPE_WIDTH)-1:0] add_eff;
wire [$clog2(PIPE_WIDTH)-1:0] rem;
wire [PIPE_WIDTH-1:0] write_en, we_decode;
// handle the address and write enable
assign add_eff = add >> $clog2(PIPE_WIDTH);
assign rem = add[$clog2(PIPE_WIDTH)-1:0]; // rem is used to select one of the blocks for writing
assign we_decode = 1 << rem; // this is a decoder, it selects the one block we are writing to
assign write_en = (we) ? we_decode:{PIPE_WIDTH{1'b0}}; // when writing, only one block should be selected
// create multiple BRAM modules(equal to the number of pipes)
generate
genvar i;
for (i = PIPE_WIDTH; i > 0; i = i - 1) begin : identifier
ram #(
.varWIDTH (varWIDTH),
.ADD_WIDTH(ADD_WIDTH - $clog2(PIPE_WIDTH))
) bram_vector (
.clk(clk),
.add(add_eff),
.data_in(data_in),
.data_out(data_out[i*varWIDTH-1-:varWIDTH]),
.cs(cs),
.we(write_en[i-1]),
.oe(oe[i-1])
);
end
endgenerate
endmodule
| 7.098866 |
module ram (
clk,
add,
data_in,
data_out,
cs,
we,
oe
);
parameter varWIDTH = 32; // number of bits in the output
parameter ADD_WIDTH = 10; // number of bits in the address
parameter FILENAME = "";
localparam [63:0] RAM_SIZE = 1 << ADD_WIDTH; // ram size
//input declaration
input clk;
input cs; // chip select
input we; // enables writing
input oe; // output enable
input [ADD_WIDTH-1:0] add; // address
input [varWIDTH-1:0] data_in;
//output declaration
output reg [varWIDTH-1:0] data_out;
// internal variables
reg [varWIDTH-1:0] memory[0:RAM_SIZE-1];
//code starts here
// initalize memory from file
initial begin
if (FILENAME != "") $readmemh(FILENAME, memory);
end
// handle writing to RAM
always @(posedge clk) begin
if (cs && we) memory[add] <= data_in;
end
// handle reading from RAM
always @(posedge clk) begin
if (cs && !we && oe) data_out <= memory[add];
else data_out <= {varWIDTH{1'b0}};
end
endmodule
| 7.56569 |
module ram_tb ();
parameter DATA_WIDTH = 32; // number of bits in the output
parameter ADD_WIDTH = 4; // number of bits in the address
parameter RAM_SIZE = 1 << ADD_WIDTH; // ram size
parameter PIPE_SIZE = 4;
reg clk, cs, we, oe;
reg [ADD_WIDTH-1:0] add;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH*PIPE_SIZE-1:0] data_out;
wire [DATA_WIDTH-1:0] data0, data1, data2, data3;
ram #(
.varWIDTH (32),
.ADD_WIDTH (ADD_WIDTH),
.PIPE_WIDTH(PIPE_SIZE)
) RAM_TEST (
clk,
add,
data_in,
data_out,
cs,
we,
oe
);
assign data0 = data_out[31:0];
assign data1 = data_out[63:32];
assign data2 = data_out[95:64];
assign data3 = data_out[DATA_WIDTH*PIPE_SIZE-1:96];
initial begin
// write to address 0
#0 clk = 0;
#0 cs = 1;
#0 we = 1;
#0 oe = 0;
#0 add = 4'd0;
#0 data_in = 32'd5;
// write to address 1
#35 add = 4'd1;
#0 data_in = 32'd15;
// write to address 2
#35 add = 4'd2;
#0 data_in = 32'd25;
// write to address 3
#35 add = 4'd3;
#0 data_in = 32'd23;
// write to address 4
#35 add = 4'd4;
#0 data_in = 32'd12341234;
// add 5
#35 add = 4'd5;
#0 data_in = 32'd12323;
// add 6
#35 add = 4'd6;
#0 data_in = 32'd0;
// add 7
#35 add = 4'd7;
#0 data_in = 32'd12;
// add 8
#35 add = 4'd8;
#0 data_in = 32'd1303;
// read first 4 address
#35 we = 0;
oe = 1;
add = 4'd0;
// read next 4
#35 add = 4'd4;
// read next 4
#35 add = 4'd8;
#35 add = 4'd12;
// read address 1
#35 add = 4'd1;
#100 $stop;
end
always begin
#5 clk = ~clk;
end
endmodule
| 7.127235 |
module distcalc_euclid (
clk,
EN_Pipe,
EN_Acc,
EN_Sqrt,
RST_Acc,
RST_Sqrt,
PRE_Acc,
invec0,
invec1,
RDY_Pipe,
RDY_Acc,
RDY_Sqrt,
outval
);
//Parameters
parameter VARWIDTH = 32;
parameter PIPEWIDTH = 16;
//Inputs
input clk;
input EN_Pipe;
input EN_Acc;
input EN_Sqrt;
input RST_Acc;
input RST_Sqrt;
input PRE_Acc;
input [VARWIDTH*PIPEWIDTH-1:0] invec0;
input [VARWIDTH*PIPEWIDTH-1:0] invec1;
//Outputs
output reg RDY_Pipe;
output RDY_Acc;
output RDY_Sqrt;
output reg [VARWIDTH-1:0] outval;
//Internal Data Types
wire [VARWIDTH*PIPEWIDTH-1:0] in_pipe0;
wire [VARWIDTH*PIPEWIDTH-1:0] in_pipe1;
wire [VARWIDTH*PIPEWIDTH-1:0] out_pipe;
reg [VARWIDTH*PIPEWIDTH-1:0] in_acc;
wire [VARWIDTH-1:0] out_acc;
reg [VARWIDTH-1:0] in_sqrt;
wire [VARWIDTH-1:0] out_sqrt;
//Code
//Modules
pipes_diffsquare #(
.WIDTH(PIPEWIDTH)
) pipes (
.EN(EN_Pipe),
.vals0(in_pipe0),
.vals1(in_pipe1),
.pipeout(out_pipe)
);
accumulator #(
.FLOAT(1),
.WIDTH(PIPEWIDTH)
) accum (
.EN (EN_Acc),
.clk (clk),
.rst (RST_Acc),
.pre (PRE_Acc),
.vals(in_acc),
.rdy (RDY_Acc),
.sum (out_acc)
);
squareroot #(
.WIDTH(VARWIDTH)
) sqrt (
.EN(EN_Sqrt),
.clk(clk),
.rst(RST_Sqrt),
.a(in_sqrt),
.rdy(RDY_Sqrt),
.sqrt(out_sqrt)
);
//Default Assignments
assign in_pipe0 = invec0;
assign in_pipe1 = invec1;
//State Machine
always @(*) begin
if (EN_Pipe) begin
in_acc <= out_pipe;
RDY_Pipe <= 0;
end else begin
RDY_Pipe <= 1;
in_acc <= in_acc;
end
if (RDY_Acc) begin
in_sqrt <= out_acc;
end else begin
in_sqrt <= in_sqrt;
end
if (RDY_Sqrt) begin
outval <= out_sqrt;
end else begin
outval <= 0;
end
end
endmodule
| 7.057303 |
module distance_test;
localparam varWIDTH = 32;
localparam pipeWIDTH = 16;
localparam HEADER_LENGTH = 2;
parameter ADD_WIDTH = 12; // what should the maximum value be?
/* Pulse input */
reg clk, START;
wire en_a, en_s;
wire rdy_p, rdy_a, rdy_s;
wire rst_a, rst_s, pre_a;
wire [ADD_WIDTH-1:0] bram_add, ctrl_add, loader_add, dist_add;
wire [31:0] dram_add, dram_in, dram_out;
wire [varWIDTH*pipeWIDTH-1:0] vector0;
wire [varWIDTH*pipeWIDTH-1:0] vector1;
wire [varWIDTH-1:0] distance;
wire [pipeWIDTH-1:0] EN_Pipe;
wire loader_done;
wire [5:0] data_flags;
wire [31:0] vecWIDTH, vecCOUNT, vecINDEX;
reg load_vectors, mem_rst;
initial begin
// Load vectors into Bram
#0 clk = 1'b0;
#0 mem_rst = 1'b1;
#35 mem_rst = 1'b0;
#10 START = 1'b1;
#35 START = 1'b0;
// TODO: initiate control unit and generate output
end
always begin
#5 clk = !clk;
end
assign bram_add = (loader_done) ? ctrl_add : loader_add;
reg32 vector_count (
.clk(clk),
.en(data_flags[0]),
.reset(1'b0),
.data(dram_out),
.q(vecCOUNT)
);
reg32 vector_width (
.clk(clk),
.en(data_flags[1]),
.reset(1'b0),
.data(dram_out),
.q(vecWIDTH)
);
reg32 vector_index (
.clk(clk),
.en(data_flags[2]),
.reset(1'b0),
.data(dram_out),
.q(vecINDEX)
);
// MEMORY CONTROLLER
vec_loader #(
.ADD_WIDTH(ADD_WIDTH),
.HEADER_LENGTH(HEADER_LENGTH)
) vec_ctrl (
.clk(clk),
.rst(mem_rst),
.en(START),
.sqrt_rdy(rdy_s),
.data_flags(data_flags),
.VECTOR_WIDTH(vecWIDTH),
.dram_add(dram_add),
.bram_add(loader_add),
.dist_add(dist_add),
.done(loader_done)
);
// create "DRAM"
ram #(
.varWIDTH (varWIDTH),
.ADD_WIDTH(ADD_WIDTH),
.FILENAME ("C:\\Users\\mcowl_000\\Desktop\\GitStuff\\Elmo\\datasets\\simple.list")
) dram (
.clk(!clk),
.add(dram_add),
.data_in(dram_in),
.data_out(dram_out),
.cs(1'b1),
.we(1'b0),
.oe(1'b1)
);
// BRAM for the target vector
BRAM #(
.varWIDTH (varWIDTH),
.ADD_WIDTH (ADD_WIDTH),
.PIPE_WIDTH(pipeWIDTH)
) bram_target (
.clk(clk),
.add(bram_add),
.data_in(dram_out),
.data_out(vector0),
.cs(1'b1),
.we(data_flags[3]),
.oe(EN_Pipe)
);
// BRAM for the training vector
BRAM #(
.varWIDTH (varWIDTH),
.ADD_WIDTH (ADD_WIDTH),
.PIPE_WIDTH(pipeWIDTH)
) bram_training (
.clk(clk),
.add(bram_add),
.data_in(dram_out),
.data_out(vector1),
.cs(1'b1),
.we(data_flags[4]),
.oe(EN_Pipe)
);
ram #(
.varWIDTH (varWIDTH),
.ADD_WIDTH(ADD_WIDTH)
) dist_ram (
.clk(clk),
.add(dist_add),
.data_in(distance),
.data_out(),
.cs(1'b1),
.we(data_flags[5]),
.oe(1'b0)
);
distcalc_euclid #(
.VARWIDTH (varWIDTH),
.PIPEWIDTH(pipeWIDTH)
) distcalc (
.clk(!clk),
.EN_Pipe(1'b1),
.EN_Acc(en_a),
.EN_Sqrt(en_s), //Enables (inputs)
.RST_Acc(rst_a),
.RST_Sqrt(rst_s),
.PRE_Acc(pre_a), //Resets (inputs)
.invec0(vector0),
.invec1(vector1),
.RDY_Pipe(rdy_p),
.RDY_Acc(rdy_a),
.RDY_Sqrt(rdy_s), //Ready Flags (outputs)
.outval(distance)
);
dist_control_unit #(
.pipeWIDTH(pipeWIDTH),
.ADD_WIDTH(ADD_WIDTH)
) distctrl (
.VECTOR_WIDTH(vecWIDTH),
.clk(clk),
.STARTCALC(loader_done),
.EN_Pipe(EN_Pipe),
.EN_Acc(en_a),
.EN_Sqrt(en_s), //Enables (outputs)
.RST_Acc(rst_a),
.RST_Sqrt(rst_s),
.PRE_Acc(pre_a), //Resets
.RDY_Acc(rdy_a),
.RDY_Sqrt(rdy_s),
.ADDR_RAM(ctrl_add)
);
initial $monitor("%g\t\n", $time);
endmodule
| 7.013026 |
module pipes_diffsquare (
EN,
vals0,
vals1,
pipeout
);
parameter WIDTH = 16; //size of each vals vector
//local parameters
localparam VARWIDTH = 32;
//input declaration
input EN;
input [VARWIDTH*WIDTH-1:0] vals0, vals1;
wire [VARWIDTH-1:0] in_vals0[0:WIDTH-1];
wire [VARWIDTH-1:0] in_vals1[0:WIDTH-1];
generate
genvar count;
for (count = WIDTH; count > 0; count = count - 1) begin : in_vals_assignment
assign in_vals0[count-1] = vals0[count*VARWIDTH-1:(count-1)*VARWIDTH];
assign in_vals1[count-1] = vals1[count*VARWIDTH-1:(count-1)*VARWIDTH];
end
endgenerate
//output declaration
output [VARWIDTH*WIDTH-1:0] pipeout;
wire [VARWIDTH*WIDTH-1:0] pipeout;
wire [VARWIDTH-1:0] out_pipe[0:WIDTH-1];
generate
for (count = WIDTH; count > 0; count = count - 1) begin : pipeout_assignment
assign pipeout[count*VARWIDTH-1:(count-1)*VARWIDTH] = out_pipe[count-1];
end
endgenerate
//internal data types
wire [VARWIDTH-1:0] diffsquare[0:WIDTH-1];
//code begins here
generate
for (count = 0; count < WIDTH; count = count + 1) begin : diffsquared_generator
diffsquared32 diffsquare32_Pipe (
.a (in_vals0[count]),
.b (in_vals1[count]),
.out(diffsquare[count])
);
end
endgenerate
generate
genvar i;
for (i = 0; i < WIDTH; i = i + 1) begin : output_assignment
assign out_pipe[i] = (EN) ? diffsquare[i] : 0;
end
endgenerate
endmodule
| 7.791017 |
module diffsquared32 (
a,
b,
out
);
localparam VARWIDTH = 32;
//input declarations
input [VARWIDTH-1:0] a, b;
//output declarations
output [VARWIDTH-1:0] out;
wire [VARWIDTH-1:0] out;
//internal wires declaration
wire [VARWIDTH-1:0] sum;
wire [VARWIDTH-1:0] float;
wire [VARWIDTH-1:0] square;
//code begins here
adder32 add32_inputs (
.a (a),
.b (~b),
.cin(1'b1),
.sum(sum)
);
int2float32 i2f32_sum (
.a(sum),
.b(float)
);
square_f32 squaref32_float (
.a (float),
.sqr(square)
);
assign out = square;
endmodule
| 7.985967 |
module squareroot (
EN,
clk,
rst,
a,
rdy,
sqrt
);
parameter WIDTH = 32;
//input declaration
input EN, clk, rst;
input [WIDTH - 1:0] a;
//output declaration
output rdy;
wire rdy;
output [WIDTH - 1:0] sqrt;
reg [WIDTH - 1:0] sqrt;
//internal data types
reg rst_internal;
wire [WIDTH - 1:0] sqrt_internal;
//code starts here
squareroot_f32 sqrtf32 (
.clk(clk),
.EN(EN),
.rst(rst_internal),
.a(a),
.rdy(rdy),
.sqrt(sqrt_internal)
);
always @(*) begin
if (EN) begin
rst_internal <= 0;
if (rdy && EN) begin
sqrt <= sqrt_internal;
end else begin
sqrt <= 0;
end
end else begin
sqrt <= 0;
rst_internal <= rst;
end
end
endmodule
| 8.070748 |
module sub2 (
input [4:0] a_e,
output [4:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 6.873213 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
(* use_dsp48 = "yes" *) module sub28(A, B, CLK, CE, SCLR, S);
input signed [27:0]A;
input signed [27:0]B;
input CLK;
input CE;
input SCLR;
output reg [27:0]S;
always @(posedge CLK)
if(SCLR)
S <= 0;
else if(CE)
S <= A - B;
endmodule
| 6.593332 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.821676 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
Sub2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
(* use_dsp48 = "yes" *) module sub_48b(A, B, CLK, CE, SCLR, S);
input signed [47:0]A;
input signed [47:0]B;
input CLK;
input CE;
input SCLR;
output reg [47:0]S;
always @(posedge CLK)
if(SCLR)
S <= 0;
else if(CE)
S <= A - B;
endmodule
| 6.593332 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.507677 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
Sub4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
Sub4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module sub8 (
output wire [7:0] out,
input wire [7:0] A,
input wire [7:0] B
);
assign out = A - B;
endmodule
| 7.904405 |
module subbytes_block #(
// PARAMETERS.
parameter NB_BYTE = 8,
parameter N_BYTES = 16,
parameter CREATE_OUTPUT_REG = 0,
parameter USE_LUT = 1
) (
// OUTPUTS.
output wire [N_BYTES * NB_BYTE - 1 : 0] o_state,
// INPUTS.
input wire [N_BYTES * NB_BYTE - 1 : 0] i_state,
input wire i_valid,
input wire i_reset,
input wire i_clock
);
// LOCAL PARAMETERS.
localparam BAD_CONF = (NB_BYTE != 8);
// INTERNAL SIGNALS.
genvar ii;
// ALGORITHM BEGIN.
// Creating N_BYTES instances of S-Box block.
generate
for (ii = 0; ii < N_BYTES; ii = ii + 1) begin : genfor_sboxes
// Local signals.
wire [NB_BYTE-1:0] ii_o_byte;
wire [NB_BYTE-1:0] ii_i_byte;
// Global inputs to local input.
assign ii_i_byte = i_state[ii*NB_BYTE+:NB_BYTE];
if (USE_LUT == 1) begin : genif_use_lut
// S-Box instance.
byte_substitution_box #(
.NB_BYTE (NB_BYTE),
.CREATE_OUTPUT_REG(CREATE_OUTPUT_REG)
) u_byte_substitution_box__ii (
.o_byte (ii_o_byte),
.i_byte (ii_i_byte),
.i_valid(i_valid),
.i_clock(i_clock)
);
end // genif_use_lut
else
begin : genelse_use_lut
// S-Box instance.
byte_substitution_algorithm #(
.NB_BYTE (NB_BYTE),
.CREATE_OUTPUT_REG(CREATE_OUTPUT_REG)
) u_byte_substitution_algorithm__ii (
.o_byte (ii_o_byte),
.i_byte (ii_i_byte),
.i_valid(i_valid),
.i_reset(i_reset), // FIXME: Analizar fanout de reset.
.i_clock(i_clock)
);
end // genelse_use_lut
// Local output to global outputs.
assign o_state[ii*NB_BYTE+:NB_BYTE] = ii_o_byte;
end // genfor_sboxes
endgenerate
endmodule
| 6.840381 |
module subBytes_mem (
clk,
rst,
W_En,
R_En,
addr_in,
addr_out,
in,
out
);
input wire clk, rst, W_En, R_En;
input wire [3:0] addr_in, addr_out;
input wire [7:0] in;
output reg [7:0] out;
reg [7:0] ram[0:15];
integer i;
always @(posedge clk or negedge rst) begin
if (!rst) begin
out <= 0;
for (i = 0; i <= 15; i = i + 1) ram[i] <= 0;
end else begin
if (W_En) ram[addr_in] <= in;
if (R_En) out <= ram[addr_out];
end
end
endmodule
| 6.720435 |
module subBytes (
input [31:0] input_col,
output [31:0] output_col
);
//A song of Wires and Regs
reg [31:0] working_reg;
assign output_col = working_reg;
wire [7:0] output_col_byte1, output_col_byte2, output_col_byte3, output_col_byte4;
sbox SBOX (
.input_byte (input_col[7:0]),
.output_byte(output_col_byte1)
);
sbox SBOX2 (
.input_byte (input_col[15:8]),
.output_byte(output_col_byte2)
);
sbox SBOX3 (
.input_byte (input_col[23:16]),
.output_byte(output_col_byte3)
);
sbox SBO4 (
.input_byte (input_col[31:24]),
.output_byte(output_col_byte4)
);
/*
initial
begin
working_reg = 0;
end
*/
always @(*) begin
working_reg[7:0] = output_col_byte1;
working_reg[15:8] = output_col_byte2;
working_reg[23:16] = output_col_byte3;
working_reg[31:24] = output_col_byte4;
end
endmodule
| 7.325733 |
module subByte_rowShift (
input clk,
input rst_n,
input [127 : 0] iBlockIn,
output reg [127 : 0] oBlockout
);
wire [127 : 0] wSubOut, wRotShift;
//字节替换逻辑，用8个双口rom实现
rom_2p rom_2p_inst0 (
.address_a(iBlockIn[127 : 120]),
.address_b(iBlockIn[119 : 112]),
.clock(clk),
.q_a(wSubOut[127 : 120]),
.q_b(wSubOut[119 : 112])
);
rom_2p rom_2p_inst1 (
.address_a(iBlockIn[111 : 104]),
.address_b(iBlockIn[103 : 96]),
.clock(clk),
.q_a(wSubOut[111 : 104]),
.q_b(wSubOut[103 : 96])
);
rom_2p rom_2p_inst2 (
.address_a(iBlockIn[95 : 88]),
.address_b(iBlockIn[87 : 80]),
.clock(clk),
.q_a(wSubOut[95 : 88]),
.q_b(wSubOut[87 : 80])
);
rom_2p rom_2p_inst3 (
.address_a(iBlockIn[79 : 72]),
.address_b(iBlockIn[71 : 64]),
.clock(clk),
.q_a(wSubOut[79 : 72]),
.q_b(wSubOut[71 : 64])
);
rom_2p rom_2p_inst4 (
.address_a(iBlockIn[63 : 56]),
.address_b(iBlockIn[55 : 48]),
.clock(clk),
.q_a(wSubOut[63 : 56]),
.q_b(wSubOut[55 : 48])
);
rom_2p rom_2p_inst5 (
.address_a(iBlockIn[47 : 40]),
.address_b(iBlockIn[39 : 32]),
.clock(clk),
.q_a(wSubOut[47 : 40]),
.q_b(wSubOut[39 : 32])
);
rom_2p rom_2p_inst6 (
.address_a(iBlockIn[31 : 24]),
.address_b(iBlockIn[23 : 16]),
.clock(clk),
.q_a(wSubOut[31 : 24]),
.q_b(wSubOut[23 : 16])
);
rom_2p rom_2p_inst7 (
.address_a(iBlockIn[15 : 8]),
.address_b(iBlockIn[7 : 0]),
.clock(clk),
.q_a(wSubOut[15 : 8]),
.q_b(wSubOut[7 : 0])
);
//行移位，直接将线路对应连接即可
assign wRotShift = {
wSubOut[127 : 120],
wSubOut[87 : 80],
wSubOut[47 : 40],
wSubOut[7 : 0],
wSubOut[95 : 88],
wSubOut[55 : 48],
wSubOut[15 : 8],
wSubOut[103 : 96],
wSubOut[63 : 56],
wSubOut[23 : 16],
wSubOut[111 : 104],
wSubOut[71 : 64],
wSubOut[31 : 24],
wSubOut[119 : 112],
wSubOut[79 : 72],
wSubOut[39 : 32]
};
//输出寄存器，传递给下一级信号
always @(posedge clk or negedge rst_n) begin
if (!rst_n) oBlockout <= 0;
else oBlockout <= wRotShift;
end
endmodule
| 7.970927 |
module subchannel_sw (
input clk,
input reset,
input clear,
//Data and code inputs.
input ca_bit,
input [ (INPUT_WIDTH-1):0] data_i,
input [ (INPUT_WIDTH-1):0] data_q,
//Accumulator states.
input [(OUTPUT_WIDTH-1):0] accumulator_i_in,
input [(OUTPUT_WIDTH-1):0] accumulator_q_in,
output wire [(OUTPUT_WIDTH-1):0] accumulator_i_out,
output wire [(OUTPUT_WIDTH-1):0] accumulator_q_out
);
parameter INPUT_WIDTH = 1;
parameter OUTPUT_WIDTH = 1;
//In-phase accumulator.
accumulator_sw #(
.INPUT_WIDTH (INPUT_WIDTH),
.OUTPUT_WIDTH(OUTPUT_WIDTH)
) accumulator_i (
.clk(clk),
.reset(reset),
.clear(clear),
.baseband_input(data_i),
.ca_bit(ca_bit),
.accumulator_in(accumulator_i_in),
.accumulator_out(accumulator_i_out)
);
//Quadrature accumulator.
accumulator_sw #(
.INPUT_WIDTH (INPUT_WIDTH),
.OUTPUT_WIDTH(OUTPUT_WIDTH)
) accumulator_q (
.clk(clk),
.reset(reset),
.clear(clear),
.baseband_input(data_q),
.ca_bit(ca_bit),
.accumulator_in(accumulator_q_in),
.accumulator_out(accumulator_q_out)
);
endmodule
| 6.653672 |
module subc_ctl ( /*AUTOARG*/
// Outputs
nack,
rt_rst,
// Inputs
ai2cb,
ack,
eof,
rt_ra,
rt_err,
rst_n
);
input ai2cb; // the ack from output ports
input ack; // the ack from the last stage of the input buffer
input eof; // the eof bit from the last stage of the input buffer
input rt_ra; // ack from the switch allocator
input rt_err; // invalid router decision
input rst_n; // the global active low reset signal
output nack; // the ack to the last stage of the input buffer
output rt_rst; // the router reset signal
wire csc; // internal wires to handle the CSC of the STG
wire acko; // the ack signal after the C2N gate
wire fend; // the end of frame indicator
wire acken; // active low ack enable
`ifdef ENABLE_LOOKAHEAD
c2n CD (
.q(acko),
.a(ai2cb),
.b(ack)
); // the C2N gate to avoid early withdrawal
`else
assign acko = ai2cb;
`endif
c2p CEN (
.b(eof),
.a(acko),
.q(fend)
);
c2 C (
.a0(rt_ra),
.a1(fend),
.q (csc)
);
nand U1 (acken, rt_ra, ~csc);
nor U2 (rt_rst, fend, ~csc);
nor AG (nack, acko & (~eof), acken | (rt_err & ack), ~rst_n);
endmodule
| 7.498287 |
module Suber (
input [31:0] data1,
input [31:0] data2,
output reg [31:0] result,
output reg zero,
output reg neg
);
/* Inputs declaration */
wire signed [31:0] data1;
wire signed [31:0] data2;
/* Main function */
always @(*) begin
result = data1 - data2;
zero = (result == 32'b0);
neg = (result < 0);
end
endmodule
| 7.580376 |
module subErrCtrlSplitter (
err_en,
err_ctrl,
sub_err_en,
sub_err_ctrl
);
parameter INW = 1; // Input bitwidth
parameter OUTW = 1; // Output bitwidth
parameter LOW = 0; // Lower limit for the submodule's error control
parameter HIGH = 1; // Upper limit for the submodule's error control
input err_en;
input [INW-1 : 0] err_ctrl;
output sub_err_en;
output [OUTW-1 : 0] sub_err_ctrl;
assign sub_err_en = ((err_ctrl > HIGH) || (err_ctrl < LOW)) ? 1'b0 : err_en;
assign sub_err_ctrl = err_ctrl - LOW;
endmodule
| 8.571143 |
module subkeys (
select,
key,
k1,
k2,
k3,
k4,
k5,
k6,
k7,
k8,
k9,
k10,
k11,
k12,
k13,
k14,
k15,
k16
);
input [64:1] key;
input select;
output [48:1] k1;
output [48:1] k2;
output [48:1] k3;
output [48:1] k4;
output [48:1] k5;
output [48:1] k6;
output [48:1] k7;
output [48:1] k8;
output [48:1] k9;
output [48:1] k10;
output [48:1] k11;
output [48:1] k12;
output [48:1] k13;
output [48:1] k14;
output [48:1] k15;
output [48:1] k16;
wire [28:1] lefto;
wire [28:1] righto;
wire [28:1] l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16;
wire [28:1] r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16;
key_Processor p (
select,
lefto,
righto,
key
);
shiftb1 h1 (
lefto,
righto,
l1,
r1
); //1
pc2 p1 (
l1,
r1,
k1
);
shiftb2 h2 (
l1,
r1,
l2,
r2
); //2
pc2 p2 (
l2,
r2,
k2
);
shiftb2 h3 (
l2,
r2,
l3,
r3
); //2
pc2 p3 (
l3,
r3,
k3
);
shiftb2 h4 (
l3,
r3,
l4,
r4
); //2
pc2 p4 (
l4,
r4,
k4
);
shiftb2 h5 (
l4,
r4,
l5,
r5
); //2
pc2 p5 (
l5,
r5,
k5
);
shiftb2 h6 (
l5,
r5,
l6,
r6
); //2
pc2 p6 (
l6,
r6,
k6
);
shiftb2 h7 (
l6,
r6,
l7,
r7
); //2
pc2 p7 (
l7,
r7,
k7
);
shiftb2 h8 (
l7,
r7,
l8,
r8
); //2
pc2 p8 (
l8,
r8,
k8
);
shiftb1 h9 (
l8,
r8,
l9,
r9
); //1
pc2 p9 (
l9,
r9,
k9
);
shiftb2 h10 (
l9,
r9,
l10,
r10
); //2
pc2 p10 (
l10,
r10,
k10
);
shiftb2 h11 (
l10,
r10,
l11,
r11
); //2
pc2 p11 (
l11,
r11,
k11
);
shiftb2 h12 (
l11,
r11,
l12,
r12
); //2
pc2 p12 (
l12,
r12,
k12
);
shiftb2 h13 (
l12,
r12,
l13,
r13
); //2
pc2 p13 (
l13,
r13,
k13
);
shiftb2 h14 (
l13,
r13,
l14,
r14
); //2
pc2 p14 (
l14,
r14,
k14
);
shiftb2 h15 (
l14,
r14,
l15,
r15
); //2
pc2 p15 (
l15,
r15,
k15
);
shiftb1 h16 (
l15,
r15,
l16,
r16
); //1
pc2 p16 (
l16,
r16,
k16
);
endmodule
| 7.044768 |
module z_add (
input x,
input y,
output [1:0] z
);
assign z = x + y;
endmodule
| 8.007447 |
module subordinate_verification #(
parameter C_AXI_ADDR_WIDTH = 4,
localparam C_AXI_DATA_WIDTH = 32
) (
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [ C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [ 2:0] S_AXI_AWPROT,
//
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
input wire [ C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
//
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
output wire [ 1:0] S_AXI_BRESP,
//
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
input wire [ C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [ 2:0] S_AXI_ARPROT,
//
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [ C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [ 1:0] S_AXI_RRESP
// }}}
);
subordinate s (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
////////////////////////////////////////////////////////////////////////
//
// The AXI-lite control interface
//
////////////////////////////////////////////////////////////////////////
//
// {{{
localparam F_AXIL_LGDEPTH = 4;
wire [F_AXIL_LGDEPTH-1:0] faxil_rd_outstanding, faxil_wr_outstanding, faxil_awr_outstanding;
faxil_slave #(
// {{{
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.F_LGDEPTH(F_AXIL_LGDEPTH),
.F_AXI_MAXWAIT(3),
.F_AXI_MAXDELAY(3),
.F_AXI_MAXRSTALL(5),
.F_OPT_COVER_BURST(4)
// }}}
) faxil (
// {{{
.i_clk(S_AXI_ACLK),
.i_axi_reset_n(S_AXI_ARESETN),
//
.i_axi_awvalid(S_AXI_AWVALID),
.i_axi_awready(S_AXI_AWREADY),
.i_axi_awaddr(S_AXI_AWADDR),
.i_axi_awprot(S_AXI_AWPROT),
//
.i_axi_wvalid(S_AXI_WVALID),
.i_axi_wready(S_AXI_WREADY),
.i_axi_wdata(S_AXI_WDATA),
.i_axi_wstrb(S_AXI_WSTRB),
//
.i_axi_bvalid(S_AXI_BVALID),
.i_axi_bready(S_AXI_BREADY),
.i_axi_bresp(S_AXI_BRESP),
//
.i_axi_arvalid(S_AXI_ARVALID),
.i_axi_arready(S_AXI_ARREADY),
.i_axi_araddr(S_AXI_ARADDR),
.i_axi_arprot(S_AXI_ARPROT),
//
.i_axi_rvalid(S_AXI_RVALID),
.i_axi_rready(S_AXI_RREADY),
.i_axi_rdata(S_AXI_RDATA),
.i_axi_rresp(S_AXI_RRESP),
//
.f_axi_rd_outstanding(faxil_rd_outstanding),
.f_axi_wr_outstanding(faxil_wr_outstanding),
.f_axi_awr_outstanding(faxil_awr_outstanding)
// }}}
);
always @(*) begin
assert (faxil_wr_outstanding == (S_AXI_BVALID ? 1 : 0));
assert (faxil_awr_outstanding == faxil_wr_outstanding);
assert (faxil_rd_outstanding == (S_AXI_RVALID ? 1 : 0));
end
endmodule
| 6.738562 |
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