code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sub_ksa_16b (
A16,
B16,
R16,
COUT_16
);
input [15:0] A16;
input [15:0] B16;
output COUT_16;
output [15:0] R16;
wire [15:0] A16;
wire [15:0] B16;
wire COUT_16;
wire [15:0] R16;
wire [15:0] B16neg;
notgate #(
.DATA_WIDTH(16)
) notgate_inst0 (
.A(B16),
.Y(B16neg)
);
ksa_top_16b ksa_top_16b_inst0 (
.c0(1'b1),
.i_a(A16),
.i_b(B16neg),
.o_s(R16),
.o_carry(COUT_16)
);
endmodule
| 7.004282 |
module sub_mod (
input wire clk,
input wire [23:0] a,
input wire [23:0] b,
output wire [23:0] out
);
reg [24:0] a_sub_b;
always @(posedge clk) a_sub_b <= a - b;
assign out = a_sub_b[23:0] + (a_sub_b[24] ? 24'd12587009 : 23'd0);
endmodule
| 7.09534 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//1-bit full adder
module fa (input wire i0, i1, cin, output wire sum, cout);
wire t0, t1, t2;
xor _i0 (sum,i0, i1, cin );
and _i1 (t0,i0, i1);
and _i2 (t1,i1, cin);
and _i3 (t2,cin, i0);
or _i4 (cout,t0, t1, t2);
endmodule
| 7.088073 |
module Adder (
a,
b,
sum
);
input [31:0] a, b;
output [31:0] sum;
wire cout;
wire [31:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[2],
q[2]
);
fa fa4 (
a[3],
b[3],
q[2],
sum[3],
q[3]
);
fa fa5 (
a[4],
b[4],
q[3],
sum[4],
q[4]
);
fa fa6 (
a[5],
b[5],
q[4],
sum[5],
q[5]
);
fa fa7 (
a[6],
b[6],
q[5],
sum[6],
q[6]
);
fa fa8 (
a[7],
b[7],
q[6],
sum[7],
q[7]
);
fa fa9 (
a[8],
b[8],
q[7],
sum[8],
q[8]
);
fa fa10 (
a[9],
b[9],
q[8],
sum[9],
q[9]
);
fa fa11 (
a[10],
b[10],
q[9],
sum[10],
q[10]
);
fa fa12 (
a[11],
b[11],
q[10],
sum[11],
q[11]
);
fa fa13 (
a[12],
b[12],
q[11],
sum[12],
q[12]
);
fa fa14 (
a[13],
b[13],
q[12],
sum[13],
q[13]
);
fa fa15 (
a[14],
b[14],
q[13],
sum[14],
q[14]
);
fa fa16 (
a[15],
b[15],
q[14],
sum[15],
q[15]
);
fa fa17 (
a[16],
b[16],
q[15],
sum[16],
q[16]
);
fa fa18 (
a[17],
b[17],
q[16],
sum[17],
q[17]
);
fa fa19 (
a[18],
b[18],
q[17],
sum[18],
q[18]
);
fa fa20 (
a[19],
b[19],
q[18],
sum[19],
q[19]
);
fa fa21 (
a[20],
b[20],
q[19],
sum[20],
q[20]
);
fa fa22 (
a[21],
b[21],
q[20],
sum[21],
q[21]
);
fa fa23 (
a[22],
b[22],
q[21],
sum[22],
q[22]
);
fa fa24 (
a[23],
b[23],
q[22],
sum[23],
q[23]
);
fa fa25 (
a[24],
b[24],
q[23],
sum[24],
q[24]
);
fa fa26 (
a[25],
b[25],
q[24],
sum[25],
q[25]
);
fa fa27 (
a[26],
b[26],
q[25],
sum[26],
q[26]
);
fa fa28 (
a[27],
b[27],
q[26],
sum[27],
q[27]
);
fa fa29 (
a[28],
b[28],
q[27],
sum[28],
q[28]
);
fa fa30 (
a[29],
b[29],
q[28],
sum[29],
q[29]
);
fa fa31 (
a[30],
b[30],
q[29],
sum[30],
q[30]
);
fa fa32 (
a[31],
b[31],
q[30],
sum[31],
cout
);
endmodule
| 6.808429 |
module sub_mon #(
parameter WIDTH = 32
) (
input clk,
input reset,
input [WIDTH-1:0] i_a,
input [WIDTH-1:0] i_b,
input [WIDTH-1:0] i_dut_o,
output reg [WIDTH-1:0] o_mon_o,
output reg [WIDTH-1:0] o_dtm_o
);
// adder logic
always @(posedge clk)
// introduce 25% error rate
if (i_a[0] && i_b[0])
o_mon_o <= i_b;
else o_mon_o <= i_a + i_b;
always @(posedge clk) o_dtm_o <= i_dut_o;
endmodule
| 6.945325 |
module SUB_n_bit (
c_out,
SUB_out,
R2,
R3
);
parameter word_size = 32; // the default size of this n bit subtractor
input [word_size-1:0] R2, R3;
output [word_size-1:0] SUB_out;
output c_out;
wire [word_size-1:0] c_inner, not_R3;
NOT_n_bit #(word_size) NOTN (
not_R3,
R3
);
// the 2's complement of R3 is added to R2
// the carry-in is hardwired to 1 in order to add 1 to not_R3, the 1's complement of R3
// the c_out of the ith 1-bit full adder is the c_in of the (i+1)th full adder
ADD_n_bit #(word_size) ADDER (
c_out,
SUB_out,
R2,
not_R3,
1'b1
);
endmodule
| 7.334721 |
module SUB_RAMZ #(
parameter RAMADDR_W = 6,
parameter RAMDATA_W = 12
) (
input wire [RAMDATA_W - 1:0] d,
input wire [RAMADDR_W - 1:0] waddr,
input wire [RAMADDR_W - 1:0] raddr,
input wire we,
input wire clk,
output wire [RAMDATA_W - 1:0] q
);
//type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
// STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
//signal mem : mem_type;
localparam MEM_SIZE = 2 ** RAMADDR_W;
reg [RAMDATA_W-1:0] mem[0:MEM_SIZE-1];
reg [RAMADDR_W-1:0] read_addr;
//-----------------------------------------------------------------------------
//q_sg:
//-----------------------------------------------------------------------------
// q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
assign q = mem[read_addr];
//-----------------------------------------------------------------------------
//read_proc: -- register read address
//-----------------------------------------------------------------------------
always @(posedge clk) begin
read_addr <= raddr;
end
//-----------------------------------------------------------------------------
//write_proc: --write access
//-----------------------------------------------------------------------------
always @(posedge clk) begin
if (we == 1'b1) begin
//mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
mem[waddr] <= d;
end
end
endmodule
| 6.553331 |
module sub_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "S";
1: label = "U";
2: label = "B";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
endcase
endmodule
| 6.706154 |
module pool_add2 (
input clock,
input reset,
input [`POOL_OUT_BITWIDTH:0] operand_a,
input [`POOL_OUT_BITWIDTH:0] operand_b,
output reg [`POOL_OUT_BITWIDTH:0] sum
);
`ifdef POOL_RESET
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) sum <= `POOL_OUT_BITWIDTH'd0;
else sum <= operand_a + operand_b;
end // always
`else
always @(posedge clock) begin
sum <= operand_a + operand_b;
end // always
`endif
endmodule
| 6.890651 |
module sub_t (
input [5:0] a_e,
output [5:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 7.30096 |
module sub_UserTimeScaleBox (
MASTER_CLK,
MASTER_RST,
VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD
);
//==================================================================//
// DEFINITIONS //
//==================================================================//
parameter P_UPleft = 10'h99;
parameter P_UPright = 10'h9D;
parameter P_UPbot = 10'h1E8;
parameter P_UPtop = 10'h1EE;
parameter P_DNleft = 10'h9F;
parameter P_DNright = 10'hA3;
parameter P_DNbot = 10'h1E8;
parameter P_DNtop = 10'h1EE;
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input MASTER_CLK; // global master clock
input MASTER_RST; // global master reset
input [9:0] XCOORD, YCOORD; // X and Y coordinates of the current mouse
// position. See the documentation for details
input BUTTON_RISE; // Trigger has risen
input BUTTON_FALL; // Trigger has fallen
output [3:0] VALUE_OUT; //
//----------------------//
// NODES //
//----------------------//
wire MASTER_CLK, MASTER_RST;
wire [9:0] XCOORD, YCOORD;
wire BUTTON_RISE, BUTTON_FALL;
reg [3:0] VALUE_OUT;
//==================================================================//
// T E S T I N G //
//==================================================================//
// NOTHING TO TEST
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
wire in_range_up, in_range_dn;
assign in_range_up = (((YCOORD >= P_UPbot) && (YCOORD <= P_UPtop)) && ((XCOORD >= P_UPleft && XCOORD <= P_UPright)));
assign in_range_dn = (((YCOORD >= P_DNbot) && (YCOORD <= P_DNtop)) && ((XCOORD >= P_DNleft && XCOORD <= P_DNright)));
always @(posedge MASTER_CLK or posedge MASTER_RST) begin
if (MASTER_RST) VALUE_OUT <= 4'b0;
else if (BUTTON_RISE && in_range_up) VALUE_OUT <= VALUE_OUT + 1;
else if (BUTTON_RISE && in_range_dn) VALUE_OUT <= VALUE_OUT - 1;
else VALUE_OUT <= VALUE_OUT;
end
endmodule
| 7.987097 |
module sub_UserTriggerStyleBox (
MASTER_CLK,
MASTER_RST,
VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD
);
//==================================================================//
// DEFINITIONS //
//==================================================================//
parameter P_RISEleft = 10'h39;
parameter P_RISEright = 10'h3D;
parameter P_RISEbot = 10'h1DF;
parameter P_RISEtop = 10'h1E5;
parameter P_FALLleft = 10'h3F;
parameter P_FALLright = 10'h43;
parameter P_FALLbot = 10'h1DF;
parameter P_FALLtop = 10'h1E5;
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input MASTER_CLK; // global master clock
input MASTER_RST; // global master reset
input [9:0] XCOORD, YCOORD; // X and Y coordinates of the current mouse
// position. See the documentation for details
input BUTTON_RISE; // Trigger has risen
input BUTTON_FALL; // Trigger has fallen
output [1:0] VALUE_OUT; //
//----------------------//
// NODES //
//----------------------//
wire MASTER_CLK, MASTER_RST;
wire [9:0] XCOORD, YCOORD;
wire BUTTON_RISE, BUTTON_FALL;
reg [1:0] VALUE_OUT;
//==================================================================//
// T E S T I N G //
//==================================================================//
// NOTHING TO TEST
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
wire in_range_rise, in_range_fall;
assign in_range_rise = (((YCOORD >= P_RISEbot) && (YCOORD <= P_RISEtop)) && ((XCOORD >= P_RISEleft && XCOORD <= P_RISEright)));
assign in_range_fall = (((YCOORD >= P_FALLbot) && (YCOORD <= P_FALLtop)) && ((XCOORD >= P_FALLleft && XCOORD <= P_FALLright)));
always @(posedge MASTER_CLK or posedge MASTER_RST) begin
if (MASTER_RST) VALUE_OUT <= 2'b00;
else if (BUTTON_RISE && in_range_rise) VALUE_OUT <= 2'b00;
else if (BUTTON_RISE && in_range_fall) VALUE_OUT <= 2'b01;
else VALUE_OUT <= VALUE_OUT;
end
endmodule
| 7.632384 |
module sub_UserLines (
MASTER_CLK,
MASTER_RST,
LINE_VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD,
RESET_VALUE,
LEFT,
RGHT,
BOT,
TOP,
SETXnY
);
//==================================================================//
// DEFINITIONS //
//==================================================================//
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input MASTER_CLK; // global master clock
input MASTER_RST; // global master reset
input XCOORD, YCOORD; // X and Y coordinates of the current mouse
// position. See the documentation for details
input LEFT, RGHT; // Left and Right limits for 'InRange'
input TOP, BOT; // Top and Bottom limits for 'InRange'
input SETXnY; // Upon trigger, either set the 'Value' to the
// X or Y coord.
input BUTTON_RISE; // Trigger has risen
input BUTTON_FALL; // Trigger has fallen
output [9:0] LINE_VALUE_OUT; // a 10 bit register to store the X or Y value
input [9:0] RESET_VALUE; // Reset value
//----------------------//
// NODES //
//----------------------//
wire MASTER_CLK, MASTER_RST;
wire [9:0] XCOORD, YCOORD, RESET_VALUE;
wire [9:0] LEFT, RGHT, TOP, BOT;
wire SETXnY;
wire BUTTON_RISE, BUTTON_FALL;
reg [9:0] LINE_VALUE_OUT;
//==================================================================//
// T E S T I N G //
//==================================================================//
// NOTHING TO TEST
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
wire in_range;
reg drag;
assign in_range = (((YCOORD >= BOT) && (YCOORD <= TOP)) && ((XCOORD >= LEFT && XCOORD <= RGHT)));
// the 'DRAG' state machine
always @(posedge MASTER_CLK or posedge MASTER_RST) begin
if (MASTER_RST) drag <= 1'b0;
else if (BUTTON_RISE && in_range) drag <= 1'b1;
else if (BUTTON_FALL) drag <= 1'b0;
else drag <= drag;
end
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Until this is figured out, it is bad to have the lines at 'zero'
(due to the comparison for 'in range')
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
always @(posedge MASTER_CLK or posedge MASTER_RST) begin
if (MASTER_RST) LINE_VALUE_OUT <= RESET_VALUE;
else if (drag && SETXnY) LINE_VALUE_OUT <= XCOORD;
else if (drag && !SETXnY && (YCOORD <= 10'd400)) LINE_VALUE_OUT <= YCOORD;
else LINE_VALUE_OUT <= LINE_VALUE_OUT;
end
endmodule
| 7.060856 |
module sequential_unsigned_comparator (
input a,
input b,
input rst,
input clk,
input op,
output reg L,
output reg E,
output reg G
);
reg [1:0] present_state, next_state;
localparam s0 = 2'b00; // equal state
localparam s1 = 2'b01; // greater than state
localparam s2 = 2'b10; // less than state
always @(posedge clk) begin
if (rst) begin // reset state
present_state <= s0;
end else begin
present_state <= next_state;
end
end
// next state logic
always @(*) begin
if (present_state == s0 && a^b) begin // state change can only take place when from equal state
next_state = (a ? s1 : s2); // if a and b not the same go to greater if a=1 and b=0 else go to less than
end else begin
next_state = present_state; // otherwise continue to stay in the present state
end
end
// store output in L, E, G
always @(*) begin
if (op == 1'b0) begin //output control logic
L = 1'b0;
E = 1'b0;
G = 1'b0;
end else if (next_state == s0) begin //output logic for equal state
L = 1'b0;
E = 1'b1;
G = 1'b0;
end else if (next_state == s1) begin //output logic for greater than state
L = 1'b0;
E = 1'b0;
G = 1'b1;
end else begin //output logic for less than state
L = 1'b1;
E = 1'b0;
G = 1'b0;
end
end
endmodule
| 7.35408 |
module AND (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.053445 |
module OR (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 7.086775 |
module NOR (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 7.611112 |
module XOR (
a,
b,
y
);
input a, b;
output y;
assign y = (a ^ b);
endmodule
| 7.915029 |
module NOT (
a,
b
);
output b;
input a;
assign b = !a;
endmodule
| 7.483426 |
module comp (
input [6:0] A,
input [6:0] B,
output reg Q
);
wire [6:0] temp1;
wire [6:0] temp2;
//XOR x1(.A(A[7]),.B(B[7]),.Q(temp));
assign temp1[0] = A[0];
assign temp1[1] = A[1];
assign temp1[2] = A[2];
assign temp1[3] = A[3];
assign temp1[4] = A[4];
assign temp1[5] = A[5];
assign temp1[6] = A[6];
assign temp2[0] = B[0];
assign temp2[1] = B[1];
assign temp2[2] = B[2];
assign temp2[3] = B[3];
assign temp2[4] = B[4];
assign temp2[5] = B[5];
assign temp2[6] = B[6];
always @(A or B) begin
if (temp1 > temp2) begin
Q = 1;
end else begin
Q = 0;
end
end
endmodule
| 6.601597 |
module mux21 (
a,
b,
s,
o
);
input a;
input b;
input s;
output o;
wire not_sel;
wire temp1, temp2;
wire Data_out_temp;
not n1 (not_sel, s);
and and_1 (temp1, a, not_sel);
and and_2 (temp2, b, s);
or or_1 (Data_out_temp, temp1, temp2);
assign o = Data_out_temp;
endmodule
| 7.579812 |
module Pnode (
input sign_LLR_C,
input sign_LLR_D,
input comp1,
input frozen1,
input frozen2,
output u2i_1,
output u2i
);
wire h, i, j, k, l, m, n, comp, o, p, q, r, s, t, u;
XOR X1 (
.a(sign_LLR_C),
.b(sign_LLR_D),
.y(j)
);
NOT N1 (
.a(frozen1),
.b(k)
);
AND A1 (
.a(k),
.b(j),
.y(u2i_1)
);
NOT N2 (
.a(frozen2),
.b(l)
);
NOT N3 (
.a(comp1),
.b(m)
);
AND A2 (
.a(comp1),
.b(l),
.y(n)
);
AND A3 (
.a(l),
.b(m),
.y(o)
);
AND A4 (
.a(sign_LLR_D),
.b(n),
.y(p)
);
AND A5 (
.a(frozen1),
.b(sign_LLR_C),
.y(q)
);
AND A6 (
.a(sign_LLR_D),
.b(k),
.y(r)
);
AND A7 (
.a(n),
.b(q),
.y(s)
);
AND A8 (
.a(r),
.b(n),
.y(t)
);
OR O1 (
.a(s),
.b(t),
.y(u)
);
OR O2 (
.a(u),
.b(p),
.y(u2i)
);
endmodule
| 7.741602 |
module SUCORE (
input [31:0] instr,
output [4:0] A1,
output reg [2:0] rsTuse,
output [4:0] A2,
output reg [2:0] rtTuse,
output [4:0] A3,
output reg [2:0] E_Tnew,
output reg [2:0] M_Tnew
);
wire [6:0] order;
BasicCORE basiccore (
.instr(instr),
.order(order),
.A1(A1),
.A2(A2),
.A3(A3)
);
//rsTuse
always @(*)
case (order)
`addu, `subu, `ori, `lw, `sw: rsTuse = 1;
`jr, `beq: rsTuse = 0;
default: rsTuse = 0;
endcase
//rtTuse
always @(*)
case (order)
`sw: rtTuse = 2;
`addu, `subu: rtTuse = 1;
`beq: rtTuse = 0;
default: rtTuse = 0;
endcase
//Tnew
always @(*)
case (order)
`lw: E_Tnew = 2;
`addu, `subu, `ori: E_Tnew = 1;
`lui, `jal: E_Tnew = 0;
default: E_Tnew = 0;
endcase
always @(*)
case (order)
`lw: M_Tnew = 1;
`addu, `subu, `ori, `lui, `jal: M_Tnew = 0;
default: M_Tnew = 0;
endcase
endmodule
| 7.213999 |
module sudoku (
clk,
rst,
puzzle_io,
puzzle_oe,
next_puzzle,
solution,
give_up,
extra_out
);
input clk, rst;
inout [9*9*4-1:0] puzzle_io;
tri [9*9*4-1:0] puzzle_io;
output puzzle_oe;
output next_puzzle;
output solution, give_up;
output [9*9*4-1:0] extra_out;
// PLL signals
wire clk_150;
wire pll_locked;
// Input fifo signals
wire ififo_rdreq;
wire ififo_rdempty;
wire ififo_rdfull;
wire ififo_wrfull;
wire [9*9*4-1:0] ififo_dataout;
// Output fifo signals
wire ofifo_wrreq;
wire ofifo_rdempty;
wire ofifo_wrfull;
wire [9*9*4-1:0] ofifo_datain;
wire [9*9*4-1:0] ofifo_dataout;
// Sudoku control signals
reg sudoku_go;
wire solution_wire;
pll spll (
.areset(rst),
.inclk0(clk),
.c0(clk_150),
.locked(pll_locked)
);
fifo ififo (
.aclr(rst),
.data(puzzle_io),
.wrclk(clk),
.wrreq(next_puzzle),
.rdclk(clk_150),
.rdreq(ififo_rdreq),
.q(ififo_dataout),
.rdempty(ififo_rdempty),
.rdfull(ififo_rdfull),
.wrempty(),
.wrfull(ififo_wrfull)
);
fifo ofifo (
.aclr(rst),
.data(ofifo_datain),
.wrclk(clk_150),
.wrreq(ofifo_wrreq),
.rdclk(clk),
.rdreq(puzzle_oe),
.q(ofifo_dataout),
.rdempty(ofifo_rdempty),
.rdfull(),
.wrempty(),
.wrfull(ofifo_wrfull)
);
// sudoku_go is a latch that goes to 1 when the input fifo is filled for the
// first time and the pll has locked.
always @(posedge clk_150 or posedge rst) begin
if (rst) sudoku_go <= 0;
else if (pll_locked && ififo_rdfull) sudoku_go <= 1'b1;
end
sudoku_core sc (
.clk(clk_150),
.rst(rst),
.go(sudoku_go),
.puzzle_avail(!ififo_rdempty && !ofifo_wrfull),
.puzzle_in(ififo_dataout),
.puzzle_out(ofifo_datain),
.read_puzzle(ififo_rdreq),
.done_puzzle(ofifo_wrreq)
);
assign extra_out = ofifo_datain ^ ififo_rdreq ^ ofifo_wrreq;
sudoku_solution ss (
.puzzle_ans(ofifo_dataout),
.solution (solution_wire)
);
defparam ss.WIDTH = 4;
// Generate output signals
assign puzzle_io = (puzzle_oe ? ofifo_dataout : 324'bz);
assign puzzle_oe = !ofifo_rdempty;
assign next_puzzle = !puzzle_oe && !ififo_wrfull && pll_locked;
assign solution = puzzle_oe && solution_wire;
assign give_up = puzzle_oe && !solution_wire;
endmodule
| 7.075497 |
module sudoku_accelerator (
input wire wb_clk_i,
input wire wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [ 3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output [31:0] wb_dat_o,
output uart_enabled,
output ser_tx,
input ser_rx,
output interrupt_sudoku,
output interrupt_uart,
output interrupt // for testbench use only
);
wire sudoku_addr = (wb_adr_i & 32'hFFF00000) == 32'h30000000;
wire uart_addr = (wb_adr_i & 32'hFFF00000) == 32'h30800000;
wire sudoku_ack;
wire [31:0] sudoku_dat;
wire uart_ack;
wire [31:0] uart_dat;
assign wb_ack_o = sudoku_addr ? sudoku_ack : uart_addr ? uart_ack : 0;
assign wb_dat_o = sudoku_addr ? sudoku_dat : uart_addr ? uart_dat : 0;
assign interrupt = interrupt_sudoku | interrupt_uart;
sudoku_puzzle_wb sudoku (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_we_i (sudoku_addr & wb_we_i),
.wb_cyc_i(sudoku_addr & wb_cyc_i),
.wb_stb_i(sudoku_addr & wb_stb_i),
.wb_ack_o(sudoku_ack),
.wb_dat_o(sudoku_dat),
.interrupt(interrupt_sudoku)
);
simpleuart_fifo_wb #(
.BASE_ADR(32'h30800000)
) uart (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_we_i (uart_addr & wb_we_i),
.wb_cyc_i(uart_addr & wb_cyc_i),
.wb_stb_i(uart_addr & wb_stb_i),
.wb_ack_o(uart_ack),
.wb_dat_o(uart_dat),
.uart_enabled(uart_enabled),
.ser_tx(ser_tx),
.ser_rx(ser_rx),
.interrupt(interrupt_uart)
);
endmodule
| 6.637512 |
module sudoku_accelerator_wrapper (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire wb_clk_i,
input wire wb_rst_i,
input wire la_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [ 3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output [31:0] wb_dat_o,
// Logic Analyzer Signals
//input [127:0] la_data_in,
//output [127:0] la_data_out,
//input [127:0] la_oenb,
output ser_tx,
output ser_tx_oeb,
input ser_rx,
// IOs
//input [`MPRJ_IO_PADS-1:0] io_in,
//output [`MPRJ_IO_PADS-1:0] io_out,
//output [`MPRJ_IO_PADS-1:0] io_oeb,
// User maskable interrupt signals
output [2:0] user_irq
);
wire uart_en;
assign ser_tx_oeb = ~uart_en;
//assign io_oeb[15] = ~uart_en;
//assign la_data_out[0] = uart_en;
wire int_sudoku;
wire int_uart;
assign user_irq[0] = int_sudoku;
assign user_irq[1] = int_uart;
//assign la_data_out[32] = int_sudoku;
//assign la_data_out[33] = int_uart;
//assign la_oenb[33:32] = 0;
// expose some la pins to GPIO, both ways
//assign io_out[25:17] = la_data_in[104:96];
//assign io_oeb[25:17] = 0;
//assign la_data_out[113:105] = io_in[34:28];
sudoku_accelerator accel (
.wb_clk_i(wb_clk_i),
.wb_rst_i(la_rst),
// MGMT SoC Wishbone Slave
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_we_i (wb_we_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_dat_o(wb_dat_o),
.uart_enabled(uart_en),
.ser_tx(ser_tx),
.ser_rx(ser_rx),
.interrupt_sudoku(int_sudoku),
.interrupt_uart (int_uart)
);
endmodule
| 6.637512 |
module sudoku_ans (
puzzle_mask_bin,
puzzle_ans_bin
);
input [9*9*9-1:0] puzzle_mask_bin;
output [9*9*9-1:0] puzzle_ans_bin;
wire [9*9*9*9-1:0] partial_x;
wire [9*9*9*9-1:0] partial_y;
wire [9*9*9*9-1:0] partial_z;
wire [9*9*9*9-1:0] partial_sq;
sudoku_partials sp (
.in(puzzle_mask_bin),
.match_bit(1'b1),
.partial_x(partial_x),
.partial_y(partial_y),
.partial_z(partial_z),
.partial_sq(partial_sq)
);
genvar i;
generate
for (i = 0; i < 9 * 9 * 9; i = i + 1) begin : ANS
assign puzzle_ans_bin[i] = (&partial_x[i*9+9-1:i*9]) |
(&partial_y[i*9+9-1:i*9]) |
(&partial_z[i*9+9-1:i*9]) |
(&partial_sq[i*9+9-1:i*9]);
end
endgenerate
endmodule
| 7.336424 |
module bin2hex (
input [9-1:0] bin,
output [ 3:0] out
);
integer hex;
always @(bin) begin
case (bin)
9'b000000001: hex = 4'h1;
9'b000000010: hex = 4'h2;
9'b000000100: hex = 4'h3;
9'b000001000: hex = 4'h4;
9'b000010000: hex = 4'h5;
9'b000100000: hex = 4'h6;
9'b001000000: hex = 4'h7;
9'b010000000: hex = 4'h8;
9'b100000000: hex = 4'h9;
default: hex = 4'h0;
endcase
end
assign out = hex[3:0];
endmodule
| 7.54151 |
module sudoku_hex2bin (
hex,
bin
);
input [9*9*4-1:0] hex;
output [9*9*9-1:0] bin;
generate
genvar i;
for (i = 0; i < 9 * 9; i = i + 1) begin : HEX2BIN
hex2bin h2b (
.hex(hex[i*4+4-1:i*4]),
.out(bin[i*9+9-1:i*9])
);
end
endgenerate
endmodule
| 6.603685 |
module hex2bin (
input [ 3:0] hex,
output [9-1:0] out
);
integer bin;
always @(hex) begin
case (hex)
4'h 1 : bin = 9'b 000000001;
4'h 2 : bin = 9'b 000000010;
4'h 3 : bin = 9'b 000000100;
4'h 4 : bin = 9'b 000001000;
4'h 5 : bin = 9'b 000010000;
4'h 6 : bin = 9'b 000100000;
4'h 7 : bin = 9'b 001000000;
4'h 8 : bin = 9'b 010000000;
4'h 9 : bin = 9'b 100000000;
default : bin = 9'b 000000000;
endcase
end
assign out = bin[9-1:0];
endmodule
| 7.029544 |
module sudoku_mask (
puzzle_reg_bin,
puzzle_mask_bin
);
input [9*9*9-1:0] puzzle_reg_bin;
output [9*9*9-1:0] puzzle_mask_bin;
wire [9*9*9*9-1:0] partial_x;
wire [9*9*9*9-1:0] partial_y;
wire [9*9*9*9-1:0] partial_z;
wire [9*9*9*9-1:0] partial_sq;
sudoku_partials sp (
.in(puzzle_reg_bin),
.match_bit(1'b0),
.partial_x(partial_x),
.partial_y(partial_y),
.partial_z(partial_z),
.partial_sq(partial_sq)
);
genvar i;
generate
for (i = 0; i < 9 * 9 * 9; i = i + 1) begin : ANS
assign puzzle_mask_bin[i] = (|partial_x[i*9+9-1:i*9]) |
(|partial_y[i*9+9-1:i*9]) |
(|partial_z[i*9+9-1:i*9]) |
(|partial_sq[i*9+9-1:i*9]);
end
endgenerate
endmodule
| 7.070515 |
module spw_to_one_hot (
input [3:0] value,
output [8:0] result,
input invert
);
assign result = invert ? ~tmp : tmp;
reg [8:0] tmp;
always @(value) begin
case (value)
1: tmp = 9'b000000001;
2: tmp = 9'b000000010;
3: tmp = 9'b000000100;
4: tmp = 9'b000001000;
5: tmp = 9'b000010000;
6: tmp = 9'b000100000;
7: tmp = 9'b001000000;
8: tmp = 9'b010000000;
9: tmp = 9'b100000000;
default: tmp = 0;
endcase
end
endmodule
| 6.506008 |
module sudoku_solution (
puzzle_ans,
solution
);
parameter WIDTH = 4; //default to puzzle_ans_hex width of 4
//width of 9 for puzzle_ans_bin.
input [9*9*WIDTH-1:0] puzzle_ans;
output solution;
wire [9*9-1:0] non_zero;
assign solution = &non_zero;
genvar i;
generate
for (i = 0; i < 9 * 9; i = i + 1) begin : NZ
assign non_zero[i] = |puzzle_ans[i*WIDTH+WIDTH-1:i*WIDTH];
end
endgenerate
endmodule
| 7.46617 |
module suhddpsram1024x16_rq (
input wire [15:0] data_a, // ram_input.datain_a
input wire [15:0] data_b, // .datain_b
input wire [ 9:0] address_a, // .address_a
input wire [ 9:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [15:0] q_a, // ram_output.dataout_a
output wire [15:0] q_b // .dataout_b
);
suhddpsram1024x16_rq_ram_2port_191_tdpa2va ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 6.853809 |
module suhddpsram1024x16_rq_ram_2port_191_tdpa2va (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
);
//.sclr (1'b0));
defparam
altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 1024,
altera_syncram_component.numwords_b = 1024,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 10,
altera_syncram_component.widthad_b = 10,
altera_syncram_component.width_a = 16,
altera_syncram_component.width_b = 16,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 6.853809 |
module suhddpsram1024x8_rq (
input wire [7:0] data_a, // ram_input.datain_a
input wire [7:0] data_b, // .datain_b
input wire [9:0] address_a, // .address_a
input wire [9:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [7:0] q_a, // ram_output.dataout_a
output wire [7:0] q_b // .dataout_b
);
suhddpsram1024x8_rq_ram_2port_191_go2l72y ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 6.853809 |
module suhddpsram1024x8_rq_ram_2port_191_go2l72y (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 1024, altera_syncram_component.numwords_b = 1024,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 10,
altera_syncram_component.widthad_b = 10,
altera_syncram_component.width_a = 8,
altera_syncram_component.width_b = 8,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 6.853809 |
module suhddpsram16384x9_s (
input wire [ 8:0] data_a, // ram_input.datain_a
input wire [ 8:0] data_b, // .datain_b
input wire [13:0] address_a, // .address_a
input wire [13:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [ 8:0] q_a, // ram_output.dataout_a
output wire [ 8:0] q_b // .dataout_b
);
suhddpsram16384x9_s_ram_2port_191_emqbfsi ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.411889 |
module suhddpsram16384x9_s_ram_2port_191_emqbfsi (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [8:0] data_a;
input [8:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [8:0] q_a;
output [8:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] sub_wire1;
wire [8:0] q_a = sub_wire0[8:0];
wire [8:0] q_b = sub_wire1[8:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 16384, altera_syncram_component.numwords_b = 16384,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 14,
altera_syncram_component.widthad_b = 14,
altera_syncram_component.width_a = 9,
altera_syncram_component.width_b = 9,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.411889 |
module suhddpsram32x57 (
input wire [56:0] data_a, // ram_input.datain_a
input wire [56:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [56:0] q_a, // ram_output.dataout_a
output wire [56:0] q_b // .dataout_b
);
suhddpsram32x57_ram_2port_191_5cp27sq ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.080523 |
module suhddpsram32x57_ram_2port_191_5cp27sq (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [56:0] data_a;
input [56:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [56:0] q_a;
output [56:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [56:0] sub_wire0;
wire [56:0] sub_wire1;
wire [56:0] q_a = sub_wire0[56:0];
wire [56:0] q_b = sub_wire1[56:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 32, altera_syncram_component.numwords_b = 32,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 5,
altera_syncram_component.widthad_b = 5,
altera_syncram_component.width_a = 57,
altera_syncram_component.width_b = 57,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.080523 |
module suhddpsram512x4_rq (
input wire [3:0] data_a, // ram_input.datain_a
input wire [3:0] data_b, // .datain_b
input wire [8:0] address_a, // .address_a
input wire [8:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [3:0] q_a, // ram_output.dataout_a
output wire [3:0] q_b // .dataout_b
);
suhddpsram512x4_rq_ram_2port_191_gytxvfq ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 6.75558 |
module suhddpsram512x4_rq_ram_2port_191_gytxvfq (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [3:0] data_a;
input [3:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [3:0] q_a;
output [3:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] q_a = sub_wire0[3:0];
wire [3:0] q_b = sub_wire1[3:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 512, altera_syncram_component.numwords_b = 512,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 9,
altera_syncram_component.widthad_b = 9,
altera_syncram_component.width_a = 4,
altera_syncram_component.width_b = 4,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 6.75558 |
module suhddpsram65536x134_s (
input wire [133:0] data_a, // ram_input.datain_a
input wire [133:0] data_b, // .datain_b
input wire [ 15:0] address_a, // .address_a
input wire [ 15:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [133:0] q_a, // ram_output.dataout_a
output wire [133:0] q_b // .dataout_b
);
suhddpsram65536x134_s_ram_2port_191_pu2i72y ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.116652 |
module suhddpsram65536x134_s_ram_2port_191_pu2i72y (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [15:0] address_a;
input [15:0] address_b;
input clock;
input [133:0] data_a;
input [133:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [133:0] q_a;
output [133:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [133:0] sub_wire1;
wire [133:0] q_a = sub_wire0[133:0];
wire [133:0] q_b = sub_wire1[133:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 65536, altera_syncram_component.numwords_b = 65536,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 16,
altera_syncram_component.widthad_b = 16,
altera_syncram_component.width_a = 134,
altera_syncram_component.width_b = 134,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.116652 |
module testsum (
output f,
input a,
b,
c
);
// sum S1(f, a, b, c); //this is known as structural modeling
assign f = (a & b & c); //known as behavioral modeling.
endmodule
| 7.006159 |
module sum512 (
input [512-1:0] in,
output [9:0] out
);
wire [8:0] outr, outl;
sum256 l (
in[512-1:256],
outl
);
sum256 r (
in[256-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.8124 |
module sum256 (
input [256-1:0] in,
output [8:0] out
);
wire [7:0] outr, outl;
sum128 l (
in[256-1:128],
outl
);
sum128 r (
in[128-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.811341 |
module sum128 (
input [128-1:0] in,
output [7:0] out
);
wire [6:0] outr, outl;
sum64 l (
in[128-1:64],
outl
);
sum64 r (
in[64-1:0],
outr
);
assign out = outr + outl;
endmodule
| 7.151327 |
module sum64 (
input [64-1:0] in,
output [6:0] out
);
wire [5:0] outr, outl;
sum32 l (
in[64-1:32],
outl
);
sum32 r (
in[32-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.986065 |
module sum32 (
input [32-1:0] in,
output [5:0] out
);
wire [4:0] outr, outl;
sum16 l (
in[32-1:16],
outl
);
sum16 r (
in[16-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.761252 |
module sum8 (
input [8-1:0] in,
output [ 3:0] out
);
wire [2:0] outr, outl;
sum4 l (
in[8-1:4],
outl
);
sum4 r (
in[4-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.64273 |
module sum4 (
input [4-1:0] in,
output [ 2:0] out
);
wire [1:0] outr, outl;
sum2 l (
in[4-1:2],
outl
);
sum2 r (
in[2-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.907832 |
module sum2 (
input [2-1:0] in,
output [ 1:0] out
);
assign out = in[1] + in[0];
endmodule
| 7.219206 |
module sum4 (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
);
wire C1, C2, C3;
fa full_adder0 (
S[0],
C1,
A[0],
B[0],
c_in
);
fa full_adder1 (
S[1],
C2,
A[1],
B[1],
C1
);
fa full_adder2 (
S[2],
C3,
A[2],
B[2],
C2
);
fa full_adder3 (
S[3],
c_out,
A[3],
B[3],
C3
);
endmodule
| 7.206358 |
module sum4b (
init,
xi,
yi,
co,
sal
);
input init;
input [3 : 0] xi;
input [3 : 0] yi;
output co;
output [3 : 0] sal;
wire [4:0] st;
assign sal = st[3:0];
assign Cout = st[4];
assign st = xi + yi;
endmodule
| 7.504786 |
module sum4b_TB;
// Inputs
reg [3:0] xi;
reg [3:0] yi;
// Outputs
wire co;
wire [3:0] zi;
// Instantiate the Unit Under Test (UUT)
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
// Initialize Inputs
xi = 0;
for (yi = 0; yi < 16; yi = yi + 1) begin
if (yi == 0) xi = xi + 1;
#5 $display("el valor de %d + %d = %d", xi, yi, zi);
end
end
initial begin : TEST_CASE
$dumpfile("sum4b_TB.vcd");
$dumpvars(-1, uut);
#(1280) $finish;
end
endmodule
| 7.47404 |
module sum4 (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
);
assign {c_out, S} = A + B + c_in;
endmodule
| 7.206358 |
module sum4_sin_fa (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
); // Se hace uso del operador de concatenación:
assign {c_out, S} = a + b + c_in; // El c_out y el S deben ir en ese orden ya que es el bit más significativo de la operación
endmodule
| 6.538546 |
module sum4_tb;
//declaracion de se�ales
reg [3:0] test_A, test_B;
reg test_c_in;
wire [3:0] test_S;
wire test_c_out;
//instancia del modulo a testear
sum4 sum (
test_S,
test_c_out,
test_A,
test_B,
test_c_in
);
initial begin
$monitor("tiempo=%0d A=%b B=%b cin=%b S=%b cout=%b", $time, test_A, test_B, test_c_in, test_S,
test_c_out);
$dumpfile("sum4_tb.vcd");
$dumpvars;
//Algunos valores de prueba
test_c_in = 1'b1;
test_A = 4'b0000;
test_B = 4'b0000;
#20;
test_c_in = 1'b0;
test_A = 4'b1111;
test_B = 4'b0001;
#20;
test_c_in = 1'b1;
test_A = 4'b1111;
test_B = 4'b1111;
#20;
test_c_in = 1'b1;
test_A = 4'b0000;
test_B = 4'b1111;
#20;
test_c_in = 1'b0;
test_A = 4'b0101;
test_B = 4'b1010;
#20;
//fin simulacion
$finish;
end
endmodule
| 7.744039 |
module Suma #(
parameter N = 25
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire signed [N-1:0] A,
B,
output reg signed [N-1:0] SUMA
);
//Declaracion de senales utilizadas dentro del modulo
reg signed [N-1:0] SUMAAux;
reg [N-1:0] maximo;
reg [N-1:0] minimo;
reg [N:0] M, m;
always @* //Lista sensitiva, responde ante cualquier cambio de senal
begin
SUMAAux = A + B; //Se realiza la suma de los operandos A y B
M = (2 ** (N - 1) - 1);
maximo = M[N-1:0]; // Se determina el valor maximo que se puede representar con N bits
m = (2 ** (N - 1) + 1);
minimo = m[N-1:0]; // Se determina el valor minimo que se puede representar con N bits
end
always @* //Lista sensitiva, responde ante cualquier cambio de senal
begin
if (A[N-1] == 0 && B[N-1] == 0 && SUMAAux[N-1] == 1)//Condiciones para overflow revisando los signos de los operandos y el resultado
begin //Si el operando A y B son positivos y la suma da negativa, implica un overflow
SUMA = maximo;
end
else if (A[N-1] == 1 && B[N-1] == 1 && SUMAAux[N-1] == 0)//Condiciones para underflow revisando los signos de los operandos y el resultado
begin //Si el operando A y B son negativos y la suma positiva, implica underflow
SUMA = minimo;
end else SUMA = SUMAAux; //Resultado de suma que no presenta ni overflow ni underflow
end
endmodule
| 7.636157 |
module Sumador1bit (
input a,
b,
c_in,
output sum,
c_out
);
wire s1, s2, c1;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
xor (c_out, s2, c1);
endmodule
| 6.871432 |
module sumador3bits(
input [0:2] in,
output reg [0:1] out,
);
always @(in)
begin
case(in)
3'b000: out = 2'b00;
3'b001: out = 2'b01;
3'b010: out = 2'b01;
3'b011: out = 2'b10;
3'b100: out = 2'b01;
3'b101: out = 2'b10;
3'b110: out = 2'b10;
3'b111: out = 2'b11;
default: out = 2'b00;
endcase
end
endmodule
| 7.566174 |
module Sum4bit (
output wire [3:0] S,
output wire Co,
input wire [3:0] e1,
input wire [3:0] e2,
input wire Ci
);
wire fa0c, fa1c, fa2c;
FA fa0 (
S[0],
fa0c,
e1[0],
e2[0],
Ci
);
FA fa1 (
S[1],
fa1c,
e1[1],
e2[1],
fa0c
);
FA fa2 (
S[2],
fa2c,
e1[2],
e2[2],
fa1c
);
FA fa3 (
S[3],
Co,
e1[3],
e2[3],
fa2c
);
endmodule
| 7.43216 |
module SumadorBranch (
input [63:0] inputPC,
input [63:0] inputSEU,
output [63:0] Nextinst
);
assign Nextinst = inputPC + inputSEU;
endmodule
| 6.523469 |
module sumadorCarryLook_4bits (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire [3:0] P, G;
wire [4:1] C;
wire temp;
medio_sumador ms0 (
A[0],
B[0],
P[0],
G[0]
);
medio_sumador ms1 (
A[1],
B[1],
P[1],
G[1]
);
medio_sumador ms2 (
A[2],
B[2],
P[2],
G[2]
);
medio_sumador ms3 (
A[3],
B[3],
P[3],
G[3]
);
carryLook_4bits CL1 (
P,
G,
C,
Ci
);
xor (S[3], P[3], C[3]);
xor (S[2], P[2], C[2]);
xor (S[1], P[1], C[1]);
xor (S[0], P[0], Ci);
assign Co = C[4];
endmodule
| 6.778141 |
module FA (
output wire S,
output wire Co,
input wire e1,
input wire e2,
input wire ci
);
wire HA1S, HA1C, HA2C;
HA ha1 (
HA1S,
HA1C,
e1,
e2
);
HA ha2 (
S,
HA2C,
ci,
HA1S
);
or (Co, HA1C, HA2C);
endmodule
| 7.885402 |
module SumadorNbits #(
parameter N = 8
) (
input [N-1:0] a,
input [N-1:0] b,
input c_in,
output [N-1:0] sum,
output c_out
);
wire [0:N-1] carry;
genvar i;
Sumador1bit sumador0 (
.a(a[0]),
.b(b[0]),
.c_in(1'b0),
.sum(sum[0]),
.c_out(carry[0])
);
generate
for (i = 0; i < N; i = i + 1) begin : add_bit
Sumador1bit sumador_medio (
.a(a[i+1]),
.b(b[i+1]),
.c_in(carry[i]),
.sum(sum[i+1]),
.c_out(carry[i+1])
);
end
endgenerate
Sumador1bit sumadorN (
.a(a[N-1]),
.b(b[N-1]),
.c_in(carry[N-2]),
.sum(sum[N-1]),
.c_out(c_out)
);
endmodule
| 6.915605 |
module Sumador_12b (
input [11:0] A,
B, // Operandos
output [11:0] SUM // Suma
);
assign SUM = A + B;
endmodule
| 6.768738 |
module sumador_4bits (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire C1, C2, C3;
sumador_completo sc0 (
A[0],
B[0],
Ci,
S[0],
C1
);
sumador_completo sc1 (
A[1],
B[1],
Ci,
S[1],
C2
);
sumador_completo sc2 (
A[2],
B[2],
Ci,
S[2],
C3
);
sumador_completo sc3 (
A[3],
B[3],
Ci,
S[3],
Co
);
endmodule
| 6.746912 |
module Sumador_8b (
input [7:0] A,
B, // Operandos
output [7:0] SUM // Suma
);
assign SUM = A + B;
endmodule
| 6.769222 |
module sumador_completo (
input A,
input B,
input Cin,
output S,
output Cout
);
wire P, G, H;
medio_sumador ms1 (
A,
B,
P,
G
);
medio_sumador ms2 (
P,
Cin,
S,
H
);
or (Cout, G, H);
endmodule
| 7.210508 |
module SUM8_LOGICO (
a,
b,
ci,
s,
co
);
parameter PwrC = 0;
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] a, b, s;
wire [3:0] a_L, a_H, b_L, b_H, s_L, s_H;
wire ci, co;
SUM4_logico #(PwrC) sum4_L (
a_L,
b_L,
ci,
s_L,
co_L
);
SUM4_logico #(PwrC) sum4_H (
a_H,
b_H,
co_L,
s_H,
co
);
assign a_L[3:0] = a[3:0];
assign b_L[3:0] = b[3:0];
assign a_H[3:0] = a[7:4];
assign b_H[3:0] = b[7:4];
assign s[3:0] = s_L[3:0];
assign s[7:4] = s_H[3:0];
endmodule
| 6.549223 |
module SUM8_LOOKAHEAD (
a,
b,
ci,
s,
co
);
parameter PwrC = 0;
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] a, b, s;
wire [3:0] a_L, a_H, b_L, b_H, s_L, s_H;
wire ci, co;
SUM4_lookahead #(PwrC) sum4look_L (
a_L,
b_L,
ci,
s_L,
co_L
);
SUM4_lookahead #(PwrC) sum4look_H (
a_H,
b_H,
co_L,
s_H,
co
);
assign a_L[3:0] = a[3:0];
assign b_L[3:0] = b[3:0];
assign a_H[3:0] = a[7:4];
assign b_H[3:0] = b[7:4];
assign s[3:0] = s_L[3:0];
assign s[7:4] = s_H[3:0];
endmodule
| 7.193794 |
module Sumador_pipe (
input clk,
input reset,
input [3:0] idx,
input [3:0] dataA,
input [3:0] dataB,
output reg [3:0] idx_dd,
output [3:0] sum30_dd
);
reg [3:0] idx_d;
always @(posedge clk) begin
if (!reset) begin
idx_d <= 0;
idx_dd <= 0;
end else begin
idx_d <= idx + 1;
idx_dd <= idx_d + 1;
end
end
Sumador s1 (
.clk(clk),
.reset(reset),
.dataA(dataA),
.dataB(dataB),
.sum30_dd(sum30_dd)
);
endmodule
| 6.586775 |
module sumador_completo ( // all 1 bit
// input wire a,
// input wire b,
// input wire ci,
// output reg s,
// output reg co
// );
// parameter
// PwrC = 0;
// // For outputs connections
// wire w0,w1,w2,w3,w4,w5;
// /////////
// /// w0
// ////////
// xor2_p xorw0(
// // Outputs
// .a ( w0),
// //Inputs
// .c (a),
// .b (b)
// );
// /////////
// /// w1
// ////////
// and2_p andw1(
// // Outputs
// .a ( w1),
// //Inputs
// .c (ci),
// .b (a)
// );
// /////////
// /// w2
// ////////
// and2_p andw2(
// // Outputs
// .a ( w2),
// //Inputs
// .c (ci),
// .b (b)
// );
// /////////
// /// w3
// ////////
// and2_p andw3(
// // Outputs
// .a ( w3),
// //Inputs
// .c (b),
// .b (a)
// );
// /////////
// /// w4
// ////////
// xor2_p xorw4(
// // Outputs
// .a ( w4),
// //Inputs
// .c (w0),
// .b (ci)
// );
// /////////
// /// w5
// ////////
// or3_p orw5(
// // Outputs
// .a ( w5),
// //Inputs
// .b (w1),
// .c (w2),
// .d (w3)
// );
// always@(*) begin
// s = w4;
// co = w5;
// end
// endmodule
| 7.210508 |
module sumador_completo ( // all 1 bit
input wire a,
input wire b,
input wire ci,
output reg s,
output reg co
);
parameter PwrC = 0;
// For outputs connections
wire w1, w2, w3, w4, w5;
/////////
/// w4
////////
xor3_p xorw4 (
// Outputs
.a(w4),
//Inputs
.b(a),
.c(b),
.d(ci)
);
/////////
/// w1
////////
and2_p andw1 (
// Outputs
.a(w1),
//Inputs
.c(ci),
.b(a)
);
/////////
/// w2
////////
and2_p andw2 (
// Outputs
.a(w2),
//Inputs
.c(ci),
.b(b)
);
/////////
/// w3
////////
and2_p andw3 (
// Outputs
.a(w3),
//Inputs
.c(b),
.b(a)
);
/////////
/// w5
////////
or3_p orw5 (
// Outputs
.a(w5),
//Inputs
.b(w1),
.c(w2),
.d(w3)
);
always @(*) begin
s = w4;
co = w5;
end
endmodule
| 7.210508 |
module SUM_RIZADO (
input wire [7:0] a, // 8 bits
input wire [7:0] b, // 8 bits
input wire ci,
output reg [7:0] s, // 8 bits
output reg co
);
parameter PwrC = 0;
// for 8 bits
wire [7:0] ws_8bit;
wire [7:0] carry_8bit;
sumador_completo sumador_completo0 (
//outputs
.s (ws_8bit[0]),
.co(carry_8bit[0]),
//inputs
.a (a[0]),
.b (b[0]),
.ci(ci)
);
sumador_completo sumador_completo1 (
//outputs
.s (ws_8bit[1]),
.co(carry_8bit[1]),
//inputs
.a (a[1]),
.b (b[1]),
.ci(carry_8bit[0])
);
sumador_completo sumador_completo2 (
//outputs
.s (ws_8bit[2]),
.co(carry_8bit[2]),
//inputs
.a (a[2]),
.b (b[2]),
.ci(carry_8bit[1])
);
sumador_completo sumador_completo3 (
//outputs
.s (ws_8bit[3]),
.co(carry_8bit[3]),
//inputs
.a (a[3]),
.b (b[3]),
.ci(carry_8bit[2])
);
sumador_completo sumador_completo4 (
//outputs
.s (ws_8bit[4]),
.co(carry_8bit[4]),
//inputs
.a (a[4]),
.b (b[4]),
.ci(carry_8bit[3])
);
sumador_completo sumador_completo5 (
//outputs
.s (ws_8bit[5]),
.co(carry_8bit[5]),
//inputs
.a (a[5]),
.b (b[5]),
.ci(carry_8bit[4])
);
sumador_completo sumador_completo6 (
//outputs
.s (ws_8bit[6]),
.co(carry_8bit[6]),
//inputs
.a (a[6]),
.b (b[6]),
.ci(carry_8bit[5])
);
sumador_completo sumador_completo7 (
//outputs
.s (ws_8bit[7]),
.co(carry_8bit[7]),
//inputs
.a (a[7]),
.b (b[7]),
.ci(carry_8bit[6])
);
always @(*) begin
s = ws_8bit[7:0];
co = carry_8bit[7:0];
end
endmodule
| 7.198251 |
module top (
input wire FPGA_SYSCLK_P,
input wire FPGA_SYSCLK_N,
inout wire I2C_FPGA_SCL,
inout wire I2C_FPGA_SDA,
output wire [7:0] LED,
// Ethernet
input wire SFP_CLK_P,
input wire SFP_CLK_N,
output wire SFP_REC_CLK_P,
output wire SFP_REC_CLK_N,
input wire SFP_CLK_ALARM_B,
// Ethernet (ETH0)
input wire ETH0_TX_P,
input wire ETH0_TX_N,
output wire ETH0_RX_P,
output wire ETH0_RX_N,
input wire ETH0_TX_FAULT,
input wire ETH0_RX_LOS,
output wire ETH0_TX_DISABLE,
// Ethernet (ETH1)
input wire ETH1_TX_P,
input wire ETH1_TX_N,
output wire ETH1_RX_P,
output wire ETH1_RX_N,
input wire ETH1_TX_FAULT,
input wire ETH1_RX_LOS,
output wire ETH1_TX_DISABLE
// SRAM Interface
//input [0:0] qdriip_cq_p,
//input [0:0] qdriip_cq_n,
//input [35:0] qdriip_q,
//inout wire [0:0] qdriip_k_p,
//inout wire [0:0] qdriip_k_n,
//output wire [35:0] qdriip_d,
//output wire [18:0] qdriip_sa,
//output wire qdriip_w_n,
//output wire qdriip_r_n,
//output wire [3:0] qdriip_bw_n,
//output wire qdriip_dll_off_n
);
/*
* Core Clocking
*/
wire clk200;
IBUFDS IBUFDS_clk200 (
.I (FPGA_SYSCLK_P),
.IB(FPGA_SYSCLK_N),
.O (clk200)
);
wire clk100;
reg clock_divide = 1'b0;
always @(posedge clk200) clock_divide <= ~clock_divide;
BUFG buffer_clk100 (
.I(clock_divide),
.O(clk100)
);
/*
* Core Reset
* ***FPGA specified logic
*/
reg [13:0] cold_counter = 14'd0;
reg sys_rst;
always @(posedge clk200)
if (cold_counter != 14'h3fff) begin
cold_counter <= cold_counter + 14'd1;
sys_rst <= 1'b1;
end else sys_rst <= 1'b0;
/*
* Ethernet Top Instance
*/
eth_top u_eth_top (
.clk100 (clk100),
.clk200 (clk200),
.sys_rst(sys_rst),
.debug (LED),
/* XGMII */
.SFP_CLK_P (SFP_CLK_P),
.SFP_CLK_N (SFP_CLK_N),
.SFP_REC_CLK_P(SFP_REC_CLK_P),
.SFP_REC_CLK_N(SFP_REC_CLK_N),
.ETH0_TX_P(ETH0_TX_P),
.ETH0_TX_N(ETH0_TX_N),
.ETH0_RX_P(ETH0_RX_P),
.ETH0_RX_N(ETH0_RX_N),
.I2C_FPGA_SCL(I2C_FPGA_SCL),
.I2C_FPGA_SDA(I2C_FPGA_SDA),
.SFP_CLK_ALARM_B(SFP_CLK_ALARM_B),
.ETH0_TX_FAULT (ETH0_TX_FAULT),
.ETH0_RX_LOS (ETH0_RX_LOS),
.ETH0_TX_DISABLE(ETH0_TX_DISABLE),
.ETH1_TX_P (ETH1_TX_P),
.ETH1_TX_N (ETH1_TX_N),
.ETH1_RX_P (ETH1_RX_P),
.ETH1_RX_N (ETH1_RX_N),
.ETH1_TX_FAULT (ETH1_TX_FAULT),
.ETH1_RX_LOS (ETH1_RX_LOS),
.ETH1_TX_DISABLE(ETH1_TX_DISABLE)
);
endmodule
| 7.233807 |
module sume_to_sdnet (
// clk/rst input
input axi_clk,
input axi_resetn,
// input SUME axi signals
input SUME_axi_tvalid,
input SUME_axi_tlast,
input SUME_axi_tready,
// output SDNet signals
output SDNet_tuple_VALID,
output SDNet_axi_TLAST
);
// registers to hold the value of tvalid and tlast on the previous clock cycle
reg SUME_axi_tvalid_prev;
reg SUME_axi_tlast_prev;
reg SUME_axi_tready_prev;
// register to remember if tvalid has already gone high for this packet
reg tvalid_has_gone_high;
always @(posedge axi_clk) begin
if (~axi_resetn) begin
SUME_axi_tvalid_prev <= 1'b0;
SUME_axi_tlast_prev <= 1'b0;
SUME_axi_tready_prev <= 1'b0;
tvalid_has_gone_high <= 1'b0;
end else begin
SUME_axi_tvalid_prev <= SUME_axi_tvalid;
SUME_axi_tlast_prev <= SUME_axi_tlast;
SUME_axi_tready_prev <= SUME_axi_tready;
if (SUME_axi_tlast) tvalid_has_gone_high <= 1'b0;
else if (SUME_axi_tvalid) tvalid_has_gone_high <= 1'b1;
else tvalid_has_gone_high <= tvalid_has_gone_high;
end
end
// tuple_in_VALID should be high whenever (tvalid goes high AND
// it is the first time tvalid has gone high since tlast went high)
// OR (tvalid stays high AND tlast was high on the previous cycle AND
// tready was high on the previous cycle).
// This lines up with the first word of each packet
assign SDNet_tuple_VALID = (SUME_axi_tvalid & ~SUME_axi_tvalid_prev & ~tvalid_has_gone_high) | (SUME_axi_tvalid & SUME_axi_tvalid_prev & SUME_axi_tlast_prev & SUME_axi_tready_prev);
// the SDNet_TLAST signal should only go high when TVALID is high
assign SDNet_axi_TLAST = SUME_axi_tvalid & SUME_axi_tlast;
endmodule
| 7.079365 |
module Summation_Logic #(
parameter DATA_WIDTH = 32,
parameter TOTAL_PARTICLE_NUM = 20000,
parameter PARTICLE_GLOBAL_ID_WIDTH = 15, // log(TOTAL_PARTICLE_NUM)/log(2)
parameter NUM_CELL_X = 5,
parameter NUM_CELL_Y = 5,
parameter NUM_CELL_Z = 5,
parameter NUM_TOTAL_CELL = NUM_CELL_X * NUM_CELL_Y * NUM_CELL_Z
) (
input clk,
input rst,
input [NUM_TOTAL_CELL-1:0] cell_done_from_pipeline,
output [3*DATA_WIDTH-1:0] force_summed_to_motion_update,
output [NUM_TOTAL_CELL-1:0] read_request_to_force_cache,
output [PARTICLE_GLOBAL_ID_WIDTH-1:0] read_address_to_force_cache,
output [NUM_TOTAL_CELL-1:0] read_cell_id,
input [3*DATA_WIDTH-1:0] force_from_force_cache_lr,
input [3*DATA_WIDTH-1:0] force_from_force_cache_sr,
input [3*DATA_WIDTH-1:0] force_from_force_cache_bf,
input force_valid_from_force_cache,
input [PARTICLE_GLOBAL_ID_WIDTH-1:0] gid_in,
output [PARTICLE_GLOBAL_ID_WIDTH-1:0] gid_out,
output valid_sum
);
wire [NUM_TOTAL_CELL-1:0] ready_to_sum;
wire [15:0] cell_id_to_sum;
Scoreboard #(
.NUM_TOTAL_CELL(NUM_TOTAL_CELL)
) Scoreboard (
.clk(clk),
.rst(rst),
.cell_done(cell_done_from_pipeline),
.ready_to_sum(ready_to_sum)
);
wire valid_out_to_FSM;
wire resume;
Ready_Buffer #(
.NUM_TOTAL_CELL(NUM_TOTAL_CELL)
) Ready_Buffer (
.clk(clk),
.rst(rst),
.ready_to_sum(ready_to_sum),
.cell_id_to_sum(cell_id_to_sum),
.valid_out(valid_out_to_FSM),
.resume(resume)
);
wire valid_out_to_adder;
FSM_Access #(
.DATA_WIDTH(DATA_WIDTH),
.TOTAL_PARTICLE_NUM(TOTAL_PARTICLE_NUM),
.PARTICLE_GLOBAL_ID_WIDTH(PARTICLE_GLOBAL_ID_WIDTH),
.NUM_CELL_X(NUM_CELL_X),
.NUM_CELL_Y(NUM_CELL_Y),
.NUM_CELL_Z(NUM_CELL_Z),
.NUM_TOTAL_CELL(NUM_TOTAL_CELL)
) FSM (
.clk(clk),
.rst(rst),
.cell_id_to_sum(cell_id_to_sum),
.cell_id_access_valid(valid_out_to_FSM),
.number_of_partical(force_from_force_cache_bf),
.access_address(read_address_to_force_cache),
.cell_id(read_cell_id),
.rd_en(read_request_to_force_cache),
.resume(resume),
.valid_in(force_valid_from_force_cache),
.valid_out_to_adder(valid_out_to_adder)
);
reg valid_out_to_adder_d;
reg valid_out_to_adder_2d;
always @(posedge clk) begin
if (rst) begin
valid_out_to_adder_d <= 0;
valid_out_to_adder_2d <= 0;
end else begin
valid_out_to_adder_d <= valid_out_to_adder;
valid_out_to_adder_2d <= valid_out_to_adder_d;
end
end
// Force Summation
Force_Summation_Unit #(
.DATA_WIDTH(DATA_WIDTH)
) Force_Summation_Unit (
.clk(clk),
.rst(rst),
.valid_in(valid_out_to_adder_2d),
.force_to_sum_from_lr(force_from_force_cache_lr),
.force_to_sum_from_sr(force_from_force_cache_sr),
.force_to_sum_from_bf(force_from_force_cache_bf),
.out_Sumed_Force(force_summed_to_motion_update),
.valid_out(valid_sum)
);
assign gid_out = gid_in;
endmodule
| 7.086003 |
module code_ram #(
parameter integer ADDR_SIZE = 18,
parameter integer WORD_SIZE = 18,
parameter integer MEM_SIZE = 1024
) (
input wire [(ADDR_SIZE-1):0] addr,
output wire [(WORD_SIZE-1):0] dout
);
reg [(WORD_SIZE-1):0] mem[(MEM_SIZE-1):0];
initial $readmemh("vmem.txt", mem);
assign dout = mem[addr];
endmodule
| 7.26833 |
module processor_tb;
parameter MEM_SIZE = 64;
parameter WORD_SIZE = 18;
reg clock;
logic [(WORD_SIZE-1):0] program_memory_addr;
wire [(WORD_SIZE-1):0] program_memory_out_data;
logic processor_reset;
logic wait_continue_execution;
logic wait_for_continue;
integer i;
wire data_we;
wire [(WORD_SIZE-1):0] data_addr;
wire [(WORD_SIZE-1):0] data_din;
wire [(WORD_SIZE-1):0] data_dout;
initial begin
clock = 0;
forever clock = #1 ~clock;
end
initial begin
$dumpfile("wout.vcd");
$dumpvars(0, program_memory_addr);
$dumpvars(0, program_memory_out_data);
$dumpvars(0, processor18);
$dumpvars(0, processor18.registers.regs[0]);
$dumpvars(0, processor18.registers.regs[1]);
$dumpvars(0, processor18.registers.regs[2]);
$dumpvars(0, processor18.registers.regs[3]);
$dumpvars(0, processor18.registers.regs[7]);
$dumpvars(0, data_memory.mem[0]);
$dumpvars(0, data_memory.mem[1]);
$dumpvars(0, data_memory.mem[2]);
$dumpvars(0, data_memory.mem[3]);
$dumpvars(0, data_memory.mem[4]);
$dumpvars(0, data_memory.mem[5]);
$dumpvars(0, data_memory.mem[6]);
$dumpvars(0, data_memory.mem[7]);
wait_continue_execution = 0;
processor_reset = 1;
#2 processor_reset = 0;
//$monitor("in_data=%x, out_data=%x addr=%x", in_data, out_data, program_memory_addr);
//$monitor("mem[0]=%x", program_memory.mem[0]);
wait (wait_for_continue)
//#2 wait_continue_execution = 1;
//#2 wait_continue_execution = 0;
#2
$finish;
end
ram #(
.ADDR_SIZE(WORD_SIZE),
.WORD_SIZE(WORD_SIZE),
.MEM_SIZE (MEM_SIZE)
) data_memory (
.clock(clock),
.we(data_we),
.addr(data_addr),
.din(data_din),
.dout(data_dout)
);
code_ram #(
.ADDR_SIZE(WORD_SIZE),
.WORD_SIZE(WORD_SIZE),
.MEM_SIZE (MEM_SIZE)
) program_memory (
.addr(program_memory_addr),
.dout(program_memory_out_data)
);
processor #(
.ADDR_SIZE(WORD_SIZE),
.WORD_SIZE(WORD_SIZE)
) processor18 (
.clock(clock),
.reset(processor_reset),
//Интерфейс для чтения программы
.code_addr(program_memory_addr),
.code_word(program_memory_out_data),
//Интерфейс для чтения данных
.memory_write_enable(data_we),
.memory_addr(data_addr),
.memory_in(data_din),
.memory_out(data_dout),
.wait_for_continue(wait_for_continue),
.wait_continue_execution(wait_continue_execution)
);
endmodule
| 6.711119 |
module mullxx_tb;
parameter WORD_SIZE = 18;
logic [WORD_SIZE-1:0] r0;
logic [WORD_SIZE-1:0] r1;
logic [WORD_SIZE-1:0] res;
logic [4:0] shift;
logic signx;
logic signy;
logic signed [WORD_SIZE-1:0] r0s;
logic signed [WORD_SIZE-1:0] r1s;
logic signed [WORD_SIZE-1:0] ress;
assign r0s = $signed(r0);
assign r1s = $signed(r1);
assign ress = $signed(res);
initial begin
$monitor("r0=%d, r1=%d, res=%d sx=%d sy=%d shift=%d, r0s=%d, r1s=%d, ress=%d", r0, r1, res,
signx, signy, shift, r0s, r1s, ress);
r0 = 0;
r1 = 0;
shift = 0;
signx = 0;
signy = 0;
#2 r0 = 2;
r1 = 2;
shift = 0;
signx = 0;
signy = 0;
#2 if (res != 4) $error("Fail");
#2 r0 = 2;
r1 = 3;
shift = 0;
signx = 0;
signy = 0;
#2 if (res != 6) $error("Fail");
#2 r0 = -2;
r1 = 3;
shift = 0;
signx = 1;
signy = 0;
#2 if ($signed(res) != -6) $error("Fail");
#2 r0 = 2;
r1 = -1;
shift = 0;
signx = 1;
signy = 1;
#2 if ($signed(res) != -2) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 0;
signx = 0;
signy = 0;
#2 if (res != 'h3ffff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 1;
signx = 0;
signy = 0;
#2 if (res != 'h1ffff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 2;
signx = 0;
signy = 0;
#2 if (res != 'hffff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 3;
signx = 0;
signy = 0;
#2 if (res != 'h7fff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 4;
signx = 0;
signy = 0;
#2 if (res != 'h3fff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 5;
signx = 0;
signy = 0;
#2 if (res != 'h1fff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 6;
signx = 0;
signy = 0;
#2 if (res != 'hfff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 1;
shift = 7;
signx = 0;
signy = 0;
#2 if (res != 'h7ff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 37;
shift = 7;
signx = 0;
signy = 0;
#2 if (res != 'h127ff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 37;
shift = 8;
signx = 0;
signy = 0;
#2 if (res != 'h93ff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 37;
shift = 9;
signx = 0;
signy = 0;
#2 if (res != 'h49ff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 37;
shift = 10;
signx = 0;
signy = 0;
#2 if (res != 'h24ff) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 10;
signx = 0;
signy = 0;
#2 if (res != 'h3ffe5) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 11;
signx = 0;
signy = 0;
#2 if (res != 'h1fff2) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 12;
signx = 0;
signy = 0;
#2 if (res != 'hfff9) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 13;
signx = 0;
signy = 0;
#2 if (res != 'h7ffc) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 14;
signx = 0;
signy = 0;
#2 if (res != 'h3ffe) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 15;
signx = 0;
signy = 0;
#2 if (res != 'h1fff) $error("Fail");
#2 r0 = 4727;
r1 = 56782;
shift = 16;
signx = 0;
signy = 0;
#2 if (res != 'hfff) $error("Fail");
#2 r0 = 47273;
r1 = 56782;
shift = 16;
signx = 0;
signy = 0;
#2 if (res != 'h9ffe) $error("Fail");
#2 r0 = 47273;
r1 = 56782;
shift = 17;
signx = 0;
signy = 0;
#2 if (res != 'h4fff) $error("Fail");
#2 r0 = 47273;
r1 = 56782;
shift = 18;
signx = 0;
signy = 0;
#2 if (res != 'h27ff) $error("Fail");
#2 r0 = 'h3ffff;
r1 = 'h3ffff;
shift = 18;
signx = 0;
signy = 0;
#2 if (res != 'h3fffe) $error("Fail");
#2 r0 = -1;
r1 = 1;
shift = 0;
signx = 1;
signy = 1;
#2 if ($signed(res) != -1) $error("Fail");
#2 r0 = -1;
r1 = -1;
shift = 0;
signx = 1;
signy = 1;
#2 if ($signed(res) != 1) $error("Fail");
#2 r0 = -'hffff;
r1 = 'hffff;
shift = 16;
signx = 1;
signy = 1;
#2 if ($signed(res) != -18'hffff) $error("Fail");
end
mulxx #(
.WORD_SIZE(WORD_SIZE)
) mulxx0 (
.r0(r0),
.r1(r1),
.shift(shift), //0..17
.signx(signx),
.signy(signy),
.res(res) //result
);
endmodule
| 6.838219 |
module takes in an array of numbers and sums them. guaranteed ceil(log2(BLOCKLENGTH)) registers.
Executes the sum with recursive calls.
PipelineSummer is a wrapper of Summer with ready and valid logic.
*/
`include "2dArrayMacros.v"
`include "PipelineTrain.v"
/* recursive sum tree with pipeline logic*/
module PipelineSummer #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 1,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output signed [DATA_WIDTH-1:0] sum
);
localparam NUM_REGISTERS = log2(BLOCKLENGTH) + 1; //register input
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #(.TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
reg [DATA_WIDTH*BLOCKLENGTH-1:0] data_in_reg;
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
data_in_reg <= 0;
end else if (1'b1 == enable) begin
data_in_reg <= data_in;
end
end
Summer #(.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sumMod(clk, reset, enable, data_in_reg, sum);
//constant function that calculates ceil(log2())
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1) begin
value = value>>1;
end
end
endfunction
endmodule
| 6.546226 |
module SummerRec #(
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output signed [DATA_WIDTH-1:0] sum
);
wire signed [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
localparam integer HALF_BLOCKLENGTH = BLOCKLENGTH / 2;
localparam integer HALF_BLOCKLENGTH_LESS_ONE = (BLOCKLENGTH - 1) / 2;
localparam REG_BLOCKLENGTH = (HALF_BLOCKLENGTH == HALF_BLOCKLENGTH_LESS_ONE) ? (HALF_BLOCKLENGTH + 1) : HALF_BLOCKLENGTH; //if true, means that input blocjklength is odd
wire signed [DATA_WIDTH-1:0] weirdAdd;
generate
if (HALF_BLOCKLENGTH == HALF_BLOCKLENGTH_LESS_ONE) begin //input blocklength odd
assign weirdAdd = in[BLOCKLENGTH-1];
end else begin
assign weirdAdd = in[BLOCKLENGTH-2] + in[BLOCKLENGTH-1];
end
endgenerate
reg signed [DATA_WIDTH-1:0] reg0[0:REG_BLOCKLENGTH-1];
integer i;
always @(posedge clk, posedge reset) begin
//fills all but last entry
for (i = 0; i < REG_BLOCKLENGTH - 1; i = i + 1) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= in[2*i] + in[2*i+1];
end
end
//fill last entry
if (1'b1 == reset) begin
reg0[REG_BLOCKLENGTH-1] <= 0;
end else if (1'b1 == enable) begin
reg0[REG_BLOCKLENGTH-1] <= weirdAdd;
end
end
wire [DATA_WIDTH*REG_BLOCKLENGTH-1:0] sumvals;
`PACK_ARRAY(DATA_WIDTH, REG_BLOCKLENGTH, reg0, sumvals)
Summer #(
.BLOCKLENGTH(REG_BLOCKLENGTH),
.DATA_WIDTH (DATA_WIDTH)
) sumMod (
clk,
reset,
enable,
sumvals,
sum
);
endmodule
| 6.815015 |
module sumofN(CLK,
RST_N,
in_put,
EN_in_put,
RDY_in_put,
EN_out_get,
out_get,
RDY_out_get,
configure_address,
configure_data,
EN_configure,
RDY_configure,
interrupt,
RDY_interrupt);
input CLK;
input RST_N;
// action method in_put
input [7 : 0] in_put;
input EN_in_put;
output RDY_in_put;
// actionvalue method out_get
input EN_out_get;
output [7 : 0] out_get;
output RDY_out_get;
// action method configure
input [7 : 0] configure_address;
input [7 : 0] configure_data;
input EN_configure;
output RDY_configure;
// value method interrupt
output interrupt;
output RDY_interrupt;
// signals for module outputs
wire [7 : 0] out_get;
wire RDY_configure, RDY_in_put, RDY_interrupt, RDY_out_get, interrupt;
// register count
reg [7 : 0] count;
wire [7 : 0] count$D_IN;
wire count$EN;
// register length
reg [7 : 0] length;
wire [7 : 0] length$D_IN;
wire length$EN;
// register start
reg start;
wire start$D_IN, start$EN;
// register sum
reg [7 : 0] sum;
wire [7 : 0] sum$D_IN;
wire sum$EN;
// rule scheduling signals
wire WILL_FIRE_RL_so5;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_count$write_1__VAL_3, MUX_sum$write_1__VAL_2;
wire MUX_count$write_1__SEL_1;
// remaining internal signals
wire [7 : 0] y__h346;
// action method in_put
assign RDY_in_put = 1'd1 ;
// actionvalue method out_get
assign out_get = sum ;
assign RDY_out_get = count == length && !WILL_FIRE_RL_so5 ;
// action method configure
assign RDY_configure = 1'd1 ;
// value method interrupt
assign interrupt = EN_in_put && !start ;
assign RDY_interrupt = 1'd1 ;
// rule RL_so5
assign WILL_FIRE_RL_so5 = start && count < length ;
// inputs to muxes for submodule ports
assign MUX_count$write_1__SEL_1 =
EN_configure && configure_address == 8'd1 ;
assign MUX_count$write_1__VAL_3 = count + 8'd1 ;
assign MUX_sum$write_1__VAL_2 = sum + y__h346 ;
// register count
assign count$D_IN =
(MUX_count$write_1__SEL_1 || EN_out_get) ?
8'd0 :
MUX_count$write_1__VAL_3 ;
assign count$EN =
WILL_FIRE_RL_so5 && EN_in_put ||
EN_configure && configure_address == 8'd1 ||
EN_out_get ;
// register length
assign length$D_IN = configure_data ;
assign length$EN = EN_configure && configure_address == 8'd0 ;
// register start
assign start$D_IN = MUX_count$write_1__SEL_1 ;
assign start$EN =
EN_configure && configure_address == 8'd1 || count == length ;
// register sum
assign sum$D_IN = MUX_count$write_1__SEL_1 ? 8'd0 : MUX_sum$write_1__VAL_2 ;
assign sum$EN =
WILL_FIRE_RL_so5 && EN_in_put ||
EN_configure && configure_address == 8'd1 ;
// remaining internal signals
assign y__h346 = EN_in_put ? in_put : 8'd0 ;
// handling of inlined registers
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
count <= `BSV_ASSIGNMENT_DELAY 8'd0;
length <= `BSV_ASSIGNMENT_DELAY 8'h0F;
start <= `BSV_ASSIGNMENT_DELAY 1'd0;
sum <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (length$EN) length <= `BSV_ASSIGNMENT_DELAY length$D_IN;
if (start$EN) start <= `BSV_ASSIGNMENT_DELAY start$D_IN;
if (sum$EN) sum <= `BSV_ASSIGNMENT_DELAY sum$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
count = 8'hAA;
length = 8'hAA;
start = 1'h0;
sum = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule
| 6.541892 |
module sumsub1 #(
parameter WIDTH = 8
) (
input wire signed [WIDTH-1:0] a, // primer operando
input wire signed [WIDTH-1:0] b, // segundo operando
input wire op, // operación (0-suma, 1-resta)
output reg signed [WIDTH-1:0] f, // salida
output reg ov // desbordamiento
);
/* Recordamos: f y ov se declaran como variables (tipo 'reg') porque
* van a usarse en un procedimiento 'always' */
always @* begin : sub
/* Definimos una variable local al bloque para realizar la
* suma con un bit adicional. La definición de varialbes
* locales es posible sólo si se nombra el bloque ('sub') en
* este caso */
reg signed [WIDTH:0] s;
/* Aquí, la construcción 'if' hubiera sido igual de efectiva
* que el 'case' pero, en general, cuando la decisión depende
* de una sola variable (en este caso 'op') 'case' resulta más
* claro, especialmente cuando el número de posibles valores
* de la variable es elevado */
case (op)
0: s = a + b;
default: s = a - b;
endcase
// Salida de desbordamiento
/* 's' contiene el valor correcto de la operación. La
* extensión del signo se realiza automáticamente ya que los
* tipos son 'signed'. El desbordamiento puede detectarse si
* comparamos el bit de signo del resultado correcto con el
* del resultado sin extensión (s[WIDTH-1:0]) */
if (s[WIDTH] != s[WIDTH-1]) ov = 1;
else ov = 0;
// Salida
f = s[WIDTH-1:0];
end
endmodule
| 7.422484 |
module sumsub2 #(
parameter WIDTH = 8
) (
input wire [WIDTH-1:0] a, // primer operando
input wire [WIDTH-1:0] b, // segundo operando
input wire op, // operación (0-suma, 1-resta)
output reg [WIDTH-1:0] f, // salida
output reg ov // desbordamiento
);
always @* begin : sub
/* Variable temporal para calcular el segundo operando */
reg [WIDTH-1:0] c;
/* Empleamos el operador condicional para calcular 'c', que
* es un sustituto muy compacto de 'if'. En caso de resta 'c'
* es el complemento a 1 (Ca1) de 'b' */
c = op == 0 ? b : ~b;
/* Calculamos el resultado. Si se trata de una resta, 'a' se
* sumará con el complemento a 2 (Ca2 = Ca1 + 1) de 'b'
* produciendo como resultado 'a - b' representado en Ca2. */
f = a + c + op;
// Salida de desbordamiento
/* Sólo se produce desbordamiento cuando se suman número del
* mismo signo, y sólo si el signo aparente del resultado
* difiere del de los operandos */
ov = ~a[WIDTH-1] & ~c[WIDTH-1] & f[WIDTH-1] | a[WIDTH-1] & c[WIDTH-1] & ~f[WIDTH-1];
end
endmodule
| 7.070679 |
module SumUnit (
input G,
input P,
input Pi,
input Cin,
output Cout,
output Sum
);
assign Cout = G | (P & Cin);
assign Sum = Pi ^ Cin;
endmodule
| 6.81255 |
module Sum_28 (
A,
B,
sum
);
input [27:0] A, B;
output [27:0] sum;
assign sum = A + B;
endmodule
| 7.150979 |
module sum_2N #(
parameter R = 8,
N = 3
) (
input clk,
rst,
input wire signed [R-1 : 0] in, // input vl
output reg signed [R+N-1:0] out, // sum val
output reg signed [R-1 : 0] mean, // mean val
output wire tick // output tick
);
//signal declaration
reg [N-1 : 0] cnt;
reg [N-1 : 0] cnt_next;
reg signed [R-1 : 0] mean_next;
reg signed [R+N-1:0] sum, sum_next, out_next;
wire state;
localparam // 2 posible states
summing = 1'd0, store = 1'd1;
// body
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}};
mean <= {R{1'b0}};
sum <= {R + N{1'b0}};
out <= {R + N{1'b0}};
end else begin
cnt <= cnt_next;
mean <= mean_next;
sum <= sum_next;
out <= out_next;
end
assign state = &cnt;
// next-state logic
always @* begin
if (state == 1'b0) begin
cnt_next = cnt + 1'b1;
mean_next = mean;
sum_next = $signed(sum) + $signed(in);
out_next = out;
end else begin
cnt_next = {N{1'b0}};
mean_next = $signed(sum[R+N-1:N]);
sum_next = $signed({{N{1'b0}}, in});
out_next = sum;
end
end
// output logic
assign tick = (cnt == {N{1'b0}});
endmodule
| 6.85532 |
module sum_2N2 #(
parameter R1 = 8,
R2 = 8,
N = 3
) (
input clk,
rst,
input wire signed [R1-1 : 0] in1, // input vl
output reg signed [R1+N-1:0] out1, // sum val
output reg signed [R1-1 : 0] mean1, // mean val
input wire signed [R2-1 : 0] in2, // input vl
output reg signed [R2+N-1:0] out2, // sum val
output reg signed [R2-1 : 0] mean2, // mean val
output wire tick // output tick
);
//signal declaration
reg [ N-1 : 0] cnt;
reg [ N-1 : 0] cnt_next;
reg signed [R1-1 : 0] mean1_next;
reg signed [R1+N-1:0] sum1, sum1_next, out1_next;
reg signed [R2-1 : 0] mean2_next;
reg signed [R2+N-1:0] sum2, sum2_next, out2_next;
wire state;
localparam // 2 posible states
summing = 1'd0, store = 1'd1;
// body
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}};
mean1 <= {R1{1'b0}};
sum1 <= {R1 + N{1'b0}};
out1 <= {R1 + N{1'b0}};
mean2 <= {R2{1'b0}};
sum2 <= {R2 + N{1'b0}};
out2 <= {R2 + N{1'b0}};
end else begin
cnt <= cnt_next;
mean1 <= mean1_next;
sum1 <= sum1_next;
out1 <= out1_next;
mean2 <= mean2_next;
sum2 <= sum2_next;
out2 <= out2_next;
end
assign state = &cnt;
// next-state logic
always @* begin
if (state == 1'b0) begin
cnt_next = cnt + 1'b1;
mean1_next = mean1;
sum1_next = $signed(sum1) + $signed(in1);
out1_next = out1;
mean2_next = mean2;
sum2_next = $signed(sum2) + $signed(in2);
out2_next = out2;
end else begin
cnt_next = {N{1'b0}};
mean1_next = $signed(sum1[R1+N-1:N]);
sum1_next = $signed({{N{1'b0}}, in1});
out1_next = sum1;
mean2_next = $signed(sum2[R2+N-1:N]);
sum2_next = $signed({{N{1'b0}}, in2});
out2_next = sum2;
end
end
// output logic
assign tick = (cnt == {N{1'b0}});
endmodule
| 7.259604 |
module Sum_51 (
A,
B,
sum
);
input [50:0] A, B;
output [50:0] sum;
assign sum = A + B;
endmodule
| 6.73343 |
module sum_and_max #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 10
)
//note: this module is not fully parametrized and must be rewritten for different LENGTH
(
input clk,
input reset_n,
input ready,
input [2*DATA_WIDTH*LENGTH-1:0] input_data,
input [DATA_WIDTH*LENGTH-1:0] biases,
output reg [LENGTH-1:0] maxi
);
reg [2*DATA_WIDTH*LENGTH-1:0] input_plus_bias;
reg [DATA_WIDTH*LENGTH-1:0] half_max;
reg [2*DATA_WIDTH*3-1:0] three_max;
reg [2*DATA_WIDTH-1:0] maximum;
reg [4:0] half_max_reg; //we need those registers to infer the right index of the result
reg [2:0] three_max_reg;
reg [1:0] i_var;
integer ii, ij, ik;
always @(posedge clk) begin
maxi = {LENGTH{1'b0}};
if (~reset_n) begin
input_plus_bias <= {2 * DATA_WIDTH * LENGTH{1'b0}};
half_max <= {DATA_WIDTH * LENGTH{1'b0}};
three_max <= {2 * DATA_WIDTH * 3{1'b0}};
maximum <= {2 * DATA_WIDTH{1'b0}};
half_max_reg <= 5'b00000;
three_max_reg <= 3'b000;
i_var <= 2'b11;
end else if (ready) begin
for (ii = 0; ii < LENGTH; ii = ii + 1) //sign-extended biases are added to sys array output
input_plus_bias[2*DATA_WIDTH*ii+:2*DATA_WIDTH] =
$signed(input_data[2*DATA_WIDTH*ii+:2*DATA_WIDTH]) +
{{DATA_WIDTH{biases[DATA_WIDTH*(ii+1)-1]}}, biases[DATA_WIDTH*ii+:DATA_WIDTH]};
for (ij = 0; ij < 5; ij = ij + 1) begin //get 5 maxes from pairs
if ($signed(
input_plus_bias[2*DATA_WIDTH*2*ij+:2*DATA_WIDTH]
) > $signed(
input_plus_bias[2*DATA_WIDTH*(2*ij+1)+:2*DATA_WIDTH]
)) begin
half_max [2*DATA_WIDTH*ij +: 2*DATA_WIDTH] = input_plus_bias[2*DATA_WIDTH*2*ij +: 2*DATA_WIDTH];
half_max_reg[ij] = 1'b0;
end else if ($signed(
input_plus_bias[2*DATA_WIDTH*2*ij+:2*DATA_WIDTH]
) <= $signed(
input_plus_bias[2*DATA_WIDTH*(2*ij+1)+:2*DATA_WIDTH]
)) begin
half_max [2*DATA_WIDTH*ij +: 2*DATA_WIDTH] = input_plus_bias[2*DATA_WIDTH*(2*ij+1) +: 2*DATA_WIDTH];
half_max_reg[ij] = 1'b1;
end
end
for (ik = 0; ik < 2; ik = ik + 1) begin //get 3 maxes out of 5
if ($signed(
half_max[2*DATA_WIDTH*2*ik+:2*DATA_WIDTH]
) > $signed(
half_max[2*DATA_WIDTH*(2*ik+1)+:2*DATA_WIDTH]
)) begin
three_max[2*DATA_WIDTH*ik+:2*DATA_WIDTH] = half_max[2*DATA_WIDTH*2*ik+:2*DATA_WIDTH];
three_max_reg[ik] = 1'b0;
end else if ($signed(
half_max[2*DATA_WIDTH*2*ik+:2*DATA_WIDTH]
) <= $signed(
half_max[2*DATA_WIDTH*(2*ik+1)+:2*DATA_WIDTH]
)) begin
three_max[2*DATA_WIDTH*ik+:2*DATA_WIDTH] = half_max[2*DATA_WIDTH*(2*ik+1)+:2*DATA_WIDTH];
three_max_reg[ik] = 1'b1;
end
end
three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2] = half_max[DATA_WIDTH*LENGTH-1:2*DATA_WIDTH*4]; //next module is 3-input max
if ($signed(
(three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2] >= three_max[2*DATA_WIDTH*2-1:2*DATA_WIDTH])
) && $signed(
(three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2] >= three_max[2*DATA_WIDTH-1:0])
)) begin
maximum = three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2];
i_var = 2'd2;
end else if ($signed(
(three_max[2*DATA_WIDTH*2-1:2*DATA_WIDTH] >= three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2])
) && $signed(
(three_max[2*DATA_WIDTH*2-1:2*DATA_WIDTH] >= three_max[2*DATA_WIDTH-1:0])
)) begin
maximum = three_max[2*DATA_WIDTH*2-1:2*DATA_WIDTH];
i_var = 2'd1;
end else if ($signed(
(three_max[2*DATA_WIDTH-1:0] >= three_max[2*DATA_WIDTH*3-1:2*DATA_WIDTH*2])
) && $signed(
(three_max[2*DATA_WIDTH-1:0] >= three_max[2*DATA_WIDTH*2-1:2*DATA_WIDTH])
)) begin
maximum = three_max[2*DATA_WIDTH-1:0];
i_var = 2'd0;
end
maxi[half_max_reg[i_var*2+three_max_reg[i_var]]+4*i_var+2*three_max_reg[i_var]] = 1'b1;
end
end
endmodule
| 7.447021 |
module sum_async_mem #(
parameter AWIDTH = 10,
parameter DWIDTH = 32,
parameter DEPTH = 1024,
parameter MEM_INIT_HEX_FILE = ""
) (
input clk,
input reset,
output done,
input [31:0] size,
output [31:0] sum
);
// TODO: Fill in the remaining logic to compute the sum of memory data from 0 to 'size'
wire [AWIDTH-1:0] rom_addr;
wire [DWIDTH-1:0] rom_rdata;
ASYNC_ROM #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH),
.MEM_INIT_HEX_FILE(MEM_INIT_HEX_FILE)
) rom (
.addr(rom_addr),
.q(rom_rdata)
);
wire [31:0] index_reg_val, index_reg_next;
wire index_reg_rst, index_reg_ce;
REGISTER_R_CE #(
.N(32)
) index_reg (
.q (index_reg_val),
.d (index_reg_next),
.ce (index_reg_ce),
.rst(index_reg_rst),
.clk(clk)
);
wire [31:0] sum_reg_val, sum_reg_next;
wire sum_reg_rst, sum_reg_ce;
REGISTER_R_CE #(
.N(32)
) sum_reg (
.q (sum_reg_val),
.d (sum_reg_next),
.ce (sum_reg_ce),
.rst(sum_reg_rst),
.clk(clk)
);
endmodule
| 7.664892 |
module sum_async_mem_tb ();
localparam AWIDTH = 10;
localparam DWIDTH = 32;
localparam DEPTH = 1024;
reg clk;
initial clk = 0;
always #(4) clk <= ~clk;
reg reset;
reg [31:0] size;
wire [DWIDTH-1:0] sum;
wire done;
sum_async_mem #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH),
.MEM_INIT_HEX_FILE("async_mem_init_hex.mif")
) dut (
.clk (clk),
.reset(reset),
.done (done),
.size (size),
.sum (sum)
);
// "Software" version
reg [31:0] test_vector[DEPTH-1:0];
integer sw_sum = 0;
integer i;
initial begin
#0;
$readmemh("async_mem_init_hex.mif", test_vector);
#1; // advance one tick to make sure sw_sum get updated
for (i = 0; i < size; i = i + 1) begin
sw_sum = sw_sum + test_vector[i];
end
end
reg [31:0] cycle_cnt;
always @(posedge clk) begin
cycle_cnt <= cycle_cnt + 1;
if (done) begin
$display("At time %d, sum = %d, sw_sum = %d, done = %d, number of cycles = %d", $time, sum,
sw_sum, done, cycle_cnt);
if (sum == sw_sum) $display("TEST PASSED!");
else $display("TEST FAILED!");
$finish();
end
end
initial begin
#0;
reset = 0;
size = 1024;
cycle_cnt = 0;
repeat (10) @(posedge clk);
reset = 1;
@(posedge clk);
reset = 0;
repeat (5 * DEPTH) @(posedge clk);
$display("Timeout");
$finish();
end
endmodule
| 7.664892 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
------------------------------------------------------
History:
01-13-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module sum_parallel_timer_test;
//defination for Variables
reg clk;
reg reset;
reg data_start;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[16:0] sum;
wire sum_enable;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
sum_parallel_enable S1( .input_data(out_num),.data_start(data_start),
.CLK(clk), .RST(reset),
.sum(sum),.sum_enable(sum_enable) );
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
data_start <= 1'b0;
end
else if (out_num == 8'hff)
begin
data_start <= 1'b1;
end
else
begin
data_start <= 1'b0;
end
end
end
endmodule
| 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
------------------------------------------------------
History:
01-13-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module sum_parallel_timer_test;
//defination for Variables
reg clk;
reg reset;
reg data_start;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[16:0] sum;
wire sum_enable;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
sum_parallel_timer S1( .input_data(out_num),.data_start(data_start),
.CLK(clk), .RST(reset),
.sum(sum),.sum_enable(sum_enable) );
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
data_start <= 1'b0;
end
else if (out_num == 8'hff)
begin
data_start <= 1'b1;
end
else
begin
data_start <= 1'b0;
end
end
end
endmodule
| 7.206611 |
module Sum_35 (
A,
B,
sum
);
input [34:0] A, B;
output [34:0] sum;
assign sum = A + B;
endmodule
| 7.472767 |
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