code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module latch_controller_1_6 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_6 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_7 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_9 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.194511 |
module latch_controller_1_7 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_7 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_8 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_10 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 6.999778 |
module latch_controller_1_8 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_8 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_9 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_11 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.105424 |
module latch_controller_1_9 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_9 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.08672 |
module latch_controller_1_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n1;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_0 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_5 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_5 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U4 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.033274 |
module latch_controller_1_5 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_5 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.046409 |
module latch_controller_1_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_4 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.34217 |
module latch_controller_1_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_3 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module sr_latch_0_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.553251 |
module c_gate_0_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.222928 |
module latch_controller_1_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_2 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_0_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 6.95665 |
module latch_controller_1_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_1 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.A(Aout),
.Z(N0)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_1_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.390817 |
module latch_controller_0_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n2;
assign Rout = Aout;
c_gate_1_0 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n2)
);
endmodule
| 7.224712 |
module c_gate_1_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.498178 |
module latch_controller_0_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_1 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.665385 |
module c_gate_1_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.741961 |
module latch_controller_0_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_2 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_3 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.608477 |
module c_gate_1_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.685153 |
module latch_controller_0_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_3 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module sr_latch_1_4 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
.Z(qn)
);
endmodule
| 6.598887 |
module c_gate_1_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
.C(preset),
.Z(set)
);
endmodule
| 7.541928 |
module latch_controller_0_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_4 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
.Z(lt_en)
);
HS65_LS_IVX9 U2 (
.A(Ain),
.Z(n1)
);
endmodule
| 7.224712 |
module c_gate_0_6 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.291887 |
module latch_controller_1_6 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_6 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_7 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_9 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.194511 |
module latch_controller_1_7 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_7 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_8 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_10 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 6.999778 |
module latch_controller_1_8 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_8 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_9 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_11 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_AND3X9 U5 (
.A(b),
.B(n1),
.C(a),
.Z(set)
);
endmodule
| 7.105424 |
module latch_controller_1_9 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_9 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Ain),
.Z(n2)
);
HS65_LS_IVX9 U2 (
.A(Aout),
.Z(N0)
);
endmodule
| 7.224712 |
module c_gate_0_0 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.08672 |
module latch_controller_1_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n1;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_0 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n1),
.A(Ain)
);
HS65_LS_IVX9 U2 (
.Z(N0),
.A(Aout)
);
endmodule
| 7.224712 |
module c_gate_0_5 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_5 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_IVX9 U4 (
.Z(n1),
.A(preset)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.033274 |
module latch_controller_1_5 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_5 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(N0),
.A(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_0_4 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.046409 |
module latch_controller_1_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_4 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(N0),
.A(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_0_3 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.34217 |
module latch_controller_1_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_3 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(N0),
.A(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module sr_latch_0_2 (
s,
r,
q,
qn
);
input s;
input r;
output q;
output qn;
// Internal wires
wire N1;
wire n1;
HS65_LS_AND2X27 C8 (
.Z(q),
.B(N1),
.A(n1)
);
HS65_LS_IVX9 U1 (
.Z(n1),
.A(r)
);
HS65_LS_IVX9 U2 (
.Z(N1),
.A(qn)
);
HS65_LS_NOR2X6 U3 (
.Z(qn),
.B(q),
.A(s)
);
endmodule
| 6.553251 |
module c_gate_0_2 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.222928 |
module latch_controller_1_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_2 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(N0),
.A(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_0_1 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 6.95665 |
module latch_controller_1_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_1 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(N0),
.A(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_1_0 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
sr_latch_1_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.Z(reset),
.C(b),
.B(preset),
.A(a)
);
HS65_LS_AO12X9 U4 (
.Z(set),
.C(preset),
.B(b),
.A(a)
);
endmodule
| 7.390817 |
module latch_controller_0_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire n2;
assign Rout = Aout;
c_gate_1_0 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(lt_en),
.A(Aout)
);
HS65_LS_IVX9 U2 (
.Z(n2),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_1_1 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
sr_latch_1_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.Z(reset),
.C(b),
.B(preset),
.A(a)
);
HS65_LS_AO12X9 U4 (
.Z(set),
.C(preset),
.B(b),
.A(a)
);
endmodule
| 7.498178 |
module latch_controller_0_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire n1;
assign Rout = Aout;
c_gate_1_1 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(lt_en),
.A(Aout)
);
HS65_LS_IVX9 U2 (
.Z(n1),
.A(Ain)
);
endmodule
| 7.224712 |
module sr_latch_1_2 (
s,
r,
q,
qn
);
input s;
input r;
output q;
output qn;
// Internal wires
wire N1;
wire n1;
HS65_LS_AND2X27 C8 (
.Z(q),
.B(N1),
.A(n1)
);
HS65_LS_IVX9 U1 (
.Z(n1),
.A(r)
);
HS65_LS_IVX9 U2 (
.Z(N1),
.A(qn)
);
HS65_LS_NOR2X6 U3 (
.Z(qn),
.B(q),
.A(s)
);
endmodule
| 6.665385 |
module c_gate_1_2 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
sr_latch_1_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.Z(reset),
.C(b),
.B(preset),
.A(a)
);
HS65_LS_AO12X9 U4 (
.Z(set),
.C(preset),
.B(b),
.A(a)
);
endmodule
| 7.741961 |
module latch_controller_0_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire n1;
assign Rout = Aout;
c_gate_1_2 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(lt_en),
.A(Aout)
);
HS65_LS_IVX9 U2 (
.Z(n1),
.A(Ain)
);
endmodule
| 7.224712 |
module sr_latch_1_3 (
s,
r,
q,
qn
);
input s;
input r;
output q;
output qn;
// Internal wires
wire N1;
wire n1;
HS65_LS_AND2X27 C8 (
.Z(q),
.B(N1),
.A(n1)
);
HS65_LS_IVX9 U1 (
.Z(n1),
.A(r)
);
HS65_LS_IVX9 U2 (
.Z(N1),
.A(qn)
);
HS65_LS_NOR2X6 U3 (
.Z(qn),
.B(q),
.A(s)
);
endmodule
| 6.608477 |
module c_gate_1_3 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
sr_latch_1_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.Z(reset),
.C(b),
.B(preset),
.A(a)
);
HS65_LS_AO12X9 U4 (
.Z(set),
.C(preset),
.B(b),
.A(a)
);
endmodule
| 7.685153 |
module latch_controller_0_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire n1;
assign Rout = Aout;
c_gate_1_3 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(lt_en),
.A(Aout)
);
HS65_LS_IVX9 U2 (
.Z(n1),
.A(Ain)
);
endmodule
| 7.224712 |
module sr_latch_1_4 (
s,
r,
q,
qn
);
input s;
input r;
output q;
output qn;
// Internal wires
wire N1;
wire n1;
HS65_LS_AND2X27 C8 (
.Z(q),
.B(N1),
.A(n1)
);
HS65_LS_IVX9 U1 (
.Z(n1),
.A(r)
);
HS65_LS_IVX9 U2 (
.Z(N1),
.A(qn)
);
HS65_LS_NOR2X6 U3 (
.Z(qn),
.B(q),
.A(s)
);
endmodule
| 6.598887 |
module c_gate_1_4 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
sr_latch_1_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.Z(reset),
.C(b),
.B(preset),
.A(a)
);
HS65_LS_AO12X9 U4 (
.Z(set),
.C(preset),
.B(b),
.A(a)
);
endmodule
| 7.541928 |
module latch_controller_0_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire n1;
assign Rout = Aout;
c_gate_1_4 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(lt_en),
.A(Aout)
);
HS65_LS_IVX9 U2 (
.Z(n1),
.A(Ain)
);
endmodule
| 7.224712 |
module c_gate_0_6 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.291887 |
module latch_controller_1_6 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_6 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
HS65_LS_IVX9 U2 (
.Z(N0),
.A(Aout)
);
endmodule
| 7.224712 |
module c_gate_0_7 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_9 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.194511 |
module latch_controller_1_7 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_7 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
HS65_LS_IVX9 U2 (
.Z(N0),
.A(Aout)
);
endmodule
| 7.224712 |
module c_gate_0_8 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_10 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 6.999778 |
module latch_controller_1_8 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_8 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
HS65_LS_IVX9 U2 (
.Z(N0),
.A(Aout)
);
endmodule
| 7.224712 |
module c_gate_0_9 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_11 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.105424 |
module latch_controller_1_9 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire N0;
wire n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_9 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(n2),
.A(Ain)
);
HS65_LS_IVX9 U2 (
.Z(N0),
.A(Aout)
);
endmodule
| 7.224712 |
module select_element_0 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);
HS65_LS_LDLRQX9 false_latch_out_reg (
.RN(n3),
.Q (false),
.GN(sel),
.D (n2)
);
HS65_LS_IVX9 U3 (
.Z(n3),
.A(preset)
);
HS65_LSS_XOR2X6 U4 (
.Z(n1),
.B(false),
.A(\input )
);
HS65_LSS_XOR2X6 U5 (
.Z(n2),
.B(true),
.A(\input )
);
endmodule
| 6.561954 |
module c_gate_0_0 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.08672 |
module c_gate_0_10 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_10 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 6.992582 |
module latch_controller_1_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_10 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U2 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module c_gate_0_5 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_5 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U4 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
HS65_LS_IVX9 U5 (
.Z(n1),
.A(preset)
);
endmodule
| 7.033274 |
module latch_controller_1_5 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_5 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U1 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module c_gate_0_4 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U4 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
HS65_LS_IVX9 U5 (
.Z(n1),
.A(preset)
);
endmodule
| 7.046409 |
module latch_controller_1_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_4 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U1 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module c_gate_0_3 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U4 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
HS65_LS_IVX9 U5 (
.Z(n1),
.A(preset)
);
endmodule
| 7.34217 |
module latch_controller_1_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_3 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U1 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module sr_latch_0_2 (
s,
r,
q,
qn
);
input s;
input r;
output q;
output qn;
// Internal wires
wire N10;
wire N12;
wire n1;
wire n2;
wire n3;
HS65_LS_LDHQX9 q_internal_reg (
.Q(q),
.G(N10),
.D(n1)
);
HS65_LS_LDHQX9 qn_internal_reg (
.Q(qn),
.G(N10),
.D(N12)
);
HS65_LS_NAND2X7 U8 (
.Z(N10),
.B(n2),
.A(n3)
);
HS65_LS_IVX9 U9 (
.Z(n2),
.A(r)
);
HS65_LS_NOR2X6 U10 (
.Z(n1),
.B(n3),
.A(r)
);
HS65_LS_NOR2X6 U11 (
.Z(N12),
.B(n2),
.A(s)
);
HS65_LS_IVX9 U12 (
.Z(n3),
.A(s)
);
endmodule
| 6.553251 |
module c_gate_0_2 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U4 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
HS65_LS_IVX9 U5 (
.Z(n1),
.A(preset)
);
endmodule
| 7.222928 |
module latch_controller_1_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_2 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U1 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module c_gate_0_1 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U4 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
HS65_LS_IVX9 U5 (
.Z(n1),
.A(preset)
);
endmodule
| 6.95665 |
module latch_controller_1_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_1 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 I_0 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U1 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module select_element_1 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);
HS65_LS_LDLRQX9 false_latch_out_reg (
.RN(n3),
.Q (false),
.GN(sel),
.D (n2)
);
HS65_LS_IVX9 U3 (
.Z(n3),
.A(preset)
);
HS65_LSS_XOR2X6 U4 (
.Z(n1),
.B(false),
.A(\input )
);
HS65_LSS_XOR2X6 U5 (
.Z(n2),
.B(true),
.A(\input )
);
endmodule
| 6.561954 |
module c_gate_0_11 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_12 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.104564 |
module c_gate_0_6 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_6 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.291887 |
module latch_controller_1_6 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_6 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U2 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module select_element_2 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);
HS65_LS_LDLRQX9 false_latch_out_reg (
.RN(n3),
.Q (false),
.GN(sel),
.D (n2)
);
HS65_LS_IVX9 U3 (
.Z(n3),
.A(preset)
);
HS65_LSS_XOR2X6 U4 (
.Z(n1),
.B(false),
.A(\input )
);
HS65_LSS_XOR2X6 U5 (
.Z(n2),
.B(true),
.A(\input )
);
endmodule
| 6.561954 |
module c_gate_0_12 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_14 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.237468 |
module c_gate_0_7 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_7 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.194511 |
module latch_controller_1_7 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_7 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.Z(not_Ain),
.A(Ain)
);
HS65_LSS_XOR2X6 U2 (
.Z(lt_en),
.B(Ain),
.A(Rin)
);
endmodule
| 7.224712 |
module select_element_3 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);
HS65_LS_LDLRQX9 false_latch_out_reg (
.RN(n3),
.Q (false),
.GN(sel),
.D (n2)
);
HS65_LS_IVX9 U3 (
.Z(n3),
.A(preset)
);
HS65_LSS_XOR2X6 U4 (
.Z(n1),
.B(false),
.A(\input )
);
HS65_LSS_XOR2X6 U5 (
.Z(n2),
.B(true),
.A(\input )
);
endmodule
| 6.561954 |
module c_gate_0_13 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_16 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
.Z(reset),
.C(n1),
.B(a),
.A(b)
);
HS65_LS_AND3X9 U5 (
.Z(set),
.C(a),
.B(n1),
.A(b)
);
endmodule
| 7.072989 |
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