code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module T34 (
input [2:0] A,
input [2:0] B,
input [2:0] C,
input [2:0] D,
output X
);
assign X = ~|{&{A}, &{B}, &{C}, &{D}}; // tmax = 3.3ns
endmodule
| 6.81509 |
module T35seg7_top (
clockIn, // 50MHz input from onboard oscillator
// n_reset, // Uncomment to have an external reset
dp, // 7 segment display decimal point
segment7
); // 7 segment display, main LEDs
input clockIn;
// input n_reset; // Uncomment to have an external reset
output reg dp;
output reg [6:0] segment7;
reg [25:0] counter; // 26-bit counter for one second count
reg [ 3:0] digit; // 4-bit counter for 7 seg 0-F display
wire n_reset; // Comment this line out to have an external reset
assign n_reset = 1'b1; // Comment this line out to have an external reset
always @(posedge clockIn) begin
if (n_reset == 0) begin // if reset set low...
digit <= 4'b0000; // reset digit to 0
counter <= 25'b0; // reset counter to 0
end // end of resetting everything
else
begin
counter <= counter + 1; // increment counter
if (counter == 25000000) begin // decimal point 1/2 second on/off
dp = !dp; // turn off decimal point
end // end of decimap point test
if (counter >= 50000000) begin // counter is at 1 second
digit <= digit + 1; // increment to next digit
dp = !dp; // turn decimal point back on
counter <= 25'b0; // finally, reset counter
end // end of one second test
end
case (digit)
4'h0: segment7 = 7'b1000000; // display 0
4'h1: segment7 = 7'b1111001; // display 1
4'h2: segment7 = 7'b0100100; // display 2
4'h3: segment7 = 7'b0110000; // display 3
4'h4: segment7 = 7'b0011001; // display 4
4'h5: segment7 = 7'b0010010; // display 5
4'h6: segment7 = 7'b0000010; // display 6
4'h7: segment7 = 7'b1111000; // display 7
4'h8: segment7 = 7'b0000000; // display 8
4'h9: segment7 = 7'b0010000; // display 9
4'ha: segment7 = 7'b0001000; // display A
4'hb: segment7 = 7'b0000011; // display B
4'hc: segment7 = 7'b1000110; // display C
4'hd: segment7 = 7'b0100001; // display D
4'he: segment7 = 7'b0000110; // display E
default: segment7 = 7'b0001110; // otherwise display F
endcase
end
endmodule
| 7.037491 |
module T3TE8_V (
input input1,
input input2,
input input3,
input inputen,
output reg [7:0] output1
// output output2,
// output output3,
// output output4,
// output output5,
// output output6,
// output output7,
// output output8
);
always @* begin
if (~inputen)
casex ({
input1, input2, input3
})
3'b000: output1 = 8'b00000001;
3'b001: output1 = 8'b00000010;
3'b010: output1 = 8'b00000100;
3'b011: output1 = 8'b00001000;
3'b100: output1 = 8'b00010000;
3'b101: output1 = 8'b00100000;
3'b110: output1 = 8'b01000000;
3'b111: output1 = 8'b10000000;
endcase
else output1 = 8'b00000000;
end
endmodule
| 7.494971 |
module simpleand (
a,
b,
c
);
input a, b;
output c;
reg c;
always @(*) c = a & b;
endmodule
| 7.04245 |
module t48_p1 (
input clk_i,
input res_i,
input en_clk_i,
input [7:0] data_i,
input write_p1_i,
input read_p1_i,
input read_reg_i,
input [7:0] p1_i,
output [7:0] data_o,
output [7:0] p1_o,
output p1_low_imp_o
);
wire [7:0] p1_q;
wire low_imp_q;
wire n4671_o;
wire n4676_o;
wire n4677_o;
wire [7:0] n4687_o;
wire [7:0] n4689_o;
wire [7:0] n4692_o;
reg [7:0] n4693_q;
wire n4694_o;
reg n4695_q;
assign data_o = n4689_o;
assign p1_o = p1_q;
assign p1_low_imp_o = low_imp_q;
/* p1.vhd:81:10 */
assign p1_q = n4693_q; // (signal)
/* p1.vhd:84:10 */
assign low_imp_q = n4695_q; // (signal)
/* p1.vhd:96:14 */
assign n4671_o = ~res_i;
/* p1.vhd:103:9 */
assign n4676_o = write_p1_i ? 1'b1 : 1'b0;
/* p1.vhd:101:7 */
assign n4677_o = en_clk_i & write_p1_i;
/* p1.vhd:133:7 */
assign n4687_o = read_reg_i ? p1_q : p1_i;
/* p1.vhd:132:5 */
assign n4689_o = read_p1_i ? n4687_o : 8'b11111111;
/* p1.vhd:100:5 */
assign n4692_o = n4677_o ? data_i : p1_q;
/* p1.vhd:100:5 */
always @(posedge clk_i or posedge n4671_o)
if (n4671_o) n4693_q <= 8'b11111111;
else n4693_q <= n4692_o;
/* p1.vhd:100:5 */
assign n4694_o = en_clk_i ? n4676_o : low_imp_q;
/* p1.vhd:100:5 */
always @(posedge clk_i or posedge n4671_o)
if (n4671_o) n4695_q <= 1'b0;
else n4695_q <= n4694_o;
endmodule
| 7.072742 |
module T4L4 (
A,
B,
out1,
out2
);
input [3:0] A, B;
output out1, out2;
assign out1 = (A > B) ? 1 : 0;
assign out2 = (A == B) ? 1 : 0;
endmodule
| 7.10832 |
module: T4L4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T4L4_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire out1;
wire out2;
// Instantiate the Unit Under Test (UUT)
T4L4 uut (
.A(A),
.B(B),
.out1(out1),
.out2(out2)
);
initial begin
// Initialize Inputs
$monitor($time,"A=%b,B=%b,out1=%b,out2=%b",A,B,out1,out2);
A = 4'b0000;
B = 4'b0000;
#100;
A = 4'b1011;
B = 4'b0001;
#100;
A = 4'b1100;
B = 4'b1101;
#100;
end
endmodule
| 6.946819 |
module T5A (
input A1,
A2,
input B1,
B2,
input S2,
S6,
output X
);
wire mux_A = S2 ? A1 : A2;
wire mux_B = S2 ? B2 : B1;
assign X = ~(S6 ? mux_A : mux_B); // tmax = 3.3ns
endmodule
| 7.869936 |
module t5_t6 (
v0,
v1,
v2,
v3,
sp0,
sp1,
sp2,
sp3,
clock_25,
clock_maior,
rst,
att_color,
data_color,
blue,
green,
red
);
// Sinais básicos de controle
input clock_25, rst;
// Vetores com as flags indicando a presenca dos sprites em cada uma das 16 posicoes
input [15:0] v0, v1, v2, v3;
// Indica o codigo do sprite referente a cada um dos vetores anteriormente definidos
input [4:0] sp0, sp1, sp2, sp3;
// Entradas para atualização da memória de cor
input [23:0] data_color; // Dado da cor vindo da mémoria
input att_color; // Sinal para atualizar a memória
// Sinal para descarregar os sinais dos barramentos de entreda
input clock_maior;
//Saidas do modulo
output wire [7:0] red, green, blue;
// memória interna de cores da FSM.
reg [23:0] Color_Memory[0:31];
// memória interna de sprites da FSM
reg [15:0] sprites[0:3];
reg [4:0] pos[0:3];
// Registradores de suporte
reg branco;
reg start;
reg [1:0] state;
reg [1:0] next_state;
reg [4:0] elemento;
reg [4:0] next_elemento;
reg [4:0] saida;
reg [3:0] count;
reg [3:0] next_count;
parameter Inicio = 2'b00, Atualizando = 2'b01, Enviando = 2'b10, Sync = 2'b11;
always @* begin
next_state = 5'bxxxxx;
next_elemento = elemento;
next_count = count;
saida = 5'bx;
branco = 1'b1;
case (state)
Inicio: begin // Estado Inicial
next_state = Atualizando;
end
Sync: begin // Estado de sincronização com o clock mais lento (25/16 Mhz)
if (start) begin
if (count == 15) begin
next_state = Enviando;
end else begin
next_state = Sync;
next_count = count + 1'b1;
end
end else begin
next_state = Sync;
end
end
Atualizando: begin // Estado para atualizar a tabela de cores.
if (elemento == 5'd31) begin
next_elemento = 5'b0;
next_state = Sync;
end else begin
next_elemento = elemento + 1'b1;
next_state = Atualizando;
end
end
Enviando: begin // Estado de saída das cores do sprite mais importante
if (att_color) begin
next_elemento = 5'b0;
next_state = Atualizando;
end else begin
next_state = Enviando;
branco = 1'b0;
if (sprites[0][15-elemento[3:0]]) begin
saida = pos[0];
end else if (sprites[1][15-elemento[3:0]]) begin
saida = pos[1];
end else if (sprites[2][15-elemento[3:0]]) begin
saida = pos[2];
end else if (sprites[3][15-elemento[3:0]]) begin
saida = pos[3];
end else begin
branco = 1'b1;
end
next_elemento = elemento + 1'b1;
end
end
default: begin
next_state = Inicio;
end
endcase
end
assign red = (branco) ? 8'b0 : Color_Memory[saida][23:16];
assign green = (branco) ? 8'b0 : Color_Memory[saida][15:8];
assign blue = (branco) ? 8'b0 : Color_Memory[saida][7:0];
always @(posedge clock_maior) begin
if (!rst) begin
sprites[0] <= v0;
sprites[1] <= v1;
sprites[2] <= v2;
sprites[3] <= v3;
pos[0] <= sp0;
pos[1] <= sp1;
pos[2] <= sp2;
pos[3] <= sp3;
if (next_state == Sync) begin
start <= 1'b1;
end else begin
start <= 1'b0;
end
end
end
always @(posedge clock_25) begin
if (rst) begin
state <= Inicio;
elemento <= 5'b0;
count <= 4'b0;
end else begin
state <= next_state;
elemento <= next_elemento;
count <= next_count;
if (next_state == Atualizando) begin
Color_Memory[next_elemento] = data_color;
end
end
end
endmodule
| 7.632149 |
module T6507LP_ALU_TestBench (
input dummy,
output error
);
`include "T6507LP_Package.v"
reg clk_i;
reg n_rst_i;
reg alu_enable;
wire [7:0] alu_result;
wire [7:0] alu_status;
reg [7:0] alu_opcode;
reg [7:0] alu_a;
//`include "T6507LP_Package.v"
T6507LP_ALU DUT (
.clk_i(clk_i),
.n_rst_i(n_rst_i),
.alu_enable(alu_enable),
.alu_result(alu_result),
.alu_status(alu_status),
.alu_opcode(alu_opcode),
.alu_a(alu_a)
);
/*
localparam period = 10;
always begin
#(period/2) clk_i = ~clk_i;
end
initial
begin
clk_i = 0;
n_rst_i = 1;
@(negedge clk_i);
n_rst_i = 0;
alu_opcode = LDA_IMM;
alu_a = 0;
@(negedge clk_i);
alu_opcode = ADC_IMM;
alu_a = 1;
while (1) begin
$display("op1 = %h op2 = c = %h d = %h n = %h v = %h ", alu_a, alu_status[C], alu_status[D], alu_status[N], alu_status[V]);
end
$finish;
end
*/
endmodule
| 6.651387 |
module t6507lp_alu_wrapper ();
parameter [3:0] DATA_SIZE = 4'd8;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
// all inputs are regs
reg clk;
reg reset_n;
reg alu_enable;
reg [DATA_SIZE_:0] alu_opcode;
reg [DATA_SIZE_:0] alu_a;
// all outputs are wires
wire [DATA_SIZE_:0] alu_result;
wire [DATA_SIZE_:0] alu_status;
wire [DATA_SIZE_:0] alu_x;
wire [DATA_SIZE_:0] alu_y;
initial clk = 0;
always #10 clk <= ~clk;
always @(posedge clk) begin
//$display("reset is %b", reset_n);
//$display("alu_enable is %b", alu_enable);
//$display("alu_opcode is %h", alu_opcode);
//$display("alu_a is %d", alu_a);
end
t6507lp_alu t6507lp_alu (
.clk(clk),
.reset_n(reset_n),
.alu_enable(alu_enable),
.alu_result(alu_result),
.alu_status(alu_status),
.alu_opcode(alu_opcode),
.alu_a(alu_a),
.alu_x(alu_x),
.alu_y(alu_y)
);
endmodule
| 6.937868 |
module t6532_tb ();
// mem_rw signals
localparam MEM_READ = 1'b0;
localparam MEM_WRITE = 1'b1;
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
reg clk; // regs are inputs
reg reset_n;
reg [15:0] io_lines;
reg enable;
reg mem_rw;
reg [ADDR_SIZE_:0] address;
reg [DATA_SIZE_:0] data_drv;
tri [DATA_SIZE_:0] data = data_drv;
t6532 #(DATA_SIZE, ADDR_SIZE) t6532 (
.clk(clk),
.reset_n(reset_n),
.io_lines(io_lines),
.enable(enable),
.mem_rw(mem_rw),
.address(address),
.data(data)
);
always #10 clk = ~clk;
always @(*) begin
if (mem_rw == MEM_READ) begin
data_drv = 8'hZ;
end
end
initial begin
clk = 1'b0;
reset_n = 1'b0;
io_lines = 16'd0;
enable = 1'b0;
mem_rw = MEM_READ;
address = 0;
@(negedge clk) // will wait for next negative edge of the clock (t=20)
reset_n = 1'b1;
@(negedge clk) // testing the port_b. all switches must change!
io_lines = 16'h00FF;
@(negedge clk) // testing the port_b. all switches must change!
io_lines = 16'h00FF;
@(negedge clk) // testing the port_a. all switches must change since ddra = 0. (0 == input)
io_lines = 16'hFF00;
@(negedge clk) // setting ddra = FF. (output)
enable = 1'b1;
io_lines = 16'hFF00;
address = 10'h281;
mem_rw = MEM_WRITE;
data_drv = 8'hFF;
@(negedge clk) // testing port_a again. no switching this time!
enable = 1'b0;
io_lines = 16'h0000;
address = 0;
mem_rw = MEM_READ;
@(negedge clk) // writing at the memory
enable = 1'b1;
address = 10'd255;
mem_rw = MEM_WRITE;
data_drv = 8'h11;
@(negedge clk) // reading memory (output)
enable = 1'b1;
address = 10'd255;
mem_rw = MEM_READ;
@(negedge clk) // using the timer to count 100*1 cycle.
enable = 1'b1;
address = 10'h294;
mem_rw = MEM_WRITE;
data_drv = 8'd100;
@(negedge clk);
mem_rw = MEM_READ;
enable = 1'b0;
#2040;
@(negedge clk) // using the timer to count 10*8 cycles.
enable = 1'b1;
address = 10'h295;
mem_rw = MEM_WRITE;
data_drv = 8'd10;
@(negedge clk);
mem_rw = MEM_READ;
enable = 1'b0;
#1640;
$finish; // to shut down the simulation
end //initial
endmodule
| 7.807723 |
module t7 (
input wire [7:0] FIFO_Red,
input wire [7:0] FIFO_Green,
input wire [7:0] FIFO_Blue,
input wire [7:0] Sprites_Red,
input wire [7:0] Sprites_Green,
input wire [7:0] Sprites_Blue,
output wire [7:0] VGA_R,
output wire [7:0] VGA_G,
output wire [7:0] VGA_B
);
assign VGA_R = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Red: Sprites_Red;
assign VGA_G = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Green: Sprites_Green;
assign VGA_B = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Blue: Sprites_Blue;
endmodule
| 6.868072 |
module z80 (
// Outputs
m1_n,
mreq_n,
iorq_n,
rd_n,
wr_n,
rfsh_n,
halt_n,
busak_n,
A,
dout,
// Inputs
reset_n,
clk,
wait_n,
int_n,
nmi_n,
busrq_n,
di
);
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
wire [7:0] d;
z80_top_direct_n cpu_goran (
.nM1(m1_n),
.nMREQ(mreq_n),
.nIORQ(iorq_n),
.nRD(rd_n),
.nWR(wr_n),
.nRFSH(rfsh_n),
.nHALT(halt_n),
.nBUSACK(busak_n),
.nWAIT(wait_n),
.nINT(int_n),
.nNMI(nmi_n),
.nRESET(reset_n),
.nBUSRQ(busrq_n),
.CLK(clk),
.A(A),
.D(d)
);
// T80a_verilog TheCPU (
// .RESET_n(reset_n),
// .CLK_n(clk),
// .WAIT_n(wait_n),
// .INT_n(int_n),
// .NMI_n(nmi_n),
// .BUSRQ_n(busrq_n),
// .M1_n(m1_n),
// .MREQ_n(mreq_n),
// .IORQ_n(iorq_n),
// .RD_n(rd_n),
// .WR_n(wr_n),
// .RFSH_n(rfsh_n),
// .HALT_n(halt_n),
// .BUSAK_n(busak_n),
// .A(A),
// .D(d)
// );
// Detector de OUT (C),0
reg [2:0] state = 3'd0;
reg [7:0] opcode = 8'h00;
always @(posedge clk) begin
if (mreq_n == 1'b0 && rd_n == 1'b0 && m1_n == 1'b0) opcode <= di;
if (reset_n == 1'b0) state <= 3'd0;
else begin
case (state)
3'd0: if (mreq_n == 1'b0 && rd_n == 1'b0 && m1_n == 1'b0) state <= 3'd1;
3'd1:
if (m1_n == 1'b1) begin
if (opcode == 8'hED) state <= 3'd2;
else state <= 3'd0;
end
3'd2: if (mreq_n == 1'b0 && rd_n == 1'b0 && m1_n == 1'b0) state <= 3'd3;
3'd3:
if (m1_n == 1'b1) begin
if (opcode == 8'h71) state <= 3'd4;
else state <= 3'd0;
end
3'd4: if (iorq_n == 1'b0) state <= 3'd5;
3'd5: if (iorq_n == 1'b1) state <= 3'd0;
endcase
end
end
assign dout = (state == 3'd4 || state == 3'd5) ? 8'h00 : d;
assign d = (!m1_n && !iorq_n) ? 8'hFF : (!rd_n) ? di : 8'hZZ;
endmodule
| 7.014568 |
module ta151_bar (
input D0, //
input D1, //
input D2, //
input D3, //
input D4, //
input D5, //
input D6, //
input D7, //
input A, //
input B, //
input C, //
input EN_BAR, //
output Y, //
output W //
);
assign EN = ~EN_BAR;
// 8-line to 1-line data selector/multiplexer
// Replaced ta151 in THESIS with jeff_74x151
jeff_74x151_behavioral U1 (
.d0(D0),
.d1(D1),
.d2(D2),
.d3(D3),
.d4(D4),
.d5(D5),
.d6(D6),
.d7(D7),
.a (A),
.b (B),
.c (C),
.en(EN),
.y (Y),
.w (W)
);
endmodule
| 8.179456 |
module ta161_bar (
input CLR_BAR, // CLEAR
input LD_BAR, // LOAD
input ENT, // ENABLE T
input ENP, // ENABLE P
input CLK, // CLK
input A,
B,
C,
D, // DATA IN
output QA,
QB,
QC,
QD, // DATA OUT
output RCO // RIPPLE CARRY OUTPUT
);
// 4-bit synchronous counter
// Replaced ta161 in THESIS with jeff_74x161
jeff_74x161 U1 (
.clr_bar(CLR_BAR),
.ld_bar(LD_BAR),
.ent(ENT),
.enp(ENP),
.clk(CLK),
.a(A),
.b(B),
.c(C),
.d(D),
.qa(QA),
.qb(QB),
.qc(QC),
.qd(QD),
.rco(RCO)
);
endmodule
| 7.474988 |
module ta181_bar (
input A3_BAR,
A2_BAR,
A1_BAR,
A0_BAR, // WORD 1
input B3_BAR,
B2_BAR,
B1_BAR,
B0_BAR, // WORD 2
input S3,
S2,
S1,
S0, // FUNCTION SELECT
input M, // MODE: 0 is arithmetic, 1 is logic
input CI, // CARRY IN
output F3_BAR,
F2_BAR,
F1_BAR,
F0_BAR, // OUTPUT
output CO, // CARRY OUT
output AEQB, // WHEN A = B
output P_BAR, // PROPAGATE - I don't use this
output G_BAR // GENERATE - I don't use this
);
// WIRES REMOVED TO KEEP ALU POSITIVE
// wire A0_SIG, A1_SIG, A2_SIG, A3_SIG;
// wire B0_SIG, B1_SIG, B2_SIG, B3_SIG;
// wire F0_SIG, F1_SIG, F2_SIG, F3_SIG;
assign CO = ~CO_BAR; // NOT IN THESIS
assign CI_BAR = ~CI; // NOT IN THESIS
// 4-bit arithmetic logic unit and function generator
// Replaced ta181 in THESIS with jeff_74x181
jeff_74x181 U1 (
.a3(A3_BAR),
.a2(A2_BAR),
.a1(A1_BAR),
.a0(A0_BAR),
.b3(B3_BAR),
.b2(B2_BAR),
.b1(B1_BAR),
.b0(B0_BAR),
.s3(S3),
.s2(S2),
.s1(S1),
.s0(S0),
.m(M),
.ci_bar(CI_BAR),
.f3(F3_BAR),
.f2(F2_BAR),
.f1(F1_BAR),
.f0(F0_BAR),
.co_bar(CO_BAR),
.aeqb(AEQB),
.x(P_BAR),
.y(G_BAR)
);
//not1 INV1 (.a(A3_BAR), .y(A3_SIG)); // REMOVED THIS TO KEEP IT POSTITVE
//not1 INV2 (.a(A2_BAR), .y(A2_SIG));
//not1 INV3 (.a(A1_BAR), .y(A1_SIG));
//not1 INV4 (.a(A0_BAR), .y(A0_SIG));
//not1 INV5 (.a(B3_BAR), .y(B3_SIG));
//not1 INV6 (.a(B2_BAR), .y(B2_SIG));
//not1 INV7 (.a(B1_BAR), .y(B1_SIG));
//not1 INV8 (.a(B0_BAR), .y(B0_SIG));
//not1 INV9 (.a(F3_SIG), .y(F3_BAR));
//not1 INV10 (.a(F2_SIG), .y(F2_BAR));
//not1 INV11 (.a(F1_SIG), .y(F1_BAR));
//not1 INV12 (.a(F0_SIG), .y(F0_BAR));
endmodule
| 7.423474 |
module main (
input vd9b5c7,
input va55d5a,
input v006143,
output vfe8161
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign w0 = vd9b5c7;
assign w2 = va55d5a;
assign w4 = v006143;
assign w9 = vd9b5c7;
assign w10 = va55d5a;
assign w11 = v006143;
assign vfe8161 = w13;
assign w9 = w0;
assign w10 = w2;
assign w11 = w4;
main_logic_gate_and vbcc84a (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
main_logic_gate_and v3cc07d (
.v0e28cb(w3),
.v3ca442(w4),
.vcbab45(w5)
);
main_logic_gate_or veb55c4 (
.v0e28cb(w5),
.v3ca442(w6),
.vcbab45(w12)
);
main_logic_gate_or vaf19bb (
.v3ca442(w10),
.v0e28cb(w12),
.vcbab45(w13)
);
main_logic_gate_and v8688cf (
.vcbab45(w6),
.v0e28cb(w7),
.v3ca442(w8)
);
main_logic_gate_not v62acdc (
.vcbab45(w1),
.v0e28cb(w2)
);
main_logic_gate_not v9ecb77 (
.vcbab45(w7),
.v0e28cb(w9)
);
main_logic_gate_not vfd1241 (
.vcbab45(w8),
.v0e28cb(w11)
);
endmodule
| 7.081372 |
module main_logic_gate_and (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
main_logic_gate_and_basic_code_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
| 8.037914 |
module main_logic_gate_and_basic_code_vf4938a (
input a,
input b,
output c
);
// AND logic gate
assign c = a & b;
endmodule
| 8.037914 |
module main_logic_gate_or (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
main_logic_gate_or_basic_code_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
| 8.037914 |
module main_logic_gate_or_basic_code_vf4938a (
input a,
input b,
output c
);
// OR logic gate
assign c = a | b;
endmodule
| 8.037914 |
module main_logic_gate_not (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
main_logic_gate_not_basic_code_vd54ca1 vd54ca1 (
.a(w0),
.c(w1)
);
endmodule
| 8.037914 |
module main_logic_gate_not_basic_code_vd54ca1 (
input a,
output c
);
// NOT logic gate
assign c = ~a;
endmodule
| 8.037914 |
module TableArray(ADDR1,DOUT1,ADDR2,DIN,WE,CLK);
parameter DBITS; // Number of data bits
parameter ABITS; // Number of address bits
parameter WORDS = (1<<ABITS);
parameter MFILE = "";
input [(ABITS-1):0] ADDR1, ADDR2;
input [(DBITS-1):0] DIN;
output reg [(DBITS-1):0] DOUT1;
input CLK,WE;
(* ram_init_file = MFILE *) (* ramstyle="no_rw_check" *)
reg [(DBITS-1):0] mem[(WORDS-1):0];
always @(posedge CLK)
if(WE)
mem[ADDR2] <= DIN;
always @(ADDR1)
DOUT1=mem[ADDR1];
endmodule
| 6.948297 |
module TableRAM #(
parameter FILE = "inittab.list",
parameter rows = 30,
parameter cols = 40,
parameter addr_width = 11, // log2(rows*cols)
parameter nsprites = 8 // cambiar nombre por spr_width = log2(nsprites)
) (
input wire clk,
input wire [ nsprites-1:0] din,
input wire write_en,
input wire [addr_width-1:0] waddr,
input wire [addr_width-1:0] raddr,
output reg [ nsprites-1:0] dout
);
reg [nsprites-1:0] mem[(rows*cols)-1:0];
initial begin
if (FILE) $readmemh(FILE, mem);
end
always @(posedge clk) // Write memory.
begin
if (write_en) mem[waddr] <= din; // Using write address bus.
end
always @(posedge clk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
| 7.038891 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// Table address is BYTE address
module table_ad_receive #(
parameter MODE_16_BITS = 1,
parameter NUM_CHN = 1
)(
input clk, // posedge mclk
input a_not_d, // receiving adderass / not data - valid during all bytes
input [7:0] ser_d, // byte-wide address/data
input [NUM_CHN-1:0] dv, // data valid - active for each address or data bytes
output [23-MODE_16_BITS:0] ta, // table address
output [(MODE_16_BITS?15:7):0] td, // 8/16 bit table data, LSB first
output [NUM_CHN-1:0] twe // table write enable
);
reg [23:0] addr_r;
reg [NUM_CHN-1:0] twe_r;
reg [(MODE_16_BITS?15:7):0] td_r;
assign td = td_r;
assign ta = MODE_16_BITS ? addr_r[23:1] : addr_r[23:0];
// assign twe = twe_r && (MODE_16_BITS ? addr_r[0]: 1'b1);
assign twe = (MODE_16_BITS ? addr_r[0]: 1'b1)? twe_r : {NUM_CHN{1'b0}} ;
always @(posedge clk) begin
// twe_r <= en && !a_not_d;
twe_r <= a_not_d ? 0 : dv;
if ((|dv) && a_not_d) addr_r[23:0] <= {ser_d,addr_r[23:8]};
else if (|twe_r) addr_r[23:0] <= addr_r[23:0] + 1;
end
generate
if (MODE_16_BITS) always @ (posedge clk) td_r[15:0] <= {ser_d[7:0],td_r[15:8]}; //LSB received first
else always @ (posedge clk) td_r[ 7:0] <= ser_d[7:0];
endgenerate
endmodule
| 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// Table address is BYTE address
module table_ad_transmit#(
parameter NUM_CHANNELS = 1,
parameter ADDR_BITS=4
)(
input clk, // posedge mclk
input srst, // reset @posedge clk
input a_not_d_in, // address/not data input (valid @ we)
input we, // write address/data (single cycle) with at least 5 inactive between
input [31:0] din, // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte address (@we)
output [ 7:0] ser_d, // 8-bit address/data to be sent to submodules that have table write port(s), LSB first
output reg a_not_d, // sending adderass / not data - valid during all bytes
output reg [NUM_CHANNELS-1:0] chn_en // sending address or data
);
wire [NUM_CHANNELS-1:0] sel;
reg [31:0] d_r;
reg any_en;
reg [ADDR_BITS-1:0] sel_a;
reg we_r;
wire we3;
assign ser_d = d_r[7:0];
always @ (posedge clk) begin
if (we) d_r <= din;
else if (any_en) d_r <= d_r >> 8;
if (we) a_not_d <= a_not_d_in;
we_r <= we && a_not_d_in;
if (srst) any_en <= 0;
else if ((we && !a_not_d_in) || we_r) any_en <= 1;
else if (we3) any_en <= 0;
if (srst) chn_en <= 0;
else if ((we && !a_not_d_in) || we_r) chn_en <= sel;
else if (we3) chn_en <= 0;
if (we && a_not_d_in) sel_a <= din[24+:ADDR_BITS];
end
// dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(4'd2), .din(we), .dout(we3)); // dly=2+1=3
dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(4'd3), .din(we), .dout(we3)); // dly=3+1=4
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : gsel
assign sel[i] = sel_a == i;
end
endgenerate
endmodule
| 8.081644 |
module table_control #(
parameter n_words = 40
) (
input clk
, input ctrl_reset_n
, input [26:0] tdatai // dispatch intf to tables
, input [14:0] twraddr
, input [ 2:0] twren
, output [26:0] tdata_0
, output [26:0] tdata_1
, output [26:0] tdata_2
, input [1:0] command
, output idle
);
localparam wbits = $clog2(n_words);
wire [26:0] tdatao[2:0];
assign tdata_0 = tdatao[0];
assign tdata_1 = tdatao[1];
assign tdata_2 = tdatao[2];
reg [14:0] trdaddr_reg, trdaddr_next;
reg trden_reg, trden_next;
reg [wbits-1:0] count_reg, count_next;
reg state_reg, state_next;
localparam ST_IDLE = 1'b0;
localparam ST_STRM = 1'b1;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_STRM = state_reg == ST_STRM;
localparam CMD_START = 2'b01;
localparam CMD_RESET = 2'b10;
localparam CMD_ABORT = 2'b11;
wire gotCMD_ABORT = command == CMD_ABORT;
wire [14:0] trdaddr = trdaddr_reg + {{(15 - wbits) {1'b0}}, count_reg};
wire last_count = count_reg == (n_words - 1);
assign idle = inST_IDLE;
always_comb begin
trdaddr_next = trdaddr_reg;
trden_next = trden_reg;
count_next = count_reg;
state_next = state_reg;
case (state_reg)
ST_IDLE: begin
if (~trden_reg) begin
case (command)
CMD_RESET: begin
trdaddr_next = '0;
trden_next = '0;
count_next = '0;
end
CMD_START: begin
trden_next = '1;
count_next = '0;
end
default: state_next = ST_IDLE;
endcase
end else begin
state_next = ST_STRM;
count_next = count_reg + 1'b1;
end
end
ST_STRM: begin
if (last_count | gotCMD_ABORT) begin
trden_next = '0;
count_next = '0;
trdaddr_next = trdaddr_reg + n_words;
state_next = ST_IDLE;
end else begin
count_next = count_reg + 1'b1;
end
end
endcase
end
always_ff @(posedge clk or negedge ctrl_reset_n) begin
if (~ctrl_reset_n) begin
trdaddr_reg <= '0;
trden_reg <= '0;
count_reg <= '0;
state_reg <= '0;
end else begin
trdaddr_reg <= trdaddr_next;
trden_reg <= trden_next;
count_reg <= count_next;
state_reg <= state_next;
end
end
genvar TGen;
generate
for (TGen = 0; TGen < 3; TGen++) begin : TGenInst
t_ram ramins (
.aclr (~ctrl_reset_n)
, .clock (clk)
, .data (tdatai)
, .wraddress(twraddr)
, .wren (twren[TGen])
, .rden (trden_reg)
, .rdaddress(trdaddr)
, .q (tdatao[TGen])
);
end
endgenerate
endmodule
| 7.469282 |
module table_control_test ();
reg clk;
reg rstb;
wire [26:0] tdata_0, tdata_1, tdata_2;
reg [1:0] command;
initial begin
clk = 0;
rstb = 0;
command = 0;
#1 rstb = 1;
#8 command = 2'b01;
#8 command = 0;
#400 command = 2'b01;
#8 command = 0;
#104 command = 2'b11;
#8 command = 0;
#16 command = 2'b10;
#8 command = 0;
#8 command = 2'b01;
#8 command = 0;
end
always @(clk) begin
clk <= #4 ~clk;
end
table_control ictrl (
.clk (clk)
, .ctrl_reset_n(rstb)
, .tdatai ('0)
, .twraddr ('0)
, .twren ('0)
, .tdata_0 (tdata_0)
, .tdata_1 (tdata_1)
, .tdata_2 (tdata_2)
, .command (command)
);
endmodule
| 7.469282 |
module Table_Generator_Test;
//Period of the clock
localparam PERIOD = 100;
//Registers given as input to the module
reg clk = 1'b0, rst = 1'b0;
reg [3:0] r_value = 4'b0;
reg [7:0] coefficient = 7'b0;
reg is_new_coefficient = 1'b0;
//Outputs of the module
wire [64*8-1:0] value;
wire valid;
//Change clock with given period
always #(PERIOD / 2) clk = ~clk;
Table_Generator table_generator (
.clk(clk),
.rst(rst),
.is_new_coefficient(is_new_coefficient),
.r_value(r_value),
.coefficient(coefficient),
.value(value),
.valid(valid)
);
initial begin
//Reset Module
@(posedge clk) rst <= 1'b1;
@(posedge clk) rst <= 1'b0;
//DC coefficient is first element
give_bit_sequence(4'b0000, 8'b10101010);
//AC coefficients
give_bit_sequence(4'b0110, 8'b11110000);
give_bit_sequence(4'b1010, 8'b11001100);
give_bit_sequence(4'b0011, 8'b11010001);
is_new_coefficient <= 1'b0;
end
//Gives bit sequence into table generator
task give_bit_sequence(input reg [3:0] r_value_input, input reg [7:0] coefficient_input);
integer i;
begin
r_value <= r_value_input;
coefficient <= coefficient_input;
is_new_coefficient <= 1'b1;
@(posedge clk);
end
endtask
endmodule
| 8.152887 |
module TABLE_READER (
EN,
STRING,
NOW_STATE_IN,
NOW_STATE_OUT,
EN_MATCH,
INITIALIZE
);
input EN;
input INITIALIZE;
input [3:0] STRING;
input [7:0] NOW_STATE_IN;
output [7:0] NOW_STATE_OUT;
output EN_MATCH;
integer i, j, k, l;
integer m, n, o, p;
reg EN_MATCH;
reg [7:0] ADDR[0:31];
reg [7:0] NOW_STATE_OUT;
reg [7:0] NOW_STATE_OUT_TMP;
reg [7:0] RAM_CURRENT_STATE_G[0:31];
reg [3:0] RAM_CHARA[0:31];
reg [7:0] RAM_NEXT_STATE[0:31];
reg [7:0] RAM_FAILURE_STATE[0:31];
initial $readmemh("current_state_goto.txt", RAM_CURRENT_STATE_G);
initial $readmemh("chara_goto.txt", RAM_CHARA);
initial $readmemh("next_state_goto.txt", RAM_NEXT_STATE);
initial $readmemh("failure_state_failure.txt", RAM_FAILURE_STATE);
wire SEARCH_OUT;
wire INITIALIZE1;
reg FAILURE_FLUG;
reg FLUG;
reg FLUG1;
reg CHARA_EN;
reg CHARA_EN1;
//aho-corasick algorithm
function PROCESS_STRING;
input EN;
input FAILURE_FLUG;
input FLUG;
input FLUG1;
input CHARA_EN;
input CHARA_EN1;
begin
if (EN == 1) begin
FLUG = 0;
NOW_STATE_OUT_TMP = 0; //INITIALIZE
j = 0;
for (i = 0; i < 11; i = i + 1) begin
if (RAM_CURRENT_STATE_G[i] == NOW_STATE_IN) begin
ADDR[j] = i;
j = j + 1;
CHARA_EN = 1; //flug on
end
end
CHARA_EN = 1; //flug on
end
if (CHARA_EN == 1) begin
for (k = 0; k < j; k = k + 1) begin
if (RAM_CHARA[ADDR[k]] == STRING) begin
FLUG = 1;
l = k;
end
end
if (FLUG == 1) begin
NOW_STATE_OUT = RAM_NEXT_STATE[ADDR[l]];
EN_MATCH = 1;
end
if (FLUG == 0) begin
if (RAM_FAILURE_STATE[NOW_STATE_IN-1] == 0) begin
NOW_STATE_OUT_TMP = 0;
FAILURE_FLUG = 1;
end else NOW_STATE_OUT_TMP = RAM_FAILURE_STATE[NOW_STATE_IN-1];
FAILURE_FLUG = 1;
end
//failure遷移後の処理
if (FAILURE_FLUG == 1) begin
FLUG1 = 0;
n = 0;
for (m = 0; m < 11; m = m + 1) begin
if (RAM_CURRENT_STATE_G[m] == NOW_STATE_OUT_TMP) begin
ADDR[n] = m;
n = n + 1;
CHARA_EN1 = 1; //flug on
end
end
CHARA_EN1 = 1; //flug on
end
if (CHARA_EN1 == 1) begin
for (o = 0; o < n; o = o + 1) begin
if (RAM_CHARA[ADDR[o]] == STRING) begin
FLUG1 = 1;
p = o;
end
end
if (FLUG1 == 1) begin
NOW_STATE_OUT = RAM_NEXT_STATE[ADDR[p]];
EN_MATCH = 1;
end
if (FLUG1 == 0) begin
NOW_STATE_OUT = 0;
p = 7;
end
end
end
if (FAILURE_FLUG == 0) begin
NOW_STATE_OUT = NOW_STATE_OUT_TMP;
end
end
endfunction
function INITIALIZE_FUN;
input INITIALIZE;
reg CHARA_EN;
reg FLUG;
reg FAILURE_FLUG;
reg CHARA_EN1;
reg FLUG1;
reg EN_MATCH;
reg EN;
begin
//初期化
if (INITIALIZE == 1) begin
CHARA_EN = 0;
FLUG = 0;
FAILURE_FLUG = 0;
CHARA_EN1 = 0;
FLUG1 = 0;
EN_MATCH = 0;
EN = 0;
i = 0;
j = 0;
k = 0;
l = 0;
m = 0;
n = 0;
o = 0;
p = 0;
end
end
endfunction
assign SEARCH_OUT = PROCESS_STRING(EN, FAILURE_FLUG, FLUG, FLUG1, CHARA_EN, CHARA_EN1);
assign INITIALIZE1 = INITIALIZE_FUN(INITIALIZE);
endmodule
| 7.49324 |
module table_walk (
input wire in_clk, // from MMU
input wire in_en, // from MMU
input wire [13:0] in_mva, // from MMU
output wire [13:0] out_paddr, // to MMU
input wire [31:0] in_mcu_data, // from MCU
output wire out_mcu_ren, // to MCU
output wire [13:0] out_mcu_addr, // to MCU
output wire [ 1:0] out_mcu_size // to MCU
);
// Hardcoded Translation table base address
reg [13:0] r_ttb_addr = 14'd0;
reg [13:0] r_paddr;
reg r_mcu_ren;
reg [13:0] r_mcu_addr;
reg [ 1:0] r_mcu_size;
reg [13:0] r_l1d; // Level one descriptor
reg [13:0] r_l2d; // Level one descriptor
reg [ 1:0] r_stage = 2'd0;
mcu mcu (
.in_dram_ren (out_mcu_ren),
.in_dram_addr (out_mcu_addr),
.in_dram_size (out_mcu_size),
.out_mcu_data (in_mcu_data),
.in_dram_data (),
.out_dram_ren (),
.out_dram_addr(),
.out_dram_size()
);
assign out_mcu_ren = r_mcu_ren;
assign out_mcu_addr = r_mcu_addr;
assign out_mcu_size = r_mcu_size;
assign out_paddr = r_paddr;
always @(posedge in_clk) begin
if (in_en) begin
case (r_stage)
// Translation table stage
2'b00: begin
// Enable ram read for the TTB
r_mcu_ren <= 1;
r_mcu_addr <= r_ttb_addr;
r_mcu_size <= 2'b10; // word length
if (in_mcu_data) begin
r_l1d = {in_mcu_data[13:6], in_mva[13:9], 2'b00};
r_stage = 2'b01;
end
end
// Page table stage
2'b01: begin
r_mcu_ren <= 1;
r_mcu_addr <= r_l1d;
r_mcu_size <= 2'b10; // word length
if (in_mcu_data) begin
// TODO: domain/permission check
r_l2d = {in_mcu_data[13:6], in_mva[8:5], 2'b00};
r_stage = 2'b10;
end
end
// Page stage
2'b10: begin
r_mcu_ren <= 1;
r_mcu_addr <= r_l2d;
r_mcu_size <= 2'b10; // word length
if (in_mcu_data) begin
r_paddr = {in_mcu_data[13:5], in_mva[4:0]};
r_stage = 2'b11;
end
end
// Reset
2'b11: begin
r_mcu_ren <= 0;
r_mcu_addr <= 0;
r_mcu_size <= 0;
r_stage <= 0;
end
endcase
end
end
endmodule
| 6.952107 |
module top (
input clk,
io_resetn,
output io_trap,
output io_mem_axi_awvalid,
input io_mem_axi_awready,
output [31:0] io_mem_axi_awaddr,
output [ 2:0] io_mem_axi_awprot,
output io_mem_axi_wvalid,
input io_mem_axi_wready,
output [31:0] io_mem_axi_wdata,
output [ 3:0] io_mem_axi_wstrb,
input io_mem_axi_bvalid,
output io_mem_axi_bready,
output io_mem_axi_arvalid,
input io_mem_axi_arready,
output [31:0] io_mem_axi_araddr,
output [ 2:0] io_mem_axi_arprot,
input io_mem_axi_rvalid,
output io_mem_axi_rready,
input [31:0] io_mem_axi_rdata,
input [31:0] io_irq,
output [31:0] io_eoi
);
wire resetn;
wire trap;
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
wire [31:0] irq;
wire [31:0] eoi;
delay4 #(1) delay_resetn (
clk,
io_resetn,
resetn
);
delay4 #(1) delay_trap (
clk,
trap,
io_trap
);
delay4 #(1) delay_mem_axi_awvalid (
clk,
mem_axi_awvalid,
io_mem_axi_awvalid
);
delay4 #(1) delay_mem_axi_awready (
clk,
io_mem_axi_awready,
mem_axi_awready
);
delay4 #(32) delay_mem_axi_awaddr (
clk,
mem_axi_awaddr,
io_mem_axi_awaddr
);
delay4 #(3) delay_mem_axi_awprot (
clk,
mem_axi_awprot,
io_mem_axi_awprot
);
delay4 #(1) delay_mem_axi_wvalid (
clk,
mem_axi_wvalid,
io_mem_axi_wvalid
);
delay4 #(1) delay_mem_axi_wready (
clk,
io_mem_axi_wready,
mem_axi_wready
);
delay4 #(32) delay_mem_axi_wdata (
clk,
mem_axi_wdata,
io_mem_axi_wdata
);
delay4 #(4) delay_mem_axi_wstrb (
clk,
mem_axi_wstrb,
io_mem_axi_wstrb
);
delay4 #(1) delay_mem_axi_bvalid (
clk,
io_mem_axi_bvalid,
mem_axi_bvalid
);
delay4 #(1) delay_mem_axi_bready (
clk,
mem_axi_bready,
io_mem_axi_bready
);
delay4 #(1) delay_mem_axi_arvalid (
clk,
mem_axi_arvalid,
io_mem_axi_arvalid
);
delay4 #(1) delay_mem_axi_arready (
clk,
io_mem_axi_arready,
mem_axi_arready
);
delay4 #(32) delay_mem_axi_araddr (
clk,
mem_axi_araddr,
io_mem_axi_araddr
);
delay4 #(3) delay_mem_axi_arprot (
clk,
mem_axi_arprot,
io_mem_axi_arprot
);
delay4 #(1) delay_mem_axi_rvalid (
clk,
io_mem_axi_rvalid,
mem_axi_rvalid
);
delay4 #(1) delay_mem_axi_rready (
clk,
mem_axi_rready,
io_mem_axi_rready
);
delay4 #(32) delay_mem_axi_rdata (
clk,
io_mem_axi_rdata,
mem_axi_rdata
);
delay4 #(32) delay_irq (
clk,
io_irq,
irq
);
delay4 #(32) delay_eoi (
clk,
eoi,
io_eoi
);
picorv32_axi #(
.TWO_CYCLE_ALU(1)
) cpu (
.clk (clk),
.resetn (resetn),
.trap (trap),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awprot (mem_axi_awprot),
.mem_axi_wvalid (mem_axi_wvalid),
.mem_axi_wready (mem_axi_wready),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_bvalid (mem_axi_bvalid),
.mem_axi_bready (mem_axi_bready),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arprot (mem_axi_arprot),
.mem_axi_rvalid (mem_axi_rvalid),
.mem_axi_rready (mem_axi_rready),
.mem_axi_rdata (mem_axi_rdata),
.irq (irq),
.eoi (eoi)
);
endmodule
| 7.233807 |
module delay4 #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
reg [WIDTH-1:0] q1, q2, q3;
always @(posedge clk) begin
q1 <= in;
q2 <= q1;
q3 <= q2;
out <= q3;
end
endmodule
| 6.625308 |
module to instantiate in a higher level file is qc16.
//
module digitalfilter(output out, input clk, input ce, input in);
reg [5:0] taps = 6'b000000;
reg result = 0;
assign out = result;
always @(posedge clk)
begin
if(ce)
begin
taps[5] <= taps[4];
taps[4] <= taps[3];
taps[3] <= taps[2];
taps[2] <= taps[1];
taps[1] <= taps[0];
taps[0] <= in;
end
if(taps[2] & taps[3] & taps[4] & taps[5])
result <= 1;
if(~taps[2] & ~taps[3] & ~taps[4] & ~taps[5])
result <= 0;
end
endmodule
| 7.261131 |
module qc16 (
output [7:0] counth,
output [7:0] countl,
input [1:0] tach,
input clk,
input freeze,
input invphase
);
wire [15:0] counter;
wire up;
wire down;
reg [1:0] adjtach;
// Swap tach signals if invphase is true
always @(*) begin
if (invphase) begin
adjtach[0] = tach[1];
adjtach[1] = tach[0];
end else begin
adjtach[0] = tach[0];
adjtach[1] = tach[1];
end
end
graycode2 gc2 (
.clk(clk),
.freeze(freeze),
.up(up),
.down(down),
.tach(adjtach)
);
udcounter16 udc16 (
.clk(clk),
.up(up),
.down(down),
.counter(counter)
);
// Assign the 16 bit counter to the high and low bytes
assign counth = counter[15:8];
assign countl = counter[7:0];
endmodule
| 6.633667 |
module debounces push buttons switches
//The input is active low and will output high when a button is pushed
//Improvements to be made:
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
//**** This module instantiation *************************
//********************************************************
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
module tactile_sw_debouncer (
//interface from one_wire_GC_intf
input CLK, //40MHZ clk input
input RESET, //master reset
//inputs from buttons
input PB, //raw signal from switch
output DEBOUNCED, //debounced signal
output PB_DOWN, //1 for 1 clock cycle when button is pushed
output PB_UP //1 for 1 clock cycle when button is released
);
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
//**** This level wires, signals, and parms **************
//********************************************************
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
//parameters
reg debounced;
wire sync_0;
wire sync_1;
reg [16:0] counter; //a 17 bit counter will max out around 3ms
wire counter_max = &counter; //1 when the timer overflows
wire idle = ( debounced==sync_1 );
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
//**** This level logic **********************************
//********************************************************
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
assign DEBOUNCED = debounced;
assign PB_DOWN = ~idle & counter_max & ~debounced;
assign PB_UP = ~idle & counter_max & debounced;
assign sync_0 = ~PB;
assign sync_1 = sync_0;
always @( posedge CLK ) begin
if ( !RESET ) begin
//reset regs
debounced <= 0;
counter <= 0;
end
else begin
if ( idle ) begin
counter <= 0;
end
else begin
counter <= counter + 1;
if ( counter_max ) begin
debounced <= ~debounced;
end
end
end
end
endmodule
| 7.514676 |
module half_adder (
Cout,
Sum,
A,
B
);
input A, B;
output Sum, Cout;
xor xor1 (Sum, A, B);
and and1 (Cout, A, B);
endmodule
| 6.966406 |
module specialized_half_adder (
Cout,
Sum,
A,
B
);
input A, B;
output Sum, Cout;
assign Cout = A | B;
assign Sum = !(A ^ B);
endmodule
| 6.74416 |
module reduced_full_adder (
Cout,
A,
B,
Cin
);
input A, B, Cin;
output Cout;
assign Cout = (A & (B | Cin)) | (B & Cin);
endmodule
| 6.562916 |
module Tag2Len #(
parameter TAG_WIDTH = 2,
parameter LEN_WIDTH = 3
) (
input [TAG_WIDTH - 1 : 0] tag,
output reg [LEN_WIDTH - 1 : 0] len
);
always @(tag)
case (tag)
2'b00: len = 3'b000;
2'b01: len = 3'b001;
2'b10: len = 3'b010;
2'b11: len = 3'b100;
default: len = 3'b100;
endcase
endmodule
| 6.937434 |
module tagArray (
input clk,
input reset,
input [7:0] we,
input [23:0] tag,
output [23:0] tagOut0,
output [23:0] tagOut1,
output [23:0] tagOut2,
output [23:0] tagOut3,
output [23:0] tagOut4,
output [23:0] tagOut5,
output [23:0] tagOut6,
output [23:0] tagOut7
);
tagBlock t0 (
clk,
reset,
we[0],
tag,
tagOut0
);
tagBlock t1 (
clk,
reset,
we[1],
tag,
tagOut1
);
tagBlock t2 (
clk,
reset,
we[2],
tag,
tagOut2
);
tagBlock t3 (
clk,
reset,
we[3],
tag,
tagOut3
);
tagBlock t4 (
clk,
reset,
we[4],
tag,
tagOut4
);
tagBlock t5 (
clk,
reset,
we[5],
tag,
tagOut5
);
tagBlock t6 (
clk,
reset,
we[6],
tag,
tagOut6
);
tagBlock t7 (
clk,
reset,
we[7],
tag,
tagOut7
);
endmodule
| 7.079652 |
module TagCompare (
Tag1,
Tag2,
CompVal
);
input [2:1] Tag1;
input [2:1] Tag2;
output CompVal;
assign CompVal = !(Tag1[1] ^ Tag2[1]) & !(Tag1[2] ^ Tag2[2]);
endmodule
| 7.348011 |
module that is responsible for controlling the operations of the TAGE predictor, you can pipeline the operations for higher speedup
module TAGE_Controller(CLK,reset,
index_tag_enable,instruction_inc_en,table_read_en, update_enable, update_predictor_enable);
input CLK,reset;
output reg index_tag_enable; //This is to enable the calculation of Table Address
output reg instruction_inc_en; //This is to load the instruction
output reg table_read_en, update_predictor_enable, update_enable;
wire temp1;
wire temp2;
reg[3:0] state, next_state;
initial begin
end
parameter[3:0] wait_state=0, state_1 = 1, state_2 = 2, state_3 = 3, state_4 = 4, state_5 = 5,
state_6 = 6, state_7 = 7, state_8 = 8, state_9 = 9;
always @(posedge CLK)begin
if(reset==0) begin
state<=wait_state;
end
else begin
state<=next_state;
end
end
always @(state)
begin
case(state)
wait_state:
begin
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b0;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
next_state<=state_1;
end
state_1:begin
instruction_inc_en <= 1'b1;
index_tag_enable<=1'b0;
table_read_en<=1'b0;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
next_state <= state_2;
end
state_2:begin
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b1;
table_read_en<=1'b0;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
next_state <= state_3;
end
state_3:begin
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b1;
next_state <= state_4;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
end
state_4:begin //comparasion of the tags takes place
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b1;
next_state <= state_5;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
end
state_5:begin //predicition takes place
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b1;
update_predictor_enable<=1'b0;
update_enable<=1'b0;
next_state <= state_6;
end
state_6:begin
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b1;
update_predictor_enable<=1'b1;
update_enable<=1'b0;
next_state <= state_7;
end
state_7:begin
instruction_inc_en <= 1'b0;
index_tag_enable<=1'b0;
table_read_en<=1'b1;
update_predictor_enable<=1'b0;
update_enable<=1'b1;
next_state <= state_1;
end
default:begin
end
endcase
end
endmodule
| 7.34132 |
module TAGE_Table (
Clk,
wr,
rd,
index,
rdata_tag_bits,
rdata_u_bits,
rdata_c_bits,
wdata_tag_bits,
correct_prediction,
inc_u_bit,
dec_u_bit,
inc_c_bit,
dec_c_bit,
alloc,
update_enable
);
parameter IL = 10; //Index size ie number of addresses
parameter tag_len = 8; //Tag length
parameter UL = 2; //Useful length
parameter CL = 3; //Counter length
reg [tag_len-1 : 0] tag_bits[(1 << IL) - 1 : 0]; //tag table
reg [UL-1 : 0] u_bits[(1 << IL) - 1 : 0]; //Useful table
reg [CL-1 : 0] c_bits[(1 << IL) - 1 : 0]; //Counter table
reg [CL-1:0] rdata_c_bits_reg;
reg [UL-1:0] rdata_u_bits_reg;
reg [tag_len-1 : 0] rdata_tag_bits_reg;
output [tag_len-1 : 0] rdata_tag_bits;
output [UL-1 : 0] rdata_u_bits;
output [CL-1 : 0] rdata_c_bits;
input [tag_len-1 : 0] wdata_tag_bits;
input [IL - 1 : 0] index;
input Clk, rd, wr;
input correct_prediction;
input inc_u_bit, dec_u_bit;
input inc_c_bit, dec_c_bit;
input alloc;
input update_enable;
integer i;
initial begin
for (i = 0; i < (1 << IL); i = i + 1) begin
tag_bits[i] = {tag_len{1'b0}}; //initialize the bits
u_bits[i] = {UL{1'b0}};
c_bits[i] = {CL{1'b0}};
end
end
// Keep addr and write data
always @(posedge Clk) begin
//update useful bits
if (alloc == 1'b0 && inc_c_bit == 1'b1 && update_enable == 1'b1 && c_bits[index] != {CL{1'b1}})
c_bits[index] <= c_bits[index] + 1;
else if(alloc==1'b0 && dec_c_bit==1'b1 && update_enable==1'b1 && c_bits[index]!= {CL{1'b0}})
c_bits[index] <= c_bits[index] - 1;
else c_bits[index] <= c_bits[index];
//update counter bits
if (inc_u_bit == 1'b1 && update_enable == 1'b1 && u_bits[index] != {UL{1'b1}})
u_bits[index] <= u_bits[index] + 1;
else if (dec_u_bit == 1'b1 && update_enable == 1'b1 && u_bits[index] != {UL{1'b0}})
u_bits[index] <= u_bits[index] - 1;
else u_bits[index] <= u_bits[index];
//update the tags
if (alloc == 1'b1 && dec_u_bit == 1'b1 && update_enable == 1'b1)
tag_bits[index] <= wdata_tag_bits;
else tag_bits[index] <= tag_bits[index];
end
//
// Read process
// ------------
always @(posedge Clk) begin
if (rd) begin
rdata_tag_bits_reg <= tag_bits[index];
rdata_u_bits_reg <= u_bits[index];
rdata_c_bits_reg <= c_bits[index];
end else begin
rdata_tag_bits_reg <= {tag_len{1'bX}};
rdata_u_bits_reg <= {UL{1'bX}};
rdata_c_bits_reg <= {CL{1'bX}};
end
end
assign rdata_tag_bits = rdata_tag_bits_reg;
assign rdata_u_bits = rdata_u_bits_reg;
assign rdata_c_bits = rdata_c_bits_reg;
endmodule
| 6.732136 |
module tagfifo (
clock,
reset,
RB_Tag,
RB_Tag_Valid,
Rd_en,
Tag_Out,
tagFifo_full,
tagFifo_empty,
increment
);
parameter DSIZE = 5;
parameter ASIZE = 6; // ASIZE = Max_number -1
output [DSIZE-1:0] Tag_Out;
output tagFifo_full;
output tagFifo_empty;
input [DSIZE-1:0] RB_Tag;
input RB_Tag_Valid;
input clock;
input reset;
input Rd_en;
input increment;
reg [ASIZE:0] wptr;
reg [ASIZE:0] rptr;
parameter MEMDEPTH = 1 << ASIZE;
parameter MEMSIZE = 1 << ASIZE - 1;
reg [DSIZE-1:0] ex_mem[0:MEMDEPTH-1];
integer i;
always @(posedge clock or posedge reset) begin
if (reset) begin
wptr <= 6'b10_0000;
for (i = 0; i < MEMSIZE; i = i + 1) begin
ex_mem[i] <= i;
end
end else if (RB_Tag_Valid && !tagFifo_full) begin
ex_mem[wptr[ASIZE-1:0]] <= RB_Tag;
wptr <= wptr + 1;
end
end
always @(posedge clock or posedge reset) begin
if (reset) rptr <= 6'b00_0000;
else if (Rd_en && !tagFifo_empty && increment) rptr <= rptr + 1;
else rptr <= rptr;
end
assign Tag_Out = ex_mem[rptr[ASIZE-1:0]];
assign tagFifo_empty = (rptr == wptr);
assign tagFifo_full = ({~wptr[ASIZE-1], wptr[ASIZE-2:0]} == rptr);
endmodule
| 7.328335 |
module tagMux_256x1 (
output reg [11:0] out,
input [3071:0] inp,
input [7:0] select
);
integer i;
always @(inp or select) begin
for (i = 0; i < 12; i = i + 1) out[i] <= inp[select*12+i];
end
endmodule
| 7.02925 |
module tagram_1k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [5:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [1:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [47:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [63:0] wide_rd_data;
wire [47:0] rd_data = {wide_rd_data[55:32], wide_rd_data[23:0]};
wire [ 1:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {2{early_ce}};
`else
assign en = {2{wr_str}} & wr_mask | {2{rd_str}};
`endif
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({2'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({2'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({2'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({2'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
endmodule
| 6.803194 |
module tagram_2k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [0:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [23:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [31:0] wide_rd_data;
wire [23:0] rd_data = {wide_rd_data[23:0]};
wire [ 0:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {1{early_ce}};
`else
assign en = {1{wr_str}} & wr_mask | {1{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
endmodule
| 7.235402 |
module tagram_2k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [1:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [47:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [63:0] wide_rd_data;
wire [47:0] rd_data = {wide_rd_data[55:32], wide_rd_data[23:0]};
wire [ 1:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {2{early_ce}};
`else
assign en = {2{wr_str}} & wr_mask | {2{rd_str}};
`endif
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
endmodule
| 6.847755 |
module tagram_2k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [2:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [71:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [95:0] wide_rd_data;
wire [71:0] rd_data = {wide_rd_data[87:64], wide_rd_data[55:32], wide_rd_data[23:0]};
wire [ 2:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {3{early_ce}};
`else
assign en = {3{wr_str}} & wr_mask | {3{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
// 3 policy bits
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
// 3 dirty bits
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
RAMB4K_S16 ram__tag_inst4 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[79:64])
);
RAMB4K_S16 ram__tag_inst5 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[95:80])
);
endmodule
| 7.38594 |
module tagram_2k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [3:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [95:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [127:0] wide_rd_data;
wire [95:0] rd_data = {
wide_rd_data[119:96], wide_rd_data[87:64], wide_rd_data[55:32], wide_rd_data[23:0]
};
wire [3:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {4{early_ce}};
`else
assign en = {4{wr_str}} & wr_mask | {4{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
RAMB4K_S16 ram__tag_inst4 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[79:64])
);
RAMB4K_S16 ram__tag_inst5 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[95:80])
);
RAMB4K_S16 ram__tag_inst6 (
.WE (wr_str && wr_mask[3]),
.EN (en[3]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[111:96])
);
RAMB4K_S16 ram__tag_inst7 (
.WE (wr_str && wr_mask[3]),
.EN (en[3]),
.RST (1'b0),
.CLK (clk),
.ADDR({1'b0, line_idx}),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[127:112])
);
endmodule
| 6.87932 |
module tagram_4k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [0:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [23:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [31:0] wide_rd_data;
wire [23:0] rd_data = {wide_rd_data[23:0]};
wire [ 0:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {1{early_ce}};
`else
assign en = {1{wr_str}} & wr_mask | {1{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
endmodule
| 7.584683 |
module tagram_4k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [1:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [47:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [63:0] wide_rd_data;
wire [47:0] rd_data = {wide_rd_data[55:32], wide_rd_data[23:0]};
wire [ 1:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {2{early_ce}};
`else
assign en = {2{wr_str}} & wr_mask | {2{rd_str}};
`endif
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
endmodule
| 7.168301 |
module tagram_4k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [2:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [71:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [95:0] wide_rd_data;
wire [71:0] rd_data = {wide_rd_data[87:64], wide_rd_data[55:32], wide_rd_data[23:0]};
wire [ 2:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {3{early_ce}};
`else
assign en = {3{wr_str}} & wr_mask | {3{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
// 3 policy bits
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
// 3 dirty bits
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
RAMB4K_S16 ram__tag_inst4 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[79:64])
);
RAMB4K_S16 ram__tag_inst5 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[95:80])
);
endmodule
| 7.543315 |
module tagram_4k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Strobe
input [3:0] wr_mask; // Write Mask
input [23:0] wr_data; // Data for Tag Write
input [0:0] bist_to;
input early_ce;
input greset;
/* Outputs */
output [95:0] rd_data; // output from read
output [0:0] bist_from;
output hci;
assign hci = 1'b0;
assign bist_from[0] = 1'b0;
wire [31:0] wide_wr_data = {8'b0, wr_data};
wire [127:0] wide_rd_data;
wire [95:0] rd_data = {
wide_rd_data[119:96], wide_rd_data[87:64], wide_rd_data[55:32], wide_rd_data[23:0]
};
wire [3:0] en;
`ifdef M14K_EARLY_RAM_CE
assign en = {4{early_ce}};
`else
assign en = {4{wr_str}} & wr_mask | {4{rd_str}};
`endif
// Each 2 RAM4K_S16 represents one cache way, that is 256 (only 128 are used) lines of 32 bits (only 24 are used) [v2.0]
// All set ways must be read simultaneously [v2.0]
// 256 x 16 (We only need 128 x 16 but this is what Xilinx got)
RAMB4K_S16 ram__tag_inst0 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[15:0])
);
RAMB4K_S16 ram__tag_inst1 (
.WE (wr_str && wr_mask[0]),
.EN (en[0]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[31:16])
);
RAMB4K_S16 ram__tag_inst2 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[47:32])
);
RAMB4K_S16 ram__tag_inst3 (
.WE (wr_str && wr_mask[1]),
.EN (en[1]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[63:48])
);
RAMB4K_S16 ram__tag_inst4 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[79:64])
);
RAMB4K_S16 ram__tag_inst5 (
.WE (wr_str && wr_mask[2]),
.EN (en[2]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[95:80])
);
RAMB4K_S16 ram__tag_inst6 (
.WE (wr_str && wr_mask[3]),
.EN (en[3]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[15:0]),
.DO (wide_rd_data[111:96])
);
RAMB4K_S16 ram__tag_inst7 (
.WE (wr_str && wr_mask[3]),
.EN (en[3]),
.RST (1'b0),
.CLK (clk),
.ADDR(line_idx),
.DI (wide_wr_data[31:16]),
.DO (wide_rd_data[127:112])
);
endmodule
| 7.017084 |
module tagreg (
input clk,
input rst,
input [1:0] index,
output [9:0] tagbits
);
// 4 10bit tag registers
reg [9:0] tagreg[0:3];
always @(posedge clk) begin
if (rst) begin
tagreg[0] <= 0;
tagreg[1] <= 0;
tagreg[2] <= 0;
tagreg[3] <= 0;
end
end
assign tagbits = tagreg[index];
endmodule
| 7.520728 |
module tags #(
parameter num_bits = 32,
parameter num_cells = 100
) (
match_lines,
set,
select_first,
tag_wires,
some_none,
CLK
);
input wire [num_cells - 1:0] match_lines;
input wire select_first;
input wire set;
input wire [num_cells - 1:0] tag_wires;
input CLK;
output reg [num_cells - 1:0] some_none;
wire [num_cells - 1:0] temp;
reg [num_cells - 1:0] tag_regs;
integer j, k;
always @(posedge CLK) begin
if (set) tag_regs = '1;
else if (match_lines[0]) tag_regs[0] = 0;
some_none[0] = tag_regs[0];
for (j = 1; j < num_cells; j = j + 1) begin : random
some_none[j] = some_none[j-1] || tag_regs[j];
if ((some_none[j-1] && select_first) || match_lines[j]) begin
tag_regs[j] <= 0;
end
end
end
assign tag_wires = tag_regs;
endmodule
| 7.078633 |
module tag_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(tag_width_lp)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter block_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)+`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input ready_o
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_o
, input yumi_i
, input [data_width_p-1:0] data_o
, input [id_width_p-1:0] id_o
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
`declare_bsg_cache_non_blocking_tag_info_s(tag_width_lp);
bsg_cache_non_blocking_tag_info_s [ways_p-1:0][sets_p-1:0] shadow_tag;
logic [data_width_p-1:0] result [*]; // indexed by id.
wire [lg_ways_lp-1:0] addr_way = cache_pkt.addr[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
wire [lg_sets_lp-1:0] addr_index = cache_pkt.addr[block_offset_width_lp+:lg_sets_lp];
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < ways_p; i++)
for (integer j = 0; j < ways_p; j++)
shadow_tag[i][j] <= '0;
end
else begin
if (v_i & ready_o & en_i) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
shadow_tag[addr_way][addr_index].tag <= cache_pkt.data[0+:tag_width_lp];
shadow_tag[addr_way][addr_index].valid <= cache_pkt.data[data_width_p-1];
shadow_tag[addr_way][addr_index].lock <= cache_pkt.data[data_width_p-2];
end
TAGLV: begin
result[cache_pkt.id] = '0;
result[cache_pkt.id][1] = shadow_tag[addr_way][addr_index].lock;
result[cache_pkt.id][0] = shadow_tag[addr_way][addr_index].valid;
end
TAGLA: begin
result[cache_pkt.id] = {
shadow_tag[addr_way][addr_index].tag,
addr_index,
{block_offset_width_lp{1'b0}}
};
end
endcase
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule
| 7.322604 |
module tag_denetleyici (
input wire clk_i,
input wire rst_i,
// Port 0: W
input wire wen_i,
input wire [8:0] wadr_i,
// Port 0: R
output wire [8:0] data0_o,
input wire [8:0] radr0_i,
// Port 1: R
output wire [8:0] data1_o,
input wire [8:0] radr1_i,
// RAM256_T0
output wire we0_o,
output wire [7:0] adr0_o,
input wire [7:0] datao0_i,
// RAM256_T1
output wire we1_o,
output wire [7:0] adr1_o,
input wire [7:0] datao1_i
);
reg [511:0] RAM;
wire [ 7:0] tage;
wire [ 7:0] tago;
wire [ 7:0] tag_addre = wen_i ? wadr_i[8:1] : radr0_i[8:1];
wire [ 7:0] tag_addro = wen_i ? wadr_i[8:1] : radr1_i[8:1];
always @(posedge clk_i) begin
if (rst_i) RAM <= 0;
else if (wen_i) RAM[wadr_i] <= 1'b1;
end
// Gerekli kosullar matematiksel olarak bulunmus olup gerekli ispat en altta gosterilmistir.
wire [7:0] tag0 = (~radr0_i[0]) ? tage : tago;
wire [7:0] tag1 = (((~radr0_i[0]) & (radr0_i == radr1_i)) || (( radr0_i[0]) & (radr0_i != radr1_i))) ? tage : tago;
assign data0_o = {RAM[radr0_i], tag0};
assign data1_o = {RAM[radr1_i], tag1};
wire wee = ~wadr_i[0] ? wen_i : 1'b0;
wire weo = wadr_i[0] ? wen_i : 1'b0;
// even
assign we0_o = wee;
assign adr0_o = tag_addre;
assign tage = datao0_i;
// odd
assign we1_o = weo;
assign adr1_o = tag_addro;
assign tago = datao1_i;
endmodule
| 6.735902 |
module tag_generator (
input wire clk,
input wire reset,
input wire branchvalid1,
input wire branchvalid2,
input wire prmiss,
input wire prsuccess,
input wire enable,
input wire [`SPECTAG_LEN-1:0] tagregfix,
output wire [`SPECTAG_LEN-1:0] sptag1,
output wire [`SPECTAG_LEN-1:0] sptag2,
output wire speculative1,
output wire speculative2,
output wire attachable,
output reg [`SPECTAG_LEN-1:0] tagreg
);
// reg [`SPECTAG_LEN-1:0] tagreg;
reg [`BRDEPTH_LEN-1:0] brdepth;
assign sptag1 = (branchvalid1) ? {tagreg[`SPECTAG_LEN-2:0], tagreg[`SPECTAG_LEN-1]} : tagreg;
assign sptag2 = (branchvalid2) ? {sptag1[`SPECTAG_LEN-2:0], sptag1[`SPECTAG_LEN-1]} : sptag1;
assign speculative1 = (brdepth != 0) ? 1'b1 : 1'b0;
assign speculative2 = ((brdepth != 0) || branchvalid1) ? 1'b1 : 1'b0;
assign attachable = (brdepth + branchvalid1 + branchvalid2)
> (`BRANCH_ENT_NUM + prsuccess) ? 1'b0 : 1'b1;
always @(posedge clk) begin
if (reset) begin
tagreg <= `SPECTAG_LEN'b1;
brdepth <= `BRDEPTH_LEN'b0;
end else begin
tagreg <= prmiss ? tagregfix : ~enable ? tagreg : sptag2;
brdepth <= prmiss ? `BRDEPTH_LEN'b0 :
~enable ? brdepth - prsuccess :
brdepth + branchvalid1 + branchvalid2 - prsuccess;
end
end
endmodule
| 7.233921 |
module tag_ram (
input wire clk,
input wire rst_n,
input wire cache_en,
// from decoder
input wire [ `TAG_WIDTH - 1 : 0] tag, // from decoder
input wire [`INDEX_WIDTH - 1 : 0] index, // from decoder
output reg [ `WAY_NUM - 1 : 0] hit_en,
// from reg1: save the replace tag
input wire read_main_memory_en,
// to data_ram
output wire way0_replace_en,
output wire way1_replace_en,
output wire way2_replace_en,
output wire way3_replace_en
);
reg [`LINE_NUM - 1 : 0] way0_value; // way0_value[0] -> way0 line0 value
reg [`LINE_NUM - 1 : 0] way1_value;
reg [`LINE_NUM - 1 : 0] way2_value;
reg [`LINE_NUM - 1 : 0] way3_value;
reg [`TAG_WIDTH - 1 : 0] way0_tag_ram[`LINE_NUM - 1 : 0];
reg [`TAG_WIDTH - 1 : 0] way1_tag_ram[`LINE_NUM - 1 : 0];
reg [`TAG_WIDTH - 1 : 0] way2_tag_ram[`LINE_NUM - 1 : 0];
reg [`TAG_WIDTH - 1 : 0] way3_tag_ram[`LINE_NUM - 1 : 0];
wire [$clog2(`WAY_NUM):0] replaced_way;
LRU u_LRU (
.clk (clk),
.rst_n (rst_n),
.cache_en (cache_en),
.hit_en (hit_en),
.index (index),
.way0_value (way0_value),
.way1_value (way1_value),
.way2_value (way2_value),
.way3_value (way3_value),
.way0_replace_en(way0_replace_en),
.way1_replace_en(way1_replace_en),
.way2_replace_en(way2_replace_en),
.way3_replace_en(way3_replace_en),
.replaced_way (replaced_way)
);
integer j;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (j = 0; j < `LINE_NUM; j = j + 1) begin
way0_value[j] <= 0;
way1_value[j] <= 0;
way2_value[j] <= 0;
way3_value[j] <= 0;
way0_tag_ram[j] <= 0;
way1_tag_ram[j] <= 0;
way2_tag_ram[j] <= 0;
way3_tag_ram[j] <= 0;
end
end else if (read_main_memory_en == 1) begin
case (replaced_way)
`REPLACE_WAY0: begin
way0_tag_ram[index] <= tag;
way0_value[index] <= 1;
end
`REPLACE_WAY1: begin
way1_tag_ram[index] <= tag;
way1_value[index] <= 1;
end
`REPLACE_WAY2: begin
way2_tag_ram[index] <= tag;
way2_value[index] <= 1;
end
`REPLACE_WAY3: begin
way3_tag_ram[index] <= tag;
way3_value[index] <= 1;
end
// replaced_way = NO_REPLACE_WAY, do nothing
endcase
end
end
always @(*) begin
if ((way0_tag_ram[index] == tag) && (way0_value[index] == 1)) begin
hit_en[0] <= 1;
end else begin
hit_en[0] <= 0;
end
if ((way1_tag_ram[index] == tag) && (way1_value[index] == 1)) begin
hit_en[1] <= 1;
end else begin
hit_en[1] <= 0;
end
if ((way2_tag_ram[index] == tag) && (way2_value[index] == 1)) begin
hit_en[2] <= 1;
end else begin
hit_en[2] <= 0;
end
if ((way3_tag_ram[index] == tag) && (way3_value[index] == 1)) begin
hit_en[3] <= 1;
end else begin
hit_en[3] <= 0;
end
end
endmodule
| 6.978067 |
module Tail (
input [2:0] io_a,
output io_b
);
assign io_b = io_a[0];
endmodule
| 7.007784 |
module TailLight (
input reset,
left,
right,
clk,
output LC,
LB,
LA,
RA,
RB,
RC
);
parameter ST_IDLE = 3'b000;
parameter ST_L1 = 3'b001;
parameter ST_L2 = 3'b010;
parameter ST_L3 = 3'b011;
parameter ST_R1 = 3'b100;
parameter ST_R2 = 3'b101;
parameter ST_R3 = 3'b110;
reg [2:0] state, next_state;
always @(posedge clk)
if (reset) state <= ST_IDLE;
else state <= next_state;
always @* begin
case (state)
ST_IDLE: begin
if (left && ~right) next_state = ST_L1;
else if (~left && right) next_state = ST_R1;
else next_state = ST_IDLE;
end
ST_L1: next_state = ST_L2;
ST_L2: next_state = ST_L3;
ST_R1: next_state = ST_R2;
ST_R2: next_state = ST_R3;
default: next_state = ST_IDLE;
endcase
if (left && right) next_state = ST_IDLE;
end
assign LA = state == ST_L1 || state == ST_L2 || state == ST_L3;
assign LB = state == ST_L2 || state == ST_L3;
assign LC = state == ST_L3;
assign RA = state == ST_R1 || state == ST_R2 || state == ST_R3;
assign RB = state == ST_R2 || state == ST_R3;
assign RC = state == ST_R3;
endmodule
| 7.423801 |
module taming_timer (
input clk_in, // 10Mhz clk in, 100ns clk
input clk_correct, // Taming Signal
input [31:0] epoch_set_dat,
input epoch_set,
input reset,
output reg [31:0] epoch,
output reg [23:0] ns_cnt,
output reg lock
);
//reg [23:0]ns_cnt;
parameter MAX_SEC = 110;
parameter MIN_SEC = 90;
parameter DELTA = 20;
parameter HALF_DELTA = 10;
always @(posedge clk_in or posedge clk_correct or posedge reset)
if (reset) begin
epoch <= 32'b0;
ns_cnt <= 24'b0;
lock <= 1'b0;
end else if (clk_correct) begin
if (ns_cnt > MIN_SEC && ns_cnt < MAX_SEC) begin
ns_cnt <= 0;
lock <= 1;
epoch <= epoch + 32'b1;
end else if (ns_cnt < DELTA) begin
epoch <= epoch;
lock <= 1;
end else begin
epoch <= epoch + 10;
lock <= 0;
ns_cnt <= ns_cnt + HALF_DELTA;
end
end else if (clk_in) begin
ns_cnt <= ns_cnt + 1;
if (ns_cnt >= MAX_SEC && lock == 0) begin
lock <= 1'b0;
ns_cnt <= HALF_DELTA;
epoch <= epoch + 1;
end
end
endmodule
| 8.149963 |
module taming_timer_testbench;
parameter delay = 500;
parameter second = 64'd100000;
reg clk_in;
reg tame_corection;
reg reset;
wire [31:0] epoch_out;
wire lock_out;
wire [23:0] ns_out;
taming_timer DUT (
clk_in,
tame_corection,
32'b0,
0,
reset,
epoch_out,
ns_out,
lock_out
);
initial begin
reset = 1;
#(2000) reset = 0;
clk_in = 0;
tame_corection = 0;
end
always #(delay) clk_in = ~clk_in;
always begin
#(second) tame_corection = ~tame_corection;
#(100) tame_corection = ~tame_corection;
end
endmodule
| 7.246814 |
module tan (
input [31:0] sayi1,
input clk,
input rst,
output reg [63:0] sonuc,
output reg hazir,
output reg gecerli
);
localparam PI = 3.14159265;
reg [31:0] yenisayi1;
always @(posedge clk) begin
yenisayi1 = sayi1;
if (sayi1 < 0) begin
yenisayi1 = -sayi1;
end
//negatif degerlerden kurtulmak icin
if ((sayi1 * (10 ** 8)) > (314159265 / 2)) begin
yenisayi1 = ((sayi1 * (10 ** 8)) % (314159265 / 2)) / (10 ** 8);
end
//tanjantin araligini korumak icin
sonuc = ((yenisayi1**13)*21844*(32'b10000000000000000000000000000000)/6081075 + (yenisayi1**11)*1382*(32'b10000000000000000000000000000000)/155925 + (yenisayi1**9)*62*(32'b10000000000000000000000000000000)/2835 + (yenisayi1**7)*17*(32'b10000000000000000000000000000000)/315 + (yenisayi1**5)*2*(32'b10000000000000000000000000000000)/15 + (yenisayi1**3)*(32'b10000000000000000000000000000000)/3 + yenisayi1*(32'b10000000000000000000000000000000));
//yukardaki satir tamamen maclaurin serisi
hazir = 1;
gecerli = 1;
if (rst) begin
sonuc = 0;
hazir = 0;
gecerli = 1;
end
end
endmodule
| 7.847415 |
module EXT_RAM (
input wire [31:0] d2,
addr1,
addr2,
input wire clk,
we,
reset,
output wire [31:0] q1,
q2
);
reg [31:0] md1, md2;
wire [31:0] din2;
wire we2;
wire [9:0] ad1, ad2;
reg [31:0] mem[0:1023];
assign q1 = md1;
assign q2 = md2;
assign we2 = we;
assign din2 = d2;
assign ad1 = addr1[11:2];
assign ad2 = addr2[11:2];
always @(posedge clk) begin
md1 <= mem[ad1];
md2 <= mem[ad2];
if (we2) begin
mem[ad2] <= din2;
end
end
//初期化
initial begin
$readmemh(
"mem.hex",
mem); /* mem.hexを入れ替えて、様々なサンプルをご利用ください。 */
end
endmodule
| 6.84605 |
module bus_master (
input wire [31:0] dataFp1,
dataFp2,
addrbus,
dataFromCpu,
output wire [31:0] data2cpu,
data2pri,
input wire [1:0] bw,
input wire we,
output wire cs1,
cs2
);
// addr : 32'h0000_0000 - 32'h0000_0fff as RAM
// addr : 32'h0001_0000 - 32'h0001_001f as Super_IO
reg [31:0] data_choice;
wire [7:0] qq2[3:0];
wire [7:0] dd2[3:0];
wire chk1 = (addrbus[31:12] == 20'd0); // メインメモリ
wire chk2 = (addrbus[31:5] == 27'h000_0800); // 複合ペリフェラル
assign {qq2[3], qq2[2], qq2[1], qq2[0]} = data_choice;
assign data2cpu[7:0] = qq2[addrbus[1:0]];
assign data2cpu[15:8] = addrbus[1] ? qq2[3] : qq2[1];
assign data2cpu[31:16] = {qq2[3], qq2[2]};
assign {dd2[3], dd2[2], dd2[1], dd2[0]} = dataFromCpu;
assign data2pri = wdata(
bw, addrbus[1:0], dd2[0], dd2[1], dd2[2], dd2[3], qq2[0], qq2[1], qq2[2], qq2[3]
);
function [31:0] wdata(input [1:0] acc_width, addr10, input [7:0] idd0, idd1, idd2, idd3, iqq0,
iqq1, iqq2, iqq3);
case (acc_width)
2'd0: begin
case (addr10)
2'd0: wdata = {iqq3, iqq2, iqq1, idd0};
2'd1: wdata = {iqq3, iqq2, idd0, iqq0};
2'd2: wdata = {iqq3, idd0, iqq1, iqq0};
2'd3: wdata = {idd0, iqq2, iqq1, iqq0};
endcase
end
2'd1: begin
case (addr10[1])
1'd0: wdata = {iqq3, iqq2, idd1, idd0};
1'd1: wdata = {idd1, idd0, iqq1, iqq0};
endcase
end
2'd2: wdata = {idd3, idd2, idd1, idd0};
2'd3: wdata = {iqq3, iqq2, iqq1, iqq0};
endcase
endfunction
assign cs1 = we & chk1;
assign cs2 = we & chk2;
always @(*) begin
case ({
chk2, chk1
})
2'b01: data_choice <= dataFp1;
2'b10: data_choice <= dataFp2;
default: data_choice <= 32'dx;
endcase
end
endmodule
| 7.893726 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
input [15:0] io_gpio_read,
output [15:0] io_gpio_write,
output [15:0] io_gpio_writeEnable,
output [15:0] io_value,
input axiClk,
input resetCtrl_axiReset
);
wire [15:0] io_gpio_read_buffercc_io_dataOut;
wire ctrl_askWrite;
wire ctrl_askRead;
wire ctrl_doWrite;
wire ctrl_doRead;
reg [15:0] io_gpio_write_driver;
reg [15:0] io_gpio_writeEnable_driver;
BufferCC_9 io_gpio_read_buffercc (
.io_dataIn (io_gpio_read[15:0]), //i
.io_dataOut (io_gpio_read_buffercc_io_dataOut[15:0]), //o
.axiClk (axiClk), //i
.resetCtrl_axiReset(resetCtrl_axiReset) //i
);
assign io_value = io_gpio_read_buffercc_io_dataOut;
assign io_apb_PREADY = 1'b1;
always @(*) begin
io_apb_PRDATA = 32'h0;
case (io_apb_PADDR)
4'b0000: begin
io_apb_PRDATA[15 : 0] = io_value;
end
4'b0100: begin
io_apb_PRDATA[15 : 0] = io_gpio_write_driver;
end
4'b1000: begin
io_apb_PRDATA[15 : 0] = io_gpio_writeEnable_driver;
end
default: begin
end
endcase
end
assign io_apb_PSLVERROR = 1'b0;
assign ctrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign ctrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (!io_apb_PWRITE));
assign ctrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE);
assign ctrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (!io_apb_PWRITE));
assign io_gpio_write = io_gpio_write_driver;
assign io_gpio_writeEnable = io_gpio_writeEnable_driver;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
io_gpio_writeEnable_driver <= 16'h0;
end else begin
case (io_apb_PADDR)
4'b1000: begin
if (ctrl_doWrite) begin
io_gpio_writeEnable_driver <= io_apb_PWDATA[15 : 0];
end
end
default: begin
end
endcase
end
end
always @(posedge axiClk) begin
case (io_apb_PADDR)
4'b0100: begin
if (ctrl_doWrite) begin
io_gpio_write_driver <= io_apb_PWDATA[15 : 0];
end
end
default: begin
end
endcase
end
endmodule
| 6.706229 |
module BufferCC_10 (
input io_dataIn,
output io_dataOut,
input clk,
input reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.968109 |
module StreamArbiter_2 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
input io_inputs_0_payload_write,
output io_output_valid,
input io_output_ready,
output [19:0] io_output_payload_addr,
output [ 3:0] io_output_payload_id,
output [ 7:0] io_output_payload_len,
output [ 2:0] io_output_payload_size,
output [ 1:0] io_output_payload_burst,
output io_output_payload_write,
output [ 0:0] io_chosenOH,
input axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz__zz_maskProposal_0_2;
wire [1:0] _zz__zz_maskProposal_0_2_1;
wire [0:0] _zz__zz_maskProposal_0_2_2;
wire [0:0] _zz_maskProposal_0_3;
reg locked;
wire maskProposal_0;
reg maskLocked_0;
wire maskRouted_0;
wire [0:0] _zz_maskProposal_0;
wire [1:0] _zz_maskProposal_0_1;
wire [1:0] _zz_maskProposal_0_2;
wire io_output_fire;
assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
assign _zz__zz_maskProposal_0_2_2 = maskLocked_0;
assign _zz__zz_maskProposal_0_2_1 = {1'd0, _zz__zz_maskProposal_0_2_2};
assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[1 : 1] | _zz_maskProposal_0_2[0 : 0]);
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign _zz_maskProposal_0 = io_inputs_0_valid;
assign _zz_maskProposal_0_1 = {_zz_maskProposal_0, _zz_maskProposal_0};
assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~_zz__zz_maskProposal_0_2));
assign maskProposal_0 = _zz_maskProposal_0_3[0];
assign io_output_fire = (io_output_valid && io_output_ready);
assign io_output_valid = (io_inputs_0_valid && maskRouted_0);
assign io_output_payload_addr = io_inputs_0_payload_addr;
assign io_output_payload_id = io_inputs_0_payload_id;
assign io_output_payload_len = io_inputs_0_payload_len;
assign io_output_payload_size = io_inputs_0_payload_size;
assign io_output_payload_burst = io_inputs_0_payload_burst;
assign io_output_payload_write = io_inputs_0_payload_write;
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_chosenOH = maskRouted_0;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
locked <= 1'b0;
maskLocked_0 <= 1'b1;
end else begin
if (io_output_valid) begin
maskLocked_0 <= maskRouted_0;
end
if (io_output_valid) begin
locked <= 1'b1;
end
if (io_output_fire) begin
locked <= 1'b0;
end
end
end
endmodule
| 6.929245 |
module StreamFifoLowLatency_1 (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz_pushPtr_valueNext;
wire [0:0] _zz_pushPtr_valueNext_1;
wire [1:0] _zz_popPtr_valueNext;
wire [0:0] _zz_popPtr_valueNext_1;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [1:0] pushPtr_valueNext;
reg [1:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [1:0] popPtr_valueNext;
reg [1:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire when_Stream_l1011;
wire when_Stream_l1024;
wire [1:0] ptrDif;
assign _zz_pushPtr_valueNext_1 = pushPtr_willIncrement;
assign _zz_pushPtr_valueNext = {1'd0, _zz_pushPtr_valueNext_1};
assign _zz_popPtr_valueNext_1 = popPtr_willIncrement;
assign _zz_popPtr_valueNext = {1'd0, _zz_popPtr_valueNext_1};
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == 2'b11);
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
pushPtr_valueNext = (pushPtr_value + _zz_pushPtr_valueNext);
if (pushPtr_willClear) begin
pushPtr_valueNext = 2'b00;
end
end
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == 2'b11);
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @(*) begin
popPtr_valueNext = (popPtr_value + _zz_popPtr_valueNext);
if (popPtr_willClear) begin
popPtr_valueNext = 2'b00;
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
assign when_Stream_l1011 = (!empty);
always @(*) begin
if (when_Stream_l1011) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign when_Stream_l1024 = (pushing != popping);
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch), ptrDif};
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
pushPtr_value <= 2'b00;
popPtr_value <= 2'b00;
risingOccupancy <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
if (when_Stream_l1024) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
| 7.046487 |
module Axi4ReadOnlyErrorSlave_1 (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 2:0] io_axi_ar_payload_size,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output io_axi_r_payload_last,
input axiClk,
input resetCtrl_axiReset
);
reg sendRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_ar_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_ar_ready = (!sendRsp);
assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready);
assign io_axi_r_valid = sendRsp;
assign io_axi_r_payload_last = remainingZero;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
sendRsp <= 1'b0;
end else begin
if (io_axi_ar_fire) begin
sendRsp <= 1'b1;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendRsp <= 1'b0;
end
end
end
end
end
always @(posedge axiClk) begin
if (io_axi_ar_fire) begin
remaining <= io_axi_ar_payload_len;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 7.858199 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
input io_axi_arw_payload_write,
input io_axi_w_valid,
output io_axi_w_ready,
input [31:0] io_axi_w_payload_data,
input [ 3:0] io_axi_w_payload_strb,
input io_axi_w_payload_last,
output io_axi_b_valid,
input io_axi_b_ready,
output [ 1:0] io_axi_b_payload_resp,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input axiClk,
input resetCtrl_axiReset
);
reg consumeData;
reg sendReadRsp;
reg sendWriteRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_arw_fire;
wire io_axi_w_fire;
wire when_Axi4ErrorSlave_l92;
wire io_axi_b_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_arw_ready = (!((consumeData || sendWriteRsp) || sendReadRsp));
assign io_axi_arw_fire = (io_axi_arw_valid && io_axi_arw_ready);
assign io_axi_w_ready = consumeData;
assign io_axi_w_fire = (io_axi_w_valid && io_axi_w_ready);
assign when_Axi4ErrorSlave_l92 = (io_axi_w_fire && io_axi_w_payload_last);
assign io_axi_b_valid = sendWriteRsp;
assign io_axi_b_payload_resp = 2'b11;
assign io_axi_b_fire = (io_axi_b_valid && io_axi_b_ready);
assign io_axi_r_valid = sendReadRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
consumeData <= 1'b0;
sendReadRsp <= 1'b0;
sendWriteRsp <= 1'b0;
end else begin
if (io_axi_arw_fire) begin
consumeData <= io_axi_arw_payload_write;
sendReadRsp <= (!io_axi_arw_payload_write);
end
if (when_Axi4ErrorSlave_l92) begin
consumeData <= 1'b0;
sendWriteRsp <= 1'b1;
end
if (io_axi_b_fire) begin
sendWriteRsp <= 1'b0;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendReadRsp <= 1'b0;
end
end
end
end
end
always @(posedge axiClk) begin
if (io_axi_arw_fire) begin
remaining <= io_axi_arw_payload_len;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input axiClk,
input resetCtrl_axiReset
);
reg sendRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_ar_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_ar_ready = (!sendRsp);
assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready);
assign io_axi_r_valid = sendRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
sendRsp <= 1'b0;
end else begin
if (io_axi_ar_fire) begin
sendRsp <= 1'b1;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendRsp <= 1'b0;
end
end
end
end
end
always @(posedge axiClk) begin
if (io_axi_ar_fire) begin
remaining <= io_axi_ar_payload_len;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 7.858199 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input axiClk,
input resetCtrl_systemReset
);
wire inputArea_target_buffercc_io_dataOut;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_m2sPipe_valid;
reg outputArea_flow_m2sPipe_payload_last;
reg [0:0] outputArea_flow_m2sPipe_payload_fragment;
BufferCC_7 inputArea_target_buffercc (
.io_dataIn (inputArea_target), //i
.io_dataOut (inputArea_target_buffercc_io_dataOut), //o
.axiClk (axiClk), //i
.resetCtrl_systemReset(resetCtrl_systemReset) //i
);
assign outputArea_target = inputArea_target_buffercc_io_dataOut;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_m2sPipe_valid;
assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last;
assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment;
always @(posedge io_jtag_tck) begin
if (io_input_valid) begin
inputArea_target <= (!inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @(posedge axiClk) begin
outputArea_hit <= outputArea_target;
if (outputArea_flow_valid) begin
outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last;
outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment;
end
end
always @(posedge axiClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
outputArea_flow_m2sPipe_valid <= 1'b0;
end else begin
outputArea_flow_m2sPipe_valid <= outputArea_flow_valid;
end
end
endmodule
| 7.790686 |
module InterruptCtrl (
input [3:0] io_inputs,
input [3:0] io_clears,
input [3:0] io_masks,
output [3:0] io_pendings,
input axiClk,
input resetCtrl_axiReset
);
reg [3:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
pendings <= 4'b0000;
end else begin
pendings <= ((pendings & (~io_clears)) | io_inputs);
end
end
endmodule
| 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input axiClk,
input resetCtrl_axiReset
);
wire [31:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [31:0] counter;
wire limitHit;
reg inhibitFull;
assign _zz_counter_1 = (!limitHit);
assign _zz_counter = {31'd0, _zz_counter_1};
assign limitHit = (counter == io_limit);
assign io_full = ((limitHit && io_tick) && (!inhibitFull));
assign io_value = counter;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
inhibitFull <= 1'b0;
end else begin
if (io_tick) begin
inhibitFull <= limitHit;
end
if (io_clear) begin
inhibitFull <= 1'b0;
end
end
end
always @(posedge axiClk) begin
if (io_tick) begin
counter <= (counter + _zz_counter);
end
if (io_clear) begin
counter <= 32'h0;
end
end
endmodule
| 6.729771 |
module BufferCC_8 (
input io_dataIn,
output io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.740109 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.82712 |
module BufferCC_4 (
input io_dataIn,
output io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk or posedge resetCtrl_vgaReset) begin
if (resetCtrl_vgaReset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.634474 |
module BufferCC_3 (
input [6:0] io_dataIn,
output [6:0] io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg [6:0] buffers_0;
(* async_reg = "true" *)reg [6:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.792516 |
module BufferCC (
input [9:0] io_dataIn,
output [9:0] io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg [9:0] buffers_0;
(* async_reg = "true" *)reg [9:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk or posedge resetCtrl_vgaReset) begin
if (resetCtrl_vgaReset) begin
buffers_0 <= 10'h0;
buffers_1 <= 10'h0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
module tang_nano_top (
input wire XTAL_IN,
input wire USER_BTN_A,
input wire USER_BTN_B,
//output reg LCD_BL,
output reg LCD_CLK,
output reg LCD_DE,
output reg LCD_HSYNC,
output reg LCD_VSYNC,
output reg [4:0] LCD_R,
output reg [5:0] LCD_G,
output reg [4:0] LCD_B,
//output reg FPGA_TX,
//input wire FPGA_RX,
//output reg PSRAM_SCLK,
//output reg PSRAM_CE,
//inout PSRAM_SIO0,
//inout PSRAM_SIO1,
//inout PSRAM_SIO2,
//inout PSRAM_SIO3,
output reg LED_R,
output reg LED_G,
output reg LED_B
);
initial begin
LCD_CLK <= 1'b0;
LCD_DE <= 1'b0;
LCD_HSYNC <= 1'b0;
LCD_VSYNC <= 1'b0;
LCD_R <= 5'b00000;
LCD_G <= 6'b000000;
LCD_B <= 5'b00000;
LED_R <= 1'b0;
LED_G <= 1'b0;
LED_B <= 1'b0;
end
assign clk_24M = XTAL_IN;
assign rstn = USER_BTN_B;
/* On-Chip Oscillator 2.5 MHz (240 MHz / 96). ********************************/
wire clk_2M5;
Gowin_OSC_div96 Gowin_OSC_div96_inst (.oscout(clk_2M5));
/* On-Chip PLL 108 MHz. *****************************************************/
wire clk_108M;
wire pll_lock;
wire pll_reset = 1'b0;
Gowin_rPLL Gowin_rPLL_inst (
.clkout(clk_108M),
.lock (pll_lock),
.reset (pll_reset),
.clkin (clk_24M)
);
reg [1:0] cnt_clkdiv = 'd0;
always @(posedge clk_108M) begin
cnt_clkdiv <= cnt_clkdiv + 1;
if (cnt_clkdiv == 'd1) begin
LCD_CLK <= ~LCD_CLK;
cnt_clkdiv <= 0;
end
end
/* Counter for LED blinking. ************************************************/
parameter CNT_LEN = 26;
reg [CNT_LEN-1:0] cnt = 0;
always @(posedge clk_2M5, negedge rstn) begin
if (rstn == 1'b0) begin
cnt <= 'd0;
end else begin
cnt <= cnt + 1;
end
end
always @(*) begin
LED_R <= ~cnt[CNT_LEN-1];
LED_G <= ~cnt[CNT_LEN-2];
LED_B <= ~cnt[CNT_LEN-3];
end
endmodule
| 7.3391 |
module tang_system (
input extclk,
input rst_n,
output ser_tx,
input ser_rx,
output [2:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_flash_csb,
output debug_flash_clk,
output debug_flash_io0,
output debug_flash_io1,
output debug_flash_io2,
output debug_flash_io3
);
wire clk;
wire pll_lock;
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
if (~pll_lock) reset_cnt <= 6'b0;
else reset_cnt <= reset_cnt + !resetn;
end
pll u_pll (
.refclk(extclk),
.reset(~rst_n),
.extlock(pll_lock),
.clk0_out(clk)
);
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
assign flash_io3 = flash_io3_oe ? flash_io3_do : 1'bz;
assign flash_io2 = flash_io2_oe ? flash_io2_do : 1'bz;
assign flash_io1 = flash_io1_oe ? flash_io1_do : 1'bz;
assign flash_io0 = flash_io0_oe ? flash_io0_do : 1'bz;
assign flash_io3_di = flash_io3;
assign flash_io2_di = flash_io2;
assign flash_io1_di = flash_io1;
assign flash_io0_di = flash_io0;
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio[2:0];
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc soc (
.clk (clk),
.resetn(resetn),
.ser_tx(ser_tx),
.ser_rx(ser_rx),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0_oe(flash_io0_oe),
.flash_io1_oe(flash_io1_oe),
.flash_io2_oe(flash_io2_oe),
.flash_io3_oe(flash_io3_oe),
.flash_io0_do(flash_io0_do),
.flash_io1_do(flash_io1_do),
.flash_io2_do(flash_io2_do),
.flash_io3_do(flash_io3_do),
.flash_io0_di(flash_io0_di),
.flash_io1_di(flash_io1_di),
.flash_io2_di(flash_io2_di),
.flash_io3_di(flash_io3_di),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
assign debug_flash_csb = flash_csb;
assign debug_flash_clk = flash_clk;
assign debug_flash_io0 = flash_io0_di;
assign debug_flash_io1 = flash_io1_di;
assign debug_flash_io2 = flash_io2_di;
assign debug_flash_io3 = flash_io3_di;
endmodule
| 6.732695 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
shift_registers_2 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
shift_registers_2 <= shift_registers_1;
end
end
assign out = shift_registers_2;
endmodule
| 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge clk) begin
if (reset) begin
reg_ax <= 0;
reg_ay <= 0;
reg_az <= 0;
reg_res <= 0;
end else begin
reg_ax <= ax;
reg_ay <= ay;
reg_az <= az;
reg_res <= (reg_ax * reg_ay) + reg_az;
end
end
assign resulta = reg_res;
reg input_valid, result_valid, output_valid;
always @(posedge clk) begin
if (reset) begin
output_valid <= 1'b0;
input_valid <= 1'b0;
result_valid <= 1'b0;
end else if (ena) begin
input_valid <= i_valid;
result_valid <= input_valid;
output_valid <= result_valid;
end
end
assign o_valid = output_valid;
endmodule
| 7.738783 |
module tanh_layer (
clk,
rst,
inputs,
outputs
);
// DESCRIPTION: takes array of inputs, weights & biases them,
// and applies tanh per output value
// NOTE: This is using systemverilog 2005 for compilation in Quartus.
// This was done so you could use 2d array inputs and output ports instead of packing/unpacking
// right click file=>file properties=> HDL Version, to make sure that setting is chosen if compilation errors occur.
// input parameters
parameter DATA_WIDTH = 16; // number of bits per input
parameter FRACT_WIDTH = 8; // number of bits for fraction part of fixed-point num
parameter N_IN = 3; // number of inputs
parameter N_OUT = 2; // number of outputs
// define ports
input clk, rst;
input [DATA_WIDTH-1:0] inputs[0:N_IN-1];
output [DATA_WIDTH-1:0] outputs[0:N_OUT-1];
// internal use
wire [DATA_WIDTH-1:0] tanh_in[0:N_OUT-1];
// module behavior:
WeightAndBiasInputs #(DATA_WIDTH, FRACT_WIDTH, N_IN, N_OUT) inst1 (
.clk(clk),
.rst(rst),
.inputs(inputs),
.outputs(tanh_in)
);
// perform element-wise tanh on outputs
genvar i;
generate
for (i = 0; i < N_OUT; i = i + 1) begin : GEN
tanh #(DATA_WIDTH, FRACT_WIDTH) tanh (
.X(tanh_in[i]),
.Y(outputs[i])
);
end
endgenerate
endmodule
| 6.770634 |
module Tan_multiplier (
clock,
a,
b,
product
);
parameter awidth = 10;
parameter bwidth = 10;
parameter pwidth = 20;
input clock;
input [awidth-1:0] a;
input [bwidth-1:0] b;
output wire [16:0] product;
wire [pwidth-1:0] product_internal;
assign product = product_internal[18:2];
DW02_mult_3_stage #(awidth, bwidth) U1 (
.A(a),
.B(b),
.TC(1'b0),
.CLK(clock),
.PRODUCT(product_internal)
);
endmodule
| 6.86148 |
module tanh_result (
input clock
, input start_interpolation
, input [16:0] product
, output wire [15:0] tanh_result
);
reg [16:0] interpolation;
reg [16:0] interpolation_internal;
reg [16:0] mux_out;
always @(posedge clock) begin
interpolation <= interpolation_internal;
end
always @(*) begin
case (start_interpolation)
1'b0: mux_out = interpolation;
1'b1: mux_out = 0;
endcase
interpolation_internal = product + mux_out;
end
assign tanh_result[15:0] = interpolation[16:1];
endmodule
| 6.896771 |
module tanh_tb ();
reg clk;
reg [17:0] tanh_in;
wire [17:0] tanh_out;
reg [7:0] cnt = 0;
reg [15:0] test_num = 16'hffff;
initial begin
tanh_in = 0;
clk = 0;
end
always @(posedge clk) begin
cnt <= cnt + 1;
if (cnt == 3) begin
tanh_in <= 18'b0000_0010_0000_0000_00; //0.5 (1,5,12)
end else if (cnt == 4) begin
tanh_in <= 18'b0000_0100_0000_0000_00; //1 (1,5,12)
end else if (cnt == 5) begin
tanh_in <= 18'b0111_1111_1111_1111_11;
end else if (cnt == 6) begin
tanh_in <= 18'b1011_1100_1111_1111_11;
end else if (cnt == 7) begin
tanh_in <= 18'b1110_1111_1111_1111_11;
end
end
tanh uut (
.clk(clk),
.tanh_in(tanh_in),
.tanh_out(tanh_out)
);
always #5 clk = ~clk;
endmodule
| 6.705764 |
module tanh (
input clock
, input [16:0] a_mod
, input [15:0] y
, output wire [11:0] y_address
, input start_tanh
, input start_interpolation
, output wire [15:0] tanh_result
);
wire [ 9:0] x1;
wire [ 9:0] x_difference;
wire [16:0] product;
Yunit U1 (
.address(a_mod[16:9]),
.start_tanh(start_tanh),
.y_address(y_address)
);
complement_9bit U2 (
.a(a_mod[8:0]),
.a_complement(x1)
);
Xunit U3 (
.clock(clock),
.x0({1'b0, a_mod[8:0]}),
.x1(x1),
.start_tanh(start_tanh),
.x_difference(x_difference)
);
Tan_multiplier U4 (
.clock(clock),
.a(x_difference[9:0]),
.b(y[15:6]),
.product(product)
);
tanh_result U5 (
.clock(clock),
.start_interpolation(start_interpolation),
.product(product),
.tanh_result(tanh_result)
);
endmodule
| 6.502063 |
module Yunit (
input [7:0] address
, input start_tanh
, output reg [11:0] y_address
);
always @(*) begin
case (start_tanh)
1'b0: y_address = {3'b0, address, 1'b0};
1'b1: y_address = {3'b0, address + 1, 1'b0};
endcase
end
endmodule
| 6.714156 |
module playfield (
hpos,
vpos,
playfield_gfx
);
input [8:0] hpos;
input [8:0] vpos;
output playfield_gfx;
reg [31:0] maze[0:27];
wire [4:0] x = hpos[7:3];
wire [4:0] y = vpos[7:3] - 2;
assign playfield_gfx = maze[y][x];
initial begin
maze[0] = 32'b11111111111111111111111111111111;
maze[1] = 32'b10000000000100000000001000000001;
maze[2] = 32'b10000000000100000000001000000001;
maze[3] = 32'b10000000000100000000000000000001;
maze[4] = 32'b10011110000000000000000000000001;
maze[5] = 32'b10000000000000000000000000000001;
maze[6] = 32'b10000000001000000000000011110001;
maze[7] = 32'b11100010000000000000000000100001;
maze[8] = 32'b10000010000000000000000000100001;
maze[9] = 32'b10000011100000000000000000000001;
maze[10] = 32'b10000000000000000000000000000001;
maze[11] = 32'b10000000000000000000000000000001;
maze[12] = 32'b11111000001000000000000000000001;
maze[13] = 32'b10001000001000000000000111100001;
maze[14] = 32'b10001000001000000000000000000001;
maze[15] = 32'b10000000001000000000000000000001;
maze[16] = 32'b10000000001000000000000000000001;
maze[17] = 32'b10000000000000000000000000000001;
maze[18] = 32'b10000010000000000000000100011001;
maze[19] = 32'b10001110000000000000000100010001;
maze[20] = 32'b10000000001000000000000100010001;
maze[21] = 32'b10000000001110000000000100000001;
maze[22] = 32'b10000000000000000010001100000001;
maze[23] = 32'b10000000000000000000000000000001;
maze[24] = 32'b10000010000111100000000000010001;
maze[25] = 32'b10000010000000100000000000010001;
maze[26] = 32'b10000010000000000010000000010001;
maze[27] = 32'b11111111111111111111111111111111;
end
endmodule
| 7.313035 |
module tank_game_top (
input clk,
input reset,
input [7:0] switches_p1,
input [7:0] switches_p2,
output hsync,
output vsync,
output [2:0] rgb
);
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
wire mine_gfx;
wire playfield_gfx;
wire tank1_gfx;
wire tank2_gfx;
// video sync generator
hvsync_generator hvsync_gen (
.clk(clk),
.reset(0),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
minefield mine_gen (
.hpos(hpos),
.vpos(vpos),
.mine_gfx(mine_gfx)
);
playfield playfield_gen (
.hpos(hpos),
.vpos(vpos),
.playfield_gfx(playfield_gfx)
);
wire p2sel = hpos > 280;
wire [7:0] tank1_sprite_addr;
wire [7:0] tank2_sprite_addr;
wire [7:0] tank_sprite_bits;
// bitmap ROM is shared between tank 1 and 2
tank_bitmap tank_bmp (
.addr(p2sel ? tank2_sprite_addr : tank1_sprite_addr),
.bits(tank_sprite_bits)
);
// player 1 tank controller
tank_controller #(16, 36, 4) tank1 (
.clk(clk),
.reset(reset),
.hpos(hpos),
.vpos(vpos),
.hsync(hsync && !p2sel),
.vsync(vsync),
.sprite_addr(tank1_sprite_addr),
.sprite_bits(tank_sprite_bits),
.gfx(tank1_gfx),
.playfield(playfield_gfx),
.switch_left(switches_p1[0]),
.switch_right(switches_p1[1]),
.switch_up(switches_p1[2])
);
// player 2 tank controller
tank_controller #(220, 190, 12) tank2 (
.clk(clk),
.reset(reset),
.hpos(hpos),
.vpos(vpos),
.hsync(hsync && p2sel),
.vsync(vsync),
.sprite_addr(tank2_sprite_addr),
.sprite_bits(tank_sprite_bits),
.gfx(tank2_gfx),
.playfield(playfield_gfx),
.switch_left(switches_p2[0]),
.switch_right(switches_p2[1]),
.switch_up(switches_p2[2])
);
// video signal mixer
wire r = display_on && (mine_gfx || tank2_gfx);
wire g = display_on && tank1_gfx;
wire b = display_on && (playfield_gfx || tank2_gfx);
assign rgb = {b, g, r};
endmodule
| 6.722855 |
module tankb__cputest_top;
//wire & reg setup
reg PUR = 1'b1;
reg clk = 1'b0;
reg nRESET = 1'b1;
wire Phi2, cpu_clken;
//start simulation specific
initial begin
#10 nRESET = 1'b0;
#1 PUR = 1'b0;
#50 PUR = 1'b1;
#70 nRESET = 1'b1;
end
always #1 clk <= ~clk;
//end simulation specific
clock cpu_clk1 (
.clk(clk),
.rst_n(nRESET),
.Phi2(Phi2),
.cpu_clken(cpu_clken)
);
//CPU 6502
wire [15:0] A;
wire r_w;
wire [7:0] cpudata_in, cpudata_out;
arlet_6502 my_cpu (
.clk (clk),
.enable (cpu_clken),
.rst_n (nRESET),
.ab (A),
.dbi (cpudata_in),
.dbo (cpudata_out),
.we (r_w),
.irq_n (1'b1),
.nmi_n (1'b1),
.ready (cpu_clken),
.pc_monitor()
);
//end of CPU 6502
//start of ROM
wire [7:0] romdata_out;
rom2716_mrw mrw1 (
.addr(A[10:0]),
.clk(clk),
.q(romdata_out)
);
//end of ROM
//start of RAM
wire [7:0] ramdata_out;
ram2114 mrw2 (
.data(cpudata_out),
.addr(A[10:0]),
.we(r_w),
.clk(clk),
.q(ramdata_out)
);
//end of RAM
//start of Address muxing
wire rom_mrw_cs = (A[15] == 1'b1);
wire ram_cs = (A[15] == 1'b0);
assign cpudata_in = rom_mrw_cs ? romdata_out : ram_cs ? ramdata_out : 8'h00;
//end of Address muxing
endmodule
| 7.159422 |
module tank_decoder2 (
output wire rack_loc_t0_in,
output wire rack_loc_t1_in,
output wire rack_loc_t2_in,
output wire rack_loc_t3_in,
output wire rack_loc_t0_out,
output wire rack_loc_t1_out,
output wire rack_loc_t2_out,
output wire rack_loc_t3_out,
input wire rack_loc_f7_pos, // Tank address bit 7 (from Tank Distribution Unit).
input wire rack_loc_f7_neg, // Inverted Tank address bit 7 (from Tank Distribution Unit).
input wire rack_loc_f8_pos, // Tank address bit 8 (from Tank Distribution Unit).
input wire rack_loc_f8_neg, // Inverted Tank address bit 8 (from Tank Distribution Unit).
input wire rack_loc_t_in,
input wire rack_loc_t_out
);
wire [1:0] count;
assign count[1:0] = {rack_loc_f8_pos, rack_loc_f7_pos};
assign {rack_loc_t3_out, rack_loc_t2_out, rack_loc_t1_out, rack_loc_t0_out} = rack_loc_t_out ? (4'b0001 << count) : 4'b0000;
assign {rack_loc_t3_in, rack_loc_t2_in, rack_loc_t1_in, rack_loc_t0_in} = rack_loc_t_in ? (4'b0001 << count) : 4'b0000;
endmodule
| 6.721101 |
module
(Similar to physical layer)
(convert the x/y relative coordinate to VGA data)
Modification History:
Date By Version Description
----------------------------------------------------------
180505 ctlvie 0.5 Module interface definition
180507 ctlvie 1.0 Initial coding completed (unverified)
180508 ctlvie 1.1 Corrected the reg conflict error(unverified)
180510 ctlvie 1.5 Full Version!
180512 ctlvie 1.6 1. Change the coordinate
2. Add enable interface
3. Change the tank's size
180525 ctlvie 2.0 Final Version
========================================================*/
`timescale 1ns/1ns
//----------------------------------------------------------
//Define the colour parameter RGB 4|4|4
`define RED 12'hF00
`define GREEN 12'h0F0
`define BLUE 12'h00F
`define WHITE 12'hFFF
`define BLACK 12'h000
`define YELLOW 12'hFF0
`define CYAN 12'hF0F
`define ROYAL 12'h0FF
module tank_display
(
input clk,
input enable,
//input the relative position of tank
input [4:0] x_rel_pos,
input [4:0] y_rel_pos,
input [10:0] VGA_xpos,
input [10:0] VGA_ypos,
input tank_state, //the state of tank
input tank_ide, //the identify of tank (my tank(1'b1) or enemy tank(1'b0))
input [1:0] tank_dir, //the direction of tank
//output the VGA data
output reg [11:0] VGA_data
);
always@(posedge clk)
begin
if(enable)
begin
// direction = upward
if (tank_state == 1'b1 && tank_dir == 2'b00)
begin
if (((VGA_xpos > x_rel_pos * 20 + 80 - 5)&&(VGA_xpos < x_rel_pos * 20 + 80 + 5))&&((VGA_ypos > y_rel_pos * 20 + 80 - 10)&&(VGA_ypos < y_rel_pos * 20 + 80)) ||
((VGA_xpos > x_rel_pos * 20 + 80 - 10)&&(VGA_xpos < x_rel_pos *20 + 80 + 10))&&((VGA_ypos > y_rel_pos * 20 + 80)&&(VGA_ypos < y_rel_pos * 20 + 80 + 10)))
begin
if (tank_ide == 1'b1) VGA_data <= `BLUE;
else VGA_data <= `RED;
end
else
VGA_data <= 12'h000;
end
// direction = downward
if (tank_state == 1'b1 && tank_dir == 2'b01)
begin
if (((VGA_xpos > x_rel_pos * 20 + 80 - 10)&&(VGA_xpos < x_rel_pos * 20 + 80 + 10))&&((VGA_ypos > y_rel_pos * 20 + 80 - 10)&&(VGA_ypos < y_rel_pos * 20 + 80)) ||
((VGA_xpos > x_rel_pos * 20 + 80 - 5)&&(VGA_xpos < x_rel_pos *20 + 80 + 5))&&((VGA_ypos > y_rel_pos * 20 + 80)&&(VGA_ypos < y_rel_pos * 20 + 80 + 10)))
begin
if (tank_ide == 1'b1) VGA_data <= `BLUE;
else VGA_data <= `RED;
end
else
VGA_data <= 12'h000;
end
//direction = left
if (tank_state == 1'b1 && tank_dir == 2'b10)
begin
if (((VGA_xpos > x_rel_pos * 20 + 80 - 10)&&(VGA_xpos < x_rel_pos * 20 + 80 ))&&((VGA_ypos > y_rel_pos * 20 + 80 - 5)&&(VGA_ypos < y_rel_pos * 20 + 80 + 5)) ||
((VGA_xpos > x_rel_pos * 20 + 80 )&&(VGA_xpos < x_rel_pos *20 + 80 + 10))&&((VGA_ypos > y_rel_pos * 20 + 80 - 10)&&(VGA_ypos < y_rel_pos * 20 + 80 + 10)))
begin
if (tank_ide == 1'b1) VGA_data <= `BLUE;
else VGA_data <= `RED;
end
else
VGA_data <= 12'h000;
end
//direction = right
if (tank_state == 1'b1 && tank_dir == 2'b11)
begin
if (((VGA_xpos > x_rel_pos * 20 + 80 - 10)&&(VGA_xpos < x_rel_pos * 20 + 80 ))&&((VGA_ypos > y_rel_pos * 20 + 80 - 10)&&(VGA_ypos < y_rel_pos * 20 + 80 + 10)) ||
((VGA_xpos > x_rel_pos * 20 + 80 )&&(VGA_xpos < x_rel_pos *20 + 80 + 10))&&((VGA_ypos > y_rel_pos * 20 + 80 - 5)&&(VGA_ypos < y_rel_pos * 20 + 80 + 5)))
begin
if (tank_ide == 1'b1) VGA_data <= `BLUE;
else VGA_data <= `RED;
end
else
VGA_data <= 12'h000;
end
end
end
endmodule
| 6.562175 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.