code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ALU (
i_a,
i_b,
i_sel,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-2:0] i_sel;
output [2*WIDTH-1:0] o_data;
wire [2*WIDTH-1:0] o_data_mult;
wire [WIDTH-1:0] o_data_sub_0;
wire [WIDTH-1:0] o_data_add_0;
wire [WIDTH-1:0] o_data_nand_0;
wire [WIDTH-1:0] o_data_nor_0;
wire [WIDTH-1:0] o_data_sub_1;
wire [WIDTH-1:0] o_data_add_1;
wire [WIDTH-1:0] o_data_nand_1;
wire [WIDTH-1:0] o_data_nor_1;
wire [WIDTH-1:0] i_a_mult;
wire [WIDTH-1:0] i_a_sub;
wire [WIDTH-1:0] i_a_add;
wire [WIDTH-1:0] i_a_nand;
wire [WIDTH-1:0] i_a_nor;
wire [WIDTH-1:0] i_b_mult;
wire [WIDTH-1:0] i_b_sub;
wire [WIDTH-1:0] i_b_add;
wire [WIDTH-1:0] i_b_nand;
wire [WIDTH-1:0] i_b_nor;
wire i_c = 1'b0;
wire i_bor = 1'b0;
assign i_a_mult = i_a;
assign i_a_sub = i_a;
assign i_a_add = i_a;
assign i_a_nand = i_a;
assign i_a_nor = i_a;
assign i_b_mult = i_b;
assign i_b_sub = i_b;
assign i_b_add = i_b;
assign i_b_nand = i_b;
assign i_b_nor = i_b;
full_adder_4bit fa (
.i_a(i_a_add),
.i_b(i_b_add),
.i_c(i_c),
.o_s(o_data_add_0)
);
bit4_sub fs (
.i_a (i_a_sub),
.i_b (i_b_sub),
.i_bor(i_bor),
.o_sub(o_data_sub_0)
);
multiplier mp (
.i_a(i_a_mult),
.i_b(i_b_mult),
.o_mult(o_data_mult)
);
bit4_nand bn (
.i_a(i_a_nand),
.i_b(i_b_nand),
.o_data(o_data_nand_0)
);
bit4_nor br (
.i_a(i_a_nor),
.i_b(i_b_nor),
.o_data(o_data_nor_0)
);
bit4_mux bm0 (
.i_data0(o_data_add_0),
.i_data1(o_data_sub_0),
.i_data2(o_data_mult[3:0]),
.i_data3(o_data_nand_0),
.i_data4(o_data_nor_0),
.i_ctrl (i_sel),
.o_data (o_data[3:0])
);
bit4_mux bm1 (
.i_data0(o_data_add_1),
.i_data1(o_data_sub_1),
.i_data2(o_data_mult[7:4]),
.i_data3(o_data_nand_1),
.i_data4(o_data_nor_1),
.i_ctrl (i_sel),
.o_data (o_data[7:4])
);
assign o_data_add_1 = 4'b0000;
assign o_data_sub_1 = 4'b0000;
assign o_data_nand_1 = 4'b0000;
assign o_data_nor_1 = 4'b0000;
endmodule
| 6.985879 |
module ALU_behav (
i_sel_g,
i_a_g,
i_b_g,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a_g, i_b_g;
input [WIDTH-2:0] i_sel_g;
output reg [2*WIDTH-1:0] o_data_g;
wire [ WIDTH-1:0] i_a_add_g;
wire [ WIDTH-1:0] i_b_add_g;
wire [ WIDTH-1:0] i_a_sub_g;
wire [ WIDTH-1:0] i_b_sub_g;
wire [ WIDTH-1:0] i_a_mult_g;
wire [ WIDTH-1:0] i_b_mult_g;
wire [ WIDTH-1:0] i_a_nand_g;
wire [ WIDTH-1:0] i_b_nand_g;
wire [ WIDTH-1:0] i_a_nor_g;
wire [ WIDTH-1:0] i_b_nor_g;
wire [ WIDTH-1:0] o_data_add_g;
wire [ WIDTH-1:0] o_data_sub_g;
wire [2*WIDTH-1:0] o_data_mult_g;
wire [ WIDTH-1:0] o_data_nand_g;
wire [ WIDTH-1:0] o_data_nor_g;
assign i_a_add_g = i_a_g;
assign i_b_add_g = i_b_g;
assign i_a_sub_g = i_a_g;
assign i_b_sub_g = i_b_g;
assign i_a_mult_g = i_a_g;
assign i_b_mult_g = i_b_g;
assign i_a_nand_g = i_a_g;
assign i_b_nand_g = i_b_g;
assign i_a_nor_g = i_a_g;
assign i_b_nor_g = i_b_g;
assign o_data_add_g = i_a_g + i_b_g;
assign o_data_sub_g = i_a_g - i_b_g;
assign o_data_mult_g = i_a_g * i_b_g;
assign o_data_nand_g = ~(i_a_g & i_b_g);
assign o_data_nor_g = ~(i_a_g | i_b_g);
always @* begin
case (i_sel_g)
3'b000: o_data_g = {4'b0000, o_data_add_g};
3'b001: o_data_g = {4'b0000, o_data_sub_g};
3'b010: o_data_g = o_data_mult_g;
3'b011: o_data_g = {4'b0000, o_data_nand_g};
3'b100: o_data_g = {4'b0000, o_data_nor_g};
default: o_data_g = o_data_g;
endcase
end
endmodule
| 7.545058 |
module add_sub (
i_a,
i_b,
i_a_g,
i_b_g,
o_res,
o_res_g,
o_c
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-1:0] i_a_g;
input [WIDTH-1:0] i_b_g;
output [WIDTH:0] o_res_g;
output [WIDTH-1:0] o_res;
output o_c;
wire [WIDTH-1:0] i_b_in;
wire carry_i, carry_wire;
`ifdef ADD
assign i_b_in = i_b;
assign carry_i = 1'b0;
assign o_res_g = i_a_g + i_b_g;
param_adder pa (
.i_a (i_a),
.i_b (i_b_in),
.i_c (carry_i),
.o_si(o_res),
.o_pi(o_c)
);
`else
assign i_b_in = ~i_b;
assign carry_i = 1'b1;
assign o_res_g = i_a_g - i_b_g;
param_adder pa (
.i_a (i_a),
.i_b (i_b_in),
.i_c (carry_i),
.o_si(o_res),
.o_pi(carry_wire)
);
assign o_c = ~carry_wire;
`endif
endmodule
| 7.314322 |
module param_adder (
i_a,
i_b,
i_c,
o_si,
o_pi
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_c;
output [WIDTH-1:0] o_si;
output o_pi;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADD
if (i == 0) begin
full_adder fa (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_c (i_c),
.o_si(o_si[i]),
.o_pi(carry[i])
);
end else if (i == (WIDTH - 1)) begin
full_adder fa (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_c (carry[i-1]),
.o_si(o_si[i]),
.o_pi(o_pi)
);
end else begin
full_adder fa (
.i_a (i_a[i]),
.i_b (i_b[i]),
.i_c (carry[i-1]),
.o_si(o_si[i]),
.o_pi(carry[i])
);
end
end
endgenerate
endmodule
| 8.614904 |
module gen_add_sub (
i_a,
i_b,
i_a_g,
i_b_g,
o_res,
o_c,
o_res_g
);
parameter ADDSUB = 1'b1;
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_res;
output [WIDTH:0] o_res_g;
output o_c;
wire o_carry;
generate
begin
if (ADDSUB == 1'b1) begin
assign o_res_g = i_a_g + i_b_g;
param_adder paa (
.i_a (i_a),
.i_b (i_b),
.i_c (1'b0),
.o_si(o_res),
.o_pi(o_c)
);
end else if (ADDSUB == 1'b0) begin
assign o_res_g = i_a_g - i_b_g;
param_adder pas (
.i_a (i_a),
.i_b (~i_b),
.i_c (1'b1),
.o_si(o_res),
.o_pi(o_carry)
);
assign o_c = ~o_carry;
end
end
endgenerate
endmodule
| 7.113416 |
module full_adder_4bit (
i_a,
i_b,
i_c,
o_pi,
o_s
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_c;
output o_pi;
output [WIDTH-1:0] o_s;
wire fa0_ci;
wire fa1_ci;
wire fa2_ci;
wire fa3_ci;
full_adder fa0 (
.i_a (i_a[0]),
.i_b (i_b[0]),
.i_c (i_c),
.o_si(o_s[0]),
.o_pi(fa0_ci)
);
full_adder fa1 (
.i_a (i_a[1]),
.i_b (i_b[1]),
.i_c (fa0_ci),
.o_si(o_s[1]),
.o_pi(fa1_ci)
);
full_adder fa2 (
.i_a (i_a[2]),
.i_b (i_b[2]),
.i_c (fa1_ci),
.o_si(o_s[2]),
.o_pi(fa2_ci)
);
full_adder fa3 (
.i_a (i_a[3]),
.i_b (i_b[3]),
.i_c (fa2_ci),
.o_si(o_s[3]),
.o_pi(o_pi)
);
endmodule
| 6.62292 |
module full_adder_4bit_tb;
parameter WIDTH = 4;
reg [WIDTH-1:0] i_a, i_b;
reg i_c;
wire o_pi;
wire [WIDTH-1:0] o_s;
full_adder_4bit fa_tb (
.i_a (i_a),
.i_b (i_b),
.i_c (i_c),
.o_pi(o_pi),
.o_s (o_s)
);
initial begin
i_a = 4'b0000;
i_b = 4'b0000;
i_c = 1'b0;
repeat (20) begin
#10 i_a = $random();
i_b = $random();
end
$finish;
end
endmodule
| 6.62292 |
module half_adder (
i_a,
i_b,
o_si,
o_pi
);
input i_a, i_b;
output o_si, o_pi;
assign o_si = i_a ^ i_b;
assign o_pi = i_a & i_b;
endmodule
| 6.966406 |
module full_adder_4bit2 (
i_a,
i_b,
i_c,
i_a_g,
i_b_g,
o_pi,
o_s,
o_sum_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-1:0] i_a_g, i_b_g;
input i_c;
output o_pi;
output [WIDTH-1:0] o_s;
output [WIDTH:0] o_sum_g;
wire fa0_ci;
wire fa1_ci;
wire fa2_ci;
wire fa3_ci;
assign o_sum_g = i_a_g + i_b_g;
full_adder2 fa0 (
.i_a (i_a[0]),
.i_b (i_b[0]),
.i_c (i_c),
.o_si(o_s[0]),
.o_pi(fa0_ci)
);
full_adder2 fa1 (
.i_a (i_a[1]),
.i_b (i_b[1]),
.i_c (fa0_ci),
.o_si(o_s[1]),
.o_pi(fa1_ci)
);
full_adder2 fa2 (
.i_a (i_a[2]),
.i_b (i_b[2]),
.i_c (fa1_ci),
.o_si(o_s[2]),
.o_pi(fa2_ci)
);
full_adder2 fa3 (
.i_a (i_a[3]),
.i_b (i_b[3]),
.i_c (fa2_ci),
.o_si(o_s[3]),
.o_pi(o_pi)
);
endmodule
| 6.62292 |
module full_adder_4bit_tb2;
parameter WIDTH = 4;
reg [WIDTH-1:0] i_a, i_b;
reg [WIDTH-1:0] i_a_g, i_b_g;
reg i_c;
wire o_pi;
wire [WIDTH-1:0] o_s;
wire [WIDTH:0] o_sum_g;
integer i = 0, j = 0, k;
full_adder_4bit2 fa_tb (
.i_a(i_a),
.i_b(i_b),
.i_c(i_c),
.i_a_g(i_a_g),
.i_b_g(i_b_g),
.o_pi(o_pi),
.o_s(o_s),
.o_sum_g(o_sum_g)
);
initial begin
i_a = 4'b0000;
i_b = 4'b0000;
i_c = 1'b0;
i_a_g = 4'b0001;
i_b_g = 4'b0000;
k = 0;
end
initial begin
forever
#10
if ({o_pi, o_s} != o_sum_g) begin
k = k + 1;
$display("Time = %d;", $time, " Error", " Golden_Model = %b;", o_sum_g, " Real_value = %b;",
{o_pi, o_s});
end else begin
k = k;
end
end
initial begin
for (i = 0; i < 16; i = i + 1) begin
for (j = 0; j < 16; j = j + 1) begin
#10 i_b = j;
i_b_g = j;
end
#10 i_a = i + 1;
i_a_g = i + 1;
end
$display("Error counter =%d", k);
$finish;
end
endmodule
| 6.62292 |
module full_adder2 (
i_a,
i_b,
i_c,
o_si,
o_pi
);
input i_a, i_b, i_c;
output o_si, o_pi;
wire ha1_sum;
wire ha2_sum;
wire ha1_carry;
wire ha2_carry;
half_adder ha1 (
.i_a (i_a),
.i_b (i_b),
.o_si(ha1_sum),
.o_pi(ha1_carry)
);
half_adder ha2 (
.i_a (ha1_sum),
.i_b (i_c),
.o_si(ha2_sum),
.o_pi(ha2_carry)
);
assign o_si = ha2_sum;
assign o_pi = ha1_carry | ha2_carry;
endmodule
| 7.985516 |
module bit4_sub (
i_a,
i_b,
i_a_g,
i_b_g,
i_bor,
o_sub,
o_sub_g,
o_b
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
input i_bor;
output [WIDTH-1:0] o_sub;
output signed [WIDTH:0] o_sub_g;
output o_b;
wire fs0_bor;
wire fs1_bor;
wire fs2_bor;
wire fs3_bor;
assign o_sub_g = i_a_g - i_b_g;
f_sub fs0 (
.i_a (i_a[0]),
.i_b (i_b[0]),
.i_bor(i_bor),
.o_sub(o_sub[0]),
.o_b (fs0_bor)
);
f_sub fs1 (
.i_a (i_a[1]),
.i_b (i_b[1]),
.i_bor(fs0_bor),
.o_sub(o_sub[1]),
.o_b (fs1_bor)
);
f_sub fs2 (
.i_a (i_a[2]),
.i_b (i_b[2]),
.i_bor(fs1_bor),
.o_sub(o_sub[2]),
.o_b (fs2_bor)
);
f_sub fs3 (
.i_a (i_a[3]),
.i_b (i_b[3]),
.i_bor(fs2_bor),
.o_sub(o_sub[3]),
.o_b (fs3_bor)
);
assign o_b = fs3_bor;
endmodule
| 7.148356 |
module h_sub (
i_a,
i_b,
o_sub,
o_b
);
input i_a, i_b;
output o_sub, o_b;
assign o_sub = i_a ^ i_b;
assign o_b = !i_a & i_b;
endmodule
| 7.262048 |
module bit1_mux (
i_ctrl,
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
o_data
);
input [2:0] i_ctrl;
input i_data0, i_data1, i_data2, i_data3, i_data4;
output o_data;
wire o_data0;
wire o_data1;
wire o_data2;
wire o_data3;
wire o_data4;
wire inv_i_ctrl0;
wire inv_i_ctrl1;
wire inv_i_ctrl2;
wire i_ctrl0;
wire i_ctrl1;
wire i_ctrl2;
assign i_ctrl0 = i_ctrl[0];
assign i_ctrl1 = i_ctrl[1];
assign i_ctrl2 = i_ctrl[2];
assign inv_i_ctrl0 = ~i_ctrl[0];
assign inv_i_ctrl1 = ~i_ctrl[1];
assign inv_i_ctrl2 = ~i_ctrl[2];
assign o_data0 = inv_i_ctrl0 & inv_i_ctrl1 & inv_i_ctrl2 & i_data0;
assign o_data1 = i_ctrl0 & inv_i_ctrl1 & inv_i_ctrl2 & i_data1;
assign o_data2 = inv_i_ctrl0 & i_ctrl1 & inv_i_ctrl2 & i_data2;
assign o_data3 = i_ctrl0 & i_ctrl1 & inv_i_ctrl2 & i_data3;
assign o_data4 = inv_i_ctrl0 & inv_i_ctrl1 & i_ctrl2 & i_data4;
assign o_data = o_data0 | o_data1 | o_data2 | o_data3 | o_data4;
endmodule
| 6.564483 |
module bit4_mux(
i_ctrl,
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
o_data,
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_ctrl;
input [WIDTH-1:0] i_data0, i_data1, i_data2, i_data3, i_data4;
output [WIDTH-1:0] o_data;
bit1_mux mx0(
.i_data0(i_data0[0]),
.i_data1(i_data1[0]),
.i_data2(i_data2[0]),
.i_data3(i_data3[0]),
.i_data4(i_data4[0]),
.i_ctrl(i_ctrl),
.o_data(o_data[0])
);
bit1_mux mx1(
.i_data0(i_data0[1]),
.i_data1(i_data1[1]),
.i_data2(i_data2[1]),
.i_data3(i_data3[1]),
.i_data4(i_data4[1]),
.i_ctrl(i_ctrl),
.o_data(o_data[1])
);
bit1_mux mx2(
.i_data0(i_data0[2]),
.i_data1(i_data1[2]),
.i_data2(i_data2[2]),
.i_data3(i_data3[2]),
.i_data4(i_data4[2]),
.i_ctrl(i_ctrl),
.o_data(o_data[2])
);
bit1_mux mx3(
.i_data0(i_data0[3]),
.i_data1(i_data1[3]),
.i_data2(i_data2[3]),
.i_data3(i_data3[3]),
.i_data4(i_data4[3]),
.i_ctrl(i_ctrl),
.o_data(o_data[3])
);
endmodule
| 7.917164 |
module bit4_mux_gm (
i_ctrl_g,
i_data0_g,
i_data1_g,
i_data2_g,
i_data3_g,
i_data4_g,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_ctrl_g;
input [WIDTH-1:0] i_data0_g, i_data1_g, i_data2_g, i_data3_g, i_data4_g;
output reg [WIDTH-1:0] o_data_g;
always @* begin
case (i_ctrl_g)
3'd0: o_data_g = i_data0_g;
3'd1: o_data_g = i_data1_g;
3'd2: o_data_g = i_data2_g;
3'd3: o_data_g = i_data3_g;
3'd4: o_data_g = i_data4_g;
default: o_data_g = o_data_g;
endcase
end
endmodule
| 6.788316 |
module bit1_nand (
i_a,
i_b,
o_data
);
input i_a, i_b;
output o_data;
nand (o_data, i_a, i_b);
endmodule
| 7.470001 |
module bit4_nand (
i_a,
i_b,
i_a_g,
i_b_g,
o_data,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_data, o_data_g;
bit1_nand bn0 (
.i_a(i_a[0]),
.i_b(i_b[0]),
.o_data(o_data[0])
);
bit1_nand bn1 (
.i_a(i_a[1]),
.i_b(i_b[1]),
.o_data(o_data[1])
);
bit1_nand bn2 (
.i_a(i_a[2]),
.i_b(i_b[2]),
.o_data(o_data[2])
);
bit1_nand bn3 (
.i_a(i_a[3]),
.i_b(i_b[3]),
.o_data(o_data[3])
);
/*
assign o_data_g[0] = ~(i_a_g[0] & i_b_g[0]);
assign o_data_g[1] = ~(i_a_g[1] & i_b_g[1]);
assign o_data_g[2] = ~(i_a_g[2] & i_b_g[2]);
assign o_data_g[3] = ~(i_a_g[3] & i_b_g[3]); */
assign o_data_g = ~(i_a_g & i_b_g);
endmodule
| 7.314856 |
module task2_module (
clk,
rst_n,
i1_a,
i2_b,
i1,
i2
);
input clk;
input rst_n;
input [8:0] i1_a;
input [8:0] i2_b;
output [7:0] i1;
output [7:0] i2;
/***********************/
reg [8:0] rData1;
reg [8:0] rData2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rData1 <= 9'd0;
rData2 <= 9'd0;
end else begin
rData1 <= i1_a[8] ? (~i1_a + 1'b1) : i1_a;
rData2 <= i2_b[8] ? (~i2_b + 1'b1) : i2_b;
end
end
assign i1 = rData1[7:0];
assign i2 = rData2[7:0];
endmodule
| 6.678459 |
module task3_module (
input clk,
input rst_n,
input [2:0] index_in,
output reg [2:0] index_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) index_out <= 3'd0;
else index_out <= index_in;
end
endmodule
| 7.268131 |
module task4_module (
input clk,
input rst_n,
input [7:0] rom_data,
input data_valid,
input [2:0] index,
output reg [2:0] rgb
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) rgb <= 3'b000;
else rgb <= data_valid ? {rom_data[index], rom_data[index], rom_data[index]} : 3'b000;
end
endmodule
| 7.644375 |
module decoder (
i_data,
o_data
);
parameter WIDTH = 2;
input [WIDTH-1:0] i_data;
output [2**WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin : DC
assign o_data[i] = (i_data == i) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
| 7.018254 |
module mux (
i_sel,
i_d0,
i_d1,
i_d2,
i_d3,
i_d4,
o_data
);
parameter WIDTH = 4;
input [2:0] i_sel;
input [WIDTH-1:0] i_d0, i_d1, i_d2, i_d3, i_d4;
output [WIDTH-1:0] o_data;
wire [7:0] one_hot;
genvar i;
decoder #(
.WIDTH(3)
) decoder_inst (
.i_data(i_sel),
.o_data(one_hot)
);
generate
for (i = 0; i < WIDTH; i = i + 1) begin : MUX
assign o_data[i] = ((one_hot[0] & i_d0[i])|
(one_hot[1] & i_d1[i])|
(one_hot[2] & i_d2[i])|
(one_hot[3] & i_d3[i])|
(one_hot[4] & i_d4[i])
);
end
endgenerate
endmodule
| 7.162551 |
module bitwise_nand (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NAND
nand nand_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.116582 |
module taskAndFunction (
input [7:0] x,
output [7:0] z
);
assign z = ~x;
endmodule
| 6.561671 |
module taskAndFunction_tb ();
reg [7:0] x;
wire [7:0] z;
reg [7:0] w;
taskAndFunction DUT (
x,
z
);
task sum(input [3:0] a, b, output [7:0] c);
begin
c = a + b;
end
endtask
function [7:0] sub(input [3:0] a, b);
begin
sub = a - b;
end
endfunction
initial begin
#0;
x = 8'h13;
sum(x[3:0], x[7:4], w);
$display("%d + %d = %d", x[3:0], x[7:4], w);
#10;
x = 8'hFF;
sum(x[3:0], x[7:4], w);
$display("%d + %d = %d", x[3:0], x[7:4], w);
#10;
x = 8'h1F;
w = sub(x[3:0], x[7:4]);
$display("%d - %d = %d", x[3:0], x[7:4], w);
#10;
end
endmodule
| 6.561671 |
module TaskFrequencyMeter (
input clk_50M, //标准信号，50M
input rst, //复位信号
input [7:0] sw, //拨码开关输入
input signal_in, //输入待测信号1~10M
output signal_out, //输出待测信号，1~10M
output [31:0] M, //标准信号计数值
output [31:0] N, //待测信号计数值
output gate_out //实际阀门输出（也就是精确门）
);
reg [31:0] M_reg;
reg [31:0] N_reg;
reg gate_out_reg;
reg signal_in2_out_reg;
wire [31:0] M_1;
wire [31:0] N_1;
wire [31:0] M_2;
wire [31:0] N_2;
wire gate_out_1;
wire gate_out_2;
wire signal_in2_out_1;
wire signal_in2_out_2;
assign M = M_reg;
assign N = N_reg;
assign gate_out = gate_out_reg;
always@(*)//对未分频信号的计数值以及已分频信号的计数值进行选择，低频信号N_1>=N_2,高频信号N_1=0，所以N_2>N_1
begin
if (N_1 >= N_2) begin
M_reg <= M_1;
N_reg <= N_1;
gate_out_reg <= gate_out_1;
signal_in2_out_reg <= signal_in2_out_1;
end else begin
M_reg <= M_2;
N_reg <= N_2 << 4;
gate_out_reg <= gate_out_2;
signal_in2_out_reg <= signal_in2_out_2;
end
end
//输出信号
Divider_module Divider_module_inst //分频及输出
(
.clk_50M(clk_50M), // input clk_50M_sig
.rst(rst), // input rst_sig
.sw(sw), // input [7:0] sw_sig
.signal_out(signal_out) // output signal_out_sig
);
//输入信号分频
Signal_in_div_module Signal_in_div_module_inst //输入信号16分频
(
.signal_in(signal_in), // input signal_in_sig
.rst(rst), // input rst_sig
.signal_in1(signal_in1) // output signal_in1_sig
);
//得到两种输入信号再同步
//输入信号同步
Signal_in_synchronize_module Signal_in_synchronize_module_inst1//输入信号同步（未分频）
(
.clk_50M(clk_50M), // input clk_50M_sig
.rst(rst), // input rst_sig
.signal_in(signal_in), // input signal_in_sig
.signal_in2(signal_in2_1), // output signal_in2_sig
.signal_in2_out(signal_in2_out_1) // output signal_in2_out_sig
);
Signal_in_synchronize_module Signal_in_synchronize_module_inst2//输入信号同步（已分频）
(
.clk_50M(clk_50M), // input clk_50M_sig
.rst(rst), // input rst_sig
.signal_in(signal_in1), // input signal_in_sig
.signal_in2(signal_in2_2), // output signal_in2_sig
.signal_in2_out(signal_in2_out_2) // output signal_in2_out_sig
);
//同步后分别测量
//输入信号测量
Gate_module Gate_module_inst1 //输入信号测量（未分频）
(
.clk_50M(clk_50M), // input clk_50M_sig
.rst(rst), // input rst_sig
.sw(sw), // input [7:0] sw_sig
.signal_in(signal_in2_1), // input signal_in_sig
.M(M_1), // output [31:0] M_sig
.N(N_1), // output [31:0] N_sig
.gate_out(gate_out_1) // output gate_out_sig
);
Gate_module Gate_module_inst2 //输入信号测量（已分频）
(
.clk_50M(clk_50M), // input clk_50M_sig
.rst(rst), // input rst_sig
.sw(sw), // input [7:0] sw_sig
.signal_in(signal_in2_2), // input signal_in_sig
.M(M_2), // output [31:0] M_sig
.N(N_2), // output [31:0] N_sig
.gate_out(gate_out_2) // output gate_out_sig
);
endmodule
| 7.601453 |
module: Task
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TaskTest;
// Inputs
reg CLK;
reg RST;
reg WRN;
reg REN;
reg [7:0] IN;
reg LIFO;
reg FIFO;
// Outputs
wire [7:0] OUT;
// Instantiate the Unit Under Test (UUT)
Task uut (
.OUT(OUT),
.CLK(CLK),
.RST(RST),
.WRN(WRN),
.REN(REN),
.IN(IN),
.LIFO(LIFO),
.FIFO(FIFO)
);
initial begin
CLK = 0; IN = 8'd0;
RST = 1; CLK = 1; #5 ; CLK = 0; #5;
RST = 0;
$display("Start testing");
LIFO = 1;
FIFO = 0;
// First write some data into the queue
WRN = 1; REN = 0;
IN = 8'd100;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd150;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd200;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd40;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd70;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd65;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd15;
CLK = 1; #5 ; CLK = 0; #5;
// Now start reading and checking the values
WRN = 0; REN = 1;
CLK = 1; #5 ; CLK = 0; #5;
// NEED to understand why this extra CLK cycle is required.
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd15 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd65 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd70 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd40 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd200 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd150 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd100 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
///////////////////////////////////////////////////////////////////////////
LIFO = 0;
FIFO = 1;
CLK = 0; IN = 8'd0;
RST = 1; CLK = 1; #5 ; CLK = 0; #5;
RST = 0;
CLK = 1; #5 ; CLK = 0; #5;
CLK = 1; #5 ; CLK = 0; #5;
CLK = 1; #5 ; CLK = 0; #5;
$display("Start testing");
// First write some data into the queue
WRN = 1; REN = 0;
IN = 8'd100;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd150;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd200;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd40;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd70;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd65;
CLK = 1; #5 ; CLK = 0; #5;
IN = 8'd15;
CLK = 1; #5 ; CLK = 0; #5;
// Now start reading and checking the values
WRN = 0; REN = 1;
CLK = 1; #5 ; CLK = 0; #5;
// NEED to understand why this extra CLK cycle is required.
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd15 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd65 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd70 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd40 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd200 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd150 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
CLK = 1; #5 ; CLK = 0; #5;
if ( OUT === 8'd100 )
$display("PASS %d ", OUT);
else
$display("FAIL %d ", OUT);
end
endmodule
| 6.912134 |
module task_axilm (
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] AXI_AWADDR,
output reg [ 3:0] AXI_AWCACHE,
output reg [ 2:0] AXI_AWPROT,
output reg AXI_AWVALID,
input AXI_AWREADY,
// Write Data Channel
output reg [31:0] AXI_WDATA,
output reg [ 3:0] AXI_WSTRB,
output reg AXI_WVALID,
input AXI_WREADY,
// Write Response Channel
input AXI_BVALID,
output reg AXI_BREADY,
input [1:0] AXI_BRESP,
// Read Address Channel
output reg [31:0] AXI_ARADDR,
output reg [ 3:0] AXI_ARCACHE,
output reg [ 2:0] AXI_ARPROT,
output reg AXI_ARVALID,
input AXI_ARREADY,
// Read Data Channel
input [31:0] AXI_RDATA,
input [ 1:0] AXI_RRESP,
input AXI_RVALID,
output reg AXI_RREADY
);
initial begin
#0;
AXI_AWADDR <= 0;
AXI_AWCACHE <= 0;
AXI_AWPROT <= 0;
AXI_AWVALID <= 0;
AXI_WDATA <= 0;
AXI_WSTRB <= 0;
AXI_WVALID <= 0;
AXI_BREADY <= 0;
AXI_ARADDR <= 0;
AXI_ARCACHE <= 0;
AXI_ARPROT <= 0;
AXI_ARVALID <= 0;
AXI_RREADY <= 0;
end
task write;
input [31:0] ADDR;
input [31:0] WDATA;
begin
@(posedge ACLK);
wait (AXI_AWREADY);
AXI_AWADDR <= ADDR;
AXI_AWCACHE <= 4'b0011;
AXI_AWPROT <= 3'b000;
AXI_AWVALID <= 1'b1;
@(posedge ACLK);
wait (AXI_AWREADY);
AXI_AWADDR <= 32'd0;
AXI_AWCACHE <= 4'b0000;
AXI_AWPROT <= 3'b000;
AXI_AWVALID <= 1'b0;
@(posedge ACLK);
wait (AXI_WREADY);
AXI_WDATA <= WDATA;
AXI_WSTRB <= 4'b1111;
AXI_WVALID <= 1'b1;
AXI_BREADY <= 1'b1;
@(posedge ACLK);
wait (AXI_WREADY);
AXI_WDATA <= 32'd0;
AXI_WSTRB <= 4'b0000;
AXI_WVALID <= 1'b0;
@(posedge ACLK);
wait (AXI_BVALID);
@(posedge ACLK);
AXI_BREADY <= 1'b0;
$display("AXI Write: [%08X] %08X", ADDR, WDATA);
end
endtask
task read;
input [31:0] ADDR;
begin
@(posedge ACLK);
wait (AXI_AWREADY);
AXI_ARADDR <= ADDR;
AXI_ARCACHE <= 4'b0011;
AXI_ARPROT <= 3'b000;
AXI_ARVALID <= 1'b1;
@(posedge ACLK);
wait (AXI_ARREADY);
AXI_ARADDR <= 32'd0;
AXI_ARCACHE <= 4'b0000;
AXI_ARPROT <= 3'b000;
AXI_ARVALID <= 1'b0;
AXI_RREADY <= 1'b1;
@(posedge ACLK);
wait (AXI_RVALID);
$display("AXI Read : [%08X] %08X", ADDR, AXI_RDATA);
@(posedge ACLK);
wait (AXI_RVALID);
AXI_RREADY <= 1'b0;
@(posedge ACLK);
end
endtask
endmodule
| 6.645389 |
module task_axism (
input RST_N,
input CLK,
output AXIS_TCLK,
output reg [31:0] AXIS_TDATA,
output reg AXIS_TKEEP,
output reg AXIS_TLAST,
input AXIS_TREADY,
output reg [ 3:0] AXIS_TSTRB,
output reg AXIS_TVALID
);
initial begin
#0;
AXIS_TDATA = 0;
AXIS_TKEEP = 0;
AXIS_TLAST = 0;
AXIS_TSTRB = 0;
AXIS_TVALID = 0;
end
reg [31:0] ram[0:65535];
task save;
input [15:0] ADDR;
input [31:0] WDATA;
begin
ram[ADDR] <= WDATA;
end
endtask
task stream;
input [15:0] WORD;
integer i;
begin
$display("AXI Stream Start(%d)", WORD);
wait (AXIS_TREADY);
@(posedge CLK);
for (i = 0; i < WORD; i = i + 1) begin
AXIS_TKEEP <= 0;
AXIS_TVALID <= 1;
AXIS_TSTRB <= 4'b1111;
AXIS_TDATA <= ram[i];
if (i == WORD - 1) begin
AXIS_TLAST <= 1;
end
@(posedge CLK);
end
AXIS_TDATA <= 0;
AXIS_TKEEP <= 0;
AXIS_TLAST <= 0;
AXIS_TSTRB <= 0;
AXIS_TVALID <= 0;
$display("AXI Stream Finish");
end
endtask
assign AXIS_TCLK = CLK;
endmodule
| 7.731861 |
module test;
task foo;
begin
$display("PASSED");
end
endtask
task bar;
begin
test.foo;
end
endtask
initial begin
test.bar;
end
endmodule
| 7.273034 |
module task_calling (
temp_a,
temp_b,
temp_c,
temp_d
);
input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
always @(temp_a) begin
convert(temp_a, temp_b);
end
always @(temp_c) begin
convert(temp_c, temp_d);
end
endmodule
| 6.886644 |
module task_tb ();
reg [3:0] a, b;
wire [3:0] sum;
wire cout;
integer i;
adder a1 (
a,
b,
sum,
cout
);
initial begin
$dumpfile("output.vcd");
$dumpvars(0);
end
initial begin
#30 $finish;
end
always dealy;
task dealy;
begin
#5 a = $random;
b = $random;
end
endtask
endmodule
| 6.935819 |
modules
An example for the book
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
RD: read flag
EN: module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
02-02-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module task_timing_test;
//defination for Variables
reg clk;
wire RD;
reg reset;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[7:0] data;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
ROM_task R1( .CLK(clk), .RD(RD),.address(out_num),
.data(data));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
assign RD = (out_num[6:0] == 8'h7f);
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
end
endmodule
| 7.059705 |
module task_total (
input CLK,
input RST,
input [7:0] width,
output reg [16:0] area
);
//Load other module(s)
//Definition for Variables in the module
//Functions for area calculation
function [15:0] circle(input [7:0] diameter);
begin
circle = (24'd201 * {16'h0, diameter} * {16'h0, diameter}) / 256;
end
endfunction
function [15:0] square(input [7:0] width);
begin
square = {8'h0, width} * {8'h0, width};
end
endfunction
task total(input [7:0] width, output [17:0] area);
begin
area <= {2'h0, square(width)} + {2'h0, circle(width)};
end
endtask
//Logical
always @(posedge CLK, negedge RST) begin
if (!RST)
//Reset
begin
area <= 17'h0000;
end else
//Data comes
begin
total(width, area);
end
end
endmodule
| 8.097842 |
module tau640 (
//X1 (Bt.656 from Tau640)
input raw_in_vclk,
input raw_in_scl,
input raw_in_sda,
input [7:0] raw_in_data,
//XS1 (Bt.656 to display)
output raw_out_vclk,
output raw_out_scl,
output raw_out_sda,
output [7:0] raw_out_data,
//XS2 (YVYU to Banana-pi)
output yuv_out_vclk,
output yuv_out_pclk,
output yuv_out_cam_pwdn,
output yuv_out_scl,
output yuv_out_sda,
output yuv_out_vsync,
output yuv_out_href,
output [9:0] yuv_out_data
);
wire [7:0] bt_data;
wire bt_h_sync, bt_v_sync, field, reset, ce;
assign reset = 1'b0;
assign ce = 1'b1;
colorbars bt656 (
.clk(raw_in_vclk),
.rst(reset),
.ce(ce),
.q(bt_data),
.h_sync(bt_h_sync),
.v_sync(bt_v_sync),
.field(field)
);
bt640_capture capture_inst (
.raw_in_vclk(raw_in_vclk),
.raw_in_scl(1'b0),
.raw_in_sda(1'b0),
.raw_in_data(bt_data),
.yuv_out_vclk(yuv_out_vclk),
.yuv_out_pclk(yuv_out_pclk),
.yuv_out_cam_pwdn(yuv_out_cam_pwdn),
.yuv_out_scl(yuv_out_scl),
.yuv_out_sda(yuv_out_sda),
.yuv_out_vsync(yuv_v_sync),
.yuv_out_href(yuv_h_ref),
.yuv_out_data(yuv_data)
);
//output bus
assign raw_out_vclk = raw_in_vclk;
assign raw_out_scl = raw_in_scl;
assign raw_out_sda = raw_in_sda;
assign raw_out_data = raw_in_data;
endmodule
| 7.615987 |
module tauConfig (
clk,
rst_n,
din,
sin,
dout,
sout
);
input clk;
input rst_n;
input [7:0] din;
input sin;
output reg [7:0] dout;
output reg sout;
reg [2:0] cnt;
reg [7:0] sum;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
cnt <= 3'd0;
sum <= 8'd0;
end else if (cnt < 3'd3)
if (sin) begin
cnt <= cnt + 3'd1;
sum <= sum + din;
end else begin
cnt <= cnt;
sum <= sum;
end
else begin
cnt <= 3'd0;
sum <= 8'd0;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
sout <= 1'd0;
dout <= 8'd0;
end else if (cnt == 3'd3) begin
sout <= 1'd1;
dout <= sum;
end else begin
sout <= 1'd0;
dout <= 8'd0;
end
endmodule
| 6.617546 |
module tb ();
reg reset, clk;
initial begin
clk = 0;
reset = 1;
#60;
reset = 0;
#1000;
$finish;
end
always #10 clk = !clk;
wire valid;
wire [15:0] X0, X1;
AWGN a1 (
clk,
reset,
valid,
X0,
X1
);
endmodule
| 7.195167 |
module tawas_rcn (
input clk,
input rst,
input [ 4:0] thread_decode,
output [31:0] rcn_stall,
input rcn_cs,
input rcn_xch,
input rcn_wr,
input [31:0] rcn_addr,
input [2:0] rcn_wbreg,
input [3:0] rcn_mask,
input [31:0] rcn_wdata,
output reg rcn_load_en,
output reg [4:0] rcn_load_thread,
output reg [2:0] rcn_load_reg,
output reg [31:0] rcn_load_data,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter MASTER_GROUP_8 = 0;
reg [4:0] seq;
wire rdone;
wire wdone;
wire [4:0] rsp_seq;
wire [3:0] rsp_mask;
wire [31:0] rsp_data;
wire master_full;
always @(posedge clk) seq <= thread_decode;
tawas_rcn_master_buf #(
.MASTER_GROUP_8(MASTER_GROUP_8)
) rcn_master (
.rst(rst),
.clk(clk),
.rcn_in (rcn_in),
.rcn_out(rcn_out),
.cs(rcn_cs),
.seq(seq),
.wr(rcn_wr),
.mask(rcn_mask),
.addr(rcn_addr[23:0]),
.wdata(rcn_wdata),
.full(master_full),
.rdone(rdone),
.wdone(wdone),
.rsp_seq(rsp_seq),
.rsp_mask(rsp_mask),
.rsp_addr(),
.rsp_data(rsp_data)
);
//
// Core thread stalls
//
reg rdone_d1;
reg rdone_d2;
reg rdone_d3;
reg wdone_d1;
reg wdone_d2;
reg wdone_d3;
reg [4:0] rsp_seq_d1;
reg [4:0] rsp_seq_d2;
reg [4:0] rsp_seq_d3;
always @(posedge clk) begin
rdone_d1 <= rdone;
rdone_d2 <= rdone_d1;
rdone_d3 <= rdone_d2;
wdone_d1 <= wdone;
wdone_d2 <= wdone_d1;
wdone_d3 <= wdone_d2;
rsp_seq_d1 <= rsp_seq;
rsp_seq_d2 <= rsp_seq_d1;
rsp_seq_d3 <= rsp_seq_d2;
end
reg [31:0] pending_stall;
wire [31:0] set_pending_stall = (rcn_cs) ? (32'd1 << seq) : 32'd0;
wire [31:0] clr_pending_stall = (rdone_d3 || wdone_d3) ? (32'd1 << rsp_seq_d3) : 32'd0;
always @(posedge clk or posedge rst)
if (rst) pending_stall <= 32'd0;
else pending_stall <= (pending_stall | set_pending_stall) & ~clr_pending_stall;
assign rcn_stall = pending_stall | {32{master_full}};
//
// Read retire
//
reg [2:0] wbreg[31:0];
reg xch[31:0];
always @(posedge clk)
if (rcn_cs) begin
wbreg[seq] <= rcn_wbreg;
xch[seq] <= rcn_wr && rcn_xch;
end
wire [31:0] rsp_data_adj = (rsp_mask[3:0] == 4'b1111) ? rsp_data[31:0] :
(rsp_mask[3:2] == 2'b11) ? {16'd0, rsp_data[31:16]} :
(rsp_mask[1:0] == 2'b11) ? {16'd0, rsp_data[15:0]} :
(rsp_mask[3]) ? {24'd0, rsp_data[31:24]} :
(rsp_mask[2]) ? {24'd0, rsp_data[23:16]} :
(rsp_mask[1]) ? {24'd0, rsp_data[15:8]} : {24'd0, rsp_data[7:0]};
always @* begin
rcn_load_en = rdone || (wdone && xch[rsp_seq]);
rcn_load_thread = rsp_seq;
rcn_load_reg = wbreg[rsp_seq];
rcn_load_data = rsp_data_adj;
end
endmodule
| 6.786753 |
module tawas_rcn_master (
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [4:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_GROUP_8 = 0;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [2:0] my_id = MASTER_GROUP_8;
wire my_resp = rin[68] && !rin[67] && (rin[65:63] == MASTER_GROUP_8);
wire req_valid;
wire [68:0] req;
always @(posedge clk or posedge rst)
if (rst) begin
rin <= 69'd0;
rout <= 69'd0;
end else begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
end
assign busy = rin[68] && !my_resp;
assign req_valid = cs && !(rin[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, seq[4:2], mask, addr[23:2], seq[1:0], wdata};
assign rdone = my_resp && !rin[66];
assign wdone = my_resp && rin[66];
assign rsp_seq = {rin[62:60], rin[33:32]};
assign rsp_mask = rin[59:56];
assign rsp_addr = {rin[55:34], 2'd0};
assign rsp_data = rin[31:0];
endmodule
| 7.623436 |
module tawas_rcn_master_buf (
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output full,
output rdone,
output wdone,
output [4:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_GROUP_8 = 0;
parameter DEPTH = 16; // max 64
reg [63:0] req_buf[(DEPTH - 1):0];
reg [5:0] write_ptr;
reg [5:0] read_ptr;
reg [6:0] req_cnt;
assign full = (req_cnt >= (DEPTH - 5));
wire req_push = cs && (req_cnt != DEPTH);
wire req_pop;
always @(posedge clk or posedge rst)
if (rst) req_cnt <= 7'd0;
else
case ({
req_push, req_pop
})
2'b10: req_cnt <= req_cnt + 7'd1;
2'd01: req_cnt <= req_cnt - 7'd1;
default: ;
endcase
always @(posedge clk or posedge rst)
if (rst) write_ptr <= 6'd0;
else if (req_push) write_ptr <= (write_ptr == (DEPTH - 1)) ? 6'd0 : write_ptr + 6'd1;
always @(posedge clk or posedge rst)
if (rst) read_ptr <= 6'd0;
else if (req_pop) read_ptr <= (read_ptr == (DEPTH - 1)) ? 6'd0 : read_ptr + 6'd1;
always @(posedge clk)
if (req_push)
req_buf[write_ptr] <= {seq, wr, mask[3:0], addr[23:2], wdata[31:0]};
wire req_vld = (req_cnt != 0);
wire [63:0] req = req_buf[read_ptr][63:0];
wire req_busy;
assign req_pop = req_vld && !req_busy;
tawas_rcn_master #(
.MASTER_GROUP_8(MASTER_GROUP_8)
) rcn_master (
.rst(rst),
.clk(clk),
.rcn_in (rcn_in),
.rcn_out(rcn_out),
.cs(req_vld),
.seq(req[63:59]),
.busy(req_busy),
.wr(req[58]),
.mask(req[57:54]),
.addr({req[53:32], 2'd0}),
.wdata(req[31:0]),
.rdone(rdone),
.wdone(wdone),
.rsp_seq(rsp_seq),
.rsp_mask(rsp_mask),
.rsp_addr(rsp_addr),
.rsp_data(rsp_data)
);
endmodule
| 7.623436 |
module taxicab_distance #(parameter N = 32)(
input [N-1:0] x1, y1, x2, y2,
output [N+1:0] dist
);
wire signed [N:0] dist_x12, dist_x21, dist_xabs, dist_y12, dist_y21, dist_yabs;
/*SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .S(dist_x12[N-1:0]), .CO(dist_x12[N]));
SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .S(dist_x21[N-1:0]), .CO(dist_x21[N]));*/
SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .D(dist_x12));
SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .D(dist_x21));
MUX #(.N(N+1)) abs_x (.A(dist_x12), .B(dist_x21), .S(dist_x12[N]), .O(dist_xabs));
/*SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .S(dist_y12[N-1:0]), .CO(dist_y12[N]));
SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .S(dist_y21[N-1:0]), .CO(dist_y21[N]));*/
SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .D(dist_y12));
SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .D(dist_y21));
MUX #(.N(N+1)) abs_y (.A(dist_y12), .B(dist_y21), .S(dist_y12[N]), .O(dist_yabs));
ADD #(.N(N+1))t_d (.A(dist_xabs), .B(dist_yabs), .CI(1'b0), .S(dist[N:0]), .CO(dist[N+1]));
endmodule
| 6.692693 |
module SUB_1 #(
parameter N = 32
) (
input [N-1:0] A,
B,
output [ N:0] D
);
wire CO;
assign D[N] = ~CO;
ADD #(
.N(N)
) ADD_ (
.A (A),
.B (~B),
.CI(1'b1),
.S (D[N-1:0]),
.CO(CO)
);
endmodule
| 6.563989 |
module Taximeter (
clk,
motor_cycle,
rst,
tube_11bit
);
input clk, motor_cycle, rst;
wire [3:0] distan_count_thous,
distan_count_hundr,
distan_count_tens,
distan_count_units,
price_count_hundr,
price_count_tens,
price_count_units;
wire [13:0] distan_count;
output [10:0] tube_11bit;
//计程模块
DistanCounter dcnt (
.motor_cycle(motor_cycle),
.rst(rst),
.count(distan_count)
);
//计费模块
PriceCounter pcnt (
.rst(rst),
.distan_count(distan_count),
.distan_count_thous(distan_count_thous),
.distan_count_hundr(distan_count_hundr),
.distan_count_tens(distan_count_tens),
.distan_count_units(distan_count_units),
.price_count_hundr(price_count_hundr),
.price_count_tens (price_count_tens),
.price_count_units(price_count_units)
);
//数码管显示模块
TubeControl tbctrl (
.clk(clk),
.distan_count_thous(distan_count_thous),
.distan_count_hundr(distan_count_hundr),
.distan_count_tens(distan_count_tens),
.distan_count_units(distan_count_units),
.price_count_hundr(price_count_hundr),
.price_count_tens(price_count_tens),
.price_count_units(price_count_units),
.tube_11bit(tube_11bit)
);
endmodule
| 7.228361 |
module taxi_fare (
input wire clk,
input wire rst_n,
input wire wait_en,
input wire en,
input wire [11:0] distance_fare_per_pulse,
input wire [11:0] s_fare,
input wire ten_meter_pulse,
input wire [11:0] wait_fare_per_unit,
output wire [7:0] fare_a,
output wire [7:0] fare_b,
output wire [7:0] fare_c,
output wire [7:0] fare_d,
output wire [7:0] distance_a,
output wire [7:0] distance_b
);
//设置两个参数MIN_COUNT和WAIT_COUNT，方便后续调整和仿真时覆写
//每分钟包含3_000_000_000个时钟周期，但是这里只检测了上跳沿
//所以是每1_500_000_000个周期（半分钟）翻转一次输出脉冲信号
parameter MIN_COUNT = 32'd1_500_000_000;
//每十分钟含有10个时钟周期，但是这里只检测了上跳沿
//所以是每五个周期（五分钟）翻转一次输出脉冲信号
parameter WAIT_COUNT = 4'd5;
wire min_pulse;
wire max;
wire wait_fare_pulse;
wire [15:0] wait_fare_bcd;
wire [7:0] distance_bcd;
wire [15:0] distance_fare_bcd;
wire [15:0] fare_total_bcd;
freq_div #(
.MIN_COUNT(MIN_COUNT)
) u_freq_div (
.clk (clk ),
.rst_n (rst_n ),
.en (en ),
.max (max ),
.min_pulse(min_pulse)
);
wait_count #(
.WAIT_COUNT(WAIT_COUNT)
) u_wait_count (
.min_pulse(min_pulse),
.rst_n (rst_n),
.wait_fare_pulse(wait_fare_pulse)
);
wait_fare u_wait_fare (
.wait_fare_pulse (wait_fare_pulse),
.rst_n (rst_n),
.max (max),
.wait_en (wait_en),
.wait_fare_per_unit(wait_fare_per_unit),
.wait_fare_bcd(wait_fare_bcd)
);
distance_fare u_distance_fare (
.ten_meter_pulse (ten_meter_pulse),
.en (en),
.max (max),
.rst_n (rst_n),
.wait_en (wait_en),
.distance_fare_per_pulse(distance_fare_per_pulse),
.s_fare (s_fare),
.distance_bcd (distance_bcd),
.distance_fare_bcd(distance_fare_bcd)
);
fare_total u_fare_total (
.distance_fare_bcd(distance_fare_bcd),
.wait_fare_bcd(wait_fare_bcd),
.fare_total_bcd(fare_total_bcd),
.max (max)
);
seg_disp u_seg_disp (
.fare_total_bcd (fare_total_bcd ),
.distance_bcd (distance_bcd ),
.max (max ),
.fare_a (fare_a ),
.fare_b (fare_b ),
.fare_c (fare_c ),
.fare_d (fare_d ),
.distance_a (distance_a ),
.distance_b (distance_b )
);
endmodule
| 8.86996 |
module taxi_fare_tb ();
reg clk;
reg rst_n;
reg en;
reg wait_en;
reg [11:0] distance_fare_per_pulse;
reg [11:0] s_fare;
reg ten_meter_pulse;
reg [11:0] wait_fare_per_unit;
wire [ 7:0] fare_a;
wire [ 7:0] fare_b;
wire [ 7:0] fare_c;
wire [ 7:0] fare_d;
wire [ 7:0] distance_a;
wire [ 7:0] distance_b;
parameter CYCLE = 5'd20;
parameter MIN_COUNT = 4'd10;
parameter WAIT_COUNT = 3'd5;
parameter SPEED = 26'd50;
always #10 clk = ~clk;
always #SPEED ten_meter_pulse = ~ten_meter_pulse;
initial begin
clk = 1'b0;
wait_en = 1'd0;
ten_meter_pulse = 1'b0;
wait_fare_per_unit = 12'b0000_0101_0000;
rst_n = 1'b0;
en = 1'b0;
distance_fare_per_pulse = 12'b0000_0000_0011;
s_fare = 12'b0011_0000_0000;
#(CYCLE);
rst_n = 1'b1;
en = 1'b1;
#(CYCLE * 100);
wait_en = 1'b1;
#(CYCLE * 100);
wait_en = 1'b0;
#(CYCLE * 1000);
$stop;
end
taxi_fare #(
.MIN_COUNT (MIN_COUNT),
.WAIT_COUNT(WAIT_COUNT)
) u_taxi_fare (
.clk (clk),
.rst_n (rst_n),
.en (en),
.wait_en (wait_en),
.distance_fare_per_pulse(distance_fare_per_pulse),
.s_fare (s_fare),
.ten_meter_pulse (ten_meter_pulse),
.wait_fare_per_unit (wait_fare_per_unit),
.fare_a (fare_a ),
.fare_b (fare_b ),
.fare_c (fare_c ),
.fare_d (fare_d ),
.distance_a (distance_a ),
.distance_b (distance_b )
);
endmodule
| 7.908547 |
module taylor_cos (
clk_80,
rst_80,
factorial2_80,
factorial4_80,
radian_80,
cos_value_80,
add_n4_value,
n2value_80,
n4value_80,
sub_n2_value_80,
radian2_pow4_80,
radian1_pow2_80
);
input clk_80, rst_80;
input [7:0] factorial2_80, factorial4_80, radian_80;
output [7:0] cos_value_80;
output [15:0] radian1_pow2_80;
output [15:0] radian2_pow4_80;
output [7:0] add_n4_value;
output [7:0] n2value_80;
output [7:0] n4value_80;
output [7:0] sub_n2_value_80;
reg [7:0] n2value_reg3_80;
reg [7:0] n4value_reg4_80;
reg [7:0] sub_n2_value_reg4_80;
wire [7:0] rm2_80, rm4_80;
reg [7:0] radian_reg1_80;
reg [7:0] pow2_reg2_80, pow4_reg3_80, pow2_reg3_80;
wire [7:0] pow2_80, pow4_80;
reg [7:0] fact2_reg1_80, fact2_reg2_80;
reg [7:0] fact4_reg1_80, fact4_reg2_80, fact4_reg3_80;
parameter ADD = 1'b1;
parameter SUB = 1'b0;
//Stage 4
always @(posedge clk_80) begin
if (rst_80) begin
sub_n2_value_reg4_80 <= 0;
n4value_reg4_80 <= 0;
end else begin
sub_n2_value_reg4_80 <= sub_n2_value_80;
n4value_reg4_80 <= n4value_80;
end
end
add_sub_8 add_n4 (
.add_sub(ADD),
.dataa (sub_n2_value_reg4_80),
.datab (n4value_reg4_80),
.result (add_n4_value)
);
assign cos_value_80 = (rst_80) ? 0 : add_n4_value;
//Stage 3
always @(posedge clk_80) begin
if (rst_80) begin
pow4_reg3_80 <= 0;
fact4_reg3_80 <= 0;
n2value_reg3_80 <= 0;
end else begin
pow4_reg3_80 <= pow4_80;
fact4_reg3_80 <= fact4_reg2_80;
n2value_reg3_80 <= n2value_80;
end
end
//calculates 1-x2/2!
add_sub_8 sub_n2 (
.add_sub(SUB),
.dataa (128),
.datab (n2value_reg3_80),
.result (sub_n2_value_80)
);
div8 i_n4value (
.denom(fact4_reg3_80),
.numer(pow4_reg3_80),
.quotient(n4value_80),
.remain(rm4_80)
);
//Stage2
always @(posedge clk_80) begin
if (rst_80) begin
pow2_reg2_80 <= 0;
fact2_reg2_80 <= 0;
fact4_reg2_80 <= 0;
end else begin
pow2_reg2_80 <= pow2_80;
fact2_reg2_80 <= fact2_reg1_80;
fact4_reg2_80 <= fact4_reg1_80;
end
end
//calculates x^4 term
sq_8 i_pow4 (
.dataa (pow2_reg2_80),
.result(radian2_pow4_80)
);
div8 i_n2value (
.denom(fact2_reg2_80),
.numer(pow2_reg2_80),
.quotient(n2value_80),
.remain(rm2_80)
);
assign pow4_80=(radian2_pow4_80[15]==0)?((radian2_pow4_80[14:6]==9'b0111_11111)?8'b0111_1111:(radian2_pow4_80[14:7]+radian2_pow4_80[6])):((radian2_pow4_80[14:7]==8'b1000_0000)?1000_0001:(radian2_pow4_80[14:7]+radian2_pow4_80[6]));
//Stage 1
always @(posedge clk_80) begin
if (rst_80) begin
radian_reg1_80 <= 0;
fact2_reg1_80 <= 0;
fact4_reg1_80 <= 0;
end else begin
radian_reg1_80 <= radian_80;
fact2_reg1_80 <= factorial2_80;
fact4_reg1_80 <= factorial4_80;
end
end
//calculates x^2 term
sq_8 i_pow2 (
.dataa (radian_reg1_80),
.result(radian1_pow2_80)
);
assign pow2_80 =(radian1_pow2_80[15]==0)?((radian1_pow2_80[14:6]==9'b0111_11111)?8'b0111_1111:(radian1_pow2_80[14:7]+radian1_pow2_80[6])):((radian1_pow2_80[14:7]==8'b1000_0000)?1000_0001:(radian1_pow2_80[14:7]+radian1_pow2_80[6]));
endmodule
| 7.127344 |
module tb_TC3to3;
reg setn, resetn;
reg clock, sensor;
wire NS_G, NS_Y, NS_R, EW_G, EW_Y, EW_R;
wire [3:0] Q; // counter Q
tc_mealy_TC3to3 TC (
Q,
NS_G,
NS_Y,
NS_R,
EW_G,
EW_Y,
EW_R,
setn,
resetn,
clock,
sensor
); // TC
initial begin
sensor <= 1;
clock <= 0;
setn <= 0;
resetn <= 1;
#1 setn <= 1;
#18 sensor <= 0; // sensor
#30 sensor <= 1;
end
always #1 clock = ~clock;
endmodule
| 6.879433 |
module tb;
parameter INPUT_WIDTH = 16;
parameter INPUT_LENGTH = 18;
parameter INPUTS_NUMBER = 115200;
parameter OUTPUT_WIDTH = 38;
parameter OUTPUT_LENGTH = 18;
parameter FIR_WIDTH = 64;
parameter COEFF_LENGTH = 7;
reg clk, rst;
reg [ INPUT_WIDTH - 1:0] DATA_IN [0:INPUTS_NUMBER - 1];
reg [OUTPUT_WIDTH - 1:0] CORRECT_DATA[0:INPUTS_NUMBER - 1];
reg [INPUT_LENGTH - 1:0] address;
wire [ INPUT_WIDTH - 1:0] data;
reg [ INPUT_WIDTH - 1:0] FIR_input;
wire [OUTPUT_WIDTH - 1:0] FIR_output;
wire Done;
reg ready;
integer i;
integer invalid = 0;
initial $readmemb("inputs.txt", DATA_IN);
initial $readmemb("outputs.txt", CORRECT_DATA);
FILTER F (
.clk (clk),
.FIR_input (FIR_input),
.rst (rst),
.ready(ready),
.FIR_output (FIR_output),
.Done (Done)
);
// reset
initial begin
rst = 0;
#50;
rst = 1;
#23;
rst = 0;
end
// clk generation
initial clk = 1'b0;
always #10 clk = ~clk;
initial begin
FIR_input = 0;
for (i = 0; i < INPUTS_NUMBER; i = i + 1) begin
@(posedge clk) begin
FIR_input = DATA_IN[i];
$display("input_data %d : %d", i, DATA_IN[i]);
ready = 1;
@(posedge Done) begin
if (CORRECT_DATA[i] != FIR_output) begin
invalid = invalid + 1;
end
end
end
end
$display("incorrect results: %d\n", invalid);
#200;
$stop;
end
endmodule
| 6.746419 |
module tb_ban_reg_micro;
reg [5:0] Sel_reg;
reg W;
reg [7:0] DW;
wire [7:0] Rx;
wire [7:0] Ry;
reg rst;
reg clk;
ban_reg_micro uut (
.Sel_reg(Sel_reg),
.W(W),
.DW(DW),
.Rx(Rx),
.Ry(Ry),
.rst(rst),
.clk(clk)
);
initial begin
rst = 1;
clk = 0;
Sel_reg = 0;
W = 0;
DW = 0;
#2 rst = 0;
Sel_reg = 6'b000_000;
W = 0;
DW = 8'b00000000;
#2 Sel_reg = 6'b000000;
W = 1;
DW = 8'b00001010;
#2 Sel_reg = 6'b000001;
W = 1;
DW = 8'b00001011;
#2 Sel_reg = 6'b000010;
W = 1;
DW = 8'b00001100;
#2 Sel_reg = 6'b000011;
W = 1;
DW = 8'b00001101;
#2 Sel_reg = 6'b000100;
W = 1;
DW = 8'b00001110;
#2 Sel_reg = 6'b000101;
W = 1;
DW = 8'b00001111;
#2 Sel_reg = 6'b000110;
W = 1;
DW = 8'b00010000;
#2 Sel_reg = 6'b000111;
W = 1;
DW = 8'b00010001;
#2 Sel_reg = 6'b001000;
W = 0;
#2 Sel_reg = 6'b011010;
W = 0;
#2 Sel_reg = 6'b101100;
W = 0;
#2 Sel_reg = 6'b111110;
W = 0;
#3 Sel_reg = 6'b000000;
W = 1;
DW = 8'b00000001;
#2 Sel_reg = 6'b000001;
W = 1;
DW = 8'b00000011;
#2 Sel_reg = 6'b001000;
W = 1;
DW = 8'b00000100;
end
always #1 clk = !clk;
endmodule
| 6.680054 |
module tb_Bus_micro;
reg [1:0] Sel_outbus;
reg [7:0] Rx;
reg [7:0] Ry;
reg [7:0] Num;
wire [7:0] o_salida_datos;
wire [7:0] o_direccion_datos;
wire RW;
reg rst;
reg clk;
Bus_micro uut (
.Sel_outbus(Sel_outbus),
.Rx(Rx),
.Ry(Ry),
.Num(Num),
.o_salida_datos(o_salida_datos),
.o_direccion_datos(o_direccion_datos),
.RW(RW),
.rst(rst),
.clk(clk)
);
initial begin
Sel_outbus = 0;
Rx = 0;
Ry = 0;
Num = 0;
rst = 1;
clk = 0;
#2 rst = 0;
Rx = 8'd5;
Ry = 8'd6;
Num = 8'd2;
Sel_outbus = 0;
#2 Sel_outbus = 2'b01;
#2 Sel_outbus = 2'b10;
#2 Sel_outbus = 2'b11;
end
always #1 clk = !clk;
endmodule
| 6.563347 |
module tb_qint ();
// QBUS signals
reg RINIT, RDIN, RIAKI;
reg [4:7] RIRQ;
wire TIAKO;
wire [4:7] TIRQ;
// internal controls
reg interrupt_request;
wire assert_vector;
reg qclk = 1;
always @(*) #25 qclk <= ~qclk; // 20 MHz clock (50ns cycle time)
// simulate an interrupt handler
always @(*) begin
if (TIRQ) begin
#75 RDIN <= 1; // after latency, send DIN
#150 RIAKI <= 1; // then ACK
end else begin
#75 RDIN <= 0; // and release the bus
#25 RIAKI <= 0;
end
end
qint qint (
qclk,
`INTP_4,
RINIT,
RDIN,
RIRQ,
RIAKI,
TIRQ,
TIAKO,
interrupt_request,
assert_vector
);
initial begin
$dumpfile("tb-qint.lxt");
$dumpvars(0, tb_qint);
// bus idle, no requests
#0{RINIT, RDIN, RIAKI} <= 0;
RIRQ <= 0;
interrupt_request <= 0;
#100 RINIT <= 1;
#100 RINIT <= 0;
#100 interrupt_request <= 1;
#20 interrupt_request <= 0;
#1000 $finish_and_return(0);
end
endmodule
| 6.930521 |
module tsense_read_tb ();
wire CS, SCK, SIO;
reg RSTN, SYSCLK;
wire [7:0] dbugout;
wire [7:0] dataSeg;
wire [1:0] disp;
//Task for simple test
task testRead;
begin
#15 RSTN = 1'b1;
end
endtask
//Instiate LM07
LM07 tsense (
.CS (CS),
.SCK(SCK),
.SIO(SIO)
);
//Instiate DUT
LM07_read dut (
.SYSCLK(SYSCLK),
.RSTN(RSTN),
.CS(CS),
.SCK(SCK),
.SIO(SIO),
.disp(disp),
.dataSeg(dataSeg),
.dbugout(dbugout)
);
//Initialize CS
initial RSTN = 1'b0;
//Generate test clock
initial SYSCLK = 1'b1;
initial forever #10 SYSCLK = ~SYSCLK;
//Testbench
initial begin
//$monitor("time= %0t;data[]=,CS=%b,CLK=%b,SIO=%b,",$time,CS,CLK,SIO);
$dumpfile("dump.vcd");
$dumpvars(1);
testRead;
#1500 $finish(2);
end
endmodule
| 7.252947 |
module position simulation top module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
localparam K_W = 3;
reg clk;
reg rst_n;
reg next_pos;
reg [3:0] row;
reg [3:0] col;
reg [(EXP+MAN+1)*K_W-1:0] data0;
reg [(EXP+MAN+1)*K_W-1:0] data1;
initial begin
clk = 1'b1;
rst_n = 1'b0;
next_pos = 1'b0;
#10
rst_n = 1'b1;
next_pos = 1'b1;
$display("[%t] : row: %d col: %d next_pos: %b\n", $realtime, row, col, next_pos);
forever #10 clk=~clk;
end
always@(posedge clk) begin
$display("[%t] : row: %d, col: %d, next_pos: %b, data0: %h, data1: %h\n", $realtime, row, col, next_pos, data0, data1);
if((row == 4'd13) && (col == 4'd13)) begin
next_pos <= 1'b0;
$finish;
end else begin
next_pos <= 1'b1;
end
end
data_multiplexer mux(
.clk(clk),
.cnn_conv_rst_n(rst_n),
._next_pos(next_pos),
._col(col),
._row(row),
._data0(data0),
._data1(data1)
);
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
//$vcdplusglitchon;
//$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, data_multiplexer);
`endif
end
end
endmodule
| 6.711652 |
module position simulation top module
`timescale 1ns/1ps
module top;
reg clk;
reg rst_n;
reg next_pos;
reg [3:0] row;
reg [3:0] col;
reg end_pos;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
rst_n = 1'b0;
next_pos = 1'b0;
#10
rst_n = 1'b1;
next_pos = 1'b1;
$display("[%t] : row: %d col: %d next_pos: %b\n", $realtime, row, col, next_pos);
end
position position(
.clk(clk),
.cnn_conv_rst_n(rst_n),
._next_pos(next_pos),
._row(row),
._col(col),
._end_pos(end_pos)
);
always #10 clk=~clk;
always@(posedge clk) begin
$display("[%t] : row: %d col: %d next_pos: %b, end pos: %b\n", $realtime, row, col, next_pos, end_pos);
if((row == 4'd13) && (col == 4'd13)) begin
next_pos <= 1'b0;
$finish;
end else begin
next_pos <= 1'b1;
end
end
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
//$vcdplusglitchon;
//$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, position);
`endif
end
end
endmodule
| 6.711652 |
module tb ();
reg clk;
reg a;
reg b;
reg bin;
wire d;
wire borrow_out;
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
initial begin
#100;
a = 1'b0;
b = 1'b0;
bin = 1'b0;
#20;
a = 1'b0;
b = 1'b0;
bin = 1'b1;
#20 a = 1'b0;
b = 1'b1;
bin = 1'b0;
#20 a = 1'b0;
b = 1'b1;
bin = 1'b1;
#20 a = 1'b1;
b = 1'b0;
bin = 1'b0;
#20 a = 1'b1;
b = 1'b0;
bin = 1'b1;
#20 a = 1'b1;
b = 1'b1;
bin = 1'b0;
#20 $finish;
end
fullSub fa (
.clock(clk),
.a(a),
.b(b),
.bin(bin),
.d(d),
.bout(borrow_out)
);
endmodule
| 7.195167 |
module testbench;
reg clk500;
initial clk500 = 1'b0;
always #1 clk500 = ~clk500;
wire nclk;
reg nreset;
divider div (
.clk(clk500),
.nreset(nreset),
.in_factor(3),
.nclk(nclk)
);
initial begin
$dumpfile("out.vcd");
$dumpvars(0, testbench);
nreset = 0;
#10;
nreset = 1;
#1000;
$finish;
end
endmodule
| 7.015571 |
module tb19 ();
reg [ 7:0] i_a;
reg [ 7:0] i_b;
wire [15:0] o_y;
initial begin
i_a = 8'd0;
#20 i_a = 8'd10;
#20 i_a = 8'd128;
#20 i_a = 8'd255;
end
initial begin
i_b = 8'd255;
#20 i_b = 8'd128;
#20 i_b = 8'd128;
#20 i_b = 8'd255;
end
test19 unsigned_mul (
.i_a(i_a),
.i_b(i_b),
.o_y(o_y)
);
endmodule
| 6.59628 |
module tb19 ();
reg signed [ 7:0] i_a;
reg signed [ 7:0] i_b;
wire signed [14:0] o_y;
initial begin
i_a = 8'sd0;
#20 i_a = -8'sd10;
#20 i_a = -8'sd128;
#20 i_a = 8'sd127;
end
initial begin
i_b = 8'sd127;
#20 i_b = +8'sd100;
#20 i_b = -8'sd128;
#20 i_b = 8'sd127;
end
test19 unsigned_mul (
.i_a(i_a),
.i_b(i_b),
.o_y(o_y)
);
endmodule
| 6.59628 |
module tb19 ();
reg signed [ 7:0] i_a;
reg [ 7:0] i_b;
wire signed [15:0] o_y;
initial begin
i_a = 8'sd0;
#20 i_a = -8'sd10;
#20 i_a = -8'sd128;
#20 i_a = 8'sd127;
end
initial begin
i_b = 8'd127;
#20 i_b = 8'd100;
#20 i_b = 8'd255;
#20 i_b = 8'd255;
end
test19 unsigned_mul (
.i_a(i_a),
.i_b(i_b),
.o_y(o_y)
);
endmodule
| 6.59628 |
module TB1;
reg clk;
reg rst, clk_en;
wire [3:0] leds;
integer EndOfSimulation;
integer i;
parameter ONE = 1'b1;
// Initial statement for signal initialization (reset, clk, EndOfSimulation)
initial begin
clk = 0;
rst = 0;
#(10) rst = 1;
#2000 $finish;
end
// Always statement to drive the clock goes here
always begin
#(5) clk = !clk;
end
// Instantiation of the gray_4bits
gray_4bits DUT (
.clk(clk),
.clk_en(ONE),
.rst(rst),
.gray_out(leds)
);
endmodule
| 6.883055 |
module top_module ();
reg clk, in, out;
reg [2:0] s;
initial begin
#0 clk = 0;
in = 0;
s = 3'd2;
#10 s = 3'd6;
#10 s = 3'd2;
in = 1;
#10 s = 3'd7;
in = 0;
#10 s = 3'd0;
in = 1;
#30 in = 0;
end
always begin
#5 clk = ~clk;
end
q7 q (
clk,
in,
s,
out
);
endmodule
| 6.627149 |
module tb20;
reg [7:0] i_data;
wire [3:0] o_count;
initial begin
i_data = 8'b1111_1111;
#100 repeat (51) #20 i_data = i_data - 'd5;
end
count1s count1s (
.i_data (i_data),
.o_count(o_count)
);
endmodule
| 6.685379 |
module tb_edge_det;
reg clk, rst_n, data;
wire rise_edge;
wire fall_edge;
wire data_edge;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(posedge clk) data = {$random};
end
$finish;
end
initial begin
$dumpfile("seq101_tb.vcd");
$dumpvars();
end
edge_det edge_det (
.clk (clk),
.rst_n (rst_n),
.data (data),
.rise_edge(rise_edge),
.fall_edge(fall_edge),
.data_edge(data_edge)
);
endmodule
| 6.661764 |
module tb28 ();
reg clk, rst_n, data_i;
wire [7:0] data_o;
initial
fork
clk = 1'b0;
rst_n = 1'b0;
#20 rst_n = 1'b1;
#10 data_i = 1'b1;
join
always #10 clk = ~clk;
always #15 data_i = ~data_i;
test28 test28 (
.clk (clk),
.rst_n (rst_n),
.data_i(data_i),
.data_o(data_o)
);
endmodule
| 6.693302 |
module tb29 ();
reg clk, rst_n, data;
wire flag_101;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(negedge clk) data = {$random};
end
$finish;
end
/* initial begin
$dumpfile("seq101_tb.vcd");
$dumpvars();
end */
test29 test29 (
.clk (clk),
.rst_n (rst_n),
.data (data),
.flag_101(flag_101)
);
endmodule
| 6.704709 |
module TB2;
parameter N = 4;
reg clk, rst, clk_en;
wire [3:0] leds;
integer EndOfSimulation;
integer i;
parameter ONE = 1'b1;
// Initial statement for signal initialization (reset, clk, EndOfSimulation)
initial begin
clk = 0;
rst = 0;
#20 rst = 1;
#30 rst = 0;
#20 rst = 1;
#2000 $finish;
end
// Always statement to drive the clock goes here
always begin
#5 clk = !clk;
end
// Instantiation of the gray_Nbits goes here
gray_Nbits Nbits_counter (
.clk(clk),
.clk_en(ONE),
.rst(rst),
.gray_out(leds)
);
endmodule
| 7.42332 |
module tb ();
reg cin;
wire cout;
wire good;
reg c;
reg [31:0] Operand1;
reg [31:0] Operand2;
wire [31:0] Result;
reg [31:0] sum;
m_adder m_adder (
.i_cIn_1 (cin),
.i_adderOperand1_32(Operand1),
.i_adderOperand2_32(Operand2),
.o_adderSum_32 (Result),
.o_cOut_1 (cout)
);
initial begin
cin = 0;
Operand1 = 0;
Operand2 = 0;
repeat (100) begin
#10 cin = {$random} % 2;
Operand1 = {$random} % 32'hFFFFFFFF;
Operand2 = {$random} % 32'hFFFFFFFF;
{c, sum} = Operand1 + Operand2 + cin;
if (!good) $finish;
end
$finish;
end
assign good = Result == sum && c == cout;
endmodule
| 7.002324 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_valid
);
initial begin
$dumpfile("lab10.vcd"); //gtkwave
$dumpvars;
CLK = 1'b0;
#10 reset = 1; //正數*正數
temp_a = 32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //正數*負數
temp_a = 32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //負數*正數
temp_a = -32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //負數*負數
temp_a = -32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //無號最大數*無號最大數
temp_a = 64'd4294967295;
temp_b = 64'd4294967295;
#20 reset = 0;
#680 reset = 1; //無號溢位數*1
temp_a = 64'd4294967296;
temp_b = 64'd1;
#20 reset = 0;
#680 reset = 1; //無號溢位數*1
temp_a = 64'd4294967297;
temp_b = 64'd1;
#20 reset = 0;
#680 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if(reset)//初始化
begin
count <= 0;
in_a <= temp_a;
in_b <= temp_b;
correct_ans <= 0;
error <= 0;
end else //對答案
begin
correct_ans <= temp_a * temp_b;
count <= count + 1;
if (out_valid == 1)
if (out != correct_ans) begin
error <= 1;
$display();
$display("// Fail //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, but correct answer is %d\n", out, correct_ans);
end else begin
error <= 0;
$display();
$display("// Successful //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, correct answer is %d\n", out, correct_ans);
end
end
end
endmodule
| 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_valid
);
initial begin
$dumpfile("lab10.vcd"); //gtkwave
$dumpvars;
CLK = 1'b0;
#10 reset = 1; //正數*正數
temp_a = 32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //正數*負數
temp_a = 32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //負數*正數
temp_a = -32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //負數*負數
temp_a = -32'd30;
temp_b = -32'd90;
#20 reset = 0;
/*#680 reset = 1;//無號最大數*無號最大數
temp_a = 64'd4294967295;
temp_b = 64'd4294967295;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967296;
temp_b = 64'd1;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967297;
temp_b = 64'd1;
#20 reset = 0;*/
#680 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if(reset)//初始化
begin
count <= 0;
in_a <= temp_a;
in_b <= temp_b;
correct_ans <= 0;
error <= 0;
end else //對答案
begin
correct_ans <= temp_a * temp_b;
count <= count + 1;
if (out_valid == 1)
if ($signed(out) != correct_ans) begin
error <= 1;
$display();
$display("// Fail //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, but correct answer is %d\n", $signed(out), correct_ans);
end else begin
error <= 0;
$display();
$display("// Successful //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, correct answer is %d\n", $signed(out), correct_ans);
end
end
end
endmodule
| 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [1:0] state;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_valid,
state
);
initial begin
$dumpfile("lab10.vcd"); //gtkwave
$dumpvars;
CLK = 1'b0;
#10 reset = 1; //正數*正數
temp_a = 32'd30;
temp_b = 32'd90;
state = 2'd3;
#20 reset = 0;
#680 reset = 1; //正數*負數
temp_a = 32'd30;
temp_b = -32'd90;
state = 2'd1;
#20 reset = 0;
#680 reset = 1; //負數*正數
temp_a = -32'd30;
temp_b = 32'd90;
state = 2'd2;
#20 reset = 0;
#680 reset = 1; //負數*負數
temp_a = -32'd30;
temp_b = -32'd90;
state = 2'd3;
#20 reset = 0;
/*#680 reset = 1;//無號最大數*無號最大數
temp_a = 64'd4294967295;
temp_b = 64'd4294967295;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967296;
temp_b = 64'd1;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967297;
temp_b = 64'd1;
#20 reset = 0;*/
#680 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if(reset)//初始化
begin
count <= 0;
in_a <= temp_a;
in_b <= temp_b;
correct_ans <= 0;
error <= 0;
end else //對答案
begin
if (state == 2'd3) correct_ans <= temp_a * temp_b;
if (state == 2'd2) correct_ans <= temp_a * temp_a;
if (state == 2'd1) correct_ans <= temp_b * temp_b;
count <= count + 1;
if (out_valid == 1)
if ($signed(out) != correct_ans) begin
error <= 1;
$display();
$display("// Fail //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, but correct answer is %d\n", $signed(out), correct_ans);
end else begin
error <= 0;
$display();
$display("// Successful //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, correct answer is %d\n", $signed(out), correct_ans);
end
end
end
endmodule
| 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_valid
);
initial begin
$dumpfile("lab10.vcd"); //gtkwave
$dumpvars;
CLK = 1'b0;
#10 reset = 1; //正數*正數
temp_a = 32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //正數*負數
temp_a = 32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //負數*正數
temp_a = -32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //負數*負數
temp_a = -32'd30;
temp_b = -32'd90;
#20 reset = 0;
/*#680 reset = 1;//無號最大數*無號最大數
temp_a = 64'd4294967295;
temp_b = 64'd4294967295;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967296;
temp_b = 64'd1;
#20 reset = 0;
#680 reset = 1;//無號溢位數*1
temp_a = 64'd4294967297;
temp_b = 64'd1;
#20 reset = 0;*/
#680 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if(reset)//初始化
begin
count <= 0;
in_a <= temp_a;
in_b <= temp_b;
correct_ans <= 0;
error <= 0;
end else //對答案
begin
correct_ans <= temp_a * temp_b;
count <= count + 1;
if (out_valid == 1)
if ($signed(out) != correct_ans) begin
error <= 1;
$display();
$display("// Fail //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, but correct answer is %d\n", $signed(out), correct_ans);
end else begin
error <= 0;
$display();
$display("// Successful //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, correct answer is %d\n", $signed(out), correct_ans);
end
end
end
endmodule
| 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [64:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_valid
);
initial begin
$dumpfile("lab10.vcd"); //gtkwave
$dumpvars;
CLK = 1'b0;
#10 reset = 1; //正數*正數
temp_a = 32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //正數*負數
temp_a = 32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //負數*正數
temp_a = -32'd30;
temp_b = 32'd90;
#20 reset = 0;
#680 reset = 1; //負數*負數
temp_a = -32'd30;
temp_b = -32'd90;
#20 reset = 0;
#680 reset = 1; //無號最大數*無號最大數
temp_a = 64'd4294967295;
temp_b = 64'd4294967295;
#20 reset = 0;
#680 reset = 1; //無號溢位數*1
temp_a = 64'd4294967296;
temp_b = 64'd1;
#20 reset = 0;
#680 reset = 1; //無號溢位數*1
temp_a = 64'd4294967297;
temp_b = 64'd1;
#20 reset = 0;
#680 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if(reset)//初始化
begin
count <= 0;
in_a <= temp_a;
in_b <= temp_b;
correct_ans <= 0;
error <= 0;
end else //對答案
begin
correct_ans <= temp_a * temp_b;
count <= count + 1;
if (out_valid == 1)
if (out != correct_ans) begin
error <= 1;
$display();
$display("// Fail //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, but correct answer is %d\n", out, correct_ans);
end else begin
error <= 0;
$display();
$display("// Successful //");
$display("//%d * %d = ?", temp_a, temp_b);
$display("//your answer is %d, correct answer is %d\n", out, correct_ans);
end
end
end
endmodule
| 6.893211 |
module tb32reg;
reg [31:0] d;
reg clk, reset;
wire [31:0] q;
reg_32bit R (
q,
d,
clk,
reset
);
initial begin
$monitor($time, " output :%b", q);
end
always @(clk) #5 clk <= ~clk;
initial begin
clk = 1'b1;
reset = 1'b0; //reset the register
#20 reset = 1'b1;
#40 d = 32'hAFAFAFAF;
#40 d = 32'hFFFFFFFF;
#200 $finish;
end
endmodule
| 7.21149 |
module TB3;
parameter N = 4;
parameter cycle = 10;
parameter distance = 100000000; //
reg clk, rst, clk_en;
wire [N-1:0] leds;
integer EndOfSimulation;
// Drive the reset and the EndOfSimulation signal
initial begin
// Your code goes here
clk = 0;
rst = 0;
#20 rst = 1;
#distance $finish;
end
// Drive the clock
always begin
// Your code goes here
#(cycle / 2) clk = !clk;
end
// Instantiate the System in the testbench
// Your code goes here
GrayCounter_System my_system (
.clk (clk),
.rst (rst),
.leds(leds)
);
endmodule
| 6.735825 |
module tb43 ();
reg clk;
reg rst_n;
reg [ 7:0] i_data;
wire [10:0] o_y;
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
#3000 $finish;
end
always @(posedge clk) i_data = {$random};
test43 #(8, 8) test43 (
.clk (clk),
.rst_n (rst_n),
.i_data(i_data),
.o_y (o_y)
);
endmodule
| 6.819205 |
module tb44 ();
reg clk;
reg rst_n;
reg [7:0] i_data;
wire [7:0] o_y;
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
// #1000 $finish;
end
always @(negedge clk) i_data = {$random};
test44 test44 (
.clk (clk),
.rst_n (rst_n),
.i_data(i_data),
.o_y (o_y)
);
endmodule
| 7.028711 |
module TB3;
parameter N = 4;
parameter cycle = 10;
parameter distance = 100000000; //
reg clk, rst, clk_en;
wire [N-1:0] leds;
integer EndOfSimulation;
// Drive the reset and the EndOfSimulation signal
initial begin
// Your code goes here
clk = 0;
rst = 1;
#20 rst = 0;
#distance $finish;
end
// Drive the clock
always begin
// Your code goes here
#(cycle / 2) clk = !clk;
end
// Instantiate the System in the testbench
// Your code goes here
GrayCounter_System my_system (
.clk (clk),
.rst (rst),
.leds(leds)
);
endmodule
| 6.735825 |
module tb_cnt( );
reg clk,rst_n;
wire [3:0] o_cnt;
initial fork
clk = 1'b0;
rst_n = 1'b0;
#20 rst_n = 1'b1;
#455 rst_n = 1'b0;
#475 rst_n = 1'b1;
#600 $finish;
join
always #10 clk = ~ clk;
cnt** cnt4(
.clk (clk ),
.rst_n (rst_n),
.o_cnt (o_cnt)
);
endmodule
| 6.857027 |
module tb ();
reg cin;
wire cout;
wire good;
reg c;
reg [63:0] Operand1;
reg [63:0] Operand2;
wire [63:0] Result;
reg [63:0] sum;
m_adder m_adder (
.i_cIn_1 (cin),
.i_adderOperand1_64(Operand1),
.i_adderOperand2_64(Operand2),
.o_adderSum_64 (Result),
.o_cOut_1 (cout)
);
initial begin
cin = 0;
Operand1 = 0;
Operand2 = 0;
repeat (100) begin
#10 cin = {$random} % 2;
Operand1 = {{$random} % 32'hFFFFFFFF, {$random} % 32'hFFFFFFFF};
Operand2 = {{$random} % 32'hFFFFFFFF, {$random} % 32'hFFFFFFFF};
{c, sum} = Operand1 + Operand2 + cin;
if (!good) $finish;
end
$finish;
end
assign good = Result == sum && c == cout;
endmodule
| 7.002324 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bloodAbnormalityDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBbloodAbnormalityDetector;
// Inputs
reg [3:0] bloodPH;
reg [2:0] bloodType;
// Outputs
wire bloodAbnormality;
// Instantiate the Unit Under Test (UUT)
bloodAbnormalityDetector uut (
.bloodPH(bloodPH),
.bloodType(bloodType),
.bloodAbnormality(bloodAbnormality)
);
initial begin
bloodType = 3'b000; //AB+
bloodPH = 4'b0111; //7 normal
#10
bloodType = 3'b000; //AB+
bloodPH = 4'b0110; //6 abnormal
#10
bloodType = 3'b010; //A+
bloodPH = 4'b0111; //7 normal
#10
bloodType = 3'b010; //A+
bloodPH = 4'b0110; //6 abnormal
#10
bloodType = 3'b100; //B+
bloodPH = 4'b0111; //7 normal
#10
bloodType = 3'b100; //B+
bloodPH = 4'b0101; //5 abnormal
#10
bloodType = 3'b110; //B+
bloodPH = 4'b0111; //7 normal
#10
bloodType = 3'b110; //B+
bloodPH = 4'b0101; //5 abnormal
#10
$finish;
end
endmodule
| 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bloodPHAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBbloodPHAnalyzer;
// Inputs
reg [3:0] bloodPH;
// Outputs
wire abnormalityP;
wire abnormalityQ;
// Instantiate the Unit Under Test (UUT)
bloodPHAnalyzer uut (
.bloodPH(bloodPH),
.abnormalityP(abnormalityP),
.abnormalityQ(abnormalityQ)
);
initial begin
// Initialize Inputs
bloodPH = 4'b0000;
#10
bloodPH = 4'b0110;
#10
bloodPH = 4'b0111;
#10
bloodPH = 4'b1000;
#10
bloodPH = 4'b1001;
#10
bloodPH = 4'b1111;
#10
$finish;
end
endmodule
| 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: BloodTypeclassification
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBBloodTypeclassification;
// Inputs
reg [2:0] bloodType;
// Outputs
wire blood_output;
// Instantiate the Unit Under Test (UUT)
BloodTypeclassification uut (
.bloodType(bloodType),
.blood_output(blood_output)
);
initial begin
// Initialize Inputs
bloodType = 3'b000;
#20
bloodType = 3'b001;
#20
bloodType = 3'b010;
#20
bloodType = 3'b011;
#20
bloodType = 3'b100;
#20
bloodType = 3'b101;
#20
bloodType = 3'b110;
#20
bloodType = 3'b111;
#20
$finish;
end
endmodule
| 8.163945 |
module tbBRL ();
reg clk, rst_n, en;
initial begin
en = `ON;
clk = `HIGH;
rst_n = `HIGH;
#44 rst_n = `LOW;
#15 rst_n = `HIGH;
end
always #1 clk = ~clk;
reg [31:0] tmp;
always #4 tmp = $random;
//reg en;
//wire wave;
//wire end_tick;
//reg [7:0] mem[99:0];
//reg [9:0] cyc_duty;
//reg [7:0] index;
//initial
//begin
//$readmemh("rtl/sine.dat", mem);
//en = `ON;
//index = 8'd0;
//end
//always @(posedge clk)
//begin
//if (end_tick == `ON)
//begin
//if (index == 8'd99)
//index <= 8'd0;
//else
//index <= index + 8'd1;
//end
//end
//always @(posedge clk)
//begin
//cyc_duty <= mem[index];
//end
//zPWM
//#(//[>autoinstparam<]
//// Parameters
//.pWIDTH (10),
//.pPERIOD (210),
//.pINC (5))
//mzPWM
//(
//// Outputs
//.wave (wave),
//// Inputs
//.en (en),
//.clk (clk),
//.rst_n (rst_n),
//// Outputs
//.end_tick (end_tick),
//// Inputs
//.cyc_duty (cyc_duty)
//[>autoinst<]
//);
wire wave;
zBRL #( ///*autoinstparam*/
// Parameters
.pCLK_FQ (1),
.pCARRIER_PRD (2)
) mzBRL ( ///*autoinst*/
// Outputs
.wave (wave),
// Inputs
.en (en),
.clk (clk),
.rst_n(rst_n)
);
endmodule
| 7.131318 |
module tbDoodle ();
localparam SCR_W = 30;
localparam SCR_H = 30;
localparam COUNT_PIXELS = SCR_W * SCR_H;
wire [23:0][COUNT_PIXELS - 1:0] screen; // r,g,b (8bit, 8bit, 8bit)
reg left, right, clk, reset;
GameBox _gameBox (
screen,
left,
right,
clk,
reset
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tbDoodle);
$monitor("time: %t, clk: %b, ph: %b", $time, clk, _gameBox.physicsUpdate);
reset = 0;
clk = 0;
#10 reset = 1;
clk = 0;
#10 reset = 0;
#40 left = 1;
#20 left = 0;
#40 right = 1;
#20 right = 0;
#40 left = 1;
#20 left = 0;
#40 right = 1;
#20 right = 0;
#40 left = 1;
#20 left = 0;
#40 right = 1;
#20 right = 0;
#40 left = 1;
#40 left = 0;
#40 right = 1;
#20 right = 0;
#40 left = 1;
#20 left = 0;
#60 left = 0;
#40 right = 1;
#20 right = 0;
#40 left = 1;
#20 left = 0;
#1250 $finish();
end
always begin
#10 clk = ~clk;
end
endmodule
| 6.685467 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: EightBitRippleCarryAdder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBEightBitRippleCarryAdder;
// Inputs
reg [7:0] A;
reg [7:0] B;
wire [7:0]S ;
wire c8;
// Instantiate the Unit Under Test (UUT)
EightBitRippleCarryAdder uut (
.A(A) , .B(B) , .S(S) , .c8(c8)
);
initial begin
A = 8'b10101010;
B = 8'b01010100;
#10
A = 8'b10010010;
B = 8'b10001001;
#10
$finish;
end
endmodule
| 8.163945 |
module tben (
output _this,
output inho,
input _bit,
input inhi
);
wire bit_n;
// ARITH.NET (504) - inho : or2
assign inho = _bit | inhi;
// ARITH.NET (505) - bit\ : iv
assign bit_n = ~_bit;
// ARITH.NET (506) - this : nr2
assign _this = ~(bit_n | inhi);
endmodule
| 6.69306 |
module tbenw (
output _this,
input _bit,
input inhi
);
wire bit_n;
// ARITH.NET (516) - bit\ : iv
assign bit_n = ~_bit;
// ARITH.NET (517) - this : nr2
assign _this = ~(bit_n | inhi);
endmodule
| 6.784942 |
module tbfifosemaphore;
parameter initialCount = 1;
integer semaphore_count;
integer first_waiting_pid;
integer last_waiting_pid;
integer resume_pid;
initial begin
semaphore_count = initialCount;
first_waiting_pid = 1;
last_waiting_pid = 0;
resume_pid = 0;
end
function integer GetNumberOfProcessesWaiting;
input dummy;
begin
GetNumberOfProcessesWaiting = last_waiting_pid - first_waiting_pid + 1;
end
endfunction
function integer GetPidIfNecessary;
input dummy;
begin
if (semaphore_count == 0 || GetNumberOfProcessesWaiting(
0
) >= semaphore_count) begin // if other processes are waiting for the semaphore,
// give them priority.
if (GetNumberOfProcessesWaiting(0) == 0) begin
last_waiting_pid = 1;
first_waiting_pid = 1;
end else begin
last_waiting_pid = last_waiting_pid + 1;
end
GetPidIfNecessary = last_waiting_pid;
end else begin
GetPidIfNecessary = 0;
end
end
endfunction
task WaitComplete;
input [31:0] pid;
begin
if (pid != 0) begin
// reset queue to empty if this is the last pid on queue
if (first_waiting_pid == last_waiting_pid) begin
first_waiting_pid = 1;
last_waiting_pid = 0;
end else // otherwise, pull this pid of the queue
begin
first_waiting_pid = first_waiting_pid + 1;
end
resume_pid = 0;
end
semaphore_count = semaphore_count - 1;
end
endtask
task Post;
begin
semaphore_count = semaphore_count + 1;
if (GetNumberOfProcessesWaiting(0) > 0) begin
// if this semaphore has already been posted, but the first waiting
// process has not had a chance to respond, then wait for that process
// to respond.
if (resume_pid == first_waiting_pid) begin
@(first_waiting_pid);
end
resume_pid = first_waiting_pid;
end
end
endtask
endmodule
| 6.940023 |
module TBGlycemiclndexCalculator;
reg [7:0] bloodSensor;
wire [3:0] glycemicIndex;
GlycemiclndexCalculator q (
.bloodSensor,
.glycemicIndex
);
initial begin
bloodSensor = 8'b10101010;
#10 bloodSensor = 8'b00010010;
#10 bloodSensor = 8'b10011111;
#10 bloodSensor = 8'b01110001;
#10 $finish;
end
endmodule
| 7.230468 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: HealthcareSystemPhase1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBHealthcareSystemPhase1;
// Inputs
reg [5:0] pressureData;
reg [3:0] bloodPH;
reg [2:0] bloodType;
reg [7:0] fdSensorValue;
reg [7:0] fdFactoryValue;
reg [7:0] bloodSensor;
reg [4:0] factotyBaseTemp;
reg [3:0] factotyTempCoef;
reg [3:0] tempSensorValue;
// Outputs
wire presureAbnormality;
wire bloodAbnormality;
wire [3:0] glycemicIndex;
wire lowTempAbnormality;
wire highTempAbnormality;
wire fallDetected;
// Instantiate the Unit Under Test (UUT)
HealthcareSystemPhase1 uut (
.pressureData(pressureData),
.bloodPH(bloodPH),
.bloodType(bloodType),
.fdSensorValue(fdSensorValue),
.fdFactoryValue(fdFactoryValue),
.bloodSensor(bloodSensor),
.factotyBaseTemp(factotyBaseTemp),
.factotyTempCoef(factotyTempCoef),
.tempSensorValue(tempSensorValue),
.presureAbnormality(presureAbnormality),
.bloodAbnormality(bloodAbnormality),
.glycemicIndex(glycemicIndex),
.lowTempAbnormality(lowTempAbnormality),
.highTempAbnormality(highTempAbnormality),
.fallDetected(fallDetected)
);
initial begin
// Initialize Inputs
pressureData=6'b001000;
bloodPH = 4'b0000;
bloodType = 3'b000;
fdSensorValue= 8'b00001000;
fdFactoryValue=8'b00100000;
factotyBaseTemp = 5'b10101;
factotyTempCoef = 4'b1111;
tempSensorValue = 4'b1100;
#10
pressureData=6'b010000;
bloodPH = 4'b0110;
bloodType = 3'b001;
fdSensorValue= 8'b00100000;
fdFactoryValue =8'b00100000;
factotyBaseTemp = 5'b10011;
factotyTempCoef = 4'b1011;
tempSensorValue = 4'b1010;
bloodSensor = 8'b10101010;
#10
pressureData=6'b010101;
bloodPH = 4'b0111;
bloodType = 3'b010;
fdSensorValue =8'b00101000;
fdFactoryValue=8'b00100000;
factotyBaseTemp = 5'b11011;
factotyTempCoef = 4'b1111;
tempSensorValue = 4'b1110;
bloodSensor = 8'b00010010;
#10
$finish;
end
endmodule
| 8.163945 |
module i2c_controller_tb ();
// Inputs
reg clk;
reg rst;
reg [6:0] addr;
reg [7:0] data_in;
reg enable;
reg rw;
// Outputs
wire [7:0] data_out;
wire ready;
// Bidirs_ios
wire i2c_sda;
wire i2c_scl;
// Instantiate the Unit Under Test (UUT)
i2cmaster master (
.clk(clk),
.rst(rst),
.addr(addr),
.data_in(data_in),
.enable(enable),
.rw(rw),
.data_out(data_out),
.ready(ready),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl)
);
i2cslave slave (
.sda(i2c_sda),
.scl(i2c_scl)
);
initial begin
clk = 0;
forever begin
clk = #1 ~clk;
end
end
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus
rst = 0;
addr = 7'b0101010;
data_in = 8'b10101010;
rw = 0;
enable = 1;
#10;
enable = 0;
#500 $finish;
end
endmodule
| 7.808223 |
module tbird_fsm (
input clk,
reset,
left,
right,
haz,
output reg [5:0] light
);
//------------------------------------------------------------------
// Registry States
//------------------------------------------------------------------
reg [2:0] state, nextstate;
//------------------------------------------------------------------
// Local Parameters All Possible States
//------------------------------------------------------------------
parameter
IDLE = 3'b000,
R1 = 3'b001,
R2 = 3'b010,
R3 = 3'b011,
L1 = 3'b100,
L2 = 3'b101,
L3 = 3'b110,
HAZARD = 3'b111;
//------------------------------------------------------------------
// Change Current to Next State
//------------------------------------------------------------------
always @(negedge clk or posedge reset) begin
if (reset) state <= IDLE;
else state <= nextstate;
end
//------------------------------------------------------------------
// Starting Immediate Hazard Sequence "when haz == 1"
//------------------------------------------------------------------
always @(posedge haz) state <= HAZARD;
always @(negedge haz) state <= IDLE;
//------------------------------------------------------------------
// Next State Selection
// "Comments describe every state transiton according to STG"
//------------------------------------------------------------------
always @(*) begin
nextstate <= IDLE;
case (state)
IDLE: begin
if (!left && !right) nextstate = IDLE; //IDLE when left == 0 and right == 0
if (right) nextstate <= R1; //R1 when right == 1
if (left) nextstate <= L1; //L1 when right == 1
if (haz) nextstate <= HAZARD; //HAZARD when haz == 1
end
L1: nextstate <= L2; //L2 when haz == 0
L2: nextstate <= L3; //L3 when haz == 0
L3: nextstate <= IDLE; //Always transits to IDLE
R1: nextstate <= R2; //R2 when haz == 0
R2: nextstate <= R3; //R3 when haz == 0
R3: nextstate <= IDLE; //Always transits to IDLE
HAZARD: nextstate <= IDLE; //Always transits to IDLE
endcase
end
//---------------------------------------------------------------
// Output Combinational Logic
//---------------------------------------------------------------
always @(*) begin
light <= 6'b000000;
case (state)
HAZARD: light <= 6'b111111;
IDLE: light <= 6'b000000;
L1: light <= 6'b001000;
L2: light <= 6'b011000;
L3: light <= 6'b111000;
R1: light <= 6'b000100;
R2: light <= 6'b000110;
R3: light <= 6'b000111;
endcase
end
endmodule
| 8.768871 |
module TBLC #(
parameter M = 11
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=11, tlog[8:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y;
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin
k = 4'b1111;
y = x[14:10];
end
16'b0100_0000_0000_0000: begin
k = 4'b1110;
y = x[13:9];
end
16'b0010_0000_0000_0000: begin
k = 4'b1101;
y = x[12:8];
end
16'b0001_0000_0000_0000: begin
k = 4'b1100;
y = x[11:7];
end
/*2.*/
16'b0000_1000_0000_0000: begin
k = 4'b1011;
y = x[10:6];
end
16'b0000_0100_0000_0000: begin
k = 4'b1010;
y = x[9:5];
end
16'b0000_0010_0000_0000: begin
k = 4'b1001;
y = x[8:4];
end
16'b0000_0001_0000_0000: begin
k = 4'b1000;
y = x[7:3];
end
/*3.*/
16'b0000_0000_1000_0000: begin
k = 4'b0111;
y = x[6:2];
end
16'b0000_0000_0100_0000: begin
k = 4'b0110;
y = x[5:1];
end
16'b0000_0000_0010_0000: begin
k = 4'b0101;
y = x[4:0];
end
16'b0000_0000_0001_0000: begin
k = 4'b0100;
y = {x[3:0], 1'b0};
end
/*4.*/
16'b0000_0000_0000_1000: begin
k = 4'b0011;
y = {x[2:0], 2'b0};
end
16'b0000_0000_0000_0100: begin
k = 4'b0010;
y = {x[1:0], 3'b0};
end
16'b0000_0000_0000_0010: begin
k = 4'b0001;
y = {x[0], 4'b0};
end
16'b0000_0000_0000_0001: begin
k = 4'b0000;
y = 5'b0;
end
default: begin
k = 4'b0000;
y = 5'b0;
end
endcase
end
endmodule
| 6.986891 |
module TBLC_11 #(
parameter M = 11
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=11, tlog[8:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y; /* M=11, y[4:0] */
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin
k = 4'b1111;
y = x[14:10];
end
16'b0100_0000_0000_0000: begin
k = 4'b1110;
y = x[13:9];
end
16'b0010_0000_0000_0000: begin
k = 4'b1101;
y = x[12:8];
end
16'b0001_0000_0000_0000: begin
k = 4'b1100;
y = x[11:7];
end
/*2.*/
16'b0000_1000_0000_0000: begin
k = 4'b1011;
y = x[10:6];
end
16'b0000_0100_0000_0000: begin
k = 4'b1010;
y = x[9:5];
end
16'b0000_0010_0000_0000: begin
k = 4'b1001;
y = x[8:4];
end
16'b0000_0001_0000_0000: begin
k = 4'b1000;
y = x[7:3];
end
/*3.*/
16'b0000_0000_1000_0000: begin
k = 4'b0111;
y = x[6:2];
end
16'b0000_0000_0100_0000: begin
k = 4'b0110;
y = x[5:1];
end
16'b0000_0000_0010_0000: begin
k = 4'b0101;
y = x[4:0];
end
16'b0000_0000_0001_0000: begin
k = 4'b0100;
y = {x[3:0], 1'b0};
end
/*4.*/
16'b0000_0000_0000_1000: begin
k = 4'b0011;
y = {x[2:0], 2'b0};
end
16'b0000_0000_0000_0100: begin
k = 4'b0010;
y = {x[1:0], 3'b0};
end
16'b0000_0000_0000_0010: begin
k = 4'b0001;
y = {x[0], 4'b0};
end
16'b0000_0000_0000_0001: begin
k = 4'b0000;
y = 5'b0;
end
default: begin
k = 4'b0000;
y = 5'b0;
end
endcase
end
endmodule
| 6.779167 |
module TBLC_5 #(
parameter M = 5
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=5 , tlog[14:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y; /* M=5 , y[10:0] */
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin
k = 4'b1111;
y = x[14:4];
end
16'b0100_0000_0000_0000: begin
k = 4'b1110;
y = x[13:3];
end
16'b0010_0000_0000_0000: begin
k = 4'b1101;
y = x[12:2];
end
16'b0001_0000_0000_0000: begin
k = 4'b1100;
y = x[11:1];
end
/*2.*/
16'b0000_1000_0000_0000: begin
k = 4'b1011;
y = x[10:0];
end
16'b0000_0100_0000_0000: begin
k = 4'b1010;
y = {x[9:0], 1'b0};
end
16'b0000_0010_0000_0000: begin
k = 4'b1001;
y = {x[8:0], 2'b0};
end
16'b0000_0001_0000_0000: begin
k = 4'b1000;
y = {x[7:0], 3'b0};
end
/*3.*/
16'b0000_0000_1000_0000: begin
k = 4'b0111;
y = {x[6:0], 4'b0};
end
16'b0000_0000_0100_0000: begin
k = 4'b0110;
y = {x[5:0], 5'b0};
end
16'b0000_0000_0010_0000: begin
k = 4'b0101;
y = {x[4:0], 6'b0};
end
16'b0000_0000_0001_0000: begin
k = 4'b0100;
y = {x[3:0], 7'b0};
end
/*4.*/
16'b0000_0000_0000_1000: begin
k = 4'b0011;
y = {x[2:0], 8'b0};
end
16'b0000_0000_0000_0100: begin
k = 4'b0010;
y = {x[1:0], 9'b0};
end
16'b0000_0000_0000_0010: begin
k = 4'b0001;
y = {x[0], 10'b0};
end
16'b0000_0000_0000_0001: begin
k = 4'b0000;
y = 11'b0;
end
default: begin
k = 4'b0000;
y = 11'b0;
end
endcase
end
endmodule
| 6.783806 |
module tbman (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr
);
wire [ 7:0] print_o;
wire print_wen;
wire [31:0] putint_o;
wire putint_wen;
wire [31:0] exit_o;
wire exit_wen;
wire defines_sim;
wire defines_fpga;
tbman_regs inst_tbman_regs (
.clk (clk),
.rst_n (rst_n),
.apbs_psel (apbs_psel),
.apbs_penable (apbs_penable),
.apbs_pwrite (apbs_pwrite),
.apbs_paddr (apbs_paddr),
.apbs_pwdata (apbs_pwdata),
.apbs_prdata (apbs_prdata),
.apbs_pready (apbs_pready),
.apbs_pslverr (apbs_pslverr),
.print_o (print_o),
.print_wen (print_wen),
.putint_o (putint_o),
.putint_wen (putint_wen),
.exit_o (exit_o),
.exit_wen (exit_wen),
.defines_sim_i (defines_sim),
.defines_fpga_i(defines_fpga)
);
// Testbench only: sim print and sim exit
`ifdef SIM
reg [0:1023] print_str = 1024'h0;
integer print_ptr = 0;
integer cycle_count;
always @(posedge clk or negedge rst_n)
if (!rst_n) cycle_count <= 0;
else cycle_count <= cycle_count + 1;
always @(posedge clk) begin
if (print_wen) begin
if (print_o == "\n") begin
$display("TBMAN: %s", print_str);
print_str = 1024'h0;
print_ptr = 0;
end else begin
print_str[print_ptr*8+:8] = print_o;
print_ptr = print_ptr + 1;
end
end
if (putint_wen) begin
$display("TBMAN: %h", putint_o);
end
if (exit_wen) begin
$display("TBMAN: CPU requested termination, exit code %d", exit_o);
$display("Design ran for %d cycles", cycle_count);
$finish;
end
end
`endif
`ifdef SIM
assign defines_sim = 1'b1;
`else
assign defines_sim = 1'b0;
`endif
`ifdef FPGA
assign defines_fpga = 1'b1;
`else
assign defines_fpga = 1'b0;
`endif
endmodule
| 6.938784 |
module tbman_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr,
// Register interfaces
output reg [7:0] print_o,
output reg print_wen,
output reg [31:0] putint_o,
output reg putint_wen,
output reg [31:0] exit_o,
output reg exit_wen,
input wire defines_sim_i,
input wire defines_fpga_i
);
// APB adapter
wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'hc;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;
localparam ADDR_PRINT = 0;
localparam ADDR_PUTINT = 4;
localparam ADDR_EXIT = 8;
localparam ADDR_DEFINES = 12;
wire __print_wen = wen && addr == ADDR_PRINT;
wire __print_ren = ren && addr == ADDR_PRINT;
wire __putint_wen = wen && addr == ADDR_PUTINT;
wire __putint_ren = ren && addr == ADDR_PUTINT;
wire __exit_wen = wen && addr == ADDR_EXIT;
wire __exit_ren = ren && addr == ADDR_EXIT;
wire __defines_wen = wen && addr == ADDR_DEFINES;
wire __defines_ren = ren && addr == ADDR_DEFINES;
wire [7:0] print_wdata = wdata[7:0];
wire [7:0] print_rdata;
wire [31:0] __print_rdata = {24'h0, print_rdata};
assign print_rdata = 8'h0;
wire [31:0] putint_wdata = wdata[31:0];
wire [31:0] putint_rdata;
wire [31:0] __putint_rdata = {putint_rdata};
assign putint_rdata = 32'h0;
wire [31:0] exit_wdata = wdata[31:0];
wire [31:0] exit_rdata;
wire [31:0] __exit_rdata = {exit_rdata};
assign exit_rdata = 32'h0;
wire defines_sim_wdata = wdata[0];
wire defines_sim_rdata;
wire defines_fpga_wdata = wdata[1];
wire defines_fpga_rdata;
wire [31:0] __defines_rdata = {30'h0, defines_fpga_rdata, defines_sim_rdata};
assign defines_sim_rdata = defines_sim_i;
assign defines_fpga_rdata = defines_fpga_i;
always @(*) begin
case (addr)
ADDR_PRINT: rdata = __print_rdata;
ADDR_PUTINT: rdata = __putint_rdata;
ADDR_EXIT: rdata = __exit_rdata;
ADDR_DEFINES: rdata = __defines_rdata;
default: rdata = 32'h0;
endcase
print_wen = __print_wen;
print_o = print_wdata;
putint_wen = __putint_wen;
putint_o = putint_wdata;
exit_wen = __exit_wen;
exit_o = exit_wdata;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
end else begin
end
end
endmodule
| 7.760792 |
module tbmast;
// Inputs
reg [6:0] address;
reg [7:0] register;
reg [7:0] data;
reg [7:0] data_wr;
reg clk;
reg rw;
// Outputs
wire sda;
wire scl;
// Instantiate the Unit Under Test (UUT)
master uut (
.address(address),
.register(register),
.clk(clk),
.rw(rw),
.sda(sda),
.scl(scl),
.data(data),
.data_wr(data_wr)
);
initial begin
// Initialize Inputs
address = 105;
register = 7'b0100101;
clk = 0;
rw = 0;
data_wr = 20;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #1 clk = !clk;
endmodule
| 6.791259 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Multiplier4x4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TBMultiplier4x4;
// Inputs
reg [3:0] A;
reg [3:0] B;
wire [7:0]R;
// Instantiate the Unit Under Test (UUT)
Multiplier4x4 uut (
.A(A) , .B(B) , .R(R)
);
initial begin
A = 4'b0000;
B = 4'b1010;
#10
A = 4'b0101;
B = 4'b1010;
#10
A = 4'b0110;
B = 4'b1001;
#10
$finish;
end
endmodule
| 8.163945 |
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