code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_clock_generator (
input [7:1] i_clkdiv,
input [63:0] i_clkperiod
);
// ---------------- TBench signal --------------------------------
reg clk_tb = ~0; // start with falling edge
always @ (clk_tb)
begin
clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end
reg rst_tb = ~0; // start inactive
initial
begin
#1;
// activate reset
rst_tb <= ~0;
rst_tb <= #(`RST_PERIOD) 0;
end
// ---------------- TBench logic signal ------------------------
// configuration signals
reg r_clkon = 'b0; // start disabled
wire w_clk;
// ---------------- device-under-test (DUT) ------------------------
clock_generator dut (
// ---- configuration ------------
.i_clkdiv (i_clkdiv),
.i_clkon (r_clkon),
// ---- global signals ------------
.clk (w_clk),
.rst (rst_tb));
// ---------------- auxilaries ------------------------------------
reg time current, last;
always @ (posedge w_clk)
begin
last <= current;
current <= $time;
end
// calculate output clock period out of measured delay between to posedges
wire [63:0] clkperiod;
assign clkperiod = (current - last);
// ---------------- test functionality ----------------------------
integer failed = 0; // failed test item counter
task t_initialize;
begin
#1;
@ (negedge rst_tb);
@ (posedge clk_tb);
#(`STROBE);
end
endtask
task t_idle;
input integer loops;
begin
repeat (loops)
begin
@ (posedge clk_tb);
#(`STROBE);
end
end
endtask
task t_enable;
begin
@ (posedge clk_tb);
#(`STROBE);
r_clkon <= 'b1;
$display("\t%m: expected clock period: %d", i_clkperiod);
end
endtask
task t_disable;
begin
@ (posedge clk_tb);
#(`STROBE);
r_clkon <= 'b0;
$display("\t%m: oscillator switched off");
end
endtask
function f_check;
input [63:0] target;
input [63:0] result;
begin
if (result < (0.95 * target))
f_check = 1;
else if (result > (1.05 * target))
f_check = 1;
else
f_check = 0;
$display("\t%m: measured clock period: %d", result);
end
endfunction
initial
begin
t_initialize;
t_enable;
t_idle(1_000);
failed = failed + f_check(i_clkperiod, clkperiod);
t_idle(1_000);
failed = failed + f_check(i_clkperiod, clkperiod);
t_disable;
#1;
if (failed)
$display("\t%m: *failed* %d times", failed);
else
$display("\t%m: *well done*");
$finish;
end
// ---------------- testbench flow control ------------------------
initial
begin
$dumpfile(`DUMPFILE);
$dumpvars;
#(`TIMELIMIT);
$display("\t%m: *time limit (%t) reached*", $time);
$finish;
end
endmodule
| 7.459005 |
module tb_clock_max (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_high = period * duty / 100;
CLK_low = period - CLK_high;
if ((offset + (maxLH + jRise / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b0; // drive initial state
#(offset + (maxLH + jRise / 2));
end else begin
if (initialize) CLK <= 1'b1; // in middle of 1 region, init to 1
// #(clk_high + offset) reduced
#(CLK_high + maxHL + jFall / 2 + offset) CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (maxLH + jRise / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (maxHL + jFall / 2))) CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (maxLH + jRise / 2)));
end
end
end
endmodule
| 7.855653 |
module tb_clock_max_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_low = period * duty / 100;
CLK_high = period - CLK_low;
if ((offset + (maxHL + jFall / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b1; // drive initial state
#(offset + (maxHL + jFall / 2));
end else begin
if (initialize) CLK <= 1'b0; // in middle of 0 region, init to 0
// #(clk_low + offset) reduced
#(CLK_low + maxLH + jRise / 2 + offset) CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (maxHL + jFall / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (maxLH + jRise / 2))) CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (maxHL + jFall / 2)));
end
end
end
endmodule
| 8.417937 |
module tb_clock_min (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_high = period * duty / 100;
CLK_low = period - CLK_high;
if ((offset + (minLH - jRise / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b0; // drive initial state
#(offset + (minLH - jRise / 2));
end else begin
if (initialize) CLK <= 1'b1; // in middle of 1 region, init to 1
// #(clk_high + offset) reduced
#(CLK_high + minHL - jFall / 2 + offset) CLK <= 1'b0;
#((CLK_low - (minHL - jFall / 2) + (minLH - jRise / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b1;
#((CLK_high - (minLH - jRise / 2) + (minHL - jFall / 2))) CLK <= 1'b0;
#((CLK_low - (minHL - jFall / 2) + (minLH - jRise / 2)));
end
end
end
endmodule
| 7.912033 |
module tb_clock_minmax (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
task DriveLHInvalidRegion;
begin
if ((jRise + maxLH - minLH) > 0.0) begin
CLK <= 1'bx;
#((jRise + maxLH - minLH));
end
end
endtask
task DriveHLInvalidRegion;
begin
if ((jFall + maxHL - minHL) > 0.0) begin
CLK <= 1'bx;
#((jFall + maxHL - minHL));
end
end
endtask
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_high = period * duty / 100;
CLK_low = period - CLK_high;
if ((offset + (minLH - jRise / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b0; // drive initial state
#(offset + (minLH - jRise / 2));
end else begin // wait for x
if (initialize) CLK <= 1'bx; // in middle of X region, init to X
#((jRise / 2 + maxLH) + (offset)) CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (minHL - jFall / 2))) DriveHLInvalidRegion;
CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (minLH - jRise / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
DriveLHInvalidRegion;
CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (minHL - jFall / 2))) DriveHLInvalidRegion;
CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (minLH - jRise / 2)));
end
end
end
endmodule
| 7.867852 |
module tb_clock_minmax_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
task DriveLHInvalidRegion;
begin
if ((jRise + maxLH - minLH) > 0.0) begin
CLK <= 1'bx;
#((jRise + maxLH - minLH));
end
end
endtask
task DriveHLInvalidRegion;
begin
if ((jFall + maxHL - minHL) > 0.0) begin
CLK <= 1'bx;
#((jFall + maxHL - minHL));
end
end
endtask
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_low = period * duty / 100;
CLK_high = period - CLK_low;
if ((offset + (minHL - jFall / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b1; // drive initial state
#(offset + (minHL - jFall / 2));
end else begin // wait for x
if (initialize) CLK <= 1'bx; // in middle of X region, init to X
#((jFall / 2 + maxHL) + (offset)) CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (minLH - jRise / 2))) DriveLHInvalidRegion;
CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (minHL - jFall / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
DriveHLInvalidRegion;
CLK <= 1'b0;
#((CLK_low - (maxHL + jFall / 2) + (minLH - jRise / 2))) DriveLHInvalidRegion;
CLK <= 1'b1;
#((CLK_high - (maxLH + jRise / 2) + (minHL - jFall / 2)));
end
end
end
endmodule
| 7.867852 |
module tb_clock_min_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_low = period * duty / 100;
CLK_high = period - CLK_low;
if ((offset + (minHL - jFall / 2)) >= 0.0) begin
if (initialize) CLK <= 1'b1; // drive initial state
#(offset + (minHL - jFall / 2));
end else begin
if (initialize) CLK <= 1'b0; // in middle of 0 region, init to 0
// #(clk_low + offset) reduced
#(CLK_low + minLH - jRise / 2 + offset) CLK <= 1'b1;
#((CLK_high - (minLH - jRise / 2) + (minHL - jFall / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b0;
#((CLK_low - (minHL - jFall / 2) + (minLH - jRise / 2))) CLK <= 1'b1;
#((CLK_high - (minLH - jRise / 2) + (minHL - jFall / 2)));
end
end
end
endmodule
| 8.294223 |
module tb_clock_typ (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_high = period * duty / 100;
CLK_low = period - CLK_high;
if ((offset + (maxLH + minLH) / 2) >= 0.0) begin
if (initialize) CLK <= 1'b0; // drive initial state
#(offset + (maxLH + minLH) / 2);
end else begin
if (initialize) CLK <= 1'b1; // in middle of 1 region, init to 1
// #(clk_low + offset) reduced
#(CLK_high + (maxHL + minHL) / 2 + offset) CLK <= 1'b0;
#((CLK_low - ((maxHL + minHL) / 2) + ((maxLH + minLH) / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b1;
#((CLK_high - ((maxLH + minLH) / 2) + ((maxHL + minHL) / 2))) CLK <= 1'b0;
#((CLK_low - ((maxHL + minHL) / 2) + ((maxLH + minLH) / 2)));
end
end
end
endmodule
| 7.543793 |
module tb_clock_typ_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
input [63:0] duty_bits;
input [63:0] minLH_bits;
input [63:0] maxLH_bits;
input [63:0] minHL_bits;
input [63:0] maxHL_bits;
input [63:0] jRise_bits;
input [63:0] jFall_bits;
reg CLK;
real offset;
real period;
real duty;
real minLH;
real maxLH;
real minHL;
real maxHL;
real jRise;
real jFall;
real CLK_high;
real CLK_low;
always begin
@(posedge tb_status[0]) offset = $bitstoreal(offset_bits);
period = $bitstoreal(period_bits);
duty = $bitstoreal(duty_bits);
minLH = $bitstoreal(minLH_bits);
maxLH = $bitstoreal(maxLH_bits);
minHL = $bitstoreal(minHL_bits);
maxHL = $bitstoreal(maxHL_bits);
jRise = $bitstoreal(jRise_bits);
jFall = $bitstoreal(jFall_bits);
if (period <= 0.0)
$display(
"Error: Period for clock %m is invalid (period=%f). Clock will not be driven", period
);
else if (duty <= 0.0)
$display("Error: Duty for clock %m is invalid (duty=%f). Clock will not be driven", duty);
else begin
CLK_low = period * duty / 100;
CLK_high = period - CLK_low;
if ((offset + (maxHL + minHL) / 2) >= 0.0) begin
if (initialize) CLK <= 1'b1; // drive initial state
#(offset + (maxHL + minHL) / 2);
end else begin
if (initialize) CLK <= 1'b0; // in middle of 0 region, init to 0
// #(clk_low + offset) reduced
#(CLK_low + (maxLH + minLH) / 2 + offset) CLK <= 1'b1;
#((CLK_high - ((maxLH + minLH) / 2) + ((maxHL + minHL) / 2)));
end
while (tb_status[0] == 1'b1) begin : clock_loop
CLK <= 1'b0;
#((CLK_low - ((maxHL + minHL) / 2) + ((maxLH + minLH) / 2))) CLK <= 1'b1;
#((CLK_high - ((maxLH + minLH) / 2) + ((maxHL + minHL) / 2)));
end
end
end
endmodule
| 7.72527 |
module tb_clz32 ();
reg [31:0] d;
wire [ 4:0] clz;
pfpu_clz32 dut (
.d (d),
.clz(clz)
);
reg [5:0] i;
reg [7:0] j;
initial begin
$display("Testing clz32 module");
for (j = 0; j < 100; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
d = (32'h80000000 >> i);
if (i < 31) d = d + ($random % (32'h40000000 >> i));
#1 $display("%b -> %d", d, clz);
if (i[4:0] != clz) begin
$display("***** TEST FAILED *****");
$display("Expected %d, got %d", i, clz);
$finish;
end
end
end
d = 32'h00000000;
#1 $display("%b -> %d", d, clz);
if (5'd31 != clz) begin
$display("***** TEST FAILED *****");
$display("Expected 31, got %d", i, clz);
$finish;
end
$display("***** TEST PASSED *****");
$finish;
end
endmodule
| 7.157389 |
module: cl_serial
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cl_serial;
// Inputs
reg cl_sertc_p;
reg cl_sertc_n;
reg clk_spi;
reg fifo_spi_wen;
reg [7:0] fifo_spi_din;
reg fifo_train_wen;
reg [7:0] fifo_train_din;
reg clk_sys;
reg rst_sys_n;
reg clk_rxg;
// Outputs
wire cl_sertfg_p;
wire cl_sertfg_n;
wire cmd_spi_wr;
wire cmd_spi_rd;
wire [255:0] spi_register;
wire [23:0] reg_integration;
wire [7:0] reg_frame;
wire hdr_enable;
wire rolling_enable;
wire [9:0] reg_cnt_timing_cycle;
wire [11:0] reg_window_row_start;
wire [11:0] reg_window_row_length;
wire [9:0] timing_bram_rd_addr;
wire [20:0] timing_bram_dout;
wire [11:0] reg_test_image_chan_0;
wire [11:0] reg_test_image_chan_1;
wire [11:0] reg_test_image_chan_2;
wire [11:0] reg_test_image_chan_3;
wire [11:0] training_word;
wire [7:0] reg_camera_control;
wire reg_ctrl_led;
wire reg_test_image_enable;
// Instantiate the Unit Under Test (UUT)
cl_serial uut (
.cl_sertc_p(cl_sertc_p),
.cl_sertc_n(cl_sertc_n),
.cl_sertfg_p(cl_sertfg_p),
.cl_sertfg_n(cl_sertfg_n),
.cmd_spi_wr(cmd_spi_wr),
.cmd_spi_rd(cmd_spi_rd),
.clk_spi(clk_spi),
.spi_register(spi_register),
.fifo_spi_wen(fifo_spi_wen),
.fifo_spi_din(fifo_spi_din),
.reg_integration(reg_integration),
.reg_frame(reg_frame),
.hdr_enable(hdr_enable),
.rolling_enable(rolling_enable),
.reg_cnt_timing_cycle(reg_cnt_timing_cycle),
.reg_window_row_start(reg_window_row_start),
.reg_window_row_length(reg_window_row_length),
.timing_bram_rd_addr(timing_bram_rd_addr),
.timing_bram_dout(timing_bram_dout),
.reg_test_image_chan_0(reg_test_image_chan_0),
.reg_test_image_chan_1(reg_test_image_chan_1),
.reg_test_image_chan_2(reg_test_image_chan_2),
.reg_test_image_chan_3(reg_test_image_chan_3),
.training_word(training_word),
.fifo_train_wen(fifo_train_wen),
.fifo_train_din(fifo_train_din),
.reg_camera_control(reg_camera_control),
.reg_ctrl_led(reg_ctrl_led),
.reg_test_image_enable(reg_test_image_enable),
.clk_sys(clk_sys),
.rst_sys_n(rst_sys_n),
.clk_col(clk_col)
);
initial begin
// Initialize Inputs
cl_sertc_p = 0;
cl_sertc_n = 0;
clk_spi = 1;
fifo_spi_wen = 0;
fifo_spi_din = 0;
fifo_train_wen = 0;
fifo_train_din = 0;
clk_sys = 0;
rst_sys_n = 0;
clk_rxg = 0;
// Wait 100 ns for global reset to finish
#100;
#1000 rst_sys_n = 1;
// Add stimulus here
end
always #20 clk_sys = ~clk_sys;
always #20 clk_spi = ~clk_spi;
always #20 clk_rxg = ~clk_rxg;
endmodule
| 7.064472 |
module TB_Cmd_Decode;
reg clk;
reg rst_n;
reg rx_done;
reg [7:0] uart_data;
wire wr_trig;
wire rd_trig;
wire wfifo_wr_en;
wire [7:0] wfifo_data;
Cmd_Decode Cmd_Decode_inst (
.clk (clk),
.rst_n (rst_n),
.rx_done (rx_done),
.uart_data (uart_data),
.wr_trig (wr_trig),
.rd_trig (rd_trig),
.wfifo_wr_en(wfifo_wr_en),
.wfifo_data (wfifo_data)
);
always #10 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
rx_done = 1'b0;
uart_data = 'h00;
#100 rst_n = 1'b1;
rx_done = 1'b1;
uart_data = 'h55;
#20 rx_done = 1'b0;
#100 rx_done = 1'b1;
uart_data = 'h01;
#20 rx_done = 1'b0;
#100 rx_done = 1'b1;
uart_data = 'h02;
#20 rx_done = 1'b0;
#100 rx_done = 1'b1;
uart_data = 'h03;
#20 rx_done = 1'b0;
#100 rx_done = 1'b1;
uart_data = 'h04;
#20 rx_done = 1'b0;
#100 rx_done = 1'b1;
uart_data = 'haa;
#20 rx_done = 1'b0;
end
endmodule
| 6.751964 |
module tb_cmd_parser;
reg CLOCK50;
reg [3:0] KEY;
always #1 CLOCK50 <= ~CLOCK50;
//
// 例化top顶层模块
wire [19:0] SRAM_ADDR;
wire [15:0] SRAM_DQ;
wire SRAM_LB_N, SRAM_UB_N;
wire SRAM_WE_N, SRAM_OE_N;
wire SRAM_CE_N;
// top module
top top_inst (
.CLOCK_50(CLOCK50),
.KEY(KEY),
// sram
.SRAM_ADDR(SRAM_ADDR),
.SRAM_DQ(SRAM_DQ),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_WE_N(SRAM_WE_N),
.SRAM_OE_N(SRAM_OE_N),
.SRAM_CE_N(SRAM_CE_N)
);
// ssram
sram_sim sram_sim_inst (
.SRAM_ADDR(SRAM_ADDR),
.SRAM_DQ (SRAM_DQ),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_WE_N(SRAM_WE_N),
.SRAM_OE_N(SRAM_OE_N),
.SRAM_CE_N(SRAM_CE_N)
);
task uart_rx_byte(input [7:0] dat);
begin
#20 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
#2 top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;
top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H3E0;
#2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
#2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
end
endtask
initial begin
#0 CLOCK50 = 0;
KEY = 0;
#20 KEY = 1;
uart_rx_byte(8'H6D);
uart_rx_byte(8'H73);
uart_rx_byte(8'H64);
uart_rx_byte(8'H64);
uart_rx_byte(8'H72);
uart_rx_byte(8'H00);
uart_rx_byte(8'H00);
uart_rx_byte(8'H00);
uart_rx_byte(8'H01);
uart_rx_byte(8'H00);
uart_rx_byte(8'H00);
uart_rx_byte(8'H00);
uart_rx_byte(8'H10);
uart_rx_byte(8'H00);
/// 结束
#2000 $stop;
end
endmodule
| 6.514063 |
module tb_cmos_inverter;
// Inputs
reg inv_in;
// Outputs
wire inv_out;
// Instantiate the Unit Under Test (UUT)
cmos_inverter uut (
.inv_in (inv_in),
.inv_out(inv_out)
);
initial begin
$dumpfile("tb_cmos_inverter.vcd");
$dumpvars(0, tb_cmos_inverter);
// Initialize Inputs
inv_in = 0;
#8 $finish;
end
always #2 inv_in = ~inv_in;
endmodule
| 7.184922 |
module tb_cmsdk_mcu;
//wires
wire NRST; // active low reset
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire XTAL2; // crystal pin 2
//instantiation
M0_Simulation uut1 (
.NRST(NRST),
.nTRST(nTRST),
.TDI(TDI),
.SWDIOTMS(SWDIOTMS),
.SWCLKTCK(SWCLKTCK),
.XTAL2(XTAL2)
);
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
// No debug connection for Cortex-M0 DesignStart
assign nTRST = NRST;
assign TDI = 1'b1;
assign SWDIOTMS = 1'b1;
assign SWCLKTCK = 1'b1;
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
initial begin
#2100000 $stop;
end
endmodule
| 7.131043 |
module TB_CNN;
reg clk;
reg reset;
wire signed [39:0] CNN_output;
wire write_strobe;
CNN uut (
.clk(clk),
.reset(reset),
.CNN_output(CNN_output),
.write_strobe(write_strobe)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
#50;
reset = 1;
#10;
reset = 0;
#400000;
reset = 1;
#10;
reset = 0;
end
endmodule
| 6.700888 |
module tb_cnn_avgp_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter KERNEL = 3; //3*3 Kernel
parameter RATE = 1; //3*3 Kernel
localparam CHANNEL_NUM_IN = 4; //The number of channel
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/Input_image/1499_satRGB_h.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_avgp_3x3_test.txt";
parameter ENDTIME = CHANNEL_NUM_IN * IMAGE_SIZE * 2;
parameter SIMULATION_CLOCK = 5;
parameter SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1'b1;
#SIMULATION_CYCLE reset = 1'b0;
valid_in = 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_avgp_3x3_top_new #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT (IMAGE_HEIGHT),
.KERNEL (KERNEL),
.RATE (RATE),
.CHANNEL_NUM_IN(CHANNEL_NUM_IN)
) DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
//output
.pxl_out (pxl_out),
.valid_out(valid_out)
);
endmodule
| 6.986005 |
module tb_cnn_conv_1x1_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT = 64; //Height
parameter CHANNEL_NUM_IN = 64; //The number of channel in
parameter CHANNEL_NUM_OUT = 48; //The number of channel out
parameter KERNEL = 1; //Kernel width
// Localparam general
localparam KERNEL_SIZE = KERNEL * KERNEL;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/second_trial/Output_cnn_layer1_02.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/Weight_hex/Decoder/decoder.block1.0.weight.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/second_trial/Output_cnn_conv_1x1_10.txt";
localparam ENDTIME = 1000000 + 8 + ((IMAGE_SIZE + IMAGE_WIDTH + 1) * (CHANNEL_NUM_IN - 1)) + 1 + (9 * $clog2(
CHANNEL_NUM_IN
)) + ((((IMAGE_WIDTH + 1 + IMAGE_SIZE) * CHANNEL_NUM_IN) - IMAGE_SIZE)) * (CHANNEL_NUM_OUT - 1);
localparam SIMULATION_CLOCK = 5;
localparam SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1'b1;
valid_weight_in = 1'b0;
#SIMULATION_CYCLE reset = 1'b0;
$readmemh(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
if (!reset) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
i <= i + 1'b1;
#(SIMULATION_CYCLE)
if (valid_out) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
end
wire [DATA_WIDTH-1:0] pxl_out_conv;
wire valid_out_conv;
cnn_conv_10_1x1 DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out_conv),
.valid_out (valid_out_conv)
);
cnn_conv_relu #(
.DATA_WIDTH(DATA_WIDTH)
) relu5 (
.clk (clk),
.reset (reset),
.valid_in (valid_out_conv),
.in (pxl_out_conv),
//output
.out (pxl_out),
.valid_out(valid_out)
);
endmodule
| 7.255475 |
module tb_cnn_conv_3x3_64 ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 64; //The number of channel in
parameter CHANNEL_NUM_OUT = 4; //The number of channel out
parameter KERNEL = 3; //Kernel width
parameter RATE = 1; //Rate of dialtion
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/R.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/weight_test.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_conv_3x3_64.txt";
localparam SIMULATION_CLOCK = 5;
localparam SIMULATION_CYCLE = 10;
// Localparam general
localparam KERNEL_SIZE = KERNEL * KERNEL;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam ENDTIME = CHANNEL_NUM_IN_PIXEL * IMAGE_WIDTH;
reg clk;
reg reset;
reg valid_in;
reg stride2;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
valid_weight_in = 1'b0;
stride2 = 1'b0;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
valid_weight_in = 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_conv_3x3_dilation_multi_channel_new #(
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT (IMAGE_HEIGHT),
.CHANNEL_NUM_IN (CHANNEL_NUM_IN),
.CHANNEL_NUM_OUT(CHANNEL_NUM_OUT),
.KERNEL (KERNEL),
.RATE (RATE)
) DUT (
.clk (clk),
.reset (reset),
.stride2 (stride2),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out),
.valid_out (valid_out)
);
endmodule
| 7.525571 |
module tb_cnn_conv_3x3_dilation_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 64; //The number of channel in
parameter CHANNEL_NUM_OUT = 4; //The number of channel out
parameter KERNEL = 3; //Kernel width
parameter RATE = 1; //Rate of dialtion
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/R.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/weight_test.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_conv_3x3_64.txt";
localparam SIMULATION_CLOCK = 5;
localparam SIMULATION_CYCLE = 10;
// Localparam general
localparam KERNEL_SIZE = KERNEL * KERNEL;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam ENDTIME = CHANNEL_NUM_IN_PIXEL * IMAGE_WIDTH;
reg clk;
reg reset;
reg valid_in;
reg stride2;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
valid_weight_in = 1'b0;
stride2 = 1'b0;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
valid_weight_in = 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_conv_3x3_dilation_multi_channel_new #(
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT (IMAGE_HEIGHT),
.CHANNEL_NUM_IN (CHANNEL_NUM_IN),
.CHANNEL_NUM_OUT(CHANNEL_NUM_OUT),
.KERNEL (KERNEL),
.RATE (RATE)
) DUT (
.clk (clk),
.reset (reset),
.stride2 (stride2),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out),
.valid_out (valid_out)
);
endmodule
| 7.525571 |
module tb_cnn_conv_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 612; //Width
parameter IMAGE_HEIGHT = 612; //Height
parameter CHANNEL_NUM_IN = 1; //The number of channel in
parameter CHANNEL_NUM_OUT = 1; //The number of channel out
parameter KERNEL = 3; //Kernel width
parameter PADDING = 1; //Padding
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam KERNEL_SIZE = KERNEL * KERNEL; // 3x3
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/R.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/weight_test.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_conv_3x3_multi_channel_stride1.txt";
// parameter ENDTIME = 1000;
localparam ENDTIME = 600000;
localparam SIMULATION_CLOCK = 5;
localparam SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
reg stride2;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
valid_weight_in = 1'b0;
stride2 = 1'b0;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
valid_weight_in = 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_conv_3x3_multi_channel #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT (IMAGE_HEIGHT),
.CHANNEL_NUM_IN (CHANNEL_NUM_IN),
.CHANNEL_NUM_OUT(CHANNEL_NUM_OUT),
.KERNEL (KERNEL),
.PADDING (PADDING)
) DUT (
.clk (clk),
.reset (reset),
.stride2 (stride2),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out),
.valid_out (valid_out)
);
endmodule
| 7.525571 |
module tb_cnn_conv_7x7_64 ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 4; //The number of channel in
parameter CHANNEL_NUM_OUT = 4; //The number of channel out
parameter KERNEL = 7; //Kernel width
localparam SIMULATION_CLOCK = 5;
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam KERNEL_SIZE = KERNEL * KERNEL; // 3x3
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/Input_image/1499_satB_h.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/Weight_hex/Encoder/encoder.layer1.0.conv2.weight.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/old/Output_cnn_conv_7x7_testB.txt";
localparam ENDTIME = ((IMAGE_WIDTH * 3) + 63 + ((IMAGE_SIZE + (3 * (IMAGE_WIDTH + 1))) * 2) + 19 + (((((IMAGE_WIDTH * 3 ) + 3 + IMAGE_SIZE) * CHANNEL_NUM_IN) - IMAGE_SIZE)) * (CHANNEL_NUM_OUT - 1) + (IMAGE_SIZE/4) * CHANNEL_NUM_OUT)*2;
localparam SIMULATION_CYCLE = SIMULATION_CLOCK * 2;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
valid_weight_in = 1'b0;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
valid_weight_in = 1'b0;
$readmemh(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
if (~reset) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
i <= i + 1'b1;
#(SIMULATION_CYCLE)
if (valid_out) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
end
cnn_conv_7x7_test DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out),
.valid_out (valid_out)
);
endmodule
| 7.191386 |
module tb_cnn_conv_7x7_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 20; //Width
parameter IMAGE_HEIGHT = 20; //Height
parameter CHANNEL_NUM_IN = 3; //The number of channel in
parameter CHANNEL_NUM_OUT = 4; //The number of channel out
parameter KERNEL = 7; //Kernel width
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM = CHANNEL_NUM_IN * CHANNEL_NUM_OUT;
localparam KERNEL_SIZE = KERNEL * KERNEL; // 3x3
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam WEIGHT_NUM = CHANNEL_NUM * KERNEL_SIZE; // 2x2x3x3
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/R.txt";
localparam WEIGHTS_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/weight_test.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_conv_7x7_stride2_test.txt";
// parameter ENDTIME = 1000;
localparam ENDTIME = 6000;
localparam SIMULATION_CLOCK = 5;
localparam SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
reg valid_weight_in;
reg [DATA_WIDTH-1:0] weight_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] weight_input [ WEIGHT_NUM-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
valid_weight_in = 1'b0;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
valid_weight_in = 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
$readmemh(WEIGHTS_INPUT_FILE, weight_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
weight_in <= weight_input[i];
valid_weight_in <= 1'b1;
if (i >= WEIGHT_NUM) begin
valid_weight_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_conv_7x7_multi_channel_new #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT (IMAGE_HEIGHT),
.CHANNEL_NUM_IN (CHANNEL_NUM_IN),
.CHANNEL_NUM_OUT(CHANNEL_NUM_OUT),
.KERNEL (KERNEL)
) DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
.valid_weight_in(valid_weight_in),
.weight_in (weight_in),
//output
.pxl_out (pxl_out),
.valid_out (valid_out)
);
endmodule
| 7.191386 |
module tb_cnn_maxp_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter KERNEL = 3; //3*3 Kernel
parameter RATE = 1; //3*3 Kernel
localparam CHANNEL_NUM_IN = 512; //The number of channel
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_IN_PIXEL = CHANNEL_NUM_IN * IMAGE_SIZE;
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/second_trial/encoder/layer4/Output_cnn_layer4_02.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/second_trial/decoder/aspp/row5/Output_cnn_avgp_3x3_01_aspp.txt";
parameter ENDTIME = (IMAGE_WIDTH + 9 + (CHANNEL_NUM_IN * (IMAGE_SIZE + IMAGE_WIDTH + 1)) + ((IMAGE_SIZE/4) * CHANNEL_NUM_IN)) * 2;
parameter SIMULATION_CLOCK = 5;
parameter SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_IN_PIXEL-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1'b1;
#SIMULATION_CYCLE reset = 1'b0;
$readmemh(IMAGE_INPUT_FILE, image_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
if (!reset) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_IN_PIXEL) begin
valid_in <= 1'b0;
end
i <= i + 1'b1;
#(SIMULATION_CYCLE)
if (valid_out) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
end
// // ReLU
// wire [DATA_WIDTH-1:0] out_relu_5 ;
// wire valid_out_relu_5;
// cnn_conv_relu #(.DATA_WIDTH(DATA_WIDTH)) relu5 (
// .clk (clk ),
// .reset (reset ),
// .valid_in (valid_in ),
// .in (pxl_in ),
// //output
// .out (out_relu_5 ),
// .valid_out(valid_out_relu_5)
// );
cnn_avgp_01_3x3 DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
//output
.pxl_out (pxl_out),
.valid_out(valid_out)
);
endmodule
| 7.316838 |
module tb_cnn_maxp_3x3_top ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 1224; //Width
parameter IMAGE_HEIGHT = 1224; //Height
parameter CHANNEL_NUM = 1; //The number of channel
parameter KERNEL = 3; //3*3 Kernel
parameter PADDING = 1; //3*3 Kernel
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam CHANNEL_NUM_PIXEL = CHANNEL_NUM * IMAGE_SIZE;
localparam IMAGE_INPUT_FILE = "D:/GitHub/CNNs/Text_file/Input/R.txt";
localparam IMAGE_OUTPUT_FILE = "D:/GitHub/CNNs/Text_file/Output/Output_cnn_maxp_3x3.txt";
parameter ENDTIME = 600000;
parameter SIMULATION_CLOCK = 5;
parameter SIMULATION_CYCLE = 10;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
reg [DATA_WIDTH-1:0] image_input [CHANNEL_NUM_PIXEL-1:0];
reg [DATA_WIDTH-1:0] image_output;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
#SIMULATION_CYCLE reset = 0;
valid_in <= 1'b0;
$readmemb(IMAGE_INPUT_FILE, image_input);
image_output = $fopen(IMAGE_OUTPUT_FILE);
end
always #(SIMULATION_CLOCK) clk = ~clk;
always @(posedge clk) begin
pxl_in <= image_input[i];
valid_in <= 1'b1;
if (i >= CHANNEL_NUM_PIXEL) begin
valid_in <= 1'b0;
end
#(SIMULATION_CYCLE) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(image_output, "%h", pxl_out);
end
if (i == ENDTIME) begin
$finish;
end
end
cnn_maxp_3x3_multi_channel #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT(IMAGE_HEIGHT),
.CHANNEL_NUM (CHANNEL_NUM),
.KERNEL (KERNEL),
.PADDING (PADDING)
) DUT (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.pxl_in (pxl_in),
//output
.pxl_out (pxl_out),
.valid_out(valid_out)
);
endmodule
| 7.316838 |
module tb_cnt5;
reg tb_clk, tb_reset_n, tb_inc; // 3 regs
wire [2:0] tb_cnt; // 3bits wire tb_cnt
cnt5 U0_cnt (
.cnt(tb_cnt),
.clk(tb_clk),
.reset_n(tb_reset_n),
.inc(tb_inc)
); // instance by using cnt5
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; // every 5ns, invert clk
end
initial begin
tb_reset_n = 0;
tb_inc = 1; // input
#10;
tb_reset_n = 1; // every 10ns, change inputs
#10;
tb_inc = 0;
#10;
tb_inc = 1;
#10;
#10;
tb_inc = 0;
#10;
tb_inc = 1;
#10;
#10;
#10;
#10;
#10;
tb_reset_n = 0;
#10;
$stop; // stop
end
endmodule
| 6.540576 |
module tb_cntr8;
reg tb_clk, tb_reset_n, tb_inc, tb_load;
reg [7:0] tb_d_in;
wire [7:0] tb_d_out;
wire [2:0] tb_o_state;
cntr8 U0_cntr8 (
tb_clk,
tb_reset_n,
tb_inc,
tb_load,
tb_d_in,
tb_d_out,
tb_o_state
);
parameter STEP = 10;
// clock period=10ns
always #(STEP / 2) tb_clk = ~tb_clk;
initial begin
tb_clk = 1;
tb_reset_n = 0;
tb_inc = 0;
tb_load = 0;
tb_d_in = 8'b0;
#23;
tb_reset_n = 1;
tb_inc = 1;
#50;
tb_inc = 0;
#50;
tb_load = 1;
tb_d_in = 8'b00101100;
#20;
tb_inc = 1;
tb_load = 0;
#40;
tb_reset_n = 0;
tb_inc = 0;
#10;
tb_reset_n = 1;
#40;
$stop;
end
endmodule
| 6.930155 |
module tb_cnt_updown ();
reg [1:0] up_down;
reg clk, reset;
wire [31:0] count;
updown_counter M1 (
count,
up_down,
clk,
reset
);
initial begin
#150 $finish;
end
initial begin
end
always begin
#5 clk = ~clk;
end
initial begin
$dumpfile("./updown_counter.dump");
$dumpvars(0, tb_cnt_updown);
up_down = 2'b00;
clk = 0;
reset = 1;
#10 reset = 0;
#10 up_down = 2'b01;
#60 up_down = 2'b10;
#30 up_down = 2'b11;
#10 reset = 1;
end
endmodule
| 6.777875 |
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
);
reg [31:0] test_id = 0;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
| 6.668841 |
module tb_codec_top ();
wire slave_read; // Read request signal. Acvtive high.
wire slave_write; // Write request signal. Active high.
wire [2:0] slave_address; // Bus address.
wire [31:0] slave_readdata; // Read bus.
wire [31:0] slave_writedata; // Write bus.
wire slave_chipselect; // Chip select. Read and write operations are allowd when it is asserted.
// Active high.
wire slave_waitrequest;
wire slave_beginbursttransfer; // Indicates burst transfer. Active high.
wire [7:0] slave_burstcount; // Number of transfers in a burst;
wire slave_irq;
wire clk, reset, i2c_sclk, i2c_sdat;
wire m_clk, b_clk, dac_lr_clk, adc_lr_clk, dacdat, adcdat;
codec_avalon I_codec_avalon (
.clk (clk),
.reset (reset),
.slave_read (slave_read),
.slave_write (slave_write),
.slave_address (slave_address),
.slave_readdata (slave_readdata),
.slave_writedata (slave_writedata),
.slave_chipselect (slave_chipselect),
.slave_waitrequest (slave_waitrequest),
.slave_beginbursttransfer(slave_beginbursttransfer),
.slave_burstcount (slave_burstcount),
.slave_irq (slave_irq),
.i2c_sclk (i2c_sclk),
.i2c_sdat (i2c_sdat),
.adcdat (adcdat),
.m_clk (m_clk),
.b_clk (b_clk),
.dac_lr_clk (dac_lr_clk),
.adc_lr_clk (adc_lr_clk),
.dacdat (dacdat)
);
sys_clk50MHz_fm I_sys_clk50MHz_fm (.Clk(clk));
sys_rst_fm I_sys_rst_fm (.Rst(reset));
sys_i2c_fm I_sys_i2c_fm (
.i2c_sdat(i2c_sdat),
.i2c_sclk(i2c_sclk)
);
adc_fm I_adc_fm (
.m_clk(m_clk),
.b_clk(b_clk),
.adc_lr_clk(adc_lr_clk),
.adcdat(adcdat)
);
dac_fm I_dac_fm (
.m_clk(m_clk),
.b_clk(b_clk),
.dac_lr_clk(dac_lr_clk),
.dacdat(dacdat)
);
master_bus_fm I_master_bus_fm (
.Clk (clk),
.slave_read (slave_read),
.slave_write (slave_write),
.slave_address (slave_address),
.slave_readdata (slave_readdata),
.slave_writedata (slave_writedata),
.slave_chipselect (slave_chipselect),
.slave_waitrequest (slave_waitrequest),
.slave_beginbursttransfer(slave_beginbursttransfer),
.slave_burstcount (slave_burstcount),
.slave_irq (slave_irq)
);
endmodule
| 7.888047 |
module TB_collision_instruction;
reg clk;
reg clk_en;
reg reset;
reg start;
reg [31:0] dataa;
reg [31:0] datab;
reg [2:0] n;
wire done;
wire [31:0] result;
CollisionInstruction #(46) U1 (
clk,
clk_en,
reset,
start, // Execution inputs
dataa,
datab, // Data inputs
n, // Instruction selection inputs
done,
result // Instruction outputs
);
initial begin
clk = 1;
clk_en = 0;
reset = 1;
start = 0;
dataa = 32'd0;
datab = 32'd0;
n = 3'd0;
end
always #10 clk = ~clk;
// For testing purposes, using instructed base message in testbench
// "XXXX Keep your FPGA spinning!", which is 232 bits (29 bytes x 8)
parameter WORD_SIZE = 32;
parameter TOTAL_WORDS = 16;
parameter BASE_MESSAGE = "XXXX Keep your FPGA spinning!";
parameter [WORD_SIZE*TOTAL_WORDS-1:0] MESSAGE = {
BASE_MESSAGE, 152'h0, 4'h8, 60'h0, 32'h00000000, 32'h00000180
};
integer i, j;
initial begin
for (i = 0; i < 32; i = i + 1) begin
// Send load base message instructions until entire message has
// been loaded
for (j = 0; j < TOTAL_WORDS; j = j + 2) begin
#20 reset = 0;
start = 1;
dataa = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-(j*WORD_SIZE))-:WORD_SIZE];
datab = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-((j+1)*WORD_SIZE))-:WORD_SIZE];
n = 3'd0;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done);
end
// Start search collision
#20 reset = 0;
start = 1;
dataa = i;
datab = 32'h00000000;
n = 3'd1;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done);
// Have to send this once to get result filled with the correct
// status (there is no do--while loop in old Verilog)
#20 start = 1;
n = 3'd3;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done);
// Keep cycling until we find a collision
while (result != 32'd1) begin
// Try out retrieving the current total digests computed
#20 start = 1;
n = 3'd4;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done) begin
$display("Total digests computed: %d", result);
end
// Now retrieve the status of our computation
#20 start = 1;
n = 3'd3;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done);
end
// Display the result of our collision detection
#20 start = 1;
n = 3'd2;
clk_en = 1;
#20 start = 0;
clk_en = 0;
wait (done) begin
$display("(Target = %d) (Collision counter = %X)", i, result);
end
end
end
endmodule
| 6.827139 |
module TB_collision_searcher;
reg clk;
reg reset;
reg start;
reg [4:0] target;
reg [511:0] message;
reg [31:0] counter;
wire [31:0] digests_computed;
wire done;
wire [31:0] result;
CollisionSearcher U1 (
clk,
reset,
start, // Execution inputs
target,
message,
counter, // Data inputs
digests_computed, // Progress outputs
done,
result // Result outputs
);
initial begin
clk = 0;
reset = 1;
start = 0;
target = 5'd0;
message = 512'd0;
counter = 32'd0;
end
always #100 clk = ~clk;
// For testing purposes, using instructed base message in testbench
// "XXXX Keep your FPGA spinning!", which is 232 bits (29 bytes x 8)
parameter WORD_SIZE = 32;
parameter TOTAL_WORDS = 16;
parameter BASE_MESSAGE = "XXXX Keep your FPGA spinning!";
parameter [WORD_SIZE*TOTAL_WORDS-1:0] MESSAGE = {
BASE_MESSAGE, 152'h0, 4'h8, 60'h0, 32'h00000000, 32'h00000180
};
integer i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
// Start execution of next collision search
#200 reset = 0;
start = 1;
target = i;
message = MESSAGE;
counter = 32'h0;
#200 start = 0;
wait (done) begin
$display("(Target is %d) Collision at %h", i, result);
end
end
end
endmodule
| 6.827139 |
module: colour_space_conversion
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_colour_space_conversion;
// Inputs
reg clk;
reg [8:0] r1_in;
reg [8:0] g1_in;
reg [8:0] b1_in;
reg [8:0] r2_in;
reg [8:0] g2_in;
reg [8:0] b2_in;
reg pair_start_in;
reg de_in;
reg hsync_in;
reg vsync_in;
// Outputs
wire [7:0] y_out;
wire [7:0] c_out;
wire de_out;
wire hsync_out;
wire vsync_out;
wire [47:0] p_b1_r;
wire [47:0] pc_g1_r;
wire [47:0] pc_r1_r;
// Instantiate the Unit Under Test (UUT)
colour_space_conversion uut (
.clk(clk),
.r1_in(r1_in),
.g1_in(g1_in),
.b1_in(b1_in),
.r2_in(r2_in),
.g2_in(g2_in),
.b2_in(b2_in),
.pair_start_in(pair_start_in),
.de_in(de_in),
.hsync_in(hsync_in),
.vsync_in(vsync_in),
.y_out(y_out),
.c_out(c_out),
.de_out(de_out),
.hsync_out(hsync_out),
.vsync_out(vsync_out),
.p_b1_r(p_b1_r),
.pc_g1_r(pc_g1_r),
.pc_r1_r(pc_r1_r)
);
initial begin
// Initialize Inputs
clk = 0;
r1_in = 0;
g1_in = 0;
b1_in = 0;
r2_in = 0;
g2_in = 0;
b2_in = 0;
pair_start_in = 0;
de_in = 0;
hsync_in = 0;
vsync_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
r1_in = 9'b1_1111_1111;
g1_in = 9'b1_1111_1111;
b1_in = 9'b1_1111_1111;
r2_in = 9'b1_1111_1111;
g2_in = 9'b1_1111_1111;
b2_in = 9'b1_1111_1111;
pair_start_in = 0;
de_in = 0;
hsync_in = 0;
vsync_in = 0;
end
initial begin
forever
#5 clk = ~clk;
end
endmodule
| 7.109511 |
module tb_columnmix ();
reg clk;
reg rst_n;
reg [127:0] data_in;
reg start_in;
reg en_de;
// internal wires
wire [127:0] data_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("AC");
$dumpfile(DUMP_FILE);
$shm_open("tb.shm");
$shm_probe("AC");
end
initial begin
start_in = 0;
en_de = 1;
clk = 0;
rst_n = 1;
forever #5 clk = ~clk;
end
initial begin
#5 rst_n = 0;
#5 rst_n = 1;
#5 data_in = 128'hd4e0b81e_bfb44127_5d521198_30aef1e5;
#10 start_in = 1;
#10 start_in = 0;
#1000 $finish;
end
columnmix overall_colmix (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data_out),
.ready_out(ready_out),
.start_in(start_in),
.en_de(en_de)
);
endmodule
| 6.832923 |
module tb_comb_str;
integer i;
reg A, B, C, D, sel;
wire y;
comb_str comb (
y,
sel,
A,
B,
C,
D
);
initial begin
for (i = 0; i <= 5'b11111; i = i + 1) begin
{A, B, C, D, sel} = i;
#5;
end
end
endmodule
| 6.58145 |
module tb_comp4bit_beh;
reg [3:0] A, B;
wire AgtB, AeqB, AltB;
comp4bit_beh compa (
A,
B,
AgtB,
AeqB,
AltB
);
initial $monitor($time, " A=%4b, B=%4b, AgtB=%b,AeqB=%b,AltB=%b ", A, B, AgtB, AeqB, AltB);
initial begin
#0 A = 4'b0000;
B = 4'b0000;
#10 A = 4'b1000;
B = 4'b1011;
#10 A = 4'b0010;
B = 4'b0111;
#10 A = 4'b0101;
B = 4'b1111;
end
endmodule
| 6.528606 |
module TB_Comparador_Mayor;
// Inputs
reg CLK;
reg [7:0] A;
reg [7:0] B;
//outputs
wire Out;
// Instantiate the Unit Under Test (UUT)
Comparador_Mayor uut (
.CLK(CLK),
.A (A),
.B (B),
.Out(Out)
);
initial begin
// Initialize Inputs
CLK = 0;
A = 8'b10000000;
B = 8'b01111111;
// // Wait 100 ns for global reset to finish
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 CLK = ~CLK;
endmodule
| 6.772632 |
module Tb_comparator;
reg [31:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9;
wire [0:3] highest;
comp_last_layer inst (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
in9,
highest
);
initial begin
in0 = 32'b01000011011011011111110010101100; //237.987
in1 = 32'b01000000111100000000000000000000; //7.5
in2 = 32'b11000100010010000000000000000000; //-800
in3 = 32'b11000011011011011111110010101100; //-237.987
in4 = 32'b01001010010001010100100100010000; //3232323.9999
in5 = 32'b00000000000000000000000000000000; //0
in6 = 32'b11000011011011011111110010101100; //-237.987
in7 = 32'b01000010010110111001100110011010; //54.9
in8 = 32'b00110001110000111101100110111011; //0.0000000057
in9 = 32'b10100010010111010101110001100110; //-0.000000000000000003
#5 $display("%b", highest);
end
endmodule
| 6.574266 |
module tb_comparator3 ();
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.et(et),
.gt(gt)
);
initial begin
//////////////////
A = 3'b001;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 3'b010;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 3'b001;
B = 3'b010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
$finish;
//////////////////
end
endmodule
| 6.843472 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.et(et),
.gt(gt)
);
initial begin
// write your code here
end
endmodule
| 6.843472 |
module tb_comparator_3;
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
Comparator_3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
//////////////////
A = 3'b001;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 3'b010;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 3'b001;
B = 3'b010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
$finish;
//////////////////
end
endmodule
| 6.843472 |
module tb_comparator_4bit ();
reg [3:0] a;
reg [3:0] b;
wire agtb, altb, aeqb;
comparator_4bit comp (
.agtb(agtb),
.altb(altb),
.aeqb(aeqb),
.a(a),
.b(b)
);
initial begin
$dumpfile("tb_comparator_4bit.vcd");
$dumpvars(0, tb_comparator_4bit);
end
initial begin
a = 4'b0000;
b = 4'b0000;
#5 a = 4'b1000;
b = 4'b1011;
#5 a = 4'b0010;
b = 4'b0111;
#5 a = 4'b0101;
b = 4'b1111;
#5 $finish();
end
initial
$monitor(
"a = %b, b = %b,signa = %b, signb = %b, agtb = %b, altb = %b, aeqb = %b",
a,
b,
comp.signa,
comp.signb,
agtb,
altb,
aeqb
);
endmodule
| 6.843472 |
module tb_comparator_8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
Comparator_8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
//////////
A = 8'b00000000;
B = 8'b00000000;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10 A = 8'b00000001;
B = 8'b00000000;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#20 A = 8'b00000001;
B = 8'b00000010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10 A = 8'b00000011;
B = 8'b00000011;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10
//////////
A = 8'b00000000;
B = 8'b00000000;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10 A = 8'b00000001;
B = 8'b00000000;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#20 A = 8'b00000001;
B = 8'b00000010;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10 A = 8'b00000011;
B = 8'b00000011;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10
//////////
A = 8'b00000000;
B = 8'b00000000;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#10 A = 8'b00000001;
B = 8'b00000000;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20 A = 8'b00000001;
B = 8'b00000010;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#10 A = 8'b00000011;
B = 8'b00000011;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#10 $finish;
end
endmodule
| 6.843472 |
module tb_compare;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire [ 2:0] stream_channel_count;
wire [72:0] data;
wire ready;
wire [ 2:0] v_stream_channel_count;
wire [72:0] v_data;
wire v_ready;
test_source i_test_source (
.clk (clk),
.stream_channel_count(stream_channel_count),
.ready (ready),
.data (data)
);
test_source_cmp i_v_test_source_cmp (
.clk (clk),
.stream_channel_count(v_stream_channel_count),
.ready (v_ready),
.data (v_data)
);
wire [72:0] diff = data ^ v_data;
endmodule
| 6.626547 |
module tb_complex ();
reg clk = 1'b0;
reg [15:0] cnt = 16'b0000000000000000;
wire out;
initial begin
while (1) begin
#1;
clk = 1'b0;
#1;
clk = 1'b1;
end
end
always @(posedge clk) begin
cnt <= cnt + 1;
end
complex dut (
.x(cnt[7:0]),
.y(cnt[15:8]),
.z(out)
);
endmodule
| 6.883067 |
module tb_complexMUL ();
parameter p_inputWidth = 8;
parameter p_PointPosition = 3;
reg [p_inputWidth-1:0] inAr;
reg [p_inputWidth-1:0] inAi;
reg [p_inputWidth-1:0] inBr;
reg [p_inputWidth-1:0] inBi;
wire [2*p_inputWidth - p_PointPosition : 0] o_ResR;
wire [2*p_inputWidth - p_PointPosition : 0] o_ResI;
complexMUL #(p_inputWidth, p_PointPosition) dut (
inAr,
inAi,
inBr,
inBi,
o_ResR,
o_ResI
);
initial begin
inAr <= 2;
inAi <= 10;
inBr <= 5;
inBi <= 24;
#10 inAr <= 17;
inAi <= 32;
inBr <= 27;
inBi <= 51;
forever begin
#10 inAr <= $urandom;
inAi <= $urandom;
inBr <= $urandom;
inBi <= $urandom;
end
$stop;
end
endmodule
| 7.001079 |
module tb_complex_fsm ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk;
reg sys_rst_n;
reg pi_money_one;
reg pi_money_half;
reg random_data_gen;
//wire define
wire po_cola;
wire po_money;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟、全局复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50MHz
always #10 sys_clk = ~sys_clk;
//random_data_gen:产生非负随机数0、1
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) random_data_gen <= 1'b0;
else random_data_gen <= {$random} % 2;
//pi_money_one:模拟投入1元的情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) pi_money_one <= 1'b0;
else pi_money_one <= random_data_gen;
//pi_money_half:模拟投入0.5元的情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) pi_money_half <= 1'b0;
else
//取反是因为一次只能投一个币，即pi_money_one和pi_money_half不能同时为1
pi_money_half <= ~random_data_gen;
//------------------------------------------------------------
//将RTL模块中的内部信号引入到Testbench模块中进行观察
wire [4:0] state = complex_fsm_inst.state;
wire [1:0] pi_money = complex_fsm_inst.pi_money;
initial begin
$timeformat(-9, 0, "ns", 6);
$monitor(
"@time %t: pi_money_one=%b pi_money_half=%b pi_money=%b state=%b po_cola=%b po_money=%b",
$time, pi_money_one, pi_money_half, pi_money, state, po_cola, po_money);
end
//------------------------------------------------------------
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------------------complex_fsm_inst------------------------
complex_fsm complex_fsm_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n (sys_rst_n), //input sys_rst_n
.pi_money_one (pi_money_one), //input pi_money_one
.pi_money_half(pi_money_half), //input pi_money_half
.po_cola (po_cola), //output po_money
.po_money(po_money) //output po_cola
);
endmodule
| 8.512986 |
module tb_complex_mult;
parameter N = 2;
// UUT Signals
reg clk;
reg ab_valid;
reg signed [N-1:0] ar, ai, br, bi;
wire p_valid;
wire signed [N+N:0] pr, pi;
// Simulation Variables
reg [4*N-1:0] i, j;
reg signed [N-1:0] exp_ar, exp_ai, exp_br, exp_bi;
reg signed [N+N:0] real_part_dsp, imag_part_dsp;
// Instantiate the Unit Under Test (UUT)
complex_mult #(
.WIDTH(N),
.INPUT_BUF("ON"),
.OUTPUT_BUF("ON")
) UUT (
.clk (clk), // Clock
.ab_valid(ab_valid),
.ar (ar),
.ai (ai), // 1st inputs real and imaginary parts
.br (br),
.bi (bi), // 2nd inputs real and imaginary parts
.p_valid (p_valid),
.pr (pr),
.pi (pi) // output signal
);
initial begin
// Initialize Inputs
// $dumpfile("dut.vcd");
// $dumpvars;
clk = 0;
i = 0;
j = 0;
ab_valid = 0;
ar = 0;
ai = 0;
br = 0;
bi = 0;
#200;
// Add stimulus here
$display("Simulation begin!");
for (i = 0; i < 2 ** (4 * N) - 1; i = i + 1) begin
@(posedge clk) #1; // !! very important otherwise iverilog simulate goes wrong!
ab_valid = 1;
ar = i[N-1:0];
ai = i[2*N-1:N];
br = i[3*N-1:2*N];
bi = i[4*N-1:3*N];
end
@(posedge clk) ab_valid = 0;
ar = 0;
ai = 0;
br = 0;
bi = 0;
@(negedge p_valid) #100;
$display("All tests are passed!");
$finish;
end
initial begin
while (1) begin
@(posedge clk);
if (p_valid) begin
exp_ar = j[N-1:0];
exp_ai = j[2*N-1:N];
exp_br = j[3*N-1:2*N];
exp_bi = j[4*N-1:3*N];
real_part_dsp = exp_ar * exp_br - exp_ai * exp_bi;
imag_part_dsp = exp_ai * exp_br + exp_ar * exp_bi;
if ((pr != real_part_dsp) && (pi != imag_part_dsp)) begin
$display(" Fail - Module output does not equal expected value\n");
$display("%d,%d,%d,%d", pr, pi, real_part_dsp, imag_part_dsp);
$stop;
end
j = j + 1;
end
end
end
///////////////////////////////////////////////////////////////////////////////
always #10 clk = ~clk;
///////////////////////////////////////////////////////////////////////////////
endmodule
| 6.613969 |
module TB_COMPRESSOR;
localparam ENDCOUNT = 10000;
localparam NUM_PATTERNS = 8;
localparam LEN_ENCODE = $clog2(NUM_PATTERNS);
reg [ 255:0] data_i;
reg clk;
reg rst_n;
reg en_i;
wire [255 + LEN_ENCODE:0] data_o;
wire [ 8:0] size_o;
wire en_o;
wire [ LEN_ENCODE-1:0] sel;
reg [ LEN_ENCODE-1:0] sel_ref;
COMPRESSOR DUT (
.data_i(data_i),
.en_i (en_i),
.clk (clk),
.rst_n (rst_n),
.data_o(data_o),
.size_o(size_o),
.en_o (en_o)
);
assign sel = data_o[255+LEN_ENCODE:256];
// clock gen
initial begin
clk = 1'b0;
forever #10 clk = !clk;
end
// reset and en_i gen
initial begin
rst_n = 1'b0;
en_i = 1'b0;
repeat (2) @(posedge clk);
rst_n <= 1'b1;
en_i <= 1'b1;
end
integer file_stat_i;
integer file_stat_o;
// input vector gen
reg [255:0] data;
reg [255:0] data_i_list [0:ENDCOUNT-1];
integer list_i;
integer file_data_i;
initial begin
list_i = 0;
data = 'd0;
data_i = data;
file_data_i = $fopen("../tb/stimulus/stimulus_compressor/data_i.txt", "r");
if (file_data_i) begin
while (!$feof(
file_data_i
)) begin
repeat (ENDCOUNT)
@(posedge clk) begin
if (rst_n) begin
file_stat_i = $fscanf(file_data_i, "%x\n", data);
data_i <= data;
data_i_list[list_i] <= data;
list_i = list_i + 1;
end
end
end
$fclose(file_data_i);
end else begin
$display("ERROR: Input file is not opened");
$finish;
end
end
// output vector
integer file_data_o;
reg [255 + LEN_ENCODE:0] data_o_stimulus;
initial begin
data_o_stimulus = 'd0;
file_data_o = $fopen("../tb/stimulus/stimulus_compressor/data_o.txt", "r");
if (file_data_o) begin
while (!$feof(
file_data_o
)) begin
repeat (ENDCOUNT)
@(posedge clk) begin
if (rst_n && en_o) begin
file_stat_o = $fscanf(file_data_o, "%b\n", data_o_stimulus);
sel_ref = data_o_stimulus[255+LEN_ENCODE:256];
end
end
end
$fclose(file_data_o);
end else begin
$display("ERROR: Output file is not opened");
$finish;
end
end
// output vector
integer file_size_o;
reg [255 + LEN_ENCODE:0] size_o_stimulus;
initial begin
size_o_stimulus = 'd0;
file_size_o = $fopen("../tb/stimulus/stimulus_compressor/size_o.txt", "r");
if (file_size_o) begin
while (!$feof(
file_size_o
)) begin
repeat (ENDCOUNT)
@(posedge clk) begin
if (rst_n && en_o) begin
file_stat_o = $fscanf(file_size_o, "%x\n", size_o_stimulus);
end
end
end
$fclose(file_size_o);
end else begin
$display("ERROR: Output file is not opened");
$finish;
end
end
// self-check
integer total, cnt;
initial begin
total = 0;
cnt = 0;
repeat (ENDCOUNT)
@(posedge clk) begin
if (en_o) begin
#(1);
if (data_o != data_o_stimulus || size_o != size_o_stimulus) begin
cnt = cnt + 1;
$display("Failed at %0d\t=>\tinput >>\t%0x", total, data_i_list[total]);
$display(" \toutput >>\t%0d:%0x, %0d:%0x\n", sel, data_o[255:0], sel_ref,
data_o_stimulus[255:0]);
end
total = total + 1;
end
end
$display("Total error: %d / %d", cnt, total);
$finish;
end
endmodule
| 6.514525 |
module tb_comp_case;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
comp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_comp_case.vcd");
$dumpvars(0, tb_comp_case);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#5000 $finish;
end
always #317 i0 = ~i0;
always #600 clk = ~clk;
always #37 i1 = ~i1;
always #57 i2 = ~i2;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.045737 |
module tb_comp_case_net;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
comp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_comp_case_net.vcd");
$dumpvars(0, tb_comp_case_net);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#5000 $finish;
end
always #317 i0 = ~i0;
always #600 clk = ~clk;
always #37 i1 = ~i1;
always #57 i2 = ~i2;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.35958 |
module tb_comp_video_timing ();
reg clk;
reg reset;
reg flybk;
reg csr;
wire csa;
always #`CLK_P clk <= ~clk;
////////////////////////////////////////////////////////////////////////////////
wire [7:0] pr;
wire [7:0] pg;
wire [7:0] pb;
wire hs, vs, de;
reg load_dma;
`define C_RES_X 1152
`define C_HFP 40
`define C_HSW 20
`define C_HBP 62
`define C_RES_Y 896
`define C_VFP 4
`define C_VSW 3
`define C_VBP 47
// Note, no reset
video_timing #() DUT (
.pclk(clk),
.t_horiz_res(`C_RES_X),
.t_horiz_fp(`C_HFP),
.t_horiz_sync_width(`C_HSW),
.t_horiz_bp(`C_HBP),
.t_vert_res(`C_RES_Y),
.t_vert_fp(`C_VFP),
.t_vert_sync_width(`C_VSW),
.t_vert_bp(`C_VBP),
.t_words_per_line_m1(8'd35),
.t_bpp(2'd3),
.t_hires(1'b1),
.t_double_x(1'b0),
.t_double_y(1'b0),
.v_cursor_x(11'h69),
.v_cursor_y(10'h123),
.v_cursor_yend(10'h143),
.o_r(pr),
.o_g(pg),
.o_b(pb),
.o_hsync(hs),
.o_vsync(vs),
.o_de(de),
.load_dma_clk(clk),
.load_dma(load_dma),
.load_dma_data(32'hfeedface),
.sync_flyback(flybk),
.config_sync_req(csr),
.config_sync_ack(csa),
.enable_test_card(1'b1)
);
////////////////////////////////////////////////////////////////////////////////
reg junk;
initial begin
if (!$value$plusargs("NO_VCD=%d", junk)) begin
$dumpfile("tb_comp_video_timing.vcd");
$dumpvars(0, tb_comp_video_timing);
end
clk <= 1;
load_dma <= 0;
flybk <= 1;
csr <= 0;
reset <= 1;
#(`CLK * 2);
reset <= 0;
#(`CLK * 10);
csr <= 1;
// Drop flyback, and wait for dut to sync to it:
#(`CLK * 70);
flybk <= 0;
@(posedge csa);
@(posedge clk);
// Now run a few clocks:
#(`CLK * 3000000);
$finish;
end
endmodule
| 7.103479 |
module tb_concat_module ();
parameter NB_ADDR = 26; // Jump addr in J type instructions
parameter NB_PC = 32;
parameter NB_UPPER_PC = 4; // Number of bits of upper PC+1
parameter NB_LOWER_BITS = 2;
// concat module
reg instruction[NB_PC-1:0]; // instruccion completa
// reg next_pc[NB_PC-1:0]; // PC completo
wire [NB_PC-1:0] jump_addr;
// PC
reg en;
reg clock;
reg reset;
reg [NB_PC-1:0] mux_pc;
wire [NB_PC-1:0] next_pc;
// mux
reg select;
wire [NB_PC-1:0] addr;
initial begin
clock = 1'b0;
pc_reset = 1'b1;
pc_enable = 1'b0;
addr = 32'b0;
select = 1'b0;
#20 pc_reset = 1'b0;
#20 select = 1'b1; // jump
#200 $finish;
end
always #10 clock = ~clock;
program_counter program_counter (
.i_enable(en),
.i_clock(clock),
.i_reset(reset),
.i_mux_pc(addr),
.o_pc(next_pc)
);
mux2 mux2 (
.i_SEL(select), // jump=1 pc+1=0
.i_A(next_pc), // pc+1
.i_B(jump_addr), // jump_addr
.o_data(addr)
);
concat_module concat_module (
.i_inst(instruction[NB_ADDR-1:0]),
.i_next_pc(next_pc[NB_PC-1:28]),
.o_jump_addr(jump_addr)
);
endmodule
| 7.589526 |
module tb_control ();
reg Rst;
reg Clk;
reg [8:0] ms_m;
reg [7:0] DataOut_Bus;
reg [2:0] band;
wire [2:0] fun;
wire [5:0] b_sel;
wire LE_sel;
wire [1:0] outbus;
wire [2:0] c_sel;
wire [7:0] Address_Instruction_Bus;
control uut (
.Rst(Rst),
.Clk(Clk),
.ms_m(ms_m),
.DataOut_Bus(DataOut_Bus),
.band(band),
.fun(fun),
.b_sel(b_sel),
.LE_sel(LE_sel),
.outbus(outbus),
.c_sel(c_sel),
.Address_Instruction_Bus(Address_Instruction_Bus)
);
initial begin
Rst = 1;
#1 Rst = 0;
Clk = 0;
ms_m = 0;
DataOut_Bus = 0;
band = 0;
#2 band = 1;
#2 band = 2;
#2 band = 3;
#1 Rst = 0;
#1 ms_m = 9'b000_001_100;
#2 ms_m = 9'b001_010_001;
#2 ms_m = 9'b010_011_010;
#2 ms_m = 9'b011_111_110;
#2 ms_m = 9'b100_001_010;
#2 ms_m = 9'b101_011_001;
#2 ms_m = 9'b110_100_001;
#2 ms_m = 9'b111_100_001;
#2 ms_m = 9'b111_100_000;
#2 ms_m = 9'b111_100_101;
#2 ms_m = 9'b111_100_111;
end
always #1 Clk = !Clk;
endmodule
| 6.899995 |
module TB_controller_model;
// Inputs
reg sys_clk;
reg sys_reset;
reg [21:0] sys_addr;
reg [15:0] sys_data_to_sdram;
reg rw;
reg in_valid;
// Outputs
wire [15:0] sys_data_from_sdram;
wire sys_data_from_sdram_valid;
wire out_valid;
wire busy;
wire sdram_clk;
wire sdram_cke;
wire [11:0] sdram_addr;
wire [1:0] sdram_ba;
wire sdram_dqmh_n;
wire sdram_dqml_n;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_ras_n;
wire sdram_cas_n;
// Bidirs
wire [15:0] sdram_dq;
// Instantiate the Unit Under Test (UUT)
sdram_controller sdram_controller (
.sys_clk(sys_clk),
.sys_reset(sys_reset),
.sys_addr(sys_addr),
.sys_data_to_sdram(sys_data_to_sdram),
.sys_data_from_sdram(sys_data_from_sdram),
.sys_data_from_sdram_valid(sys_data_from_sdram_valid),
.rw(rw),
.in_valid(in_valid),
.out_valid(out_valid),
.busy(busy),
.sdram_clk(sdram_clk),
.sdram_cke(sdram_cke),
.sdram_addr(sdram_addr),
.sdram_dq(sdram_dq),
.sdram_ba(sdram_ba),
.sdram_dqmh_n(sdram_dqmh_n),
.sdram_dqml_n(sdram_dqml_n),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_ras_n(sdram_ras_n),
.sdram_cas_n(sdram_cas_n)
);
// Instantiate the Unit Under Test (UUT)
sdr sdr (
.Dq(sdram_dq),
.Addr(sdram_addr),
.Ba(sdram_ba),
.Clk(sdram_clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dqm({sdram_dqmh_n, sdram_dqml_n})
);
initial begin
// Initialize Inputs
sys_clk = 0;
sys_reset = 1;
sys_addr = 0;
sys_data_to_sdram = 0;
rw = 0;
in_valid = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
sys_reset = 0;
#150005;
rw = 1;
sys_addr = 22'b0000000001110000000000;
sys_data_to_sdram = 16'b0011001100110011;
in_valid = 1;
#10;
rw = 0;
in_valid = 0;
#100;
in_valid = 1;
rw = 0;
sys_addr = 22'b0000000001110000000000;
#10;
in_valid = 0;
#1000;
$finish;
end
always #5 sys_clk = ~sys_clk;
endmodule
| 6.524437 |
module TB_ControlPID;
// Inputs
reg [7:0] y_k_i;
reg clk_i;
reg dataf_i;
reg reset;
reg [7:0] coeff_1;
reg [7:0] coeff_2;
reg [7:0] coeff_3;
reg [7:0] ref_i;
// Outputs
wire dataf_oo;
wire [15:0] servo_o;
// Instantiate the Unit Under Test (UUT)
ControlPID uut (
.dataf_oo(dataf_oo),
.y_k_i(y_k_i),
.clk_i(clk_i),
.dataf_i(dataf_i),
.reset(reset),
.coeff_1(coeff_1),
.coeff_2(coeff_2),
.coeff_3(coeff_3),
.ref_i(ref_i),
.servo_o(servo_o)
);
initial begin
// Initialize Inputs
y_k_i = 0;
clk_i = 0;
dataf_i = 0;
reset = 0;
coeff_1 = 8'b00010010; // 18
coeff_2 = 8'b00000111; // 7
coeff_3 = 8'b10010110; // 150 // 8 bits no da para los bits de signo
ref_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.661511 |
module ControlUnitTestbench;
reg [2:0] opcode;
wire PCWrite;
wire RegWrite;
wire isSend;
wire isBranch;
wire [1:0] ULAOp;
wire MemWrite;
wire MemRead;
wire RegMemWrite;
ControlUnit dut (
opcode,
PCWrite,
RegWrite,
isSend,
isBranch,
ULAOp,
MemWrite,
MemRead,
RegMemWrite
);
initial begin
$display("Teste 1: Verificando os sinais de controle da instrucao MUL");
opcode = 3'b010;
#1 $display("Teste 2: Verificando os sinais de controle da instrucao SEND");
opcode = 3'b111;
end
initial begin
$monitor(
"Time = %d, opcode = %d, PCWrite = %d, RegWrite = %d, isSend = %d, isBranch = %d, ULAOp = %d, MemWrite = %d, MemRead = %d, RegMemWrite = %d",
$time, opcode, PCWrite, RegWrite, isSend, isBranch, ULAOp, MemWrite, MemRead, RegMemWrite);
end
endmodule
| 7.533746 |
module tb_converter;
reg tb_data_clk = 0;
reg tb_rst = 0;
//master
wire [ 15:0] tb_dmaster;
wire tb_vmaster;
reg tb_rmaster;
//slave
reg [127:0] tb_dslave;
reg tb_vslave;
wire tb_rslave;
reg tb_vslave_off;
reg tb_vslave_toggle = 0;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
util_axis_data_width_converter #(
.master_width(2),
.slave_width (16)
) dut (
//axi streaming clock and reset.
.aclk(tb_data_clk),
.arstn(~tb_rst),
//1553
//master data out interface
.m_axis_tdata(tb_dmaster),
.m_axis_tvalid(tb_vmaster),
.m_axis_tready(tb_rmaster),
//slave data in interface
.s_axis_tdata(tb_dslave),
.s_axis_tvalid(tb_vslave),
.s_axis_tready(tb_rslave)
);
//reset
initial begin
tb_rst <= 1'b1;
tb_vslave_off <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
#30000;
tb_vslave_off <= 1'b0;
#30500;
tb_vslave_off <= 1'b1;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_converter.vcd");
$dumpvars(0, tb_converter);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 4);
end
//valid off/on
always begin
tb_vslave_toggle <= ~tb_vslave_toggle;
#(CLK_PERIOD / 2);
end
//product data
always @(posedge tb_data_clk) begin
if (tb_rst == 1'b1) begin
tb_dslave <= 128'h55005500550055005500550055005500;
tb_vslave <= 0;
tb_rmaster <= 0;
end else begin
tb_rmaster <= $random % 2;
tb_vslave <= tb_vslave_off;
tb_dslave <= tb_dslave;
if ((tb_rslave == 1'b1) && (tb_vslave_off == 1'b1)) begin
tb_dslave <= tb_dslave + 128'h01010101010101010101010101010101;
end
end
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 8.179145 |
module tb_converters_cgrundey ();
reg enable;
reg ctr_enable;
reg ctr_clear;
reg conv_enable_n;
wire clk_out;
wire [5:0] counter_out, out184, out185;
clk M1 (
enable,
clk_out
);
counter6bit_cgrundey U1 (
clk_out,
ctr_clear,
ctr_enable,
counter_out
);
sn184_cgrundey U2 (
conv_enable_n,
counter_out,
out184
);
sn185_cgrundey U3 (
conv_enable_n,
counter_out,
out185
);
initial begin
enable = 1'b1; // enable clock
conv_enable_n = 1'b1; // disable converters
ctr_enable = 1'b0; // disable counter
ctr_clear = 1'b0;
#10 ctr_clear = 1'b1; // clear counter
#40 ctr_clear = 1'b0;
#50 ctr_enable = 1'b1; // enable counter
#50 conv_enable_n = 1'b0; // enable converters
end
endmodule
| 6.503465 |
module tb_convert_fxp_float ();
initial $dumpvars(0, tb_convert_fxp_float);
localparam WII = 16;
localparam WIF = 16;
localparam WOI = 15;
localparam WOF = 18;
reg rstn = 1'b0;
reg clk = 1'b1;
always #(10000) clk = ~clk; // 50MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg [WII+WIF-1:0] fxp1 = 0;
wire [ 31:0] float2;
wire [ 31:0] float3;
wire [WOI+WOF-1:0] fxp4;
wire overflow4;
wire [WOI+WOF-1:0] fxp5;
wire overflow5;
fxp2float #(
.WII(WII),
.WIF(WIF)
) fxp2float_i (
.in (fxp1),
.out(float2)
);
fxp2float_pipe #(
.WII(WII),
.WIF(WIF)
) fxp2float_pipe_i (
.rstn(rstn),
.clk (clk),
.in (fxp1),
.out (float3)
);
float2fxp #(
.WOI (WOI),
.WOF (WOF),
.ROUND(1)
) float2fxp_i (
.in (float2),
.out (fxp4),
.overflow(overflow4)
);
float2fxp_pipe #(
.WOI (WOI),
.WOF (WOF),
.ROUND(1)
) float2fxp_pipe_i (
.rstn (rstn),
.clk (clk),
.in (float2),
.out (fxp5),
.overflow(overflow5)
);
reg [31:0] cyclecnt = 0;
always @(posedge clk)
if (rstn) begin
cyclecnt <= cyclecnt + 1;
$display(
"cycle%3d fxp1=%16f float2=0x%08x float3=0x%08x fxp4=%16f %s fxp5=%16f %s",
cyclecnt, ($signed(fxp1) * 1.0) / (1 << WIF), float2, float3, ($signed(fxp4)
* 1.0) / (1 << WOF), overflow4 ? "(o)" : " ", ($signed(fxp5) * 1.0) / (1 << WOF),
overflow5 ? "(o)" : " ");
end
initial begin
while (~rstn) @(posedge clk);
@(posedge clk) fxp1 <= 'h00201551;
@(posedge clk) fxp1 <= 'h00300010;
@(posedge clk) fxp1 <= 'h009b63b3;
@(posedge clk) fxp1 <= 'h0bb51e68;
@(posedge clk) fxp1 <= 'h0e56e35e;
@(posedge clk) fxp1 <= 'h0432d234;
@(posedge clk) fxp1 <= 'h0bb004db;
@(posedge clk) fxp1 <= 'h09ad79bc;
@(posedge clk) fxp1 <= 'h16de4b61;
@(posedge clk) fxp1 <= 'h166f2bff;
@(posedge clk) fxp1 <= 'h1a164399;
@(posedge clk) fxp1 <= 'h18d9b80a;
@(posedge clk) fxp1 <= 'h16ba294f;
@(posedge clk) fxp1 <= 'hf6360551;
@(posedge clk) fxp1 <= 'ha34728f2;
@(posedge clk) fxp1 <= 'h16b53c9c;
@(posedge clk) fxp1 <= 'hb6b62e8e;
@(posedge clk) fxp1 <= 'h170edf8b;
@(posedge clk) fxp1 <= 'h1e546855;
@(posedge clk) fxp1 <= 'h180a9d44;
@(posedge clk) fxp1 <= 'hf6c772c2;
@(posedge clk) fxp1 <= 'ha2ad7ac4;
@(posedge clk) fxp1 <= 'h00001551;
@(posedge clk) fxp1 <= 'h00000010;
@(posedge clk) fxp1 <= 'ha09b63b3;
@(posedge clk) fxp1 <= 'h8bb51e68;
@(posedge clk) fxp1 <= 'h6e56e35e;
@(posedge clk) fxp1 <= 'h9432d234;
@(posedge clk) fxp1 <= 'h2bb004db;
@(posedge clk) fxp1 <= 'h39ad79bc;
@(posedge clk) fxp1 <= 'h76de4b61;
@(posedge clk) fxp1 <= 'h666f2bff;
@(posedge clk) fxp1 <= 'h7a164399;
@(posedge clk) fxp1 <= 'h68d9b80a;
@(posedge clk) fxp1 <= 'hb6ba294f;
@(posedge clk) fxp1 <= 'hf6360551;
@(posedge clk) fxp1 <= 'ha34728f2;
@(posedge clk) fxp1 <= 'h66b53c9c;
@(posedge clk) fxp1 <= 'hb6b62e8e;
@(posedge clk) fxp1 <= 'hd70edf8b;
@(posedge clk) fxp1 <= 'h6e546855;
@(posedge clk) fxp1 <= 'h680a9d44;
@(posedge clk) fxp1 <= 'hf6c772c2;
@(posedge clk) fxp1 <= 'ha2ad7ac4;
repeat (WII + WIF + WOI + WOF + 8) @(posedge clk) fxp1 <= 'h00000000;
$finish;
end
endmodule
| 6.631833 |
module tb_Conv_Data_mover;
parameter integer MEM0_DEPTH = 896;
parameter integer MEM1_DEPTH = 896;
parameter integer MEM0_ADDR_WIDTH = 10;
parameter integer MEM1_ADDR_WIDTH = 10;
parameter integer MEM0_DATA_WIDTH = 128;
parameter integer MEM1_DATA_WIDTH = 128;
parameter integer PE_SIZE = 16;
parameter integer WEIGHT_ROW_NUM = 70;
parameter integer WEIGHT_COL_NUM = 294;
reg clk;
reg rst_n;
reg en;
wire [MEM0_DATA_WIDTH-1:0] mem0_q0_i;
wire [MEM1_DATA_WIDTH-1:0] mem1_q0_i;
//wire [MEM0_DATA_WIDTH-1:0] mem0_q0;
wire [MEM0_ADDR_WIDTH-1:0] mem0_addr0;
wire mem0_ce0;
wire mem0_we0;
//wire [MEM1_DATA_WIDTH-1:0] mem1_q0;
wire [MEM1_ADDR_WIDTH-1:0] mem1_addr0;
wire mem1_ce0;
wire mem1_we0;
wire [MEM0_DATA_WIDTH-1:0] mem0_q0_o;
wire mem0_q0_vaild;
// GLB interface
wire [MEM0_DATA_WIDTH-1:0] mem1_q0_o;
wire wren_o;
wire rden_o;
always #5 clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
en = 0;
#30 rst_n = 1;
en = 1;
end
Conv_Data_mover_v2 #(
.MEM0_DEPTH(MEM0_DEPTH),
.MEM1_DEPTH(MEM1_DEPTH),
.MEM0_ADDR_WIDTH(MEM0_ADDR_WIDTH),
.MEM1_ADDR_WIDTH(MEM1_ADDR_WIDTH),
.MEM0_DATA_WIDTH(MEM0_DATA_WIDTH),
.MEM1_DATA_WIDTH(MEM1_DATA_WIDTH),
.PE_SIZE(PE_SIZE),
.WEIGHT_ROW_NUM(WEIGHT_ROW_NUM),
.WEIGHT_COL_NUM(WEIGHT_COL_NUM)
) DUT (
.clk(clk),
.rst_n(rst_n),
.en(en),
.mem0_q0_i (mem0_q0_i),
.mem0_addr0(mem0_addr0),
.mem0_ce0 (mem0_ce0),
.mem0_we0 (mem0_we0),
.mem1_q0_i (mem1_q0_i),
.mem1_addr0(mem1_addr0),
.mem1_ce0 (mem1_ce0),
.mem1_we0 (mem1_we0),
.mem0_q0_o(mem0_q0_o),
.mem0_q0_vaild(mem0_q0_vaild),
.mem1_q0_o(mem1_q0_o),
.wren_o(wren_o),
.rden_o(rden_o)
);
true_dpbram #(
.DWIDTH (MEM0_DATA_WIDTH),
.AWIDTH (MEM0_ADDR_WIDTH),
.MEM_SIZE(MEM0_DEPTH)
) mem0 (
/* Special Inputs */
.clk(clk),
/* input for port 0 */
.addr0_i(mem0_addr0),
.ce0_i(mem0_ce0),
.we0_i(mem0_we0),
.d0_i(),
/* input for port 1 */
.addr1_i(),
.ce1_i(),
.we1_i(),
.d1_i(),
/* output for port 0 */
.q0_o(mem0_q0_i),
/* output for port 1 */
.q1_o()
);
true_dpbram #(
.DWIDTH (MEM1_DATA_WIDTH),
.AWIDTH (MEM1_ADDR_WIDTH),
.MEM_SIZE(MEM1_DEPTH)
) mem1 (
/* Special Inputs */
.clk(clk),
/* input for port 0 */
.addr0_i(mem1_addr0),
.ce0_i(mem1_ce0),
.we0_i(mem1_we0),
.d0_i(),
/* input for port 1 */
.addr1_i(),
.ce1_i(),
.we1_i(),
.d1_i(),
/* output for port 0 */
.q0_o(mem1_q0_i),
/* output for port 1 */
.q1_o()
);
endmodule
| 7.19881 |
module tb_conv_mask ();
localparam T = 20;
reg clk, rst_n, act;
reg [7:0] a, b;
wire [15:0] result;
wire [7:0] c_i;
integer i;
conv_mask result_1 (
clk,
rst_n,
act,
a,
b,
result,
c_i
);
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
end
initial begin
rst_n = 1'b0;
@(posedge clk);
rst_n = 1'b1;
//@(posedge clk);
for (i = 0; i < 8; i = i + 1) begin
a[i] = $random();
b[i] = $random();
end
@(negedge clk) a = 255;
b = 50;
@(negedge clk) a = 30;
b = 70;
// @(posedge clk)
// a=
end
endmodule
| 6.834287 |
module testbench_CORDIC_main;
parameter width = 16; //width of x and y
// Inputs
reg signed [width-1:0] x_start, y_start;
reg signed [31:0] angle;
reg clock;
//reg signed [63:0] i;
wire signed [width-1:0] cosine, sine;
parameter An = 32000;
// here, 32000 is the scaling factor
// 32,000 is multiplied, as a random constant, so that verilog can process and display the <1 values efficiently
CORDIC_main Instance (
clock,
cosine,
sine,
x_start,
y_start,
angle
);
initial begin
//set clock
clock = 'b0;
//set initial values
//angle = 'b00010010111001000000010100011101;
//90 degrees = 1073741824
// Input angle = x
// y = 90/x
// degree angle is represented below in binary format
angle = 1073741824 / 1.5; // 60 degrees (angle)
x_start = An; // Xout = 32000*cos(angle)
y_start = 0; // Yout = 32000*sin(angle)
end
always #5 clock = !clock;
endmodule
| 8.5053 |
module tb_CORDIC_combination_2bit_int_angle_16bit ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = -32768;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 16'sb00000000_00000001;
end
$write("Simulation has finished");
$stop;
end
CORDIC_combination_2bit_int_angle_16bit #(
.LEN(LEN)
) sinh_cosh (
.angle(angle),
.cosh (cosh),
.sinh (sinh)
);
always #5 clk = ~clk;
endmodule
| 7.190503 |
module tb_cordic_exponential_8bit ();
localparam SZ = 8;
reg [SZ-1:0] Xin, Yin;
reg [SZ-1:0] angle;
wire [SZ+1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
localparam FALSE = 1'b0;
localparam TRUE = 1'b1;
localparam VALUE = 64/0.82815936; // reduce by a factor of 1.647 since thats the gain of the system
reg signed [63:0] i;
reg start;
initial begin
start = FALSE;
$write("Starting sim");
clk = 1'b0;
angle = 0;
Xin = VALUE; // Xout = 32000*cos(angle)
Yin = 1'd0; // Yout = 32000*sin(angle)
#10 @(posedge clk);
start = TRUE;
// sin/cos output
for (
i = -180; i < 180; i = i + 1
) // from 0 to 359 degress in 1 degree increment
// for ( i = 30; i < 360; i=i+1) // increment by 30 degrees only
begin
@(posedge clk);
start = FALSE;
angle = ((1 << SZ) * i)/360 ; // example: 45 deg = 45 / 360 * 2^32 = 32'b00100000000000000000000000000000 = 45.000 degrees -> atan(2^0)
$display("angle = %d, %h", i, angle);
end
#500 $write("Simulation has finished");
$stop;
end
CORDIC_Exponential_8bit dut0 (
.clk (clk),
.angle(angle),
.Xin (Xin),
.Yin (Yin),
.exp (exp)
);
always #5 clk = ~clk;
endmodule
| 8.389862 |
module tb_cordic_hyperbolic_8bit ();
localparam SZ = 8;
reg [SZ-1:0] Xin, Yin;
reg [SZ-1:0] angle;
wire [SZ:0] Xout, Yout;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
localparam FALSE = 1'b0;
localparam TRUE = 1'b1;
localparam VALUE = 64/0.82815936; // reduce by a factor of 1.647 since thats the gain of the system
reg signed [63:0] i;
reg start;
initial begin
start = FALSE;
$write("Starting sim");
clk = 1'b0;
angle = 0;
Xin = VALUE; // Xout = 32000*cos(angle)
Yin = 1'd0; // Yout = 32000*sin(angle)
#10 @(posedge clk);
start = TRUE;
// sin/cos output
for (
i = -180; i < 180; i = i + 1
) // from 0 to 359 degress in 1 degree increment
// for ( i = 30; i < 360; i=i+1) // increment by 30 degrees only
begin
@(posedge clk);
start = FALSE;
angle = ((1 << SZ) * i)/360 ; // example: 45 deg = 45 / 360 * 2^32 = 32'b00100000000000000000000000000000 = 45.000 degrees -> atan(2^0)
$display("angle = %d, %h", i, angle);
end
#500 $write("Simulation has finished");
$stop;
end
CORDIC_Hyperbolic_8bit dut (
.clk (clk),
.angle(angle),
.Xin (Xin),
.Yin (Yin),
.Xout (Xout),
.Yout (Yout)
);
always #5 clk = ~clk;
endmodule
| 8.356309 |
module tb_CORDIC_combination_16bit ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = -32768;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 16'sb00000000_00000001;
end
$write("Simulation has finished");
$stop;
end
CORDIC_Hyperbolic_combination_16bit #(
.LEN(LEN)
) sinh_cosh (
.angle(angle),
.cosh (cosh),
.sinh (sinh)
);
always #5 clk = ~clk;
endmodule
| 7.190503 |
module tb_CORDIC_combination_16bit_2bit_int_angle ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = -32768;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 16'sb00000000_00000001;
end
$write("Simulation has finished");
$stop;
end
CORDIC_Hyperbolic_combination_16bit_2bit_int_angle #(
.LEN(LEN)
) sinh_cosh (
.angle(angle),
.cosh (cosh),
.sinh (sinh)
);
always #5 clk = ~clk;
endmodule
| 7.190503 |
module tb_CORDIC_Hyperbolic_combination_32bit ();
localparam LEN = 32;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = 32'h80000000;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 32'sb00000000_00000001_00000000_00000000;
end
$write("Simulation has finished");
$stop;
end
CORDIC_Hyperbolic_combination_32bit #(
.LEN(LEN)
) sinh_cosh (
.angle(angle),
.cosh (cosh),
.sinh (sinh)
);
always #5 clk = ~clk;
endmodule
| 7.166328 |
module tb_CORDIC_sequential_32bit ();
localparam LEN = 32;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [LEN-1:0] angle;
reg signed [ 63:0] i;
localparam NUM = 16'hFFFF;
initial begin
clk = 0;
angle = 32'h80000000;
#10
for (i = 0; i < NUM; i = i + 1)
@(posedge clk) begin
angle = angle + 32'sb00000000_00000001_00000000_00000000;
end
$write("Simulation has finished");
$stop;
end
CORDIC_Hyperbolic_sequential_32bit #(
.LEN(LEN)
) sinh_cosh (
.clk (clk),
.angle(angle),
.cosh (cosh),
.sinh (sinh)
);
always #5 clk = ~clk;
endmodule
| 6.75044 |
module: core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_core;
// Inputs
reg [31:0] io_IR;
reg [31:0] from_data_mem;
reg data_valid;
reg data_ready;
reg clk;
reg reset;
reg [24:0] temp1;
reg [24:0] temp2;
reg [21:0] temp3;
reg [24:0] temp4;
reg [21:0] temp5;
reg [21:0] temp6;
reg [21:0] temp7;
reg [21:0] temp8;
reg [14:0] temp9;
reg [4:0] opcode;
// Outputs
wire [31:0] to_data_mem_reg;
wire [31:0] ins_mem_addr;
wire [31:0] data_mem_addr_reg;
wire mem_rd_reg;
wire mem_wr_reg;
wire [4:0]rd;
assign rd = io_IR[11:7];
// Instantiate the Unit Under Test (UUT)
core uut (
.from_ins_mem(io_IR),
.from_data_mem(from_data_mem),
.to_data_mem_reg(to_data_mem_reg),
.data_valid(data_valid),
.data_ready(data_ready),
.ins_mem_addr(ins_mem_addr),
.data_mem_addr_reg(data_mem_addr_reg),
.clk(clk),
.reset(reset),
.mem_rd_reg(mem_rd_reg),
.mem_wr_reg(mem_wr_reg)
);
always begin
clk = ~clk;
#50;
end
initial begin
// Initialize Inputs
io_IR = 0;
from_data_mem = 0;
data_valid = 1;
data_ready = 1;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#100;
reset = 0;
// Add stimulus here
temp1 = $random;
io_IR = {temp1,7'b0110111}; //LUI
opcode = io_IR[6:2];
#100;
temp2 = $random;
io_IR = {temp2,7'b0010111}; //AUIPC
opcode = io_IR[6:2];
#100;
/* temp3 = $random;
io_IR = {temp3[21:5],3'b000,temp3[4:0],7'b1100111}; //JALR
opcode = io_IR[6:2];
#100;
temp4 = $random;
io_IR = {temp4,7'b1101111}; //JAL
opcode = io_IR[6:2];
#100;
temp5 = $random;
io_IR = {temp5[21:5],3'b000,temp5[4:0],7'b1100011}; //BEQ
opcode = io_IR[6:2];
#100;
temp6 = $random;
io_IR = {temp6[21:5],3'b000,temp6[4:0],7'b0000011}; //LB
opcode = io_IR[6:2];
from_data_mem = $random;
#100;
temp7 = $random;
io_IR = {temp7[21:5],3'b000,temp7[4:0],7'b0100011}; //SB
opcode = io_IR[6:2];
#100;
temp8 = $random;
io_IR = {temp8[21:5],3'b000,temp8[4:0],7'b0010011}; //ADDI
opcode = io_IR[6:2];
#100;
temp9 = $random;
io_IR = {7'b0000000,temp9[14:5],3'b000,temp9[4:0],7'b0110011}; //ADD
opcode = io_IR[6:2];
#100;*/
end
endmodule
| 6.608059 |
module tb_core_mem (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
output wire ack,
input wire [ 15 : 0] addr,
input wire [127 : 0] block_wr,
output wire [127 : 0] block_rd
);
localparam NUM_WORDS = 128;
localparam WAIT_CYCLES = 8'h01;
//----------------------------------------------------------------
//----------------------------------------------------------------
reg [127 : 0] mem [0 : (NUM_WORDS - 1)];
reg mem_we;
reg [ 7 : 0] wait_ctr_reg;
reg [ 7 : 0] wait_ctr_new;
reg tmp_ack;
reg [127 : 0] tmp_block_rd;
reg [127 : 0] block_rd_reg;
reg ack_reg;
reg ack_new;
//----------------------------------------------------------------
//----------------------------------------------------------------
assign ack = ack_reg;
assign block_rd = block_rd_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @(posedge clk) begin : reg_update
integer i;
if (!reset_n) begin
block_rd_reg <= 128'h0;
wait_ctr_reg <= 8'h0;
ack_reg <= 1'h0;
end else begin
wait_ctr_reg <= wait_ctr_new;
ack_reg <= ack_new;
block_rd_reg <= mem[addr];
if (mem_we) mem[addr] <= block_wr;
end
end // reg_update
//----------------------------------------------------------------
// mem_access
//----------------------------------------------------------------
always @* begin : mem_access
;
mem_we = 1'h0;
wait_ctr_new = 8'h0;
ack_new = 1'h0;
tmp_block_rd = 128'h0;
if (cs) begin
wait_ctr_new = wait_ctr_reg + 1'h1;
if (wait_ctr_reg >= WAIT_CYCLES) begin
ack_new = 1'h1;
if (we) mem_we = 1'h1;
end
end
end
endmodule
| 7.142714 |
module tb_core_pixel ();
wire [7:0] O_PIXEL_IN_ADDR0;
wire [7:0] O_PIXEL_IN_ADDR1;
wire [7:0] O_PIXEL_IN_ADDR2;
wire [7:0] O_PIXEL_IN_ADDR3;
wire [7:0] O_PIXEL_OUT_ADDRB;
wire [7:0] O_PIXEL_OUT_ADDRG;
wire [7:0] O_PIXEL_OUT_ADDRR;
wire [7:0] O_PIXEL_OUT_ADDR0;
wire [7:0] O_PIXEL_OUT_ADDR1;
wire [7:0] O_PIXEL_OUT_ADDR2;
wire [7:0] O_PIXEL_OUT_ADDR3;
wire [7:0] O_PIXEL_IN_ADDRB;
wire [7:0] O_PIXEL_IN_ADDRG;
wire [7:0] O_PIXEL_IN_ADDRR;
reg [15:0] I_HEIGHT;
reg [15:0] I_WIDTH;
reg I_DIRECTION;
reg [1:0] I_DEGREES;
reg I_DMA_READY;
reg I_START;
reg I_HRESET_N;
reg I_HCLK;
core_pixel U0 (
.O_PIXEL_IN_ADDR0 (O_PIXEL_IN_ADDR0),
.O_PIXEL_IN_ADDR1 (O_PIXEL_IN_ADDR1),
.O_PIXEL_IN_ADDR2 (O_PIXEL_IN_ADDR2),
.O_PIXEL_IN_ADDR3 (O_PIXEL_IN_ADDR3),
.O_PIXEL_OUT_ADDRB(O_PIXEL_OUT_ADDRB),
.O_PIXEL_OUT_ADDRG(O_PIXEL_OUT_ADDRG),
.O_PIXEL_OUT_ADDRR(O_PIXEL_OUT_ADDRR),
.O_PIXEL_OUT_ADDR0(O_PIXEL_OUT_ADDR0),
.O_PIXEL_OUT_ADDR1(O_PIXEL_OUT_ADDR1),
.O_PIXEL_OUT_ADDR2(O_PIXEL_OUT_ADDR2),
.O_PIXEL_OUT_ADDR3(O_PIXEL_OUT_ADDR3),
.O_PIXEL_IN_ADDRB (O_PIXEL_IN_ADDRB),
.O_PIXEL_IN_ADDRG (O_PIXEL_IN_ADDRG),
.O_PIXEL_IN_ADDRR (O_PIXEL_IN_ADDRR),
.I_HEIGHT(I_HEIGHT),
.I_WIDTH(I_WIDTH),
.I_DIRECTION(I_DIRECTION),
.I_DEGREES(I_DEGREES),
.I_DMA_READY(I_DMA_READY),
.I_START(I_START),
.I_HRESET_N(I_HRESET_N),
.I_HCLK(I_HCLK)
);
always #1 I_HCLK <= ~I_HCLK;
initial begin
//TODO: write initialization here..
I_HEIGHT = 0;
I_WIDTH = 0;
I_DIRECTION = 0;
I_DEGREES = 0;
I_DMA_READY = 0;
I_START = 0;
I_HRESET_N = 1;
I_HCLK = 0;
end
initial begin
$vcdpluson;
//TODO: write test here..
//SET UP-----------------
//SQUARE IMAGE, H & W DIVISIBLE BY 8
I_HEIGHT = 8;
I_WIDTH = 8;
I_DEGREES = 1; //90
I_DIRECTION = 0; //CW
//start sequence
@(posedge I_HCLK) I_HRESET_N <= 0;
@(posedge I_HCLK) I_HRESET_N <= 1;
@(posedge I_HCLK) I_START <= 1;
@(posedge I_HCLK) I_START <= 0;
@(posedge I_HCLK) I_DMA_READY <= 1;
repeat (128) @(posedge I_HCLK);
I_DEGREES = 0;
//start sequence
@(posedge I_HCLK) I_HRESET_N <= 0;
@(posedge I_HCLK) I_HRESET_N <= 1;
@(posedge I_HCLK) I_START <= 1;
@(posedge I_HCLK) I_START <= 0;
@(posedge I_HCLK) I_DMA_READY <= 1;
#3000;
$finish;
end
endmodule
| 6.542703 |
module tb_count #(
parameter WIDTH = 4
) ();
reg clk;
reg rst;
reg en_i;
wire [WIDTH-1:0] count_o;
integer j;
count #(
.WIDTH(WIDTH)
) i_count (
.clk_i(clk),
.rst_i(rst),
.en_i(en_i),
.count_o(count_o)
);
initial begin
$dumpfile("tb_count.vcd");
// $dumpvars(level, list_of_variables_or_modules)
// level = 1 -> only variables in list_of_variables_or_modules
$dumpvars(0, tb_count);
//$readmemb("tb/egse.stim", stim);
//$monitor("%b%b LED:%b RS232TX:%b", clk, rst_n, led, rs232_tx);
clk = 0;
rst = 1;
en_i = 1'b0;
#10 rst = 0;
@(posedge clk)
/* Wait some cycles without enabling */
for (
j = 0; j < 5; j = j + 1
) begin
@(posedge clk)
if (count_o != 0) begin
$display("Invalid count: j=%d", j);
end
end
@(posedge clk);
/* Enable counter */
en_i = 1'b1;
for (j = 0; j < 15; j = j + 1) begin
@(posedge clk)
if (count_o != j + 1) begin
$display("Missing count: j=%d", j);
end
end
@(posedge clk);
$finish;
end
always #1 clk = !clk;
endmodule
| 6.60798 |
module tb_counter;
reg clk, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
counter UUT (
.clk(clk),
.reset(reset),
.q(q)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
#period;
if (q !== 1) begin
$display("test 1 failed");
$finish;
end else $display("clk=%b, reset=%b, q=%b", clk, reset, q);
// check value does not change during reset
#period;
if (q !== 1) begin
$display("test 1a failed");
$finish;
end else $display("clk=%b, reset=%b, q=%b", clk, reset, q);
// start counter
reset = 0;
#period;
if (q !== 2) begin
$display("test 2 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 3) begin
$display("test 3 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 4) begin
$display("test 4 failed");
//$finish;
end else $display("q=%b", q);
#period;
if (q !== 5) begin
$display("test 5 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 6) begin
$display("test 6 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 7) begin
$display("test 7 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 8) begin
$display("test 8 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 9) begin
$display("test 9 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 10) begin
$display("test 10 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 11) begin
$display("test 11 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 12) begin
$display("test 12 failed");
$finish;
end else $display("q=%b", q);
// counter should go back to 1
#period;
if (q !== 1) begin
$display("test 13 failed");
$finish;
end else $display("q=%b", q);
// check reset after a few cycles
#period;
if (q !== 2) begin
$display("test 14 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 3) begin
$display("test 15 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 4) begin
$display("test 16 failed");
$finish;
end else $display("q=%b", q);
#period;
if (q !== 5) begin
$display("test 17 failed");
$finish;
end else $display("q=%b", q);
reset = 1;
#period;
if (q !== 1) begin
$display("test 18 failed");
$finish;
end else $display("q=%b", q);
$display("all tests passed");
$finish;
end
endmodule
| 6.555401 |
module tb_counter4bit ();
wire [3:0] q;
reg clk, reset;
initial clk = 0;
always #2 clk = ~clk;
initial begin
$monitor("q = %b ", q, " clk = %b ", clk, " reset = %b ", reset);
end
counter4bit ctr (
q,
clk,
reset
);
initial begin
reset = 1'b1;
#4 reset = 1'b0;
// #10 reset = 1'b1;
#64 $finish;
end
endmodule
| 6.883755 |
module tb_counter6bit_cgrundey ();
reg clk_enable;
reg ctr_enable;
reg ctr_clr;
wire clk_out;
wire [5:0] count1;
wire [5:0] count2;
// Instantiate the clock generator with a period of 100 ns
clk #(100) clk1 (
clk_enable,
clk_out
);
// Intantiate two versions of the counter. ctr1 uses the default values.
// ctr2 overrides the default values of the parameters with #(20,30) ns.
counter6bit_cgrundey ctr1 (
clk_out,
ctr_clr,
ctr_enable,
count1
);
counter6bit_cgrundey #(20, 30) ctr2 (
clk_out,
ctr_clr,
ctr_enable,
count2
);
// Sequence the ENABLE and CLR signals
initial begin
clk_enable = 1;
ctr_enable = 0;
ctr_clr = 0;
#10 ctr_clr = 1;
#40 ctr_clr = 0;
#50 ctr_enable = 1;
#500 ctr_enable = 0;
#200 ctr_enable = 1;
#500 ctr_clr = 1;
#100 ctr_clr = 0;
end
endmodule
| 6.986135 |
module tb_counter9b_updown;
reg clk, reset, dir;
wire [7:0] count;
counter8b_updown counter (
count,
clk,
reset,
dir
);
initial begin
clk <= 0;
reset <= 0;
dir <= 0;
#500 reset = 1;
#10 reset = 0;
#490 $stop;
end
always begin
#5 clk = ~clk;
end
always begin
#100 dir = ~dir;
end
endmodule
| 6.83216 |
module TB_COUNTER_5B;
parameter P = 5;
// Inputs
reg CLK;
reg RST;
reg EN;
//outputs
wire [P-1:0] Y;
// Instantiate the Unit Under Test (UUT)
COUNTER_5B uut (
.CLK(CLK),
.RST(RST),
.EN (EN),
.Y (Y)
);
initial begin
// Initialize Inputs
CLK = 0;
RST = 0;
EN = 0;
#10 RST = 1;
#10 RST = 0;
#10 EN = 1;
// // Wait 100 ns for global reset to finish
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 CLK = ~CLK;
endmodule
| 6.549991 |
module tb_counter_60;
// counter_60 Parameters
parameter PERIOD = 10;
// counter_60 Inputs
reg rst_n = 0;
reg clk = 0;
reg load = 0;
reg set = 0;
reg [1:0] set_id = 0;
reg [3:0] set_num = 0;
reg signal = 0;
// counter_60 Outputs
wire [3:0] ones;
wire [2:0] tens;
wire loop;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
forever #(PERIOD) signal = ~signal;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
initial begin
#(PERIOD * 10) set = 1;
#(PERIOD * 10) set = 0;
end
initial begin
#(PERIOD * 11) set_num = 1;
set_id = 'b10;
#(PERIOD) set_num = 2;
set_id = 'b01;
#(PERIOD) set_num = 0;
set_id = 0;
end
counter_60 u_counter_60 (
.rst_n (rst_n),
.clk (clk),
.load (load),
.set (set),
.set_id (set_id[1:0]),
.set_num(set_num[3:0]),
.signal (signal),
.ones(ones[3:0]),
.tens(tens[2:0]),
.loop(loop)
);
initial begin
$finish;
end
endmodule
| 7.632061 |
module tb_counter_async ();
localparam S_RATE = 1000.0 / 20.0;
localparam M_RATE = 1000.0 / 210.7;
initial begin
$dumpfile("tb_counter_async.vcd");
$dumpvars(0, tb_counter_async);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(M_RATE / 2.0) m_clk = ~m_clk;
reg reset = 1'b1;
initial #(S_RATE * 100) reset = 1'b0;
localparam COUNTER_WIDTH = 16;
reg [COUNTER_WIDTH-1:0] s_add = 1;
reg s_valid = 0;
wire [COUNTER_WIDTH-1:0] m_counter;
wire m_valid;
initial begin
#(S_RATE * 200) s_valid = 1'b1;
#(S_RATE * 300) s_valid = 1'b0;
end
integer s_c = 0;
always @(posedge s_clk) begin
if (s_valid) begin
s_c <= s_c + s_add;
end
end
integer m_c = 0;
always @(posedge m_clk) begin
if (!reset) begin
if (m_valid) begin
m_c <= m_c + m_counter;
end
end
end
jelly_counter_async #(
.ASYNC (1),
.COUNTER_WIDTH(COUNTER_WIDTH)
) i_count_async (
.s_reset(reset),
.s_clk (s_clk),
.s_add (s_add),
.s_valid(s_valid),
.m_reset (reset),
.m_clk (m_clk),
.m_counter(m_counter),
.m_valid (m_valid)
);
endmodule
| 7.737253 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire enable;
wire clk;
wire reset;
wire [1:0] mode; // choose from 00, 01, 10, 11
wire [31:0] D;
wire [7:0] load;
wire [7:0] rco; // 2^nbits - 1 = #
wire [31:0] Q;
wire [7:0] load_syn;
wire [7:0] rco_syn; // 2^nbits - 1 = #
wire [31:0] Q_syn;
// Use /*AUTOREGINPUT*/ for create inputs in /*AUTOINST*/ in case inputs, outputs of inout signals
// are not declared.
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// b32 COUNTER
////////////
///////////////////////////////////////////////////////////////////////////////////////////
counter_b32 counter_b32_beh ( /*AUTOINST*/
// outputs
.b32_Q (Q[31:0]),
.b32_load (load[7:0]),
.b32_rco (rco[7:0]),
// inputs
.b32_clk (clk),
.b32_reset (reset),
.b32_enable(enable),
.b32_mode (mode), // choose from 00, 01, 10, 11
.b32_D (D[31:0])
);
counter_b32_syn counter_b32_synt ( /*AUTOINST*/
// outputs
.b32_Q (Q_syn[31:0]),
.b32_load (load_syn[7:0]),
.b32_rco (rco_syn[7:0]),
// inputs
.b32_clk (clk),
.b32_reset (reset),
.b32_enable(enable),
.b32_mode (mode), // choose from 00, 01, 10, 11
.b32_D (D[31:0])
);
// tester ...
t_counter_b32 t_counter_b32 ( /*AUTOINST*/
// outputs
.b32_clk (clk),
.b32_reset (reset),
.b32_enable(enable),
.b32_mode (mode), // choose from 00, 01, 10, 11
.b32_D (D[31:0]),
// inputs
.b32_Q (Q[31:0]),
.b32_load(load[7:0]),
.b32_rco (rco[7:0]),
.b32_Q_syn (Q_syn[31:0]),
.b32_load_syn(load_syn[7:0]),
.b32_rco_syn (rco_syn[7:0])
);
endmodule
| 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire enable;
wire clk;
wire reset;
wire [1:0] mode; // choose from 00, 01, 10, 11
wire [3:0] D;
wire load;
wire rco; // 2^nbits - 1 = #
wire [3:0] Q;
wire load_syn;
wire rco_syn; // 2^nbits - 1 = #
wire [3:0] Q_syn;
// Use /*AUTOREGINPUT*/ for create inputs in /*AUTOINST*/ in case inputs, outputs of inout signals
// are not declared.
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// b4 COUNTER
////////////
///////////////////////////////////////////////////////////////////////////////////////////
counter_b4 counter_b4_beh ( /*AUTOINST*/
// outputs
.b4_Q (Q),
.b4_load (load),
.b4_rco (rco),
// inputs
.b4_clk (clk),
.b4_reset (reset),
.b4_enable(enable),
.b4_mode (mode), // choose from 00, 01, 10, 11
.b4_D (D)
);
counter_b4_syn counter_b4_synt ( /*AUTOINST*/
// outputs
.b4_Q (Q_syn),
.b4_load (load_syn),
.b4_rco (rco_syn),
// inputs
.b4_clk (clk),
.b4_reset (reset),
.b4_enable(enable),
.b4_mode (mode), // choose from 00, 01, 10, 11
.b4_D (D)
);
// tester ...
t_counter_b4 t_counter_b4 ( /*AUTOINST*/
// outputs
.b4_clk (clk),
.b4_reset (reset),
.b4_enable(enable),
.b4_mode (mode), // choose from 00, 01, 10, 11
.b4_D (D),
// inputs
.b4_Q (Q),
.b4_load(load),
.b4_rco (rco),
.b4_Q_syn (Q_syn),
.b4_load_syn(load_syn),
.b4_rco_syn (rco_syn)
);
endmodule
| 7.554736 |
module tb_counter_top ();
/* Size of ROM */
parameter ROM_WIDTH = 8;
parameter ROM_ADDR_BITS = 8;
/* ROM Ports */
reg CLK;
reg EN;
reg [ROM_ADDR_BITS-1:0] ADDR;
wire [ROM_WIDTH-1:0] DATA_OUT;
/* Counter_top Ports */
reg C_RST;
reg C_EN;
reg C_DIR;
wire [7:0] C_CNT;
integer i;
/* Instantiating Counter Top - UUT */
counter_top UUT (
CLK,
C_RST,
C_EN,
C_DIR,
C_CNT
);
/* Instantiating ROM */
ROM R1 (
CLK,
ADDR,
EN,
DATA_OUT
);
/* Clock */
initial begin
CLK = 0;
forever #(`CLK_PER) CLK = ~CLK;
end
/* Counter for ADDR to access memory */
always @(negedge CLK) begin
if (EN) begin
if (!C_DIR) ADDR <= ADDR + 1;
else if (C_DIR) ADDR <= ADDR - 1;
end else ADDR <= ADDR;
end
/* Display the content of memory */
initial
$monitor(
"C_RST = %b, C_EN = %b, C_DIR = %b --- DATA_OUT = %h C_CNT = %h",
C_RST,
C_EN,
C_DIR,
DATA_OUT,
C_CNT
);
/* Checking for Errors */
always @(posedge CLK) begin
if (C_CNT != DATA_OUT)
$display("Error: C_CNT = %h DOES NOT EQUAL DATA_OUT = %h", C_CNT, DATA_OUT);
end
initial begin
ADDR = 0;
EN = 1; // Initializing ROM counter
C_EN = 1;
C_DIR = 0;
C_RST = 0; // Count Direction UP
#(`CLK_PER) $display("Checking Up Count");
C_RST = 1;
// Check if Error Checking is working properly //
#(`CLK_PER * 10) force UUT.CNT = 0;
#(`CLK_PER) release UUT.CNT;
#(`CLK_PER * 10) ADDR = 0;
C_DIR = 1;
C_RST = 0; // Count Direction Down
#(`CLK_PER) $display("Checking Down Count");
C_RST = 1;
#(`CLK_PER * 10) $finish;
end
endmodule
| 6.651759 |
module tb_count_slow;
reg clk, slowena, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
count_slow UUT (
.clk(clk),
.reset(reset),
.slowena(slowena),
.q(q)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
#period;
if (q !== 0) begin
$display("test 1 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
// should stay in reset
slowena = 1;
#period;
#period;
if (q !== 0) begin
$display("test 2 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
// start counter
reset = 0;
slowena = 1;
#period;
if (q !== 1) begin
$display("test 3 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 2) begin
$display("test 4 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 3) begin
$display("test 5 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 4) begin
$display("test 6 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 5) begin
$display("test 7 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
// pause counter
slowena = 0;
#period;
if (q !== 5) begin
$display("test 8 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 5) begin
$display("test 9 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
// resume counter
slowena = 1;
#period;
if (q !== 6) begin
$display("test 10 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 7) begin
$display("test 11 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 8) begin
$display("test 12 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 9) begin
$display("test 13 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
#period;
if (q !== 0) begin
$display("test 14 failed");
$finish;
end else $display("clk=%b, reset=%b, ena=%b, q=%b", clk, reset, slowena, q);
$display("all tests passed");
$finish;
end
endmodule
| 6.750727 |
module tb;
// Do this in your test bench
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb);
end
parameter N = 8;
reg [N-1:0] a, b;
wire [N-1:0] s;
wire cout;
cla CarryLookahead (
a,
b,
s,
cout
);
initial begin
$monitor($time, "%d + %d = %d (+8*%d)", a, b, s, cout);
a = 50;
b = 10;
#100 $finish;
end
endmodule
| 6.961556 |
module: Decorder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cpath_decode;
// Inputs
reg clock;
reg reset;
reg [31:0] io_IR;
reg io_br_eq;
reg io_br_lt;
reg io_br_ltu;
reg io_DataMem_rdy;
reg [24:0] temp1;
reg [24:0] temp2;
reg [21:0] temp3;
reg [24:0] temp4;
reg [21:0] temp5;
reg [21:0] temp6;
reg [21:0] temp7;
reg [21:0] temp8;
reg [14:0] temp9;
reg [4:0] opcode;
// Outputs
wire io_BUS_A_sel;
wire [1:0] io_BUS_B_sel;
wire [1:0] io_WB_sel;
wire io_BRJMP_sel;
wire io_JBType_sel;
wire [1:0] io_PC_MUX_sel;
wire io_WEN_RegFile;
wire io_Mem_rd;
wire io_Mem_wr;
// Instantiate the Unit Under Test (UUT)
Decorder uut (
.clock(clock),
.reset(reset),
.io_IR(io_IR),
.io_br_eq(io_br_eq),
.io_br_lt(io_br_lt),
.io_br_ltu(io_br_ltu),
.io_DataMem_rdy(io_DataMem_rdy),
.io_BUS_A_sel(io_BUS_A_sel),
.io_BUS_B_sel(io_BUS_B_sel),
.io_WB_sel(io_WB_sel),
.io_BRJMP_sel(io_BRJMP_sel),
.io_JBType_sel(io_JBType_sel),
.io_PC_MUX_sel(io_PC_MUX_sel),
.io_WEN_RegFile(io_WEN_RegFile),
.io_Mem_rd(io_Mem_rd),
.io_Mem_wr(io_Mem_wr)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
io_IR = 0;
io_br_eq = 0;
io_br_lt = 0;
io_br_ltu = 0;
io_DataMem_rdy = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
temp1 = 32'd177902135;
//io_IR = {temp1,7'b0110111}; //LUI
io_IR = 32'd177902135; //LUI
opcode = io_IR[6:2];
#100;
/*
temp2 = $random;
io_IR = {temp2,7'b0010111}; //AUIPC
opcode = io_IR[6:2];
#100;
temp3 = $random;
io_IR = {temp3[21:5],3'b000,temp3[4:0],7'b1100111}; //JALR
opcode = io_IR[6:2];
#100;
temp4 = $random;
io_IR = {temp4,7'b1101111}; //JAL
opcode = io_IR[6:2];
#100;
temp5 = $random;
io_IR = {temp5[21:5],3'b000,temp5[4:0],7'b1100011}; //BEQ
opcode = io_IR[6:2];
#100;
temp6 = $random;
io_IR = {temp6[21:5],3'b000,temp6[4:0],7'b0000011}; //LB
opcode = io_IR[6:2];
io_DataMem_rdy = 1'b0;
#50;
io_DataMem_rdy = 1'b1;
#100;
temp7 = $random;
io_IR = {temp7[21:5],3'b000,temp7[4:0],7'b0100011}; //SB
opcode = io_IR[6:2];
io_DataMem_rdy = 1'b0;
#50;
io_DataMem_rdy = 1'b1;
#100;
temp8 = $random;
io_IR = {temp8[21:5],3'b000,temp8[4:0],7'b0010011}; //ADDI
opcode = io_IR[6:2];
#100;
temp9 = $random;
io_IR = {7'b0000000,temp9[14:5],3'b000,temp9[4:0],7'b0110011}; //ADD
opcode = io_IR[6:2];
#100;
*/
end
endmodule
| 6.64125 |
module async_ram (
input wire [15:0] a,
input wire we_n,
inout wire [7:0] d
);
reg [7:0] mem[0:65535];
assign d = (we_n) ? mem[a] : 8'hZZ;
always @* begin
if (we_n == 1'b0) mem[a] = d;
end
endmodule
| 7.601231 |
module: tv80n_wrapper
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cpu;
// Inputs
reg reset_n;
reg clk;
reg clk_enable;
reg wait_n;
reg int_n;
reg nmi_n;
reg busrq_n;
reg [7:0] di;
// Outputs
wire m1_n;
wire mreq_n;
wire iorq_n;
wire rd_n;
wire wr_n;
wire rfsh_n;
wire halt_n;
wire busak_n;
wire [15:0] A;
wire [7:0] dout;
// Instantiate the Unit Under Test (UUT)
tv80n_wrapper uut (
.m1_n(m1_n),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.halt_n(halt_n),
.busak_n(busak_n),
.A(A),
.dout(dout),
.reset_n(reset_n),
.clk(clk),
.clk_enable(clk_enable),
.wait_n(wait_n),
.int_n(int_n),
.nmi_n(nmi_n),
.busrq_n(busrq_n),
.di(di)
);
reg [7:0] mem[0:15];
initial begin
mem[ 0] = 8'h21;
mem[ 1] = 8'h0F;
mem[ 2] = 8'h00;
mem[ 3] = 8'h36;
mem[ 4] = 8'h00;
mem[ 5] = 8'h34;
mem[ 6] = 8'd211;
mem[ 7] = 8'hFE;
mem[ 8] = 8'h18;
mem[ 9] = 8'd251;
mem[10] = 8'h00;
mem[11] = 8'h00;
mem[12] = 8'h00;
mem[13] = 8'h00;
mem[14] = 8'h00;
mem[15] = 8'h00;
end
always @* begin
if (mreq_n == 1'b0 && rd_n == 1'b0)
di = #10 mem[A];
if (mreq_n == 1'b0 && wr_n == 1'b0)
mem[A] = #5 dout;
end
initial begin
// Initialize Inputs
reset_n = 0;
clk = 0;
clk_enable = 1;
wait_n = 1;
int_n = 1;
nmi_n = 1;
busrq_n = 1;
repeat (3)
@(posedge clk);
reset_n = 1;
// Add stimulus here
repeat (256)
@(posedge clk);
$finish;
end
always begin
clk = #(1000/56) ~clk;
end
endmodule
| 6.539653 |
module tb_cpu0 ();
// cpu pin
reg clk;
reg rstn;
wire [7:0] err;
wire [31:0] i_addr;
wire [31:0] i_wdata;
reg [31:0] i_rdata;
wire i_en;
wire [3:0] i_we;
wire [31:0] d_addr;
wire [31:0] d_wdata;
reg [31:0] d_rdata;
wire d_en;
wire [3:0] d_we;
wire [3:0] f_ope_data;
wire [31:0] f_in1_data;
wire [31:0] f_in2_data;
wire f_in_rdy;
wire f_in_vld;
wire [31:0] f_out_data;
wire f_out_rdy;
wire f_out_vld;
wire [2:0] f_err;
dFPU dfunit (
clk,
rstn,
f_ope_data,
f_in1_data,
f_in2_data,
f_in_rdy,
f_in_vld,
f_out_data,
f_out_rdy,
f_out_vld,
f_err
);
wire [7:0] io_in_data;
wire io_in_rdy;
wire io_in_vld;
wire [7:0] io_out_data;
wire io_out_rdy;
wire io_out_vld;
wire [4:0] io_err;
wire [7:0] red;
dIOcontroller dio (
clk,
rstn,
red,
io_in_data,
io_in_rdy,
io_in_vld,
io_out_data,
io_out_rdy,
io_out_vld,
io_err
);
cpu core (
clk,
rstn,
err,
i_addr,
i_wdata,
i_rdata,
i_en,
i_we,
d_addr,
d_wdata,
d_rdata,
d_en,
d_we,
f_ope_data,
f_in1_data,
f_in2_data,
f_in_rdy,
f_in_vld,
f_out_data,
f_out_rdy,
f_out_vld,
f_err,
io_in_data,
io_in_rdy,
io_in_vld,
io_out_data,
io_out_rdy,
io_out_vld,
io_err
);
reg [31:0] imem[31:0];
reg [31:0] dmem[7:0];
reg [7:0] outputs;
//clk
initial begin
clk <= 0;
end
always begin
#1 clk <= ~clk;
end
// rstn
initial begin
rstn <= 0;
#2 rstn <= 1;
end
//memory
initial begin
imem[0] <= 32'b00100000001000000000000000000111;
imem[1] <= 32'b00100000010000000000000000000001;
imem[2] <= 32'b00011100000000100000100000000000;
imem[3] <= 32'b00111100011000100000000000000000;
imem[4] <= 32'b00001100000000110000000000000000;
imem[5] <= 32'b00011000000000000000000000000000;
imem[6] <= 32'b0;
imem[7] <= 32'b0;
imem[8] <= 32'b0;
imem[9] <= 32'b0;
imem[10] <= 32'b0;
imem[11] <= 32'b0;
imem[12] <= 32'b0;
imem[13] <= 32'b0;
imem[14] <= 32'b0;
imem[15] <= 32'b0;
dmem[0] <= 0;
dmem[1] <= 0;
dmem[2] <= 0;
dmem[3] <= 0;
dmem[4] <= 0;
dmem[5] <= 0;
dmem[6] <= 0;
dmem[7] <= 0;
end
always @(posedge clk) begin
i_rdata <= imem[i_addr>>2];
d_rdata <= dmem[d_addr>>2];
if (i_we != 0) begin
imem[i_addr>>2] <= i_wdata;
end
if (d_we != 0) begin
dmem[d_addr>>2] <= d_wdata;
end
end
//IO
/*
initial begin
io_in_data <= 5;
io_in_vld <= 1;
io_out_rdy <= 1;
end
always @(posedge clk) begin
if(io_out_rdy && io_out_vld) begin
outputs <= io_out_data;
end
end
*/
endmodule
| 6.626065 |
module tb;
// Do this in your test bench
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb);
end
parameter N = 100;
reg [N-1:0] a, b;
wire [N-1:0] s;
wire cout;
adder100 CarryLookahead (
a,
b,
1'b0,
cout,
s
);
initial begin
$monitor($time, "%d + %d = %d (+8*%d)", a, b, s, cout);
a = 10;
b = 12;
#100 $finish;
end
endmodule
| 6.961556 |
module tb ();
reg RST;
reg CLK;
reg [31:0] D_IN;
wire CRC_RDY;
wire [35:0] D_OUT;
integer fp;
integer i;
parameter DUTY = 2;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST = 1;
#8 RST = 0;
end
initial begin
fp = $fopen("./crc.out", "w");
$fmonitor(fp, "At time", $time, " ns, rst = %h, in = %h, out = %h", RST, D_IN, D_OUT);
$monitor("At time", $time, " ns, rst = %h, in = %h, out = %h", RST, D_IN, D_OUT);
#1000 $fclose(fp);
$stop;
end
always @(posedge CLK) begin
if (RST) D_IN <= $urandom % 32'hffff_ffff;
// D_IN <= 1'b1;
else if (CRC_RDY == 1'b1) D_IN <= $urandom % 32'hffff_ffff;
//D_IN <= 1'b1;
end
CRC U_CRC (
.D_IN(D_IN),
.CLK(CLK),
.RST(RST),
.D_OUT(D_OUT),
.CRC_RDY(CRC_RDY)
);
endmodule
| 7.002324 |
module tb_crc16 ();
reg clk_i;
reg rstn_i;
reg [7:0] byte_i;
reg etkin_i;
wire [15:0] crc16_o;
crc16 uut (
.clk_i (clk_i),
.rstn_i (rstn_i),
.byte_i (byte_i),
.etkin_i(etkin_i),
.crc16_o(crc16_o)
);
always begin
clk_i = 1'b0;
#5;
clk_i = 1'b1;
#5;
end
initial begin
rstn_i = 0;
etkin_i = 0;
byte_i = 0;
@(posedge clk_i);
#2;
rstn_i = 1;
@(posedge clk_i);
#2;
etkin_i = 1;
byte_i = 8'h4;
@(posedge clk_i);
#2;
byte_i = 8'h3;
@(posedge clk_i);
#2;
byte_i = 8'h2;
@(posedge clk_i);
#2;
byte_i = 8'h1;
@(posedge clk_i);
#2;
etkin_i = 0;
end
endmodule
| 6.842413 |
module tb_crc32;
reg clk;
reg nrst;
reg enable;
reg [7 : 0] data;
wire [31 : 0] crc_out;
crc32 DUT (
.nrst (nrst),
.clock (clk),
.enable(enable),
.din (data),
.crc_o(crc_out)
);
always begin
#2.5 clk = ~clk;
end
initial begin
fork
begin
#0 clk = 1'b0;
nrst = 1'b0;
enable = 1'b0;
data = 8'd0;
#100 nrst = 1'b1;
@(posedge clk) enable <= 1'b1;
data <= 8'h4d;
@(posedge clk) data <= 8'h00;
@(posedge clk) enable <= 1'b0;
end
join
end
endmodule
| 6.713297 |
module tb_crc_comb ();
localparam FRAME_SIZE = 4;
localparam CRC_SIZE = 4;
localparam MASK = 4'b0000;
wire [ CRC_SIZE - 1 : 0] crc_comb_out [0 : FRAME_SIZE];
reg [FRAME_SIZE - 1 : 0] data_in;
reg [CRC_SIZE - 1 : 0] crc_init;
reg [CRC_SIZE - 1 : 0] crc_poly;
reg [CRC_SIZE - 2 : 0] crc_poly_size;
assign crc_comb_out[0] = crc_init;
generate
genvar i;
for (i = 0; i < FRAME_SIZE; i = i + 1) begin
crc_comb #(
.CRC_SIZE(CRC_SIZE),
.MASK (MASK)
) CRC_COMB (
.crc_out (crc_comb_out[i+1]),
.data_in (data_in[FRAME_SIZE-1-i]),
.crc_in (crc_comb_out[i]),
.crc_poly (crc_poly),
.crc_poly_size(crc_poly_size)
);
end
endgenerate
function [3:0] crc_golden;
input [3:0] Data;
input [3:0] crc;
reg [3:0] d;
reg [3:0] c;
reg [3:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2];
newcrc[1] = d[3] ^ d[0] ^ c[0] ^ c[3];
newcrc[2] = d[1] ^ c[1];
newcrc[3] = d[1] ^ d[0] ^ c[0] ^ c[1];
crc_golden = newcrc;
end
endfunction
initial begin
crc_init = 0;
crc_poly_size = 3'b000;
crc_poly = 4'b1011;
data_in = 0;
repeat (16) begin
#10;
if (crc_comb_out[FRAME_SIZE] != crc_golden(data_in, crc_init)) begin
$display("TEST FAILED!");
$stop;
end
data_in = data_in + 1;
end
$display("TEST PASSED!");
end
endmodule
| 7.449577 |
module tb_crc_parallel;
localparam CRC_SIZE = `CRC_SIZE;
localparam FRAME_SIZE = `FRAME_SIZE;
localparam CRC_INIT = 0;
localparam CODE_SIZE = FRAME_SIZE + CRC_SIZE;
localparam PATTERN_VECTOR_NUMBER = `PATTERN_VECTOR_NUMBER;
localparam PATTERN_POLYNOMIAL_NUMBER = `PATTERN_VECTOR_NUMBER;
localparam CODE_WORD_NUMBER = PATTERN_POLYNOMIAL_NUMBER * PATTERN_VECTOR_NUMBER;
reg [CODE_SIZE - 1 : 0] code_word[0 : CODE_WORD_NUMBER - 1];
reg [CRC_SIZE : 0] crc_poly[0 : PATTERN_POLYNOMIAL_NUMBER - 1];
reg [CRC_SIZE - 1:0] crc_poly_size[0 : PATTERN_POLYNOMIAL_NUMBER - 1];
reg [FRAME_SIZE - 1 : 0] data_in;
reg [CRC_SIZE - 1 : 0] crc_init;
wire [CRC_SIZE - 1 : 0] crc_out;
wire crc_ready;
reg crc_in;
reg start;
reg [CRC_SIZE - 1:0] crc_poly_in;
reg [CRC_SIZE - 1 : 0] crc_poly_size_in;
reg crc_poly_wr;
reg rst_n;
reg clk;
integer error;
crc_parallel #(
.CRC_SIZE (CRC_SIZE),
.FRAME_SIZE(FRAME_SIZE)
) CRC_PARALLEL (
.crc_out (crc_out),
.data_in (data_in),
.crc_in (crc_init),
.crc_poly (crc_poly_in),
.crc_poly_size(crc_poly_size_in)
);
task reset;
begin
clk = 0;
start = 0;
crc_poly_in = 0;
data_in = 0;
error = 0;
crc_init = CRC_INIT;
end
endtask
task check_result;
input [CRC_SIZE - 1 : 0] result;
input [CRC_SIZE - 1 : 0] golden;
begin
if (result != golden || (result == golden) === 1'bx) begin
$display("ERROR at time %0d: Expected %x, obtained %x", $time, golden, result);
error = error + 1;
end
end
endtask
task check_test;
input integer test_number;
begin
if (error != 0) $display("TEST %0d FAILED!! Founded %d errors", test_number, error);
else $display("TEST %0d PASSED!!", test_number);
end
endtask
task check_final_test;
begin
$display("\nEnded Test Phase.");
if (error != 0) $display("TEST FAILED!! Founded %d errors", error);
else $display("TEST PASSED!!");
end
endtask
task read_files;
begin
$readmemb("../scripts/pattern_vector.bin", code_word);
$readmemb("../scripts/crc_poly.bin", crc_poly);
$readmemb("../scripts/crc_poly_size.bin", crc_poly_size);
end
endtask
integer i, j;
initial begin
read_files;
reset;
for (j = 0; j < PATTERN_POLYNOMIAL_NUMBER; j = j + 1) begin
$display("Test %0d: Poly = %b", j, crc_poly[j]);
@(posedge clk);
crc_poly_in = crc_poly[j][CRC_SIZE-1 : 0];
crc_poly_size_in = crc_poly_size[j];
@(posedge clk);
for (i = 0; i < PATTERN_VECTOR_NUMBER; i = i + 1) begin
data_in = code_word[i+j*PATTERN_VECTOR_NUMBER][CODE_SIZE-1-:FRAME_SIZE];
@(posedge clk);
check_result(crc_out, code_word[i+j*PATTERN_VECTOR_NUMBER][CRC_SIZE-1 : 0]);
end
check_test(j);
end
check_final_test;
$stop;
end
always #10 clk = !clk;
endmodule
| 6.80547 |
module tb_crossbar #(
parameter STAGE = 0,
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter ACT_LEN = 25,
parameter width_2B = 16,
parameter width_4B = 32,
parameter width_6B = 48
) ();
reg clk;
reg rst_n;
//input from PHV
reg [ PHV_LEN-1:0] phv_in;
reg phv_in_valid;
//input from action
reg [ACT_LEN*25-1:0] action_in;
reg action_in_valid;
//output to the ALU
wire alu_in_valid;
wire [width_6B*8-1:0] alu_in_6B_1;
wire [width_6B*8-1:0] alu_in_6B_2;
wire [width_4B*8-1:0] alu_in_4B_1;
wire [width_4B*8-1:0] alu_in_4B_2;
wire [width_4B*8-1:0] alu_in_4B_3;
wire [width_2B*8-1:0] alu_in_2B_1;
wire [width_2B*8-1:0] alu_in_2B_2;
wire [ 355:0] phv_remain_data;
//clk signal
localparam CYCLE = 10;
wire [width_6B-1:0] con_6B_7_in;
wire [width_6B-1:0] con_6B_6_in;
assign con_6B_7_in = phv_in[PHV_LEN-1-:width_6B];
assign con_6B_6_in = phv_in[PHV_LEN-1-width_6B-:width_6B];
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
setup new
*/
phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
action_in <= 625'b0;
action_in_valid <= 1'b0;
#(2 * CYCLE)
/*
extract values from PHV
*/
phv_in <= {
48'hfffffffffffe, 48'heeeeeeeeeeef, 672'b0, 356'b0
};
phv_in_valid <= 1'b1;
//switch the con_6B_7 with con_6B_6
action_in <= {4'b0001, 5'd6, 5'd7, 11'b0, 600'b0};
action_in_valid <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
action_in <= 625'b0;
action_in_valid <= 1'b0;
#(CYCLE)
/*
extract values from imm
*/
phv_in <= {
48'hffffffffffff, 48'heeeeeeeeeeee, 672'b0, 356'b0
};
phv_in_valid <= 1'b1;
//switch the con_6B_7 with con_6B_6
action_in <= {4'b1010, 5'd6, 16'hffff, 600'b0};
action_in_valid <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
action_in <= 625'b0;
action_in_valid <= 1'b0;
#(CYCLE)
/*
empty actions to take (return the original value)
*/
phv_in <= {
48'hffffffffffff, 48'heeeeeeeeeeee, 672'b0, 356'b0
};
phv_in_valid <= 1'b1;
//this is an invalid action
action_in <= {4'b0000, 5'd6, 16'hffff, 600'b0};
action_in_valid <= 1'b1;
#(CYCLE) phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
action_in <= 625'b0;
action_in_valid <= 1'b0;
#(CYCLE)
//reset to zeros.
phv_in <= 1124'b0;
phv_in_valid <= 1'b0;
action_in <= 625'b0;
action_in_valid <= 1'b0;
#(2 * CYCLE);
end
crossbar #(
.STAGE(STAGE),
.PHV_LEN(),
.ACT_LEN(),
.width_2B(),
.width_4B(),
.width_6B()
) crossbar_1 (
.clk(clk),
.rst_n(rst_n),
//input from PHV
.phv_in(phv_in),
.phv_in_valid(phv_in_valid),
//input from action
.action_in(action_in),
.action_in_valid(action_in_valid),
//output to the ALU
.alu_in_valid(alu_in_valid),
.alu_in_6B_1(alu_in_6B_1),
.alu_in_6B_2(alu_in_6B_2),
.alu_in_4B_1(alu_in_4B_1),
.alu_in_4B_2(alu_in_4B_2),
.alu_in_4B_3(alu_in_4B_3),
.alu_in_2B_1(alu_in_2B_1),
.alu_in_2B_2(alu_in_2B_2),
.phv_remain_data(phv_remain_data)
);
endmodule
| 7.606265 |
module tb_csi_rx_lane_aligner;
reg clk;
reg [3:0] bytes_valid;
reg [63:0] bytes_i;
wire [63:0] bytes_o;
wire synced;
reg reset;
wire reset_g;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
mipi_csi_rx_lane_aligner ins1 (
.clk_i(clk),
.reset_i(reset),
.bytes_valid_i(bytes_valid),
.byte_i(bytes_i),
.lane_valid_o(synced),
.lane_byte_o(bytes_o)
);
task sendbytes;
input [63:0] bytes;
begin
bytes_i = bytes;
clk = 1'b0;
#4 clk = 1'b1;
#4;
end
endtask
initial begin
reset = 1'b0;
clk = 1'b0;
bytes_valid = 4'h0;
#50 sendbytes(64'h00000000);
reset = 1'h1;
sendbytes(64'h00000000);
reset = 1'h0;
sendbytes(64'h00000000);
sendbytes(64'h00000000);
bytes_valid[1] = 1'h1;
sendbytes(64'h0000000011B80000);
sendbytes(64'h0000000033220000);
bytes_valid[2] = 1'h1;
bytes_valid[3] = 1'h1;
bytes_valid[0] = 1'h1;
sendbytes(64'h11B811B8554411B8);
sendbytes(64'h3322332277663322);
sendbytes(64'h5544554499885544);
bytes_valid[1] = 1'h0;
sendbytes(64'h7766776600007766);
sendbytes(64'h9988998800009988);
bytes_valid[2] = 1'h0;
bytes_valid[3] = 1'h0;
bytes_valid[0] = 1'h0;
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
bytes_valid[1] = 1'h1;
sendbytes(64'h0000000011B80000);
sendbytes(64'h0000000033220000);
bytes_valid[2] = 1'h1;
bytes_valid[0] = 1'h1;
sendbytes(64'h000011B8554411B8);
bytes_valid[3] = 1'h1;
sendbytes(64'h11B8332277663322);
sendbytes(64'h3322554499885544);
bytes_valid[1] = 1'h0;
sendbytes(64'h5544776600007766);
sendbytes(64'h7766998800009988);
bytes_valid[0] = 1'h0;
bytes_valid[2] = 1'h0;
sendbytes(64'h9988000000000000);
bytes_valid[3] = 1'h0;
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
sendbytes(64'h00000000);
end
endmodule
| 6.552817 |
module tb_csi_rx_lane_aligner_8b2lane;
reg clk;
reg [2:0] bytes_valid;
reg [15:0] bytes_i;
wire [15:0] bytes_o;
wire synced;
reg reset;
wire reset_g;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
mipi_csi_rx_lane_aligner #(
.MIPI_GEAR (8),
.MIPI_LANES(2)
) ins1 (
.clk_i(clk),
.reset_i(reset),
.bytes_valid_i(bytes_valid),
.byte_i(bytes_i),
.lane_valid_o(synced),
.lane_byte_o(bytes_o)
);
task sendbytes;
input [15:0] bytes;
begin
bytes_i = bytes;
clk = 1'b0;
#4 clk = 1'b1;
#4;
end
endtask
initial begin
reset = 1'b0;
clk = 1'b0;
bytes_valid = 4'h0;
#50 sendbytes(16'h0000);
reset = 1'h1;
sendbytes(16'h0000);
reset = 1'h0;
sendbytes(16'h0000);
sendbytes(16'h0000);
bytes_valid[0] = 1'h1;
sendbytes(16'h00B8);
bytes_valid[1] = 1'h1;
sendbytes(16'hB811);
sendbytes(16'h1122);
sendbytes(16'h2233);
sendbytes(16'h3344);
sendbytes(16'h4455);
sendbytes(16'h5566);
bytes_valid[0] = 1'h0;
sendbytes(16'h6677);
bytes_valid[1] = 1'h0;
sendbytes(16'h0000);
sendbytes(16'h0000);
sendbytes(16'h0000);
reset = 1'h1;
sendbytes(16'h0000);
reset = 1'h0;
sendbytes(16'h0000);
sendbytes(16'h0000);
bytes_valid[0] = 1'h1;
bytes_valid[1] = 1'h1;
sendbytes(16'hB8B8);
sendbytes(16'h1111);
sendbytes(16'h2222);
sendbytes(16'h3333);
sendbytes(16'h4444);
sendbytes(16'h5555);
sendbytes(16'h6666);
bytes_valid[0] = 1'h0;
bytes_valid[1] = 1'h0;
sendbytes(16'h7777);
sendbytes(16'h0000);
sendbytes(16'h0000);
sendbytes(16'h0000);
reset = 1'h1;
sendbytes(16'h0000);
reset = 1'h0;
sendbytes(16'h0000);
sendbytes(16'h0000);
bytes_valid[1] = 1'h1;
sendbytes(16'hB800);
sendbytes(16'h1100);
bytes_valid[0] = 1'h1;
sendbytes(16'h22B8);
sendbytes(16'h3311);
sendbytes(16'h4422);
sendbytes(16'h5533);
sendbytes(16'h6644);
bytes_valid[1] = 1'h0;
sendbytes(16'h7755);
sendbytes(16'h8866);
bytes_valid[0] = 1'h0;
sendbytes(16'h0000);
sendbytes(16'h0000);
sendbytes(16'h0000);
end
endmodule
| 6.552817 |
module tb_csi_rx_lane_phy;
reg RST_N;
reg CLK_P;
wire CLK_N;
reg CLK_DIV;
reg DIN_P;
wire DIN_N;
reg DOUT_CLK;
wire DOUT_VALID;
wire [7:0] DOUT;
initial begin
CLK_P = 0;
CLK_DIV = 0;
DOUT_CLK = 0;
RST_N = 0;
#100;
RST_N = 1;
end
always begin
#(2) CLK_P <= ~CLK_P;
end
always begin
#(4) CLK_DIV <= ~CLK_DIV;
end
always begin
#(8) DOUT_CLK <= ~DOUT_CLK;
end
assign CLK_N = ~CLK_P;
initial begin
#100000;
$finish();
end
always begin
wait (RST_N);
#(1) DIN_P = 1; // 1001_0101
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 1; // 1011_0111
#(2) DIN_P = 1;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0; // 1010_1010
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0; // 1010_1010
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(2) DIN_P = 0;
#(2) DIN_P = 1;
#(1);
end
assign DIN_N = ~DIN_P;
wire clk_bit, clk_byte;
csi_rx_clk_phy u_csi_rx_clk_phy (
.RST_N(RST_N),
.MIPI_CLK_P(CLK_P),
.MIPI_CLK_N(CLK_N),
.CLK_BIT (clk_bit),
.CLK_DIV (),
.CLK_BYTE(data_clk)
);
csi_rx_lane_phy u_csi_rx_lane_phy (
.RST_N(RST_N),
.CLK_P(clk_bit),
.CLK_N(~clk_bit),
.CLK_DIV(data_clk),
.DIN_P(DIN_P),
.DIN_N(DIN_N),
.DOUT_CLK(DOUT_CLK),
.DOUT_VALID(DOUT_VALID),
.DOUT(DOUT)
);
endmodule
| 6.552817 |
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