code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_img_mnist_unit ();
localparam RATE = 1000.0 / 300.0;
initial begin
$dumpfile("tb_img_mnist_unit.vcd");
$dumpvars(2, tb_img_mnist_unit);
#20000000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
wire cke = 1'b1;
localparam FILE_NAME = "mnist_test.txt";
localparam DATA_SIZE = 10000;
localparam USER_WIDTH = 8;
localparam INPUT_WIDTH = 28 * 28;
localparam OUTPUT_WIDTH = 30;
reg [USER_WIDTH+INPUT_WIDTH-1:0] mem[0:DATA_SIZE-1];
initial begin
$readmemb(FILE_NAME, mem);
end
reg [28*28-1:0] input_mem[0:255];
reg [1080-1:0] lut0_mem[0:255];
reg [180-1:0] lut1_mem[0:255];
reg [30-1:0] lut2_mem[0:255];
initial begin
$readmemb("mnist_mpl_mini_input.txt", input_mem);
$readmemb("mnist_mpl_mini_lut0.txt", lut0_mem);
$readmemb("mnist_mpl_mini_lut1.txt", lut1_mem);
$readmemb("mnist_mpl_mini_lut2.txt", lut2_mem);
end
reg [180-1:0] lut1_in_mem [0:255];
reg [180-1:0] lut1_out_mem[0:255];
initial begin
$readmemb("mnist_mpl_mini_lut1_in.txt", lut1_in_mem);
$readmemb("mnist_mpl_mini_lut1_out.txt", lut1_out_mem);
end
wire [ 28*28-1:0] input_sig0 = input_mem[0];
wire [ 1080-1:0] lut0_sig0 = lut0_mem[0];
wire [ 180-1:0] lut1_sig0 = lut1_mem[0];
wire [ 30-1:0] lut2_sig0 = lut2_mem[0];
wire [ 180-1:0] lut1_in_sig0 = lut1_in_mem[0];
wire [ 180-1:0] lut1_out_sig0 = lut1_out_mem[0];
integer index = 0;
wire [ USER_WIDTH-1:0] in_user;
wire [INPUT_WIDTH-1:0] in_data;
reg in_valid = 0;
assign {in_user, in_data} = in_valid ? mem[index] : {(USER_WIDTH + INPUT_WIDTH) {1'bx}};
always @(posedge clk) begin
if (reset) begin
index <= 0;
in_valid <= 1'b0;
end else begin
index <= index + in_valid;
in_valid <= 1'b1;
if (index == DATA_SIZE - 1) begin
index <= 0;
end
end
end
wire [USER_WIDTH-1:0] out_user;
wire [ 1:0] out_count;
wire [ 3:0] out_number;
wire out_valid;
img_mnist_unit #(
.USER_WIDTH(USER_WIDTH)
) i_img_mnist_unit (
.reset(reset),
.clk (clk),
.cke (cke),
.in_user (in_user),
.in_data (in_data),
.in_valid(in_valid),
.out_user (out_user),
.out_count (out_count),
.out_number(out_number),
.out_valid (out_valid)
);
wire match = (out_number == out_user) && (out_count > 0);
endmodule
| 6.910056 |
module tb_imm_gen ();
reg [31:0] i_instruction;
reg [ 2:0] i_sel;
wire [31:0] o_dataout;
imm_gen DUT (
i_instruction,
i_sel,
o_dataout
);
task input_t();
begin
i_instruction = 32'h12353112; //0001_0010_0011_0101_0011_0001_0001_0010
i_sel = {$random} % 8;
end
endtask
initial begin
repeat (10) begin
input_t;
#10;
end
$finish;
end
initial begin
$dumpfile("tb_reg_file.vcd");
$dumpvars();
end
initial $monitor("instruction:%b /n i_sel:%d /n o_dataout:%h", i_instruction, i_sel, o_dataout);
endmodule
| 6.501145 |
module test_impl_micron_controller (
input clk50MHz,
input sw_7,
input sw_6,
input sw_1,
input sw_0,
output mwe_L,
output moe_L,
output madv_L,
output mclk,
output mub_L,
output mlb_L,
output mce_L,
output mcre,
input mwait,
output ready,
//output reg clk_slow,
output [22:0] maddr,
output [7:0] debug_out,
inout [15:0] mem_data
);
/*reg [31:0] cntr;
initial begin
cntr <= 0;
clk_slow <= 0;
end
always@(posedge clk50MHz) begin
cntr <= cntr + 1;
if (cntr == 50000000) begin
cntr <= 0;
clk_slow <= ~clk_slow;
end
end */
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [7:0] req;
assign req[6:0] = 0;
wire [7:0] ack;
wire [BUS_WIDTH-1:0] master_out;
wire [CTRL_WIDTH-1:0] master_ctrl_out;
wire [BUS_WIDTH-1:0] bus_data_out;
wire [CTRL_WIDTH-1:0] bus_ctrl_out;
wire [BUS_WIDTH-1:0] slave_out;
wire [CTRL_WIDTH-1:0] slave_ctrl_out;
micron_controller sramctrl (
.clk50MHz(clk50MHz),
.bus_data_in(bus),
.bus_data_out(slave_out),
.bus_ctrl_in(ctrl),
.bus_ctrl_out(slave_ctrl_out),
.bus_ack(ack[0]),
.ready(ready),
.reset_external(sw_7),
.mem_data(mem_data),
.maddr(maddr),
.moe_L(moe_L),
.mwe_L(mwe_L),
.madv_L(madv_L),
.mclk(mclk),
.mub_L(mub_L),
.mlb_L(mlb_L),
.mce_L(mce_L),
.mcre(mcre),
.mwait(mwait)
);
/*
tb_impl_test_master master(.bus_in(bus),
.ack(ack[7]),
.clk(clk50MHz),
.req(req[7]),
.ready_in(ready),
.writeTransfer(sw_6),
.en(~sw_7),
.debug_sel({sw_1, sw_0}),
.bus_out(master_out),
.ctrl_in(ctrl),
.ctrl_out(master_ctrl_out),
.debug_out(debug_out));
BusController controller(.req(req),
.clk(clk50MHz),
.ack(ack),
.bus_in_0(slave_out),
.bus_in_7(master_out),
.bus_out(bus),
.ctrl_in_0(slave_ctrl_out),
.ctrl_in_7(master_ctrl_out),
.ctrl_out(ctrl));
*/
endmodule
| 6.652946 |
module tb_impl_uart_interface (
input clk50MHz,
input rx,
output tx,
output [7:0] debug_out
);
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
wire [7:0] req;
assign req[6:0] = 0;
wire [7:0] ack;
reg clk;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [BUS_WIDTH-1:0] master_out;
wire [CTRL_WIDTH-1:0] master_ctrl_out;
uartInterface master (
.bus_in(bus),
.bus_ack(ack[7]),
.clk50MHz(clk50MHz),
.bus_req(req[7]),
.bus_out(master_out),
.ctrl_in(ctrl),
.ctrl_out(master_ctrl_out),
.rx(rx),
.tx(tx)
);
wire [ BUS_WIDTH-1:0] slave_out;
wire [CTRL_WIDTH-1:0] slave_ctrl_out;
tb_test_slave slave (
.bus_in(bus),
.ack(ack[0]),
.clk(clk50MHz),
.bus_out(slave_out),
.ctrl_in(ctrl),
.ctrl_out(slave_ctrl_out),
.debug_out(debug_out)
);
BusController controller (
.req(req),
.clk(clk50MHz),
.ack(ack),
.bus_in_0(slave_out),
.bus_in_7(master_out),
.bus_out(bus),
.ctrl_in_0(slave_ctrl_out),
.ctrl_in_7(master_ctrl_out),
.ctrl_out(ctrl)
);
endmodule
| 7.862894 |
modules testbench
* Dependencies :
*
* Company : Beijing soul
* Author : Hu Gang
*
*****************************************************************************/
`timescale 1ns/1ps
module tb(/*AUTOARG*/
// Outputs
stream_valid, stream_left, stream_done, stream_data2,
stream_data1, stream_data0, fi_cnt,
// Inputs
m_endn
);
parameter LZF_WIDTH = 20;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input m_endn; // To data of data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [LZF_WIDTH-1:0]fi_cnt; // From data of data.v
output [31:0] stream_data0; // From jhash_in of jhash_in.v
output [31:0] stream_data1; // From jhash_in of jhash_in.v
output [31:0] stream_data2; // From jhash_in of jhash_in.v
output stream_done; // From jhash_in of jhash_in.v
output [1:0] stream_left; // From jhash_in of jhash_in.v
output stream_valid; // From jhash_in of jhash_in.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ce; // From data of data.v
wire clk; // From data of data.v
wire [63:0] fi; // From data of data.v
wire fo_full; // From data of data.v
wire m_last; // From data of data.v
wire m_src_getn; // From jhash_in of jhash_in.v
wire rst; // From data of data.v
wire src_empty; // From data of data.v
// End of automatics
data data(/*AUTOINST*/
// Outputs
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
// Inputs
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.chk";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
reg stream_ack;
jhash_in jhash_in(/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]),
// Inputs
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty),
.stream_ack (stream_ack));
initial
begin
$dumpfile("tb_in.vcd");
$dumpvars(0, tb);
stream_ack = 1'b1;
@(posedge stream_done);
$finish;
end
endmodule
| 6.73988 |
module tb_incomp_case;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
incomp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_incomp_case.vcd");
$dumpvars(0, tb_incomp_case);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#5000 $finish;
end
always #317 i0 = ~i0;
always #600 clk = ~clk;
always #37 i1 = ~i1;
always #57 i2 = ~i2;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.284379 |
module tb_incomp_case_net;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
incomp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_incomp_case_net.vcd");
$dumpvars(0, tb_incomp_case_net);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#5000 $finish;
end
always #317 i0 = ~i0;
always #600 clk = ~clk;
always #37 i1 = ~i1;
always #57 i2 = ~i2;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.284379 |
module tb_input_top11 ();
reg clk, rstn;
reg req;
reg [15:0] data; //input
initial begin
clk = 1'b0;
rstn = 1'b0; //复位
req = 1'b1; //打开输入请求
data = 16'h7fff; //输入1
#80 rstn = 1'b1; // 解除复位
data = 16'h7fff;
#400 data = 16'h0000; //输入0
end
always begin
#5 clk = ~clk; //10ns 时钟
end
fft_top fft_top (
.clk(clk),
.rstn(rstn),
.req_i(req),
.data_i(data)
);
endmodule
| 7.333101 |
module TB_Insertion_block #(
parameter W = 42
);
// Inputs
reg clk;
reg rst;
reg wr, rd;
reg [(W-1)-1:0] data_in;
reg sub;
reg repair_period;
// Outputs
wire [(W-1)-1:0] data_out;
wire data_valid;
wire [(W-1)-1:0] data_fail;
wire fail;
// Instantiate the Unit Under Test (UUT)
Insertion_block #(
.W((W)),
.N(4)
) Insertion_block (
.clk(clk),
.rst(rst),
.subtract(sub),
.wr(wr),
.rd(rd),
.data_in(data_in),
.repair_period(repair_period),
.data_out(data_out),
.empty(data_valid),
.data_fail(data_fail),
.fail(fail)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
// Initialize Inputs
wr = 0;
data_in = 0;
rd = 0;
sub = 0;
repair_period = 0;
rst = 1;
@(posedge clk) rst = 0;
////// tasks
forever begin
wr = 1;
data_in = {8'h01, 16'h0006, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h02, 16'h0007, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h03, 16'h0008, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h04, 16'h0009, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h05, 16'h0006, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h06, 16'h0005, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h07, 16'h0004, 16'h0004, 1'b0};
@(posedge clk) data_in = {8'h08, 16'h0004, 16'h0004, 1'b0};
@(posedge clk) wr = 0;
@(posedge clk) @(posedge clk) @(posedge clk) @(posedge clk) sub = 1;
@(posedge clk) sub = 0;
repair_period = 1;
@(posedge clk) @(posedge clk) @(posedge clk) @(posedge clk) repair_period = 0;
rd = 1;
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
rd = 0;
end
end
/* initial begin
forever begin
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
rd = ~wr;
@(posedge clk)
rd = 0;
end
end*/
endmodule
| 6.726677 |
module TB_INST ();
reg CLOCK_50;
reg rst;
initial begin
$display("simulation started!");
rst = 1'b0;
CLOCK_50 = 1'b0;
forever #2 CLOCK_50 = ~CLOCK_50;
end
SOPC sopc1 (
.clk(CLOCK_50),
.rst(rst)
);
reg dbus_we_delay;
reg [15:0] dbus_addr_delay;
reg [31:0] dbus_data_delay;
reg [31:0] addr;
always @(negedge CLOCK_50) begin
dbus_we_delay <= sopc1.fake_ram1.ramWriteEnable_i;
dbus_addr_delay <= {sopc1.fake_ram1.ramAddr_i[15:2], 2'b0};
dbus_data_delay <= sopc1.fake_ram1.data_w;
end
reg post_stall;
always @(negedge CLOCK_50) begin
post_stall <= sopc1.fake_ram1.stall;
end
task judge;
input integer fans, cycle;
input reg [8*25:1] out;
reg [8*25:1] ans;
begin
$fscanf(fans, "%s\n", ans);
if (out != ans && ans != "skip") begin
$display("[%0d] %s", cycle, out);
$display("[Error] Expected: %0s, Got: %0s", ans, out);
$stop;
end else begin
$display("[%0d] %s [%s]", cycle, out, ans == "skip" ? "Skip" : "Correct");
end
end
endtask
task unitTest;
input [128*8-1:0] name;
integer i, fans, cycle, is_event;
reg [8*25:1] ans, out, info;
begin
$display("======= Unit Test : %0s Started =======\n", name, name);
cycle = 0;
is_event = 0;
for (i = 0; i < 1025; i = i + 1) begin
sopc1.fake_rom1.instructions[i] = 32'h0;
end
for (i = 0; i < 8192; i = i + 1) begin
sopc1.fake_ram1.inst_ram[i] = 32'h0;
end
fans = $fopen({`PATH_PREFIX1, name, ".ans"}, "r");
$display("File .ans Loaded.");
if (fans) begin
$readmemh({`PATH_PREFIX1, name, ".mem"}, sopc1.fake_rom1.instructions, 0, 1023);
$display("File .mem Loaded.");
end
begin
rst = 1'b1;
#50 rst = 1'b0;
end
cycle = 0;
while (!$feof(
fans
)) begin
@(negedge CLOCK_50);
cycle = cycle + 1;
if (sopc1.cpu1.regWriteAddr_mem_wb_to_reg && sopc1.cpu1.regWriteEnable_mem_wb_to_reg) begin
$sformat(out, "$%0d=0x%x", sopc1.cpu1.regWriteAddr_mem_wb_to_reg,
sopc1.cpu1.regWriteData_mem_wb_to_reg);
judge(fans, cycle, out);
end
if (sopc1.cpu1.regHILOEnable_mem_wb_to_hilo) begin
$sformat(out, "$hilo=0x%x%x", sopc1.cpu1.regHI_mem_wb_to_hilo,
sopc1.cpu1.regLO_mem_wb_to_hilo);
judge(fans, cycle, out);
end
if (dbus_we_delay) begin
$sformat(out, "[0x%x]=0x%x", dbus_addr_delay[15:0], dbus_data_delay);
judge(fans, cycle, out);
end
end
$display("======= Unit Test : %0s Finished =======\n", name, name);
end
endtask
initial begin
wait (rst == 1'b0);
$display("Unit Test Started.\n");
unitTest("except_delayslot");
unitTest("inst_arith");
unitTest("inst_jump");
unitTest("inst_llsc");
unitTest("inst_logical");
unitTest("inst_mem_aligned");
unitTest("inst_mem_unaligned");
unitTest("inst_move");
unitTest("inst_multicyc");
unitTest("inst_ori");
unitTest("inst_shift");
unitTest("inst_trap");
$display("[Done]", 0);
$display("Unit Test Finished.\n");
$finish;
$stop;
end
endmodule
| 7.831 |
module InstructionMemoryTestbench;
reg clock;
reg [7:0] in;
wire [7:0] out;
InstructionMemory dut (
clock,
in,
out
);
initial begin
clock = 1;
in = 0;
$display("Teste 1: Buscando a intrucao 0");
in = 0;
#1 clock = 0;
#1 clock = 1;
in = 0;
$display("Teste 2: Buscando a instrucao 1");
in = 1;
#1 clock = 0;
#1 clock = 1;
in = 0;
$display("Teste 3: Buscando a instrucao 2");
in = 2;
#1 clock = 0;
#1 clock = 1;
in = 0;
$display("Teste 4: Buscando a instrucao 3");
in = 3;
#1 clock = 0;
#1 clock = 1;
in = 0;
end
initial begin
$monitor("Time=%0d, Clock=%b, in=%d, out=%b ", $time, clock, in, out);
end
endmodule
| 6.694363 |
module tb_instructionRegister ();
wire [3:0] OPCODE, FUNCFIELD;
wire [3:0] A_ReadReg1RT, A_ReadReg2RT;
wire [1:0] A_Offset, A_RegSWLW;
wire [3:0] A_WriteRegRT_BT;
reg [15:0] D_MemData;
reg C_IRWrite;
reg clk, rst;
instructionRegister uut (
OPCODE,
FUNCFIELD,
A_ReadReg1RT,
A_ReadReg2RT,
A_Offset,
A_RegSWLW,
A_WriteRegRT_BT,
D_MemData,
C_IRWrite,
clk,
rst
);
initial begin
#00 clk = 1'b0;
forever #10 clk = ~clk;
end
initial begin
#0 rst = 1;
#17 D_MemData = 16'b1000_1011_0100_1000;
C_IRWrite = 1'b1;
rst = 0; //add
/* #17 D_MemData = 16'b1001_1011_11001001; C_IRWrite = 1'b1; rst = 0; //addimex
#17 D_MemData = 16'b1010_1011_11001001; C_IRWrite = 1'b1; rst = 0; //addimz
#17 D_MemData = 16'b1100_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //sub
#17 D_MemData = 16'b1101_1011_11001001; C_IRWrite = 1'b1; rst = 0; //subimex
#17 D_MemData = 16'b1110_1011_11001001; C_IRWrite = 1'b1; rst = 0; //subimz
#17 D_MemData = 16'b0000_1011_0100_0001; C_IRWrite = 1'b1; rst = 0; //shl
#17 D_MemData = 16'b0000_1011_0100_0010; C_IRWrite = 1'b1; rst = 0; //shr
#17 D_MemData = 16'b0000_1011_0100_0011; C_IRWrite = 1'b1; rst = 0; //sar
#17 D_MemData = 16'b1011_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //lnandr
#17 D_MemData = 16'b1111_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //lorr
#17 D_MemData = 16'b0111_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lnandim
#17 D_MemData = 16'b0110_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lorim
#17 D_MemData = 16'b0100_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //be
#17 D_MemData = 16'b0101_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //bne
#17 D_MemData = 16'b0011_101101111000; C_IRWrite = 1'b1; rst = 0; //jmp
#17 D_MemData = 16'b0001_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lw
#17 D_MemData = 16'b0010_1011_11001001; C_IRWrite = 1'b1; rst = 0; //sw
*/ #17 C_IRWrite = 1'b0;
rst = 0;
#17 C_IRWrite = 1'b0;
rst = 1;
#17 C_IRWrite = 1'b1;
rst = 1;
/* #17 D_MemData = 16'b1000_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //add
#17 D_MemData = 16'b1001_1011_11001001; C_IRWrite = 1'b1; rst = 0; //addimex
#17 D_MemData = 16'b1010_1011_11001001; C_IRWrite = 1'b1; rst = 0; //addimz
#17 D_MemData = 16'b1100_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //sub
#17 D_MemData = 16'b1101_1011_11001001; C_IRWrite = 1'b1; rst = 0; //subimex
#17 D_MemData = 16'b1110_1011_11001001; C_IRWrite = 1'b1; rst = 0; //subimz
#17 D_MemData = 16'b0000_1011_0100_0001; C_IRWrite = 1'b1; rst = 0; //shl
#17 D_MemData = 16'b0000_1011_0100_0010; C_IRWrite = 1'b1; rst = 0; //shr
#17 D_MemData = 16'b0000_1011_0100_0011; C_IRWrite = 1'b1; rst = 0; //sar
#17 D_MemData = 16'b1011_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //lnandr
#17 D_MemData = 16'b1111_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //lorr
#17 D_MemData = 16'b0111_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lnandim
#17 D_MemData = 16'b0110_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lorim
#17 D_MemData = 16'b0100_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //be
#17 D_MemData = 16'b0101_1011_0100_1000; C_IRWrite = 1'b1; rst = 0; //bne
#17 D_MemData = 16'b0011_101101111000; C_IRWrite = 1'b1; rst = 0; //jmp
#17 D_MemData = 16'b0001_1011_11001001; C_IRWrite = 1'b1; rst = 0; //lw
*/
#17 D_MemData = 16'b0010_1011_11001001;
C_IRWrite = 1'b1;
rst = 0; //sw
#17 $stop;
end
initial begin
$dumpfile("instructionRegister.vcd");
$dumpvars;
end
endmodule
| 7.102099 |
module tb_instruction_fsm;
// Inputs
reg clk;
reg reset;
reg instr_fsm_enable;
// Outputs
wire e;
wire instr_fsm_done;
wire upper;
reg [9:0] instruction;
wire [5:0] encoding;
instruction_fsm instr_fsm (
.clk(clk),
.reset(reset),
.instr_fsm_enable(instr_fsm_enable),
.e(e),
.instr_fsm_done(instr_fsm_done),
.upper(upper)
);
assign encoding[5] = instruction[9];
assign encoding[4] = instruction[8];
assign encoding[3:0] = upper ? instruction[7:4] : instruction[3:0];
initial begin
clk = 1;
reset = 0;
instr_fsm_enable = 0;
#100;
reset = 1;
#20;
reset = 0;
// ############ THE TESTING COMMENCE HERE ################
// Going to send a Function Set instruction
instruction = 10'b00_0010_1000;
instr_fsm_enable = 1;
while (instr_fsm_done == 0) #20;
instr_fsm_enable = 0;
#100;
// Going to send Display ON instruction
instruction = 10'b00_0000_1100;
instr_fsm_enable = 1;
while (instr_fsm_done == 0) #20;
instr_fsm_enable = 0;
#100;
// Going to write letter 'S'
instruction = 10'b10_0110_0011;
instr_fsm_enable = 1;
while (instr_fsm_done == 0) #20;
instr_fsm_enable = 0;
end
always #10 clk = ~clk;
endmodule
| 7.102099 |
module tb_instru_mem ();
parameter MEMORY_WIDTH = 8;
parameter MEMORY_DEPTH = 64;
parameter NB_ADDR = 32;
parameter NB_INSTRUCTION = 32;
reg [ NB_ADDR-1:0] read_addr;
reg clock;
reg read_enable;
reg i_write_enable;
reg [ MEMORY_WIDTH-1:0] i_write_data;
wire [NB_INSTRUCTION-1:0] o_data;
initial begin
clock = 1'b0;
read_enable = 1'b0;
i_write_enable = 1'b0;
i_write_data = {MEMORY_WIDTH{1'b0}}; // DEBUG UNIT
read_addr = 6'd0;
// Se leen datos de la memoria
#40 read_addr = 6'd0;
read_enable = 1'b1;
#40 read_addr = 6'd4;
#40 read_addr = 6'd8;
#40 read_addr = 6'd12;
#20 read_enable = 1'b0;
#200 $finish;
end
always #10 clock = ~clock;
instru_mem instru_mem (
.i_clock(clock),
.i_read_enable(read_enable),
.i_write_enable(i_write_enable),
.i_write_data(i_write_data),
.i_read_addr(read_addr),
.o_read_data(o_data)
);
endmodule
| 6.506437 |
module
*/
module mem(
// input [15:0] in_data,
// input [4:0] in_addr,
input [5:0] out_addr,
output [15:0] out_data);
parameter ADDR_WIDTH=6;
parameter DEPTH =1<<ADDR_WIDTH;
reg [15:0] mem_data[DEPTH-1:0];
assign out_data = mem_data[out_addr];
endmodule
| 8.043954 |
module tb_instFetch;
//Port declarition
reg clk;
reg [5:0] mem_addr;
reg rst;
wire [31:0] inst;
wire valid;
wire [15:0] inst_hw;
wire is_inst_len_16;
integer fl;
//Module instancise
inst_fetch top (
inst_hw,
clk,
rst,
inst,
valid,
is_inst_len_16
);
mem inst_mem (
mem_addr,
inst_hw
);
//input Signals initialization
initial begin
clk = 0;
mem_addr = 0;
rst = 1;
#6 rst = 0;
end
//Clock generation
always #5 clk = ~clk;
//PC emulation
always @(posedge clk) begin
if (valid == 1'b1 || valid == 1'b0) begin
mem_addr = mem_addr + 1;
end
end
//Logging
initial begin
$readmemh("./inst.dat", inst_mem.mem_data);
fl = $fopen("./inst_fetch.log", "w");
$fdisplay(fl, "valid\tis_lsb_hw\tis_inst_len_16\tinst_hw\tinst\tmem_addr\ttime");
$fsdbDumpfile("./waveform.fsdb");
$fsdbDumpvars();
end
always @(posedge clk) begin
if (mem_addr == 36) begin
$finish;
end else begin
#1
$fdisplay(
fl,
"%b\t%b\t%b\t%h\t%h\t%d\t@ %d",
valid,
top.is_lsb_hw,
is_inst_len_16,
inst_hw,
inst,
mem_addr,
$time
);
end
end
endmodule
| 6.736553 |
module tb_inst_mem;
// Inputs
reg clk;
reg rst;
reg inst_in_v;
reg [`INST_WIDTH-1:0] inst_in;
// Outputs
wire inst_out_v;
wire [`INST_WIDTH-1:0] inst_out;
// Instantiate the Unit Under Test (UUT)
inst_mem uut (
.clk(clk),
.rst(rst),
.inst_in_v(inst_in_v),
.inst_in(inst_in),
.inst_out_v(inst_out_v),
.inst_out(inst_out)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
inst_in_v = 0;
inst_in = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
// Add stimulus here
#20;
inst_in_v = 0;
rst = 0;
#20;
inst_in_v = 0;
#20;
inst_in_v = 0;
#20;
inst_in_v = 0;
#20;
inst_in_v = 1;
inst_in = 32'hffff0000;
#20;
inst_in_v = 1;
inst_in = 32'hffffaaaa;
#20;
inst_in_v = 1;
inst_in = 32'hffffbbbb;
#20;
inst_in_v = 1;
inst_in = 32'hffffcccc;
#20;
inst_in_v = 1;
inst_in = 32'hffffdddd;
#20;
inst_in_v = 0;
inst_in = 0;
#20;
inst_in_v = 0;
#20;
inst_in_v = 0;
#20;
inst_in_v = 0;
#1000;
end
endmodule
| 6.994919 |
module
// Module Name: C:/Users/Filipe/Documents/Classes/Spring - 2013/SystemOnChipDesign/Project5/ise_project/tb_interface_plus_cell.v
// Project Name: soc_with_memory
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: memory_test_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_interface_plus_cell;
// Inputs
reg clk;
reg reset;
reg [7:0] data_in;
reg [3:0] address;
reg write;
reg read;
reg [22:0] i;
reg [15:0] dado;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
memory_test_module uut (
.clk(clk),
.reset(reset),
.data_out(data_out),
.data_in(data_in),
.addr_mem_interface(address),
.write(write),
.read(read)
);
always #5
clk = ~ clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
data_in = 0;
address = 0;
write = 0;
read = 0;
dado = 16'hC2A5;
#10;
reset = 1;
#200000;
i=23'h50AEDF;
for(i=0; i<23'h200; i=i+1) begin
#10;
address = 1;
data_in = i[7:0];
write = 1;
read = 0;
#10;
address = 2;
data_in = i[15:8];
write=1;
read = 0;
#10;
address = 3;
data_in = i[22:16];
write=1;
read = 0;
//data = 0xEEFF
//write data register
#10;
address = 4;
data_in = dado[7:0];
write = 1;
read = 0;
#10;
address = 5;
data_in = dado[15:8];
write = 1;
read = 0;
#10;
address=0;
write=0;
#10;
write=1;
address=9;
#50;
write=0;
address=9;
#150;
end
//read all memory positions
for(i=0; i<23'h200; i=i+1) begin
#10;
address = 1;
data_in = i[7:0];
write = 1;
read = 0;
#10;
address = 2;
data_in = i[15:8];
write=1;
read = 0;
#10;
address = 3;
data_in = i[22:16];
write=1;
read = 0;
//READ MEM
address = 8;
read = 0;
write = 1;
#50;
write = 0;
#90;
end
$finish;
// Add stimulus here
end
endmodule
| 6.999332 |
module tb;
parameter DATA_WIDTH=8, // Width of data bus
ADDR_WIDTH=8, // Width of address bus
NUM_INTR=16, // Number of peripheral controllers i.e. max number of interrupts
INTR_SERV=4, // Number of bits required to represent each interrupts (Depends on NUM_INTR)
MAX_DELAY=30, // Max delay to serve one interrupt by Master
TIME_PERIOD=2; // Time period of clock
reg pclk_i, pwrite_i, penable_i, intr_serviced_i, preset_i, psel_i;
reg [DATA_WIDTH-1 : 0] pwdata_i;
reg [ADDR_WIDTH-1 : 0] paddr_i;
reg [NUM_INTR-1 : 0] intr_active_i;
wire pready_o, perror_o, intr_valid_o;
wire [DATA_WIDTH-1 : 0] prdata_o;
wire [INTR_SERV-1 : 0] intr_to_service_o;
reg [INTR_SERV-1 : 0] random_priority_array [NUM_INTR-1 : 0];
reg [30*8 : 1] testname;
integer i;
interrupt_controller #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), .NUM_INTR(NUM_INTR), .INTR_SERV(INTR_SERV)) u0 (.*);
initial begin
pclk_i = 0;
forever #(TIME_PERIOD/2.0) pclk_i = ~pclk_i;
end
initial begin
// Store type of test in testname variable
$value$plusargs("testname=%s",testname);
// intialize reg variables
pwrite_i = 0;
penable_i = 0;
intr_serviced_i = 0;
psel_i = 0;
pwdata_i = 0;
paddr_i = 0;
intr_active_i = 0;
for (i=0; i<NUM_INTR; i=i+1) random_priority_array[i] = 0;
// Hold and release reset
preset_i = 1;
repeat (5) @ (posedge pclk_i);
preset_i = 0;
randomizer(); // create a randomized priority array to use in random_priority test case
for (i=0; i<NUM_INTR; i=i+1) begin
if (testname == "ascending_priority") write_intc(i, i); // (peripheral->priority) 0->0, 1->1, ...n->n
else if (testname == "descending_priority") write_intc(i, NUM_INTR-1-i); // (peripheral->priority) 0->n, 1->n-1, ...n->0
else if (testname == "random_priority") write_intc(i, random_priority_array[i]);
else begin
$display("*** Error testname ***");
i = NUM_INTR;
end
end
intr_active_i = $random;
#300;
intr_active_i = $random;
#300;
intr_active_i = $random;
#300;
$finish;
end
initial begin
forever begin
@(posedge pclk_i);
if (intr_valid_o == 1) begin
#($urandom_range(1,MAX_DELAY)); // time taken by master to serve interrupt request from intc
intr_active_i[intr_to_service_o] = 0; // Specific Peripheral controller indicating INTC that interrupt is serviced
intr_serviced_i = 1; // Master/ processor giving signal to indicate previous interrupt request served
@(posedge pclk_i);
intr_serviced_i = 0; // Master/ processor making reseting flag after INTC already got acknowledged
end
end
end
task write_intc (input reg [ADDR_WIDTH-1 : 0] addr, input reg [DATA_WIDTH-1 : 0]data);
begin
paddr_i = addr;
pwdata_i = data;
pwrite_i = 1;
psel_i = 1;
penable_i = 1;
wait (pready_o == 1);
@(posedge pclk_i);
paddr_i = 0;
pwdata_i = 0;
pwrite_i = 0;
psel_i = 0;
penable_i = 0;
end
endtask
// Task to generate random unique values of priority for each of NUM_INTR peripheral controllers
// This randomizer task is used in random_priority test case
task randomizer();
reg [INTR_SERV-1 : 0] temp;
reg unique;
integer j, k;
begin
for (j=0; j<NUM_INTR-1; ) begin
temp = $urandom;
unique = 1;
for (k=0; k<j; k=k+1) begin
if (random_priority_array[k] == temp) begin
unique = 0;
k = j;
end
end
if (unique == 1) begin
random_priority_array[j] = temp;
j=j+1;
end
end
//for (j=0; j<NUM_INTR-1; j=j+1) $display("Port-%d Priority-%d",j,random_priority_array[j]);
end
endtask
endmodule
| 7.110249 |
module tb_intg ();
initial begin
$dumpfile("tb_intg.vcd");
$dumpvars;
end
reg clear, clock;
wire wf;
intg mod (
.wf(wf),
.clear(clear),
.clock(clock)
);
initial clock = 1'b0;
always #0.5 clock = ~clock;
initial begin
clear = 1'b1;
#1 clear = 1'b0;
#1000 $finish;
end
// initial
// $monitor("Main := clock = %b, clear = %b, wf = %b \n Cntr3bit := clock = %b, q = %d \n Cntr4bit := clock = %b, q = %d \n MuxLarge := input = %b, sel = %d, output = %b\n\n",clock, clear, wf, mod.cnt3bit.clock, mod.cnt3bit.q,mod.cnt4bit.clock, mod.cnt4bit.q,mod.mux.inp,mod.mux.sel, mod.mux.outp);
endmodule
| 6.584221 |
module tb;
parameter NUM_INTR = 16;
reg pclk_i, prst_i, pwrite_i, penable_i;
reg [3:0] paddr_i;
reg [3:0] pwdata_i;
wire [3:0] prdata_o;
wire pready_o;
wire pslverr_o;
wire [3:0] intr_to_service_o;
wire intr_valid_o;
reg intr_serviced_i;
reg [NUM_INTR-1:0] intr_active_i;
integer i;
intr_ctlr dut (
//processor
pclk_i,
prst_i,
paddr_i,
pwdata_i,
prdata_o,
pwrite_i,
penable_i,
pready_o,
pslverr_o,
intr_to_service_o,
intr_valid_o,
intr_serviced_i,
//Peripheral controllers
intr_active_i
);
initial begin
pclk_i = 0;
forever #5 pclk_i = ~pclk_i;
end
initial begin
prst_i = 1;
intr_active_i = 0;
paddr_i = 0;
pwdata_i = 0;
pwrite_i = 0;
penable_i = 0;
repeat (2) @(posedge pclk_i);
prst_i = 0;
//program the regsiters for priority values
for (i = 0; i < NUM_INTR; i = i + 1) begin
reg_write(i, NUM_INTR - 1 - i);
end
//raise interrupts
intr_active_i = $random;
//Dropping hand: make corrersponding bit in intr_active_i to 0
#500;
intr_active_i = $random;
#500;
$finish;
end
always begin
@(posedge pclk_i);
if (intr_valid_o == 1) begin //Processor logic
#30; //to process the question or interrupt
intr_active_i[intr_to_service_o] = 0; //dropping the interrupt ===> peripheral logic
intr_serviced_i = 1; //processor logic
@(posedge pclk_i);
intr_serviced_i = 0;
end
end
task reg_write(input [3:0] addr, input [3:0] data);
begin
@(posedge pclk_i);
paddr_i = addr; //0->1->2...
pwdata_i = data; //(i : giving lowest priority, 15-i : giving highest priority)
pwrite_i = 1;
penable_i = 1;
wait (pready_o == 1);
@(posedge pclk_i);
pwrite_i = 0;
penable_i = 0;
paddr_i = 0;
pwdata_i = 0;
end
endtask
endmodule
| 6.612288 |
module tb_int_ctl ();
reg clk;
reg rst_n;
// drive signal
reg [7:0] IE;
reg [7:0] TCON;
reg [1:0] SCON;
// out signal
wire [4:0] interupt;
wire [7:0] TCON_out;
// clk generator
initial begin
clk = 0;
forever #1 clk = ~clk;
end
// reset generator
initial begin
rst_n = 1'b1;
#5 rst_n = 1'b0;
#15 rst_n = 1'b1;
end
// enable interupt
initial begin
repeat (20) #({$random} % 10 + 5) IE = {$random} % 256;
end
// set interupt flag
initial begin
repeat (20) begin
#({$random} % 10 + 5) TCON = {$random} % 32;
SCON = {$random} % 4;
end
end
IntControl IntControl_ins (
.clk(clk),
.rst_n(rst_n),
.IE(IE),
.TCON(TCON),
.SCON(SCON),
.interupt(interupt),
.TCON_out(TCON_out)
);
endmodule
| 6.749346 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
// Clock Interface
reg clk;
reg reset;
reg [ 3:0] int_vec;
wire mem_valid;
reg mem_ready;
wire [31:0] mem_address;
wire mem_wr_en;
wire [31:0] mem_wr_data;
wire [ 3:0] mem_wr_size;
reg mem_dp_valid;
wire mem_dp_ready;
reg [31:0] mem_dp_read_data;
wire flush_fetch;
wire flush_decode_0;
wire flush_decode_1;
wire flush_register;
wire flush_address;
wire flush_execute;
wire flush_writeback;
wire fetch_load;
wire [31:0] fetch_load_address;
wire decode_start_int;
reg decode_end_int;
wire reg_load_cs;
wire [15:0] reg_cs;
sys_cont_top uut (
clk,
reset,
int_vec,
mem_valid,
mem_ready,
mem_address,
mem_wr_en,
mem_wr_data,
mem_wr_size,
mem_dp_valid,
mem_dp_ready,
mem_dp_read_data,
flush_fetch,
flush_decode_0,
flush_decode_1,
flush_register,
flush_address,
flush_execute,
flush_writeback,
fetch_load,
fetch_load_address,
decode_start_int,
decode_end_int,
reg_load_cs,
reg_cs
);
initial begin
$strobe("============ \n Begin Test \n============");
reset = 1;
clk = 0;
int_vec = 0;
mem_dp_read_data = 32'h3000;
#55 reset = 0;
#20 int_vec = 1;
#20 int_vec = 0;
$display("==========\n End Test \n==========");
end
initial #2000 $finish;
always @(posedge clk) begin
if (reset) begin
//f_valid <= 1'b1;
mem_ready <= 0;
mem_dp_valid <= 0;
decode_end_int <= 0;
end else begin
//f_valid <= (f_valid) ? ~f_ready : 1'b0;
mem_ready <= (mem_ready) ? 1 : mem_valid;
mem_dp_valid <= (mem_dp_valid) ? 1 : mem_ready;
decode_end_int <= (decode_end_int) ? 1 : decode_start_int;
end
end
always #10 clk = ~clk;
initial begin
$vcdplusfile("sys_cont_seq.dump.vpd");
$vcdpluson(0, TOP);
end
endmodule
| 6.594167 |
module tb_inverter;
reg [`WIDTH-1:0] p;
reg [`WIDTH-1:0] q;
reg clk;
reg reset;
wire finish;
wire [`WIDTH-1:0] e;
wire [`WIDTH*2-1:0] d;
inverter uut (
p,
q,
clk,
reset,
finish,
e,
d
);
initial begin
p = 32'd23;
q = 32'd5;
clk = 0;
reset = 0;
#10 reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
endmodule
| 6.926467 |
module: io_buf
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_iobuf;
// Inputs
reg [15:0] I;
reg T;
// Outputs
wire [15:0] O;
// Bidirs
wire [15:0] IO;
reg [15:0] IO_BUF;
// Instantiate the Unit Under Test (UUT)
io_buf uut (
.IO(IO),
.O(O),
.I(I),
.T(T)
);
assign IO = IO_BUF;
initial begin
// Initialize Inputs
I = 0;
T = 1;
IO_BUF = 16'hAABB;
#20;
I = 16'h4433;
T = 0;
IO_BUF = 16'hzzzz;
#20;
I = 16'h0022;
T = 0;
IO_BUF = 16'hzzzz;
#20;
T = 1;
IO_BUF = 16'hCCFF;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.819267 |
module: ip_header_checksum
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ip_header_checksum;
// Inputs
reg clk;
reg [31:0] header;
reg reset;
// Outputs
wire [15:0] checksum;
// Instantiate the Unit Under Test (UUT)
ip_header_checksum uut (
.clk(clk),
.checksum(checksum),
.header(header),
.reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
header = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
@(posedge clk);
reset = 0;
header = 32'h4500_0030;
@(posedge clk);
header = 32'h4422_4000;
@(posedge clk);
header = 32'h8006_0000;
@(posedge clk);
header = 32'h8c7c_19ac;
@(posedge clk);
header = 32'hae24_1e2b;
@(posedge clk);
@(posedge clk);
$display("%h - should be 442E", checksum);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$display("%h - should still be 442E", checksum);
// Verifying a header with a valid checksum should give ffff.
reset = 1;
@(posedge clk);
reset = 0;
header = 32'h4500_0030;
@(posedge clk);
header = 32'h4422_4000;
@(posedge clk);
header = 32'h8006_442e;
@(posedge clk);
header = 32'h8c7c_19ac;
@(posedge clk);
header = 32'hae24_1e2b;
@(posedge clk);
@(posedge clk);
$display("%h - should be FFFF", checksum);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$display("%h - should still be FFFF", checksum);
$stop;
// Add stimulus here
end
always begin
#10;
clk = ~clk;
end
endmodule
| 7.241327 |
module tb_ip_receive ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
//板卡MAC地址
parameter BOARD_MAC = 48'h12_34_56_78_9A_BC;
//板卡IP地址
parameter BOARD_IP = {8'd169, 8'd254, 8'd1, 8'd23};
//reg define
reg eth_rx_clk; //PHY芯片接收数据时钟信号
reg eth_tx_clk; //PHY芯片发送数据时钟信号
reg sys_rst_n; //系统复位,低电平有效
reg eth_rxdv; //PHY芯片输入数据有效信号
reg [3:0] data_mem[171:0]; //data_mem是一个存储器,相当于一个ram
reg [7:0] cnt_data; //数据包字节计数器
reg start_flag; //数据输入开始标志信号
//wire define
wire rec_end; //数据接收使能信号
wire [3:0] rec_en; //接收数据
wire rec_data; //数据包接收完成信号
wire rec_data_num; //接收数据字节数
wire [3:0] eth_rx_data; //PHY芯片输入数据
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial $readmemh("E:/GitLib/Altera/EP4CE10/code/54_ethernet/sim/data.txt", data_mem);
//时钟、复位信号
initial begin
eth_rx_clk = 1'b1;
eth_tx_clk = 1'b1;
sys_rst_n <= 1'b0;
start_flag <= 1'b0;
#200 sys_rst_n <= 1'b1;
#100 start_flag <= 1'b1;
#50 start_flag <= 1'b0;
end
always #20 eth_rx_clk = ~eth_rx_clk;
always #20 eth_tx_clk = ~eth_tx_clk;
//eth_rxdv:PHY芯片输入数据有效信号
always @(negedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) eth_rxdv <= 1'b0;
else if (cnt_data == 171) eth_rxdv <= 1'b0;
else if (start_flag == 1'b1) eth_rxdv <= 1'b1;
else eth_rxdv <= eth_rxdv;
//cnt_data:数据包字节计数器
always @(negedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_data <= 8'd0;
else if (eth_rxdv == 1'b1) cnt_data <= cnt_data + 1'b1;
else cnt_data <= cnt_data;
//eth_rx_data:PHY芯片输入数据
assign eth_rx_data = (eth_rxdv == 1'b1) ? data_mem[cnt_data] : 4'b0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- ethernet_inst -------------
ip_receive #(
.BOARD_MAC(BOARD_MAC), //板卡MAC地址
.BOARD_IP (BOARD_IP) //板卡IP地址
) ip_receive_inst (
.sys_clk (eth_rx_clk), //时钟信号
.sys_rst_n (sys_rst_n), //复位信号,低电平有效
.eth_rxdv (eth_rxdv), //数据有效信号
.eth_rx_data(eth_rx_data), //输入数据
.rec_end (rec_end), //数据接收使能信号
.rec_data_en (rec_en), //接收数据
.rec_data (rec_data), //数据包接收完成信号
.rec_data_num(rec_data_num) //接收数据字节数
);
endmodule
| 7.352738 |
module tb_ir;
reg [15:0] iw = 16'b0000010001100101;
wire [ 3:0] op;
wire [2:0] Ra, Rb, Rd, func;
wire [5:0] imm;
wire [6:0] addr;
ir r (
iw,
op,
Ra,
Rb,
Rd,
func,
imm,
addr
);
initial
$monitor(
"iw = %b, op = %b, Ra = %b, Rb = %b, Rd = %b, func = %b, imm = %b, addr = %b",
iw,
op,
Ra,
Rb,
Rd,
func,
imm,
addr
);
endmodule
| 6.587801 |
module top ();
wire [31:0] inst;
reg clk;
reg reset;
reg read_strobe;
reg [31:0] read_addr;
reg transl;
reg priv;
wire [31:0] read_data;
wire read_stall;
wire [ 1:0] read_fault;
// Memory for IF:
reg [63:0] memory [1023:0];
reg [63:0] emi_read_data;
wire emi_read_req;
wire [31:0] emi_if_address;
wire [ 9:0] ram_addr = emi_if_address[12:3];
always @(posedge clk) begin
if (emi_read_req) begin
emi_read_data <= memory[ram_addr];
end
end
////////////////////////////////////////////////////////////////////////////////
// DUT
itlb_icache IF (
.clk (clk),
.reset(reset),
.read_strobe(read_strobe),
.read_addr (read_addr),
.translation_enabled(transl),
.privileged(priv),
.read_data(read_data),
.stall(read_stall),
.fault(read_fault),
.emi_if_address(emi_if_address),
.emi_if_req(emi_read_req),
.emi_if_rdata(emi_read_data),
.emi_if_valid(1'b1)
);
////////////////////////////////////////////////////////////////////////////////
always #`CLK_P clk <= ~clk;
reg [11:0] i;
initial begin
$dumpfile("tb_itlb_icache.vcd");
$dumpvars(0, top);
clk <= 0;
reset <= 1;
read_strobe <= 0;
read_addr <= 0;
transl <= 0;
priv <= 0;
/* Initialise test memory */
for (i = 0; i < 64; i = i + 1) begin
memory[i] = {magic_number((i * 2) + 1), magic_number(i * 2)};
end
for (i = 0; i < 64; i = i + 1) begin
$display("mem[%d] = %x", i, memory[i]);
end
#`CLK_P;
reset <= 0;
#`CLK_P;
//////////////////////////////////////////////////////////////////////
// Test 1: Read a couple of addresses, test against known RAM contents:
read_and_test(32'h30);
read_and_test(32'h68);
#`CLK;
read_and_test(32'h184);
#`CLK;
read_and_test(32'h110);
#`CLK;
read_and_test(32'h180);
#`CLK;
$display("PASS");
$finish(0);
end
function [31:0] magic_number;
input [9:0] addr;
begin
magic_number = {addr[9:0], addr[9:0], addr[9:0]} ^
{{addr[8:0], addr[8:0], addr[8:0]}, 1'b0} ^
{{addr[3:0], addr[3:0], addr[3:0]}, 4'h1};
// $display("addr %x magic %x", addr, magic_number);
end
endfunction // magic_number
task read_and_test;
input [31:0] address;
reg [ 9:0] timeout;
reg [31:0] match;
begin
timeout = 10'h3ff;
match <= magic_number(address / 4);
read_addr <= address;
read_strobe <= 1;
#`CLK;
while (read_stall) begin
#`CLK;
timeout = timeout - 1;
if (timeout == 0) begin
$fatal(1, "FAIL: Timed out");
end
end
$display("Read addr %x, data %x", read_addr, read_data);
if (read_fault) begin
$fatal(1, "FAIL: Unexpected fault %x", read_fault);
end
if (read_data != match) begin
$fatal(1, "FAIL: Read %x != %x, addr %x", read_data, match, address);
end
read_strobe <= 0;
end
endtask // wait_and_test_for_instr
endmodule
| 7.326089 |
module tb_je_ip;
reg [7:0] spram[131071:0];
reg pclk, reset_n, pixel_wr_disable, img_req;
integer file_in, r, file_out;
wire mem_wr;
wire [ 7:0] mem_dataw;
wire [16:0] mem_addrw;
wire [16:0] mem_addrr;
reg [ 7:0] mem_datar;
wire img_rdy;
reg [ 2:0] spi_rd_cnt;
wire esp32_spi_rd = (&spi_rd_cnt);
wire [ 7:0] esp32_spi_data;
reg [15:0] eoi_check_reg;
reg [31:0] jpeg_size;
reg [31:0] jpeg_data_cnt;
parameter EOI_MARK = 16'hFFD9;
initial begin
pclk = 0;
reset_n = 0;
img_req = 0;
pixel_wr_disable = 0;
file_in = $fopen("default_320x200.yuyv", "rb");
if (!file_in) begin
$display("Could not open output file");
$finish;
end
r = $fread(spram, file_in);
$fclose(file_in);
file_out = $fopen("default_320x200.jpg", "wb");
if (!file_out) begin
$display("Could not open output file");
$finish;
end
#100 reset_n = 1;
#100 img_req = 1;
#100 pixel_wr_disable = 1;
end
always @(*) #5 pclk <= !pclk;
always @(posedge pclk) begin
if (mem_wr) begin
spram[mem_addrw] <= #1 mem_dataw;
mem_datar <= #1 mem_datar;
end else begin
mem_datar <= #1 spram[mem_addrr];
end
end
je_ip #(
.WIDTH (320),
.HEIGHT(200)
) dut (
.clk (pclk),
.reset_n (reset_n),
.conv_start (img_req && pixel_wr_disable),
.conv_end (img_rdy),
.data_out (esp32_spi_data),
.data_rd (esp32_spi_rd),
.mem_write_en (mem_wr),
.mem_write_data(mem_dataw),
.mem_write_addr(mem_addrw),
.mem_read_data (mem_datar),
.mem_read_addr (mem_addrr)
);
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) spi_rd_cnt <= #1 3'h0;
else if (img_rdy) spi_rd_cnt <= #1 spi_rd_cnt + 3'h1;
else spi_rd_cnt <= #1 3'h0;
end
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) eoi_check_reg <= #1 16'h0000;
else if (esp32_spi_rd && (jpeg_data_cnt > 32'h3))
eoi_check_reg <= #1{eoi_check_reg[7:0], esp32_spi_data};
end
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) jpeg_data_cnt <= #1 32'h00000000;
else if (esp32_spi_rd) jpeg_data_cnt <= #1 jpeg_data_cnt + 32'h00000001;
else jpeg_data_cnt <= #1 jpeg_data_cnt;
end
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) jpeg_size <= #1 32'h00000000;
else if (esp32_spi_rd && (jpeg_data_cnt < 32'h4))
jpeg_size <= #1{jpeg_size[23:0], esp32_spi_data};
else jpeg_size <= #1 jpeg_size;
end
always @(posedge pclk) begin
if (esp32_spi_rd && (jpeg_data_cnt > 32'h3)) $fwriteb(file_out, "%c", esp32_spi_data);
end
always @(posedge pclk) begin
if (eoi_check_reg == EOI_MARK) begin
$fclose(file_out);
$display("Conversion Done");
$finish;
end
end
endmodule
| 6.584107 |
module tb_jkff_nand ();
reg clk;
reg J;
reg K;
wire Q;
wire QBar;
jk_ff_behavioural ff (
.clk(clk),
.J(J),
.K(K),
.Q(Q),
.QBar(QBar)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
#10;
J = 1'b0;
K = 1'b0;
#10;
J = 1'b1;
K = 1'b0;
#10;
J = 1'b0;
K = 1'b1;
#10;
J = 1'b1;
K = 1'b1;
#10;
J = 1'b1;
K = 1'b1;
#10;
J = 1'b1;
K = 1'b0;
#10;
J = 1'b0;
K = 1'b1;
#10;
J = 1'b1;
K = 1'b1;
#10 $finish;
end
endmodule
| 6.516483 |
module testbench;
reg J, K, clk;
wire Q, Qn;
JK_FF JK_FF_1 (
J,
K,
clk,
Q,
Qn
);
initial begin
clk <= 1'b1;
J <= 1'b0;
K <= 1'b1;
#30 J <= 1'b1;
#30 K <= 1'b0;
#30 J <= 1'b0;
end
always begin
#10 clk = ~clk;
end
endmodule
| 7.015571 |
module tb_jump ();
reg Rst;
reg Clk;
reg [5:0] cond;
reg [7:0] DataOut_Bus;
reg [2:0] band;
wire [7:0] Addres_Instruction_Bus;
jump uut (
.Rst(Rst),
.Clk(Clk),
.cond(cond),
.DataOut_Bus(DataOut_Bus),
.band(band),
.Addres_Instruction_Bus(Addres_Instruction_Bus)
);
initial begin
band = 3'b001;
DataOut_Bus = 8'b00000011;
cond = 4'b1010;
Clk = 0;
Rst = 1;
Rst = 0;
#2 band = 3'b100;
cond = 4'b1011;
DataOut_Bus = 8'b00001011;
#2 band = 3'b010;
cond = 4'b1011;
DataOut_Bus = 8'b00100011;
end
always #1 Clk = !Clk;
endmodule
| 7.221413 |
module test;
wire clk;
wire reset_p;
wire reset = ~reset_p;
reg stop;
clock clock (
clk,
reset_p
);
pdp10 pdp10 (
.clk (clk),
.reset(reset)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
stop = 0;
#100000 stop = 1;
$finish;
end
initial begin
pdp10.key_stop_sw = 0;
pdp10.key_exa_sw = 0;
pdp10.key_ex_nxt_sw = 0;
pdp10.key_dep_sw = 0;
pdp10.key_dep_nxt_sw = 0;
pdp10.key_reset_sw = 0;
pdp10.key_exe_sw = 0;
pdp10.key_sta_sw = 0;
pdp10.key_rdi_sw = 0;
pdp10.key_cont_sw = 0;
pdp10.key_sing_inst = 0;
pdp10.key_sing_cycle = 0;
pdp10.key_adr_inst = 0;
pdp10.key_adr_rd = 0;
pdp10.key_adr_wr = 0;
pdp10.key_adr_stop = 0;
pdp10.key_adr_brk = 0;
pdp10.key_par_stop = 0;
pdp10.key_nxm_stop = 0;
pdp10.key_repeat_sw = 0;
pdp10.ds = 0;
pdp10.as = 0;
pdp10.sc_stop_sw = 0;
pdp10.fm_enable_sw = 1;
pdp10.key_repeat_bypass_sw = 0;
pdp10.mi_prog_dis_sw = 0;
pdp10.rdi_sel = 'o104 >> 2;
pdp10.sw_power = 0;
#20 pdp10.sw_power = 1;
end
function [0:35] Inst;
input [0:8] op;
input [9:12] ac;
input i;
input [14:17] x;
input [18:35] y;
begin
Inst = {op, ac, i, x, y};
end
endfunction
function [0:35] IoInst;
input [10:12] op;
input [3:11] dev;
input i;
input [14:17] x;
input [18:35] y;
begin
IoInst = {3'o7, dev[3:9], op, i, x, y};
end
endfunction
//`include "diag_ka10.inc"
`include "test_ka10.inc"
//`include "test_ka10_arith.inc"
//`include "test_ka10_fp.inc"
//`include "test_ka10_dpy.inc"
initial begin
pdp10.ka10.ma = 3;
pdp10.ka10.ar = 1234;
pdp10.ka10.pc = 22;
// pdp10.as = 3;
pdp10.as = 'o20;
// pdp10.as = 100000;
pdp10.ds = 36'o201040001234;
// pdp10.ds = 36'o777777777777;
// pdp10.key_repeat_sw = 1;
// pdp10.key_adr_stop = 1;
#1000 `TESTKEY = 1;
// pdp10.ka10.pi_act = 1;
// pdp10.ka10.pir = 7'b0000010;
// pdp10.ka10.pio = 7'b1111111;
// pdp10.ka10.cpa_clk_en = 1;
// pdp10.ka10.cpa_clk_flag = 1;
// pdp10.ka10.cpa_pia = 1;
// pdp10.ka10.ar_ov_flag = 1;
// pdp10.ka10.ar_cry0_flag = 1;
// pdp10.ka10.ar_cry1_flag = 1;
// pdp10.ka10.ar_fov = 1;
#1200 `TESTKEY = 0;
end
// IR decode test
/* initial begin: irtest
integer i;
#10000;
pdp10.ka10.ar = 0;
pdp10.ka10.ir = 0;
for(i = 0; i < 'o700; i = i+1)
#10 pdp10.ka10.ir[0:8] = i;
for(i = 'o700000; i <= 'o700340; i = i + 'o40)
#10 pdp10.ka10.ir = i;
#10;
end
*/
/*
reg [0:35] rimdata[0:1000];
initial begin: rimtest
integer i;
i <= 0;
pdp10.iobus_rdi_data <= 0;
rimdata[0] <= 36'o777776001000;
rimdata[1] <= 36'o123321456654;
rimdata[2] <= 36'o254200000123;
#100;
@(posedge pdp10.iobus_rdi_pulse);
while(1) begin
#2000;
pdp10.iobus_rdi_data <= 1;
@(posedge pdp10.iobus_iob_fm_datai);
pdp10.iob_test <= rimdata[i];
@(negedge pdp10.iobus_iob_fm_datai);
pdp10.iobus_rdi_data <= 0;
pdp10.iob_test <= 0;
i <= i + 1;
end
end
*/
reg [7:0] holes[0:100];
initial begin : rimtest
integer i;
for (i = 0; i < 100; i = i + 1) holes[i] <= 0;
holes[0] <= 8'hbf;
holes[1] <= 8'hbf;
holes[2] <= 8'hbe;
holes[3] <= 8'h80;
holes[4] <= 8'h88;
holes[5] <= 8'h80;
holes[6] <= 8'h8a;
holes[7] <= 8'h9a;
holes[8] <= 8'h91;
holes[9] <= 8'ha5;
holes[10] <= 8'hb6;
holes[11] <= 8'hac;
holes[12] <= 8'h95;
holes[13] <= 8'ha2;
holes[14] <= 8'h80;
holes[15] <= 8'h80;
holes[16] <= 8'h81;
holes[17] <= 8'h93;
i <= 0;
while (1) begin
@(posedge pdp10.ptr_req);
@(posedge clk);
pdp10.ptr_writedata <= holes[i];
pdp10.ptr_write <= 1;
i <= i + 1;
@(posedge clk);
pdp10.ptr_write <= 0;
@(posedge clk);
@(posedge clk);
end
end
endmodule
| 6.964054 |
module tb_16bit ();
reg [15:0] a;
reg [15:0] b;
wire [30:0] y;
KA_16bit dut (
a,
b,
y
);
initial begin
#5;
a = 16'b1010101110101011;
b = 16'b1101111011011110;
#10;
end
endmodule
| 6.641143 |
module tb_keyexp ();
reg clk;
reg rst_n;
reg [127:0] key_in;
reg start_in;
reg en_de;
reg [3:0] round_in;
// internal wires
wire [127:0] key_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("AC");
$dumpfile(DUMP_FILE);
$shm_open("tb.shm");
$shm_probe("AC");
end
initial begin
start_in = 0;
en_de = 1;
clk = 0;
rst_n = 1;
forever #5 clk = ~clk;
end
initial begin
#5 rst_n = 0;
#5 rst_n = 1;
#5 key_in = 128'h2b28ab09_7eaef7cf_15d2154f_16a6883c;
#10 round_in = 1;
#10 start_in = 1;
#10 start_in = 0;
#1000 $finish;
end
top_keyexp overall_ke (
.clk(clk),
.rst_n(rst_n),
.key_in(key_in),
.start_in(start_in),
.en_de(en_de),
.round_in(round_in),
.key_out(key_out),
.ready_out(ready_out)
);
endmodule
| 6.804416 |
module tb_keypad;
/* naming rule: key_row_column_name */
reg key_0_0_1 = 0, key_0_1_2 = 0, key_0_2_3 = 0, key_0_3_A = 0;
reg key_1_0_4 = 0, key_1_1_5 = 0, key_1_2_6 = 0, key_1_3_B = 0;
reg key_2_0_7 = 0, key_2_1_8 = 0, key_2_2_9 = 0, key_2_3_C = 0;
reg key_3_0_0 = 0, key_3_1_F = 0, key_3_2_E = 0, key_3_3_D = 0;
reg clk = 0;
reg row_0, row_1, row_2, row_3;
wire col_0, col_1, col_2, col_3;
wire keydown_start, keydown_confirm, keydown_clear, keydown_num;
wire [3:0] num;
keypad tb_keypad__keypad (
.clk(clk),
.row_1(row_0),
.row_2(row_1),
.row_3(row_2),
.row_4(row_3),
.col_1(col_0),
.col_2(col_1),
.col_3(col_2),
.col_4(col_3),
.keydown_start(keydown_start),
.keydown_clear(keydown_clear),
.keydown_confirm(keydown_confirm),
.keydown_num(keydown_num),
.num(num)
);
always @(col_0, col_1, col_2, col_3) begin
if (!col_0) begin
row_0 = !key_0_0_1;
row_1 = !key_1_0_4;
row_2 = !key_2_0_7;
row_3 = !key_3_0_0;
end else if (!col_1) begin
row_0 = !key_0_1_2;
row_1 = !key_1_1_5;
row_2 = !key_2_1_8;
row_3 = !key_3_1_F;
end else if (!col_2) begin
row_0 = !key_0_2_3;
row_1 = !key_1_2_6;
row_2 = !key_2_2_9;
row_3 = !key_3_2_E;
end else begin
row_0 = !key_0_3_A;
row_1 = !key_1_3_B;
row_2 = !key_2_3_C;
row_3 = !key_3_3_D;
end
end
initial begin
forever #50 clk = !clk;
end
initial begin
// click key '6'
#120 key_1_2_6 = 1;
#1000 key_1_2_6 = 0;
// click key '8', with bouncing
#500 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1000 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
#1 key_2_1_8 = 1;
#1 key_2_1_8 = 0;
// long press key 'F' (start)
#500 key_3_1_F = 1;
#5000 key_3_1_F = 0;
end
endmodule
| 6.575387 |
module tb_key_control ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19 ,
CNT_11MS = 21'd69 ,
CNT_41MS = 22'd149 ,
CNT_51MS = 22'd199 ,
CNT_60MS = 22'd249 ;
//wire define
wire [ 3:0] wave_select;
//reg define
reg sys_clk;
reg sys_rst_n;
reg [21:0] tb_cnt;
reg key_in;
reg [ 1:0] cnt_key;
reg [ 3:0] key;
//defparam define
defparam key_control_inst.CNT_MAX = 24;
//**************************************************************//
//************************** Main Code *************************//
//**************************************************************//
//sys_rst_n,sys_clk,key
initial begin
sys_rst_n = 1'b0;
sys_clk = 1'b0;
key = 4'b0000;
#200;
sys_rst_n = 1'b1;
end
always #10 sys_clk = ~sys_clk;
//tb_cnt:按键过程计数器，通过该计数器的计数时间来模拟按键的抖动过程
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) tb_cnt <= 22'b0;
else if (tb_cnt == CNT_60MS) tb_cnt <= 22'b0;
else tb_cnt <= tb_cnt + 1'b1;
//key_in:产生输入随机数，模拟按键的输入情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key_in <= 1'b1;
else if((tb_cnt >= CNT_1MS && tb_cnt <= CNT_11MS)
|| (tb_cnt >= CNT_41MS && tb_cnt <= CNT_51MS))
key_in <= {$random} % 2;
else if (tb_cnt >= CNT_11MS && tb_cnt <= CNT_41MS) key_in <= 1'b0;
else key_in <= 1'b1;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_key <= 2'd0;
else if (tb_cnt == CNT_60MS) cnt_key <= cnt_key + 1'b1;
else cnt_key <= cnt_key;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key <= 4'b1111;
else
case (cnt_key)
0: key <= {3'b111, key_in};
1: key <= {2'b11, key_in, 1'b1};
2: key <= {1'b1, key_in, 2'b11};
3: key <= {key_in, 3'b111};
default: key <= 4'b1111;
endcase
//**************************************************************//
//************************ Instantiation ***********************//
//**************************************************************//
//------------- key_control_inst -------------
key_control key_control_inst (
.sys_clk (sys_clk), //系统时钟,50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (key), //输入4位按键
.wave_select(wave_select) //输出波形选择
);
endmodule
| 9.169656 |
module tb_key_control ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19 ,
CNT_11MS = 21'd69 ,
CNT_41MS = 22'd149 ,
CNT_51MS = 22'd199 ,
CNT_60MS = 22'd249 ;
//wire define
wire [ 3:0] wave_select;
//reg define
reg sys_clk;
reg sys_rst_n;
reg [21:0] tb_cnt;
reg key_in;
reg [ 1:0] cnt_key;
reg [ 3:0] key;
//defparam define
defparam key_control_inst.CNT_MAX = 24;
//**************************************************************//
//************************** Main Code *************************//
//**************************************************************//
//sys_rst_n,sys_clk,key
initial begin
sys_rst_n = 1'b0;
sys_clk = 1'b0;
key = 4'b0000;
#200;
sys_rst_n = 1'b1;
end
always #10 sys_clk = ~sys_clk;
//tb_cnt:按键过程计数器，通过该计数器的计数时间来模拟按键的抖动过程
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) tb_cnt <= 22'b0;
else if (tb_cnt == CNT_60MS) tb_cnt <= 22'b0;
else tb_cnt <= tb_cnt + 1'b1;
//key_in:产生输入随机数，模拟按键的输入情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key_in <= 1'b1;
else if((tb_cnt >= CNT_1MS && tb_cnt <= CNT_11MS)
|| (tb_cnt >= CNT_41MS && tb_cnt <= CNT_51MS))
key_in <= {$random} % 2;
else if (tb_cnt >= CNT_11MS && tb_cnt <= CNT_41MS) key_in <= 1'b0;
else key_in <= 1'b1;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_key <= 2'd0;
else if (tb_cnt == CNT_60MS) cnt_key <= cnt_key + 1'b1;
else cnt_key <= cnt_key;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key <= 4'b1111;
else
case (cnt_key)
0: key <= {3'b111, key_in};
1: key <= {2'b11, key_in, 1'b1};
2: key <= {1'b1, key_in, 2'b11};
3: key <= {key_in, 3'b111};
default: key <= 4'b1111;
endcase
//**************************************************************//
//************************ Instantiation ***********************//
//**************************************************************//
//------------- key_control_inst -------------
key_control key_control_inst (
.sys_clk (sys_clk), //系统时钟,50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (key), //输入4位按键
.wave_select(wave_select) //输出波形选择
);
endmodule
| 9.169656 |
module tb_key_extract #(
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter KEY_LEN = 48 * 2 + 32 * 2 + 16 * 2 + 5,
parameter KEY_OFF = (3 + 3) * 3
) ();
reg clk;
reg rst_n;
reg [PHV_LEN-1:0] phv_in;
reg phv_valid_in;
//signals used to config key extract offset
reg [KEY_OFF-1:0] key_offset_in;
reg key_offset_valid_in;
wire [PHV_LEN-1:0] phv_out;
wire phv_valid_out;
wire [KEY_LEN-1:0] key_out;
wire key_valid_out;
localparam STAGE = 0;
//clk signal
localparam CYCLE = 10;
always begin
#(CYCLE / 2) clk = ~clk;
end
//reset signal
initial begin
clk = 0;
rst_n = 1;
#(10);
rst_n = 0; //reset all the values
#(10);
rst_n = 1;
end
initial begin
#(2 * CYCLE); //after the rst_n, start the test
#(5) //posedge of clk
/*
set up the key extract table
*/
phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
key_offset_in <= {3'd6, 3'd7, 3'd6, 3'd7, 3'd6, 3'd7};
key_offset_valid_in <= 1'b1;
#CYCLE phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
key_offset_in <= 18'b0;
key_offset_valid_in <= 1'b0;
#(2 * CYCLE)
/*
switch the value in container 7 and 6
*/
phv_in <= {
48'hffffffffffff,
48'heeeeeeeeeeee,
288'h0,
32'hcccccccc,
32'hbbbbbbbb,
192'b0,
16'hffff,
16'heeee,
96'h0,
356'b0
};
phv_valid_in <= 1'b1;
key_offset_in <= {3'd6, 3'd7, 3'd6, 3'd7, 3'd6, 3'd7};
key_offset_valid_in <= 1'b0;
#CYCLE phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
key_offset_in <= 18'b0;
key_offset_valid_in <= 1'b0;
#(2 * CYCLE);
/*
check if comparator works right
*/
phv_in <= {
48'hffffffffffff,
48'heeeeeeeeeeee,
288'h0,
32'hcccccccc,
32'hbbbbbbbb,
192'b0,
16'hffff,
16'heeee,
96'h0,
2'b0,
4'b0,
2'b10,
3'd7,
4'b0,
2'b10,
3'd6,
80'b0,
256'b0
};
phv_valid_in <= 1'b1;
key_offset_in <= {3'd6, 3'd7, 3'd6, 3'd7, 3'd6, 3'd7};
key_offset_valid_in <= 1'b0;
#CYCLE phv_in <= 1124'b0;
phv_valid_in <= 1'b0;
key_offset_in <= 18'b0;
key_offset_valid_in <= 1'b0;
#(2 * CYCLE);
end
key_extract #(
.STAGE (STAGE),
.PHV_LEN(),
.KEY_LEN(),
.KEY_OFF()
) key_extract (
.clk(clk),
.rst_n(rst_n),
.phv_in(phv_in),
.phv_valid_in(phv_valid_in),
//signals used to config key extract offset
.key_offset_in(key_offset_in),
.key_offset_valid_in(key_offset_valid_in),
.phv_out(phv_out),
.phv_valid_out(phv_valid_out),
.key_out(key_out),
.key_valid_out(key_valid_out)
);
endmodule
| 8.267745 |
module tb_key_filter ();
reg clk;
reg rst_n;
reg key_in;
wire key_out;
key_filter #(
.SYS_CLK(500), // 500 Hz
.FILTER_TIME(20) // 20 ms
) component (
.clk(clk),
.rst_n(rst_n),
.key_in(key_in),
.key_out(key_out)
);
initial begin
clk = 1'b1;
rst_n = 1'b0;
#15 rst_n = 1'b1;
#2 key_in = 1'b0;
#4 key_in = 1'b1;
#4 key_in = 1'b0;
#40 key_in = 1'b1;
#5 key_in = 1'b0;
#4 key_in = 1'b1;
#5 key_in = 1'b0;
#50 key_in = 1'b1;
#3 key_in = 1'b0;
#4 key_in = 1'b1;
#5 key_in = 1'b0;
#25 key_in = 1'b1;
#10 $finish;
end
always #1 clk = ~clk;
initial begin
$dumpfile("tb_key_filter.vcd");
$dumpvars(0, component);
end
endmodule
| 6.827627 |
module tb_key_schedule ();
reg clk;
reg signal_start;
reg [127:0] key;
wire [127:0] outKey;
wire [3:0] state;
wire finished;
key_schedule key_schedule (
.clk(clk),
.signal_start(signal_start),
.finished(finished),
.key(key),
.outKey(outKey),
.state_response(state)
);
//key_schedule_decrypt key_schedule(.clk(clk), .signal_start(signal_start), .finished(finished), .key(key), .outKey(outKey), .state_response(state));
initial begin
clk <= 0;
signal_start <= 0;
//key <= 128'h1111111111111119bababababababab2;
key <= 128'habababababababababababababababab;
#10 signal_start <= 1;
#10 signal_start <= 0;
#200 $stop;
end
initial begin
forever #5 clk = ~clk;
end
endmodule
| 7.52862 |
module tb_key_test;
//declare input to DUT
reg clk_tb;
reg sys_rst_n_tb;
reg key_in_tb;
//declare output of DUT
wire key_en_tb;
//instancing the DUT
key_test u1 (
.clk(clk_tb),
.sys_rst_n(sys_rst_n_tb),
.key_in(key_in_tb),
.key_en(key_en_tb)
);
//creat 1KHz clock
initial clk_tb = 1'b0;
always begin
#0.5 clk_tb = ~clk_tb;
#0.5 clk_tb = ~clk_tb;
end
//key_in
initial key_in_tb = 1'b0;
always begin
#100 key_in_tb = 1'b1;
#15 key_in_tb = 1'b0;
#50 key_in_tb = 1'b1;
#5 key_in_tb = 1'b0;
#50 key_in_tb = 1'b1;
#8 key_in_tb = 1'b0;
#15 key_in_tb = 1'b1;
#10 key_in_tb = 1'b0;
end
//key_rst_n
initial sys_rst_n_tb = 1'b1;
//key_
endmodule
| 6.945219 |
module tb_kogge;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] y;
wire cout;
wire [8:0] sum;
kogge_adder_8bit ksa (
.a(a),
.b(b),
.cin(cin),
.y(y),
.cout(cout),
.sum(sum)
);
initial begin
a = 8'b00001000;
b = 8'b00011011;
cin = 1'b0;
#100 a = 8'b00011000;
b = 8'b00101011;
cin = 1'b1;
#100 a = 8'b001011000;
b = 8'b01011011;
cin = 1'b0;
#100 a = 8'b01001000;
b = 8'b11011011;
cin = 1'b1;
#100 $stop;
end
endmodule
| 7.008121 |
module tb_L1_spi_master;
reg clk;
reg rst_n;
reg im_work_en;
reg [7:0] im_data;
wire [7:0] om_data;
reg im_MISO_spi;
wire om_MOSI_spi;
wire om_SCLK_spi;
wire om_send_finish;
wire om_receive_finish;
L1_spi_master_v2 #(
.MODE(2'b00)
) tb_U1 (
.clk(clk),
.rst_n(rst_n),
.im_work_en(im_work_en),
.im_data(im_data),
.om_data(om_data),
.im_MISO_spi(im_MISO_spi),
.om_MOSI_spi(om_MOSI_spi),
.om_SCLK_spi(om_SCLK_spi),
.om_send_finish(om_send_finish),
.om_receive_finish(om_receive_finish)
);
initial begin
clk = 0;
rst_n = 0;
im_work_en = 0;
im_data = 0;
im_MISO_spi = 1;
end
always #1 clk = ~clk;
initial begin
#1 im_data <= 8'd100;
#4 rst_n = 1;
#12 im_work_en = 1;
#150 $stop();
end
endmodule
| 7.742308 |
module tb_L2_clk_read_cnt;
reg clk;
reg rst_n;
reg im_SCLK_spi;
wire om_up_edge;
wire om_down_edge;
wire om_high_read;
wire om_low_read;
L2_clk_read_cnt tb_U1 (
.clk (clk),
.rst_n(rst_n),
.im_SCLK_spi(im_SCLK_spi),
.om_up_edge (om_up_edge),
.om_down_edge(om_down_edge),
.om_high_read(om_high_read),
.om_low_read (om_low_read)
);
initial begin
clk = 0;
rst_n = 0;
im_SCLK_spi = 0;
end
always #1 clk = ~clk;
always #20 im_SCLK_spi = ~im_SCLK_spi;
initial begin
#10 rst_n = 1'b1;
#1000 $stop();
end
endmodule
| 7.205289 |
module: LampState
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lamp_state;
// Inputs
reg [3:0] active_lights;
// Outputs
wire [15:0] lights_state;
// Instantiate the Unit Under Test (UUT)
LampState uut (
.active_lights(active_lights),
.lights_state(lights_state)
);
initial begin
// Initialize Inputs
active_lights = 0;
// Wait 100 ns for global reset to finish
#100;
active_lights = 4'b0010;
#100;
active_lights = 4'b0010;
#100;
active_lights = 4'b1010;
#100;
active_lights = 4'b1110;
#100;
active_lights = 4'b0011;
#100;
active_lights = 4'b1111;
#100
$finish;
// Add stimulus here
end
endmodule
| 7.417602 |
module tb_lane_assist;
reg CLK, RST, assist_right, assist_left, assist_disable;
wire [2:0] lane;
lane_assist DUT (
.CLK(CLK),
.RST(RST),
.assist_right(assist_right),
.assist_left(assist_left),
.assist_disable(assist_disable),
.lane(lane)
);
initial begin
CLK = 1'b0;
RST = 1'b1;
assist_right = 1'b0;
assist_left = 1'b0;
assist_disable = 1'b0; // Car is driving perfectly in lane.
#10 CLK = 1'b1;
RST = 1'b0;
assist_right = 1'b1; // Car too close to right side of lane.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
#10 CLK = 1'b0;
#10 CLK = 1'b1;
assist_right = 1'b0; // Car back in the center of lane.
#10 CLK = 1'b0;
RST = 1'b1;
#10 CLK = 1'b1;
RST = 1'b0;
assist_left = 1'b1; // Car too close to left side of lane.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
#10 CLK = 1'b0;
#10 CLK = 1'b1;
assist_left = 1'b0; // Car back in the center of lane.
#10 CLK = 1'b0;
RST = 1'b1;
#10 CLK = 1'b1;
RST = 1'b0;
assist_disable = 1'b1; // Turn off lane assist feature.
#10 CLK = 1'b0;
#10 CLK = 1'b1;
#10 CLK = 1'b0;
#5 $finish;
end
endmodule
| 6.837297 |
module tb_latch_N;
// latch_N Parameters
parameter PERIOD = 10;
parameter N = 8;
// latch_N Inputs
reg clk = 0;
reg [N-1:0] d = 0;
// latch_N Outputs
wire [N-1:0] q;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
latch_N #(
.N(N)
) u_latch_N (
.clk(clk),
.d (d[N-1:0]),
.q(q[N-1:0])
);
initial begin
d = 2;
#(PERIOD * 20);
d = 5;
#(PERIOD * 50);
d = 8;
#(PERIOD * 20);
d = 12;
#(PERIOD * 70);
$finish;
end
endmodule
| 6.84923 |
module tb_layer1;
reg clock;
reg reset_n;
reg readdatavalid;
reg [15:0] readdata;
reg waitrequest;
reg ready;
reg cont = 1;
reg [9:0] counter = 0;
reg [15:0] memory[0:131072];
wire [31:0] address;
reg [31:0] rdadr;
reg isread = 0;
reg [7:0] s1_q;
reg [7:0] s2_q;
initial begin
isread <= 0;
clock <= 0;
ready <= 0;
reset_n <= 0;
readdatavalid <= 0;
readdata <= 16'h0001;
waitrequest <= 0;
#20;
reset_n <= 1;
ready <= 1;
s1_q <= 8'h1;
s2_q <= 8'h2;
end
layer2 DUT (
.clk(clock),
.reset_n(reset_n),
.waitrequest(waitrequest),
.readdatavalid(readdatavalid),
.readdata(readdata),
.read_n(read_n),
.write_n(write_n),
.chipselect(chipselect),
.address(address),
.byteenable(byteenable),
.writedata(writedata),
.ready(ready),
.done(done),
.s1_q(s1_q),
.s2_q(s2_q)
);
always begin
#10 clock = ~clock;
if (read_n == 0 && counter > 8) begin
counter = 0;
isread = 1;
end
if ((write_n == 0) && counter > 6) begin
counter = 0;
end
if (counter == 4) begin
waitrequest <= 0;
rdadr <= ~read_n ? address : 0;
end else begin
waitrequest <= 0;
end
if ((counter == 6) && isread == 1) begin
readdatavalid = 1;
//readdata = memory[rdadr] || 0;
end else begin
readdatavalid = 1;
end
if (counter == 8) begin
isread = 0;
end
counter = counter + clock;
readdata <= $random;
//readdata <= 0;
end
endmodule
| 6.927942 |
module: lb_11bitsShiftRegister
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_11bitsShiftRegister;
// Inputs
reg clk;
reg reset;
reg load;
reg shift;
reg [10:0] data_in;
// Outputs
wire data_out;
//local variables
integer i;
// Instantiate the Unit Under Test (UUT)
lb_11bitsShiftRegister uut (
.clk(clk),
.reset(reset),
.load(load),
.shift(shift),
.data_in(data_in),
.data_out(data_out)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
load = 0;
shift = 0;
data_in = 11'b00_11_0_1_0_1_00_1;
#30;
reset = 1;
load = 1;
#10;
load = 0;
#20;
for(i=0; i<11; i=i+1) begin
shift = 1;
#20;
shift = 0;
#40;
end
data_in = 11'b11_00_0_1_0_1_11_0;
load = 1;
#20;
load = 0;
#20;
for(i=0; i<11; i=i+1) begin
shift = 1;
#20;
shift = 0;
#40;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.689198 |
module: lb_16BaudTickCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_16BaudTickCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] prescale;
// Outputs
wire done;
// Instantiate the Unit Under Test (UUT)
lb_16BaudTickCounter uut (
.clk(clk),
.reset(reset),
.prescale(prescale),
.done(done)
);
always
#20 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
prescale = 3;
#10
reset = 1;
// Wait 100 ns for global reset to finish
#400;
// Add stimulus here
end
endmodule
| 6.566402 |
module: lb_16_n_8BaudTickCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_16_n_8BaudTickCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] prescale;
reg _16_or_8_ticks;
reg cs;
reg load;
// Outputs
wire done;
// Instantiate the Unit Under Test (UUT)
lb_16_n_8BaudTickCounter uut (
.clk(clk),
.reset(reset),
.prescale(prescale),
._16_or_8_ticks(_16_or_8_ticks),
.cs(cs),
.load(load),
.done(done)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
prescale = 0;
_16_or_8_ticks = 0;
cs = 0;
load = 1;
#15;
reset = 1;
#300;
_16_or_8_ticks = 1;
load = 0;
#10;
load = 1;
// Wait 100 ns for global reset to finish
#500;
// Add stimulus here
end
endmodule
| 6.584844 |
module: lb_buffer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_buffer;
// Inputs
reg clk;
reg reset;
reg re;
reg [7:0] w_data;
reg we;
// Outputs
wire full;
wire [7:0] r_data;
wire empty;
// Instantiate the Unit Under Test (UUT)
lb_buffer uut (
.clk(clk),
.reset(reset),
.re(re),
.w_data(w_data),
.we(we),
.full(full),
.r_data(r_data),
.empty(empty)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
re = 0;
w_data = 0;
we = 0;
#10;
reset = 1;
#10;
w_data = 8'hA5;
we = 1;
#10;
we = 0;
#30;
re = 1;
#30;
re = 0;
#10;
w_data = 8'hAA;
we = 1;
#10;
we = 0;
#30;
re = 1;
#30
re = 0;
#10;
w_data = 8'hFE;
we = 1;
#30;
re = 1;
#30;
re = 0;
#20;
// Add stimulus here
end
endmodule
| 6.761163 |
module: lb_clockCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_clockCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] value;
// Outputs
wire done;
// Instantiate the Unit Under Test (UUT)
lb_clockCounter uut (
.clk(clk),
.reset(reset),
.value(value),
.done(done)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
value = 200;
#10;
reset = 1;
// Wait 100 ns for global reset to finish
#300;
#10;
reset = 0;
#10;
reset = 1;
// Wait 100 ns for global reset to finish
#300;
// Add stimulus here
end
endmodule
| 6.890798 |
module: lb_contNumBits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_contNumBits;
// Inputs
reg clk;
reg reset;
reg parity_en;
reg bit8;
reg [1:0] value;
reg inc;
reg cs;
// Outputs
wire done;
integer i;
// Instantiate the Unit Under Test (UUT)
lb_contNumBits uut (
.clk(clk),
.reset(reset),
.parity_en(parity_en),
.bit8(bit8),
.inc(inc),
.cs(cs),
.done(done)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
parity_en = 0;
bit8 = 0;
value = 0;
inc =0;
cs = 0;
#20
reset = 0;
#20;
reset = 1;
inc=1;
#10;
for(i=0; i<4; i=i+1) begin
#220;
value = value + 1;
#20
{parity_en,bit8} = value;
#20
reset = 0;
#20;
reset = 1;
#10;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.726019 |
module: lb_debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_debouncer;
// Inputs
reg clk;
reg sw;
reg reset;
// Outputs
wire db;
// Instantiate the Unit Under Test (UUT)
lb_debounce uut (
.clk(clk),
.sw(sw),
.reset(reset),
.db(db)
);
always
#10clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
sw = 0;
reset = 1;
#10;
reset = 0;
#15;
sw = 1;
#250
sw = 0;
// Wait 100 ns for global reset to finish
#100000000;
// Add stimulus here
end
endmodule
| 7.937816 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_FULL_UART_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg oe;
reg adrs;
reg [7:0] data;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
reg rx;
// Outputs
wire tx;
wire [7:0] data_out;
reg [10:0] char;
reg [3:0] i;
// Instantiate the Unit Under Test (UUT)
lb_UART_toplevel uut (
.clk(clk),
.reset(reset),
.cs(cs),
.we(we),
.oe(oe),
.adrs(adrs),
.data(data),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.rx(rx),
.tx(tx),
.data_out(data_out)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
cs = 0;
we = 0;
oe = 0;
adrs = 0;
data = 0;
bit8 = 1;
parity_en = 0;
odd_n_even = 0;
baud_val = 4'b0100;
rx = 1;
char = 11'b1_1_01000001_0; //ASC A
#10;
reset =1;
cs=1;
for(i=0; i<11; i=i+1) begin
rx=char[i];
#104170;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.136444 |
module: lb_pulseMaker
//
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_pulseMaker;
// Inputs
reg clk;
reg signal_in;
reg reset;
// Outputs
wire pulse;
// Instantiate the Unit Under Test (UUT)
lb_pulseMaker uut (
.clk(clk),
.signal_in(signal_in),
.reset(reset),
.pulse(pulse)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
signal_in = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#10;
reset = 1;
#100;
signal_in = 1;
#20;
signal_in = 0;
#100;
signal_in = 1;
#40;
signal_in = 0;
#100;
signal_in = 1;
#60;
signal_in = 0;
#100
$finish;
// Add stimulus here
end
endmodule
| 7.225992 |
module: lb_shiftreg_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_shiftreg_rx;
// Inputs
reg clk;
reg reset;
reg data_in;
reg shift;
// Outputs
wire [10:0] data_out;
reg [5:0] i;
// Instantiate the Unit Under Test (UUT)
lb_shiftreg_rx uut (
.clk(clk),
.reset(reset),
.data_in(data_in),
.shift(shift),
.data_out(data_out)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
data_in = 0;
shift = 0;
#15;
reset = 1;
for(i=0; i<10; i=i+1) begin
data_in = i[0];
shift = 1;
#10;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.757516 |
module: soc_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_soc_block;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
// Outputs
wire tx;
wire interrupt_ack;
//internal
reg [10:0] char;
reg [3:0] i;
// Instantiate the Unit Under Test (UUT)
soc_block uut (
.clk(clk),
.reset(reset),
.tx(tx),
.rx(rx),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
rx = 0;
interrupt = 0;
bit8 = 1;
parity_en = 0;
odd_n_even = 0;
baud_val = 4'b0100;
char = 11'b1_1_01000001_0; //ASC A
#10;
reset =0;
for(i=0; i<11; i=i+1) begin
rx=char[i];
#104110;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.636792 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_full_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg oe;
reg adrs;
reg [7:0] data;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
reg rx;
// Outputs
wire tx;
wire [7:0] data_out;
reg [10:0] shifter;
reg [4:0] j;
reg [7:0] i;
// Instantiate the Unit Under Test (UUT)
lb_UART_toplevel uut (
.clk(clk),
.reset(reset),
.cs(cs),
.we(we),
.oe(oe),
.adrs(adrs),
.data(data),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.rx(rx),
.tx(tx),
.data_out(data_out)
);
always
#5 clk = ~clk; //clock 10ns = 100MHz
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
cs = 0;
we = 0;
oe = 0;
adrs = 1;
data = 0;
bit8 = 1;
parity_en = 0;
odd_n_even = 1;
baud_val = 4;
rx = 1;
#10;
reset = 1;
#10;
for(i=65; i<96; i=i+1) begin
shifter = {2'b11,i,1'b0};
for(j=0; j<10; j=j+1) begin
rx=shifter[j];
#104170;
end
#500;
adrs = 1; //watch data
#100;
adrs = 1;
#10;
oe = 1;
#10;
oe = 0;
end
end
endmodule
| 8.136444 |
module: lb_UART_Rx_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Receive_fsm;
// Inputs
reg clk;
reg reset;
reg bit8;
reg parity_en;
reg [19:0] baudPrescale;
reg cs;
reg rx;
// Outputs
wire done;
wire shift;
// Instantiate the Unit Under Test (UUT)
lb_UART_Rx_ControlUnit uut (
.clk(clk),
.reset(reset),
.bit8(bit8),
.parity_en(parity_en),
.baudPrescale(baudPrescale),
.cs(cs),
.rx(rx),
.done(done),
.shift(shift)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
bit8 = 1;
parity_en = 1;
baudPrescale = 0;
cs = 0;
rx = 1;
#15;
reset = 1;
#30;
rx = 0;
#380;
rx = 1;
// Wait 100 ns for global reset to finish
#10000;
// Add stimulus here
end
endmodule
| 7.600689 |
module: lb_UART_Rx_Core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Rx_Core;
// Inputs
reg clk;
reg reset;
reg [19:0] baud_value;
reg bit8;
reg parity_en;
reg odd_n_even;
reg cs;
reg rx;
// Outputs
wire [7:0] data_out;
wire done;
wire parity_err;
wire stopErr;
// Instantiate the Unit Under Test (UUT)
lb_UART_Rx_Core uut (
.clk(clk),
.reset(reset),
.baud_value(baud_value),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.cs(cs),
.rx(rx),
.data_out(data_out),
.done(done),
.parity_err(parity_err),
.stopErr(stopErr)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
baud_value = 0;
bit8 = 1;
parity_en = 1;
odd_n_even = 1;
cs = 1;
rx = 1;
#20;
reset =1;
#20;
rx=0;
#380;
rx=1;
// Wait 100 ns for global reset to finish
#100000;
// Add stimulus here
end
endmodule
| 7.600689 |
module: lb_UART_Rx_fsm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Rx_fsm;
// Inputs
reg clk;
reg reset;
reg baudTickCounterDone;
reg bitCounterDone;
reg rx;
// Outputs
wire done;
wire shift;
wire half_n_complete;
wire incNumBits;
wire resetBaudTickCounter;
wire resetNumBitsCounter;
// Instantiate the Unit Under Test (UUT)
lb_UART_Rx_fsm uut (
.clk(clk),
.reset(reset),
.baudTickCounterDone(baudTickCounterDone),
.bitCounterDone(bitCounterDone),
.rx(rx),
.done(done),
.shift(shift),
.half_n_complete(half_n_complete),
.incNumBits(incNumBits),
.resetBaudTickCounter(resetBaudTickCounter),
.resetNumBitsCounter(resetNumBitsCounter)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
baudTickCounterDone = 0;
bitCounterDone = 0;
rx = 0;
#15;
reset = 1;
#60;
// Wait 100 ns for global reset to finish
#100000;
// Add stimulus here
end
endmodule
| 7.16557 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg [7:0] data;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
// Outputs
wire txrdy;
wire tx;
// Instantiate the Unit Under Test (UUT)
lb_UART_toplevel uut (
.clk(clk),
.reset(reset),
.cs(cs),
.we(we),
.data(data),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.txrdy(txrdy),
.tx(tx)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
cs = 1;
we = 0;
data = 8'hA5;
bit8 = 1;
parity_en = 1;
odd_n_even = 1;
baud_val = 4'b0000;
#15
cs = 0;
#15;
reset = 1;
#15;
we = 1;
#35;
we = 0;
// Wait 100 ns for global reset to finish
#5000;
end
endmodule
| 8.136444 |
module: lb_UART_Tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg [7:0] data;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [19:0] baud_val;
// Outputs
wire txrdy;
wire tx;
integer i;
reg flag;
// Instantiate the Unit Under Test (UUT)
lb_UART_Tx uut (
.clk(clk),
.reset(reset),
.cs(cs),
.we(we),
.data(data),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.txrdy(txrdy),
.tx(tx)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
cs = 0;
we = 0;
data = 8'hA5;
bit8 = 1;
parity_en = 1;
odd_n_even = 1;
baud_val = 3;
i = 0;
flag = 0;
#15;
reset = 1;
#15;
we = 1;
#15;
we = 0;
// Wait 100 ns for global reset to finish
#5000;
// Add stimulus here
end
endmodule
| 7.609279 |
module: lb_UART_Tx_Core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_core;
// Inputs
reg clk;
reg reset;
reg [7:0] data;
reg start;
reg [19:0] baud_value;
reg bit8;
reg parity_en;
reg odd_n_even;
// Outputs
wire tx;
wire tx_done;
// Instantiate the Unit Under Test (UUT)
lb_UART_Tx_Core uut (
.clk(clk),
.reset(reset),
.data(data),
.start(start),
.baud_value(baud_value),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.tx(tx),
.tx_done(tx_done)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
//data = 0;
start = 0;
baud_value = 3;
bit8 = 0;
parity_en = 1;
odd_n_even = 0;
data = 8'b0110_1010;
#15
reset = 1;
#15
start = 1;
#50
start = 0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
end
endmodule
| 8.892 |
module: lb_UART_Tx_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_CU;
// Inputs
reg clk;
reg reset;
reg start;
reg bit8;
reg parity_en;
reg [19:0] baudPrescale;
// Outputs
wire done;
wire load;
wire shift;
// Instantiate the Unit Under Test (UUT)
lb_UART_Tx_ControlUnit uut (
.clk(clk),
.reset(reset),
.start(start),
.bit8(bit8),
.parity_en(parity_en),
.baudPrescale(baudPrescale),
.done(done),
.load(load),
.shift(shift)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
start = 0;
bit8 = 1;
parity_en = 1;
baudPrescale = 3;
#15
reset = 1;
#15
start = 1;
#15
start = 0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
end
endmodule
| 8.892 |
module: lb_UART_Tx_FSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_FSM;
// Inputs
reg clk;
reg reset;
reg start;
reg baudTickCounterDone;
reg bitCounterDone;
// Outputs
wire done;
wire shift;
wire load;
wire incNumBits;
wire resetBaudTickCounter;
integer i;
// Instantiate the Unit Under Test (UUT)
lb_UART_Tx_FSM uut (
.clk(clk),
.reset(reset),
.start(start),
.baudTickCounterDone(baudTickCounterDone),
.bitCounterDone(bitCounterDone),
.done(done),
.shift(shift),
.load(load),
.incNumBits(incNumBits),
.resetBaudTickCounter(resetBaudTickCounter)
);
always #
5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
start = 0;
baudTickCounterDone = 0;
bitCounterDone = 0;
#30;
reset = 1;
#10;
start = 1;
for(i=0; i<10; i=i+1) begin
#40;
baudTickCounterDone = 1;
if(i==9)
bitCounterDone = 1;
#10;
baudTickCounterDone = 0;
bitCounterDone = 0;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.929707 |
module tb_lcbbc;
parameter N = 8;
parameter MIN_HD = 2;
parameter MEM_DEPTH = 256;
reg clk;
reg rst;
reg [N-1:0] n;
reg start;
reg [N-1:0] min_hd;
wire [N-1:0] codes;
initial begin
clk <= 1'b0;
rst = 1'b1;
end
always #5 clk = ~clk;
initial begin
repeat (10) @(negedge clk);
rst = 1'b0; //disable reset
@(negedge clk);
start = 1;
n = N;
min_hd = MIN_HD;
end
/* lcbbc AUTO_TEMPLATE
(
);
*/
lcbbc #(
.N(N),
.depth(MEM_DEPTH),
.width(N)
) LCBBC_INST ( /*AUTOINST*/
// Outputs
.codes (codes[N-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.n (n[N-1:0]),
.min_hd(min_hd[N-1:0]),
.start (start)
);
/* -----\/----- EXCLUDED -----\/-----
initial
begin
#15000;
$finish;
end
-----/\----- EXCLUDED -----/\----- */
initial begin
$monitor("codeword = %b\t ", codes);
end
endmodule
| 6.851514 |
module tb_LCD_controller;
// Inputs
reg clk;
reg reset;
// Outputs
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [3:0] SF_D;
// Instantiate the Unit Under Test (UUT)
LCDcontroller LCDcontroller_inst (
.clk(clk),
.reset(reset),
.LCD_E(LCD_E),
.LCD_RS(LCD_RS),
.LCD_RW(LCD_RW),
.SF_D(SF_D)
);
initial begin
clk = 1;
reset = 0;
#100 reset = 1;
#100 reset = 0;
#100000000 reset = 1;
#100000 reset = 0;
#100000000 reset = 1;
#100000 reset = 0;
#100000000 reset = 1;
#100000 reset = 0;
end
always #10 clk = ~clk;
endmodule
| 7.290108 |
module tb_LCD_control_unit;
reg clk;
reg reset;
wire LCD_RS;
wire LCD_RW;
wire LCD_EN;
wire [3:0] LCD_SF_D;
LCD_controller_module dut_LCD_controller_inst (
.clk(clk),
.reset(reset),
.LCD_RS(LCD_RS),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_SF_D(LCD_SF_D)
);
localparam CLK_PERIOD = 20;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
clk = 1'b1;
reset = 1'b1;
#200 reset = 1'b0;
end
endmodule
| 7.290108 |
module: lCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lCounter;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
lCounter uut (
.lfsr(lfsr),
.out(out)
);
initial begin
// Initialize Inputs
lfsr = 16'b0000000000000000;
// Wait 100 ns for global reset to finish
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, (hex): %h", lfsr, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule
| 6.651678 |
module tb8;
reg [7:0] seq;
wire [3:0] idx;
leadingZero8 u_lze_8 (
seq,
idx
);
initial begin
#3 seq = 8'h80;
#3 $display("seq %h, idx %d\n", seq, idx);
seq = 8'h01;
#3 $display("seq %h, idx %d\n", seq, idx);
seq = 8'h08;
#3 $display("seq %h, idx %d\n", seq, idx);
seq = 8'h03;
#3 $display("seq %h, idx %d\n", seq, idx);
end
endmodule
| 6.864263 |
module tb_LeakyIntegrator2;
parameter WI = 8;
parameter WF = 32;
reg [(WI+WF-1):0] InLeaky;
reg Clk;
reg LIdvi;
wire [(WI+WF-1):0] OutSmooth;
wire LIdvo;
parameter Clockperiod = 10;
initial Clk = 0;
always #(Clockperiod / 2) Clk = ~Clk;
LeakyIntegrator2 #(
.WI(WI),
.WF(WF)
) UUTLeakyIntegrator2 (
.InLeaky(InLeaky),
.Clk(Clk),
.LIdvi(LIdvi),
.OutSmooth(OutSmooth),
.LIdvo(LIdvo)
);
real Input;
real Output;
function real fixedToFloat;
input [63:0] in;
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx < WI + WF - 1; idx = idx + 1) begin
if (in[idx] == 1'b1) begin
retVal = retVal + (2.0 ** (idx - WF));
end
end
fixedToFloat = retVal - (in[WI+WF-1] * (2.0 ** (WI - 1)));
end
endfunction
parameter data_width = 40;
parameter addr_width = 1008;
reg [(data_width-1):0] rom1[addr_width-1:0];
initial begin
$readmemb("TestingLeakyInt.txt", rom1);
end
integer i1;
initial begin
LIdvi = 0;
InLeaky = 0;
for (i1 = 0; i1 < 1008; i1 = i1 + 1) begin
@(posedge Clk);
LIdvi = 1;
InLeaky = rom1[i1];
end
end
always @(posedge Clk) begin
Input = fixedToFloat(InLeaky, WI, WF);
Output = fixedToFloat(OutSmooth, WI, WF);
$display(Output);
end
endmodule
| 6.531694 |
module tb_leakyrelu_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam NUM = {DATA_WIDTH{1'b1}};
// interface
reg clk;
reg rst_n;
reg [ NUM_INPUT_DATA-1:0] i_valid;
reg [ WIDTH_INPUT_DATA-1:0] i_data_bus;
wire [ NUM_OUTPUT_DATA-1:0] o_valid;
wire [WIDTH_OUTPUT_DATA-1:0] o_data_bus; //{o_data_a, o_data_b}
reg i_en;
initial begin
clk = 1'b0;
rst_n = 1'b1;
i_data_bus = ZERO_POINT;
i_valid = 1'b0;
i_en = 1'b1;
// reset
#10 rst_n = 1'b0;
// input activate below zero (negative)
#10 rst_n = 1'b1;
i_data_bus = {1'b1, {(DATA_WIDTH - 1) {1'b0}}};
i_valid = 1'b1;
// input activate larger than zero
#10
// i_data_bus = {1'b0, {(DATA_WIDTH-1){1'b1}}};
i_data_bus = ZERO_POINT;
i_valid = 1'b1;
#2600 $stop;
end
integer i;
always begin
@(posedge clk)
for (i = 0; i < NUM; i = i + 1) begin
i_data_bus = i_data_bus + 2'sb01;
end
end
always #5 clk = ~clk;
leakyrelu_seq #(
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.rst_n(rst_n),
.i_data_bus(i_data_bus),
.i_valid(i_valid),
.o_data_bus(o_data_bus),
.o_valid(o_valid),
.i_en(i_en)
);
endmodule
| 7.742861 |
module tb_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out;
//reg define
reg key_in;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化输入信号
initial key_in <= 1'b0;
//key_in:产生输入随机数，模拟按键的输入情况
always #10 key_in <= {$random} % 2; /*取模求余数，产生非负随机数0、1
每隔10ns产生一次随机数*/
//********************************************************************//
//**************************** Instantiate ***************************//
//********************************************************************//
//------------- led_inst -------------
led led_inst (
.key_in(key_in), //input key_in
.led_out(led_out) //output led_out
);
endmodule
| 7.421857 |
module tb_leds;
reg clk = 0;
always begin
#5;
clk = ~clk;
end
reg key;
wire w_data;
colors colors_inst (
.clk(clk),
.button(key),
.data(w_data)
);
initial begin
$dumpfile("out.vcd");
$dumpvars(0, tb_leds);
key = 1'b0;
#100;
@(posedge clk);
#0;
key = 1'b1;
#50000;
$finish();
end
endmodule
| 6.792791 |
module: lb_reset
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lf_reset;
// Inputs
reg clk;
reg resetb;
wire system_reset;
// Instantiate the Unit Under Test (UUT)
lb_reset uut (
.clk(clk),
.resetb(resetb),
.system_reset(system_reset)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
resetb = 0;
// Wait 100 ns for global reset to finish
#25;
resetb = 1;
#25;
resetb = 0;
#100;
resetb = 1;
#25;
resetb = 0;
#100;
$finish;
// Add stimulus here
end
endmodule
| 7.707976 |
module tb_lightcube8_top;
reg clk;
reg rst;
//clock generating
real CYCLE_100MHz = 10;
always begin
clk = 0;
#(CYCLE_100MHz / 2);
clk = 1;
#(CYCLE_100MHz / 2);
end
wire resetn;
assign resetn = ~rst;
//reset generating
initial begin
rst = 1'b0;
#8 rst = 1'b1;
#2000 rst = 1'b0;
end
real BAUD_PERIOD = 8680;
real IDLE_PERIOD = 8680 * 10;
real FPS_PERIOD = 8680 * 20;
reg rx;
reg [15:0] switch;
// //FRAME MODE
// initial begin
// rx = 1'b1;
// switch = 16'h000f; //mode: 2'b00, sel: 0xf
// end
// //GEN MODE
// initial begin
// rx = 1'b1;
// switch = 16'h800f; //mode: 2'b10, speed: 0xf
// end
//UART MODE
integer i, j, k;
reg [7:0] data;
initial begin
rx = 1'b1;
switch = 16'b0;
switch[15:14] = 2'b00; //default mode
#3000 switch[15:14] = 2'b11; //uart mode
for (i = 0; i < 10; i = i + 1) begin //10 frames
for (j = 0; j < 64; j = j + 1) begin //64 bytes
data = i[7:0] ^ j[7:0];
rx = 1'b0;
#BAUD_PERIOD;
rx = data[0];
#BAUD_PERIOD;
rx = data[1];
#BAUD_PERIOD;
rx = data[2];
#BAUD_PERIOD;
rx = data[3];
#BAUD_PERIOD;
rx = data[4];
#BAUD_PERIOD;
rx = data[5];
#BAUD_PERIOD;
rx = data[6];
#BAUD_PERIOD;
rx = data[7];
#BAUD_PERIOD;
rx = data[0];
#BAUD_PERIOD;
rx = 1'b1;
#BAUD_PERIOD;
#IDLE_PERIOD;
end
#FPS_PERIOD;
end
end
wire tx;
wire [7:0] high_csn;
wire [7:0] row;
wire [7:0] row_cs;
lightcube8_top #(
.FRAME_GEN_CLK_DIV(14),
.SCAN_CLK_DIV(14)
) lightcube8_top (
.clk(clk),
.resetn(resetn),
.switch(switch),
.rx(rx),
.tx(tx),
.high_csn(high_csn),
.row(row),
.row_cs(row_cs)
);
endmodule
| 7.429878 |
module tb_link_controller();
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter ADDR_PAGE_NUM_LOG = 12;
logic clk;
logic rst_n;
logic [ADDR_PAGE_NUM_LOG - 1:0]data_table_read_addr;
logic [ADDR_PAGE_NUM_LOG - 1:0]data_table_read_last_addr;
logic data_table_empty;
logic data_table_read_req;
logic data_table_write_req;
logic [ADDR_PAGE_NUM_LOG - 1:0]data_table_write_addr;
logic [ADDR_PAGE_NUM_LOG - 1:0]empty_table_read_addr;
logic [ADDR_PAGE_NUM_LOG - 1:0]empty_table_read_last_addr;
logic empty_table_empty;
logic empty_table_read_req;
logic empty_table_write_req;
logic [ADDR_PAGE_NUM_LOG - 1:0]empty_table_write_addr;
logic ram_write_req;
logic [ADDR_WIDTH - 1:0]ram_addr;
logic [DATA_WIDTH - 1:0]ram_write_data;
logic ram_controller_write_req;
logic link_table_read_valid;
logic link_table_write_req;
logic link_table_read_req;
link_controller #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.ADDR_PAGE_NUM_LOG(ADDR_PAGE_NUM_LOG)
) dut (
.clk (clk),
.rst_n (rst_n),
.data_table_read_addr (data_table_read_addr),
.data_table_read_last_addr (data_table_read_last_addr),
.data_table_empty (data_table_empty),
.data_table_read_req (data_table_read_req),
.data_table_write_req (data_table_write_req),
.data_table_write_addr (data_table_write_addr),
.empty_table_read_addr (empty_table_read_addr),
.empty_table_read_last_addr(empty_table_read_last_addr),
.empty_table_empty (empty_table_empty),
.empty_table_read_req (empty_table_read_req),
.empty_table_write_req (empty_table_write_req),
.empty_table_write_addr (empty_table_write_addr),
.ram_write_req (ram_write_req),
.ram_addr (ram_addr),
.ram_write_data (ram_write_data),
.ram_controller_write_req (ram_controller_write_req),
.link_table_read_valid (link_table_read_valid),
.link_table_write_req (link_table_write_req),
.link_table_read_req (link_table_read_req)
);
initial begin
clk = 0;
forever begin
# <clock> clk = ~clk;
end
end
initial begin
rst_n = 1'b1;
#5 rst_n = 1'b0;
#10 rst_n = 1'b1;
end
initial begin
data_table_read_addr = 'b0;
data_table_read_last_addr = 'b0;
data_table_empty = 'b0;
empty_table_read_addr = 'b0;
empty_table_read_last_addr = 'b0;
empty_table_empty = 'b0;
link_table_write_req = 'b0;
link_table_read_req = 'b0;
end
endmodule
| 7.254308 |
module: ll8_to_txmac
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ll8_to_txmac;
// Inputs
reg clk;
reg reset;
reg clear;
reg [7:0] ll_data;
reg ll_sof;
reg ll_eof;
reg ll_src_rdy;
reg tx_ack;
// Outputs
wire ll_dst_rdy;
wire [7:0] tx_data;
wire tx_valid;
wire tx_error;
wire [2:0] debug;
// Instantiate the Unit Under Test (UUT)
ll8_to_txmac uut (
.clk(clk),
.reset(reset),
.clear(clear),
.ll_data(ll_data),
.ll_sof(ll_sof),
.ll_eof(ll_eof),
.ll_src_rdy(ll_src_rdy),
.ll_dst_rdy(ll_dst_rdy),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_error(tx_error),
.tx_ack(tx_ack),
.debug(debug)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
clear = 0;
ll_data = 0;
ll_sof = 0;
ll_eof = 0;
ll_src_rdy = 0;
tx_ack = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(posedge clk);
ll_data = 1;
tx_ack = 1;
ll_src_rdy = 1;
repeat(50) begin
@(posedge clk);
ll_data = ll_data + 1'b1;
tx_ack = 0;
end
@(posedge clk);
ll_eof = 1;
ll_data = ll_data + 1'b1;
@(posedge clk);
ll_eof = 0;
// Add stimulus here
end
always begin
#5;
clk = ~clk;
end
endmodule
| 8.270685 |
module tb_lmmi_mst
#( //--begin_param--
//----------------------------
// Parameters
//----------------------------
parameter AWIDTH = 16,
parameter DWIDTH = 32,
parameter MODEL_NAME = "LMMI_MST",
parameter integer TIMEOUT_VALUE = 512
) //--end_param--
( //--begin_ports--
//----------------------------
// Inputs
//----------------------------
input lmmi_clk,
input lmmi_resetn,
input [DWIDTH-1:0] lmmi_rdata,
input lmmi_rdata_valid,
input lmmi_ready,
//----------------------------
// Outputs
//----------------------------
output reg [AWIDTH-1:0] lmmi_offset,
output reg lmmi_request,
output reg [DWIDTH-1:0] lmmi_wdata,
output reg lmmi_wr_rdn
); //--end_ports--
//--------------------------------------------------------------------------
//--- Registers ---
//--------------------------------------------------------------------------
reg [8*15:1] model_name;
//reg [AWIDTH-1:0] addr;
//reg [DWIDTH-1:0] data;
//reg [DWIDTH-1:0] rddata;
reg [31:0] timeout_cntr;
initial begin
lmmi_offset = {AWIDTH{1'b0}};
lmmi_request = 1'b0;
lmmi_wdata = {DWIDTH{1'b0}};
lmmi_wr_rdn = 1'b0;
model_name = MODEL_NAME;
end
task m_write
(
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] data
);
begin
$display("[%010t] [%0s]: LMMI Write Access.. Addr=%0h, WriteData=%0h",$time, model_name, addr,data);
lmmi_request <= 1'b1;
lmmi_wr_rdn <= 1'b1;
lmmi_wdata <= data;
lmmi_offset <= addr;
if (lmmi_resetn)
@(posedge lmmi_clk);
while(~(lmmi_ready | ~lmmi_resetn)) begin // exits on ready and reset
@(posedge lmmi_clk);
end
lmmi_request <= 1'b0;
if (~lmmi_resetn) begin // negate all outputs
lmmi_wr_rdn <= 1'b0;
lmmi_wdata <= {DWIDTH{1'b0}};
lmmi_offset <= {AWIDTH{1'b0}};
end
end
endtask // m_write
task m_read //single access only, cannot do burst
(
input [AWIDTH-1:0] addr,
output [DWIDTH-1:0] data
);
reg done;
reg valid;
reg read_failed;
begin
lmmi_request <= 1'b1;
lmmi_wr_rdn <= 1'b0;
lmmi_offset <= addr;
timeout_cntr = 0;
read_failed = 0;
fork
begin // request
done = 0;
while(!done) begin
@(posedge lmmi_clk);
done = lmmi_ready;
end
lmmi_request <= 1'b0;
end
begin // data
valid = 0;
while(!valid | !done) begin
@(posedge lmmi_clk);
read_failed = (timeout_cntr > TIMEOUT_VALUE);
valid = (read_failed)? 1'b1 : lmmi_rdata_valid;
timeout_cntr = timeout_cntr + 1;
end
data = (read_failed)? {32{1'b1}} : lmmi_rdata;
end
join
if (read_failed)
$display("[%010t] [%0s]: LMMI Read Access Failed.. Addr=%0h Timeout value=%0h",$time,model_name,addr,TIMEOUT_VALUE);
else
$display("[%010t] [%0s]: LMMI Read Access.. Addr=%0h ReadData=%0h",$time,model_name,addr,data);
end
endtask // m_read
endmodule
| 7.428441 |
module tb_lms;
reg clk;
reg rst_n;
reg [15:0] d;
reg [15:0] x;
reg [ 3:0] u;
reg [15:0] signal;
wire [15:0] y;
wire [15:0] err;
wire [15:0] out;
initial begin
clk = 0;
rst_n = 0;
signal = 0;
d = 0;
x = 0;
u = 0;
#100
rst_n = 1;
#6000000
$finish;
end
always #10 clk = ~clk;
lms
//#(
//.W(16)
//)
lms_inst
(
.clk (clk ),
.rst_n (rst_n ),
.en (1'b1 ),
.din (d ),
.xin (x ),
.u (4'd6 ),
.yout (y ),
.err (err ),
.update ()
);
parameter datalen = 32000;
integer k,j,m;
reg [15:0] stimulus_s[1:datalen];
reg [15:0] stimulus_x[1:datalen];
reg [15:0] stimulus_d[1:datalen];
initial
begin
$readmemb("x_in.txt",stimulus_x);
k=0;
repeat(datalen)
begin
// #160;
k=k+1;
x = stimulus_x[k];
#160;
end
end
initial
begin
$readmemb("d_in.txt",stimulus_d);
j =0;
repeat(datalen)
begin
// #160;
j=j+1;
d = stimulus_d[j];
#160;
end
end
initial
begin
$readmemb("signal.txt",stimulus_s);
m=0;
repeat(datalen)
begin
// #160;
m=m+1;
signal = stimulus_s[m];
#160;
end
end
/*滤波后的数据输出，保存在out.txt中，用于matlab仿真分析*/
integer file_out;
initial
begin
file_out = $fopen("lms_err.txt");
if(!file_out)
begin
$display("could not open file");
$finish;
end
end
wire rst_write;
wire signed[15:0] yout_final;
assign yout_final = err;
// assign rst_write = sclk & (rst_n);//产生写入时钟信号，复位状态下不写入数据
// always @(posedge rst_write)
always @ (posedge clk)
$fdisplay(file_out,"%d",yout_final);
initial begin
$fsdbDumpfile("tb.fsdb");
$fsdbDumpvars;
end
endmodule
| 7.461522 |
module tb_LO;
// Inputs
reg clk;
reg rst;
reg start;
// Outputs
wire [15:0] sin;
wire [15:0] cos;
// DUT
local_oscillator dut (
.clk (clk),
.rst (rst),
.start(start),
.sin (sin),
.cos (cos)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
start = 1;
// Wait 10 ns for global reset to finish
#10;
rst = 1;
end
always #5 clk <= ~clk;
initial begin
#20000 $stop;
end
endmodule
| 7.374222 |
module tb_logic ();
reg clk, reset;
reg a, b, c, yexpected;
wire y;
reg [31:0] vectornum, errors;
reg [3:0] testvectors[10000:0];
// instantiate device under test
logic dut (
y,
a,
b,
c
);
// generate clock
always begin
clk = 1;
#5;
clk = 0;
#5;
end
// at start of test, load vectors
// and pulse reset
initial begin
$readmemb("example.tv", testvectors);
vectornum = 0;
errors = 0;
reset = 1;
#27;
reset = 0;
end
// apply test vectors on rising edge of clk
always @(posedge clk) begin
#1;
{a, b, c, yexpected} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset) begin // skip during reset
if (y !== yexpected) begin
$display("Error: inputs = %b", {a, b, c});
$display("outputs = %b (%b expected)", y, yexpected);
errors = errors + 1;
end
vectornum = vectornum + 1;
if (testvectors[vectornum] === 4'bx) begin
$display("%d tests completed with %d errors", vectornum, errors);
//$finish;
end
end
endmodule
| 7.026219 |
module tb_logic_analysis;
//print_task.vϢӡװ
print_task print ();
//sys_ctrl_task.vϵͳʱӲԪϵͳλ
sys_ctrl_task sys_ctrl (
.clk (clk),
.rst_n(rst_n)
);
//input
wire clk; //FPAGʱź25MHz
wire rst_n; //ϵͳλź
reg [3:0] signal; //4·ź
reg trigger; //1·źţΪػ½ش
reg tri_mode; //źģʽѡ1--ش0--½ش
reg [2:0] sampling_mode; //ģʽѡ,mode=001--MODE1mode=010--MODE2mode=100--MODE3
reg sampling_clr_n; //źţǰݣЧ
//output
wire hsync; //ͬź
wire vsync; //ͬź
wire vga_r;
wire vga_g;
wire vga_b;
//Թ̵ڲźŽй۲
/*wire clk_100m = uut.clk_100m; //PLL100MHz
wire clk_25m = uut.clk_25m; //PLL25MHz
wire[31:0] topic_data = uut.topic_data; //ROM
wire[7:0] topic_addr = uut.topic_addr; //ROMַ
wire[15:0] char_data = uut.char_data; //char ROM
wire[8:0] char_addr = uut.char_addr; //char ROMַ
*/
logic_analysis uut (
.clk(clk),
.rst_n(rst_n),
.signal(signal),
.trigger(trigger),
//.tri_mode(tri_mode),
//.sampling_mode(sampling_mode),
.add_key(add_key),
.dec_key(dec_key),
.sampling_clr_n(sampling_clr_n),
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
integer i;
parameter MODE1 = 3'b001, //MODE1
MODE2 = 3'b010, //MODE2
MODE3 = 3'b100; //MODE3
parameter POS_TRI = 1'b1, //ش
NEG_TRI = 1'b0; //½ش
//
task test_ing_task;
input [2:0] test_tri_mode; //ģʽ
input test_sap_mode; //ģʽ
begin
tri_mode = test_sap_mode;
sampling_mode = test_tri_mode;
trigger = ~test_sap_mode; //źŸλ
#10;
for (i = 0; i < 100; i = i + 1) begin
@(posedge clk);
signal = {$random} >> 28; //ź
end
trigger = test_sap_mode; //źŴ
#10;
for (i = 0; i < 100; i = i + 1) begin
@(posedge clk);
signal = {$random} >> 28; //ź
end
#1000; //delay 1us
end
endtask
//Ѵʾ
task wave_clr_task;
begin
sampling_clr_n = 1'b0;
#200;
sampling_clr_n = 1'b1;
#200;
end
endtask
//
initial begin
signal = 4'h0;
trigger = 1'b0;
tri_mode = 3'bzzz;
sampling_mode = 1'bz;
sampling_clr_n = 1'b1;
sys_ctrl.sys_reset(200); //Чλ200ns
#3_000; //delay 3us
//ֱԲͬĴģʽͲͬIJģʽǷҪ
wave_clr_task; //Ѵʾ
test_ing_task(MODE1, POS_TRI); //ģʽ1ش
wave_clr_task; //Ѵʾ
test_ing_task(MODE1, NEG_TRI); //ģʽ1½ش
wave_clr_task; //Ѵʾ
test_ing_task(MODE2, POS_TRI); //ģʽ2ش
wave_clr_task; //Ѵʾ
test_ing_task(MODE2, NEG_TRI); //ģʽ2½ش
wave_clr_task; //Ѵʾ
test_ing_task(MODE3, POS_TRI); //ģʽ3ش
wave_clr_task; //Ѵʾ
test_ing_task(MODE3, NEG_TRI); //ģʽ3½ش
#1000;
$stop;
end
endmodule
| 6.612361 |
module tb_log_memory;
localparam NB_DATA = 16;
localparam DEPTH = 32;
localparam NB_ADDR = $clog2(DEPTH);
reg clock, reset, run;
reg [NB_DATA-1 : 0] input_data;
wire [NB_DATA-1 : 0] output_data;
reg [NB_ADDR-1 : 0] read_addr;
wire tb_mem_full;
initial begin
clock = 0;
reset = 1;
run = 0;
read_addr = 0;
#6 reset = 0;
#6 run = 1;
input_data = 0;
end
always #1 clock = ~clock;
always @(posedge clock) begin
input_data <= input_data + 1;
end
always @(posedge clock) begin
if (tb_mem_full) read_addr <= read_addr + 1;
end
log_memory #(
.NB_DATA(NB_DATA),
.DEPTH (DEPTH),
.NB_ADDR(NB_ADDR)
) u_log_memory (
.i_clock (clock),
.i_reset (reset),
.i_run (run),
.i_read_addr(read_addr),
.i_data (input_data),
.o_full(tb_mem_full),
.o_data(output_data)
);
endmodule
| 6.661808 |
module tb_lookupflow ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg of_lookup_req;
reg [242:0] of_lookup_data;
wire of_lookup_ack;
wire of_lookup_err;
wire [3:0] of_lookup_fwd_port;
lookupflow #(
.NPORT(4'h4)
) lookupflow_tb (
.sys_clk(sys_clk)
, .sys_rst(sys_rst)
, .of_lookup_req(of_lookup_req)
, .of_lookup_data(of_lookup_data)
, .of_lookup_ack(of_lookup_ack)
, .of_lookup_err(of_lookup_err)
, .of_lookup_fwd_port(of_lookup_fwd_port)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
/*
always @(posedge sys_clk) begin
if (of_lookup_ack)
$display("dest_ip:%d.%d.%d.%d src_mac:%x dest_mac:%x forward_port:%b", dest_ip[31:24], dest_ip[23:16], dest_ip[15:8], dest_ip[7:0], src_mac, dest_mac, forward_port);
end
*/
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_lookupflow);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd1,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd2,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd3,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd4,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd5,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
of_lookup_req = 1'b1;
of_lookup_data = {
4'h0,
48'h0,
48'h0,
16'h0,
12'h0,
3'h0,
32'h0,
8'd10,
8'd0,
8'd0,
8'd6,
8'h0,
8'h0,
16'h0,
16'h0
};
waitclock;
of_lookup_req = 1'b0;
of_lookup_data = 243'h0;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
#300;
$finish;
end
endmodule
| 6.57943 |
module tb_lpf ();
reg [31:0] y_ex, x, lpf_k, ek_ex, ki, uk_min, uk_max;
reg clk;
reg rst_n;
reg lpfsta;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
lpfsta = 1'b0;
y_ex = 32'h46;
x = 32'h56;
lpf_k = 32'h66;
#500;
lpfsta = 1'b1;
rst_n = 1'b1;
#100;
lpfsta = 1'b0;
#5000;
$finish;
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0, tb_lpf, "+all");
end
lpf u_lpf (
.clk (clk),
.rst_n (rst_n),
.lpfsta(lpfsta),
.y_ex (y_ex),
.x (x),
.lpf_k (lpf_k)
);
endmodule
| 7.046486 |
module : tb_LRU
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_LRU();
//define the log2 function
function integer log2;
input integer value;
begin
value = value-1;
for(log2=0; value>0; log2=log2+1)
value = value >> 1;
end
endfunction
parameter WIDTH=4;
parameter INDEX_BITS = 8;
reg clock, reset;
reg [INDEX_BITS-1:0] current_index;
reg [log2(WIDTH)-1:0] access;
reg access_valid;
wire [WIDTH-1:0] lru;
LRU #(
.WIDTH(WIDTH),
.INDEX_BITS(INDEX_BITS)
) DUT (
.clock (clock ),
.reset (reset ),
.current_index(current_index),
.access (access ),
.access_valid (access_valid ),
.lru (lru )
);
always #1 clock = ~clock;
integer n;
initial begin
clock = 0;
reset = 0;
current_index = 1;
access_valid = 0;
access = 0;
n = 0;
@(posedge clock) reset <= 1;
repeat(5) @(posedge clock);
@(posedge clock) reset <= 0;
if (lru == 8)
n = n + 1; // 1 if all passed
repeat(2) @(posedge clock);
@(posedge clock)begin
access <= 2;
access_valid <= 1;
if (lru == 8)
n = n + 1; //2 if all passed
end
@(posedge clock) access_valid <= 0;
repeat(4) @(posedge clock);
@(posedge clock)begin
access <= 1;
access_valid <= 1;
if (lru == 8)
n = n + 1; //3 if all passed
end
@(posedge clock)begin
access <= 3;
access_valid <= 1;
if (lru == 8)
n = n + 1; //4 if all passed
end
@(posedge clock) access_valid <= 0;
repeat(4) @(posedge clock);
@(posedge clock)begin
access <= 2;
access_valid <= 1;
if (lru == 1)
n = n + 1; // 5 if all passed
end
@(posedge clock)begin
access <= 0;
access_valid <= 1;
if (lru == 1)
n = n + 1; // 6 if all passed
end
@(posedge clock) access_valid <= 0;
if(n == 6)begin
$display("All tests passed.");
$display("\ntb_LRU --> Test Passed!\n\n");
$stop;
end
else begin
$display("Failed one or more tests; simulation ends.");
$display("\ntb_lRU --> Test Failed!\n\n");
$stop;
end
end
endmodule
| 7.326626 |
module tb_LTC2351_controller ();
reg clk;
reg reset_n;
wire go;
wire [15:0] sample_rate;
wire sdo;
wire [95:0] data_out;
wire valid;
wire conv;
wire [95:0] data_in;
reg en;
parameter CLK_HALF_PERIOD = 20; // 25Mhz
parameter RST_DEASSERT_DELAY = 100;
parameter EN_DELAY = 110;
parameter END_SIM_DELAY = 10000;
assign sample_rate = 16'd100; // 250 ksps
// Uncomment to run the LTC2351 model with a DFF on the
// conv signal.
//`define TEST_WITH_FF = 1
// Generate the clock
initial begin
clk = 1'b0;
end
always begin
#CLK_HALF_PERIOD clk = ~clk;
end
// Generate the reset_n
initial begin
reset_n = 1'b0;
#RST_DEASSERT_DELAY reset_n = 1'b1;
end
// Generate the go
initial begin
en = 1'b0;
#EN_DELAY en = 1'b1;
end
// Stop the sim
initial begin
#END_SIM_DELAY;
$stop;
$finish; // close the simulation
end
// Sample_rate_controller
sample_rate_controller src1 (
.clk(clk),
.reset_n(reset_n),
.en(en),
.sample_rate(sample_rate),
.go(go)
);
// Set the ADC input data
assign data_in = {
2'bzz,
14'h3111,
2'bzz,
14'h3222,
2'bzz,
14'h3333,
2'bzz,
14'h3444,
2'bzz,
14'h3555,
2'bzz,
14'h3666
};
`ifndef TEST_WITH_FF
// Device under test
LTC2351_controller dut (
.clk(clk),
.reset_n(reset_n),
.go(go),
.data_in(sdo),
.conv(conv),
.valid(valid),
.data_out(data_out)
);
// The LTC2351 digital model
LTC2351_model m1 (
.sck(clk),
.reset_n(reset_n),
.conv(conv),
.sel(3'd5),
.sdo(sdo),
.data_in(data_in)
);
`else
// Device under test
LTC2351_controller #(
.RETIMEING_FF(1)
) dut (
.clk(clk),
.reset_n(reset_n),
.go(go),
.data_in(sdo),
.conv(conv),
.valid(valid),
.data_out(data_out)
);
reg conv_d1;
// The LTC2351 digital model
LTC2351_model m1 (
.sck(clk),
.reset_n(reset_n),
.conv(conv_d1),
.sel(3'd5),
.sdo(sdo),
.data_in(data_in)
);
always @(posedge clk) begin
conv_d1 <= conv;
end
`endif
endmodule
| 6.815079 |
module is to test the LTC2351 model
*/
module tb_LTC2351_model();
reg clk;
reg reset_n;
reg conv;
wire sdo;
wire [95:0] data_in;
assign data_in = {2'bzz, 14'h3111, 2'bzz, 14'h3222, 2'bzz, 14'h3333, 2'bzz, 14'h3444, 2'bzz, 14'h3555, 2'bzz, 14'h3666};
parameter CLK_HALF_PERIOD = 20; // 25Mhz
parameter RST_DEASSERT_DELAY = 100;
parameter CONV_ASSERTION_DELAY_IN_CLOCK_CYCLES = 100; //250Ksps
parameter END_SIM_DELAY = 10000;
// Generate the clock
initial
begin
clk = 1'b0;
end
always
begin
#CLK_HALF_PERIOD clk = ~clk;
end
// Generate the reset_n
initial
begin
reset_n = 1'b0;
#RST_DEASSERT_DELAY reset_n = 1'b1;
end
// Generate the conv
initial
begin
conv = 1'b0;
end
always
begin
repeat(CONV_ASSERTION_DELAY_IN_CLOCK_CYCLES *2)
#CLK_HALF_PERIOD;
conv = 1'b1;
repeat(2)
#CLK_HALF_PERIOD;
conv = 1'b0;
end
// Stop the sim
initial
begin
#END_SIM_DELAY;
$stop;
$finish; // close the simulation
end
LTC2351_model dut
(
.sck(clk),
.reset_n(reset_n),
.conv(conv),
.sel(3'd5),
.sdo(sdo),
.data_in(data_in)
);
endmodule
| 7.58345 |
module tb_lut_exponential ();
localparam SZ = 8;
reg [SZ-1:0] angle;
wire [SZ-1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [ 63:0] i;
initial begin
$write("Starting sim");
clk = 1'b0;
angle = 0;
#10 @(posedge clk);
// sin/cos output
for (
i = -180; i < 180; i = i + 1
) // from 0 to 359 degress in 1 degree increment
// for ( i = 30; i < 360; i=i+1) // increment by 30 degrees only
begin
@(posedge clk);
angle = ((1 << SZ) * i)/360 ; // example: 45 deg = 45 / 360 * 2^32 = 32'b00100000000000000000000000000000 = 45.000 degrees -> atan(2^0)
$display("angle = %d, %h", i, angle);
end
#500 $write("Simulation has finished");
$stop;
end
lut_exponential dut0 (
.angle(angle),
.exp (exp)
);
always #5 clk = ~clk;
endmodule
| 7.371991 |
module tb_lut_piecewise_exponential ();
localparam SZ = 8;
reg [SZ-1:0] angle;
wire [SZ-1:0] exp;
reg clk;
//wire [SZ-1:0] slope;
//wire [SZ-1:0] bias;
//wire [SZ-1:0] angle_out;
//wire [2*SZ-1:0] MulRst;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------
reg signed [ 63:0] i;
initial begin
$write("Starting sim");
clk = 1'b0;
angle = 0;
#10 @(posedge clk);
// sin/cos output
for (
i = -180; i < 180; i = i + 1
) // from 0 to 359 degress in 1 degree increment
// for ( i = 30; i < 360; i=i+1) // increment by 30 degrees only
begin
@(posedge clk);
angle = ((1 << SZ) * i)/360 ; // example: 45 deg = 45 / 360 * 2^32 = 32'b00100000000000000000000000000000 = 45.000 degrees -> atan(2^0)
$display("angle = %d, %h", i, angle);
end
#500 $write("Simulation has finished");
$stop;
end
//lut_piecewise_exponential#(.XY_SZ(SZ)) dut0(.clk(clk), .angle(angle), .exp(exp), .MulRst(MulRst), .slope(slope), .bias(bias), .angle_out(angle_out));
lut_piecewise_exponential #(
.XY_SZ(SZ)
) dut0 (
.clk (clk),
.angle(angle),
.exp (exp)
);
//Mul dut0(.clk(clk), .angle(angle), .exp(exp));
always #5 clk = ~clk;
endmodule
| 7.893788 |
module TB_LUT_SHIFT;
parameter ROM_WIDTH = 5;
// Inputs
reg CLK;
reg EN_ROM1;
reg [4:0] ADRS;
//outputs
wire [ROM_WIDTH-1:0] O_D;
// Instantiate the Unit Under Test (UUT)
LUT_SHIFT uut (
.CLK(CLK),
.EN_ROM1(EN_ROM1),
.ADRS(ADRS),
.O_D(O_D)
);
initial begin
// Initialize Inputs
CLK = 0;
EN_ROM1 = 0;
ADRS = 5'b00000;
#10 EN_ROM1 = 1;
// // Wait 100 ns for global reset to finish
#10 ADRS = 5'b00110;
#10 ADRS = 5'b00111;
#10 ADRS = 5'b01000;
#10 ADRS = 5'b11110;
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 CLK = ~CLK;
endmodule
| 7.0073 |
module tb_lzma_compressor ();
reg clk = 1'b0;
reg rstn = 1'b0;
always #5 clk = ~clk;
initial begin
repeat (5) @(posedge clk);
rstn <= 1'b1;
end
wire i_ready;
wire i_valid;
wire i_last;
wire [7:0] i_data;
wire o_valid;
wire [7:0] o_data;
wire o_last;
tb_random_data_source u_tb_random_data_source ( // generate input data
.clk (clk),
.tready(i_ready),
.tvalid(i_valid),
.tdata (i_data),
.tlast (i_last)
);
lzma_compressor_top u_lzma_compressor_top ( // design under test
.rstn (rstn),
.clk (clk),
.i_ready(i_ready),
.i_valid(i_valid),
.i_last (i_last),
.i_data (i_data),
.o_valid(o_valid),
.o_data (o_data),
.o_last (o_last)
);
tb_save_result_to_file u_tb_save_result_to_file ( // save output data
.clk (clk),
.tvalid(o_valid),
.tdata (o_data),
.tlast (o_last)
);
reg [31:0] cyc = 0;
always @(posedge clk)
if (i_valid | o_valid) cyc <= 0;
else if (cyc < 999999) cyc <= cyc + 1;
else $finish;
//initial $dumpvars(0, u_lzma_compressor_top);
endmodule
| 6.708391 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m1;
// Inputs
reg [31:0] tc_base;
reg [7:0] tc_ref;
reg [15:0] adc_data;
// Outputs
wire [31:0] tempc;
// Instantiate the Unit Under Test (UUT)
TemperatureCalculator uut (
.tc_base(tc_base),
.tc_ref(tc_ref),
.adc_data(adc_data),
.tempc(tempc)
);
initial begin
tc_ref = 8'b11111011; // -5
adc_data = 16'b1000000000001100; //-12
tc_base = 32'b00000000000000000000000000100010; // 34
#200;
$finish;
end
endmodule
| 8.396779 |
module: GasDetectorSensor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m2;
// Inputs
reg arst;
reg clk;
reg din;
// Outputs
wire [2:0] dout;
// Instantiate the Unit Under Test (UUT)
GasDetectorSensor uut (
.arst(arst),
.clk(clk),
.din(din),
.dout(dout)
);
initial begin
clk = 1'b0;
#1000
$finish;
end
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
din = 1'b0;
arst = 1'b0;
#5
arst = 1'b1;
#5
arst = 1'b0;
#20
din = 1'b1;
#20
din = 1'b0;
#20
din = 1'b1;
#20
din = 1'b1;
#20
din = 1'b1;
#20
din = 1'b0;
#20
din = 1'b1;
#20
din = 1'b0;
#20
din = 1'b1;
#20
din = 1'b0;
#20;
din = 1'b0;
#20;
din = 1'b1;
#20;
din = 1'b0;
#20;
din = 1'b0;
#20;
din = 1'b1;
#20;
din = 1'b1;
#20;
$finish;
end
endmodule
| 7.168269 |
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