code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axi_perf_mon_v5_0_11_counter #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input ... | 6.932985 |
module axi_perf_mon_v5_0_11_counter_ovf #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input ... | 6.932985 |
module axi_perf_mon_v5_0_11_glbl_clk_cnt #(
parameter C_FAMILY = "nofamily",
parameter C_GLOBAL_COUNT_WIDTH = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input Global_Clk_Cnt_En,
input ... | 6.932985 |
module.v
// Version : v5.0
// Description: AXI Performance monitor interrupt module generates
// interrupt to processor based on different counter/fifo
// overflow conditions
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------... | 6.757895 |
module. Interrupt generated
// at core clock are synchronized with AXI4-Lite clock
// pulse synchronization method is used for interrupt
// synchronization
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Struct... | 7.002021 |
module generates external event
// metric count enables which will be used in metric counter
// Verilog-Standard: Verilog 2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_ext_calc.v
//--------------... | 8.337749 |
module instantiates the counter
// with load value from sample interval register
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_samp_intl_cnt.v
//------------------------... | 7.670485 |
module accumulates metrics and samples
// into sampled metric counter if sampling trigger is set
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
// Structure:
// -- axi_perf_mon_v5_0_11_top.v
// -- axi_perf_mon_v5_0_11_profile.v
// ... | 7.097044 |
module_profile.v
// Version : v5.0
// Description : register module having all the registers of axi performance
// monitor read and write logic. Address decoding is also
// implemented in this module based on which the corresponding
// read and write enables being gen... | 7.065413 |
module axi_perf_mon_v5_0_11_sync_fifo #(
parameter WIDTH = 8, // The width of the FIFO data
parameter DEPTH_LOG2 = 3 // Specify power-of-2 FIFO depth
) (
input rst_n,
input clk,
input wren,
input rden,
input [WI... | 6.932985 |
module axi_perf_mon_v5_0_11_counter #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input ... | 6.932985 |
module axi_perf_mon_v5_0_11_counter_ovf #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input ... | 6.932985 |
module axi_perf_mon_v5_0_11_glbl_clk_cnt #(
parameter C_FAMILY = "nofamily",
parameter C_GLOBAL_COUNT_WIDTH = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input Global_Clk_Cnt_En,
input ... | 6.932985 |
module.v
// Version : v5.0
// Description: AXI Performance monitor interrupt module generates
// interrupt to processor based on different counter/fifo
// overflow conditions
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------... | 6.757895 |
module generates external event
// metric count enables which will be used in metric counter
// Verilog-Standard: Verilog 2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_ext_calc.v
//--------------... | 8.337749 |
module instantiates the counter
// with load value from sample interval register
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_samp_intl_cnt.v
//------------------------... | 7.670485 |
module. Interrupt generated
// at core clock are synchronized with AXI4-Lite clock
// pulse synchronization method is used for interrupt
// synchronization
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Struct... | 7.002021 |
module accumulates metrics and samples
// into sampled metric counter if sampling trigger is set
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
// Structure:
// -- axi_perf_mon_v5_0_11_top.v
// -- axi_perf_mon_v5_0_11_profile.v
// ... | 7.097044 |
module axi_pipe #(
parameter STAGES = 3
) (
input clk,
input reset,
input clear,
input i_tlast,
input i_tvalid,
output i_tready,
output o_tlast,
output o_tvalid,
input o_tready,
output [STAGES-1:0] enables,
output reg [STAGES-1:0] valids
);
assign o_tvalid = valids[STA... | 6.569749 |
module axi_pipe_join #(
parameter PRE_JOIN_STAGES0 = 3,
parameter PRE_JOIN_STAGES1 = 3,
parameter POST_JOIN_STAGES = 3
) (
input clk,
input reset,
input clear,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input i1_tlast,
input i1_tvalid,
output i1_tready,
output... | 7.3756 |
module axi_pipe_mac #(
parameter LATENCY = 3,
parameter CASCADE_IN = 0
) (
input clk,
input reset,
input clear,
input a_tlast,
input a_tvalid,
output a_tready,
input b_tlast,
input b_tvalid,
output b_tready,
input c_tlast,
input c_tvalid,
output c_tready,
outp... | 7.580024 |
module AXI_RAM_Slave_tb ();
//parameters
parameter HIGH = 1'b1;
parameter LOW = 1'b0;
//global signals
reg clk;
reg reset;
//write address channel
reg [3:0] awid;
reg [31:0] awaddr;
reg [3:0] awlen; //maximum of 16 ttransfers
reg [1:0] awsize; //max is 7 ,128 length, not sure
reg [1:0] a... | 7.636564 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_regfile_tb ();
localparam clk_period = 10;
localparam C_M00_AXI_ADDR_WIDTH = 32;
localparam C_M00_AXI_DATA_WIDTH = 32;
logic m00_axi_init_axi_txn;
logic m00_axi_error;
logic m00_axi_txn_done;
//
logic m00_axi_aclk;
logic m00_axi_aresetn;
logic [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr;... | 7.562335 |
module wraps the register file so that it can be instantiated in VHDL.
module axi_regfile_v1_0_S00_AXI_wrapper # (
parameter integer C_S_AXI_DATA_WIDTH = 32, // only 32 has been tested.
parameter integer C_S_AXI_ADDR_WIDTH = 5) // address width of the register file in bytes. For 16 32bit registers set this t... | 8.09981 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_register_slice_v2_1_22_tdm_sample (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire slow_clk,
input wire fast_clk,
output wire sample_cycle... | 7.238617 |
module="yes" *)
module axi_register_slice_v2_1_22_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
outpu... | 7.483958 |
module axi_register_slice_v2_1_22_auto_src #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DATA_WIDTH-1:0] payload_pi... | 7.238617 |
module axi_register_slice_v2_1_22_auto_dest #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DATA_WIDTH-1:0] payload_pi... | 7.238617 |
module axi_register_slice_v2_1_22_srl_rtl #(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
) (
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire ... | 7.238617 |
module axi_repeat #(
parameter WIDTH = 16
) (
input clk,
input reset,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output reg [WIDTH-1:0] o_tdata,
output reg o_tlast,
output reg o_tvalid,
input o_tready
);
assign i_tready = 1'b1;
always @(p... | 6.521732 |
module axi_rom (
clk,
rstn,
axi_ARVALID,
axi_ARREADY,
axi_AR,
axi_ARBURST,
axi_ARLEN,
axi_R,
axi_RVALID,
axi_RREADY,
axi_RLAST
);
input clk, rstn;
input axi_ARVALID, axi_RREADY;
output reg axi_ARREADY, axi_RVALID;
output reg axi_RLAST;
input [7:0] axi_ARLEN;
... | 8.029424 |
module axi_round #(
parameter WIDTH_IN = 17,
parameter WIDTH_OUT = 16,
parameter round_to_zero = 0, // original behavior
parameter round_to_nearest = 1, // lowest noise
parameter trunc = 0, // round to negative infinity
parameter FIFOSIZE = 0
) // leav... | 8.007399 |
module axi_round_and_clip #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter CLIP_BITS = 3,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
... | 6.585041 |
module axi_round_and_clip_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter CLIP_BITS = 3,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tr... | 6.585041 |
module axi_round_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH_OUT-1:0] o_t... | 7.189171 |
module AXI_RTC_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add port... | 7.389783 |
module axi_r_buffer #(
parameter ID_WIDTH = 4,
parameter DATA_WIDTH = 64,
parameter USER_WIDTH = 6,
parameter BUFFER_DEPTH = 8,
parameter STRB_WIDTH = DATA_WIDTH / 8 // DO NOT OVERRIDE
) (
clk_i,
rst_ni,
test_en_i,
slave_valid_i,
slave_data_i,
slave_resp_i,
sla... | 8.462336 |
module axi_r_reg_slice (
rvalids,
rids,
rdatas,
rresps,
rlasts,
rusers,
rreadym,
aclk,
aresetn,
rreadys,
rvalidm,
ridm,
rdatam,
rrespm,
rlastm,
ruserm
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDS... | 7.843582 |
module axi_sd_fifo #(
parameter addr_bits = 4
) (
input clk,
input rst,
input re,
input we,
input [31:0] din,
output reg [31:0] dout,
output [addr_bits-1:0] data_len,
output [addr_bits-1:0] free_len,
output full,
output empty
);
reg [31:0] mem[(1<<addr_bits)-1:0];
reg [a... | 6.518904 |
module axi_sd_fifo_filler #(
parameter fifo_addr_bits = 6
) (
input clock,
input clock_posedge,
input reset,
// Bus signals
output reg [31:2] bus_adr_o,
output [31:0] bus_dat_o,
input [31:0] bus_dat_i,
output bus_we_o,
output bus_stb_o,
input bus_last_i,
input bus_ack_i,... | 7.832133 |
module axi_self_test_master #(
parameter A_WIDTH_TEST = 26,
parameter A_WIDTH = 26,
parameter D_WIDTH = 16,
parameter D_LEVEL = 1,
parameter [7:0] WBURST_LEN = 8'd7,
parameter [7:0] RBURST_LEN = 8'd7
) (
input wire rstn,
input wi... | 7.509651 |
module axi_serializer #(
parameter WIDTH = 32
) (
input clk,
input rst,
input reverse_input,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output reg i_tready,
output reg o_tdata,
output reg o_tlast,
output reg o_tvalid,
input o_tready
);
reg i_tlast_latch;... | 7.353453 |
module axi_setting_reg #(
parameter ADDR = 0,
parameter USE_ADDR_LAST = 0,
parameter ADDR_LAST = ADDR + 1,
parameter AWIDTH = 8,
parameter WIDTH = 32,
parameter USE_FIFO = 0,
parameter FIFO_SIZE = 5,
parameter DATA_AT_RESET = 0,
parameter VALID_AT_RESET = 0,
parameter LAST_AT_RES... | 6.840989 |
module axi_shim (
input user_clk,
// Input AXI4-Lite interface
input t_awvalid,
input [ 31:0] t_awaddr,
input [ 3:0] t_awlen,
input [ 2:0] t_awregion,
input [ 2:0] t_awsize,
output t_awready,
input t_wvalid,
input [127:0] t_wdata,
in... | 7.959267 |
module axi_sim_sim_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET sync_rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN axi_sim_sim_clk_gen_0_0_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_PARAMET... | 7.09873 |
module axi_sink #(
parameter WIDTH = 24, // Must be 8x
parameter SIZE = 128,
parameter AXI = 64 // Must be 32 or 64
) (
input clk_i,
input rst_ni,
input srst_i,
input en_i,
input aval_i,
input [31:0] addr_i,
input val_i,
input [WIDTH-1:0] data_i,
input m_axi_a... | 7.721135 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module PREFIX_addr_gen (
PORTS
);
input clk;
input reset;
input [ADDR_BITS-1:0] cmd_addr;
input [SIZE_BITS-1:0] cmd_size;
input advance;
input restart;
output [ADDR_BITS-1:0] ADDR;
reg [ADDR_BITS-1:0] offset;
wire [ 3:0] size_bytes;
assign size_bytes =
cmd_size ... | 6.989261 |
module axi_slave_bfm ( /*AUTOARG*/
// Outputs
awready,
wready,
bid,
bresp,
bvalid,
arready,
rid,
rdata,
rresp,
rlast,
rvalid,
// Inputs
aclk,
aresetn,
awid,
awadr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
... | 7.441535 |
module PREFIX_busy(PORTS);
CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
`include "prgen_rand.v"
input clk;
input reset;
output ARBUSY;
output RBUSY;
output AWBUSY;
output WBUSY;
output BBUSY;
reg stall... | 6.837044 |
module PREFIX_cmd_fifo (PORTS);
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7... | 7.517693 |
module axi_slave_connect_example
*/
module axi_slave_connect_example (
output ariane_axi::req_t dm_axi_s_req,
input ariane_axi::resp_t dm_axi_s_resp,
input ariane_axi::req_t dm_axi_m_req,
output ariane_axi::resp_t dm_axi_m_resp
);
localparam AxiAddrWidth = 64;
localparam AxiDataWi... | 8.842413 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0... | 6.889752 |
module axi_slave_mux #(
parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
parameter DST_WIDTH = 16, // Width of DST field we are routing on.
parameter NUM_INPUTS = 2 // number of input AXI buses
) (
input clk,
input r... | 6.595203 |
module axi_slave_stub (
output S2M_AXI_ACLK,
// Read interface
input S2M_AXI_ARVALID,
output S2M_AXI_ARREADY,
input [31:0] S2M_AXI_ARADDR,
input [11:0] S2M_AXI_ARID,
output S2M_AXI_RVALID,
input S2M_AXI_RREADY,
output S2M_AXI_RLAST,
output [31:0] S2M_AXI_RDATA,
output [11:... | 6.631391 |
module axi_slave_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
) (
// Users to add p... | 6.957782 |
module PREFIX_wresp_fifo (
PORTS
);
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(... | 6.848803 |
module axi_source #(
parameter WIDTH = 24, // Must be 8x
parameter SIZE = 128,
parameter AXI = 64 // Must be 32 or 64
) (
input clk_i,
input rst_ni,
input srst_i,
input en_i,
input aval_i,
input [31:0] addr_i,
input rdy_i,
output [WIDTH-1:0] data_o,
input m_ax... | 8.247999 |
module AXI_SP32B1024 (
input CLK,
input RST,
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [ 3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input ... | 7.578883 |
module AXI_SPLIT #(
parameter AXIS_TDATA_WIDTH = 32,
parameter N_PORTS = 4 //Number of split ports, max 4, min 2
) (
input clk, //These are here to trick vivado
input rst,
//Slave input
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_DATA_tda... | 8.261344 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: AXI-stream upsizing or downsizing,
// see AMBA 4 AXI4-stream Protocol Version: 1.0 Specification -> 2.3.3 -> downsizing considerations
//--------------------------------------------------------------------------------------------------------
modul... | 9.286837 |
module axi_stream_ingress_demo #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8)
) (
input clk,
input rst,
//Write Data Channel
input i_tvalid,
output reg o_tready,
input [DATA_WIDTH... | 7.121741 |
module axi_stream_insert_header #(
parameter DATA_WD = 32,
parameter DATA_BYTE_WD = DATA_WD / 8
) (
input clk,
input rst_n,
// AXI Stream input original data
input valid_in,
input [DATA_WD-1 : 0] data_in,
input [DATA_BYTE_WD-1 : 0] keep_in,
input last_in,
output ready_in,
// ... | 7.121741 |
module implements a simple AXI4 Stream pipeline stage
*/
// `timescale 1ns/1ps
module axi_stream_pipeline
#(
// Pkt AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128
)
(
... | 6.904081 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: AXI-stream upsizing or downsizing,
// see AMBA 4 AXI4-stream Protocol Version: 1.0 Specification -> 2.3.3 -> downsizing considerations / upsizing considerations
//-------------------------------------------------------------------------------------... | 9.286837 |
module axi_stream_sample_v1_0_M00_AXIS_A #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH ... | 8.637001 |
module axi_stream_sample_v1_0_S00_AXIS_A #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
// Users to add ports here
output wire AXIS_SLAVE_VAILD,
... | 8.637001 |
module axi_sts_register #(
parameter integer STS_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Status bits
input wire [STS_DATA_WIDTH-1:0] sts_data,
// Slave side
inp... | 7.475637 |
module axi_arbiter_stom_s3 #(
parameter NUM = 3
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input ... | 7.648984 |
module axi_arbiter_stom_s5 #(
parameter NUM = 5
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input ... | 7.648984 |
module axi_sync #(
parameter SIZE = 2,
parameter WIDTH = 32,
parameter [32*SIZE-1:0] WIDTH_VEC = {SIZE{WIDTH[31:0]}},
parameter FIFO_SIZE = 0
) (
input clk,
input reset,
input clear,
input [msb(SIZE,WIDTH_VEC)-1:0] i_tdata,
input [SI... | 7.667937 |
module axi_test_vfifo #(
parameter PACKET_SIZE = 128
) (
input aclk,
input aresetn,
input enable,
// AXI Stream Out
output reg out_axis_tvalid,
input out_axis_tready,
output [63 : 0] out_axis_tdata,
output reg [7 : 0] out_axis_tstrb,
output reg [7 : 0] out_axis_tkeep,
output ... | 6.983659 |
module axi_throttle #(
parameter INITIAL_STATE = 0, // Throttle state after reset
parameter WAIT_FOR_LAST = 0, // 0: Throttle mid packet, 1: Wait for end of packet
parameter WIDTH = 64
) (
input clk,
input reset,
input enable,
output active,
input [WIDTH-1:0] i_tdata,
input... | 6.510657 |
module axi_time_out (
input clks,
input reset,
input vld_in,
input ready_in,
input [15:0] reg_tmout_us_cfg,
output reg time_out
);
////////////////////////////////////////////////////////////////////////////////
// parameter declear
///////////////////... | 6.97277 |
module axi_top (
input clk,
input rst_n,
output [2:0] slave_ARID,
output [2:0] slave_ARADDR,
output slave_ARVLD,
input slave_ARRDY,
//read data
input [2:0] slave_RID,
input [7:0] slave_RDATA,
input slave_RVLD,
output slave_RRDY,
//write addr
... | 7.001033 |
module apb_mux_s3
#(parameter P_NUM=3) // num of slaves
(
input wire [P_NUM-1:0] PSEL
, output reg [31:0] PRDATA
, input wire [31:0] PRDATA0
, input wire [31:0] PRDATA1
, input wire [31:0] PRDATA2
`ifdef AMBA_APB3
, output reg ... | 7.266466 |
module AXI_to_MEM_buffer #(
parameter AXI_DATA_WIDTH = 32,
parameter MEM_DATA_WIDTH = 128
) (
input clk,
input rst,
input [AXI_DATA_WIDTH-1:0] AXI_wdata_i,
input [MEM_DATA_WIDTH-1:0] MEM_rdata_i,
input AXI_read_req,
inpu... | 8.717123 |
module axi_to_strobed #(
parameter WIDTH = 32,
parameter FIFO_SIZE = 1,
parameter MIN_RATE = 256
) (
input clk,
input reset,
input clear,
input [$clog2(MIN_RATE):0] out_rate, // Number of clock cycles between strobes
inp... | 7.593528 |
module axi_traffic_controller_v1_0 #(
// Users to add parameters here
parameter write_data_file = "wire_data_example",
parameter write_addr_file = "write_addr_example",
parameter read_data_file = "read_data_example",
parameter read_addr_file = "read_addr_example",
// User parameters ends
/... | 7.121312 |
module axi_traffic_controller_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M_AXI_INIT_AXI_TXN;
wire M_AXI_TXN_DONE;
wire M_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (
.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M_AXI_TXN_DONE(M_AXI_TXN_DONE),
.M_AXI_ERROR(M_AX... | 7.121312 |
module axi_traffic_gen_v2_0_12_asynch_rst_ff (
data,
clk,
reset,
q
);
input data, clk, reset;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @(posedge clk or posedge reset) begin
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
end
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_regslice #(
parameter DWIDTH = 64,
parameter IDWIDTH = 64,
parameter DATADEPTH = 3 ,
parameter IDDEPTH = 2
) (
input [ DWIDTH-1:0] din,
output [ DWIDTH-1:0] dout,
output [ DWIDTH-1:0] dout_early,
input [IDWIDTH-1:0] idin,
output... | 6.812039 |
module axi_traffic_gen_v2_0_12_randgen #(
parameter seed = 16'hABCD
) (
output [15:0] randnum,
input generate_next,
input reset,
input clk
);
reg [15:0] lfsr;
wire lfsr_xnor;
always @(posedge clk) begin
if (reset) begin
lfsr <= seed;
end else if... | 6.812039 |
module axi_traffic_gen_v2_0_12_id_track #(
parameter ID_WIDTH = 1
) (
input Clk,
input rst_l,
input [ID_WIDTH-1:0] in_push_id,
input in_push,
input [ID_WIDTH-1:0] in_search_id,
input [ 3:0] in_clear_pos,
input in_... | 6.812039 |
module axi_traffic_gen_v2_0_12_static_cmdgen #(
parameter C_ATG_STATIC_ADDRESS = 32'h12A0_0000,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_ATG_MIF_ADDR_BITS = 4, // 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_STATIC_LENGTH = 3,
parameter C_ATG_SYSTEM_INIT = 0,
paramet... | 6.812039 |
module axi_traffic_gen_v2_0_12_axis_fifo #(
parameter WIDTH = 33,
parameter HEADREG = 1,
parameter ZERO_INVALID = 1,
parameter FULL_LEVEL = 14,
parameter DEPTH = 16,
parameter DEPTHBITS = 4
) (
input Clk,
input Rst_n,
input [ WIDTH-1:0] in_data,
input... | 6.812039 |
module axi_trivium_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 6
) (
// Users to add ... | 6.76226 |
module axi_true_dpbram #(
parameter DWIDTH = 128,
parameter AWIDTH = 7,
parameter MEM_SIZE = 98
) (
/* Special Inputs */
input clk,
/* input for port 0 */
input [AWIDTH - 1 : 0] addr0_i,
input ce0_i,
input we0_i,
input [DWIDTH -1 : 0] d0_i,
/* input for port 1 */
in... | 7.497574 |
module axi_uart #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
/*
* AXI output
*/
output wire [D... | 8.206574 |
module axi_vfifo_64 (
aclk,
aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m... | 7.161848 |
module axi_vga #(
parameter h_frontporch = 56 - 1,
parameter h_active = 56 + 120 - 1,
parameter h_backporch = 56 + 120 + 800 - 1,
parameter h_total = 56 + 120 + 800 + 64 - 1,
parameter v_frontporch = 37 - 1,
parameter v_active = 37 + 6 - 1,
parameter v_backporch = 37 + 6 + 60... | 8.139766 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_w_buffer #(
parameter DATA_WIDTH = 64,
parameter USER_WIDTH = 6,
parameter BUFFER_DEPTH = 2,
parameter STRB_WIDTH = DATA_WIDTH / 8 // DO NOT OVERRIDE
) (
clk_i,
rst_ni,
test_en_i,
slave_valid_i,
slave_data_i,
slave_strb_i,
slave_user_i,
slave_last_i,
... | 8.251875 |
module axi_w_reg_slice (
wreadys,
wvalidm,
widm,
wdatam,
wstrbm,
wlastm,
wuserm,
aclk,
aresetn,
wvalids,
wids,
wdatas,
wstrbs,
wlasts,
wusers,
wreadym
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDS... | 7.843046 |
module AxROM (
output led,
input m2,
input romsel,
input cpu_rw_in,
output [18:12] cpu_addr_out,
input [14:0] cpu_addr_in,
input [7:0] cpu_data_in,
output cpu_wr_out,
output cpu_rd_out,
output cpu_flash_ce,
output cpu_sram_ce,
input ppu_rd_in,
input ppu_wr_in,
i... | 7.073278 |
module ax_debounce (
input clk,
input rst,
input button_in,
output reg button_posedge,
output reg button_negedge,
output reg button_out
);
//// ---------------- internal constants --------------
parameter N = 32; // debounce timer bitwidth
parameter FREQ = 50; //model cloc... | 7.37815 |
module implements the modular product between an input
four term polynomial with coefficients in Galois-Field{2^8} <i_column> and
the AES cipher fixed polynomial {03}x^3+{01}x^2+{01}x^1+{02}x^0.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Arge... | 7.842559 |
module implements the modular product between an input
four term polynomial with coefficients in Galois-Field{2^8} <i_column> and
the AES cipher fixed polynomial {03}x^3+{01}x^2+{01}x^1+{02}x^0.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Arge... | 7.842559 |
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