code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axi_perf_mon_v5_0_11_counter #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input Count_Load,
input Count_Down,
output [(C_NUM_BITS - 1):0] Count_Out,
output reg Carry_Out
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire [63:0] rst_load_64 = (COUNTER_LOAD_VALUE == 32'h00000000)?64'h0000000000000000:{32'hFFFFFFFF,COUNTER_LOAD_VALUE};
wire Overflow;
reg Overflow_D1;
reg [C_NUM_BITS:0] Count_Out_i;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- counter
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Count_Out_i <= {1'b0, rst_load_64[C_NUM_BITS-1:0]};
end else begin
if (Count_Load == 1'b1) begin
Count_Out_i <= {1'b0, Load_In};
end else if (Count_Enable == 1'b1) begin
if (Count_Down == 1'b1) begin
Count_Out_i <= Count_Out_i - 1;
end else begin
Count_Out_i <= Count_Out_i + 1;
end
end else begin
Count_Out_i <= Count_Out_i;
end
end
end
assign Overflow = Count_Out_i[C_NUM_BITS];
assign Count_Out = Count_Out_i[C_NUM_BITS-1:0];
//-- Delaying Overflow
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Overflow_D1 <= 1'b0;
end else begin
Overflow_D1 <= Overflow;
end
end
//-- Overflow Pulse
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Carry_Out <= 1'b0;
end else begin
Carry_Out <= Overflow & (~Overflow_D1);
end
end
endmodule
| 6.932985 |
module axi_perf_mon_v5_0_11_counter_ovf #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input Count_Load,
input Count_Down,
output [(C_NUM_BITS - 1):0] Count_Out,
output Carry_Out
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire [63:0] rst_load_64 = (COUNTER_LOAD_VALUE == 32'h00000000)?64'h0000000000000000:{32'hFFFFFFFF,COUNTER_LOAD_VALUE};
reg [C_NUM_BITS : 0] Count_Out_i;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- counter
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Count_Out_i <= {1'b0, rst_load_64[C_NUM_BITS-1:0]};
end else begin
if (Count_Load == 1'b1) begin
Count_Out_i <= {1'b0, Load_In};
end else if (Count_Enable == 1'b1) begin
if (Count_Down == 1'b1) begin
Count_Out_i <= Count_Out_i - 1;
end else begin
Count_Out_i <= Count_Out_i + 1;
end
end else begin
Count_Out_i <= Count_Out_i;
end
end
end
assign Carry_Out = Count_Out_i[C_NUM_BITS];
assign Count_Out = Count_Out_i[C_NUM_BITS-1:0];
endmodule
| 6.932985 |
module axi_perf_mon_v5_0_11_glbl_clk_cnt #(
parameter C_FAMILY = "nofamily",
parameter C_GLOBAL_COUNT_WIDTH = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input Global_Clk_Cnt_En,
input Global_Clk_Cnt_Reset,
output [(C_GLOBAL_COUNT_WIDTH - 1):0] Global_Clk_Cnt,
output Global_Clk_Cnt_OF
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
localparam ALL_ZEROES = {C_GLOBAL_COUNT_WIDTH{1'b0}};
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Counter Instantiation
axi_perf_mon_v5_0_11_counter #(
.C_FAMILY (C_FAMILY),
.C_NUM_BITS (C_GLOBAL_COUNT_WIDTH),
.COUNTER_LOAD_VALUE(COUNTER_LOAD_VALUE)
) counter_inst (
.clk (clk),
.rst_n (rst_n),
.Load_In (ALL_ZEROES),
.Count_Enable(Global_Clk_Cnt_En),
.Count_Load (Global_Clk_Cnt_Reset),
.Count_Down (1'b0),
.Count_Out (Global_Clk_Cnt),
.Carry_Out (Global_Clk_Cnt_OF)
);
endmodule
| 6.932985 |
module.v
// Version : v5.0
// Description: AXI Performance monitor interrupt module generates
// interrupt to processor based on different counter/fifo
// overflow conditions
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_interrupt_module.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_interrupt_module
#(
parameter C_FAMILY = "nofamily",
parameter C_NUM_INTR_INPUTS = 10
)
(
input clk,
input rst_n,
input [(C_NUM_INTR_INPUTS - 1):0] Intr,
input Interrupt_Enable,
input IER_Wr_En,
input ISR_Wr_En,
input [(C_NUM_INTR_INPUTS - 1):0] Wr_Data,
output reg [(C_NUM_INTR_INPUTS - 1):0] IER,
output reg [(C_NUM_INTR_INPUTS - 1):0] ISR,
output reg Interrupt
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire irq_gen;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
IER <= 0;
end
else begin
if (IER_Wr_En == 1'b1) begin
IER <= Wr_Data;
end
else begin
IER <= IER;
end
end
end
genvar i;
generate
for (i=0; i < C_NUM_INTR_INPUTS ; i=i+1) begin : GEN_ISR_REG
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
ISR[i] <= 1'b0;
end
else begin
if ((ISR_Wr_En == 1'b1) && (Wr_Data[i] == 1'b1)) begin
ISR[i] <= 1'b0;
end
else if ((Intr[i] == 1'b1)) begin
ISR[i] <= 1'b1;
end
else begin
ISR[i] <= ISR[i];
end
end
end
end
endgenerate
assign irq_gen = | (ISR & IER);
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Interrupt <= 1'b0;
end
else begin
Interrupt <= irq_gen && Interrupt_Enable;
end
end
endmodule
| 6.757895 |
module. Interrupt generated
// at core clock are synchronized with AXI4-Lite clock
// pulse synchronization method is used for interrupt
// synchronization
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_intr_sync.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_intr_sync
#(
parameter C_FAMILY = "nofamily",
parameter C_DWIDTH = 32
)
(
input clk_1,
input rst_1_n,
input [(C_DWIDTH - 1):0] DATA_IN,
input clk_2,
input rst_2_n,
output [(C_DWIDTH - 1):0] SYNC_DATA_OUT
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
genvar i;
generate
for (i=0; i<C_DWIDTH; i=i+1) begin : GEN_SYNC
axi_perf_mon_v5_0_11_cdc_sync
#(
.c_cdc_type (0 ),
.c_flop_input (0 ),
.c_reset_state (1 ),
.c_single_bit (1 ),
.c_vector_width (1 ),
.c_mtbf_stages (4 )
)cdc_sync_inst
(
.prmry_aclk (clk_1 ),
.prmry_rst_n (rst_1_n ),
.prmry_in (DATA_IN[i] ),
.prmry_vect_in (1'b0 ),
.scndry_aclk (clk_2 ),
.scndry_rst_n (rst_2_n ),
.prmry_ack ( ),
.scndry_out (SYNC_DATA_OUT[i] ),
.scndry_vect_out ( )
);
end
endgenerate
endmodule
| 7.002021 |
module generates external event
// metric count enables which will be used in metric counter
// Verilog-Standard: Verilog 2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_ext_calc.v
//-----------------------------------------------------------------------------
// Author : NLR
// History:
// NLR 1/10/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_ext_calc
(
//AXI Signals
input clk,
input rst_n,
// External Events
input Ext_Event,
input Ext_Event_Start,
input Ext_Event_Stop,
input Ext_Event_Valid,
// Register inputs
input Metrics_Cnt_En,
input Metrics_Cnt_Reset,
//External Event outputs
output reg External_Event_Cnt_En
);
//Parameter Declarations
parameter RST_ACTIVE = 0;
//Register declarations
reg Ext_Event_going_on;
reg Ext_Event_d1;
reg Ext_Event_Valid_d1;
//wire declaration
wire rst_int_n1 = rst_n & ~(Metrics_Cnt_Reset);
reg rst_int_n;
always @(posedge clk) begin
rst_int_n <= rst_int_n1;
end
// External event enable generation logic
// Event going on signal generation based on start and stop signals
always @(posedge clk) begin
if (rst_int_n == RST_ACTIVE) begin
Ext_Event_going_on <= 1'b0;
end
else begin
if (Ext_Event_Stop == 1'b1 && Ext_Event_Valid == 1'b1) begin
Ext_Event_going_on <= 1'b0;
end
else if (Ext_Event_Start == 1'b1 && Ext_Event_Valid == 1'b1) begin
Ext_Event_going_on <= 1'b1;
end
else begin
Ext_Event_going_on <= Ext_Event_going_on;
end
end
end
// External event and corresponding event valid registering
always @(posedge clk) begin
if(rst_int_n == RST_ACTIVE) begin
Ext_Event_d1 <= 0;
Ext_Event_Valid_d1 <= 0;
end
else begin
Ext_Event_d1 <= Ext_Event;
Ext_Event_Valid_d1 <= Ext_Event_Valid;
end
end
// Event count enable generation
always @(posedge clk) begin
if(rst_int_n == RST_ACTIVE) begin
External_Event_Cnt_En <= 1'b0;
end
else begin
External_Event_Cnt_En <=Ext_Event_going_on & Ext_Event_d1 & Metrics_Cnt_En & Ext_Event_Valid_d1;
end
end
endmodule
| 8.337749 |
module instantiates the counter
// with load value from sample interval register
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_samp_intl_cnt.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_samp_intl_cnt
#(
parameter C_FAMILY = "nofamily",
parameter C_METRICS_SAMPLE_COUNT_WIDTH = 32
)
(
input clk,
input rst_n,
input Interval_Cnt_En,
input Interval_Cnt_Ld,
input [(C_METRICS_SAMPLE_COUNT_WIDTH - 1):0] Interval_Cnt_Ld_Val,
output [(C_METRICS_SAMPLE_COUNT_WIDTH - 1):0] Sample_Interval_Cnt,
output Sample_Interval_Cnt_Lapse
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
localparam ALL_ZEROES = {C_METRICS_SAMPLE_COUNT_WIDTH{1'b0}};
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire Sample_Interval_Cnt_Lapse_int;
wire Sample_Cnt_Ld = Interval_Cnt_Ld | Sample_Interval_Cnt_Lapse_int;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Counter Instantiation
axi_perf_mon_v5_0_11_counter
#(
.C_FAMILY (C_FAMILY),
.C_NUM_BITS (C_METRICS_SAMPLE_COUNT_WIDTH),
.COUNTER_LOAD_VALUE (32'h00000000)
) counter_inst
(
.clk (clk),
.rst_n (rst_n),
.Load_In (Interval_Cnt_Ld_Val),
.Count_Enable (Interval_Cnt_En),
.Count_Load (Sample_Cnt_Ld),
.Count_Down (1'b1),
.Count_Out (Sample_Interval_Cnt),
.Carry_Out (Sample_Interval_Cnt_Lapse_int)
);
assign Sample_Interval_Cnt_Lapse = Sample_Interval_Cnt_Lapse_int;
endmodule
| 7.670485 |
module accumulates metrics and samples
// into sampled metric counter if sampling trigger is set
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
// Structure:
// -- axi_perf_mon_v5_0_11_top.v
// -- axi_perf_mon_v5_0_11_profile.v
// \-- axi_perf_mon_v5_0_11_metric_counters_profile.v
// \--axi_perf_mon_v5_0_11_acc_sample_profile.v
//-----------------------------------------------------------------------------
// Author: NLR
// History:
// NLR 02/10/2013 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_perf_mon_v5_0_11_acc_sample_profile
#(
parameter C_FAMILY = "nofamily",
parameter DWIDTH = 32,
parameter C_HAVE_SAMPLED_METRIC_CNT = 1
)
(
input clk,
input rst_n,
input Sample_rst_n,
input Enable,
input Reset,
input [(DWIDTH - 1):0] Add_in,
input Add_in_Valid,
input Accumulate,
input Sample_En,
output [(DWIDTH - 1):0] Accumulator,
output [(DWIDTH - 1):0] Sample_Accumulator
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
reg [DWIDTH:0] Accum_i;
reg [DWIDTH-1:0] Samp_Metric_Cnt;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Accumulator
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Accum_i <= 0;
end
else begin
if (Reset == 1'b1) begin
Accum_i <= 0;
end
else if (Enable == 1'b1 && Add_in_Valid == 1'b1 && Accumulate == 1'b1) begin
Accum_i <= Accum_i + {1'b0, Add_in};
end
else if (Enable == 1'b1 && Add_in_Valid == 1'b1) begin
Accum_i <= Add_in ;
end
else begin
Accum_i <= Accum_i;
end
end
end
assign Accumulator = Accum_i[DWIDTH -1:0];
assign Overflow = Accum_i[DWIDTH] ;
//-- Sampled Metric Counter
generate
if (C_HAVE_SAMPLED_METRIC_CNT == 1) begin : GEN_SAMPLE_METRIC_CNT
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Samp_Metric_Cnt <= 0;
end
else begin
if (Sample_rst_n == RST_ACTIVE) begin
Samp_Metric_Cnt <= 0;
end
else if (Sample_En == 1'b1) begin
Samp_Metric_Cnt <= Accum_i[DWIDTH -1:0];
end
else begin
Samp_Metric_Cnt <= Samp_Metric_Cnt;
end
end
end
assign Sample_Accumulator = Samp_Metric_Cnt;
end
else begin : GEN_NO_SAMPLE_METRIC_CNT
assign Sample_Accumulator = 0;
end
endgenerate
endmodule
| 7.097044 |
module_profile.v
// Version : v5.0
// Description : register module having all the registers of axi performance
// monitor read and write logic. Address decoding is also
// implemented in this module based on which the corresponding
// read and write enables being generated
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
//
// axi_perf_mon_v5_0_11_top.v
// \-- axi_perf_mon_v5_0_11_dff_async_reset.v
//
//-----------------------------------------------------------------------------
// Description: Used to detect the edge for capture event and reset event
// ~~~~~~~~~~~
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module axi_perf_mon_v5_0_11_dff_async_reset (
data ,
clk ,
reset ,
q
);
input data, clk, reset ;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @ ( posedge clk or posedge reset)
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
endmodule
| 7.065413 |
module axi_perf_mon_v5_0_11_sync_fifo #(
parameter WIDTH = 8, // The width of the FIFO data
parameter DEPTH_LOG2 = 3 // Specify power-of-2 FIFO depth
) (
input rst_n,
input clk,
input wren,
input rden,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout,
output reg full,
output reg empty
);
localparam DEPTH = 1 << DEPTH_LOG2;
/* ========================================================================== */
// Register and Wire Declarations
/* ========================================================================== */
(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:DEPTH-1]; // memory for storing FIFO data
reg [DEPTH_LOG2:0] wptr; // wr ptr, with extra wrap bit
reg [DEPTH_LOG2:0] rptr; // rd ptr, with extra wrap bit
//reg rd_en_del; //Delayed read enable
wire [DEPTH_LOG2:0] wptr_inc; // wr ptr incremented by 1
wire [DEPTH_LOG2:0] rptr_inc; // rd ptr incremented by 1
wire [DEPTH_LOG2:0] wptr_nxt; // next wr ptr, with extra wrap bit
wire [DEPTH_LOG2:0] rptr_nxt; // next rd ptr, with extra wrap bit
wire [DEPTH_LOG2-1:0] mem_wptr; // mem wrptr, extra bit removed
wire [DEPTH_LOG2-1:0] mem_rptr; // mem rdptr, extra bit removed
wire almost_full; // only 1 entry available in FIFO
wire almost_empty; // only 1 space used in FIFO
//================================================================================
// Code the FIFO
//================================================================================
assign wptr_inc = wptr + 1'b1; // automatically wraps
assign rptr_inc = rptr + 1'b1; // automatically wraps
assign wptr_nxt = wren ? wptr_inc : wptr;
assign rptr_nxt = rden ? rptr_inc : rptr;
assign mem_wptr = wptr[DEPTH_LOG2-1:0]; // get rid of extra bit
assign mem_rptr = rptr[DEPTH_LOG2-1:0]; // get rid of extra bit
// Assign dout
always @(posedge clk) begin
//if (~rst_n)
// dout <= 0;
//else if(rden == 1'b1) begin
dout <= mem[mem_rptr]; //read data output
//end
end
// Almost_full if one more write will make the FIFO full
assign almost_full = (wptr_inc[DEPTH_LOG2] != rptr[DEPTH_LOG2]) &&
(wptr_inc[DEPTH_LOG2-1:0] == rptr[DEPTH_LOG2-1:0]);
// Almost_empty if one more read will make the FIFO empty
assign almost_empty = (wptr[DEPTH_LOG2:0] == rptr_inc[DEPTH_LOG2:0]);
// Flags
always @(posedge clk) begin
if (~rst_n) begin
full <= 1'b0;
empty <= 1'b1;
rptr <= {(DEPTH_LOG2 + 1) {1'b0}};
wptr <= {(DEPTH_LOG2 + 1) {1'b0}};
end else begin
full <= (almost_full & wren & ~rden) | (full & ~rden);
empty <= (almost_empty & rden & ~wren) | (empty & ~wren);
rptr <= rptr_nxt;
wptr <= wptr_nxt;
// rd_en_del <= rden;
end
end
// Assign memory
always @(posedge clk) begin
if (wren) mem[mem_wptr] <= din;
end
endmodule
| 6.932985 |
module axi_perf_mon_v5_0_11_counter #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input Count_Load,
input Count_Down,
output [(C_NUM_BITS - 1):0] Count_Out,
output reg Carry_Out
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire [63:0] rst_load_64 = (COUNTER_LOAD_VALUE == 32'h00000000)?64'h0000000000000000:{32'hFFFFFFFF,COUNTER_LOAD_VALUE};
wire Overflow;
reg Overflow_D1;
reg [C_NUM_BITS:0] Count_Out_i;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- counter
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Count_Out_i <= {1'b0, rst_load_64[C_NUM_BITS-1:0]};
end else begin
if (Count_Load == 1'b1) begin
Count_Out_i <= {1'b0, Load_In};
end else if (Count_Enable == 1'b1) begin
if (Count_Down == 1'b1) begin
Count_Out_i <= Count_Out_i - 1;
end else begin
Count_Out_i <= Count_Out_i + 1;
end
end else begin
Count_Out_i <= Count_Out_i;
end
end
end
assign Overflow = Count_Out_i[C_NUM_BITS];
assign Count_Out = Count_Out_i[C_NUM_BITS-1:0];
//-- Delaying Overflow
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Overflow_D1 <= 1'b0;
end else begin
Overflow_D1 <= Overflow;
end
end
//-- Overflow Pulse
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Carry_Out <= 1'b0;
end else begin
Carry_Out <= Overflow & (~Overflow_D1);
end
end
endmodule
| 6.932985 |
module axi_perf_mon_v5_0_11_counter_ovf #(
parameter C_FAMILY = "nofamily",
parameter C_NUM_BITS = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input [(C_NUM_BITS - 1):0] Load_In,
input Count_Enable,
input Count_Load,
input Count_Down,
output [(C_NUM_BITS - 1):0] Count_Out,
output Carry_Out
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire [63:0] rst_load_64 = (COUNTER_LOAD_VALUE == 32'h00000000)?64'h0000000000000000:{32'hFFFFFFFF,COUNTER_LOAD_VALUE};
reg [C_NUM_BITS : 0] Count_Out_i;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- counter
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Count_Out_i <= {1'b0, rst_load_64[C_NUM_BITS-1:0]};
end else begin
if (Count_Load == 1'b1) begin
Count_Out_i <= {1'b0, Load_In};
end else if (Count_Enable == 1'b1) begin
if (Count_Down == 1'b1) begin
Count_Out_i <= Count_Out_i - 1;
end else begin
Count_Out_i <= Count_Out_i + 1;
end
end else begin
Count_Out_i <= Count_Out_i;
end
end
end
assign Carry_Out = Count_Out_i[C_NUM_BITS];
assign Count_Out = Count_Out_i[C_NUM_BITS-1:0];
endmodule
| 6.932985 |
module axi_perf_mon_v5_0_11_glbl_clk_cnt #(
parameter C_FAMILY = "nofamily",
parameter C_GLOBAL_COUNT_WIDTH = 32,
parameter COUNTER_LOAD_VALUE = 32'h00000000
) (
input clk,
input rst_n,
input Global_Clk_Cnt_En,
input Global_Clk_Cnt_Reset,
output [(C_GLOBAL_COUNT_WIDTH - 1):0] Global_Clk_Cnt,
output Global_Clk_Cnt_OF
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
localparam ALL_ZEROES = {C_GLOBAL_COUNT_WIDTH{1'b0}};
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Counter Instantiation
axi_perf_mon_v5_0_11_counter #(
.C_FAMILY (C_FAMILY),
.C_NUM_BITS (C_GLOBAL_COUNT_WIDTH),
.COUNTER_LOAD_VALUE(COUNTER_LOAD_VALUE)
) counter_inst (
.clk (clk),
.rst_n (rst_n),
.Load_In (ALL_ZEROES),
.Count_Enable(Global_Clk_Cnt_En),
.Count_Load (Global_Clk_Cnt_Reset),
.Count_Down (1'b0),
.Count_Out (Global_Clk_Cnt),
.Carry_Out (Global_Clk_Cnt_OF)
);
endmodule
| 6.932985 |
module.v
// Version : v5.0
// Description: AXI Performance monitor interrupt module generates
// interrupt to processor based on different counter/fifo
// overflow conditions
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_interrupt_module.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_interrupt_module
#(
parameter C_FAMILY = "nofamily",
parameter C_NUM_INTR_INPUTS = 10
)
(
input clk,
input rst_n,
input [(C_NUM_INTR_INPUTS - 1):0] Intr,
input Interrupt_Enable,
input IER_Wr_En,
input ISR_Wr_En,
input [(C_NUM_INTR_INPUTS - 1):0] Wr_Data,
output reg [(C_NUM_INTR_INPUTS - 1):0] IER,
output reg [(C_NUM_INTR_INPUTS - 1):0] ISR,
output reg Interrupt
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire irq_gen;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
IER <= 0;
end
else begin
if (IER_Wr_En == 1'b1) begin
IER <= Wr_Data;
end
else begin
IER <= IER;
end
end
end
genvar i;
generate
for (i=0; i < C_NUM_INTR_INPUTS ; i=i+1) begin : GEN_ISR_REG
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
ISR[i] <= 1'b0;
end
else begin
if ((ISR_Wr_En == 1'b1) && (Wr_Data[i] == 1'b1)) begin
ISR[i] <= 1'b0;
end
else if ((Intr[i] == 1'b1)) begin
ISR[i] <= 1'b1;
end
else begin
ISR[i] <= ISR[i];
end
end
end
end
endgenerate
assign irq_gen = | (ISR & IER);
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Interrupt <= 1'b0;
end
else begin
Interrupt <= irq_gen && Interrupt_Enable;
end
end
endmodule
| 6.757895 |
module generates external event
// metric count enables which will be used in metric counter
// Verilog-Standard: Verilog 2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_ext_calc.v
//-----------------------------------------------------------------------------
// Author : NLR
// History:
// NLR 1/10/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_ext_calc
(
//AXI Signals
input clk,
input rst_n,
// External Events
input Ext_Event,
input Ext_Event_Start,
input Ext_Event_Stop,
input Ext_Event_Valid,
// Register inputs
input Metrics_Cnt_En,
input Metrics_Cnt_Reset,
//External Event outputs
output reg External_Event_Cnt_En
);
//Parameter Declarations
parameter RST_ACTIVE = 0;
//Register declarations
reg Ext_Event_going_on;
reg Ext_Event_d1;
reg Ext_Event_Valid_d1;
//wire declaration
wire rst_int_n1 = rst_n & ~(Metrics_Cnt_Reset);
reg rst_int_n;
always @(posedge clk) begin
rst_int_n <= rst_int_n1;
end
// External event enable generation logic
// Event going on signal generation based on start and stop signals
always @(posedge clk) begin
if (rst_int_n == RST_ACTIVE) begin
Ext_Event_going_on <= 1'b0;
end
else begin
if (Ext_Event_Stop == 1'b1 && Ext_Event_Valid == 1'b1) begin
Ext_Event_going_on <= 1'b0;
end
else if (Ext_Event_Start == 1'b1 && Ext_Event_Valid == 1'b1) begin
Ext_Event_going_on <= 1'b1;
end
else begin
Ext_Event_going_on <= Ext_Event_going_on;
end
end
end
// External event and corresponding event valid registering
always @(posedge clk) begin
if(rst_int_n == RST_ACTIVE) begin
Ext_Event_d1 <= 0;
Ext_Event_Valid_d1 <= 0;
end
else begin
Ext_Event_d1 <= Ext_Event;
Ext_Event_Valid_d1 <= Ext_Event_Valid;
end
end
// Event count enable generation
always @(posedge clk) begin
if(rst_int_n == RST_ACTIVE) begin
External_Event_Cnt_En <= 1'b0;
end
else begin
External_Event_Cnt_En <=Ext_Event_going_on & Ext_Event_d1 & Metrics_Cnt_En & Ext_Event_Valid_d1;
end
end
endmodule
| 8.337749 |
module instantiates the counter
// with load value from sample interval register
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_samp_intl_cnt.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_samp_intl_cnt
#(
parameter C_FAMILY = "nofamily",
parameter C_METRICS_SAMPLE_COUNT_WIDTH = 32
)
(
input clk,
input rst_n,
input Interval_Cnt_En,
input Interval_Cnt_Ld,
input [(C_METRICS_SAMPLE_COUNT_WIDTH - 1):0] Interval_Cnt_Ld_Val,
output [(C_METRICS_SAMPLE_COUNT_WIDTH - 1):0] Sample_Interval_Cnt,
output Sample_Interval_Cnt_Lapse
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
localparam ALL_ZEROES = {C_METRICS_SAMPLE_COUNT_WIDTH{1'b0}};
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
wire Sample_Interval_Cnt_Lapse_int;
wire Sample_Cnt_Ld = Interval_Cnt_Ld | Sample_Interval_Cnt_Lapse_int;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Counter Instantiation
axi_perf_mon_v5_0_11_counter
#(
.C_FAMILY (C_FAMILY),
.C_NUM_BITS (C_METRICS_SAMPLE_COUNT_WIDTH),
.COUNTER_LOAD_VALUE (32'h00000000)
) counter_inst
(
.clk (clk),
.rst_n (rst_n),
.Load_In (Interval_Cnt_Ld_Val),
.Count_Enable (Interval_Cnt_En),
.Count_Load (Sample_Cnt_Ld),
.Count_Down (1'b1),
.Count_Out (Sample_Interval_Cnt),
.Carry_Out (Sample_Interval_Cnt_Lapse_int)
);
assign Sample_Interval_Cnt_Lapse = Sample_Interval_Cnt_Lapse_int;
endmodule
| 7.670485 |
module. Interrupt generated
// at core clock are synchronized with AXI4-Lite clock
// pulse synchronization method is used for interrupt
// synchronization
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
// axi_perf_mon.v
// \-- axi_perf_mon_v5_0_11_intr_sync.v
//-----------------------------------------------------------------------------
// Author: Kalpanath
// History:
// Kalpanath 07/25/2012 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module axi_perf_mon_v5_0_11_intr_sync
#(
parameter C_FAMILY = "nofamily",
parameter C_DWIDTH = 32
)
(
input clk_1,
input rst_1_n,
input [(C_DWIDTH - 1):0] DATA_IN,
input clk_2,
input rst_2_n,
output [(C_DWIDTH - 1):0] SYNC_DATA_OUT
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
genvar i;
generate
for (i=0; i<C_DWIDTH; i=i+1) begin : GEN_SYNC
axi_perf_mon_v5_0_11_cdc_sync
#(
.c_cdc_type (0 ),
.c_flop_input (0 ),
.c_reset_state (1 ),
.c_single_bit (1 ),
.c_vector_width (1 ),
.c_mtbf_stages (4 )
)cdc_sync_inst
(
.prmry_aclk (clk_1 ),
.prmry_rst_n (rst_1_n ),
.prmry_in (DATA_IN[i] ),
.prmry_vect_in (1'b0 ),
.scndry_aclk (clk_2 ),
.scndry_rst_n (rst_2_n ),
.prmry_ack ( ),
.scndry_out (SYNC_DATA_OUT[i] ),
.scndry_vect_out ( )
);
end
endgenerate
endmodule
| 7.002021 |
module accumulates metrics and samples
// into sampled metric counter if sampling trigger is set
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
// Structure:
// -- axi_perf_mon_v5_0_11_top.v
// -- axi_perf_mon_v5_0_11_profile.v
// \-- axi_perf_mon_v5_0_11_metric_counters_profile.v
// \--axi_perf_mon_v5_0_11_acc_sample_profile.v
//-----------------------------------------------------------------------------
// Author: NLR
// History:
// NLR 02/10/2013 First Version
// ^^^^^^
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_perf_mon_v5_0_11_acc_sample_profile
#(
parameter C_FAMILY = "nofamily",
parameter DWIDTH = 32,
parameter C_HAVE_SAMPLED_METRIC_CNT = 1
)
(
input clk,
input rst_n,
input Sample_rst_n,
input Enable,
input Reset,
input [(DWIDTH - 1):0] Add_in,
input Add_in_Valid,
input Accumulate,
input Sample_En,
output [(DWIDTH - 1):0] Accumulator,
output [(DWIDTH - 1):0] Sample_Accumulator
);
//-------------------------------------------------------------------
// Parameter Declaration
//-------------------------------------------------------------------
localparam RST_ACTIVE = 1'b0;
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
reg [DWIDTH:0] Accum_i;
reg [DWIDTH-1:0] Samp_Metric_Cnt;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-- Accumulator
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Accum_i <= 0;
end
else begin
if (Reset == 1'b1) begin
Accum_i <= 0;
end
else if (Enable == 1'b1 && Add_in_Valid == 1'b1 && Accumulate == 1'b1) begin
Accum_i <= Accum_i + {1'b0, Add_in};
end
else if (Enable == 1'b1 && Add_in_Valid == 1'b1) begin
Accum_i <= Add_in ;
end
else begin
Accum_i <= Accum_i;
end
end
end
assign Accumulator = Accum_i[DWIDTH -1:0];
assign Overflow = Accum_i[DWIDTH] ;
//-- Sampled Metric Counter
generate
if (C_HAVE_SAMPLED_METRIC_CNT == 1) begin : GEN_SAMPLE_METRIC_CNT
always @(posedge clk) begin
if (rst_n == RST_ACTIVE) begin
Samp_Metric_Cnt <= 0;
end
else begin
if (Sample_rst_n == RST_ACTIVE) begin
Samp_Metric_Cnt <= 0;
end
else if (Sample_En == 1'b1) begin
Samp_Metric_Cnt <= Accum_i[DWIDTH -1:0];
end
else begin
Samp_Metric_Cnt <= Samp_Metric_Cnt;
end
end
end
assign Sample_Accumulator = Samp_Metric_Cnt;
end
else begin : GEN_NO_SAMPLE_METRIC_CNT
assign Sample_Accumulator = 0;
end
endgenerate
endmodule
| 7.097044 |
module axi_pipe #(
parameter STAGES = 3
) (
input clk,
input reset,
input clear,
input i_tlast,
input i_tvalid,
output i_tready,
output o_tlast,
output o_tvalid,
input o_tready,
output [STAGES-1:0] enables,
output reg [STAGES-1:0] valids
);
assign o_tvalid = valids[STAGES-1];
assign i_tready = enables[0];
// //////////////////////////////
// Valids
genvar i;
generate
for (i = 1; i < STAGES; i = i + 1)
always @(posedge clk)
if (reset | clear) valids[i] <= 1'b0;
else valids[i] <= valids[i-1] | (valids[i] & ~enables[i]);
endgenerate
always @(posedge clk)
if (reset | clear) valids[0] <= 1'b0;
else valids[0] <= i_tvalid | (valids[0] & ~enables[0]);
// //////////////////////////////
// Enables
genvar j;
generate
for (j = 0; j < STAGES; j = j + 1) assign enables[j] = o_tready | (|(~valids[STAGES-1:j]));
endgenerate
// /////////////////////////////
// tlast
reg [STAGES-1:0] tlast;
genvar k;
generate
for (k = 1; k < STAGES; k = k + 1)
always @(posedge clk)
if (reset | clear) tlast[k] <= 1'b0;
else if (enables[k]) tlast[k] <= tlast[k-1];
endgenerate
always @(posedge clk)
if (reset | clear) tlast[0] <= 1'b0;
else if (enables[0]) tlast[0] <= i_tlast;
assign o_tlast = tlast[STAGES-1];
endmodule
| 6.569749 |
module axi_pipe_join #(
parameter PRE_JOIN_STAGES0 = 3,
parameter PRE_JOIN_STAGES1 = 3,
parameter POST_JOIN_STAGES = 3
) (
input clk,
input reset,
input clear,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input i1_tlast,
input i1_tvalid,
output i1_tready,
output o_tlast,
output o_tvalid,
input o_tready,
output [PRE_JOIN_STAGES0-1:0] enables0,
output [PRE_JOIN_STAGES1-1:0] enables1,
output [POST_JOIN_STAGES-1:0] enables_post
);
wire join_tlast, join_tvalid, join_tready;
wire int0_tlast, int0_tvalid, int0_tready;
wire int1_tlast, int1_tvalid, int1_tready;
axi_pipe #(
.STAGES(PRE_JOIN_STAGES0)
) pipe_pre_0 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(i0_tlast),
.i_tvalid(i0_tvalid),
.i_tready(i0_tready),
.o_tlast(int0_tlast),
.o_tvalid(int0_tvalid),
.o_tready(int0_tready),
.enables(enables0),
.valids()
);
axi_pipe #(
.STAGES(PRE_JOIN_STAGES1)
) pipe_pre_1 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(i1_tlast),
.i_tvalid(i1_tvalid),
.i_tready(i1_tready),
.o_tlast(int1_tlast),
.o_tvalid(int1_tvalid),
.o_tready(int1_tready),
.enables(enables1),
.valids()
);
axi_pipe #(
.STAGES(POST_JOIN_STAGES)
) pipe_post (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(join_tlast),
.i_tvalid(join_tvalid),
.i_tready(join_tready),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.enables(enables_post),
.valids()
);
axi_join #(
.INPUTS(2)
) joiner (
.i_tlast ({int1_tlast, int0_tlast}),
.i_tvalid({int1_tvalid, int0_tvalid}),
.i_tready({int1_tready, int0_tready}),
.o_tlast (join_tlast),
.o_tvalid(join_tvalid),
.o_tready(join_tready)
);
endmodule
| 7.3756 |
module axi_pipe_mac #(
parameter LATENCY = 3,
parameter CASCADE_IN = 0
) (
input clk,
input reset,
input clear,
input a_tlast,
input a_tvalid,
output a_tready,
input b_tlast,
input b_tvalid,
output b_tready,
input c_tlast,
input c_tvalid,
output c_tready,
output p_tlast,
output p_tvalid,
input p_tready,
output [LATENCY-3:0] enables_a,
output [LATENCY-3:0] enables_b,
output enable_c,
output enable_m,
output enable_p
);
wire join_tlast, join_tvalid, join_tready;
wire join1_tlast, join1_tvalid, join1_tready;
wire int0_tlast, int0_tvalid, int0_tready;
wire int1_tlast, int1_tvalid, int1_tready;
wire int2_tlast, int2_tvalid, int2_tready;
wire int3_tlast, int3_tvalid, int3_tready;
axi_pipe #(
.STAGES(LATENCY - 2)
) pipe_a (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(a_tlast),
.i_tvalid(a_tvalid),
.i_tready(a_tready),
.o_tlast(int0_tlast),
.o_tvalid(int0_tvalid),
.o_tready(int0_tready),
.enables(enables_a),
.valids()
);
axi_pipe #(
.STAGES(LATENCY - 2)
) pipe_b (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(b_tlast),
.i_tvalid(b_tvalid),
.i_tready(b_tready),
.o_tlast(int1_tlast),
.o_tvalid(int1_tvalid),
.o_tready(int1_tready),
.enables(enables_b),
.valids()
);
axi_join #(
.INPUTS(2)
) join_ab (
.i_tlast ({int1_tlast, int0_tlast}),
.i_tvalid({int1_tvalid, int0_tvalid}),
.i_tready({int1_tready, int0_tready}),
.o_tlast (join_tlast),
.o_tvalid(join_tvalid),
.o_tready(join_tready)
);
axi_pipe #(
.STAGES(1)
) pipe_m (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(join_tlast),
.i_tvalid(join_tvalid),
.i_tready(join_tready),
.o_tlast(int2_tlast),
.o_tvalid(int2_tvalid),
.o_tready(int2_tready),
.enables(enable_m),
.valids()
);
// If we use the cascade input, there is no flop in the input side adder
generate
if (CASCADE_IN) begin
assign int3_tlast = c_tlast;
assign int3_tvalid = c_tvalid;
assign c_tready = int3_tready;
assign enable_c = 1'b0;
end else
axi_pipe #(
.STAGES(1)
) pipe_c (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(c_tlast),
.i_tvalid(c_tvalid),
.i_tready(c_tready),
.o_tlast(int3_tlast),
.o_tvalid(int3_tvalid),
.o_tready(int3_tready),
.enables(enable_c),
.valids()
);
endgenerate
axi_join #(
.INPUTS(2)
) joiner_mc (
.i_tlast ({int2_tlast, int3_tlast}),
.i_tvalid({int2_tvalid, int3_tvalid}),
.i_tready({int2_tready, int3_tready}),
.o_tlast (join1_tlast),
.o_tvalid(join1_tvalid),
.o_tready(join1_tready)
);
axi_pipe #(
.STAGES(1)
) pipe_p (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tlast(join1_tlast),
.i_tvalid(join1_tvalid),
.i_tready(join1_tready),
.o_tlast(p_tlast),
.o_tvalid(p_tvalid),
.o_tready(p_tready),
.enables(enable_p),
.valids()
);
endmodule
| 7.580024 |
module AXI_RAM_Slave_tb ();
//parameters
parameter HIGH = 1'b1;
parameter LOW = 1'b0;
//global signals
reg clk;
reg reset;
//write address channel
reg [3:0] awid;
reg [31:0] awaddr;
reg [3:0] awlen; //maximum of 16 ttransfers
reg [1:0] awsize; //max is 7 ,128 length, not sure
reg [1:0] awburst; //burst type of either fixed,incremental or wrapping burst
reg awvalid;
wire awready;
//write data channel
reg [3:0] wid;
reg [31:0] wdata;
reg [3:0] wstrb;
reg wlast;
reg wvalid;
wire wready;
//write response channel
wire [3:0] bid;
wire [1:0] bresp;
wire bvalid;
reg bready;
//read address channel
reg [3:0] arid;
reg [31:0] araddr;
reg [3:0] arlen;
reg [1:0] arsize;
reg [1:0] arburst;
reg arvalid;
wire arready;
//read data channel signals
wire [3:0] rid;
wire [31:0] rdata;
wire [1:0] rresp;
wire rlast;
wire rvalid;
reg rready;
AXI_Slave_RAM Test_Slave (
clk,
reset,
//write address channel
awid,
awaddr,
awlen,
awsize,
awburst,
awvalid,
awready,
//write data channel
wid,
wdata,
wstrb,
wlast,
wvalid,
wready,
//write response channel
bid,
bresp,
bvalid,
bready,
//read address channel
arid,
araddr,
arlen,
arsize,
arburst,
arvalid,
arready,
//read data channel signals
rid,
rdata,
rresp,
rlast,
rvalid,
rready
);
initial begin
clk = 0;
reset = 1;
//write address channel
awid = 0;
awaddr = 0;
awlen = 0; //maximum of 16 ttransfers
awsize = 0; //max is 7 ,128 length, not sure
awburst = 0; //burst type of either fixed,incremental or wrapping burst
awvalid = 0;
//write data channel
wid = 0;
wdata = 0;
wstrb = 0;
wlast = 0;
wvalid = 0;
//write response channel
bready = 0;
//read address channel
arid = 0;
araddr = 0;
arlen = 0;
arsize = 0;
arburst = 0;
arvalid = 0;
//read data channel signals
rready = 0;
end
initial begin
#1600 $finish;
end
always #20 clk = !clk;
initial begin
#100 #4 reset = 0;
#6 reset = 1;
#40 awvalid <= 1;
awaddr <= 32'd64;
awsize <= 1;
awlen <= 2;
awburst <= 2'b10; //incremetal burst
#40 awvalid = 0;
#40 awaddr <= 32'd512;
awsize <= 1;
awlen <= 2;
awvalid <= 1;
#40 awvalid <= 0;
#40 wdata <= 32'hFFFDFFFC;
wvalid = HIGH;
#40 wvalid = LOW;
#80 wdata <= 32'hFFFBFFFA;
wvalid = HIGH;
#40 wvalid = LOW;
#40 bready = 1;
//second write burst
#120 wdata <= 32'hFFF0FFF8;
wvalid = HIGH;
#40 wvalid = LOW;
#40 wdata <= 32'h444F555F;
wvalid = HIGH;
#40 wvalid = LOW;
//first read address transfer
#40 araddr <= 32'd64;
arvalid <= 1;
arsize <= 1;
arlen <= 2;
arburst <= 2'b10;
#40 arvalid <= LOW;
#160 rready = HIGH;
#40 rready = LOW;
#80 rready = HIGH;
#40 rready = LOW;
end
endmodule
| 7.636564 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_read_slave #(
parameter DATA_WIDTH = 32,
parameter READ_ACCEPTANCE = 4,
parameter MIN_LATENCY = 48,
parameter MAX_LATENCY = 48
) (
input clk,
input reset,
input arvalid,
output arready,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input [2:0] arprot,
input [3:0] arcache,
output rvalid,
input rready,
output [DATA_WIDTH-1:0] rdata,
output [1:0] rresp,
output rlast
);
reg [DATA_WIDTH-1:0] data = 'h00;
wire [31:0] beat_addr;
assign rresp = 2'b00;
assign rdata = data;
always @(*) begin: gen_data
integer i;
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
data[i+:8] <= beat_addr[7:0] + i / 8;
end
end
axi_slave #(
.DATA_WIDTH(DATA_WIDTH),
.ACCEPTANCE(READ_ACCEPTANCE),
.MIN_LATENCY(MIN_LATENCY),
.MAX_LATENCY(MAX_LATENCY)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(arvalid),
.ready(arready),
.addr(araddr),
.len(arlen),
.size(arsize),
.burst(arburst),
.prot(arprot),
.cache(arcache),
.beat_stb(rvalid),
.beat_ack(rvalid & rready),
.beat_last(rlast),
.beat_addr(beat_addr)
);
endmodule
| 8.180735 |
module axi_regfile_tb ();
localparam clk_period = 10;
localparam C_M00_AXI_ADDR_WIDTH = 32;
localparam C_M00_AXI_DATA_WIDTH = 32;
logic m00_axi_init_axi_txn;
logic m00_axi_error;
logic m00_axi_txn_done;
//
logic m00_axi_aclk;
logic m00_axi_aresetn;
logic [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr;
logic [2 : 0] m00_axi_awprot;
logic m00_axi_awvalid;
logic m00_axi_awready;
logic [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata;
logic [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb;
logic m00_axi_wvalid;
logic m00_axi_wready;
logic [1 : 0] m00_axi_bresp;
logic m00_axi_bvalid;
logic m00_axi_bready;
logic [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr;
logic [2 : 0] m00_axi_arprot;
logic m00_axi_arvalid;
logic m00_axi_arready;
logic [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata;
logic [1 : 0] m00_axi_rresp;
logic m00_axi_rvalid;
logic m00_axi_rready;
logic [7:0][31:0] slv_reg, slv_read;
assign slv_read = slv_reg;
logic clk = 0;
initial forever #(clk_period / 2) clk = ~clk;
assign m00_axi_aclk = clk;
initial begin
m00_axi_aresetn = 0;
m00_axi_init_axi_txn = 0;
#(clk_period * 10);
m00_axi_aresetn = 1;
#(clk_period * 10);
forever begin
m00_axi_init_axi_txn = 1;
#(clk_period * 1);
m00_axi_init_axi_txn = 0;
#(clk_period * 100);
end
end
axi_sim_master_v1_0 #(.C_M00_AXI_TRANSACTIONS_NUM(8)) axi_master (.*);
axi_regfile_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_ADDR_WIDTH(5)
) axi_regfile (
// registers out
.slv_reg(slv_reg),
// read ports in
.slv_read(slv_read),
// axi interface
.S_AXI_ACLK(m00_axi_aclk),
.S_AXI_ARESETN(m00_axi_aresetn),
.S_AXI_AWADDR(m00_axi_awaddr),
.S_AXI_AWPROT(m00_axi_awprot),
.S_AXI_AWVALID(m00_axi_awvalid),
.S_AXI_AWREADY(m00_axi_awready),
.S_AXI_WDATA(m00_axi_wdata),
.S_AXI_WSTRB(m00_axi_wstrb),
.S_AXI_WVALID(m00_axi_wvalid),
.S_AXI_WREADY(m00_axi_wready),
.S_AXI_BRESP(m00_axi_bresp),
.S_AXI_BVALID(m00_axi_bvalid),
.S_AXI_BREADY(m00_axi_bready),
.S_AXI_ARADDR(m00_axi_araddr),
.S_AXI_ARPROT(m00_axi_arprot),
.S_AXI_ARVALID(m00_axi_arvalid),
.S_AXI_ARREADY(m00_axi_arready),
.S_AXI_RDATA(m00_axi_rdata),
.S_AXI_RRESP(m00_axi_rresp),
.S_AXI_RVALID(m00_axi_rvalid),
.S_AXI_RREADY(m00_axi_rready)
);
endmodule
| 7.562335 |
module wraps the register file so that it can be instantiated in VHDL.
module axi_regfile_v1_0_S00_AXI_wrapper # (
parameter integer C_S_AXI_DATA_WIDTH = 32, // only 32 has been tested.
parameter integer C_S_AXI_ADDR_WIDTH = 5) // address width of the register file in bytes. For 16 32bit registers set this to 6.
(
// register file i/o
output wire [31:0] reg0_out,
output wire [31:0] reg1_out,
output wire [31:0] reg2_out,
output wire [31:0] reg3_out,
output wire [31:0] reg4_out,
output wire [31:0] reg5_out,
output wire [31:0] reg6_out,
output wire [31:0] reg7_out,
//
input wire [31:0] reg0_in,
input wire [31:0] reg1_in,
input wire [31:0] reg2_in,
input wire [31:0] reg3_in,
input wire [31:0] reg4_in,
input wire [31:0] reg5_in,
input wire [31:0] reg6_in,
input wire [31:0] reg7_in,
// axi port
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY);
logic [2**(C_S_AXI_ADDR_WIDTH-2)-1:0][C_S_AXI_DATA_WIDTH-1:0] slv_reg;
logic [2**(C_S_AXI_ADDR_WIDTH-2)-1:0][C_S_AXI_DATA_WIDTH-1:0] slv_read;
axi_regfile_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH))
axi_regfile (
// registers out
.slv_reg(slv_reg),
// read ports in
.slv_read(slv_read),
// axi interface
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY));
assign reg0_out = slv_reg[0];
assign reg1_out = slv_reg[1];
assign reg2_out = slv_reg[2];
assign reg3_out = slv_reg[3];
assign reg4_out = slv_reg[4];
assign reg5_out = slv_reg[5];
assign reg6_out = slv_reg[6];
assign reg7_out = slv_reg[7];
assign slv_read[0] = reg0_in;
assign slv_read[1] = reg1_in;
assign slv_read[2] = reg2_in;
assign slv_read[3] = reg3_in;
assign slv_read[4] = reg4_in;
assign slv_read[5] = reg5_in;
assign slv_read[6] = reg6_in;
assign slv_read[7] = reg7_in;
endmodule
| 8.09981 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_register_slice #(
parameter DATA_WIDTH = 32,
parameter FORWARD_REGISTERED = 0,
parameter BACKWARD_REGISTERED = 0)(
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
/*
s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
*/
wire [DATA_WIDTH-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [DATA_WIDTH-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid = 1'b0;
reg [DATA_WIDTH-1:0] fwd_data = 'h00;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready = 1'b1;
reg [DATA_WIDTH-1:0] bwd_data = 'h00;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin
assign bwd_valid_s = s_axi_valid;
assign bwd_data_s = s_axi_data;
assign bwd_ready_s = fwd_ready_s;
end endgenerate
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
assign s_axi_ready = bwd_ready_s;
endmodule
| 8.180735 |
module axi_register_slice_v2_1_22_tdm_sample (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire slow_clk,
input wire fast_clk,
output wire sample_cycle
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_clk_div2 = 1'b0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg sample_cycle_d;
(* shreg_extract = "no" *)reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge slow_clk) begin
slow_clk_div2 <= ~slow_clk_div2;
end
// Find matching rising edges by clocking slow_clk_div2 onto faster clock
always @(posedge fast_clk) begin
posedge_finder_first <= slow_clk_div2;
end
always @(posedge fast_clk) begin
posedge_finder_second <= ~slow_clk_div2;
end
assign first_edge = slow_clk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d = first_edge | second_edge;
end
always @(posedge fast_clk) begin
sample_cycle_r <= sample_cycle_d;
end
assign sample_cycle = sample_cycle_r;
endmodule
| 7.238617 |
module="yes" *)
module axi_register_slice_v2_1_22_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
wire handshake_pipe;
wire ready_pipe;
wire [C_DATA_WIDTH-1:0] payload_pipe;
(* keep="true" *) reg s_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg s_areset_resp = 1'b0;
(* keep="true" *) reg s_areset_resp2 = 1'b0;
(* keep="true" *) reg m_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg m_areset_resp = 1'b0;
(* keep="true" *) reg m_areset_resp2 = 1'b0;
// Global Reset pipelining
always @(posedge ACLK) begin
s_aclear <= ~ARESETN;
s_areset_fwd <= ~ARESETN;
s_areset_resp <= s_areset_fwd; // Auto-pipeline
s_areset_resp2 <= s_areset_resp; // Auto-pipeline
end
always @(posedge ACLK) begin
m_aclear <= ~ARESETN;
m_areset_fwd <= ~ARESETN;
m_areset_resp <= m_areset_fwd; // Auto-pipeline
m_areset_resp2 <= m_areset_resp; // Auto-pipeline
end
// Source-side submodule
axi_register_slice_v2_1_22_auto_src #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_src
(
.ACLK (ACLK),
.s_aclear (s_aclear),
.s_areset_resp2 (s_areset_resp2),
.S_VALID (S_VALID),
.S_READY (S_READY),
.S_PAYLOAD_DATA (S_PAYLOAD_DATA),
.ready_pipe (ready_pipe),
.handshake_pipe (handshake_pipe),
.payload_pipe (payload_pipe)
);
// Destination-side submodule
axi_register_slice_v2_1_22_auto_dest #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_dest
(
.ACLK (ACLK),
.m_aclear (m_aclear),
.m_areset_resp2 (m_areset_resp2),
.M_READY (M_READY),
.M_VALID (M_VALID),
.M_PAYLOAD_DATA (M_PAYLOAD_DATA),
.handshake_pipe (handshake_pipe),
.ready_pipe (ready_pipe),
.payload_pipe (payload_pipe)
);
endmodule
| 7.483958 |
module axi_register_slice_v2_1_22_auto_src #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DATA_WIDTH-1:0] payload_pipe,
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r;
(* keep="true" *) reg [2:0] s_aresetn_resp4 = 3'b000;
wire s_aresetn_resp3;
wire s_aresetn_d;
wire s_aresetn_q;
wire s_handshake_d;
wire s_ready_i;
assign S_READY = s_ready_i & s_aresetn_q;
assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;
assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;
assign payload_pipe = payload_pipe_r;
always @(posedge ACLK or posedge s_aclear) begin
if (s_aclear) begin
s_aresetn_resp4 <= 3'b000;
end else begin
s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};
end
end
always @(posedge ACLK) begin
payload_pipe_r <= S_PAYLOAD_DATA;
end
FDCE #(
.INIT(1'b0)
) s_aresetn_resp3_inst (
.Q (s_aresetn_resp3),
.C (ACLK),
.CE (1'b1),
.CLR(1'b0),
.D (~s_areset_resp2)
);
// Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (s_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR(s_aclear),
.D (s_aresetn_d)
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *)
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (handshake_pipe),
.C (ACLK),
.CE (1'b1),
.CLR(s_aclear),
.D (s_handshake_d)
);
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (s_ready_i),
.C (ACLK),
.CE (1'b1),
.CLR(s_aclear),
.D (ready_pipe)
);
endmodule
| 7.238617 |
module axi_register_slice_v2_1_22_auto_dest #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DATA_WIDTH-1:0] payload_pipe,
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
(* keep="true" *) reg [2:0] m_aresetn_resp4 = 3'b000;
wire m_aresetn_resp3;
wire m_aresetn_d;
wire m_aresetn_q;
wire m_valid_i;
wire pop;
wire m_ready_d;
wire m_handshake_q;
reg [C_DATA_WIDTH-1:0] m_payload_q;
assign M_VALID = m_valid_i;
assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;
assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;
assign pop = M_READY & m_valid_i;
always @(posedge ACLK or posedge m_aclear) begin
if (m_aclear) begin
m_aresetn_resp4 <= 3'b000;
end else begin
m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};
end
end
always @(posedge ACLK) begin
m_payload_q <= payload_pipe;
end
FDCE #(
.INIT(1'b0)
) m_aresetn_resp3_inst (
.Q (m_aresetn_resp3),
.C (ACLK),
.CE (1'b1),
.CLR(1'b0),
.D (~m_areset_resp2)
);
// Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (m_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (m_aresetn_d)
);
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (m_handshake_q),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (handshake_pipe)
);
(* autopipeline_group="resp" *)
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (ready_pipe),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (m_ready_d)
);
axi_register_slice_v2_1_22_axic_reg_srl_fifo #(
.C_FIFO_WIDTH(C_DATA_WIDTH),
.C_FIFO_SIZE (5)
) srl_fifo (
.aclk (ACLK),
.areset (~m_aresetn_q),
.aclear (m_aclear),
.s_mesg (m_payload_q),
.s_valid(m_handshake_q),
.m_mesg (M_PAYLOAD_DATA),
.m_valid(m_valid_i),
.m_ready(pop)
);
endmodule
| 7.238617 |
module axi_register_slice_v2_1_22_srl_rtl #(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
) (
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire q // Output Data
);
localparam integer P_SRLDEPTH = 2 ** C_A_WIDTH;
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge clk) if (ce) shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
assign q = shift_reg[a];
endmodule
| 7.238617 |
module axi_repeat #(
parameter WIDTH = 16
) (
input clk,
input reset,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output reg [WIDTH-1:0] o_tdata,
output reg o_tlast,
output reg o_tvalid,
input o_tready
);
assign i_tready = 1'b1;
always @(posedge clk) begin
if (reset) begin
o_tdata <= 'd0;
o_tlast <= 'd0;
o_tvalid <= 'd0;
end else begin
if (i_tvalid) begin
o_tvalid <= 1'b1;
o_tlast <= i_tlast;
o_tdata <= o_tdata;
end
end
end
endmodule
| 6.521732 |
module axi_rom (
clk,
rstn,
axi_ARVALID,
axi_ARREADY,
axi_AR,
axi_ARBURST,
axi_ARLEN,
axi_R,
axi_RVALID,
axi_RREADY,
axi_RLAST
);
input clk, rstn;
input axi_ARVALID, axi_RREADY;
output reg axi_ARREADY, axi_RVALID;
output reg axi_RLAST;
input [7:0] axi_ARLEN;
input [1:0] axi_ARBURST;
output [31:0] axi_R;
input [31:0] axi_AR;
reg [ 7:0] Mem [1023:0];
reg [31:0] Qint;
wire [ 9:0] A0;
reg [ 9:0] A1;
reg read_transaction;
reg burst_transaction;
reg [ 7:0] burstn;
reg [ 7:0] len;
assign A0 = {axi_AR[9:2], 2'b00};
initial begin
$readmemh("boot.mem", Mem, 0);
end
// Read process
always @(posedge clk) Qint[7:0] <= Mem[A1+0];
always @(posedge clk) Qint[15:8] <= Mem[A1+1];
always @(posedge clk) Qint[23:16] <= Mem[A1+2];
always @(posedge clk) Qint[31:24] <= Mem[A1+3];
assign axi_R = Qint;
// control
always @(posedge clk or negedge rstn)
if (~rstn) begin
axi_ARREADY <= 0;
axi_RVALID <= 0;
read_transaction <= 0;
burst_transaction <= 0;
burstn <= 0;
axi_RLAST <= 0;
end else begin
if (axi_ARVALID & ~read_transaction & ~burst_transaction) begin
axi_ARREADY <= 1;
A1 <= A0;
if ((axi_ARLEN != 8'h0) && (axi_ARBURST == 2'b01)) begin
len <= axi_ARLEN;
burst_transaction <= 1;
end else read_transaction <= 1;
end else begin
axi_ARREADY <= 0;
end
if (axi_RREADY & read_transaction) begin
axi_RVALID <= 1;
axi_RLAST <= 1;
read_transaction <= 0;
end else if (axi_RREADY & burst_transaction) begin
axi_RVALID <= 1;
if (burstn == len) begin
axi_RLAST <= 1;
burst_transaction <= 0;
end
burstn <= burstn + 1;
A1 <= A1 + 4;
end else begin
axi_RVALID <= 0;
axi_RLAST <= 0;
burstn <= 0;
end
end
endmodule
| 8.029424 |
module axi_round #(
parameter WIDTH_IN = 17,
parameter WIDTH_OUT = 16,
parameter round_to_zero = 0, // original behavior
parameter round_to_nearest = 1, // lowest noise
parameter trunc = 0, // round to negative infinity
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH_OUT-1:0] out;
generate
if (WIDTH_IN == WIDTH_OUT) begin
assign out = i_tdata;
end else begin
wire round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
wire [WIDTH_IN-WIDTH_OUT-1:0] err;
assign round_corr_trunc = 0;
assign round_corr_rtz = (i_tdata[WIDTH_IN-1] & |i_tdata[WIDTH_IN-WIDTH_OUT-1:0]);
assign round_corr_nearest = i_tdata[WIDTH_IN-WIDTH_OUT-1];
assign round_corr_nearest_safe = (WIDTH_IN-WIDTH_OUT > 1) ?
((~i_tdata[WIDTH_IN-1] & (&i_tdata[WIDTH_IN-2:WIDTH_IN-WIDTH_OUT])) ? 1'b0 : round_corr_nearest) :
round_corr_nearest;
assign round_corr = round_to_nearest ? round_corr_nearest_safe :
trunc ? round_corr_trunc :
round_to_zero ? round_corr_rtz :
0; // default to trunc
assign out = i_tdata[WIDTH_IN-1:WIDTH_IN-WIDTH_OUT] + round_corr;
assign err = i_tdata - {out, {(WIDTH_IN - WIDTH_OUT) {1'b0}}};
end
endgenerate
axi_fifo #(
.WIDTH(WIDTH_OUT + 1),
.SIZE (FIFOSIZE)
) flop (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata({i_tlast, out}),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.occupied(),
.space()
);
endmodule
| 8.007399 |
module axi_round_and_clip #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter CLIP_BITS = 3,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH_OUT+CLIP_BITS-1:0] int_tdata;
wire int_tlast, int_tvalid, int_tready;
axi_round #(
.WIDTH_IN(WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT + CLIP_BITS),
.round_to_nearest(1)
) round (
.clk(clk),
.reset(reset),
.i_tdata(i_tdata),
.i_tlast(i_tlast),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata(int_tdata),
.o_tlast(int_tlast),
.o_tvalid(int_tvalid),
.o_tready(int_tready)
);
axi_clip #(
.WIDTH_IN (WIDTH_OUT + CLIP_BITS),
.WIDTH_OUT(WIDTH_OUT),
.FIFOSIZE (FIFOSIZE)
) clip (
.clk(clk),
.reset(reset),
.i_tdata(int_tdata),
.i_tlast(int_tlast),
.i_tvalid(int_tvalid),
.i_tready(int_tready),
.o_tdata(o_tdata),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready)
);
endmodule
| 6.585041 |
module axi_round_and_clip_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter CLIP_BITS = 3,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH_IN-1:0] ii_tdata, iq_tdata;
wire ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata;
wire oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
split_complex #(
.WIDTH(WIDTH_IN)
) split (
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
.oi_tdata (ii_tdata),
.oi_tlast (ii_tlast),
.oi_tvalid(ii_tvalid),
.oi_tready(ii_tready),
.oq_tdata (iq_tdata),
.oq_tlast (iq_tlast),
.oq_tvalid(iq_tvalid),
.oq_tready(iq_tready)
);
axi_round_and_clip #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.CLIP_BITS(CLIP_BITS),
.FIFOSIZE (FIFOSIZE)
) r_and_c_i (
.clk(clk),
.reset(reset),
.i_tdata(ii_tdata),
.i_tlast(ii_tlast),
.i_tvalid(ii_tvalid),
.i_tready(ii_tready),
.o_tdata(oi_tdata),
.o_tlast(oi_tlast),
.o_tvalid(oi_tvalid),
.o_tready(oi_tready)
);
axi_round_and_clip #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.CLIP_BITS(CLIP_BITS),
.FIFOSIZE (FIFOSIZE)
) r_and_c_q (
.clk(clk),
.reset(reset),
.i_tdata(iq_tdata),
.i_tlast(iq_tlast),
.i_tvalid(iq_tvalid),
.i_tready(iq_tready),
.o_tdata(oq_tdata),
.o_tlast(oq_tlast),
.o_tvalid(oq_tvalid),
.o_tready(oq_tready)
);
join_complex #(
.WIDTH(WIDTH_OUT)
) join_complex (
.ii_tdata (oi_tdata),
.ii_tlast (oi_tlast),
.ii_tvalid(oi_tvalid),
.ii_tready(oi_tready),
.iq_tdata (oq_tdata),
.iq_tlast (oq_tlast),
.iq_tvalid(oq_tvalid),
.iq_tready(oq_tready),
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready)
);
endmodule
| 6.585041 |
module axi_round_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter FIFOSIZE = 0
) // leave at 0 for a normal single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH_IN-1:0] ii_tdata, iq_tdata;
wire ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata;
wire oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
split_complex #(
.WIDTH(WIDTH_IN)
) split_complex (
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
.oi_tdata (ii_tdata),
.oi_tlast (ii_tlast),
.oi_tvalid(ii_tvalid),
.oi_tready(ii_tready),
.oq_tdata (iq_tdata),
.oq_tlast (iq_tlast),
.oq_tvalid(iq_tvalid),
.oq_tready(iq_tready)
);
axi_round #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.FIFOSIZE (FIFOSIZE)
) axi_round_i (
.clk(clk),
.reset(reset),
.i_tdata(ii_tdata),
.i_tlast(ii_tlast),
.i_tvalid(ii_tvalid),
.i_tready(ii_tready),
.o_tdata(oi_tdata),
.o_tlast(oi_tlast),
.o_tvalid(oi_tvalid),
.o_tready(oi_tready)
);
axi_round #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.FIFOSIZE (FIFOSIZE)
) axi_round_q (
.clk(clk),
.reset(reset),
.i_tdata(iq_tdata),
.i_tlast(iq_tlast),
.i_tvalid(iq_tvalid),
.i_tready(iq_tready),
.o_tdata(oq_tdata),
.o_tlast(oq_tlast),
.o_tvalid(oq_tvalid),
.o_tready(oq_tready)
);
join_complex #(
.WIDTH(WIDTH_OUT)
) join_complex (
.ii_tdata (oi_tdata),
.ii_tlast (oi_tlast),
.ii_tvalid(oi_tvalid),
.ii_tready(oi_tready),
.iq_tdata (oq_tdata),
.iq_tlast (oq_tlast),
.iq_tvalid(oq_tvalid),
.iq_tready(oq_tready),
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready)
);
endmodule
| 7.189171 |
module AXI_RTC_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input i_modify,
input [7:0] i_im_min,
i_im_hour,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
AXI_RTC_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) AXI_RTC_v1_0_S00_AXI_inst (
.i_msec(w_msec),
.i_sec(w_sec),
.i_min(w_min),
.i_hour(w_hour),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
wire [7:0] w_msec, w_sec, w_min, w_hour;
// Add user logic here
top_RTC(
.sys_clock(s00_axi_aclk),
.i_modify(i_modify),
.i_im_min(i_im_min),
.i_im_hour(i_im_hour),
.o_msec(w_msec),
.o_sec(w_sec),
.o_min(w_min),
.o_hour(w_hour)
);
// User logic ends
endmodule
| 7.389783 |
module axi_r_buffer #(
parameter ID_WIDTH = 4,
parameter DATA_WIDTH = 64,
parameter USER_WIDTH = 6,
parameter BUFFER_DEPTH = 8,
parameter STRB_WIDTH = DATA_WIDTH / 8 // DO NOT OVERRIDE
) (
clk_i,
rst_ni,
test_en_i,
slave_valid_i,
slave_data_i,
slave_resp_i,
slave_user_i,
slave_id_i,
slave_last_i,
slave_ready_o,
master_valid_o,
master_data_o,
master_resp_o,
master_user_o,
master_id_o,
master_last_o,
master_ready_i
);
//parameter ID_WIDTH = 4;
//parameter DATA_WIDTH = 64;
//parameter USER_WIDTH = 6;
//parameter BUFFER_DEPTH = 8;
//parameter STRB_WIDTH = DATA_WIDTH / 8;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire slave_valid_i;
input wire [DATA_WIDTH - 1:0] slave_data_i;
input wire [1:0] slave_resp_i;
input wire [USER_WIDTH - 1:0] slave_user_i;
input wire [ID_WIDTH - 1:0] slave_id_i;
input wire slave_last_i;
output wire slave_ready_o;
output wire master_valid_o;
output wire [DATA_WIDTH - 1:0] master_data_o;
output wire [1:0] master_resp_o;
output wire [USER_WIDTH - 1:0] master_user_o;
output wire [ID_WIDTH - 1:0] master_id_o;
output wire master_last_o;
input wire master_ready_i;
wire [((2 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH:0] s_data_in;
wire [((2 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH:0] s_data_out;
assign s_data_in = {slave_id_i, slave_user_i, slave_data_i, slave_resp_i, slave_last_i};
assign {master_id_o, master_user_o, master_data_o, master_resp_o, master_last_o} = s_data_out;
generic_fifo #(
.DATA_WIDTH(((3 + DATA_WIDTH) + USER_WIDTH) + ID_WIDTH),
.DATA_DEPTH(BUFFER_DEPTH)
) buffer_i (
.clk(clk_i),
.rst_n(rst_ni),
.data_i(s_data_in),
.valid_i(slave_valid_i),
.grant_o(slave_ready_o),
.data_o(s_data_out),
.valid_o(master_valid_o),
.grant_i(master_ready_i),
.test_mode_i(test_en_i)
);
endmodule
| 8.462336 |
module axi_r_reg_slice (
rvalids,
rids,
rdatas,
rresps,
rlasts,
rusers,
rreadym,
aclk,
aresetn,
rreadys,
rvalidm,
ridm,
rdatam,
rrespm,
rlastm,
ruserm
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + DATA_WIDTH + USER_WIDTH + 3;
input aclk;
input aresetn;
output rvalids;
input rreadys;
output [ID_WIDTH-1:0] rids;
output [DATA_WIDTH-1:0] rdatas;
output [1:0] rresps;
output rlasts;
output [USER_WIDTH-1:0] rusers;
input rvalidm;
output rreadym;
input [ID_WIDTH-1:0] ridm;
input [DATA_WIDTH-1:0] rdatam;
input [1:0] rrespm;
input rlastm;
input [USER_WIDTH-1:0] ruserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = rvalidm;
assign rreadym = ready_src;
assign payload_src = {ridm, rdatam, rrespm, rlastm, ruserm};
assign rvalids = valid_dst;
assign ready_dst = rreadys;
assign {rids, rdatas, rresps, rlasts, rusers} = payload_dst;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.843582 |
module axi_sd_fifo #(
parameter addr_bits = 4
) (
input clk,
input rst,
input re,
input we,
input [31:0] din,
output reg [31:0] dout,
output [addr_bits-1:0] data_len,
output [addr_bits-1:0] free_len,
output full,
output empty
);
reg [31:0] mem[(1<<addr_bits)-1:0];
reg [addr_bits-1:0] inp_pos;
reg [addr_bits-1:0] out_pos;
wire [addr_bits-1:0] inp_nxt;
wire [addr_bits-1:0] out_nxt;
assign full = inp_nxt == out_pos;
assign empty = inp_pos == out_pos;
assign inp_nxt = inp_pos + 1;
assign out_nxt = out_pos + 1;
assign data_len = inp_pos - out_pos;
assign free_len = out_pos - inp_nxt;
always @(posedge clk)
if (rst) begin
inp_pos <= 0;
out_pos <= 0;
end else begin
if (we && !full) begin
mem[inp_pos] <= din;
inp_pos <= inp_nxt;
if (empty) dout <= din;
end
if (re && !empty) begin
if (we && !full && out_nxt == inp_pos) dout <= din;
else dout <= mem[out_nxt];
out_pos <= out_nxt;
end
end
endmodule
| 6.518904 |
module axi_sd_fifo_filler #(
parameter fifo_addr_bits = 6
) (
input clock,
input clock_posedge,
input reset,
// Bus signals
output reg [31:2] bus_adr_o,
output [31:0] bus_dat_o,
input [31:0] bus_dat_i,
output bus_we_o,
output bus_stb_o,
input bus_last_i,
input bus_ack_i,
// Data Master Control signals
input en_rx_i,
input en_tx_i,
input [31:2] adr_i,
// Data Serial signals
input [31:0] dat_i,
output [31:0] dat_o,
input wr_i,
input rd_i,
output [fifo_addr_bits-1:0] tx_free,
output [fifo_addr_bits-1:0] rx_data,
output rx_full_o,
output tx_empty_o,
output tx_ready_o,
output rx_empty_o
);
localparam fifo_threshold = 1 << (fifo_addr_bits - 1);
reg bus_wait;
wire [fifo_addr_bits-1:0] tx_data;
wire tx_stb;
wire rx_stb;
assign tx_ready_o = tx_data >= fifo_threshold;
assign tx_stb = en_tx_i && tx_free >= fifo_threshold;
assign rx_stb = en_rx_i ? (rx_data >= fifo_threshold) : !rx_empty_o;
assign bus_we_o = !rx_empty_o;
assign bus_stb_o = bus_wait | tx_stb | rx_stb;
// Note: bus accesses continue for a while after en_rx_i goes to 0
axi_sd_fifo #(
.addr_bits(fifo_addr_bits)
) rx_fifo (
.clk(clock),
.rst(reset),
.din(dat_i),
.we(wr_i & clock_posedge),
.dout(bus_dat_o),
.re(bus_we_o & bus_stb_o & bus_ack_i),
.data_len(rx_data),
.full(rx_full_o),
.empty(rx_empty_o)
);
// TODO: tx fifo reads more memory words than needed
axi_sd_fifo #(
.addr_bits(fifo_addr_bits)
) tx_fifo (
.clk(clock),
.rst(reset | !en_tx_i),
.din(bus_dat_i),
.we(!bus_we_o & bus_stb_o & bus_ack_i),
.dout(dat_o),
.re(rd_i & clock_posedge),
.free_len(tx_free),
.data_len(tx_data),
.empty(tx_empty_o)
);
always @(posedge clock)
if (reset) begin
bus_adr_o <= 0;
bus_wait <= 0;
end else if (bus_stb_o & bus_ack_i) begin
bus_adr_o <= bus_adr_o + 1;
bus_wait <= !bus_last_i;
end else if (bus_stb_o) begin
bus_wait <= 1;
end else if (!en_rx_i & !en_tx_i & rx_empty_o) bus_adr_o <= adr_i;
endmodule
| 7.832133 |
module axi_self_test_master #(
parameter A_WIDTH_TEST = 26,
parameter A_WIDTH = 26,
parameter D_WIDTH = 16,
parameter D_LEVEL = 1,
parameter [7:0] WBURST_LEN = 8'd7,
parameter [7:0] RBURST_LEN = 8'd7
) (
input wire rstn,
input wire clk,
output wire awvalid,
input wire awready,
output reg [A_WIDTH-1:0] awaddr,
output wire [ 7:0] awlen,
output wire wvalid,
input wire wready,
output wire wlast,
output wire [D_WIDTH-1:0] wdata,
input wire bvalid,
output wire bready,
output wire arvalid,
input wire arready,
output reg [A_WIDTH-1:0] araddr,
output wire [ 7:0] arlen,
input wire rvalid,
output wire rready,
input wire rlast,
input wire [D_WIDTH-1:0] rdata,
output reg error,
output reg [ 15:0] error_cnt
);
initial {awaddr, araddr} = 0;
initial {error, error_cnt} = 0;
wire aw_end;
reg awaddr_carry = 1'b0;
reg [7:0] w_cnt = 8'd0;
localparam [2:0] INIT = 3'd0, AW = 3'd1, W = 3'd2, B = 3'd3, AR = 3'd4, R = 3'd5;
reg [2:0] stat = INIT;
generate
if (A_WIDTH_TEST < A_WIDTH) assign aw_end = awaddr[A_WIDTH_TEST];
else assign aw_end = awaddr_carry;
endgenerate
assign awvalid = stat == AW;
assign awlen = WBURST_LEN;
assign wvalid = stat == W;
assign wlast = w_cnt == WBURST_LEN;
assign wdata = awaddr;
assign bready = 1'b1;
assign arvalid = stat == AR;
assign arlen = RBURST_LEN;
assign rready = 1'b1;
localparam [A_WIDTH:0] ADDR_INC = (1 << D_LEVEL);
wire [A_WIDTH:0] araddr_next = {1'b0, araddr} + ADDR_INC;
always @(posedge clk or negedge rstn)
if (~rstn) begin
{awaddr_carry, awaddr} <= 0;
w_cnt <= 8'd0;
araddr <= 0;
stat <= INIT;
end else begin
case (stat)
INIT: begin
{awaddr_carry, awaddr} <= 0;
w_cnt <= 8'd0;
araddr <= 0;
stat <= AW;
end
AW:
if (awready) begin
w_cnt <= 8'd0;
stat <= W;
end
W:
if (wready) begin
{awaddr_carry, awaddr} <= {awaddr_carry, awaddr} + ADDR_INC;
w_cnt <= w_cnt + 8'd1;
if (wlast) stat <= B;
end
B:
if (bvalid) begin
stat <= aw_end ? AR : AW;
end
AR:
if (arready) begin
stat <= R;
end
R:
if (rvalid) begin
araddr <= araddr_next[A_WIDTH-1:0];
if (rlast) begin
stat <= AR;
if (araddr_next[A_WIDTH_TEST]) araddr <= 0;
end
end
endcase
end
// ------------------------------------------------------------
// read and write mismatch detect
// ------------------------------------------------------------
wire [D_WIDTH-1:0] rdata_idle = araddr;
always @(posedge clk or negedge rstn)
if (~rstn) begin
error <= 1'b0;
error_cnt <= 16'd0;
end else begin
error <= rvalid && rready && rdata != rdata_idle;
if (error) error_cnt <= error_cnt + 16'd1;
end
endmodule
| 7.509651 |
module axi_serializer #(
parameter WIDTH = 32
) (
input clk,
input rst,
input reverse_input,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output reg i_tready,
output reg o_tdata,
output reg o_tlast,
output reg o_tvalid,
input o_tready
);
reg i_tlast_latch;
reg [WIDTH-1:0] serial_data_reg;
reg [$clog2(WIDTH)-1:0] serial_cnt;
reg serializing;
always @(posedge clk) begin
if (rst) begin
i_tready <= 1'b0;
i_tlast_latch <= 1'b0;
o_tdata <= 1'b0;
o_tlast <= 1'b0;
o_tvalid <= 1'b0;
serial_data_reg <= 'd0;
serializing <= 1'b0;
serial_cnt <= 0;
end else begin
i_tready <= 1'b0;
// Shift out a bit when downstream can consume it
if (serializing & o_tready) begin
o_tvalid <= 1'b1;
if (reverse_input) begin
o_tdata <= serial_data_reg[0];
serial_data_reg[WIDTH-2:0] <= serial_data_reg[WIDTH-1:1];
end else begin
o_tdata <= serial_data_reg[WIDTH-1];
serial_data_reg[WIDTH-1:1] <= serial_data_reg[WIDTH-2:0];
end
if (serial_cnt == WIDTH - 1) begin
serial_cnt <= 0;
serial_data_reg <= i_tdata;
i_tlast_latch <= i_tlast;
o_tlast <= i_tlast_latch;
if (~i_tvalid) begin
serializing <= 1'b0;
end else begin
i_tready <= 1'b1;
end
end else begin
serial_cnt <= serial_cnt + 1;
end
end else if (~serializing) begin
i_tready <= 1'b1;
o_tvalid <= 1'b0;
// Serial shift register (serial_data_reg) is empty, load it
if (i_tvalid) begin
i_tready <= 1'b0;
serializing <= 1'b1;
i_tlast_latch <= i_tlast;
serial_data_reg <= i_tdata;
end
end
end
end
endmodule
| 7.353453 |
module axi_setting_reg #(
parameter ADDR = 0,
parameter USE_ADDR_LAST = 0,
parameter ADDR_LAST = ADDR + 1,
parameter AWIDTH = 8,
parameter WIDTH = 32,
parameter USE_FIFO = 0,
parameter FIFO_SIZE = 5,
parameter DATA_AT_RESET = 0,
parameter VALID_AT_RESET = 0,
parameter LAST_AT_RESET = 0,
parameter STROBE_LAST = 0,
parameter REPEATS = 0,
parameter MSB_ALIGN = 0
) (
input clk,
input reset,
output reg error_stb,
input set_stb,
input [AWIDTH-1:0] set_addr,
input [31:0] set_data,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
reg init;
reg [WIDTH-1:0] o_tdata_int;
reg o_tlast_int, o_tvalid_int;
wire o_tready_int;
always @(posedge clk) begin
if (reset) begin
o_tdata_int <= DATA_AT_RESET;
o_tvalid_int <= VALID_AT_RESET;
o_tlast_int <= LAST_AT_RESET;
init <= 1'b0;
error_stb <= 1'b0;
end else begin
error_stb <= 1'b0;
if (o_tvalid_int & o_tready_int) begin
// Deassert tvalid / tlast only if not repeating the output
if (REPEATS == 0) begin
o_tvalid_int <= 1'b0;
end
if ((REPEATS == 0) | (STROBE_LAST == 1)) begin
o_tlast_int <= 1'b0;
end
end
if (set_stb & ((ADDR[AWIDTH-1:0] == set_addr) | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
init <= 1'b1;
o_tdata_int <= (MSB_ALIGN == 0) ? set_data[WIDTH-1:0] : set_data[31:32-WIDTH];
o_tvalid_int <= 1'b1;
if (set_stb & (STROBE_LAST | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
o_tlast_int <= 1'b1;
end else begin
o_tlast_int <= 1'b0;
end
if (~o_tready_int) begin
error_stb <= 1'b1;
end
end
end
end
generate
if (USE_FIFO) begin
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata({o_tlast_int, o_tdata_int}),
.i_tvalid(o_tvalid_int),
.i_tready(o_tready_int),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
end else begin
assign o_tdata = o_tdata_int;
assign o_tlast = o_tlast_int;
assign o_tvalid = o_tvalid_int;
assign o_tready_int = o_tready;
end
endgenerate
endmodule
| 6.840989 |
module axi_shim (
input user_clk,
// Input AXI4-Lite interface
input t_awvalid,
input [ 31:0] t_awaddr,
input [ 3:0] t_awlen,
input [ 2:0] t_awregion,
input [ 2:0] t_awsize,
output t_awready,
input t_wvalid,
input [127:0] t_wdata,
input [ 15:0] t_wstrb,
input t_wlast,
output t_wready,
output t_bvalid,
input t_bready,
output [ 1:0] t_bresp,
input t_arvalid,
input [ 31:0] t_araddr,
input [ 3:0] t_arlen,
input [ 2:0] t_arregion,
input [ 2:0] t_arsize,
output t_arready,
output t_rvalid,
input t_rready,
output [127:0] t_rdata,
output [ 1:0] t_rresp,
output t_rlast,
// Output AXI4-Lite interface
output s_axi_awvalid,
output [ 31:0] s_axi_awaddr,
input s_axi_awready,
output s_axi_wvalid,
output [ 31:0] s_axi_wdata,
output [ 3:0] s_axi_wstrb,
input s_axi_wready,
input s_axi_bvalid,
output s_axi_bready,
input [ 1:0] s_axi_bresp,
output s_axi_arvalid,
input s_axi_arready,
output [ 31:0] s_axi_araddr,
input s_axi_rvalid,
output s_axi_rready,
input [ 31:0] s_axi_rdata,
input [ 1:0] s_axi_rresp
);
reg [3:0] rd_addr_nibble = 4'd0;
/********* SHIM FOR TARGET AXI to AXI-LITE connection ***********/
//- This shim enabless the 128-bit target AXI master to connect to
//- 32-bit AXILITE interconnect
//- All register operations issued by software are read-modify-write
//- operations i.e. access to all bits of one entire register
/*
In case of writes, it puts the appropriate 32-bit data slice based on
value of wstrb.
wstrb wdata bit locations
---------------------------------
[0] = 1 [31:0]
[4] = 1 [63:32]
[8] = 1 [95:64]
[12] = 1 [127:96]
---------------------------------
In case of reads, it places the 32-bit read data value in the
appropriate segment in the 128-bit read data bus based on the read
address' lowest nibble value.
araddr[3:0] rdata segment
-----------------------------
4'b0000 [31:0]
4'b0100 [63:32]
4'b1000 [95:64]
4'b1100 [127:96]
-----------------------------
*/
assign s_axi_awaddr = {16'd0, t_awaddr[15:0]};
assign s_axi_awvalid = t_awvalid;
assign t_awready = s_axi_awready;
assign s_axi_wvalid = t_wvalid;
//- Extract out valid write data based on strobe
assign s_axi_wdata = t_wstrb[0] ? t_wdata[31:0] :
t_wstrb[4] ? t_wdata[63:32] :
t_wstrb[8] ? t_wdata[95:64] : t_wdata[127:96];
assign s_axi_wstrb = 4'b1111;
assign t_wready = s_axi_wready;
assign t_bvalid = s_axi_bvalid;
assign s_axi_bready = t_bready;
assign t_bresp = s_axi_bresp;
assign s_axi_arvalid = t_arvalid;
assign s_axi_araddr = {16'd0, t_araddr[15:0]};
assign t_arready = s_axi_arready;
assign t_rvalid = s_axi_rvalid;
assign s_axi_rready = t_rready;
//- Latch onto the read address lowest nibble
always @(posedge user_clk) if (s_axi_arvalid & s_axi_arready) rd_addr_nibble <= s_axi_araddr[3:0];
//- Place the read 32-bit data into the appropriate 128-bit rdata
// location based on address nibble latched above
assign t_rdata = (rd_addr_nibble == 4'hC) ? {s_axi_rdata,96'd0} :
(rd_addr_nibble == 4'h8) ? {32'd0,s_axi_rdata,64'd0} :
(rd_addr_nibble == 4'h4) ? {64'd0,s_axi_rdata,32'd0} :
{96'd0,s_axi_rdata};
assign t_rresp = s_axi_rresp;
assign t_rlast = s_axi_rvalid;
endmodule
| 7.959267 |
module axi_sim_sim_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET sync_rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN axi_sim_sim_clk_gen_0_0_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME sync_rst, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sync_rst RST" *)
output wire sync_rst;
sim_clk_gen #(
.CLOCK_PERIOD(10),
.INITIAL_RESET_CLOCK_CYCLES(500),
.RESET_POLARITY(0)
) inst (
.clk(clk),
.clk_n(),
.clk_p(),
.sync_rst(sync_rst)
);
endmodule
| 7.09873 |
module axi_sink #(
parameter WIDTH = 24, // Must be 8x
parameter SIZE = 128,
parameter AXI = 64 // Must be 32 or 64
) (
input clk_i,
input rst_ni,
input srst_i,
input en_i,
input aval_i,
input [31:0] addr_i,
input val_i,
input [WIDTH-1:0] data_i,
input m_axi_awready,
input m_axi_bvalid,
input m_axi_wready,
input [1:0] m_axi_bresp,
input [5:0] m_axi_bid,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_wlast,
output m_axi_wvalid,
output [1:0] m_axi_awburst,
output [1:0] m_axi_awlock,
output [2:0] m_axi_awsize,
output [2:0] m_axi_awprot,
output [31:0] m_axi_awaddr,
output [AXI-1:0] m_axi_wdata,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [3:0] m_axi_awqos,
output [AXI/8-1:0] m_axi_wstrb,
output [5:0] m_axi_awid,
output [5:0] m_axi_wid
);
localparam TRANS = 16;
localparam BATCH = AXI * TRANS;
localparam NBATCH = (WIDTH * SIZE + BATCH - 1) / BATCH;
// data_i -> repacker -> fifo -> | -> M_AXI_W
wire wfval, wfrdy;
wire [AXI-1:0] wfdata;
repacker #(
.IN (WIDTH / 8),
.OUT(AXI / 8)
) i_wpacker (
.clk_i(clk_i),
.rst_ni(rst_ni),
.srst_i(aval_i),
.in_val_i(val_i),
.in_data_i(data_i),
.in_rdy_o(),
.out_val_o(wfval),
.out_data_o(wfdata),
.out_rdy_i(wfrdy)
);
wire fifo_valid;
reg wde2;
wire [AXI-1:0] wd2;
fifo #(
.WIDTH(AXI),
.BURST(TRANS - 1)
) i_wfifo (
.clk_i(clk_i),
.srst_i(srst_i),
.en_i(~aval_i),
.in_val_i(wfval),
.in_data_i(wfdata),
.in_rdy_o(wfrdy),
.out_val_o(fifo_valid),
.out_data_o(wd2),
.out_rdy_i(wde2)
);
reg awval, wemit;
reg [31:0] waddr, wladdr;
reg wglast;
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
waddr <= 0;
wladdr <= 0;
wglast <= 0;
end else if (aval_i) begin
waddr <= addr_i;
wladdr <= addr_i + (NBATCH - 1) * TRANS * AXI / 8;
wglast <= 0;
end else if (awval && m_axi_awready) begin
waddr <= waddr + TRANS * AXI / 8;
wglast <= waddr == wladdr;
end
end
always @(*) begin
wde2 = 0;
if (aval_i) begin
wde2 = 0;
end else if ((~m_axi_wvalid || m_axi_wlast) && fifo_valid && ~wglast && en_i) begin
wde2 = 1;
end else if (m_axi_wvalid && m_axi_wready && ~m_axi_wlast) begin
wde2 = 1;
end
end
reg [AXI-1:0] wbuff;
reg [3:0] wcnt;
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
awval <= 0;
wemit <= 0;
wcnt <= 0;
wbuff <= 0;
end else if (aval_i) begin
awval <= 0;
wemit <= 0;
wcnt <= 0;
end else if (awval && m_axi_awready) begin
awval <= 0;
wcnt <= 0;
if (wemit) begin
wcnt <= wcnt + 1;
wbuff <= wd2;
end
end else if ((~wemit || &wcnt) && fifo_valid && ~wglast && en_i) begin
awval <= 1;
wemit <= 1;
wcnt <= 0;
wbuff <= wd2;
end else if (wemit && m_axi_wready && m_axi_wlast) begin
wemit <= 0;
wcnt <= 0;
wbuff <= wd2;
end else if (wemit && m_axi_wready) begin
wcnt <= wcnt + 1;
wbuff <= wd2;
end
end
assign m_axi_awvalid = awval;
assign m_axi_awburst = 2'b01; // INCR
assign m_axi_awlock = 0;
assign m_axi_awsize = $clog2(AXI / 8); // 4/8 bytes each transfer
assign m_axi_awprot = 0;
assign m_axi_awaddr = waddr;
assign m_axi_awcache = 0;
assign m_axi_awlen = TRANS - 1;
assign m_axi_awqos = 0;
assign m_axi_awid = 0;
assign m_axi_wlast = &wcnt;
assign m_axi_wvalid = wemit;
assign m_axi_wdata = wbuff;
assign m_axi_wstrb = {(AXI / 8) {1'b1}};
assign m_axi_wid = 0;
assign m_axi_bready = 1;
endmodule
| 7.721135 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_slave #(
parameter DATA_WIDTH = 32,
parameter ACCEPTANCE = 3,
parameter MIN_LATENCY = 16,
parameter MAX_LATENCY = 32
) (
input clk,
input reset,
input valid,
output ready,
input [31:0] addr,
input [7:0] len,
input [2:0] size,
input [1:0] burst,
input [2:0] prot,
input [3:0] cache,
output beat_stb,
input beat_ack,
output [31:0] beat_addr,
output beat_last
);
reg [31:0] timestamp = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
timestamp <= 'h00;
end else begin
timestamp <= timestamp + 1'b1;
end
end
reg [32+32+8-1:0] req_fifo[0:15];
reg [3:0] req_fifo_rd = 'h00;
reg [3:0] req_fifo_wr = 'h00;
wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
assign ready = req_fifo_level < ACCEPTANCE;
always @(posedge clk) begin
if (reset == 1'b1) begin
req_fifo_wr <= 'h00;
end else begin
if (valid == 1'b1 && ready == 1'b1) begin
req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
req_fifo[req_fifo_wr][39:0] <= {addr,len};
req_fifo_wr <= req_fifo_wr + 1'b1;
end
end
end
reg [7:0] beat_counter = 'h00;
assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= 'h00;
end else begin
if (beat_ack == 1'b1) begin
if (beat_last == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= req_fifo_rd + 1'b1;
end else begin
beat_counter <= beat_counter + 1'b1;
end
end
end
end
endmodule
| 8.180735 |
module PREFIX_addr_gen (
PORTS
);
input clk;
input reset;
input [ADDR_BITS-1:0] cmd_addr;
input [SIZE_BITS-1:0] cmd_size;
input advance;
input restart;
output [ADDR_BITS-1:0] ADDR;
reg [ADDR_BITS-1:0] offset;
wire [ 3:0] size_bytes;
assign size_bytes =
cmd_size == 2'b00 ? 4'd1 :
cmd_size == 2'b01 ? 4'd2 :
cmd_size == 2'b10 ? 4'd4 :
cmd_size == 2'b11 ? 4'd8 : 4'd0;
always @(posedge clk or posedge reset)
if (reset) offset <= #FFD{ADDR_BITS{1'b0}};
else if (restart) offset <= #FFD{ADDR_BITS{1'b0}};
else if (advance) offset <= #FFD offset + size_bytes;
assign ADDR = cmd_addr + offset;
endmodule
| 6.989261 |
module axi_slave_bfm ( /*AUTOARG*/
// Outputs
awready,
wready,
bid,
bresp,
bvalid,
arready,
rid,
rdata,
rresp,
rlast,
rvalid,
// Inputs
aclk,
aresetn,
awid,
awadr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
wid,
wrdata,
wstrb,
wlast,
wvalid,
bready,
arid,
araddr,
arlen,
arsize,
arlock,
arcache,
arprot,
arvalid,
rready
);
//
// Global Signals
//
input wire aclk;
input wire aresetn; //Active LOW
//
// Write Address Channel
//
input wire [3:0] awid; // Address Write ID
input wire [31:0] awadr; // Write Address
input wire [3:0] awlen; // Burst Length
input wire [2:0] awsize; // Burst Size
input wire [1:0] awburst; // Burst Type
input wire [1:0] awlock; // Lock Type
input wire [3:0] awcache; // Cache Type
input wire [2:0] awprot; // Protection Type
input wire awvalid; // Write Address Valid
output reg awready; // Write Address Ready
//
// Write Data Channel
//
input wire [3:0] wid; // Write ID
input wire [31:0] wrdata; // Write Data
input wire [3:0] wstrb; // Write Strobes
input wire wlast; // Write Last
input wire wvalid; // Write Valid
output reg wready; // Write Ready
//
// Write Response CHannel
//
output reg [3:0] bid; // Response ID
output reg [1:0] bresp; // Write Response
output reg bvalid; // Write Response Valid
input wire bready; // Response Ready
//
// Read Address Channel
//
input wire [3:0] arid; // Read Address ID
input wire [31:0] araddr; // Read Address
input wire [3:0] arlen; // Burst Length
input wire [2:0] arsize; // Burst Size
input wire [1:0] arlock; // Lock Type
input wire [3:0] arcache; // Cache Type
input wire [2:0] arprot; // Protection Type
input wire arvalid; // Read Address Valid
output reg arready; // Read Address Ready
output reg [3:0] rid; // Read ID
output reg [31:0] rdata; // Read Data
output reg [1:0] rresp; // Read Response
output reg rlast; // Read Last
output reg rvalid; // Read Valid
input wire rready; // Read Ready
endmodule
| 7.441535 |
module PREFIX_busy(PORTS);
CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
`include "prgen_rand.v"
input clk;
input reset;
output ARBUSY;
output RBUSY;
output AWBUSY;
output WBUSY;
output BBUSY;
reg stall_enable = 1;
integer burst_chance = 1;
integer burst_len = 10;
integer burst_val = 90;
integer ar_stall_chance = 10;
integer r_stall_chance = 10;
integer aw_stall_chance = 10;
integer w_stall_chance = 10;
integer b_stall_chance = 10;
integer burst_type;
reg burst_stall;
integer ar_stall_chance_valid;
integer r_stall_chance_valid;
integer aw_stall_chance_valid;
integer w_stall_chance_valid;
integer b_stall_chance_valid;
reg ARBUSY_pre = 0;
reg RBUSY_pre = 0;
reg AWBUSY_pre = 0;
reg WBUSY_pre = 0;
reg BBUSY_pre = 0;
reg ARBUSY;
reg RBUSY;
reg AWBUSY;
reg WBUSY;
reg BBUSY;
task set_stall;
reg stall;
begin
ar_stall_chance_valid = ar_stall_chance;
r_stall_chance_valid = r_stall_chance;
aw_stall_chance_valid = aw_stall_chance;
w_stall_chance_valid = w_stall_chance;
b_stall_chance_valid = b_stall_chance;
end
endtask
initial
begin
#FFD;
set_stall;
if (burst_chance > 0)
forever
begin
burst_stall = rand_chance(burst_chance);
if (burst_stall)
begin
#FFD;
burst_type = rand(1, 5);
case (burst_type)
1 : ar_stall_chance_valid = burst_val;
2 : r_stall_chance_valid = burst_val;
3 : aw_stall_chance_valid = burst_val;
4 : w_stall_chance_valid = burst_val;
5 : b_stall_chance_valid = burst_val;
endcase
repeat (burst_len) @(posedge clk);
set_stall;
end
else
begin
@(posedge clk);
end
end
end
always @(posedge clk)
begin
#FFD;
ARBUSY_pre = rand_chance(ar_stall_chance_valid);
RBUSY_pre = rand_chance(r_stall_chance_valid);
AWBUSY_pre = rand_chance(aw_stall_chance_valid);
WBUSY_pre = rand_chance(w_stall_chance_valid);
BBUSY_pre = rand_chance(b_stall_chance_valid);
end
always @(posedge clk or posedge reset)
if (reset)
begin
ARBUSY <= #FFD 1'b0;
RBUSY <= #FFD 1'b0;
AWBUSY <= #FFD 1'b0;
WBUSY <= #FFD 1'b0;
BBUSY <= #FFD 1'b0;
end
else if (stall_enable)
begin
ARBUSY <= #FFD ARBUSY_pre;
RBUSY <= #FFD RBUSY_pre;
AWBUSY <= #FFD AWBUSY_pre;
WBUSY <= #FFD WBUSY_pre;
BBUSY <= #FFD BBUSY_pre;
end
else
begin
ARBUSY <= #FFD 1'b0;
RBUSY <= #FFD 1'b0;
AWBUSY <= #FFD 1'b0;
WBUSY <= #FFD 1'b0;
BBUSY <= #FFD 1'b0;
end
endmodule
| 6.837044 |
module PREFIX_cmd_fifo (PORTS);
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
input clk;
input reset;
input [ADDR_BITS-1:0] AADDR;
input [ID_BITS-1:0] AID;
input [SIZE_BITS-1:0] ASIZE;
input [LEN_BITS-1:0] ALEN;
input AVALID;
input AREADY;
input VALID;
input READY;
input LAST;
output [ADDR_BITS-1:0] cmd_addr;
output [ID_BITS-1:0] cmd_id;
output [SIZE_BITS-1:0] cmd_size;
output [LEN_BITS-1:0] cmd_len;
output [1:0] cmd_resp;
output cmd_timeout;
output cmd_ready;
output cmd_empty;
output cmd_full;
wire push;
wire pop;
wire empty;
wire full;
wire [DEPTH_BITS:0] fullness;
wire [1:0] resp_in;
wire timeout_in;
wire timeout_out;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
assign resp_in =
push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
assign timeout_in = push & (TIMEOUT_addr == AADDR);
assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
assign cmd_full = full | (DEPTH == fullness);
assign cmd_empty = empty;
assign cmd_ready = ~empty;
assign push = AVALID & AREADY;
assign pop = VALID & READY & LAST;
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+SIZE_BITS+LEN_BITS+2+1, DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({AADDR,
AID,
ASIZE,
ALEN,
resp_in,
timeout_in
}
),
.dout({cmd_addr,
cmd_id,
cmd_size,
cmd_len,
cmd_resp,
timeout_out
}
),
.fullness(fullness),
.empty(empty),
.full(full)
);
endmodule
| 7.517693 |
module axi_slave_connect_example
*/
module axi_slave_connect_example (
output ariane_axi::req_t dm_axi_s_req,
input ariane_axi::resp_t dm_axi_s_resp,
input ariane_axi::req_t dm_axi_m_req,
output ariane_axi::resp_t dm_axi_m_resp
);
localparam AxiAddrWidth = 64;
localparam AxiDataWidth = 64;
localparam AxiIdWidthMaster = 4;
localparam AxiIdWidthSlaves = 4;
localparam AxiUserWidth = 1;
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMaster ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master();
axi_master_connect i_axi_master_dm (.axi_req_i(dm_axi_m_req), .axi_resp_o(dm_axi_m_resp), .master(slave));
axi_slave_connect i_axi_slave_dm (.axi_req_o(dm_axi_s_req), .axi_resp_i(dm_axi_s_resp), .slave(master));
endmodule
| 8.842413 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
reg [ DATA_BITS-1:0] DOUT;
wire [ DATA_BITS-1:0] BitSEL;
wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
assign BitSEL = {CONCAT({8{BSEL[BX]}},)};
always @(posedge clk)
if (WR)
Mem[ADDR_WR_word] <= #FFD(Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
always @(posedge clk or posedge reset)
if (reset) DOUT <= #FFD{DATA_BITS{1'b0}};
else if (RD) DOUT <= #FFD Mem[ADDR_RD_word];
endmodule
| 6.889752 |
module axi_slave_mux #(
parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
parameter DST_WIDTH = 16, // Width of DST field we are routing on.
parameter NUM_INPUTS = 2 // number of input AXI buses
) (
input clk,
input reset,
input clear,
// Inputs
input [(FIFO_WIDTH*NUM_INPUTS)-1:0] i_tdata,
input [ NUM_INPUTS-1:0] i_tvalid,
input [ NUM_INPUTS-1:0] i_tlast,
output [ NUM_INPUTS-1:0] i_tready,
// Forwarding Flags
input [ NUM_INPUTS-1:0] forward_valid,
output reg [ NUM_INPUTS-1:0] forward_ack,
// Output
output [ FIFO_WIDTH-1:0] o_tdata,
output o_tvalid,
output o_tlast,
input o_tready
);
wire [ FIFO_WIDTH-1:0] i_tdata_array[0:NUM_INPUTS-1];
reg [`LOG2(NUM_INPUTS):0] select;
reg enable;
reg state;
localparam CHECK_THIS_INPUT = 0;
localparam WAIT_LAST = 1;
always @(posedge clk)
if (reset | clear) begin
state <= CHECK_THIS_INPUT;
select <= 0;
enable <= 0;
forward_ack <= 0;
end else begin
case (state)
// Is the currently selected input addressing this slave with a ready packet?
CHECK_THIS_INPUT: begin
if (forward_valid[select]) begin
enable <= 1;
forward_ack[select] <= 1;
state <= WAIT_LAST;
end else if (select == NUM_INPUTS - 1) begin
select <= 0;
end else begin
select <= select + 1;
end
end
// Assert ACK immediately to forwarding logic and then wait for end of packet.
WAIT_LAST: begin
if (i_tlast[select] && i_tvalid[select] && o_tready) begin
if (select == NUM_INPUTS - 1) begin
select <= 0;
end else begin
select <= select + 1;
end
state <= CHECK_THIS_INPUT;
forward_ack <= 0;
enable <= 0;
end else begin
forward_ack[select] <= 1;
enable <= 1;
end
end
endcase // case(state)
end
//
// Combinatorial mux
//
genvar m;
generate
for (m = 0; m < NUM_INPUTS; m = m + 1) begin : form_buses
assign i_tdata_array[m] = i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH];
end
endgenerate
assign o_tdata = i_tdata_array[select];
assign o_tvalid = enable && i_tvalid[select];
assign o_tlast = enable && i_tlast[select];
// assign i_tready = {NUM_INPUTS{o_tready}} & (enable << select);
generate
for (m = 0; m < NUM_INPUTS; m = m + 1) begin : form_ready
assign i_tready[m] = o_tready && enable && (select == m);
end
endgenerate
endmodule
| 6.595203 |
module axi_slave_stub (
output S2M_AXI_ACLK,
// Read interface
input S2M_AXI_ARVALID,
output S2M_AXI_ARREADY,
input [31:0] S2M_AXI_ARADDR,
input [11:0] S2M_AXI_ARID,
output S2M_AXI_RVALID,
input S2M_AXI_RREADY,
output S2M_AXI_RLAST,
output [31:0] S2M_AXI_RDATA,
output [11:0] S2M_AXI_RID,
output [1:0] S2M_AXI_RRESP,
//write interface
input S2M_AXI_AWVALID,
output S2M_AXI_AWREADY,
input [31:0] S2M_AXI_AWADDR,
input [11:0] S2M_AXI_AWID,
input S2M_AXI_WVALID,
output S2M_AXI_WREADY,
input [31:0] S2M_AXI_WDATA,
input [3:0] S2M_AXI_WSTRB,
output S2M_AXI_BVALID,
input S2M_AXI_BREADY,
output [1:0] S2M_AXI_BRESP,
output [11:0] S2M_AXI_BID
);
assign S2M_AXI_ACLK = 1'b0;
// Read interface
assign S2M_AXI_ARREADY = 1'b0;
assign S2M_AXI_RVALID = 1'b0;
assign S2M_AXI_RLAST = 1'b0;
assign S2M_AXI_RDATA = 32'b0;
assign S2M_AXI_RID = 12'b0;
assign S2M_AXI_RRESP = 2'b0;
//write interface
assign S2M_AXI_AWREADY = 1'b0;
assign S2M_AXI_WREADY = 1'b0;
assign S2M_AXI_BVALID = 1'b0;
assign S2M_AXI_BRESP = 2'b0;
assign S2M_AXI_BID = 12'b0;
endmodule
| 6.631391 |
module axi_slave_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
) (
// Users to add ports here
// Passthrough signals
output wire S_AXI_ACLK,
output wire S_AXI_ARESETN,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
output wire [2 : 0] S_AXI_AWPROT,
output wire S_AXI_AWVALID,
input wire S_AXI_AWREADY,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
output wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
output wire S_AXI_WVALID,
input wire S_AXI_WREADY,
input wire [1 : 0] S_AXI_BRESP,
input wire S_AXI_BVALID,
output wire S_AXI_BREADY,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
output wire [2 : 0] S_AXI_ARPROT,
output wire S_AXI_ARVALID,
input wire S_AXI_ARREADY,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
input wire [1 : 0] S_AXI_RRESP,
input wire S_AXI_RVALID,
output wire S_AXI_RREADY,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Add user logic here
assign S_AXI_ACLK = s00_axi_aclk;
assign S_AXI_ARESETN = s00_axi_aresetn;
assign S_AXI_AWADDR = s00_axi_awaddr;
assign S_AXI_AWPROT = s00_axi_awprot;
assign S_AXI_AWVALID = s00_axi_awvalid;
assign s00_axi_awready = S_AXI_AWREADY;
assign S_AXI_WDATA = s00_axi_wdata;
assign S_AXI_WSTRB = s00_axi_wstrb;
assign S_AXI_WVALID = s00_axi_wvalid;
assign s00_axi_wready = S_AXI_WREADY;
assign s00_axi_bresp = S_AXI_BRESP;
assign s00_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s00_axi_bready;
assign S_AXI_ARADDR = s00_axi_araddr;
assign S_AXI_ARPROT = s00_axi_arprot;
assign S_AXI_ARVALID = s00_axi_arvalid;
assign s00_axi_arready = S_AXI_ARREADY;
assign s00_axi_rdata = S_AXI_RDATA;
assign s00_axi_rresp = S_AXI_RRESP;
assign s00_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s00_axi_rready;
// User logic ends
endmodule
| 6.957782 |
module PREFIX_wresp_fifo (
PORTS
);
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
input clk;
input reset;
input AWVALID;
input AWREADY;
input [ADDR_BITS-1:0] AWADDR;
input WVALID;
input WREADY;
input [ID_BITS-1:0] WID;
input WLAST;
output [ID_BITS-1:0] BID;
output [1:0] BRESP;
input BVALID;
input BREADY;
output empty;
output pending;
output timeout;
wire timeout_in;
wire timeout_out;
wire [ 1:0] resp_in;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
wire push;
wire push1;
wire pop;
wire empty;
wire full;
wire [ DEPTH_BITS:0] fullness;
reg pending;
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
assign resp_in =
push1 & (SLVERR_addr == AWADDR) ? RESP_SLVERR :
push1 & (DECERR_addr == AWADDR) ? RESP_DECERR : 2'b00;
assign timeout_in = push1 & (TIMEOUT_addr == AWADDR);
assign timeout = timeout_out & (TIMEOUT_addr != 0);
always @(posedge clk or posedge reset)
if (reset) pending <= #1 1'b0;
else if (BVALID & BREADY) pending <= #1 1'b0;
else if (BVALID & (~BREADY)) pending <= #1 1'b1;
assign push1 = AWVALID & AWREADY;
assign push = WVALID & WREADY & WLAST;
assign pop = BVALID & BREADY;
prgen_fifo_stub #(ID_BITS, DEPTH) wresp_fifo (
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({WID}),
.dout({BID}),
.fullness(fullness),
.empty(empty),
.full(full)
);
prgen_fifo_stub #(2 + 1, DEPTH * 2) wresp_fifo1 (
.clk(clk),
.reset(reset),
.push(push1),
.pop(pop),
.din({resp_in, timeout_in}),
.dout({BRESP, timeout_out}),
.fullness(),
.empty(),
.full()
);
endmodule
| 6.848803 |
module axi_source #(
parameter WIDTH = 24, // Must be 8x
parameter SIZE = 128,
parameter AXI = 64 // Must be 32 or 64
) (
input clk_i,
input rst_ni,
input srst_i,
input en_i,
input aval_i,
input [31:0] addr_i,
input rdy_i,
output [WIDTH-1:0] data_o,
input m_axi_arready,
input m_axi_rlast,
input m_axi_rvalid,
input [1:0] m_axi_rresp,
input [AXI-1:0] m_axi_rdata,
input [5:0] m_axi_rid,
output m_axi_arvalid,
output m_axi_rready,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [2:0] m_axi_arsize,
output [2:0] m_axi_arprot,
output [31:0] m_axi_araddr,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [3:0] m_axi_arqos,
output [5:0] m_axi_arid
);
localparam TRANS = 16;
localparam BATCH = AXI * TRANS;
localparam NBATCH = (WIDTH * SIZE + BATCH - 1) / BATCH;
// M_AXI_R -> fifo -> repacker -> fifo -> data_o
wire rfval1, rfrdy1;
wire [AXI-1:0] rfdata1;
fifo #(
.WIDTH(AXI)
) i_rfifo1 (
.clk_i(clk_i),
.srst_i(srst_i),
.en_i(~aval_i),
.in_val_i(m_axi_rvalid),
.in_data_i(m_axi_rdata),
.in_rdy_o(m_axi_rready),
.out_val_o(rfval1),
.out_data_o(rfdata1),
.out_rdy_i(rfrdy1)
);
wire rfval2, rfrdy2;
wire [WIDTH-1:0] rfdata2;
repacker #(
.IN (AXI / 8),
.OUT(WIDTH / 8)
) i_rpacker (
.clk_i(clk_i),
.rst_ni(rst_ni),
.srst_i(aval_i),
.in_val_i(rfval1),
.in_data_i(rfdata1),
.in_rdy_o(rfrdy1),
.out_val_o(rfval2),
.out_data_o(rfdata2),
.out_rdy_i(rfrdy2)
);
fifo #(
.WIDTH(WIDTH)
) i_rfifo2 (
.clk_i(clk_i),
.srst_i(srst_i),
.en_i(~aval_i),
.in_val_i(rfval2),
.in_data_i(rfdata2),
.in_rdy_o(rfrdy2),
.out_val_o(),
.out_data_o(data_o),
.out_rdy_i(rdy_i)
);
reg arval;
reg [31:0] raddr, rladdr;
wire rglast = raddr == rladdr;
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
raddr <= 0;
rladdr <= 0;
end else if (aval_i) begin
raddr <= addr_i;
rladdr <= addr_i + (NBATCH - 1) * TRANS * AXI / 8;
end else if (arval && m_axi_arready) begin
raddr <= raddr + TRANS * AXI / 8;
end
end
reg aval_r;
always @(posedge clk_i) begin
aval_r <= aval_i;
end
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
arval <= 0;
end else if (aval_i) begin
arval <= 0;
end else if (aval_r && en_i) begin
arval <= 1;
end else if (arval && m_axi_arready) begin
arval <= ~rglast && en_i;
end
end
assign m_axi_arvalid = arval;
assign m_axi_arburst = 2'b01; // INCR
assign m_axi_arlock = 0;
assign m_axi_arsize = $clog2(AXI / 8); // 4/8 bytes each transfer
assign m_axi_arprot = 0;
assign m_axi_araddr = raddr;
assign m_axi_arcache = 0;
assign m_axi_arlen = TRANS - 1;
assign m_axi_arqos = 0;
assign m_axi_arid = 0;
// assign m_axi_rready;
endmodule
| 8.247999 |
module AXI_SP32B1024 (
input CLK,
input RST,
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [ 3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [ 4-1:0] axi_wstrb,
output axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [ 3-1:0] axi_arprot,
output axi_rvalid,
input axi_rready,
output [32-1:0] axi_rdata,
// Memory Interface
input [31:0] Q,
output reg CEN,
output reg WEN,
output reg [9:0] A,
output [31:0] D
);
// The address capturing is a single operation, we can handle this always 1
assign axi_awready = 1'b1;
assign axi_arready = 1'b1;
assign axi_wready = 1'b1;
//reg [9:0] A;
reg [31:0] DP;
//wire [31:0] Q;
assign axi_rdata = Q;
// For memory, we provide the signals in negedge, because the setup and hold sh*t
always @(negedge CLK) begin
if (RST == 1'b0) begin
A <= {10{1'b0}};
DP <= {32{1'b0}};
end else begin
if (axi_awvalid == 1'b1) begin
A <= axi_awaddr[9:0];
end else if (axi_arvalid == 1'b1) begin
A <= axi_araddr[9:0];
end
if (axi_wvalid == 1'b1) begin
DP <= axi_wdata;
end
end
end
// Flags for reading
reg reading1, reading2;
assign axi_rvalid = reading2;
always @(posedge CLK) begin
if (RST == 1'b0) begin
reading1 <= 1'b0;
reading2 <= 1'b0;
end else begin
if (axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading1 <= 1'b0;
end else if (axi_arvalid == 1'b1) begin
reading1 <= 1'b1;
end
if (axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading2 <= 1'b0;
end else if (reading1 == 1'b1) begin
reading2 <= 1'b1;
end
end
end
// Flags for writting
reg writting1, writting2, writting3;
assign axi_bvalid = writting3;
always @(posedge CLK) begin
if (RST == 1'b0) begin
writting1 <= 1'b0;
writting2 <= 1'b0;
writting3 <= 1'b0;
end else begin
if (axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting3 <= 1'b0;
end else if (writting2 == 1'b1) begin
writting3 <= 1'b1;
end else begin
writting3 <= writting3;
end
if (axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting1 <= 1'b0;
end else if (axi_awvalid == 1'b1) begin
writting1 <= 1'b1;
end else begin
writting1 <= writting1;
end
if (axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting2 <= 1'b0;
end else if (axi_wvalid == 1'b1) begin
writting2 <= 1'b1;
end else begin
writting2 <= writting2;
end
end
end
// Control of memory based on Flags
//reg CEN, WEN;
// For memory, we provide the signals in negedge, because the setup and hold sh*t
always @(negedge CLK) begin
if (RST == 1'b0) begin
CEN <= 1'b1;
WEN <= 1'b1;
end else begin
CEN <= ~(reading1 | writting1);
WEN <= ~writting2;
end
end
//wire [31:0] D;
assign D[7:0] = axi_wstrb[0] ? DP[7:0] : Q[7:0];
assign D[15:8] = axi_wstrb[1] ? DP[15:8] : Q[15:8];
assign D[23:16] = axi_wstrb[2] ? DP[23:16] : Q[23:16];
assign D[31:24] = axi_wstrb[3] ? DP[31:24] : Q[31:24];
// Thanks god, the memory provides their data in posedge.
/*SP32B1024 THEMEMORY(
.Q(Q),
.CLK(CLK),
.CEN(CEN),
.WEN(WEN),
.A(A),
.D(D)
);*/
endmodule
| 7.578883 |
module AXI_SPLIT #(
parameter AXIS_TDATA_WIDTH = 32,
parameter N_PORTS = 4 //Number of split ports, max 4, min 2
) (
input clk, //These are here to trick vivado
input rst,
//Slave input
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_DATA_tdata, //Add other AXIS signals when needed
input S_AXIS_DATA_tvalid,
output S_AXIS_DATA_tready,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] M_AXIS_COPY1_tdata,
output wire M_AXIS_COPY1_tvalid,
input wire M_AXIS_COPY1_tready,
output wire [AXIS_TDATA_WIDTH-1:0] M_AXIS_COPY2_tdata,
output wire M_AXIS_COPY2_tvalid,
input wire M_AXIS_COPY2_tready,
output wire [AXIS_TDATA_WIDTH-1:0] M_AXIS_COPY3_tdata,
output wire M_AXIS_COPY3_tvalid,
input wire M_AXIS_COPY3_tready,
output wire [AXIS_TDATA_WIDTH-1:0] M_AXIS_COPY4_tdata,
output wire M_AXIS_COPY4_tvalid,
input wire M_AXIS_COPY4_tready
);
generate //Unsure if generate will reduce logic footprint by much as ports are still declared
case (N_PORTS)
2: begin
assign M_AXIS_COPY1_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY1_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY2_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY2_tvalid = S_AXIS_DATA_tvalid;
assign S_AXIS_DATA_tready = M_AXIS_COPY1_tready || M_AXIS_COPY2_tready; //Ambiguity in tready, could alternatively AND the tready signals, but the handshake should prevent unready sources from receiving data
end
3: begin
assign M_AXIS_COPY1_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY1_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY2_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY2_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY3_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY3_tvalid = S_AXIS_DATA_tvalid;
assign S_AXIS_DATA_tready = M_AXIS_COPY1_tready || M_AXIS_COPY2_tready || M_AXIS_COPY3_tready;
end
4: begin
assign M_AXIS_COPY1_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY1_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY2_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY2_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY3_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY3_tvalid = S_AXIS_DATA_tvalid;
assign M_AXIS_COPY4_tdata = S_AXIS_DATA_tdata;
assign M_AXIS_COPY4_tvalid = S_AXIS_DATA_tvalid;
assign S_AXIS_DATA_tready = M_AXIS_COPY1_tready || M_AXIS_COPY2_tready || M_AXIS_COPY3_tready || M_AXIS_COPY4_tready;
end
endcase
endgenerate
endmodule
| 8.261344 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: AXI-stream upsizing or downsizing,
// see AMBA 4 AXI4-stream Protocol Version: 1.0 Specification -> 2.3.3 -> downsizing considerations
//--------------------------------------------------------------------------------------------------------
module axi_stream_downsizing #(
parameter IEW = 0, // input width, 0=1Byte, 1=2Byte, 2=4Byte, 3=8Bytes, 4=16Bytes, ...
parameter OEW = 0 // output width, 0=1Byte, 1=2Byte, 2=4Byte, 3=8Bytes, 4=16Bytes, ...
// OEW must < IEW
) (
input wire rstn,
input wire clk,
// AXI-stream slave
output wire i_tready,
input wire i_tvalid,
input wire [(8<<IEW)-1:0] i_tdata,
input wire [(1<<IEW)-1:0] i_tkeep,
input wire i_tlast,
// AXI-stream master
input wire o_tready,
output wire o_tvalid,
output wire [(8<<OEW)-1:0] o_tdata,
output wire [(1<<OEW)-1:0] o_tkeep,
output wire o_tlast
);
reg [(8<<IEW)-1:0] tmp_data = {(8<<IEW){1'b0}};
reg [(1<<IEW)-1:0] tmp_keep = {(1<<IEW){1'b0}};
reg tmp_last = 1'b0;
wire [(8<<IEW)-1:0] tmp_data_next;
wire [(1<<IEW)-1:0] tmp_keep_next;
assign {tmp_data_next, o_tdata} = {{(8<<OEW){1'b0}}, tmp_data};
assign {tmp_keep_next, o_tkeep} = {{(1<<OEW){1'b0}}, tmp_keep};
assign o_tlast = ( tmp_keep_next == {(1<<IEW){1'b0}} ) ? tmp_last : 1'b0;
assign o_tvalid = (|o_tkeep);
assign i_tready = ( tmp_keep == {(1<<IEW){1'b0}} ) ? 1'b1 :
( tmp_keep_next == {(1<<IEW){1'b0}} ) ? o_tready :
1'b0 ;
always @ (posedge clk or negedge rstn)
if (~rstn) begin
tmp_data <= {(8<<IEW){1'b0}};
tmp_keep <= {(1<<IEW){1'b0}};
tmp_last <= 1'b0;
end else begin
if ( tmp_keep == {(1<<IEW){1'b0}} ) begin // no data in tmp
// i_tready = 1
if (i_tvalid) begin
tmp_data <= i_tdata;
tmp_keep <= i_tkeep;
tmp_last <= i_tlast;
end
end else if ( tmp_keep_next == {(1<<IEW){1'b0}} ) begin // only one data in tmp
if (o_tready) begin
// i_tready = 1
if (i_tvalid) begin
tmp_data <= i_tdata;
tmp_keep <= i_tkeep;
tmp_last <= i_tlast;
end else begin
tmp_data <= tmp_data_next;
tmp_keep <= tmp_keep_next;
end
end
end else if (o_tready | ~o_tvalid) begin
tmp_data <= tmp_data_next;
tmp_keep <= tmp_keep_next;
end
end
endmodule
| 9.286837 |
module axi_stream_ingress_demo #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8)
) (
input clk,
input rst,
//Write Data Channel
input i_tvalid,
output reg o_tready,
input [DATA_WIDTH - 1:0] i_tdata,
input [STROBE_WIDTH - 1:0] i_tstrb,
input [STROBE_WIDTH - 1:0] i_tkeep,
input i_tlast,
input [ 3:0] i_tuser,
input [ 3:0] i_tid,
input [ 31:0] i_tdest
);
//local parameters
localparam IDLE = 4'h0;
localparam RECEIVE_WRITE_DATA = 4'h1;
//Address Map
localparam ADDR_CONTROL = 0;
localparam ADDR_STATUS = 1;
//registes/wires
reg [ 3:0] state;
reg [ADDR_WIDTH - 1:0] address;
reg [DATA_WIDTH - 1:0] control;
reg [DATA_WIDTH - 1:0] status;
//submodules
//asynchronous logic
//synchronous logic
always @(posedge clk) begin
//Deassert Strobes
if (rst) begin
o_tready <= 0;
//Demo values
control <= 0;
status <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
o_tready <= 1;
//Only handle read or write at one time, not both
if (i_tvalid) begin
state <= RECEIVE_WRITE_DATA;
$display("Dest: %h", i_tdest);
$display("User: %h", i_tuser);
$display("ID: %h", i_tid);
$display("Data: 0x%08X", i_tdata);
end
end
RECEIVE_WRITE_DATA: begin
if (!i_tvalid) begin
state <= IDLE;
o_tready <= 0;
end else begin
$display("Data: 0x%08X", i_tdata);
end
end
default: begin
$display("Shouldn't have gotten here!");
end
endcase
if (i_tlast) begin
$display("Last Signal Strobed");
end
end
end
endmodule
| 7.121741 |
module axi_stream_insert_header #(
parameter DATA_WD = 32,
parameter DATA_BYTE_WD = DATA_WD / 8
) (
input clk,
input rst_n,
// AXI Stream input original data
input valid_in,
input [DATA_WD-1 : 0] data_in,
input [DATA_BYTE_WD-1 : 0] keep_in,
input last_in,
output ready_in,
// AXI Stream output with header inserted
output valid_out,
output [DATA_WD-1 : 0] data_out,
output [DATA_BYTE_WD-1 : 0] keep_out,
output last_out,
input ready_out,
// The header to be inserted to AXI Stream input
input valid_insert,
input [DATA_WD-1 : 0] header_insert,
input [DATA_BYTE_WD-1 : 0] keep_insert,
output ready_insert
);
// Your code here
//store data
reg [ DATA_WD*2-1:0] data_mem;
reg [ DATA_WD-1 : 0] data_out_reg;
reg [DATA_BYTE_WD-1 : 0] keep_out_reg;
integer last_reg = 0;
assign data_out = data_out_reg;
assign keep_out = keep_out_reg;
assign last_out = last_reg;
reg [DATA_WD:0] cnt_one = 'b0;
//calculate 1's number utilizing loop
function [DATA_WD:0] swar;
input [DATA_WD:0] in_data;
reg [DATA_WD:0] width;
begin
for (width = 0; width < DATA_WD; width = width + 1) begin
if (in_data[width]) cnt_one = cnt_one + 1'b1;
else cnt_one = cnt_one;
end
swar = cnt_one;
end
endfunction
// data_mem initial
genvar j;
generate
for (j = 5'd0; j < DATA_WD; j = j + 1) begin
always @(posedge clk or negedge rst_n) begin
data_out_reg[j] <= data_mem[j];
if (!last_in && valid_insert && ready_in && j < swar(keep_insert)) begin
data_mem[j] <= header_insert[j+swar(keep_insert)];
keep_out_reg[j] <= 1;
end else if (!last_in && valid_insert && ready_in && j >= swar(keep_insert)) begin
data_mem[j] <= data_in[j+keep_insert];
keep_out_reg[j] <= 1;
end else if (last_in && valid_insert && ready_in && j < swar(keep_insert)) begin
data_mem[j] <= header_insert[j+swar(keep_insert)];
keep_out_reg[j] <= 0;
last_reg = 1;
end else if (last_in && valid_insert && ready_in && j >= swar(keep_insert)) begin
data_mem[j] <= data_in[j+keep_insert];
keep_out_reg[j] <= 1;
last_reg = 1;
end else data_mem[j] <= data_mem[j];
end
end
endgenerate
endmodule
| 7.121741 |
module implements a simple AXI4 Stream pipeline stage
*/
// `timescale 1ns/1ps
module axi_stream_pipeline
#(
// Pkt AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128
)
(
// Global Ports
input axis_aclk,
input axis_resetn,
// Master Pkt Stream Ports (outgoing pkts)
output reg [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output reg [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output reg [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast,
// Slave Pkt Stream Ports (incomming pkts)
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output reg s_axis_tready,
input s_axis_tlast
);
always @(*) begin
s_axis_tready = m_axis_tready;
end
always @(posedge axis_aclk) begin
if (~axis_resetn) begin
m_axis_tvalid <= 0;
m_axis_tdata <= 0;
m_axis_tkeep <= 0;
m_axis_tuser <= 0;
m_axis_tlast <= 0;
end
else begin
m_axis_tvalid <= (m_axis_tready) ? s_axis_tvalid : m_axis_tvalid;
m_axis_tdata <= (m_axis_tready) ? s_axis_tdata : m_axis_tdata;
m_axis_tkeep <= (m_axis_tready) ? s_axis_tkeep : m_axis_tkeep;
m_axis_tuser <= (m_axis_tready) ? s_axis_tuser : m_axis_tuser;
m_axis_tlast <= (m_axis_tready) ? s_axis_tlast : m_axis_tlast;
end
end
//`ifdef COCOTB_SIM
//initial begin
// $dumpfile("axi_stream_pipeline_waveform.vcd");
// $dumpvars(0,axi_stream_pipeline);
// #1 $display("Sim running...");
//end
//`endif
endmodule
| 6.904081 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: AXI-stream upsizing or downsizing,
// see AMBA 4 AXI4-stream Protocol Version: 1.0 Specification -> 2.3.3 -> downsizing considerations / upsizing considerations
//--------------------------------------------------------------------------------------------------------
module axi_stream_resizing #(
parameter IEW = 0, // input width, 0=1Byte, 1=2Byte, 2=4Byte, 3=8Bytes, 4=16Bytes, ...
parameter OEW = 0 // output width, 0=1Byte, 1=2Byte, 2=4Byte, 3=8Bytes, 4=16Bytes, ...
) (
input wire rstn,
input wire clk,
// AXI-stream slave
output wire i_tready,
input wire i_tvalid,
input wire [(8<<IEW)-1:0] i_tdata,
input wire [(1<<IEW)-1:0] i_tkeep,
input wire i_tlast,
// AXI-stream master
input wire o_tready,
output wire o_tvalid,
output wire [(8<<OEW)-1:0] o_tdata,
output wire [(1<<OEW)-1:0] o_tkeep,
output wire o_tlast
);
generate if (IEW < OEW) begin
axi_stream_upsizing #(
.IEW ( IEW ),
.OEW ( OEW )
) u_axi_stream_upsizing (
.rstn ( rstn ),
.clk ( clk ),
.i_tready ( i_tready ),
.i_tvalid ( i_tvalid ),
.i_tdata ( i_tdata ),
.i_tkeep ( i_tkeep ),
.i_tlast ( i_tlast ),
.o_tready ( o_tready ),
.o_tvalid ( o_tvalid ),
.o_tdata ( o_tdata ),
.o_tkeep ( o_tkeep ),
.o_tlast ( o_tlast )
);
end else if (IEW > OEW) begin
axi_stream_downsizing #(
.IEW ( IEW ),
.OEW ( OEW )
) u_axi_stream_downsizing (
.rstn ( rstn ),
.clk ( clk ),
.i_tready ( i_tready ),
.i_tvalid ( i_tvalid ),
.i_tdata ( i_tdata ),
.i_tkeep ( i_tkeep ),
.i_tlast ( i_tlast ),
.o_tready ( o_tready ),
.o_tvalid ( o_tvalid ),
.o_tdata ( o_tdata ),
.o_tkeep ( o_tkeep ),
.o_tlast ( o_tlast )
);
end else begin // (IEW==OEW)
assign i_tready = o_tready;
assign o_tvalid = i_tvalid;
assign o_tdata = i_tdata;
assign o_tkeep = i_tkeep;
assign o_tlast = i_tlast;
end endgenerate
endmodule
| 9.286837 |
module axi_stream_sample_v1_0_M00_AXIS_A #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
// Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT = 32
) (
// Users to add ports here
input wire AXIS_MASTER_VALID,
output wire AXIS_MASTER_READY,
input wire [C_M_AXIS_TDATA_WIDTH-1 : 0] AXIS_MASTER_DATA_IN,
// User ports ends
// Do not modify the ports beyond this line
// Global ports
input wire M_AXIS_ACLK,
//
input wire M_AXIS_ARESETN,
// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
output wire M_AXIS_TVALID,
// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
// TLAST indicates the boundary of a packet.
output wire M_AXIS_TLAST,
// TREADY indicates that the slave can accept a transfer in the current cycle.
input wire M_AXIS_TREADY
);
// Add user logic here
reg [C_M_AXIS_TDATA_WIDTH-1 : 0] data_in;
reg m_axis_valid;
reg m_axis_valid_1;
reg m_axis_valid_2;
reg m_axis_valid_3;
always @(posedge M_AXIS_ACLK or negedge M_AXIS_ARESETN) begin
if (!M_AXIS_ARESETN) begin
data_in <= 31'b0;
m_axis_valid <= 0;
m_axis_valid_1 <= 0;
m_axis_valid_2 <= 0;
m_axis_valid_3 <= 0;
end else if (AXIS_MASTER_VALID && M_AXIS_TREADY) begin
data_in <= AXIS_MASTER_DATA_IN;
m_axis_valid_1 <= AXIS_MASTER_VALID;
m_axis_valid_2 <= m_axis_valid_1;
m_axis_valid_3 <= m_axis_valid_2;
m_axis_valid <= m_axis_valid_3;
end else begin
data_in <= data_in;
m_axis_valid_1 <= 0;
m_axis_valid_2 <= m_axis_valid_1;
m_axis_valid_3 <= m_axis_valid_2;
m_axis_valid <= m_axis_valid_3;
end
end
assign AXIS_MASTER_READY = M_AXIS_TREADY;
assign M_AXIS_TVALID = m_axis_valid;
assign M_AXIS_TDATA = data_in;
// User logic ends
endmodule
| 8.637001 |
module axi_stream_sample_v1_0_S00_AXIS_A #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
// Users to add ports here
output wire AXIS_SLAVE_VAILD,
input wire AXIS_SLAVE_READY,
output wire [C_S_AXIS_TDATA_WIDTH-1 : 0] AXIS_SLAVE_DATA_OUT,
// User ports ends
// Do not modify the ports beyond this line
// AXI4Stream sink: Clock
input wire S_AXIS_ACLK,
// AXI4Stream sink: Reset
input wire S_AXIS_ARESETN,
// Ready to accept data in
output wire S_AXIS_TREADY,
// Data in
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
// Byte qualifier
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
// Indicates boundary of last packet
input wire S_AXIS_TLAST,
// Data is in valid
input wire S_AXIS_TVALID
);
// Add user logic here
reg [C_S_AXIS_TDATA_WIDTH-1 : 0] data_out;
always @(posedge S_AXIS_ACLK or negedge S_AXIS_ARESETN) begin
if (!S_AXIS_ARESETN) begin
data_out <= 32'b0;
end else if (S_AXIS_TVALID && S_AXIS_TREADY) begin
data_out <= S_AXIS_TDATA;
end
end
assign AXIS_SLAVE_VAILD = S_AXIS_TVALID;
assign S_AXIS_TREADY = AXIS_SLAVE_READY;
assign AXIS_SLAVE_DATA_OUT = data_out;
// User logic ends
endmodule
| 8.637001 |
module axi_sts_register #(
parameter integer STS_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Status bits
input wire [STS_DATA_WIDTH-1:0] sts_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [ 1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [ 1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2(input integer value);
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH / 8 - 1);
localparam integer STS_SIZE = STS_DATA_WIDTH / AXI_DATA_WIDTH;
localparam integer STS_WIDTH = STS_SIZE > 1 ? clogb2(STS_SIZE - 1) : 1;
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
wire [AXI_DATA_WIDTH-1:0] int_data_mux[STS_SIZE-1:0];
genvar j, k;
generate
for (j = 0; j < STS_SIZE; j = j + 1) begin : WORDS
assign int_data_mux[j] = sts_data[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
end
endgenerate
always @(posedge aclk) begin
if (~aresetn) begin
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH) {1'b0}};
end else begin
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @* begin
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if (s_axi_arvalid) begin
int_rvalid_next = 1'b1;
int_rdata_next = int_data_mux[s_axi_araddr[ADDR_LSB+STS_WIDTH-1:ADDR_LSB]];
end
if (s_axi_rready & int_rvalid_reg) begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = 1'b1;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
| 7.475637 |
module axi_arbiter_stom_s3 #(
parameter NUM = 3
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input wire [NUM:0] BREADY
, output wire [NUM:0] BGRANT
//-----------------------------------------------------------
, input wire [NUM:0] RSELECT // selected by comparing trans_id
, input wire [NUM:0] RVALID
, input wire [NUM:0] RREADY
, input wire [NUM:0] RLAST
, output wire [NUM:0] RGRANT
);
//-----------------------------------------------------------
// read-data arbiter
//-----------------------------------------------------------
reg [NUM:0] rgrant_reg;
//-----------------------------------------------------------
localparam STR_RUN = 'h0, STR_WAIT = 'h1;
reg stateR = STR_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end else begin
case (stateR)
STR_RUN: begin
if (|RGRANT) begin
if (~|(RGRANT & RREADY & RLAST)) begin
rgrant_reg <= RGRANT;
stateR <= STR_WAIT;
end
end
end // STR_RUN
STR_WAIT: begin
if (|(RGRANT & RVALID & RREADY & RLAST)) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end
end // STR_WAIT
endcase
end
end
//-----------------------------------------------------------
assign RGRANT = (stateR == STR_RUN) ? priority_sel(RSELECT & RVALID) : rgrant_reg;
//-----------------------------------------------------------
// write-response arbiter
//-----------------------------------------------------------
reg [NUM:0] bgrant_reg;
localparam STB_RUN = 'h0, STB_WAIT = 'h1;
reg stateB = STB_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end else begin
case (stateB)
STB_RUN: begin
if (|BGRANT) begin
if (~|(BGRANT & BREADY)) begin
bgrant_reg <= BGRANT;
stateB <= STB_WAIT;
end
end
end // STB_RUN
STB_WAIT: begin
if (|(BGRANT & BVALID & BREADY)) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end
end // STB_WAIT
endcase
end
end
//-----------------------------------------------------------
assign BGRANT = (stateB == STB_RUN) ? priority_sel(BSELECT & BVALID) : bgrant_reg;
//-----------------------------------------------------------
function [NUM:0] priority_sel;
input [NUM:0] request;
begin
casex (request)
4'bxxx1: priority_sel = 4'h1;
4'bxx10: priority_sel = 4'h2;
4'bx100: priority_sel = 4'h4;
4'b1000: priority_sel = 4'h8;
default: priority_sel = 4'h0;
endcase
end
endfunction
//-----------------------------------------------------------
endmodule
| 7.648984 |
module axi_arbiter_stom_s5 #(
parameter NUM = 5
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input wire [NUM:0] BREADY
, output wire [NUM:0] BGRANT
//-----------------------------------------------------------
, input wire [NUM:0] RSELECT // selected by comparing trans_id
, input wire [NUM:0] RVALID
, input wire [NUM:0] RREADY
, input wire [NUM:0] RLAST
, output wire [NUM:0] RGRANT
);
//-----------------------------------------------------------
// read-data arbiter
//-----------------------------------------------------------
reg [NUM:0] rgrant_reg;
//-----------------------------------------------------------
localparam STR_RUN = 'h0, STR_WAIT = 'h1;
reg stateR = STR_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end else begin
case (stateR)
STR_RUN: begin
if (|RGRANT) begin
if (~|(RGRANT & RREADY & RLAST)) begin
rgrant_reg <= RGRANT;
stateR <= STR_WAIT;
end
end
end // STR_RUN
STR_WAIT: begin
if (|(RGRANT & RVALID & RREADY & RLAST)) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end
end // STR_WAIT
endcase
end
end
//-----------------------------------------------------------
assign RGRANT = (stateR == STR_RUN) ? priority_sel(RSELECT & RVALID) : rgrant_reg;
//-----------------------------------------------------------
// write-response arbiter
//-----------------------------------------------------------
reg [NUM:0] bgrant_reg;
localparam STB_RUN = 'h0, STB_WAIT = 'h1;
reg stateB = STB_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end else begin
case (stateB)
STB_RUN: begin
if (|BGRANT) begin
if (~|(BGRANT & BREADY)) begin
bgrant_reg <= BGRANT;
stateB <= STB_WAIT;
end
end
end // STB_RUN
STB_WAIT: begin
if (|(BGRANT & BVALID & BREADY)) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end
end // STB_WAIT
endcase
end
end
//-----------------------------------------------------------
assign BGRANT = (stateB == STB_RUN) ? priority_sel(BSELECT & BVALID) : bgrant_reg;
//-----------------------------------------------------------
function [NUM:0] priority_sel;
input [NUM:0] request;
begin
casex (request)
6'bxxxxx1: priority_sel = 6'h1;
6'bxxxx10: priority_sel = 6'h2;
6'bxxx100: priority_sel = 6'h4;
6'bxx1000: priority_sel = 6'h8;
6'bx10000: priority_sel = 6'h10;
6'b100000: priority_sel = 6'h20;
default: priority_sel = 6'h0;
endcase
end
endfunction
//-----------------------------------------------------------
endmodule
| 7.648984 |
module axi_sync #(
parameter SIZE = 2,
parameter WIDTH = 32,
parameter [32*SIZE-1:0] WIDTH_VEC = {SIZE{WIDTH[31:0]}},
parameter FIFO_SIZE = 0
) (
input clk,
input reset,
input clear,
input [msb(SIZE,WIDTH_VEC)-1:0] i_tdata,
input [SIZE-1:0] i_tlast,
input [SIZE-1:0] i_tvalid,
output [SIZE-1:0] i_tready,
output [msb(SIZE,WIDTH_VEC)-1:0] o_tdata,
output [SIZE-1:0] o_tlast,
output [SIZE-1:0] o_tvalid,
input [SIZE-1:0] o_tready
);
// Helper function to calculate the MSB index based on widths stored in WIDTH_VEC.
// Note: If n is negative, returns 0
function automatic integer msb(input integer n, input [SIZE*32-1:0] bit_vec);
automatic integer i, total;
begin
total = 0;
if (n >= 0) begin
for (i = 0; i <= n; i = i + 1) begin
total = total + ((bit_vec >> 32 * i) & 32'hFF);
end
end
msb = total;
end
endfunction
wire [msb(SIZE,WIDTH_VEC)-1:0] int_tdata;
wire [SIZE-1:0] int_tlast, int_tvalid, int_tready;
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1) begin
axi_fifo #(
.WIDTH(msb(i, WIDTH_VEC) - msb(i - 1, WIDTH_VEC) + 1),
.SIZE (FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({i_tlast[i], i_tdata[msb(i, WIDTH_VEC)-1:msb(i-1, WIDTH_VEC)]}),
.i_tvalid(i_tvalid[i]),
.i_tready(i_tready[i]),
.o_tdata({int_tlast[i], int_tdata[msb(i, WIDTH_VEC)-1:msb(i-1, WIDTH_VEC)]}),
.o_tvalid(int_tvalid[i]),
.o_tready(int_tready[i]),
.space(),
.occupied()
);
end
endgenerate
assign o_tdata = int_tdata;
assign o_tlast = int_tlast;
wire consume = (&int_tvalid) & (&o_tready);
assign int_tready = {SIZE{consume}};
assign o_tvalid = {SIZE{consume}};
endmodule
| 7.667937 |
module axi_test_vfifo #(
parameter PACKET_SIZE = 128
) (
input aclk,
input aresetn,
input enable,
// AXI Stream Out
output reg out_axis_tvalid,
input out_axis_tready,
output [63 : 0] out_axis_tdata,
output reg [7 : 0] out_axis_tstrb,
output reg [7 : 0] out_axis_tkeep,
output reg out_axis_tlast,
output reg [0 : 0] out_axis_tid,
output reg [0 : 0] out_axis_tdest,
input vfifo_full,
// AXI Stream In
input in_axis_tvalid,
output reg in_axis_tready,
input [63 : 0] in_axis_tdata,
input [7 : 0] in_axis_tstrb,
input [7 : 0] in_axis_tkeep,
input in_axis_tlast,
input [0 : 0] in_axis_tid,
input [0 : 0] in_axis_tdest,
// Flags
output reg flag_error,
output heartbeat_in,
output heartbeat_out,
output [31:0] expected_count
);
reg [31:0] out_count;
reg [31:0] in_count;
reg [63:0] in_axis_tdata_reg;
reg in_data_valid;
//
// Output
//
always @(posedge aclk)
if (!aresetn) begin
out_count <= 0;
out_axis_tvalid <= 0;
out_axis_tid <= 0; // Don't care.
out_axis_tdest <= 0; // Only use port 0 of VFIFO.
out_axis_tstrb <= 0; // Unused in VFIFO
out_axis_tkeep <= 8'hFF; // Always use every byte of data
out_axis_tlast <= 1'b0;
end else if (enable) begin
if (~vfifo_full) begin
// Always ready to output new count value.
out_axis_tvalid <= 1;
if (out_axis_tready) out_count <= out_count + 1;
// Assert TLAST every PACKET_SIZE beats.
if (out_count[15:0] == PACKET_SIZE) out_axis_tlast <= 1'b1;
else out_axis_tlast <= 1'b0;
end else begin
out_axis_tvalid <= 0;
end
end else begin
out_axis_tlast <= 1'b0;
out_axis_tvalid <= 0;
end
assign out_axis_tdata = {out_count, out_count};
assign heartbeat_out = out_count[28];
//
// Input (Ignore TLAST signal)
//
always @(posedge aclk)
if (!aresetn) begin
in_axis_tready <= 0;
in_axis_tdata_reg <= 0;
in_data_valid <= 0;
end else if (enable) begin
in_axis_tready <= 1;
in_axis_tdata_reg <= in_axis_tdata;
if (in_axis_tvalid) in_data_valid <= 1;
else in_data_valid <= 0;
end else begin
in_data_valid <= 0;
in_axis_tready <= 0;
end // else: !if(enable)
assign heartbeat_in = in_count[28];
//
// Input Checker
//
always @(posedge aclk)
if (!aresetn) begin
in_count <= 0;
flag_error <= 0;
end else if (enable) begin
if (in_data_valid) begin
if ((in_axis_tdata_reg[63:32] != in_count) || (in_axis_tdata_reg[31:0] != in_count)) begin
flag_error <= 1;
in_count <= in_axis_tdata_reg[63:32] + 1;
end else begin
flag_error <= 0;
in_count <= in_count + 1;
end
end
end
assign expected_count = in_count;
endmodule
| 6.983659 |
module axi_throttle #(
parameter INITIAL_STATE = 0, // Throttle state after reset
parameter WAIT_FOR_LAST = 0, // 0: Throttle mid packet, 1: Wait for end of packet
parameter WIDTH = 64
) (
input clk,
input reset,
input enable,
output active,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
reg throttle_reg = INITIAL_STATE[0];
reg mid_pkt;
assign active = WAIT_FOR_LAST ? throttle_reg : enable;
assign o_tdata = i_tdata;
assign o_tlast = i_tlast;
assign o_tvalid = active ? 1'b0 : i_tvalid;
assign i_tready = active ? 1'b1 : o_tready;
always @(posedge clk) begin
if (reset) begin
mid_pkt <= 1'b0;
throttle_reg <= INITIAL_STATE[0];
end else begin
if (i_tvalid & i_tready) begin
mid_pkt <= ~i_tlast;
end
if (enable & ((i_tvalid & i_tready & i_tlast) | (~mid_pkt & (~i_tvalid | ~i_tready)))) begin
throttle_reg <= 1'b1;
end else if (~enable) begin
throttle_reg <= 1'b0;
end
end
end
endmodule
| 6.510657 |
module axi_time_out (
input clks,
input reset,
input vld_in,
input ready_in,
input [15:0] reg_tmout_us_cfg,
output reg time_out
);
////////////////////////////////////////////////////////////////////////////////
// parameter declear
////////////////////////////////////////////////////////////////////////////////
parameter TIMER_1US_CFG = 200;
reg [ 7:0] timer_1us_cnt;
reg [15:0] timer_us_cnt;
reg [15:0] timer_out_cfg;
////////////////////////////////////////////////////////////////////////////////
// wire and reg declear
////////////////////////////////////////////////////////////////////////////////
reg [23:0] reg_1us_cnt;
always @(posedge clks or posedge reset) begin
if (reset == 1'b1) begin
timer_1us_cnt <= 8'd0;
end else if ((timer_1us_cnt >= TIMER_1US_CFG) || (vld_in == 1'b0)) begin
timer_1us_cnt <= 8'd0;
end else begin
timer_1us_cnt <= timer_1us_cnt + 8'd1;
end
end
always @(posedge clks or posedge reset) begin
if (reset == 1'b1) begin
timer_out_cfg <= 16'hffff;
end else begin
timer_out_cfg <= reg_tmout_us_cfg[15:0] - 16'd2;
end
end
always @(posedge clks or posedge reset) begin
if (reset == 1'b1) begin
time_out <= 1'd0;
end else begin
time_out <= (timer_us_cnt >= timer_out_cfg[15:0]);
end
end
always @(posedge clks or posedge reset) begin
if (reset == 1'b1) begin
timer_us_cnt <= 16'd0;
end else if ((time_out == 1'b1) || (ready_in == 1'b1)) begin
timer_us_cnt <= 16'd0;
end else if ((timer_1us_cnt >= TIMER_1US_CFG) && (vld_in == 1'b1)) begin
timer_us_cnt <= timer_us_cnt + 16'd1;
end else;
end
endmodule
| 6.97277 |
module axi_top (
input clk,
input rst_n,
output [2:0] slave_ARID,
output [2:0] slave_ARADDR,
output slave_ARVLD,
input slave_ARRDY,
//read data
input [2:0] slave_RID,
input [7:0] slave_RDATA,
input slave_RVLD,
output slave_RRDY,
//write addr
output [2:0] slave_AWID,
output [2:0] slave_AWADDR,
output slave_AWVLD,
input slave_AWRDY,
//write data
output [2:0] slave_WID,
output [7:0] slave_WDATA,
output slave_WVLD,
input slave_WRDY,
//write resp
input [2:0] slave_BID,
input slave_BRESP,
input slave_BVLD,
output slave_BRDY,
//read addr
input [2:0] master_ARID,
input [2:0] master_ARADDR,
input master_ARVLD,
output master_ARRDY,
//read data
output [2:0] master_RID,
output [7:0] master_RDATA,
output master_RVLD,
input master_RRDY,
//write addr
input [2:0] master_AWID,
input [2:0] master_AWADDR,
input master_AWVLD,
output master_AWRDY,
//write data
input [2:0] master_WID,
input [7:0] master_WDATA,
input master_WVLD,
output master_WRDY,
//write resp
output [2:0] master_BID,
output master_BRESP,
output master_BVLD,
input master_BRDY
);
wire sif2mif_fifo_empty;
wire [31:0] sif_s2m_fifo_dout;
wire s2m_fifo_full;
wire s2m_fifo_empty;
wire mif_m2s_fifo_empty;
wire [31:0] mif_m2s_fifo_dout;
wire sif_m2s_fifo_full;
master_if U_master_if (
.clk(clk),
.rst_n(rst_n),
//read addr
.ARID(slave_ARID),
.ARADDR(slave_ARADDR),
.ARVLD(slave_ARVLD),
.ARRDY(slave_ARRDY),
//read data
.RID(slave_RID),
.RDATA(slave_RDATA),
.RVLD(slave_RVLD),
.RRDY(slave_RRDY),
//write addr
.AWID(slave_AWID),
.AWADDR(slave_AWADDR),
.AWVLD(slave_AWVLD),
.AWRDY(slave_AWRDY),
//write data
.WID(slave_WID),
.WDATA(slave_WDATA),
.WVLD(slave_WVLD),
.WRDY(slave_WRDY),
//write resp
.BID(slave_BID),
.BRESP(slave_BRESP),
.BVLD(slave_BVLD),
.BRDY(slave_BRDY),
//to master_if
.mif_m2s_fifo_empty(mif_m2s_fifo_empty),
.mif_m2s_fifo_dout(mif_m2s_fifo_dout),
.mif_m2s_fifo_ren(!sif_m2s_fifo_full),
.s2m_fifo_wen(!s2m_fifo_empty),
.sif2mif_din(sif_s2m_fifo_dout),
.s2m_fifo_full(s2m_fifo_full)
);
slave_if U_slave_if (
.clk(clk),
.rst_n(rst_n),
//read addr
.ARID(master_ARID),
.ARADDR(master_ARADDR),
.ARVLD(master_ARVLD),
.ARRDY(master_ARRDY),
//read data
.RID(master_RID),
.RDATA(master_RDATA),
.RVLD(master_RVLD),
.RRDY(master_RRDY),
//write addr
.AWID(master_AWID),
.AWADDR(master_AWADDR),
.AWVLD(master_AWVLD),
.AWRDY(master_AWRDY),
//write data
.WID(master_WID),
.WDATA(master_WDATA),
.WVLD(master_WVLD),
.WRDY(master_WRDY),
//write resp
.BID(master_BID),
.BRESP(master_BRESP),
.BVLD(master_BVLD),
.BRDY(master_BRDY),
//to master_if
.sif_s2m_fifo_dout(sif_s2m_fifo_dout),
.sif_s2m_fifo_ren(!s2m_fifo_full),
.s2m_fifo_empty(s2m_fifo_empty),
.mif2sif_wen(!mif_m2s_fifo_empty),
.mif2sif_din(mif_m2s_fifo_dout),
.sif_m2s_fifo_full(sif_m2s_fifo_full)
);
endmodule
| 7.001033 |
module apb_mux_s3
#(parameter P_NUM=3) // num of slaves
(
input wire [P_NUM-1:0] PSEL
, output reg [31:0] PRDATA
, input wire [31:0] PRDATA0
, input wire [31:0] PRDATA1
, input wire [31:0] PRDATA2
`ifdef AMBA_APB3
, output reg PREADY
, output reg PSLVERR
, input wire PREADY0
, input wire PSLVERR0
, input wire PREADY1
, input wire PSLVERR1
, input wire PREADY2
, input wire PSLVERR2
`endif
);
always @ ( PSEL or PRDATA0 or PRDATA1 or PRDATA2) begin
case (PSEL)
3'h1: PRDATA = PRDATA0;
3'h2: PRDATA = PRDATA1;
3'h4: PRDATA = PRDATA2;
default: PRDATA = 32'h0;
endcase
end // always
`ifdef AMBA_APB3
always @ ( PSEL or PREADY0 or PREADY1 or PREADY2) begin
case (PSEL)
3'h1: PREADY = PREADY0;
3'h2: PREADY = PREADY1;
3'h4: PREADY = PREADY2;
default: PREADY = 1'b1; // make ready by default
endcase
end // always
`endif
`ifdef AMBA_APB3
always @ ( PSEL or PSLVERR0 or PSLVERR1 or PSLVERR2) begin
case (PSEL)
3'h1: PSLVERR = PSLVERR0;
3'h2: PSLVERR = PSLVERR1;
3'h4: PSLVERR = PSLVERR2;
default: PSLVERR = 1'b1; // make error by default
endcase
end // always
`endif
endmodule
| 7.266466 |
module AXI_to_MEM_buffer #(
parameter AXI_DATA_WIDTH = 32,
parameter MEM_DATA_WIDTH = 128
) (
input clk,
input rst,
input [AXI_DATA_WIDTH-1:0] AXI_wdata_i,
input [MEM_DATA_WIDTH-1:0] MEM_rdata_i,
input AXI_read_req,
input AXI_write_req,
output [AXI_DATA_WIDTH-1:0] AXI_rdata_o,
output [MEM_DATA_WIDTH-1:0] MEM_wdata_o
);
reg AXI_read_req_delay;
always @(posedge clk) begin
AXI_read_req_delay <= AXI_read_req;
end
reg [1:0] write_idx;
reg [1:0] read_idx;
always @(posedge clk or negedge rst) begin
if (!rst) begin
write_idx <= 2'b0;
read_idx <= 2'b0;
end else begin
if (AXI_write_req) begin
write_idx <= write_idx + 1;
end
if (AXI_read_req) begin
read_idx <= read_idx + 1;
end
end
end
reg [MEM_DATA_WIDTH-1:0] AXI_wbuff;
reg [MEM_DATA_WIDTH-1:0] AXI_rbuff;
always @(posedge clk) begin
if (AXI_write_req) begin
AXI_wbuff[(write_idx*AXI_DATA_WIDTH)+:AXI_DATA_WIDTH] <= AXI_wdata_i;
end
if (AXI_read_req_delay) begin
AXI_rbuff <= MEM_rdata_i;
end
end
assign mem0_addr1 = mem0_addr_cnt[MEM0_ADDR_WIDTH-1:0];
assign mem0_ce1 = mem0_data_write_hit || mem0_data_read_hit;
assign mem0_we1 = mem0_data_write_hit;
assign mem0_d1 = mem0_data_reg;
endmodule
| 8.717123 |
module axi_to_strobed #(
parameter WIDTH = 32,
parameter FIFO_SIZE = 1,
parameter MIN_RATE = 256
) (
input clk,
input reset,
input clear,
input [$clog2(MIN_RATE):0] out_rate, // Number of clock cycles between strobes
input ready,
output error, // Output strobe but no data
input [ WIDTH-1:0] i_tdata,
input i_tvalid,
input i_tlast,
output i_tready,
output out_stb,
output out_last,
output [ WIDTH-1:0] out_data
);
reg strobe;
wire valid;
reg [$clog2(MIN_RATE):0] counter = 1;
always @(posedge clk) begin
if (reset | clear) begin
strobe <= 1'b0;
counter <= 1;
end else if (ready) begin
if (counter >= out_rate) begin
strobe <= 1'b1;
counter <= 1;
end else begin
strobe <= 1'b0;
counter <= counter + 1'b1;
end
end else begin
strobe <= 1'b0;
end
end
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({i_tlast, i_tdata}),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata({out_last, out_data}),
.o_tvalid(valid),
.o_tready(strobe),
.space(),
.occupied()
);
assign out_stb = valid & strobe;
assign error = ~valid & strobe;
endmodule
| 7.593528 |
module axi_traffic_controller_v1_0 #(
// Users to add parameters here
parameter write_data_file = "wire_data_example",
parameter write_addr_file = "write_addr_example",
parameter read_data_file = "read_data_example",
parameter read_addr_file = "read_addr_example",
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M_AXI
parameter C_M_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_TRANSACTIONS_NUM = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M_AXI
input wire m_axi_init_axi_txn,
output wire m_axi_error,
output wire m_axi_txn_done,
input wire m_axi_aclk,
input wire m_axi_aresetn,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output wire [2 : 0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr,
output wire [2 : 0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata,
input wire [1 : 0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Instantiation of Axi Bus Interface M_AXI
axi_traffic_controller_v1_0_M_AXI #(
.write_data_file(write_data_file),
.write_addr_file(write_addr_file),
.read_data_file(read_data_file),
.read_addr_file(read_addr_file),
.C_M_START_DATA_VALUE(C_M_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M_AXI_TRANSACTIONS_NUM)
) axi_traffic_controller_v1_0_M_AXI_inst (
.INIT_AXI_TXN(m_axi_init_axi_txn),
.ERROR(m_axi_error),
.TXN_DONE(m_axi_txn_done),
.M_AXI_ACLK(m_axi_aclk),
.M_AXI_ARESETN(m_axi_aresetn),
.M_AXI_AWADDR(m_axi_awaddr),
.M_AXI_AWPROT(m_axi_awprot),
.M_AXI_AWVALID(m_axi_awvalid),
.M_AXI_AWREADY(m_axi_awready),
.M_AXI_WDATA(m_axi_wdata),
.M_AXI_WSTRB(m_axi_wstrb),
.M_AXI_WVALID(m_axi_wvalid),
.M_AXI_WREADY(m_axi_wready),
.M_AXI_BRESP(m_axi_bresp),
.M_AXI_BVALID(m_axi_bvalid),
.M_AXI_BREADY(m_axi_bready),
.M_AXI_ARADDR(m_axi_araddr),
.M_AXI_ARPROT(m_axi_arprot),
.M_AXI_ARVALID(m_axi_arvalid),
.M_AXI_ARREADY(m_axi_arready),
.M_AXI_RDATA(m_axi_rdata),
.M_AXI_RRESP(m_axi_rresp),
.M_AXI_RVALID(m_axi_rvalid),
.M_AXI_RREADY(m_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 7.121312 |
module axi_traffic_controller_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M_AXI_INIT_AXI_TXN;
wire M_AXI_TXN_DONE;
wire M_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (
.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M_AXI_TXN_DONE(M_AXI_TXN_DONE),
.M_AXI_ERROR(M_AXI_ERROR),
.M_AXI_INIT_AXI_TXN(M_AXI_INIT_AXI_TXN)
);
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
// Drive the BFM
initial begin
// Wait for end of reset
wait (tb_ARESETn === 0) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
M_AXI_INIT_AXI_TXN = 1'b0;
#500 M_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M_AXI:");
wait (M_AXI_TXN_DONE == 1'b1);
$display("M_AXI: PTGEN_TEST_FINISHED!");
if (M_AXI_ERROR) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule
| 7.121312 |
module axi_traffic_gen_v2_0_12_asynch_rst_ff (
data,
clk,
reset,
q
);
input data, clk, reset;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @(posedge clk or posedge reset) begin
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
end
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_regslice #(
parameter DWIDTH = 64,
parameter IDWIDTH = 64,
parameter DATADEPTH = 3 ,
parameter IDDEPTH = 2
) (
input [ DWIDTH-1:0] din,
output [ DWIDTH-1:0] dout,
output [ DWIDTH-1:0] dout_early,
input [IDWIDTH-1:0] idin,
output [IDWIDTH-1:0] idout,
output id_stable,
output reg id_stable_ff,
output data_stable,
input clk,
input reset
);
(* max_fanout = 500 *) wire reset_reg;
assign reset_reg = reset;
reg [ DWIDTH-1:0] datapath [0:DATADEPTH-1];
reg [ IDWIDTH-1:0] idpath [ 0:IDDEPTH-1];
reg [DATADEPTH-1:0] din_newpath;
reg [ IDDEPTH-1:0] idin_newpath;
integer ix;
wire din_new = (din != datapath[DATADEPTH-1]);
wire idin_new = (idin != idpath[IDDEPTH-1]);
always @(posedge clk) begin
if (reset_reg) begin
for (ix = 0; ix < DATADEPTH; ix = ix + 1) datapath[ix] <= 0;
for (ix = 0; ix < IDDEPTH; ix = ix + 1) idpath[ix] <= 0;
idin_newpath <= 0;
din_newpath <= 0;
end else begin
datapath[DATADEPTH-1] <= din;
idpath[IDDEPTH-1] <= idin;
din_newpath[DATADEPTH-1] <= din_new;
idin_newpath[IDDEPTH-1] <= idin_new;
for (ix = 0; ix < DATADEPTH - 1; ix = ix + 1) datapath[ix] <= datapath[ix+1];
for (ix = 0; ix < DATADEPTH - 1; ix = ix + 1) din_newpath[ix] <= din_newpath[ix+1];
for (ix = 0; ix < IDDEPTH - 1; ix = ix + 1) idpath[ix] <= idpath[ix+1];
for (ix = 0; ix < IDDEPTH - 1; ix = ix + 1) idin_newpath[ix] <= idin_newpath[ix+1];
id_stable_ff <= id_stable;
end
end // always @ (posedge clk)
generate
if (DATADEPTH > 1) begin : g1
assign dout_early = datapath[1];
end else begin : g2
assign dout_early = 0;
end
endgenerate
assign dout = datapath[0];
assign idout = idpath[0];
assign id_stable = (idin_newpath == 0) && (idin_new == 0);
assign data_stable = (din_newpath == 0) && (din_newpath == 0);
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_randgen #(
parameter seed = 16'hABCD
) (
output [15:0] randnum,
input generate_next,
input reset,
input clk
);
reg [15:0] lfsr;
wire lfsr_xnor;
always @(posedge clk) begin
if (reset) begin
lfsr <= seed;
end else if (generate_next) begin
lfsr <= {lfsr_xnor, lfsr[15:1]};
end
end
assign randnum = lfsr;
assign lfsr_xnor = (lfsr[12] ^ lfsr[3] ^ lfsr[1] ^ lfsr[0]) ? 1'd0 : 1'd1;
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_id_track #(
parameter ID_WIDTH = 1
) (
input Clk,
input rst_l,
input [ID_WIDTH-1:0] in_push_id,
input in_push,
input [ID_WIDTH-1:0] in_search_id,
input [ 3:0] in_clear_pos,
input in_only_entry0,
output [ 3:0] out_push_pos,
output [ 3:0] out_search_hit,
output [ 3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = {1'b1, in_push_id[ID_WIDTH-1:0]};
wire [3:0] push_search = {
(push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0])
};
wire [3:0] free_pre = {
~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH], ~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH]
};
wire [3:0] free = (in_only_entry0) ? {3'b000, free_pre[0]} : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = {1'b1, in_search_id[ID_WIDTH-1:0]};
wire [3:0] search_pos = {
(search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0])
};
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] & in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_static_cmdgen #(
parameter C_ATG_STATIC_ADDRESS = 32'h12A0_0000,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_ATG_MIF_ADDR_BITS = 4, // 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_STATIC_LENGTH = 3,
parameter C_ATG_SYSTEM_INIT = 0,
parameter C_ATG_SYSTEM_TEST = 0
) (
input Clk,
input rst_l,
input static_ctl_en,
input [ 7:0] static_len,
input [ 9:0] rom_addr_ptr_ff,
input [ 31:0] rom_addr,
input [ 31:0] rom_data,
output [ 127:0] cmd_out_mw,
output [C_M_AXI_DATA_WIDTH-1:0] cmd_data,
output [ 127:0] cmd_out_mr
);
wire [2:0] size;
generate
if (C_M_AXI_DATA_WIDTH == 32) begin : M_SISE32
assign size = 3'b010;
end
endgenerate
generate
if (C_M_AXI_DATA_WIDTH == 64) begin : M_SISE64
assign size = 3'b011;
end
endgenerate
generate
if (C_M_AXI_DATA_WIDTH == 128) begin : M_SISE128
assign size = 3'b100;
end
endgenerate
generate
if (C_M_AXI_DATA_WIDTH == 256) begin : M_SISE256
assign size = 3'b101;
end
endgenerate
generate
if (C_M_AXI_DATA_WIDTH == 512) begin : M_SISE512
assign size = 3'b110;
end
endgenerate
wire [5:0] id = 6'h0;
wire [1:0] burst = 2'b01;
reg [7:0] len = 8'h0;
always @(posedge Clk) begin
len[7:0] <= (rst_l) ? static_len[7:0] : C_ATG_STATIC_LENGTH;
end
//
//Static-mode
//
generate
if (C_ATG_SYSTEM_INIT == 0 && C_ATG_SYSTEM_TEST == 0) begin : STATIC_MODE_ON
assign cmd_out_mw = {
32'h0, 32'h0, static_ctl_en, 7'h0, 3'b010, id, size, burst, 2'b00, len, C_ATG_STATIC_ADDRESS
};
assign cmd_out_mr = {
32'h0, 32'h0, static_ctl_en, 7'h0, 3'b010, id, size, burst, 2'b00, len, C_ATG_STATIC_ADDRESS
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = {
64'hCAFE5AFE_C001CAFE, 64'hCAFE1AFE_C001DAFE, 64'hCAFE2AFE_C001EAFE, 64'hCAFE3AFE_C001FAFE
};
end
endgenerate
wire system_init_en;
wire system_init_cnt_en;
wire system_init_cmd_en;
// disable when no.of commands count reached Maximum limit(16)
assign system_init_cnt_en = (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS] != 1'b1);
// disable when command has cmd-valid bit set to 0
assign system_init_cmd_en = ~(&rom_addr); // All 1's is NOP OPCODE.
assign system_init_en = system_init_cnt_en && system_init_cmd_en;
generate
if (C_ATG_SYSTEM_INIT == 1 || C_ATG_SYSTEM_TEST == 1) begin : SYSTEM_INIT_TEST_MODE_ON
assign cmd_out_mw = {
32'h0, 32'h0, system_init_en, 7'h0, 3'b010, id, size, burst, 2'b00, 8'h0, rom_addr[31:0]
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = rom_data[31:0];
end
endgenerate
endmodule
| 6.812039 |
module axi_traffic_gen_v2_0_12_axis_fifo #(
parameter WIDTH = 33,
parameter HEADREG = 1,
parameter ZERO_INVALID = 1,
parameter FULL_LEVEL = 14,
parameter DEPTH = 16,
parameter DEPTHBITS = 4
) (
input Clk,
input Rst_n,
input [ WIDTH-1:0] in_data,
input [ WIDTH-1:0] in_invalid_data,
input in_push,
input in_ready,
input in_block_notfull,
input in_block_outvalid,
output out_valid,
output out_notfull,
output out_overflow,
output [DEPTHBITS-1:0] out_depth,
output [ WIDTH-1:0] out_data
);
(* ram_style = "distributed" *)reg [WIDTH-1:0] data_ff [DEPTH-1:0];
reg [WIDTH-1:0] headreg_ff;
reg [DEPTHBITS-1:0] in_ptr_ff, out_ptr_ff;
reg [DEPTHBITS:0] depth_ff;
reg valid_ff, full_ff, notfull_ff, valid_filt_ff;
wire do_pop = in_ready && valid_filt_ff;
wire [DEPTHBITS-1:0] in_ptr = (in_push) ? in_ptr_ff[DEPTHBITS-1:0] + 'h1 :
in_ptr_ff[DEPTHBITS-1:0];
wire [DEPTHBITS:0] depth =
(in_push && ~do_pop) ? depth_ff[DEPTHBITS:0] + 'h1 :
(~in_push && do_pop) ? depth_ff[DEPTHBITS:0] - 'h1 :
depth_ff[DEPTHBITS:0];
wire depth_was1 = (depth_ff[DEPTHBITS:0] == 'h1);
wire valid = (depth[DEPTHBITS:0] != 'h0);
wire full = (depth[DEPTHBITS:0] >= FULL_LEVEL) || in_block_notfull;
wire notfull = ~full;
wire [WIDTH-1:0] raw_data = data_ff[out_ptr_ff[DEPTHBITS-1:0]];
wire [DEPTHBITS-1:0] out_ptr = (do_pop) ? out_ptr_ff[DEPTHBITS-1:0] + 'h1 :
out_ptr_ff[DEPTHBITS-1:0];
wire [WIDTH-1:0] head_raw_data = (depth_was1) ? in_data[WIDTH-1:0] : raw_data[WIDTH-1:0];
wire [WIDTH-1:0] headreg = (!valid_ff && in_push) ? in_data[WIDTH-1:0] :
(do_pop) ? head_raw_data[WIDTH-1:0] :
headreg_ff[WIDTH-1:0];
wire valid_filt = valid && ((valid_filt_ff && ~do_pop) || ~in_block_outvalid);
always @(posedge Clk) begin
in_ptr_ff[DEPTHBITS-1:0] <= (Rst_n) ? in_ptr[DEPTHBITS-1:0] : 'h0;
out_ptr_ff[DEPTHBITS-1:0] <= (Rst_n) ? out_ptr[DEPTHBITS-1:0] : ((HEADREG) ? 'h1 : 'h0);
depth_ff[DEPTHBITS:0] <= (Rst_n) ? depth[DEPTHBITS:0] : 'h0;
valid_ff <= (Rst_n) ? valid : 1'b0;
valid_filt_ff <= (Rst_n) ? valid_filt : 1'b0;
full_ff <= (Rst_n) ? full : 1'b0;
notfull_ff <= (Rst_n) ? notfull : 1'b0;
headreg_ff[WIDTH-1:0] <= (Rst_n) ? headreg[WIDTH-1:0] : 'h0;
end
integer i;
always @(posedge Clk) begin
if (in_push) begin
data_ff[in_ptr_ff[DEPTHBITS-1:0]] <= in_data[WIDTH-1:0];
end
end
wire [WIDTH-1:0] out_data_pre = (HEADREG) ? headreg_ff[WIDTH-1:0] : raw_data[WIDTH-1:0];
assign out_data[WIDTH-1:0] = (ZERO_INVALID && ~valid_filt_ff) ?
in_invalid_data[WIDTH-1:0] : out_data_pre[WIDTH-1:0];
assign out_valid = valid_filt_ff;
assign out_notfull = notfull_ff;
assign out_overflow = depth_ff[DEPTHBITS];
assign out_depth = depth_ff[DEPTHBITS-1:0];
endmodule
| 6.812039 |
module axi_trivium_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 6
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
axi_trivium_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axi_trivium_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.76226 |
module axi_true_dpbram #(
parameter DWIDTH = 128,
parameter AWIDTH = 7,
parameter MEM_SIZE = 98
) (
/* Special Inputs */
input clk,
/* input for port 0 */
input [AWIDTH - 1 : 0] addr0_i,
input ce0_i,
input we0_i,
input [DWIDTH -1 : 0] d0_i,
/* input for port 1 */
input [AWIDTH - 1 : 0] addr1_i,
input ce1_i,
input we1_i,
input [DWIDTH -1 : 0] d1_i,
/* output for port 0 */
output reg [DWIDTH - 1 : 0] q0_o,
/* output for port 1 */
output reg [DWIDTH - 1 : 0] q1_o
);
/* Making Block Memory*/
(* ram_style = "block" *) reg [DWIDTH - 1 : 0] ram[0 : MEM_SIZE - 1];
integer i;
initial begin
for (i = 0; i < MEM_SIZE; i = i + 1) begin
ram[i] <= {
8'b0000_0000,
8'b0000_0001,
8'b0000_0010,
8'b0000_0011,
8'b0000_0100,
8'b0000_0101,
8'b0000_0110,
8'b0000_0111
};
end
end
// always block for port0
always @(posedge clk) begin
if (ce0_i) begin
if (we0_i) ram[addr0_i] <= d0_i;
else q0_o <= ram[addr0_i];
end
end
// always block for port1
always @(posedge clk) begin
if (ce1_i) begin
if (we1_i) ram[addr1_i] <= d1_i;
else q1_o <= ram[addr1_i];
end
end
endmodule
| 7.497574 |
module axi_uart #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
/*
* UART interface
*/
input wire rxd,
output wire txd,
/*
* Status
*/
output wire tx_busy,
output wire rx_busy,
output wire rx_overrun_error,
output wire rx_frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
uart_tx #(
.DATA_WIDTH(DATA_WIDTH)
) uart_tx_inst (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(tx_busy),
// configuration
.prescale(prescale)
);
uart_rx #(
.DATA_WIDTH(DATA_WIDTH)
) uart_rx_inst (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
// configuration
.prescale(prescale)
);
endmodule
| 8.206574 |
module axi_vfifo_64 (
aclk,
aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
vfifo_mm2s_channel_full,
vfifo_s2mm_channel_full,
vfifo_mm2s_channel_empty,
vfifo_mm2s_rresp_err_intr,
vfifo_s2mm_bresp_err_intr,
vfifo_s2mm_overrun_err_intr,
vfifo_idle
);
input aclk;
input aresetn;
output [0 : 0] m_axi_awid;
output [31 : 0] m_axi_awaddr;
output [7 : 0] m_axi_awlen;
output [2 : 0] m_axi_awsize;
output [1 : 0] m_axi_awburst;
output [0 : 0] m_axi_awlock;
output [3 : 0] m_axi_awcache;
output [2 : 0] m_axi_awprot;
output [3 : 0] m_axi_awqos;
output [3 : 0] m_axi_awregion;
output [0 : 0] m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [63 : 0] m_axi_wdata;
output [7 : 0] m_axi_wstrb;
output m_axi_wlast;
output [0 : 0] m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0 : 0] m_axi_bid;
input [1 : 0] m_axi_bresp;
input [0 : 0] m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0 : 0] m_axi_arid;
output [31 : 0] m_axi_araddr;
output [7 : 0] m_axi_arlen;
output [2 : 0] m_axi_arsize;
output [1 : 0] m_axi_arburst;
output [0 : 0] m_axi_arlock;
output [3 : 0] m_axi_arcache;
output [2 : 0] m_axi_arprot;
output [3 : 0] m_axi_arqos;
output [3 : 0] m_axi_arregion;
output [0 : 0] m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0 : 0] m_axi_rid;
input [63 : 0] m_axi_rdata;
input [1 : 0] m_axi_rresp;
input m_axi_rlast;
input [0 : 0] m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [63 : 0] s_axis_tdata;
input [7 : 0] s_axis_tstrb;
input [7 : 0] s_axis_tkeep;
input s_axis_tlast;
input [0 : 0] s_axis_tid;
input [0 : 0] s_axis_tdest;
output m_axis_tvalid;
input m_axis_tready;
output [63 : 0] m_axis_tdata;
output [7 : 0] m_axis_tstrb;
output [7 : 0] m_axis_tkeep;
output m_axis_tlast;
output [0 : 0] m_axis_tid;
output [0 : 0] m_axis_tdest;
input [1 : 0] vfifo_mm2s_channel_full;
output [1 : 0] vfifo_s2mm_channel_full;
output [1 : 0] vfifo_mm2s_channel_empty;
output vfifo_mm2s_rresp_err_intr;
output vfifo_s2mm_bresp_err_intr;
output vfifo_s2mm_overrun_err_intr;
output [1 : 0] vfifo_idle;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
| 7.161848 |
module axi_vga #(
parameter h_frontporch = 56 - 1,
parameter h_active = 56 + 120 - 1,
parameter h_backporch = 56 + 120 + 800 - 1,
parameter h_total = 56 + 120 + 800 + 64 - 1,
parameter v_frontporch = 37 - 1,
parameter v_active = 37 + 6 - 1,
parameter v_backporch = 37 + 6 + 600 - 1,
parameter v_total = 37 + 6 + 600 + 23 - 1,
parameter screen_length = 400,
parameter screen_width = 300,
parameter X_WIDTH = 11,
parameter Y_WIDTH = 11,
parameter VMEM_ADDR_WIDTH = 32
) (
//axi interface
input axi_clk,
input axi_resetn,
input [31:0] axi_awaddr,
input [ 0:0] axi_awvalid,
output [ 0:0] axi_awready,
input [31:0] axi_wdata,
input [ 3:0] axi_wstrb,
input [ 0:0] axi_wvalid,
output [ 0:0] axi_wready,
output [ 1:0] axi_bresp,
output [ 0:0] axi_bvalid,
input [ 0:0] axi_bready,
input [31:0] axi_araddr,
input [ 0:0] axi_arvalid,
output [ 0:0] axi_arready,
output [31:0] axi_rdata,
output [ 1:0] axi_rresp,
output [ 0:0] axi_rvalid,
input [ 0:0] axi_rready,
//vga
input vga_clk, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA CLK" *)
output m_clk, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA RED" *)
output [3:0] m_red, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA GREEN" *)
output [3:0] m_green, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA BLUE" *)
output [3:0] m_blue, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA HSYNC" *)
output m_hsync, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA VSYNC" *)
output m_vsync, (* X_INTERFACE_INFO = "xilinx.com:interface:vga:1.0 VGA DE" *)
output m_de
);
wire wdata_en;
wire [31:0] wdata;
wire [31:0] wdata_addr;
wire [3:0] wdata_byte_en;
axilite_naive_bridge b0 (
.axi_clk(axi_clk),
.axi_resetn(axi_resetn),
.axi_awaddr(axi_awaddr),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_bresp(axi_bresp),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_araddr(axi_araddr),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_rdata(axi_rdata),
.axi_rresp(axi_rresp),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.wdata_en(wdata_en),
.wdata_addr(wdata_addr),
.wdata(wdata),
.wdata_byte_en(wdata_byte_en)
);
vga_controller #(
.h_frontporch(h_frontporch),
.h_active(h_active),
.h_backporch(h_backporch),
.h_total(h_total),
.v_frontporch(v_frontporch),
.v_active(v_active),
.v_backporch(v_backporch),
.v_total(v_total),
.screen_length(screen_length),
.screen_width (screen_width),
.X_WIDTH(X_WIDTH),
.Y_WIDTH(Y_WIDTH),
.VMEM_ADDR_WIDTH(VMEM_ADDR_WIDTH)
) vga_ctr (
.clk (axi_clk),
.pclk (vga_clk),
.reset(~axi_resetn),
.vga_w_en (wdata_en),
.vga_w_addr (wdata_addr[VMEM_ADDR_WIDTH-1:0]),
.vga_w_byte_en(wdata_byte_en),
.vga_w_data (wdata),
.hsync(m_hsync),
.vsync(m_vsync),
.vga_r(m_red),
.vga_g(m_green),
.vga_b(m_blue)
);
endmodule
| 8.139766 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_write_slave #(
parameter DATA_WIDTH = 32,
parameter WRITE_ACCEPTANCE = 3
) (
input clk,
input reset,
input awvalid,
output awready,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input [2:0] awprot,
input [3:0] awcache,
input wvalid,
output wready,
input [DATA_WIDTH-1:0] wdata,
input [DATA_WIDTH/8-1:0] wstrb,
input wlast,
output reg bvalid,
input bready,
output [1:0] bresp
);
wire beat_last;
axi_slave #(
.ACCEPTANCE(WRITE_ACCEPTANCE)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(awvalid),
.ready(awready),
.addr(awaddr),
.len(awlen),
.size(awsize),
.burst(awburst),
.prot(awprot),
.cache(awcache),
.beat_stb(wready),
.beat_ack(wvalid & wready),
.beat_last(beat_last)
);
reg [4:0] resp_count = 'h00;
wire [4:0] resp_count_next;
reg [DATA_WIDTH-1:0] data_cmp = 'h00;
reg failed = 'b0;
assign bresp = 2'b00;
wire resp_count_dec = bvalid & bready;
wire resp_count_inc = wvalid & wready & beat_last;
assign resp_count_next = resp_count - resp_count_dec + resp_count_inc;
always @(posedge clk) begin
if (reset == 1'b1) begin
resp_count <= 'h00;
end else begin
resp_count <= resp_count - resp_count_dec + resp_count_inc;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
bvalid <= 1'b0;
end else if (bvalid == 1'b0 || bready == 1'b1) begin
if (resp_count_next != 'h00) begin
bvalid <= {$random} % 4 == 0;
end else begin
bvalid <= 1'b0;
end
end
end
integer byte_count;
always @(*) begin: count
integer i;
byte_count = 0;
for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin
byte_count = byte_count + wstrb[i];
end
end
always @(posedge clk) begin: gen_data_cmp
integer i;
if (reset) begin
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
data_cmp[i+:8] <= i/8;
end
failed <= 'b0;
end else if (wvalid & wready) begin
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
if (data_cmp[i+:8] !== wdata[i+:8] && wstrb[i/8] == 1'b1) begin
failed <= 1'b1;
end
data_cmp[i+:8] <= data_cmp[i+:8] + byte_count;
end
end
end
endmodule
| 8.180735 |
module axi_w_buffer #(
parameter DATA_WIDTH = 64,
parameter USER_WIDTH = 6,
parameter BUFFER_DEPTH = 2,
parameter STRB_WIDTH = DATA_WIDTH / 8 // DO NOT OVERRIDE
) (
clk_i,
rst_ni,
test_en_i,
slave_valid_i,
slave_data_i,
slave_strb_i,
slave_user_i,
slave_last_i,
slave_ready_o,
master_valid_o,
master_data_o,
master_strb_o,
master_user_o,
master_last_o,
master_ready_i
);
//parameter DATA_WIDTH = 64;
//parameter USER_WIDTH = 6;
//parameter BUFFER_DEPTH = 2;
//parameter STRB_WIDTH = DATA_WIDTH / 8;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire slave_valid_i;
input wire [DATA_WIDTH - 1:0] slave_data_i;
input wire [STRB_WIDTH - 1:0] slave_strb_i;
input wire [USER_WIDTH - 1:0] slave_user_i;
input wire slave_last_i;
output wire slave_ready_o;
output wire master_valid_o;
output wire [DATA_WIDTH - 1:0] master_data_o;
output wire [STRB_WIDTH - 1:0] master_strb_o;
output wire [USER_WIDTH - 1:0] master_user_o;
output wire master_last_o;
input wire master_ready_i;
wire [(DATA_WIDTH + STRB_WIDTH) + USER_WIDTH:0] s_data_in;
wire [(DATA_WIDTH + STRB_WIDTH) + USER_WIDTH:0] s_data_out;
assign s_data_in = {slave_user_i, slave_strb_i, slave_data_i, slave_last_i};
assign {master_user_o, master_strb_o, master_data_o, master_last_o} = s_data_out;
generic_fifo #(
.DATA_WIDTH(((1 + DATA_WIDTH) + STRB_WIDTH) + USER_WIDTH),
.DATA_DEPTH(BUFFER_DEPTH)
) buffer_i (
.clk(clk_i),
.rst_n(rst_ni),
.data_i(s_data_in),
.valid_i(slave_valid_i),
.grant_o(slave_ready_o),
.data_o(s_data_out),
.valid_o(master_valid_o),
.grant_i(master_ready_i),
.test_mode_i(test_en_i)
);
endmodule
| 8.251875 |
module axi_w_reg_slice (
wreadys,
wvalidm,
widm,
wdatam,
wstrbm,
wlastm,
wuserm,
aclk,
aresetn,
wvalids,
wids,
wdatas,
wstrbs,
wlasts,
wusers,
wreadym
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter STRB_WIDTH = DATA_WIDTH / 8;
localparam PAYLD_WIDTH = ID_WIDTH + DATA_WIDTH + USER_WIDTH + STRB_WIDTH + 1;
input aclk;
input aresetn;
input wvalids;
output wreadys;
input [ID_WIDTH-1:0] wids;
input [DATA_WIDTH-1:0] wdatas;
input [STRB_WIDTH-1:0] wstrbs;
input wlasts;
input [USER_WIDTH-1:0] wusers;
output wvalidm;
input wreadym;
output [ID_WIDTH-1:0] widm;
output [DATA_WIDTH-1:0] wdatam;
output [STRB_WIDTH-1:0] wstrbm;
output wlastm;
output [USER_WIDTH-1:0] wuserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = wvalids;
assign payload_src = {wids, wdatas, wstrbs, wlasts, wusers};
assign wreadys = ready_src;
assign wvalidm = valid_dst;
assign {widm, wdatam, wstrbm, wlastm, wuserm} = payload_dst;
assign ready_dst = wreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.843046 |
module AxROM (
output led,
input m2,
input romsel,
input cpu_rw_in,
output [18:12] cpu_addr_out,
input [14:0] cpu_addr_in,
input [7:0] cpu_data_in,
output cpu_wr_out,
output cpu_rd_out,
output cpu_flash_ce,
output cpu_sram_ce,
input ppu_rd_in,
input ppu_wr_in,
input [13:10] ppu_addr_in,
output [18:10] ppu_addr_out,
output ppu_rd_out,
output ppu_wr_out,
output ppu_flash_ce,
output ppu_sram_ce,
output ppu_ciram_a10,
output ppu_ciram_ce,
output irq
);
reg [7:0] bank;
assign led = ~romsel;
assign cpu_addr_out[18:12] = {bank[2:0], cpu_addr_in[14:12]};
assign cpu_wr_out = 1;
assign cpu_rd_out = ~cpu_rw_in;
assign cpu_flash_ce = romsel;
assign cpu_sram_ce = 1;
assign ppu_rd_out = ppu_rd_in;
assign ppu_wr_out = ppu_wr_in;
assign ppu_flash_ce = 1;
assign ppu_sram_ce = ppu_addr_in[13];
assign ppu_ciram_a10 = bank[4];
assign ppu_ciram_ce = ~ppu_addr_in[13];
assign irq = 1'bz;
always @(posedge romsel) begin
if (cpu_rw_in == 0) bank = cpu_data_in;
end
endmodule
| 7.073278 |
module ax_debounce (
input clk,
input rst,
input button_in,
output reg button_posedge,
output reg button_negedge,
output reg button_out
);
//// ---------------- internal constants --------------
parameter N = 32; // debounce timer bitwidth
parameter FREQ = 50; //model clock :Mhz
parameter MAX_TIME = 20; //ms
localparam TIMER_MAX_VAL = MAX_TIME * 1000 * FREQ;
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg; // timing regs
reg [N-1 : 0] q_next;
reg DFF1, DFF2; // input flip-flops
wire q_add; // control flags
wire q_reset;
reg button_out_d0;
//// ------------------------------------------------------
////contenious assignment for counter control
assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level chage to reset counter
assign q_add = ~(q_reg == TIMER_MAX_VAL); // add to counter when q_reg msb is equal to 0
//// combo counter to manage q_next
always @(q_reset, q_add, q_reg) begin
case ({
q_reset, q_add
})
2'b00: q_next <= q_reg;
2'b01: q_next <= q_reg + 1;
default: q_next <= {N{1'b0}};
endcase
end
//// Flip flop inputs and q_reg update
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
DFF1 <= 1'b0;
DFF2 <= 1'b0;
q_reg <= {N{1'b0}};
end else begin
DFF1 <= button_in;
DFF2 <= DFF1;
q_reg <= q_next;
end
end
//// counter control
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) button_out <= 1'b1;
else if (q_reg == TIMER_MAX_VAL) button_out <= DFF2;
else button_out <= button_out;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
button_out_d0 <= 1'b1;
button_posedge <= 1'b0;
button_negedge <= 1'b0;
end else begin
button_out_d0 <= button_out;
button_posedge <= ~button_out_d0 & button_out;
button_negedge <= button_out_d0 & ~button_out;
end
end
endmodule
| 7.37815 |
module implements the modular product between an input
four term polynomial with coefficients in Galois-Field{2^8} <i_column> and
the AES cipher fixed polynomial {03}x^3+{01}x^2+{01}x^1+{02}x^0.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module ax_modular_multiplier
#(
// PARAMETERS.
parameter NB_BYTE = 8 ,
parameter N_ROWS = 4
)
(
// OUTPUTS.
output wire [NB_BYTE * N_ROWS -1:0] o_column , // [HINT] Colums are consecutive and column 0 is on MSB (previous version assumed rows were consecutive and first row was on LSB).
// INPUTS.
input wire [NB_BYTE * N_ROWS -1:0] i_column
) ;
// LOCAL PARAMETERS.
localparam BAD_CONF = ( NB_BYTE != 8 ) || ( N_ROWS != 4 ) ;
// INTERNAL SIGNALS.
genvar ii ;
wire [NB_BYTE * N_ROWS -1:0] column_x02 ;
wire [NB_BYTE * N_ROWS -1:0] column_x03 ;
// ALGORITHM BEGIN.
// {02} x and {03} x product generation.
// -----------------------------------------------------
generate
for ( ii=0; ii<N_ROWS; ii=ii+1 )
begin : genfor_x02_and_x03_products
wire [NB_BYTE-1:0] ii_s_x03 ;
wire [NB_BYTE-1:0] ii_s_x02 ;
wire [NB_BYTE-1:0] ii_s ;
assign ii_s
= i_column[ ii*NB_BYTE +: NB_BYTE ] ;
time_03
#(
.NB_BYTE ( NB_BYTE )
)
u_time_03_ii
(
.o_byte ( ii_s_x03 ),
.i_byte ( ii_s )
) ;
xtime
#(
.NB_BYTE ( NB_BYTE )
)
u_xtime_ii
(
.o_byte ( ii_s_x02 ),
.i_byte ( ii_s )
) ;
assign column_x03[ ii*NB_BYTE +: NB_BYTE ]
= ii_s_x03 ;
assign column_x02[ ii*NB_BYTE +: NB_BYTE ]
= ii_s_x02 ;
end // genfor_x02_and_x03_products
endgenerate
// Modular product.
// -----------------------------------------------------
assign o_column[3*NB_BYTE+:NB_BYTE] = column_x02[3*NB_BYTE+:NB_BYTE] ^ column_x03[2*NB_BYTE+:NB_BYTE] ^ i_column[1*NB_BYTE+:NB_BYTE] ^ i_column[0*NB_BYTE+:NB_BYTE] ;
assign o_column[2*NB_BYTE+:NB_BYTE] = i_column[3*NB_BYTE+:NB_BYTE] ^ column_x02[2*NB_BYTE+:NB_BYTE] ^ column_x03[1*NB_BYTE+:NB_BYTE] ^ i_column[0*NB_BYTE+:NB_BYTE] ;
assign o_column[1*NB_BYTE+:NB_BYTE] = i_column[3*NB_BYTE+:NB_BYTE] ^ i_column[2*NB_BYTE+:NB_BYTE] ^ column_x02[1*NB_BYTE+:NB_BYTE] ^ column_x03[0*NB_BYTE+:NB_BYTE] ;
assign o_column[0*NB_BYTE+:NB_BYTE] = column_x03[3*NB_BYTE+:NB_BYTE] ^ i_column[2*NB_BYTE+:NB_BYTE] ^ i_column[1*NB_BYTE+:NB_BYTE] ^ column_x02[0*NB_BYTE+:NB_BYTE] ;
endmodule
| 7.842559 |
module implements the modular product between an input
four term polynomial with coefficients in Galois-Field{2^8} <i_column> and
the AES cipher fixed polynomial {03}x^3+{01}x^2+{01}x^1+{02}x^0.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module ax_modular_multiplier_new
#(
// PARAMETERS.
parameter NB_BYTE = 8 ,
parameter N_ROWS = 4
)
(
// OUTPUTS.
output wire [NB_BYTE * N_ROWS -1:0] o_column , // [HINT] Colums are consecutive and column 0 is on MSB (previous version assumed rows were consecutive and first row was on LSB).
// INPUTS.
input wire [NB_BYTE * N_ROWS -1:0] i_column
) ;
// LOCAL PARAMETERS.
localparam BAD_CONF = ( NB_BYTE != 8 ) || ( N_ROWS != 4 ) ;
// INTERNAL SIGNALS.
wire [NB_BYTE-1:0] col0;
wire [NB_BYTE-1:0] col1;
wire [NB_BYTE-1:0] col2;
wire [NB_BYTE-1:0] col3;
wire [NB_BYTE-1:0] col01;
wire [NB_BYTE-1:0] col12;
wire [NB_BYTE-1:0] col23;
wire [NB_BYTE-1:0] col30;
wire [NB_BYTE-1:0] col012;
wire [NB_BYTE-1:0] col123;
wire [NB_BYTE-1:0] col230;
wire [NB_BYTE-1:0] col301;
wire [NB_BYTE-1:0] xtime0;
wire [NB_BYTE-1:0] xtime1;
wire [NB_BYTE-1:0] xtime2;
wire [NB_BYTE-1:0] xtime3;
// ALGORITHM BEGIN.
// Rewire
// -----------------------------------------------------
assign col3 = i_column[3*NB_BYTE+:NB_BYTE];
assign col2 = i_column[2*NB_BYTE+:NB_BYTE];
assign col1 = i_column[1*NB_BYTE+:NB_BYTE];
assign col0 = i_column[0*NB_BYTE+:NB_BYTE];
assign col01 = col0 ^ col1;
assign col12 = col1 ^ col2;
assign col23 = col2 ^ col3;
assign col30 = col3 ^ col0;
assign col012 = col0 ^ col12;
assign col123 = col1 ^ col23;
assign col230 = col2 ^ col30;
assign col301 = col3 ^ col01;
// Xtime
// -----------------------------------------------------
xtime_new
#(
.NB_BYTE ( NB_BYTE )
)
u_xtime_new_0
(
.o_byte ( xtime0 ),
.i_byte ( col01 )
) ;
xtime_new
#(
.NB_BYTE ( NB_BYTE )
)
u_xtime_new_1
(
.o_byte ( xtime1 ),
.i_byte ( col12 )
) ;
xtime_new
#(
.NB_BYTE ( NB_BYTE )
)
u_xtime_new_2
(
.o_byte ( xtime2 ),
.i_byte ( col23 )
) ;
xtime_new
#(
.NB_BYTE ( NB_BYTE )
)
u_xtime_new_3
(
.o_byte ( xtime3 ),
.i_byte ( col30 )
) ;
// Modular product.
// -----------------------------------------------------
assign o_column[3*NB_BYTE+:NB_BYTE] = xtime1 ^ col230;
assign o_column[2*NB_BYTE+:NB_BYTE] = xtime2 ^ col301;
assign o_column[1*NB_BYTE+:NB_BYTE] = xtime3 ^ col012;
assign o_column[0*NB_BYTE+:NB_BYTE] = xtime0 ^ col123;
endmodule
| 7.842559 |
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