code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ax_pwm #(
parameter N = 16 //pwm bit width
) (
input clk,
input rst,
input [N - 1:0] period,
input [N - 1:0] duty,
output pwm_out
);
reg [N - 1:0] period_r;
reg [N - 1:0] duty_r;
reg [N - 1:0] period_cnt;
reg pwm_r;
assign pwm_out = pwm_r;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
period_r <= {N{1'b0}};
duty_r <= {N{1'b0}};
end else begin
period_r <= period;
duty_r <= duty;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) period_cnt <= {N{1'b0}};
else period_cnt <= period_cnt + period_r;
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
pwm_r <= 1'b0;
end else begin
if (period_cnt >= duty_r) pwm_r <= 1'b1;
else pwm_r <= 1'b0;
end
end
endmodule
| 6.821939 |
module aynDff (
D,
clr_n,
clk,
Q
);
input D;
input clr_n;
input clk;
output reg Q;
always @(negedge clr_n or posedge clk) begin
if (!clr_n) begin
Q <= 0;
end else Q <= D;
end
endmodule
| 7.467651 |
module aysnc_fifo_16_to_32 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [9:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire [9:0] rdusedw = sub_wire2[9:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.eccstatus (),
.rdfull (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.add_usedw_msb_bit = "ON",
dcfifo_mixed_widths_component.intended_device_family = "Cyclone 10 LP",
dcfifo_mixed_widths_component.lpm_numwords = 1024,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 16,
dcfifo_mixed_widths_component.lpm_widthu = 11,
dcfifo_mixed_widths_component.lpm_widthu_r = 10,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
endmodule
| 6.755726 |
module aysnc_fifo_32_to_16 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [9:0] wrusedw = sub_wire2[9:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrusedw (sub_wire2),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_mixed_widths_component.add_usedw_msb_bit = "ON",
dcfifo_mixed_widths_component.intended_device_family = "Cyclone 10 LP",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 10,
dcfifo_mixed_widths_component.lpm_widthu_r = 11,
dcfifo_mixed_widths_component.lpm_width_r = 16,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
endmodule
| 6.625786 |
module AYUMU (
input CLK,
input [31:0] INPUT,
output [31:0] OUTPUT
);
reg [10:0] CLKS;
always @(posedge CLK) begin
case (CLKS)
5'b00001: CLKS <= 5'b00010;
5'b00010: CLKS <= 5'b00100;
5'b00100: CLKS <= 5'b01000;
5'b01000: CLKS <= 5'b10000;
5'b10000: CLKS <= 5'b00001;
default: CLKS <= 5'b00001;
endcase
end
always @(posedge CLKS[2]) begin
C_FLAG <= C_OUT;
F_FLAG <= F_OUT;
end
initial begin
CLKS = 4'b00001;
end
wire [15:0] NEXT;
wire [15:0] ADDR;
wire [15:0] COMMAND;
wire [3:0] CAL;
wire [1:0] MODE;
wire [7:0] IM;
wire [3:0] REG_A_ADDR;
wire [3:0] REG_B_ADDR;
wire [3:0] REG_O_ADDR;
wire [1:0] REG_O_TYPE;
wire [1:0] JUMP_MODE;
wire REG_WRITE;
wire [1:0] SEL;
wire MEM_WRITE;
wire INOUT_FLAG;
wire [127:0] REG_R;
wire [63:0] REG_IO;
wire [63:0] REG_INT;
wire [7:0] REG_A;
wire [7:0] REG_B;
wire [7:0] INT_FLAG_OUT;
reg C_FLAG;
reg F_FLAG;
wire [7:0] ALU_OUT;
wire C_OUT;
wire F_OUT;
wire [7:0] DATA;
wire INT_PROCESS;
assign OUTPUT[31:8] = REG_IO[31:8];
assign OUTPUT[7:0] = REG_IO[7:0];
PC PC (
.CLK_FT(CLKS[0]),
.NEXT (NEXT),
.ADDR (ADDR)
);
ROM ROM (
.ADDR(ADDR),
.COMMAND(COMMAND)
);
DECODER DECODER (
.COMMAND(COMMAND),
.CAL(CAL),
.MODE(MODE),
.IM(IM),
.REG_A(REG_A_ADDR),
.REG_B(REG_B_ADDR),
.REG_O(REG_O_ADDR),
.REG_O_TYPE(REG_O_TYPE),
.JUMP_MODE(JUMP_MODE),
.REG_WRITE(REG_WRITE),
.SEL(SEL),
.MEM_WRITE(MEM_WRITE),
.INOUT_FLAG(INOUT_FLAG)
);
REG_DC REG_DC (
.CLK_DC(CLKS[1]),
.REG_R(REG_R),
.REG_IO(REG_IO),
.SEL(SEL),
.REG_O_TYPE(REG_O_TYPE),
.REG_A_ADDR(REG_A_ADDR),
.REG_B_ADDR(REG_B_ADDR),
.REG_O_ADDR(REG_O_ADDR),
.IM(IM),
.REG_A(REG_A),
.REG_B(REG_B)
);
ALU ALU (
.CLK_EX(CLKS[2]),
.IN_A(REG_A),
.IN_B(REG_B),
.CAL(CAL),
.MODE(MODE),
.C_IN(C_FLAG),
.F_IN(F_FLAG),
.OUT(ALU_OUT),
.C_OUT(C_OUT),
.F_OUT(F_OUT)
);
MEM MEM (
.CLK_MEM(CLKS[3]),
.REG_A(REG_A),
.ADDR(ALU_OUT),
.Q(DATA)
);
REG_WB REG_WB (
.CLK_WB(CLKS[4]),
.REG_WRITE(REG_WRITE),
.F_FLAG(F_FLAG),
.INOUT_FLAG(INOUT_FLAG),
.INT_FLAG_OUT(INT_FLAG_OUT),
.PC(ADDR),
.REG_A_ADDR(REG_A_ADDR),
.MODE(MODE),
.JUMP_MODE(JUMP_MODE),
.REG_O_TYPE(REG_O_TYPE),
.DATA(DATA),
.INPUT(INPUT),
.NEXT(NEXT),
.REG_R_OUT(REG_R),
.REG_IO_OUT(REG_IO),
.REG_INT_FLAG_OUT(REG_INT)
);
INPUT_INT INPUT_0 (
.CLK(CLKS[4]),
.INPUT(INPUT[7:0]),
.INT_NO(4'd0),
.REG_INT(REG_INT[7:0]),
.INT_FLAG(INT_FLAG_OUT[0])
);
INPUT_INT INPUT_1 (
.CLK(CLKS[4]),
.INPUT(INPUT[15:8]),
.INT_NO(4'd1),
.REG_INT(REG_INT[15:8]),
.INT_FLAG(INT_FLAG_OUT[1])
);
INPUT_INT INPUT_2 (
.CLK(CLKS[4]),
.INPUT(INPUT[23:16]),
.INT_NO(4'd2),
.REG_INT(REG_INT[23:16]),
.INT_FLAG(INT_FLAG_OUT[2])
);
INPUT_INT INPUT_3 (
.CLK(CLKS[4]),
.INPUT(INPUT[31:24]),
.INT_NO(4'd3),
.REG_INT(REG_INT[31:24]),
.INT_FLAG(INT_FLAG_OUT[3])
);
TIMER_INT TIMER_0 (
.CLK_WB (CLKS[4]),
.REG_INT (REG_INT[39:32]),
.INT_FLAG(INT_FLAG_OUT[4])
);
TIMER_INT TIMER_1 (
.CLK_WB (CLKS[4]),
.REG_INT (REG_INT[47:40]),
.INT_FLAG(INT_FLAG_OUT[5])
);
TIMER_INT TIMER_2 (
.CLK_WB (CLKS[4]),
.REG_INT (REG_INT[55:48]),
.INT_FLAG(INT_FLAG_OUT[6])
);
TIMER_INT TIMER_3 (
.CLK_WB (CLKS[4]),
.REG_INT (REG_INT[63:56]),
.INT_FLAG(INT_FLAG_OUT[7])
);
endmodule
| 6.94234 |
module ayush_and_gate (
out,
a,
b
);
input a, b;
output reg out;
always @(a, b) begin
out = a & b;
end
endmodule
| 7.307613 |
module ay_model_channel // one of three identical AY channels
(
input wire f1, //
input wire _f1, // clock phases
input wire cnt_clk, //
input wire rst_1, // reset
input wire reg_wr, // common write/store strobes
input wire _reg_wr,
input wire sel_tone_lo, // select for tone low register
input wire sel_tone_hi, // tone high
input wire sel_vol, // volume register
inout wire [7:0] b, // internal AY bidir bus
input wire _noise_en, // from mixer register
input wire _tone_en, //
input wire [3:0] e, // from envelope generator
input wire noise, // from noise generator
output wire [3:0] sound // output data, 0 -- cutoff, 1..15 -- corresponding DAC values
);
wire [ 3:0] volume;
wire env_ena;
wire [11:0] period;
wire [11:0] _period;
wire tone;
wire snd;
/* volume latch */
ay_model_rw_latch #(
.WIDTH(4)
) volume_reg (
.gate (sel_vol),
.write(reg_wr),
.store(_reg_wr),
.d (b[3:0]),
.q (volume),
._q()
);
/* env enable latch */
ay_model_rw_latch #(
.WIDTH(1)
) env_reg (
.gate (sel_vol),
.write(reg_wr),
.store(_reg_wr),
.d (b[4]),
.q (env_ena),
._q()
);
/* period low latch */
ay_model_rw_latch #(
.WIDTH(8)
) period_low_reg (
.gate (sel_tone_lo),
.write(reg_wr),
.store(_reg_wr),
.d (b),
.q (period[7:0]),
._q(_period[7:0])
);
/* period high latch */
ay_model_rw_latch #(
.WIDTH(4)
) period_high_reg (
.gate (sel_tone_hi),
.write(reg_wr),
.store(_reg_wr),
.d (b[3:0]),
.q (period[11:8]),
._q(_period[11:8])
);
/* SND_* signal */
wire int_noise_gated;
wire int_tone_gated;
assign int_noise_gated = ~(noise | _noise_en);
assign int_tone_gated = ~(tone | _tone_en);
assign snd = ~(int_noise_gated | int_tone_gated);
/* DAC output */
wire [3:0] int_volume;
wire [3:0] int_volume_n;
wire int_snd_n;
assign int_volume = env_ena ? e : volume;
assign int_volume_n = ~int_volume;
assign int_snd_n = ~snd;
assign sound = ~(int_volume_n |{4{int_snd_n}});
/* period counter */
wire carry_out;
wire tone_latch_up_phase;
wire tone_latch_dn_phase;
wire counter_rst;
// clock conditioning flipflop
ay_model_rs_ff clk_conditioning (
.reset(_f1),
.set (rst_1 | (cnt_clk & carry_out)),
.q (tone_latch_up_phase),
._q(tone_latch_dn_phase)
);
// tone output latch
ay_model_clk_ff tone_output (
.up_phase(tone_latch_up_phase),
.dn_phase(tone_latch_dn_phase),
.set(1'b0),
.rst(rst_1),
.q_up(tone),
.q_dn()
);
// period counter reset
assign counter_rst = ~tone_latch_dn_phase;
ay_model_counter #(
.WIDTH(12)
) channel_counter (
.f1 (f1),
._f1(_f1),
.rst(counter_rst),
.period (period),
._period(_period),
.carry_out(carry_out)
);
endmodule
| 8.127227 |
module ay_model_gpio // one of two identical AY gpio ports
(
inout wire [7:0] b,
inout tri1 [7:0] io,
input wire _reg_wr,
input wire wr_reg_1,
input wire _r7_b_1,
input wire _en_reg_rd
);
wire [7:0] int_output;
ay_model_latch out_latch (
.d(b),
.load(wr_reg_1),
.store(_reg_wr),
.q(int_output),
._q()
);
assign io = _r7_b_1 ? 8'hZZ : int_output; // out data
assign b = _en_reg_rd ? 8'hZZ : io; // in data
endmodule
| 6.509412 |
module ay_model_clk_ff // clock flipflop
#(
parameter UP_RST = 1
) (
input wire up_phase, // upper (on schematics) phase
input wire dn_phase, // lower (on schematics) phase
input wire set, // upper gate clear signal
input wire rst,
output reg q_up, // upper and lower (on schematics) outputs
output reg q_dn //
);
trireg up_store; // modelled passgates that feed NAND inputs of main gates
trireg dn_store; //
wire int_up_rst;
assign int_up_rst = UP_RST ? rst : 1'b0;
assign up_store = int_up_rst ? 1'b0 : (dn_phase ? q_up : 1'bZ);
assign dn_store = dn_phase ? q_dn : 1'bZ;
always @* q_up <= #0.01 (~q_dn) & (~set) & (~(up_phase & up_store)) & (~(int_up_rst & dn_phase));
always @* q_dn <= #0.01 (~q_up) & (~rst) & (~(dn_store & up_phase));
endmodule
| 8.220087 |
module ay_model_latch // 2-phase latch
#(
parameter WIDTH = 8
) (
input wire load, // when 1, latch is transparent
input wire store, // when 1, latch stores its last value
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q,
output wire [WIDTH-1:0] _q
);
trireg [WIDTH-1:0] inwire;
assign inwire = load ? d : {WIDTH{1'bZ}};
assign inwire = store ? q : {WIDTH{1'bZ}};
assign _q = ~inwire;
assign q = ~_q;
endmodule
| 8.729969 |
module ay_model_rw_latch // readable and writable latch
#(
parameter WIDTH = 8
) (
input wire gate, // input gating
input wire write, // write strobe (REG_WR on schematics)
input wire store, // store strobe (/REG_WR on schematics)
inout wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q,
output wire [WIDTH-1:0] _q
);
wire d_oe;
assign d = d_oe ? q : {WIDTH{1'bZ}};
assign d_oe = store & gate;
assign _q = ~q;
always @* if (gate && write) q <= d;
endmodule
| 8.361155 |
module ay_model_counter // async resettable counter with a comparator
#(
parameter WIDTH = 0
) (
input wire f1,
input wire _f1, // clocking phases
input wire rst, // async reset
input wire [WIDTH-1:0] period,
input wire [WIDTH-1:0] _period, // inverse copy of period
output wire carry_out // 1 when counter value is greater than period
);
wire [ WIDTH-1:0] cnt_up;
wire [ WIDTH-1:0] cnt_dn;
wire [ WIDTH-1:0] i;
wire [WIDTH-1:-1] c;
genvar g;
// first flipflop
ay_model_clk_ff #(
.UP_RST(0)
) counter_bit_0 (
.up_phase(_f1),
.dn_phase(f1),
.set(1'b0),
.rst(rst),
.q_up(cnt_up[0]),
.q_dn(cnt_dn[0])
);
// remaining flipflops
generate
begin
for (g = 1; g < WIDTH; g = g + 1) begin : counter_bits
ay_model_clk_ff counter_bit (
.up_phase(cnt_up[g-1]),
.dn_phase(cnt_dn[g-1]),
.set(1'b0),
.rst(rst),
.q_up(cnt_up[g]),
.q_dn(cnt_dn[g])
);
end
end
endgenerate
// carry propagation (carry_out=1 when counter>=period)
assign c[-1] = 1'b1;
assign i[WIDTH-1:0] = ~(c[WIDTH-2:-1] | (cnt_dn & _period));
assign c[WIDTH-1:0] = ~(i | (cnt_up & period));
assign carry_out = c[WIDTH-1];
endmodule
| 9.090441 |
module ay_model_shiftreg #(
parameter WIDTH = 17
) (
input wire _f,
input wire f,
input wire rst,
input wire shift_in,
output wire [WIDTH-1:0] result
);
wire [WIDTH-1:0] shin;
trireg [WIDTH-1:0] l1;
trireg [WIDTH-1:0] l2;
// shift in
assign shin = {l2[WIDTH-2:0], shift_in};
assign l1 = rst ? {WIDTH{1'b0}} : (_f ? shin : {WIDTH{1'bZ}});
assign l2 = f ? l1 : {WIDTH{1'bZ}};
assign result = l2;
endmodule
| 8.540725 |
module ay_note_ram (
addr,
data
);
input wire [6:0] addr;
output wire [11:0] data; //12 бит - максимум
reg [11:0] note_ram[0:127];
initial begin
note_ram[0] <= 12'd03977;
note_ram[1] <= 12'd03977;
note_ram[2] <= 12'd03977;
note_ram[3] <= 12'd03977;
note_ram[4] <= 12'd03977;
note_ram[5] <= 12'd03977;
note_ram[6] <= 12'd03977;
note_ram[7] <= 12'd03977;
note_ram[8] <= 12'd03977;
note_ram[9] <= 12'd03977;
note_ram[10] <= 12'd03977;
note_ram[11] <= 12'd03977;
note_ram[12] <= 12'd03977;
note_ram[13] <= 12'd03977;
note_ram[14] <= 12'd03977;
note_ram[15] <= 12'd03977;
note_ram[16] <= 12'd03977;
note_ram[17] <= 12'd03977;
note_ram[18] <= 12'd03977;
note_ram[19] <= 12'd03977;
note_ram[20] <= 12'd03977;
note_ram[21] <= 12'd03977;
note_ram[22] <= 12'd03754;
note_ram[23] <= 12'd03543;
note_ram[24] <= 12'd03344;
note_ram[25] <= 12'd03157;
note_ram[26] <= 12'd02980;
note_ram[27] <= 12'd02812;
note_ram[28] <= 12'd02655;
note_ram[29] <= 12'd02506;
note_ram[30] <= 12'd02365;
note_ram[31] <= 12'd02232;
note_ram[32] <= 12'd02107;
note_ram[33] <= 12'd01989;
note_ram[34] <= 12'd01877;
note_ram[35] <= 12'd01772;
note_ram[36] <= 12'd01672;
note_ram[37] <= 12'd01578;
note_ram[38] <= 12'd01490;
note_ram[39] <= 12'd01406;
note_ram[40] <= 12'd01327;
note_ram[41] <= 12'd01253;
note_ram[42] <= 12'd01182;
note_ram[43] <= 12'd01116;
note_ram[44] <= 12'd01053;
note_ram[45] <= 12'd0994;
note_ram[46] <= 12'd0939;
note_ram[47] <= 12'd0886;
note_ram[48] <= 12'd0836;
note_ram[49] <= 12'd0789;
note_ram[50] <= 12'd0745;
note_ram[51] <= 12'd0703;
note_ram[52] <= 12'd0664;
note_ram[53] <= 12'd0626;
note_ram[54] <= 12'd0591;
note_ram[55] <= 12'd0558;
note_ram[56] <= 12'd0527;
note_ram[57] <= 12'd0497;
note_ram[58] <= 12'd0469;
note_ram[59] <= 12'd0443;
note_ram[60] <= 12'd0418;
note_ram[61] <= 12'd0395;
note_ram[62] <= 12'd0372;
note_ram[63] <= 12'd0352;
note_ram[64] <= 12'd0332;
note_ram[65] <= 12'd0313;
note_ram[66] <= 12'd0296;
note_ram[67] <= 12'd0279;
note_ram[68] <= 12'd0263;
note_ram[69] <= 12'd0249;
note_ram[70] <= 12'd0235;
note_ram[71] <= 12'd0221;
note_ram[72] <= 12'd0209;
note_ram[73] <= 12'd0197;
note_ram[74] <= 12'd0186;
note_ram[75] <= 12'd0176;
note_ram[76] <= 12'd0166;
note_ram[77] <= 12'd0157;
note_ram[78] <= 12'd0148;
note_ram[79] <= 12'd0140;
note_ram[80] <= 12'd0132;
note_ram[81] <= 12'd0124;
note_ram[82] <= 12'd0117;
note_ram[83] <= 12'd0111;
note_ram[84] <= 12'd0105;
note_ram[85] <= 12'd099;
note_ram[86] <= 12'd093;
note_ram[87] <= 12'd088;
note_ram[88] <= 12'd083;
note_ram[89] <= 12'd078;
note_ram[90] <= 12'd074;
note_ram[91] <= 12'd070;
note_ram[92] <= 12'd066;
note_ram[93] <= 12'd062;
note_ram[94] <= 12'd059;
note_ram[95] <= 12'd055;
note_ram[96] <= 12'd052;
note_ram[97] <= 12'd049;
note_ram[98] <= 12'd047;
note_ram[99] <= 12'd044;
note_ram[100] <= 12'd041;
note_ram[101] <= 12'd039;
note_ram[102] <= 12'd037;
note_ram[103] <= 12'd035;
note_ram[104] <= 12'd033;
note_ram[105] <= 12'd031;
note_ram[106] <= 12'd029;
note_ram[107] <= 12'd028;
note_ram[108] <= 12'd026;
note_ram[109] <= 12'd025;
note_ram[110] <= 12'd023;
note_ram[111] <= 12'd022;
note_ram[112] <= 12'd021;
note_ram[113] <= 12'd020;
note_ram[114] <= 12'd018;
note_ram[115] <= 12'd017;
note_ram[116] <= 12'd016;
note_ram[117] <= 12'd016;
note_ram[118] <= 12'd015;
note_ram[119] <= 12'd014;
note_ram[120] <= 12'd013;
note_ram[121] <= 12'd012;
note_ram[122] <= 12'd012;
note_ram[123] <= 12'd011;
note_ram[124] <= 12'd010;
note_ram[125] <= 12'd010;
note_ram[126] <= 12'd09;
note_ram[127] <= 12'd09;
end
assign data = note_ram[addr];
endmodule
| 6.655261 |
module hazard_f (
input wire a,
input wire b,
output wire f
);
assign f = ~a & b | a & b;
endmodule
| 6.577595 |
module hazard_e #(
// Retraso por defecto para las operaciones lógicas
/* Dentro de un módulo se pueden definir "parámetros". Los parámetros
* son constantes que pueden usarse dentro del módulo para facilitar el
* diseño. A diferencia de las macros declaradas con "`define", los
* parámetros son elementos del módulo en que se definen y no meras
* directivas para el compilador. El valor definido para un parámetro
* con "parameter" es un valor por defecto que puede redefinirse para
* cada instancia del módulo. */
parameter delay = 5
) (
input wire a,
input wire b,
output wire f
);
// Señales intermedias
wire x, y, z;
// Descripción estructural con puertas lógicas. Todas las puertas
// tienen el mismo retraso, tomado del parámetro "delay".
/* Verilog permite indicar el retraso de la puerta usando la construcción
* "#<delay_spec>" antes del nombre de la instancia. "<delay_spec>" puede
* tener distintos formatos:
* x: un número. Indica el retraso en unidades de tiempo.
* (x,y): indica retrasos subida (salida cambia a 1) y de bajada
* (salida cambia a 0) diferenciados.
* (x,y,z): indica retraso de subida, bajada, y cambio a desconexión
* (alta impedancia) diferenciados.
* A su vez, cada número, puede convertirse en una terna de valores
* separados por ":" para indicar valores mínimo, típico y máximo del
* retraso respectivamente. Ej: "#(1:2:3,2:4:5)". */
not #delay inv (x, a);
and #delay and1 (y, a, b);
and #delay and2 (z, x, b);
or #delay or1 (f, y, z);
endmodule
| 9.031604 |
module: Az_toLSP_FSM
// Dependencies: L_mac.v, L_msu.v,L_shl,L_sub,add,mult,norm_s
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Az_LSP_Test_v;
`include "paramList.v"
// Inputs
reg clk;
reg reset;
reg start;
reg lspMuxSel;
reg [11:0] testReadRequested;
//mux1 regs
reg [11:0] testWriteRequested;
//mux2 regs
reg [31:0] testLspOut;
//mux3regs
reg testLspWrite;
//Outputs
wire [31:0] lspIn;
//working regs
reg [15:0] aSubI_in [0:9999];
reg [15:0] lspOutMem [0:9999];
integer i,j;
//file read in for inputs and output tests
initial
begin// samples out are samples from ITU G.729 test vectors
$readmemh("lsp_az_lsp_in.out", aSubI_in);
$readmemh("lsp_az_lsp_out.out", lspOutMem);
end
// Instantiate the Unit Under Test (UUT)
Az_LSP_Top uut(
.clk(clk),
.reset(reset),
.start(start),
.lspMuxSel(lspMuxSel),
.testReadRequested(testReadRequested),
.testWriteRequested(testWriteRequested),
.testLspOut(testLspOut),
.testLspWrite(testLspWrite),
.done(done),
.lspIn(lspIn)
);
initial begin
// Initialize Input
#100;
clk = 0;
reset = 0;
start = 0;
testReadRequested = 0;
testWriteRequested = 0;
testLspWrite = 0;
lspMuxSel = 0;
testLspOut = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
// Wait 100 ns for global reset to finish
@(posedge clk);
@(posedge clk) #5;
reset = 1;
@(posedge clk);
@(posedge clk) #5;
reset = 0;
@(posedge clk);
@(posedge clk) #5;
for(j=0;j<120;j=j+1)
begin
@(posedge clk);
@(posedge clk) #5;
//writing the previous modules to memory
lspMuxSel = 0;
for(i=0;i<11;i=i+1)
begin
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
lspMuxSel = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5; //Added Delay BY PARKER
testWriteRequested = {A_T_HIGH[10:4],i[3:0]};
testLspOut = aSubI_in[j*11+i];
testLspWrite = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
end
lspMuxSel = 0;
start = 1;
@(posedge clk);
@(posedge clk) #5;
start = 0;
@(posedge clk);
@(posedge clk) #5;
// Add stimulus here
wait(done);
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
lspMuxSel = 1;
for (i = 0; i<10;i=i+1)
begin
testReadRequested = {LSP_NEW[10:4],i[3:0]};
@(posedge clk);
@(posedge clk) #5;
if (lspIn != lspOutMem[10*j+i])
$display($time, " ERROR: lsp[%d] = %x, expected = %x", 10*j+i, lspIn, lspOutMem[10*j+i]);
else if (lspIn == lspOutMem[10*j+i])
$display($time, " CORRECT: lsp[%d] = %x", 10*j+i, lspIn);
@(posedge clk) #5;
end
end// for loop j
end//initial
initial forever #10 clk = ~clk;
endmodule
| 7.260268 |
module a_4 (
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
key,
dout
);
input [31:0] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
input [127:0] key;
output [127:0] dout;
//col 1
a col_00 (
.dout(dout[127:120]),
.r0 (R0[31:24]),
.r1 (R1[7:0]),
.r2 (R2[15:8]),
.r3 (R3[23:16]),
.key (key[127:120])
);
a col_10 (
.dout(dout[119:112]),
.r0 (R0[23:16]),
.r1 (R1[31:24]),
.r2 (R2[7:0]),
.r3 (R3[15:8]),
.key (key[119:112])
);
a col_20 (
.dout(dout[111:104]),
.r0 (R0[15:8]),
.r1 (R1[23:16]),
.r2 (R2[31:24]),
.r3 (R3[7:0]),
.key (key[111:104])
);
a col_30 (
.dout(dout[103:96]),
.r0 (R0[7:0]),
.r1 (R1[15:8]),
.r2 (R2[23:16]),
.r3 (R3[31:24]),
.key (key[103:96])
);
//col 2
a col_01 (
.dout(dout[95:88]),
.r0 (R4[31:24]),
.r1 (R5[7:0]),
.r2 (R6[15:8]),
.r3 (R7[23:16]),
.key (key[95:88])
);
a col_11 (
.dout(dout[87:80]),
.r0 (R4[23:16]),
.r1 (R5[31:24]),
.r2 (R6[7:0]),
.r3 (R7[15:8]),
.key (key[87:80])
);
a col_21 (
.dout(dout[79:72]),
.r0 (R4[15:8]),
.r1 (R5[23:16]),
.r2 (R6[31:24]),
.r3 (R7[7:0]),
.key (key[79:72])
);
a col_31 (
.dout(dout[71:64]),
.r0 (R4[7:0]),
.r1 (R5[15:8]),
.r2 (R6[23:16]),
.r3 (R7[31:24]),
.key (key[71:64])
);
//col 3
a col_02 (
.dout(dout[63:56]),
.r0 (R8[31:24]),
.r1 (R9[7:0]),
.r2 (R10[15:8]),
.r3 (R11[23:16]),
.key (key[63:56])
);
a col_12 (
.dout(dout[55:48]),
.r0 (R8[23:16]),
.r1 (R9[31:24]),
.r2 (R10[7:0]),
.r3 (R11[15:8]),
.key (key[55:48])
);
a col_22 (
.dout(dout[47:40]),
.r0 (R8[15:8]),
.r1 (R9[23:16]),
.r2 (R10[31:24]),
.r3 (R11[7:0]),
.key (key[47:40])
);
a col_32 (
.dout(dout[39:32]),
.r0 (R8[7:0]),
.r1 (R9[15:8]),
.r2 (R10[23:16]),
.r3 (R11[31:24]),
.key (key[39:32])
);
//col 4
a col_03 (
.dout(dout[31:24]),
.r0 (R12[31:24]),
.r1 (R13[7:0]),
.r2 (R14[15:8]),
.r3 (R15[23:16]),
.key (key[31:24])
);
a col_13 (
.dout(dout[23:16]),
.r0 (R12[23:16]),
.r1 (R13[31:24]),
.r2 (R14[7:0]),
.r3 (R15[15:8]),
.key (key[23:16])
);
a col_23 (
.dout(dout[15:8]),
.r0 (R12[15:8]),
.r1 (R13[23:16]),
.r2 (R14[31:24]),
.r3 (R15[7:0]),
.key (key[15:8])
);
a col_33 (
.dout(dout[7:0]),
.r0 (R12[7:0]),
.r1 (R13[15:8]),
.r2 (R14[23:16]),
.r3 (R15[31:24]),
.key (key[7:0])
);
endmodule
| 6.66563 |
module a_block (
sum,
gen,
prop,
c_in,
a,
b
);
input a, b, c_in;
output sum, gen, prop;
wire w;
or (prop, a, b);
and (gen, a, b);
xor (w, a, b);
xor (sum, w, c_in);
endmodule
| 6.533783 |
module a_compress (
input clk,
input iq,
input signed [17:0] d_in,
output signed [17:0] d_out,
// Adjust saturation characteristics
(*external*)
input [15:0] sat_ctl // external
);
// Pipeline match
// "Free" spot for multiplier for overall gain setting (no added latency)
wire signed [17:0] m1;
reg_delay #(
.dw (18),
.len(9)
) match (
.clk (clk),
.reset(1'b0),
.gate (1'b1),
.din (d_in),
.dout (m1)
);
// Magnitude-square of the input
wire signed [18:0] mag2;
mag_square square (
.clk(clk),
.iq(iq),
.d_in(d_in),
.mag2_out(mag2)
);
// mag2 is guaranteed positive!
// Now find an approximate 1/(1+mag2)
// See a_comp.m
reg signed [18:0] gain = 0;
reg signed [35:0] quad1 = 0;
wire signed [17:0] quad1s = quad1[34:17];
reg signed [17:0] quad2 = 0, quad3 = 0;
reg [18:0] mag3 = 0, mag4 = 0, mag5 = 0;
wire quad_sel = mag4[17];
reg signed [19:0] line1 = 0;
always @(posedge clk) begin
mag3 <= mag2;
mag4 <= mag3;
mag5 <= mag4; // just to match quad pipeline
line1 <= (mag3 >>> 1) - 32768;
quad1 <= $signed(mag2[18:1]) * $signed(mag2[18:1]);
quad2 <= quad1s;
quad3 <= quad_sel ? line1 : quad2;
gain <= 163840 + sat_ctl - mag5 + quad3;
end
// Apply the gain function to the (delayed) input
reg signed [35:0] prod1 = 0;
wire signed [17:0] prod1s = prod1[33:16];
reg signed [17:0] prod2 = 0;
always @(posedge clk) begin
prod1 <= m1 * $signed({1'b0, gain[17:1]});
prod2 <= prod1s;
end
assign d_out = prod2;
endmodule
| 6.90251 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end else if (J == 0 & K == 1) begin
Q <= 0;
NQ <= 1;
end else begin
Q <= ~Q;
NQ <= ~NQ;
end
end
endmodule
| 6.615218 |
module a_filter_reference_32x11 (
input [31:0] x_in,
input clk,
input [5:0] reset,
output [31:0] y_out
);
wire [10:0] a1_1;
wire [10:0] a1_2;
wire [10:0] a1_3;
wire [10:0] a1_4;
wire [10:0] b1;
// update coefficent
// h_fixp(i) = sign(h_fixp(i))*floor(abs(h_fixp(i))/M)*M;
assign a1_1 = -11'sd208;
assign a1_2 = -11'sd1021;
assign a1_3 = -11'sd930;
assign a1_4 = -11'sd1010;
assign b1 = 11'sd307;
wire [31:0] y_1;
wire [31:0] y_2;
wire [31:0] y_3;
wire [31:0] y_4;
wire [31:0] y_5;
//First stage
fos_exact_v4 first_stage (
x_in,
a1_4,
clk,
reset[0],
y_1
);
//Second stage
fos_exact_v3 second_stage (
y_1,
a1_3,
b1,
clk,
reset[1],
y_2
);
//Third stage
fos_exact_v2 third_stage (
y_2,
a1_2,
clk,
reset[2],
y_3
);
//Fourth stage
fos_exact_v2 fourth_stage (
y_3,
a1_2,
clk,
reset[3],
y_4
);
//Fifth stage
fos_exact_v1 fifth_stage (
y_4,
a1_1,
clk,
reset[4],
y_5
);
//Sixth stage
fos_exact_v1 sixth_stage (
y_5,
a1_1,
clk,
reset[5],
y_out
);
endmodule
| 6.772869 |
module a_filter_reference_32x32 (
input [31:0] x_in,
input clk,
input [5:0] reset,
output [31:0] y_out
);
wire [31:0] a1_1;
wire [31:0] a1_2;
wire [31:0] a1_3;
wire [31:0] a1_4;
wire [31:0] b1;
// update coefficent
// h_fixp(i) = sign(h_fixp(i))*floor(abs(h_fixp(i))/M)*M;
assign a1_1 = -32'sd208;
assign a1_2 = -32'sd1021;
assign a1_3 = -32'sd930;
assign a1_4 = -32'sd1010;
assign b1 = 32'sd307;
wire [31:0] y_1;
wire [31:0] y_2;
wire [31:0] y_3;
wire [31:0] y_4;
wire [31:0] y_5;
//First stage
fos_exact_v4 first_stage (
x_in,
a1_4,
clk,
reset[0],
y_1
);
//Second stage
fos_exact_v3 second_stage (
y_1,
a1_3,
b1,
clk,
reset[1],
y_2
);
//Third stage
fos_exact_v2 third_stage (
y_2,
a1_2,
clk,
reset[2],
y_3
);
//Fourth stage
fos_exact_v2 fourth_stage (
y_3,
a1_2,
clk,
reset[3],
y_4
);
//Fifth stage
fos_exact_v1 fifth_stage (
y_4,
a1_1,
clk,
reset[4],
y_5
);
//Sixth stage
fos_exact_v1 sixth_stage (
y_5,
a1_1,
clk,
reset[5],
y_out
);
endmodule
| 6.772869 |
module a_input_register (
load_zero,
load_sb,
zero,
sb,
a_out
);
input load_zero; //net: 984; aka zero_add
input load_sb; //net: 549; aka sb_add
input [7:0] zero; //all zeros
input [7:0] sb; //special data bus
output reg [7:0] a_out; //goes to the alu
always @(*) begin
if (load_zero) a_out <= zero;
else if (load_sb) a_out <= sb;
end
endmodule
| 7.009598 |
module alu (
ALU_out,
Carry_out,
A,
B,
ALU_sel,
clk
);
parameter n = 32;
input [n-1:0] A, B;
input [2:0] ALU_sel;
input clk;
output [n-1:0] ALU_out;
output Carry_out;
reg [n-1:0] ALU_result;
wire [n:0] temp, prod;
assign ALU_out = ALU_result;
assign temp = {1'b0, A} + {1'b0, B};
assign Carry_out = temp[n];
always @(*) begin
case (ALU_sel)
3'b000: ALU_result = A + B;
3'b001: ALU_result = A - B;
3'b010: ALU_result = prod;
3'b011: ALU_result = A / B;
3'b100: ALU_result = A << B;
3'b101: ALU_result = A >> B;
3'b110: ALU_result = A & B;
3'b111: ALU_result = A | B;
default: ALU_result = A + B;
endcase
end
booth_multiplier mul (
prod,
A,
B,
clk,
(ALU_sel == 3'b010)
);
endmodule
| 7.764211 |
module booth_multiplier (
ans,
m,
q,
clk,
start
);
parameter n = 16;
input [n-1:0] m, q;
output reg [2*n-1:0] ans;
input clk, start;
reg [2:0] state;
reg [5:0] cnt;
reg [n-1:0] ab, qb;
reg qm1;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
always @(posedge clk) begin
case (state)
s0: if (start) state = s1;
s1: begin
ab = 0;
cnt = n;
qb = q;
qm1 = 0;
state = s2;
end
s2: begin
if ({qb[0], qm1} == 2'b10) begin
ab = ab - m;
state = s3;
end else if ({qb[0], qm1} == 2'b01) begin
ab = ab + m;
state = s3;
end else begin
state = s3;
end
end
s3: begin
{ab, qb, qm1} = {qb[0], ab, qb};
cnt = cnt - 1;
if (|cnt) state = s2;
else state = s4;
end
s4: begin
ans = {ab, qb};
state = s5;
end
s5: state = s5;
default: state = s0;
endcase
end
endmodule
| 6.943306 |
module a_model (
input clk,
input [1:0] subcycle,
input signed [17:0] coeff,
input signed [17:0] drive,
output signed [17:0] cavity,
output error
);
// subcycle = 2 coeff = drive coupling, drive input is valid
// subcycle = 3 coeff = cavity decay bandwidth
// subcycle = 0 or 1 other inputs are don't care
parameter shift = 3;
// As usual, negative-full-scale coeff is considered invalid
reg signed [17+shift:0] cavity_r = 0;
wire signed [17:0] m_in = subcycle[0] ? (cavity_r >>> shift) : drive;
wire signed [35:0] m_result = m_in * coeff;
wire signed [17:0] m_result_s = m_result[34:17];
reg carry = 0, error_r = 0;
// XXX pipelining needs work
always @(posedge clk)
if (subcycle[1]) begin
{carry, cavity_r} <= cavity_r + m_result_s;
error_r <= carry != (cavity_r[17+shift]) | (m_result[35] != m_result[34]);
end
assign cavity = cavity_r >>> shift;
assign error = error_r;
endmodule
| 6.840715 |
module a_port_unit (
clk_core,
rst_x,
// port side
i_req,
i_we,
i_len,
o_ack,
i_strw,
o_ackw,
o_strr,
o_dbr,
// internal
i_cack,
o_wdata_read_end,
i_wdata_ack,
i_strr,
i_dbr
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_SIDLE = 1'b0;
parameter P_SDOUT = 1'b1;
////////////////////////////
// I/O definitions
////////////////////////////
input i_req; // command request
input i_we; // write enable
input [P_IB_LEN_WIDTH-1:0] i_len; // burst length
output o_ack; // command acknowledge
input i_strw; // write data strobe
output o_ackw; // write data acknowledge
output o_strr; // read data strobe
output [P_IB_DATA_WIDTH-1:0] o_dbr; // read data
input i_cack; // command acknowledge
output o_wdata_read_end; // write data end
input i_wdata_ack; // write data acknowledge
input i_strr; // read data strobe
input [P_IB_DATA_WIDTH-1:0] i_dbr; // read data
input clk_core; // system clock
input rst_x; // system reset
/////////////////////////
// register definition
/////////////////////////
reg r_state;
reg [ P_IB_LEN_WIDTH-1:0] r_len;
reg r_strr;
reg [P_IB_DATA_WIDTH-1:0] r_dbr;
/////////////////////////
// wire definition
/////////////////////////
wire w_accept;
wire w_not_burst;
wire w_idle_state;
wire w_wdata_ack;
/////////////////////////
// assign statement
/////////////////////////
assign w_accept = i_req & i_cack & i_we;
assign w_not_burst = !i_we | (i_len == 1);
assign w_idle_state = (r_state == P_SIDLE);
// output port connection
assign o_ack = (i_req) ? i_cack : 1'b1;
assign w_wdata_ack = (i_req) ? i_cack & i_wdata_ack : 1'b1;
assign o_ackw = (w_idle_state) ? w_wdata_ack : i_wdata_ack;
assign o_wdata_read_end = (w_idle_state) ? (i_strw & w_not_burst & i_wdata_ack) :
(i_strw & (r_len == 1) & i_wdata_ack);
assign o_strr = r_strr;
assign o_dbr = r_dbr;
/////////////////////////
// always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_SIDLE;
end else begin
case (r_state)
P_SIDLE: begin
if (w_accept & !w_not_burst) begin
r_state <= P_SDOUT;
end
end
P_SDOUT: begin
if (o_wdata_read_end) begin
r_state <= P_SIDLE;
end
end
default: r_state <= r_state;
endcase
end
end
// set input data
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_len <= 1;
end else begin
if (w_accept) begin
r_len <= i_len - 1'b1;
end else if (i_strw & i_wdata_ack) begin
r_len <= r_len - 1'b1;
end
end
end
// read data
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_strr <= 1'b0;
end else begin
r_strr <= i_strr;
end
end
always @(posedge clk_core) begin
r_dbr <= i_dbr;
end
endmodule
| 7.91759 |
module A_reg (
clk,
a,
a_reg
);
input clk;
input [31:0] a;
output reg [31:0] a_reg;
always @(posedge clk) a_reg <= a;
endmodule
| 7.85871 |
module A_reg_module (
clk,
read_data1_in,
read_data1_out
);
input clk;
input [31:0] read_data1_in;
output [31:0] read_data1_out;
reg [31:0] read_data1_out;
always @(posedge clk) read_data1_out <= read_data1_in;
endmodule
| 7.124601 |
module a_up_counter (
L,
clk
);
input clk;
output [3:0] L;
wire qbar;
JK_FF ff1 (
1,
1,
L[0],
qbar,
clk
);
JK_FF ff2 (
1,
1,
L[1],
qbar,
~L[0]
);
JK_FF ff3 (
1,
1,
L[2],
qbar,
~L[1]
);
JK_FF ff4 (
1,
1,
L[3],
qbar,
~L[2]
);
endmodule
| 6.723838 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end else if (J == 0 & K == 1) begin
Q <= 0;
NQ <= 1;
end else begin
Q <= ~Q;
NQ <= ~NQ;
end
end
endmodule
| 6.615218 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b01_comb/b01_comb.opt (
line1_pad,
line2_pad,
\stato_reg[0]/NET0131 ,
\stato_reg[1]/NET0131 ,
\stato_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g220/_2_ ,
\g221/_0_ ,
\g222/_0_ ,
\g224/_0_ ,
\g44/_1_
);
input line1_pad, line2_pad, \stato_reg[0]/NET0131 ,
\stato_reg[1]/NET0131 , \stato_reg[2]/NET0131 ;
output _al_n0, _al_n1, \g220/_2_ , \g221/_0_ , \g222/_0_ , \g224/_0_ , \g44/_1_ ;
wire new_n15_, new_n16_, new_n17_, new_n18_, new_n19_, new_n20_, new_n21_,
new_n23_, new_n24_, new_n25_, new_n26_, new_n29_;
assign \g220/_2_ = ~new_n15_ | new_n19_ | new_n20_;
assign new_n15_ = ~new_n16_ & (~new_n18_ | (~new_n17_ & ~\stato_reg[0]/NET0131 ));
assign new_n16_ = \stato_reg[0]/NET0131 ? (\stato_reg[2]/NET0131 & ~\stato_reg[1]/NET0131 ) : (~\stato_reg[2]/NET0131 & \stato_reg[1]/NET0131 );
assign new_n17_ = line1_pad & line2_pad;
assign new_n18_ = \stato_reg[1]/NET0131 & \stato_reg[2]/NET0131 & (line2_pad | line1_pad);
assign new_n19_ = \stato_reg[0]/NET0131 & ~\stato_reg[2]/NET0131 & ~new_n17_ & ~\stato_reg[1]/NET0131 ;
assign new_n20_ = \stato_reg[2]/NET0131 & new_n21_ & ~\stato_reg[0]/NET0131 & ~\stato_reg[1]/NET0131 ;
assign new_n21_ = ~line1_pad & ~line2_pad;
assign \g221/_0_ = new_n26_ | new_n23_ | (~new_n21_ & new_n24_);
assign new_n23_ = new_n17_ & ((\stato_reg[1]/NET0131 & ~\stato_reg[0]/NET0131 ) | (~\stato_reg[2]/NET0131 & ~\stato_reg[1]/NET0131 & \stato_reg[0]/NET0131 ));
assign new_n24_ = ~new_n25_ & \stato_reg[2]/NET0131 ;
assign new_n25_ = ~\stato_reg[0]/NET0131 & \stato_reg[1]/NET0131 ;
assign new_n26_ = ~new_n17_ & ~\stato_reg[2]/NET0131 & (~\stato_reg[1]/NET0131 ^ \stato_reg[0]/NET0131 );
assign \g222/_0_ = new_n24_ ? (~line1_pad ^ line2_pad) : (~line1_pad ^ ~line2_pad);
assign \g224/_0_ = (new_n29_ | ~\stato_reg[2]/NET0131 ) & (new_n25_ | new_n17_ | \stato_reg[2]/NET0131 );
assign new_n29_ = ~\stato_reg[1]/NET0131 & (\stato_reg[0]/NET0131 | ~new_n21_);
assign \g44/_1_ = \stato_reg[0]/NET0131 & ~\stato_reg[2]/NET0131 & \stato_reg[1]/NET0131 ;
assign _al_n0 = 1'b0;
assign _al_n1 = 1'b1;
endmodule
| 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b02_comb/b02_comb.opt (
linea_pad,
\stato_reg[0]/NET0131 ,
\stato_reg[1]/NET0131 ,
\stato_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g110/_1_ ,
\g111/_0_ ,
\g112/_0_ ,
\g128/_0_
);
input linea_pad, \stato_reg[0]/NET0131 , \stato_reg[1]/NET0131 , \stato_reg[2]/NET0131 ;
output _al_n0, _al_n1, \g110/_1_ , \g111/_0_ , \g112/_0_ , \g128/_0_ ;
assign \g110/_1_ = (\stato_reg[0]/NET0131 & ((~linea_pad & (\stato_reg[2]/NET0131 | ~\stato_reg[1]/NET0131 )) | (\stato_reg[2]/NET0131 & ~\stato_reg[1]/NET0131 ))) | (~\stato_reg[2]/NET0131 & \stato_reg[1]/NET0131 & ~\stato_reg[0]/NET0131 );
assign \g111/_0_ = (linea_pad & (\stato_reg[0]/NET0131 | (\stato_reg[1]/NET0131 & ~\stato_reg[2]/NET0131 ))) | (\stato_reg[0]/NET0131 & (~\stato_reg[1]/NET0131 ^ ~\stato_reg[2]/NET0131 )) | (~linea_pad & ~\stato_reg[0]/NET0131 & \stato_reg[1]/NET0131 & \stato_reg[2]/NET0131 );
assign \g112/_0_ = (~\stato_reg[1]/NET0131 & (~\stato_reg[0]/NET0131 | (~\stato_reg[2]/NET0131 & linea_pad))) | (\stato_reg[2]/NET0131 & linea_pad & \stato_reg[1]/NET0131 & \stato_reg[0]/NET0131 ) | (~\stato_reg[0]/NET0131 & ~\stato_reg[2]/NET0131 & ~linea_pad);
assign \g128/_0_ = \stato_reg[2]/NET0131 & ~\stato_reg[0]/NET0131 & ~\stato_reg[1]/NET0131 ;
assign _al_n0 = 1'b0;
assign _al_n1 = 1'b1;
endmodule
| 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b06_comb/b06_comb.opt (
cont_eql_pad,
eql_pad,
\state_reg[0]/NET0131 ,
\state_reg[1]/NET0131 ,
\state_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g211/_0_ ,
\g212/_0_ ,
\g213/_0_ ,
\g218/_0_ ,
\g219/_0_ ,
\g220/_0_ ,
\g223/_0_ ,
\g227/_0_
);
input cont_eql_pad, eql_pad, \state_reg[0]/NET0131 ,
\state_reg[1]/NET0131 , \state_reg[2]/NET0131 ;
output _al_n0, _al_n1, \g211/_0_ , \g212/_0_ , \g213/_0_ , \g218/_0_ ,
\g219/_0_ , \g220/_0_ , \g223/_0_ , \g227/_0_ ;
wire new_n20_, new_n21_;
assign \g211/_0_ = (~\state_reg[0]/NET0131 | (\state_reg[1]/NET0131 ? ~\state_reg[2]/NET0131 : ~eql_pad)) & (~eql_pad | ((\state_reg[0]/NET0131 | \state_reg[2]/NET0131 | ~\state_reg[1]/NET0131 ) & (~\state_reg[2]/NET0131 | \state_reg[1]/NET0131 )));
assign \g212/_0_ = (eql_pad | \state_reg[1]/NET0131 | (~\state_reg[0]/NET0131 ^ \state_reg[2]/NET0131 )) & (~\state_reg[1]/NET0131 | ~\state_reg[2]/NET0131 | (~eql_pad & ~\state_reg[0]/NET0131 ));
assign \g213/_0_ = new_n20_ | new_n21_;
assign new_n20_ = \state_reg[1]/NET0131 & ~\state_reg[2]/NET0131 & ~eql_pad & ~\state_reg[0]/NET0131 ;
assign new_n21_ = ~cont_eql_pad & (~\state_reg[0]/NET0131 | ~\state_reg[1]/NET0131 | ~\state_reg[2]/NET0131 );
assign \g218/_0_ = (eql_pad & (\state_reg[1]/NET0131 ? ~\state_reg[0]/NET0131 : \state_reg[2]/NET0131 )) | (~\state_reg[1]/NET0131 & (\state_reg[0]/NET0131 ^ \state_reg[2]/NET0131 ));
assign \g219/_0_ = (~eql_pad & (~\state_reg[0]/NET0131 ^ ~\state_reg[1]/NET0131 )) | (~\state_reg[2]/NET0131 & (~\state_reg[0]/NET0131 ^ \state_reg[1]/NET0131 ));
assign \g220/_0_ = (eql_pad & (\state_reg[0]/NET0131 ? ~\state_reg[2]/NET0131 : \state_reg[1]/NET0131 )) | (~\state_reg[0]/NET0131 & ((\state_reg[1]/NET0131 & ~\state_reg[2]/NET0131 ) | (~eql_pad & ~\state_reg[1]/NET0131 & \state_reg[2]/NET0131 )));
assign \g223/_0_ = (\state_reg[2]/NET0131 & ((eql_pad & (~\state_reg[1]/NET0131 | ~\state_reg[0]/NET0131 )) | (~\state_reg[1]/NET0131 & ~\state_reg[0]/NET0131 ))) | (\state_reg[0]/NET0131 & ~\state_reg[2]/NET0131 & ~eql_pad & ~\state_reg[1]/NET0131 );
assign \g227/_0_ = ~\state_reg[0]/NET0131 & \state_reg[2]/NET0131 & (~eql_pad ^ \state_reg[1]/NET0131 );
assign _al_n0 = 1'b0;
assign _al_n1 = 1'b1;
endmodule
| 6.939825 |
module b1 (
pi0,
pi1,
pi2,
po0,
po1,
po2,
po3
);
input pi0, pi1, pi2;
output po0, po1, po2, po3;
wire new_n11_, new_n12_;
assign po1 = ~new_n11_;
assign po2 = ~new_n12_;
assign po3 = ~pi2;
assign new_n11_ = ~pi0 ^ pi1;
assign new_n12_ = (pi0 & (~pi1 | pi2)) | (~pi0 & (pi1 | ~pi2)) | (~pi1 & ~pi2) | (pi1 & pi2);
assign po0 = pi2;
endmodule
| 7.122641 |
module eval_test;
parameter l=16;
reg clk, reset;
reg `L din;
wire `L dout, a;
wire `L d;
wire wr_b, rd_b, ble_b, bhe_b;
b16_eval flk10k30e(clk, reset, din, dout, a, d, wr_b, rd_b, ble_b, bhe_b);
integer oldtime;
always @(dout)
begin
$display("%d: dout <= %b", $time-oldtime, dout);
oldtime <= $time;
end
initial
begin
reset <= 1;
clk <= 0;
#1000 reset <= 0;
forever #50 clk <= ~clk;
end
task send_byte;
input [7:0] byte;
begin
#8700 din[0] <= 0;
#8700 din[0] <= byte[0];
#8700 din[0] <= byte[1];
#8700 din[0] <= byte[2];
#8700 din[0] <= byte[3];
#8700 din[0] <= byte[4];
#8700 din[0] <= byte[5];
#8700 din[0] <= byte[6];
#8700 din[0] <= byte[7];
#8700 din[0] <= 1;
#8700 din[0] <= 1;
end
endtask
initial
begin
din <= 16'h0001;
#100000 send_byte(8'h30); // start bit
send_byte(8'h03);
send_byte(8'h02);
send_byte(8'h04);
send_byte(8'h12);
send_byte(8'h34);
send_byte(8'h56);
send_byte(8'h78);
#100000 send_byte(8'h31);
send_byte(8'h03);
send_byte(8'h02);
send_byte(8'h04);
end
endmodule
| 6.710345 |
module test;
wire [15:0] a0, a1, d0, d1;
wire DP, DN, send0, send1;
reg clk, nreset;
assign {DP, DN} = (send0 | send1) ? 2'bzz : 2'b10;
b16_eval_usb #(16, "master.hex") core0 (
clk,
nreset,
a0,
d0,
wr_b0,
rd_b0,
ble_b0,
bhe_b0,
DP,
DN,
dif0,
send0,
dp0,
dn0
);
b16_eval_usb #(16, "slave.hex") core1 (
clk,
nreset,
a1,
d1,
wr_b1,
rd_b1,
ble_b1,
bhe_b1,
DP,
DN,
dif1,
send1,
dp1,
dn1
);
usbphys usbp0 (
DP,
DN,
dif0,
send0,
dp0,
dn0
);
usbphys usbp1 (
DP,
DN,
dif1,
send1,
dp1,
dn1
);
initial begin
$dumpfile("b16-eval-usb.vcd");
$dumpvars();
nreset <= 0;
clk <= 0;
#10000 nreset <= 1;
repeat (10000) #10 clk <= ~clk;
$finish;
end
endmodule
| 6.964054 |
module b16_eval_usb (
clk,
nreset,
a,
d,
wr_b,
rd_b,
ble_b,
bhe_b,
DP,
DN,
dif,
send,
dp,
dn
);
parameter l = 16, bootram = "b16.hex";
input clk, nreset;
output `L a;
inout `L d;
output wr_b, rd_b, ble_b, bhe_b;
input DP, DN, dif;
output send, dp, dn;
wire `L mem_addr, addr, dout, dout_boot, dma, data;
wire r, mem_r, intreq, intack, reqr, reqw;
wire [3:0] pid;
wire [7:0] intvec = {1'b0, pid, 3'b000};
wire [1:0] w, mem_w;
reg [2:0] sel;
reg [1:0] dout24;
reg ack;
wire nrst = nreset;
wire reset = nreset;
wire cpu_rw = |w | r;
always @(negedge cpu_rw or negedge reqr or negedge reqw) ack <= reqr | reqw;
assign mem_r = ack ? reqr : r;
assign mem_w = ack ? {(2) {reqw}} : w;
assign mem_addr = ack ? dma : addr;
wire usb_sel = sel[2];
wire mem_sel = ~usb_sel;
cpu #(1) b16 (
clk,
nrst,
addr,
r,
w,
data,
dout,
intreq,
intack,
intvec
);
usb #(1) usb1 (
clk,
reset,
DP,
DN,
dif,
send,
dp,
dn,
usb_sel,
addr[2:1],
r,
w,
dma,
reqr,
reqw,
ack,
data,
data,
pid,
intreq,
intack
);
ram1024 #(bootram) ram (
mem_addr[10:1],
w,
~clk,
data,
sel[1] & |w,
dout_boot
);
assign a = {1'b0, mem_addr[l-1:1]};
assign d = mem_r ? 16'hzzzz : data;
always @(addr)
if (&addr[15:3]) sel <= 3'b100;
else if (addr[15:11] == 5'h00) sel <= 3'b010;
else sel <= 3'b001;
reg wr_b, rd_b, ble_b, bhe_b;
always @(clk or nrst or r or w or sel)
if (sel[0] & nrst) begin
rd_b <= ~r;
{wr_b, ble_b, bhe_b} <= 3'b111;
if (!clk) begin
wr_b <= ~|w;
{bhe_b, ble_b} <= ~w & {~r, ~r};
end
end else {wr_b, rd_b, ble_b, bhe_b} <= 4'b1111;
assign data = mem_w ? dout : {r, sel} == 4'b1010 ? dout_boot : {r, sel} == 4'b1010 ? d : 16'hzzzz;
endmodule
| 6.742856 |
module b16_eval(clk, reset, din, dout, a, d, wr_b, rd_b, ble_b, bhe_b);
parameter l=16;
input clk, reset;
input `L din;
output `L dout, a;
inout `L d;
output wr_b, rd_b, ble_b, bhe_b;
wire `L addr, dwrite, a_out;
wire r, waits;
wire [1:0] w;
reg `L dout_out, data, a_old;
reg [2:0] sel;
reg [1:0] dout24;
wire [7:0] intvec = 0;
wire intreq = 0;
wire nrst = ~reset;
cpu b16(clk, nrst, addr, r, w, data, dwrite, intreq, intack, intvec);
assign d = r ? {(l){ 1'bz }} : dwrite;
assign a_out = { 1'b0, addr[l-1:1] };
always @(posedge clk)
a_old <= a_out;
assign a[0] = (a_out[0] & a_old[0]) ? 1'bz : a_out[0];
assign a[1] = (a_out[1] & a_old[1]) ? 1'bz : a_out[1];
assign a[2] = (a_out[2] & a_old[2]) ? 1'bz : a_out[2];
assign a[3] = (a_out[3] & a_old[3]) ? 1'bz : a_out[3];
assign a[4] = (a_out[4] & a_old[4]) ? 1'bz : a_out[4];
assign a[5] = (a_out[5] & a_old[5]) ? 1'bz : a_out[5];
assign a[6] = (a_out[6] & a_old[6]) ? 1'bz : a_out[6];
assign a[7] = (a_out[7] & a_old[7]) ? 1'bz : a_out[7];
assign a[8] = (a_out[8] & a_old[8]) ? 1'bz : a_out[8];
assign a[9] = (a_out[9] & a_old[9]) ? 1'bz : a_out[9];
assign a[10] = (a_out[10] & a_old[10]) ? 1'bz : a_out[10];
assign a[11] = (a_out[11] & a_old[11]) ? 1'bz : a_out[11];
assign a[12] = (a_out[12] & a_old[12]) ? 1'bz : a_out[12];
assign a[13] = (a_out[13] & a_old[13]) ? 1'bz : a_out[13];
assign a[14] = (a_out[14] & a_old[14]) ? 1'bz : a_out[14];
assign a[15] = (a_out[15] & a_old[15]) ? 1'bz : a_out[15];
assign dout[2] = (dout_out[2] & dout24[0]) ? 1'bz : dout_out[2];
assign dout[4] = (dout_out[4] & dout24[1]) ? 1'bz : dout_out[4];
assign { dout[15:5], dout[3], dout[1:0] } = { dout_out[15:5], dout_out[3], dout_out[1:0] };
always @(addr)
if(addr[15:2] == 14'h3fff) sel <= 3'b100;
else if(addr[15:11] == 5'h00) sel <= 3'b010;
else sel <= 3'b001;
always @(negedge clk or negedge nrst)
if(!nrst)
begin
dout_out <= 16'b1010_0101_0001_0101;
dout24 <= 2'b11;
end
else
begin
if(sel[2] & addr[1]) begin
if(w[1]) dout_out[15:8] <= dwrite[15:8];
if(w[0]) dout_out[07:0] <= dwrite[07:0];
end // if (sel[2] & addr[0])
dout24 <= { dout_out[2], dout_out[4] };
end
reg wr_b, rd_b, ble_b, bhe_b;
always @(clk or nrst or r or w or sel)
if(sel[0] & nrst) begin
rd_b <= ~r;
{ wr_b, ble_b, bhe_b } <= 3'b111;
if(!clk) begin
wr_b <= ~|w;
{ bhe_b, ble_b } <= ~w & { ~r, ~r };
end
end
else { wr_b, rd_b, ble_b, bhe_b } <= 4'b1111;
reg [7:0] bootraml[0:1023], bootramh[0:1023];
always @(negedge clk)
if(sel[1]) begin
if(w[1]) bootramh[addr[11:1]] <= d[15:8];
if(w[0]) bootraml[addr[11:1]] <= d[ 7:0];
if(&w) $display("bootram[%x] <= %x", { addr[11:1], 1'b0 }, d);
else begin
if(w[0]) $display("bootram[%x] <= %x", { addr[11:1], 1'b1 }, d[15:8]);
if(w[1]) $display("bootram[%x] <= %x", { addr[11:1], 1'b0 }, d[ 7:0]);
end
end
initial
begin
$readmemh("bootl.hex", bootraml);
$readmemh("booth.hex", bootramh);
end
integer oldtime;
initial oldtime = 0;
always @(sel or r or d or din or dout_out or addr)
begin
casez({ r, sel })
4'b1100: begin
data <= addr[1] ? dout_out : din;
if(!addr[1] && (($time-oldtime) != 0)) begin
$display("%d: Read din %x", $time-oldtime, din);
oldtime = $time;
end
end
4'b1010: data <= { bootramh[addr[11:1]], bootraml[addr[11:1]] };
4'b1001: data <= d;
4'b????: data <= 16'h0000;
endcase // case(sel)
end
endmodule
| 7.023475 |
module for c16 core */
`define L [l-1:0]
`timescale 1ns / 1ns
module memory(reset, sel, addr, r, w, data, dout);
parameter l=16;
input reset;
input `L addr;
input sel, r;
input [1:0] w;
output `L data;
input `L dout;
reg `L mem[((1<<(l-1)))-1:0];
wire `L dstore, dfetch;
assign data = (r & sel) ? dfetch : 16'hzzzz;
assign dfetch = mem[addr[l-1:1]];
assign dstore = { w[1] ? dout[15:8] : dfetch[15:8],
w[0] ? dout[7:0] : dfetch[7:0] };
always @(w)
if(reset & sel & |w) begin
#1 $display("cpu: mem[%x] <= %x", addr[l-1:1], dstore);
mem[addr[l-1:1]] <= dstore;
end
initial
$readmemh("b16.hex", mem);
// always @(data)
// $display("data=%x[%x]", data, addr[l-1:1]);
endmodule
| 7.899441 |
module alu(res, carry, zero, T, N, c, inst);
parameter l=16;
input `L T, N;
input c;
input [2:0] inst;
output `L res;
output carry, zero;
wire prop, andor, selr;
assign #1 { prop, andor, selr } = inst;
wire `L sum, logic;
wire cout;
assign { cout, sum } =
T + N + ((c | andor) & selr);
assign logic = andor ?
(selr ? (T | N) : (T & N)) :
T ^ N;
assign { carry, res } =
prop ? { cout, sum } : { c, logic };
assign zero = ~|T;
endmodule
| 7.249315 |
module b16toBCD_tb;
reg [15:0] to_display;
reg enable;
wire [3:0] D5;
wire [3:0] D4;
wire [3:0] D3;
wire [3:0] D2;
wire [3:0] D1;
integer file, i, j, limit;
localparam period = 20;
b16toBCD UUT (
.to_display(to_display),
.enable(enable),
.D5(D5),
.D4(D4),
.D3(D3),
.D2(D2),
.D1(D1)
);
initial begin
limit = 100;
file = $fopen("b16toBCD.log", "a");
$display("Pre-initial values:\nTime %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ", $time,
enable, to_display, D5, D4, D3, D2, D1);
$fdisplay(file, "Pre-initial values:\nTime %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ",
$time, enable, to_display, D5, D4, D3, D2, D1);
enable = $random % 2;
#(period / 2)
$display(
"Initial values:\nTime %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ",
$time,
enable,
to_display,
D5,
D4,
D3,
D2,
D1
);
$fdisplay(file, "Initial values:\nTime %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ",
$time, enable, to_display, D5, D4, D3, D2, D1);
for (i = 0; i < limit; i = i + 1) begin
to_display = $random % 2 ** 16;
enable = $random % 2;
#period;
$display("Time %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ", $time, enable,
to_display, D5, D4, D3, D2, D1);
$fdisplay(file, "Time %0d enable %0d binary %0d BCD %0d %0d %0d %0d %0d ", $time, enable,
to_display, D5, D4, D3, D2, D1);
end
$fclose(file);
end
endmodule
| 6.969533 |
module b16_4to1_bridge //4时钟16bits合成 1时钟64bits
(
input wire clk_i,
input wire clk_i_div4,
input wire rst_n,
input wire [15: 0]d_i,
input wire d_i_en,//d_i_en使能期间必须保证有4的倍数个时钟
output wire clk_o, //clk_o与d_o,d_o_valid,d_i_en...相位不确定
output reg [63:0] d_o,
output wire d_o_valid
);
reg [47:0] b;
reg [ 1:0] c;
always @(posedge clk_i or negedge rst_n) begin
if (!rst_n) begin
c <= 2'd0;
end else if (d_i_en) begin
c <= c + 1'd1;
end else begin
c <= 2'd0;
end
end
always @(posedge clk_i or negedge rst_n) begin
if (!rst_n) begin
d_o <= 64'd0;
b <= 48'd0;
end else if (d_i_en) begin
if (c == 2'd3)
d_o <= {b, d_i[7:0], d_i[15:8]}; //交换高低字节(FX2先发的字节在低位)
else b <= {b[31:0], d_i[7:0], d_i[15:8]};
end
end
reg [3:0] shifft_buff;
assign d_o_valid = shifft_buff[3]; //迟4个clk_i, 并与clk_i上升沿同步
always @(posedge clk_i or negedge rst_n) begin
if (!rst_n) shifft_buff <= 4'd0;
else shifft_buff <= {shifft_buff[2:0], d_i_en};
end
assign clk_o = clk_i_div4; //4分频使用pll源
reg [1:0] cnt_div4;
always @(posedge clk_i or negedge rst_n) begin
if (!rst_n) cnt_div4 <= 2'd0;
else cnt_div4 <= cnt_div4 + 1'd1;
end
endmodule
| 6.907193 |
module b16_loom (
input clk,
input rst_n,
input sel,
input sign,
// in1, in2
input [15:0] in1,
input [15:0] in2,
input [31:0] in3,
// output
output [31:0] out
);
reg [15:0] in1_reg;
reg [15:0] in2_reg;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
in1_reg <= 16'b0;
in2_reg <= 16'b0;
end else begin
in1_reg <= in1;
in2_reg <= in2;
end
end
wire [19:0] out_AC1;
b16_loom_AC1 U1 (
.clk (clk),
.rst_n(rst_n),
.in1 (in1_reg),
.in2 (in2_reg),
.out (out_AC1)
);
b16_loom_AC2 U2 (
.clk (clk),
.rst_n(rst_n),
.in1 (out_AC1),
.in2 (in3),
.sign (sign),
.sel (sel),
.out (out)
);
endmodule
| 7.781791 |
module b16_loom_AC1 (
input clk,
input rst_n,
// in1, in2
input [15:0] in1,
input [15:0] in2,
// output
output [19:0] out
);
wire [3:0] psum;
assign psum = in1[0] & in2[0]
+ in1[1] & in2[1]
+ in1[2] & in2[2]
+ in1[3] & in2[3]
+ in1[4] & in2[4]
+ in1[5] & in2[5]
+ in1[6] & in2[6]
+ in1[7] & in2[7]
+ in1[8] & in2[8]
+ in1[9] & in2[9]
+ in1[10] & in2[10]
+ in1[11] & in2[11]
+ in1[12] & in2[12]
+ in1[13] & in2[13]
+ in1[14] & in2[14]
+ in1[15] & in2[15]
;
reg [19:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 20'b0;
end else begin
out <= psum + out << 1;
end
end
endmodule
| 6.855877 |
module b16_loom_AC2 (
input clk,
input rst_n,
// in1, in2
input [19:0] in1,
input [31:0] in2,
input sign,
input sel,
// output
output [31:0] out
);
wire [19:0] sign_in1;
assign sign_in1 = (sign == 1'b1) ? ~in1 : in1;
wire [31:0] sel_in2;
assign sel_in2 = (sel == 1'b1) ? in2 : out << 1;
reg [31:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 32'b0;
end else begin
out <= sign_in1 + sel_in2 + sign;
end
end
endmodule
| 7.5071 |
module b16_loom_AC1 (
input clk,
input rst_n,
// in1, in2
input [15:0] in1,
input [15:0] in2,
// output
output [19:0] out
);
wire [3:0] psum;
assign psum = in1[0] & in2[0]
+ in1[1] & in2[1]
+ in1[2] & in2[2]
+ in1[3] & in2[3]
+ in1[4] & in2[4]
+ in1[5] & in2[5]
+ in1[6] & in2[6]
+ in1[7] & in2[7]
+ in1[8] & in2[8]
+ in1[9] & in2[9]
+ in1[10] & in2[10]
+ in1[11] & in2[11]
+ in1[12] & in2[12]
+ in1[13] & in2[13]
+ in1[14] & in2[14]
+ in1[15] & in2[15]
;
reg [19:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 20'b0;
end else begin
out <= psum + out << 1;
end
end
endmodule
| 6.855877 |
module b16_loom_AC2 (
input clk,
input rst_n,
// in1, in2
input [19:0] in1,
input [31:0] in2,
input sign,
input sel,
// output
output [31:0] out
);
wire [19:0] sign_in1;
assign sign_in1 = (sign == 1'b1) ? ~in1 : in1;
wire [31:0] sel_in2;
assign sel_in2 = (sel == 1'b1) ? in2 : out << 1;
reg [31:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 32'b0;
end else begin
out <= sign_in1 + sel_in2 + sign;
end
end
endmodule
| 7.5071 |
module b16_SIP (
input clk,
input rst_n,
//in1, in2,
input [15:0] in1_0,
input [15:0] in1_1,
input [15:0] in1_2,
input [15:0] in1_3,
input [15:0] in1_4,
input [15:0] in1_5,
input [15:0] in1_6,
input [15:0] in1_7,
input [15:0] in1_8,
input [15:0] in1_9,
input [15:0] in1_10,
input [15:0] in1_11,
input [15:0] in1_12,
input [15:0] in1_13,
input [15:0] in1_14,
input [15:0] in1_15,
//in1, in2,
input in2_0,
input in2_1,
input in2_2,
input in2_3,
input in2_4,
input in2_5,
input in2_6,
input in2_7,
input in2_8,
input in2_9,
input in2_10,
input in2_11,
input in2_12,
input in2_13,
input in2_14,
input in2_15,
// output
output [31:0] out
);
wire [19:0] psum;
assign psum = in1_0 & {16{in2_0}}
+ in1_1 & {16{in2_1}}
+ in1_2 & {16{in2_2}}
+ in1_3 & {16{in2_3}}
+ in1_4 & {16{in2_4}}
+ in1_5 & {16{in2_5}}
+ in1_6 & {16{in2_6}}
+ in1_7 & {16{in2_7}}
+ in1_8 & {16{in2_8}}
+ in1_9 & {16{in2_9}}
+ in1_10 & {16{in2_10}}
+ in1_11 & {16{in2_11}}
+ in1_12 & {16{in2_12}}
+ in1_13 & {16{in2_13}}
+ in1_14 & {16{in2_14}}
+ in1_15 & {16{in2_15}}
+ out<<1 ;
reg [31:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 32'b0;
end else begin
out <= psum;
end
end
endmodule
| 6.908117 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b1_comb/b1_comb.opt (
a_pad,
b_pad,
d_pad,
e_pad,
f_pad,
g_pad
);
input a_pad, b_pad, d_pad;
output e_pad, f_pad, g_pad;
assign e_pad = a_pad ^ b_pad;
assign f_pad = a_pad ? (b_pad & ~d_pad) : (~b_pad & d_pad);
assign g_pad = ~d_pad;
endmodule
| 6.939825 |
module b1_demux_1_3_case (
input din,
input [1:0] sel,
output reg dout0,
output reg dout1,
output reg dout2
);
always @(*)
case (sel)
2'b00: begin
dout0 = din;
dout1 = 0;
dout2 = 0;
end
2'b01: begin
dout0 = 0;
dout1 = din;
dout2 = 0;
end
2'b10: begin
dout0 = 0;
dout1 = 0;
dout2 = din;
end
default: begin
dout0 = 0;
dout1 = 0;
dout2 = 0;
end
endcase
endmodule
| 8.151336 |
module b1_demux_1_3_case_v2 (
input din,
input [1:0] sel,
output reg dout0,
output reg dout1,
output reg dout2
);
always @(*) begin
dout0 = 1'b0;
dout1 = 1'b0;
dout2 = 1'b0;
case (sel)
2'b00: dout0 = din;
2'b01: dout1 = din;
2'b10: dout2 = din;
endcase
end
endmodule
| 8.151336 |
module b1_demux_1_3_shift (
input din,
input [1:0] sel,
output dout0,
output dout1,
output dout2
);
assign {dout2, dout1, dout0} = din << sel;
endmodule
| 8.151336 |
module b200_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
b200_clk_gen clknetwork ( // Clock in ports
.CLK_IN1_40_P (CLK_IN1_P),
.CLK_IN1_40_N (CLK_IN1_N),
// Clock out ports
.CLK_OUT1_40_int (clk_int[1]),
.CLK_OUT2_100_gpif(clk_int[2]),
.CLK_OUT3_100_bus (clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr (
.Q (CLK_OUT[clk_out_pins1]),
.C0(clk[clk_out_pins]),
.C1(clk_n[clk_out_pins]),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 7.230123 |
module b200_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 25.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
wire CLK_IN1_P = CLK_IN1;
wire CLK_IN1_N = ~CLK_IN1;
// The high bits of the sampling counters
wire [ 3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 3:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
b200_clk_gen_exdes dut ( // Clock in ports
.CLK_IN1_P (CLK_IN1_P),
.CLK_IN1_N (CLK_IN1_N),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.230123 |
module b205_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
b205_clk_gen clknetwork ( // Clock in ports
.CLK_IN1_40 (CLK_IN1),
// Clock out ports
.CLK_OUT1_40_int (clk_int[1]),
.CLK_OUT2_100_bus (clk_int[2]),
.CLK_OUT3_200_ref_pll(clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr (
.Q (CLK_OUT[clk_out_pins]),
.C0(clk[clk_out_pins]),
.C1(clk_n[clk_out_pins]),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 7.108747 |
module b205_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 25.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [ 3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 3:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
b205_clk_gen_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.108747 |
module b222 (
BCLK,
WR_MRAM,
VADR,
MMU_DIN,
rd_addr,
rd_result
);
input BCLK;
input WR_MRAM;
input [31:0] VADR;
input [23:0] MMU_DIN;
input [1:0] rd_addr;
output [35:0] rd_result;
reg [31:0] VADR_R;
reg [35:0] MMU_TAGS[0:3];
always @(posedge BCLK) VADR_R <= VADR;
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:18]] <= {VADR_R[31:20], MMU_DIN[23:0]};
assign rd_result = MMU_TAGS[rd_addr];
endmodule
| 6.879602 |
module b2bcd_99 (
input [19:0] din,
output [19:0] dout
);
assign dout = din + (din / 8'd10) * 8'd6;
endmodule
| 6.795267 |
module b2bcd_99_test;
reg [19:0] din;
wire [19:0] dout;
b2bcd_99 dut (
.din (din),
.dout(dout)
);
initial begin
din = 20'd23;
#500000 $stop;
end
endmodule
| 6.839372 |
module b2d #(
parameter dw = 16, // input data width in bits
parameter sim_mode = 0
) (
input clk,
input [dw-1:0] bdata,
input load,
output [3:0] nibble,
output nstrobe
);
// Hold the data in a shift register
reg [dw-1:0] sr;
wire shiftin;
always @(posedge clk) sr <= load ? bdata : {sr[dw-2:0], shiftin};
wire shiftout = sr[dw-1];
// Need to know how often the word repeats
reg [4:0] bcnt;
wire bdone = load || bcnt == 0;
always @(posedge clk) bcnt <= bdone ? dw - 1 : bcnt - 1;
// Actual work
// Get the basics working using 10
// can optimize to 5*2 later if the synthesizer can't optimize sufficiently
reg [3:0] accum;
wire [4:0] accum5 = {accum, shiftout};
wire got_one = accum5 >= 10;
wire [3:0] accum_sub = got_one ? accum5 - 10 : accum5;
always @(posedge clk) accum <= bdone ? 0 : accum_sub;
assign shiftin = got_one;
// Construct output
assign nstrobe = bcnt == 0;
assign nibble = (nstrobe | !sim_mode) ? accum_sub : 4'bx;
endmodule
| 7.425536 |
module b2decimal #(
parameter dw = 16
) (
input clk,
input [dw-1:0] bdata,
input load,
output [3:0] nibble,
output nstrobe
);
// Hold the data in a shift register
reg [dw-1:0] sr;
wire shiftin;
always @(posedge clk) sr <= load ? bdata : {sr[dw-2:0], shiftin};
wire shiftout = sr[dw-1];
// Need to know how often the word repeats
reg [4:0] bcnt;
wire bdone = load || bcnt == 0;
always @(posedge clk) bcnt <= bdone ? dw - 1 : bcnt - 1;
// Actual work
// Get the basics working using 10
// can optimize to 5*2 later if the synthesizer can't optimize sufficiently
reg [3:0] accum;
wire [4:0] accum5 = {accum, shiftout};
wire got_one = accum5 >= 10;
wire [3:0] accum_sub = got_one ? accum5 - 10 : accum5;
always @(posedge clk) accum <= bdone ? 0 : accum_sub;
assign shiftin = got_one;
// Construct output
`ifdef SIMULATE
assign nibble = bdone ? accum_sub : 4'bx;
`else
assign nibble = accum_sub;
`endif
assign nstrobe = bcnt == 0;
endmodule
| 6.854576 |
module b2d_ssd (
BIN,
SSD
);
input [15:0] BIN;
output reg [0:6] SSD;
always begin
case (BIN)
0: SSD = 7'b0000001;
1: SSD = 7'b1001111;
2: SSD = 7'b0010010;
3: SSD = 7'b0000110;
4: SSD = 7'b1001100;
5: SSD = 7'b0100100;
6: SSD = 7'b0100000;
7: SSD = 7'b0001111;
8: SSD = 7'b0000000;
9: SSD = 7'b0001100;
endcase
end
endmodule
| 6.814137 |
module b2Yb (
input iClk,
input iReset_n,
input [7:0] iB,
output [4:0] oYB
);
//====================REGISTERS==================
reg [ 7:0] s1_iB;
//===============================================
//======================WIRES====================
wire [20:0] yb;
// Pre-Calculate
//===============================================
wire [20:0] B_shl_13 = {s1_iB, 13'b0};
wire [17:0] B_shl_10 = {s1_iB, 10'b0};
wire [15:0] B_shl_8 = {s1_iB, 8'b0};
wire [12:0] B_shl_5 = {s1_iB, 5'b0};
wire [11:0] B_shl_4 = {s1_iB, 4'b0};
wire [ 8:0] B_shl_1 = {s1_iB, 1'b0};
//===============================================
// COMBINATION
//===============================================
assign yb = ((B_shl_13 - B_shl_10) + (B_shl_8 + B_shl_5)) + (B_shl_4 - B_shl_1);
assign oYB = yb[20:16];
//===============================================
// SEQUENCE
//===============================================
always @(posedge iClk)
if (~iReset_n) s1_iB <= 8'h0;
else s1_iB <= iB;
endmodule
| 6.620707 |
module b2_demux_1_4_univ #(
parameter MODE = "CASE"
) (
input [1:0] din,
input [1:0] sel,
output [1:0] dout0,
output [1:0] dout1,
output [1:0] dout2,
output [1:0] dout3
);
// generate & parameter can be used to select one of module implementations
generate
// the 1st implementation
if (MODE == "CASE") begin : demux_case
bN_demux_1_4_case #(2) dmux (
.din (din),
.sel (sel),
.dout0(dout0),
.dout1(dout1),
.dout2(dout2),
.dout3(dout3)
);
end // the 2nd implementation
else if (MODE == "SV") begin : demux_sv
wire [7:0] dout;
assign {dout3, dout2, dout1, dout0} = dout;
bN_demux_1_N #(
.DATA_WIDTH(2),
.ADDR_WIDTH(2)
) dmux (
.din (din),
.sel (sel),
.dout(dout)
);
end // or the module stub!
else begin : nothing
assign dout0 = 2'b0;
assign dout1 = 2'b0;
assign dout2 = 2'b0;
assign dout3 = 2'b0;
end
endgenerate
endmodule
| 6.829371 |
module b2_mux_3_1_case_full (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All possible values of input signals should be provided
// or an inferred latch will be generated!
always @(*) begin
case (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
2'b11: y = d2;
endcase
end
endmodule
| 6.712042 |
module b2_mux_3_1_case (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All the possible input-output pairs should be provided!
// The first way to provide all possible values of input signals
// is to add the default value out of the 'case' block
always @(*) begin
y = d2;
case (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
endcase
end
endmodule
| 6.712042 |
module b2_mux_3_1_case_default (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All the possible input-output pairs should be provided!
// The second way to provide all possible values of input signals
// is to use the 'default' inside the 'case' block
always @(*)
case (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
default: y = d2;
endcase
endmodule
| 6.712042 |
module b2_mux_3_1_casez #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] d0,
d1,
d2,
input [ 1:0] sel,
output reg [WIDTH-1:0] y
);
always @(*)
casez (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b1?: y = d2;
endcase
endmodule
| 6.712042 |
module b2_mux_4_1_case_one_hot (
input [1:0] d0,
input [1:0] d1,
input [1:0] d2,
input [1:0] d3,
input [3:0] sel,
output reg [1:0] y
);
always @(*)
case (sel)
4'b0001: y = d0;
4'b0010: y = d1;
4'b0100: y = d2;
4'b1000: y = d3;
default: y = d0;
endcase
endmodule
| 7.2134 |
module b2_mux_4_1_casez_priority (
input [1:0] d0,
input [1:0] d1,
input [1:0] d2,
input [1:0] d3,
input [3:0] sel,
output reg [1:0] y
);
always @(*)
casez (sel)
4'b0001: y = d0;
4'b001?: y = d1;
4'b01??: y = d2;
4'b1???: y = d3;
default: y = d0;
endcase
endmodule
| 7.2134 |
module b8_SIP (
input clk,
input rst_n,
//in1, in2,
input [7:0] in1_0,
input [7:0] in1_1,
input [7:0] in1_2,
input [7:0] in1_3,
input [7:0] in1_4,
input [7:0] in1_5,
input [7:0] in1_6,
input [7:0] in1_7,
input [7:0] in1_8,
input [7:0] in1_9,
input [7:0] in1_10,
input [7:0] in1_11,
input [7:0] in1_12,
input [7:0] in1_13,
input [7:0] in1_14,
input [7:0] in1_15,
//in1, in2,
input in2_0,
input in2_1,
input in2_2,
input in2_3,
input in2_4,
input in2_5,
input in2_6,
input in2_7,
input in2_8,
input in2_9,
input in2_10,
input in2_11,
input in2_12,
input in2_13,
input in2_14,
input in2_15,
// output
output [15:0] out
);
wire [19:0] psum;
assign psum = in1_0 & {8{in2_0}}
+ in1_1 & {8{in2_1}}
+ in1_2 & {8{in2_2}}
+ in1_3 & {8{in2_3}}
+ in1_4 & {8{in2_4}}
+ in1_5 & {8{in2_5}}
+ in1_6 & {8{in2_6}}
+ in1_7 & {8{in2_7}}
+ in1_8 & {8{in2_8}}
+ in1_9 & {8{in2_9}}
+ in1_10 & {8{in2_10}}
+ in1_11 & {8{in2_11}}
+ in1_12 & {8{in2_12}}
+ in1_13 & {8{in2_13}}
+ in1_14 & {8{in2_14}}
+ in1_15 & {8{in2_15}}
+ out<<1 ;
reg [15:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 16'b0;
end else begin
out <= psum;
end
end
endmodule
| 6.663066 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b9_comb/b9_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f0_pad,
f_pad,
g0_pad,
g_pad,
h0_pad,
h_pad,
i0_pad,
i_pad,
j0_pad,
j_pad,
k0_pad,
k_pad,
l0_pad,
l_pad,
m0_pad,
m_pad,
n0_pad,
n_pad,
o0_pad,
o_pad,
p_pad,
q_pad,
r_pad,
s_pad,
t_pad,
u_pad,
v_pad,
w_pad,
x_pad,
y_pad,
z_pad,
a1_pad,
b1_pad,
c1_pad,
d1_pad,
e1_pad,
f1_pad,
g1_pad,
h1_pad,
i1_pad,
j1_pad,
j4,
p0_pad,
q0_pad,
r0_pad,
s0_pad,
t0_pad,
u277_syn_3,
v0_pad,
w0_pad,
y0_pad,
z0_pad
);
input a0_pad, a_pad, b0_pad, b_pad, c0_pad, c_pad, d0_pad, d_pad,
e0_pad, e_pad, f0_pad, f_pad, g0_pad, g_pad, h0_pad, h_pad, i0_pad,
i_pad, j0_pad, j_pad, k0_pad, k_pad, l0_pad, l_pad, m0_pad, m_pad,
n0_pad, n_pad, o0_pad, o_pad, p_pad, q_pad, r_pad, s_pad, t_pad, u_pad,
v_pad, w_pad, x_pad, y_pad, z_pad;
output a1_pad, b1_pad, c1_pad, d1_pad, e1_pad, f1_pad, g1_pad, h1_pad,
i1_pad, j1_pad, j4, p0_pad, q0_pad, r0_pad, s0_pad, t0_pad, u277_syn_3,
v0_pad, w0_pad, y0_pad, z0_pad;
wire new_n65_, new_n66_, new_n67_, new_n69_, new_n71_, new_n72_, new_n73_,
new_n74_, new_n76_, new_n77_, new_n78_, new_n79_, new_n84_, new_n88_,
new_n90_, new_n92_, new_n95_, new_n96_, new_n99_, new_n100_, new_n101_,
new_n102_;
assign a1_pad = new_n65_ & (~new_n67_ | (b0_pad & e_pad));
assign new_n65_ = ~j_pad & ~new_n66_ & ~e0_pad;
assign new_n66_ = o0_pad & n0_pad & d0_pad & i_pad;
assign new_n67_ = ~c0_pad & j0_pad & (i_pad | b0_pad);
assign b1_pad = ~new_n69_ & ~new_n74_;
assign new_n69_ = u277_syn_3 & (new_n73_ | (~new_n71_ & new_n72_));
assign u277_syn_3 = n0_pad & o0_pad;
assign new_n71_ = ~k0_pad & (~j0_pad | c0_pad);
assign new_n72_ = ~e_pad & b0_pad;
assign new_n73_ = ~e_pad & k_pad;
assign new_n74_ = b0_pad & (l0_pad | (c0_pad & j0_pad));
assign d1_pad = ~new_n76_ & ~new_n77_;
assign new_n76_ = u_pad & new_n74_ & ~s_pad & ~t_pad;
assign new_n77_ = new_n79_ & (new_n78_ | e0_pad | g0_pad);
assign new_n78_ = b0_pad & (~c0_pad | (j0_pad & k0_pad));
assign new_n79_ = o0_pad & n0_pad & ~e_pad & ~n_pad;
assign e1_pad = m_pad & i0_pad & a0_pad & b0_pad;
assign f1_pad = b_pad & ~x_pad & w_pad;
assign g1_pad = b_pad & x_pad & ~y_pad & w_pad;
assign j1_pad = ~new_n84_ & new_n65_;
assign new_n84_ = j0_pad & (b0_pad | (~c0_pad & i_pad));
assign v0_pad = ~l0_pad & (~c0_pad | ~b0_pad);
assign p0_pad = ~q_pad | (~p_pad & (new_n74_ | new_n69_));
assign q0_pad = new_n88_ | ~e_pad;
assign new_n88_ = ~e0_pad & ~g0_pad & (~b0_pad | new_n71_);
assign r0_pad = ~new_n90_ | (~new_n67_ & e_pad);
assign new_n90_ = u277_syn_3 & (c_pad | (d0_pad & i_pad));
assign s0_pad = new_n92_ | ~v_pad;
assign new_n92_ = (~l0_pad | b0_pad) & (~c0_pad | ~j0_pad | ~b0_pad);
assign t0_pad = new_n92_ | v_pad;
assign w0_pad = ~new_n95_ & d_pad & (~o_pad | new_n96_);
assign new_n95_ = m0_pad & (z_pad ? o_pad : ~a_pad);
assign new_n96_ = ~f0_pad & ~h0_pad & (~r_pad | p_pad);
assign y0_pad = l_pad & i0_pad & a0_pad & b0_pad;
assign z0_pad = new_n100_ | new_n102_ | (new_n99_ & ~new_n88_);
assign new_n99_ = f_pad & ~e_pad & u277_syn_3;
assign new_n100_ = new_n101_ & ~new_n71_ & new_n72_;
assign new_n101_ = h_pad & (~o0_pad | ~n0_pad);
assign new_n102_ = l0_pad & b0_pad & g_pad;
assign c1_pad = new_n76_ | new_n77_;
assign h1_pad = ~new_n65_ | (new_n67_ & (~b0_pad | ~e_pad));
assign j4 = ~v0_pad;
assign i1_pad = new_n65_ & (~new_n67_ | (b0_pad & e_pad));
endmodule
| 6.939825 |
module cntrl_jump_upto (
flagSet,
prevFlags,
jumpType,
jumpIndex,
jumpPredTk,
jumpTbufMiss,
indirMismatch,
jumpMisPred,
jumpTaken,
flagOut,
flagOutN,
flags0,
flags1,
flags2,
flags3,
flags4,
flags5,
flags6,
flags7,
flags8,
flags9
);
parameter INDEX = 0;
localparam WIDTH = 6;
input [9:0] flagSet;
input [WIDTH-1:0] prevFlags;
input [4:0] jumpType;
input [3:0] jumpIndex;
input jumpPredTk;
input jumpTbufMiss;
input indirMismatch;
output jumpMisPred;
output jumpTaken;
output [WIDTH-1:0] flagOut;
output [WIDTH-1:0] flagOutN;
input [WIDTH-1:0] flags0;
input [WIDTH-1:0] flags1;
input [WIDTH-1:0] flags2;
input [WIDTH-1:0] flags3;
input [WIDTH-1:0] flags4;
input [WIDTH-1:0] flags5;
input [WIDTH-1:0] flags6;
input [WIDTH-1:0] flags7;
input [WIDTH-1:0] flags8;
input [WIDTH-1:0] flags9;
wire [WIDTH-1:0] flags[9:0];
wire [9:0] jumpTaken_x;
wire [9:0] mispred_x;
wire [9:0] flagLast;
wire nFlagIsPrev;
wire jumpTaken_0;
wire mispred_0;
assign flags[0] = flags0;
assign flags[1] = flags1;
assign flags[2] = flags2;
assign flags[3] = flags3;
assign flags[4] = flags4;
assign flags[5] = flags5;
assign flags[6] = flags6;
assign flags[7] = flags7;
assign flags[8] = flags8;
assign flags[9] = flags9;
bit_find_last_bit #(10) flg_mod (
flagSet,
flagLast,
nFlagIsPrev
);
generate
genvar k;
for (k = 0; k < 10; k = k + 1) begin : jcmp_gen
except_jump_cmp cmp_mod (
flags[k],
jumpType,
jumpTaken_x[k]
);
assign mispred_x[k]=(jumpTaken_x[k] ^ jumpPredTk) | (indirMismatch && jumpType==5'h11) | jumpTbufMiss && INDEX==jumpIndex;
assign jumpTaken=(flagLast[k] && INDEX==jumpIndex) ? jumpTaken_x[k]&~jumpTbufMiss : 1'bz;
assign jumpMisPred = flagLast[k] ? mispred_x[k] : 1'bz;
assign flagOut = (flagLast[k] && INDEX == jumpIndex) ? flags[k] : 'z;
assign flagOutN = flagLast[k] ? flags[k] : 'z;
end
endgenerate
except_jump_cmp cmp_mod (
prevFlags,
jumpType,
jumpTaken_0
);
assign mispred_0=(jumpTaken_0 ^ jumpPredTk) | (indirMismatch && jumpType==5'h11) && INDEX==jumpIndex;
assign jumpTaken = (~nFlagIsPrev && INDEX == jumpIndex) ? jumpTaken_0 : 1'bz;
assign jumpMisPred = (~nFlagIsPrev) ? mispred_0 : 1'bz;
assign flagOut = (~nFlagIsPrev && INDEX == jumpIndex) ? prevFlags : 'z;
assign flagOutN = (~nFlagIsPrev) ? prevFlags : 'z;
endmodule
| 7.48293 |
module cntrl_get_shortIP (
baseIP,
srcIPOff,
jupd0_IP,
jupd0_en,
jupd1_IP,
jupd1_en
);
input [19:0] baseIP;
input [8:0] srcIPOff;
output [19:0] jupd0_IP;
input jupd0_en;
output [19:0] jupd1_IP;
input jupd1_en;
adder2o #(20 - 4) last_add (
baseIP[19:4],
{11'b0, srcIPOff[8:4]},
jupd0_IP[19:4],
jupd1_IP[19:4],
1'b0,
jupd0_en,
jupd1_en
,,,,
);
assign jupd0_IP[3:0] = jupd0_en ? srcIPOff[3:0] : 4'bz;
assign jupd1_IP[3:0] = jupd1_en ? srcIPOff[3:0] : 4'bz;
endmodule
| 6.637794 |
module babbage_diff (
input clk,
rst_n,
input start,
input [5:0] i, //6 bit value f "n"
output [17:0] ans,
output reg ready,
done_tick
);
//babbage function values(3-order polynomial)
localparam f0 = 1, g1 = 5, h2 = 10, c = 6;
//FSM state declarations
localparam [1:0] idle = 2'd0, op = 2'd1, done = 2'd2;
reg [1:0] state_reg, state_nxt;
reg [17:0] f_reg, f_nxt;
reg [17:0] g_reg, g_nxt;
reg [17:0] h_reg, h_nxt;
reg [5:0] n_reg, n_nxt;
//FSM register operations
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state_reg <= idle;
f_reg <= 0;
g_reg <= 0;
h_reg <= 0;
n_reg <= 0;
end else begin
state_reg <= state_nxt;
f_reg <= f_nxt;
g_reg <= g_nxt;
h_reg <= h_nxt;
n_reg <= n_nxt;
end
end
//FSM next-state logics
always @* begin
state_nxt = state_reg;
f_nxt = f_reg;
g_nxt = g_reg;
h_nxt = h_reg;
n_nxt = n_reg;
ready = 0;
done_tick = 0;
case (state_reg)
idle: begin
ready = 1;
if (start == 1) begin
f_nxt = f0;
g_nxt = 0;
h_nxt = 0;
n_nxt = 0;
state_nxt = op;
end
end
op: begin
if (n_reg == i) state_nxt = done;
else begin
n_nxt = n_reg + 1;
case (n_nxt)
1: begin
g_nxt = g1;
f_nxt = g_nxt + f_reg;
end
2: begin
h_nxt = h2;
g_nxt = h_nxt + g_reg;
f_nxt = g_nxt + f_reg;
end
default: begin
h_nxt = c + h_reg;
g_nxt = h_nxt + g_reg;
f_nxt = g_nxt + f_reg;
end
endcase
end
end
done: begin
done_tick = 1;
state_nxt = idle;
end
default: state_nxt = idle;
endcase
end
assign ans = f_reg;
endmodule
| 6.843682 |
module babbage_diff_TB;
// Inputs
reg clk;
reg rst_n;
reg start;
reg [5:0] i;
integer index;
// Outputs
wire [17:0] ans;
wire ready;
wire done_tick;
// Instantiate the Unit Under Test (UUT)
babbage_diff uut (
.clk(clk),
.rst_n(rst_n),
.start(start),
.i(i),
.ans(ans),
.ready(ready),
.done_tick(done_tick)
);
always begin
clk = 0;
#5;
clk = 1;
#5;
end
initial begin
clk = 0;
rst_n = 1;
start = 0;
i = 0;
@(negedge clk);
for (index = 0; index <= 63; index = index + 1) begin
start = 1;
i = index;
wait (done_tick);
start = 0;
@(negedge clk);
$display("f(%0d) -> %0d", index, ans);
repeat (5) @(negedge clk);
end
$stop;
end
endmodule
| 7.340608 |
module babbage_diff_TEST (
input clk,
rst_n,
input sw0,
sw1, //active low
output [7:0] seg_out,
output [5:0] sel_out
);
//FSM state declarations
localparam [1:0] idle = 2'd0, babbage = 2'd1, bin2bcd = 2'd2;
reg [1:0] state_reg, state_nxt;
reg [5:0] mod64_reg, mod64_nxt;
reg start_babbage, start_bin2bcd;
wire done_babbage, done_bin2bcd;
wire sw_redg;
wire [17:0] bin;
wire [3:0] dig0, dig1, dig2, dig3, dig4, dig5;
wire [3:0] mod_dig0, mod_dig1;
reg [3:0] in0, in1, in2, in3, in4, in5;
wire sw0_hi;
assign sw0_hi = !sw0;
//FSM register operations
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state_reg <= idle;
mod64_reg <= 0;
end else begin
state_reg <= state_nxt;
mod64_reg <= mod64_nxt;
end
end
//FSM next-state logics
always @* begin
state_nxt = state_reg;
mod64_nxt = mod64_reg;
start_babbage = 0;
start_bin2bcd = 0;
case (state_reg)
idle: begin
if (sw_redg) begin
mod64_nxt = mod64_reg + 1;
start_babbage = 1;
state_nxt = babbage;
end
end
babbage:
if (done_babbage) begin
start_bin2bcd = 1;
state_nxt = bin2bcd;
end
bin2bcd: if (done_bin2bcd) state_nxt = idle;
default: state_nxt = idle;
endcase
end
//debounce
debounce_explicit deb (
.clk(clk),
.rst_n(rst_n),
.sw(sw0_hi),
.db_level(),
.db_tick(sw_redg)
);
//module instantiations
babbage_diff m0 (
.clk(clk),
.rst_n(rst_n),
.start(start_babbage),
.i(mod64_reg), //6 bit value f "n"
.ans(bin),
.ready(),
.done_tick(done_babbage)
);
bin2bcd m1 //for mod64 counter value
(
.clk(clk),
.rst_n(rst_n),
.start(start_bin2bcd),
.bin(mod64_reg), //limit is 6 digit of bcd
.ready(),
.done_tick(),
.dig0(mod_dig0),
.dig1(mod_dig1),
.dig2(),
.dig3(),
.dig4(),
.dig5()
);
bin2bcd m2 //for babbage value
(
.clk(clk),
.rst_n(rst_n),
.start(start_bin2bcd),
.bin(bin), //limit is 6 digit of bcd
.ready(),
.done_tick(done_bin2bcd),
.dig0(dig0),
.dig1(dig1),
.dig2(dig2),
.dig3(dig3),
.dig4(dig4),
.dig5(dig5)
);
LED_mux m3 (
.clk(clk),
.rst(rst_n),
.in0({1'b0, in0}),
.in1({1'b0, in1}),
.in2({1'b0, in2}),
.in3({1'b0, in3}),
.in4({1'b0, in4}),
.in5({1'b0, in5}), //format: {dp,hex[3:0]}
.seg_out(seg_out),
.sel_out(sel_out)
);
//sw1 chooses which value to display: babbage value or counter(n) value
always @* begin
if (sw1) begin
in0 = mod_dig0;
in1 = mod_dig1;
in2 = 0;
in3 = 0;
in4 = 0;
in5 = 0;
end else begin
in0 = dig0;
in1 = dig1;
in2 = dig2;
in3 = dig3;
in4 = dig4;
in5 = dig5;
end
end
endmodule
| 7.340608 |
module babbage_engine_f (
input wire clk,
reset,
input wire start,
output reg done_tick,
input wire [ 5:0] in,
output wire [19:0] out // length just to match the _h file
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, calc = 2'b01, done = 2'b10;
// constant declarations
localparam F0 = 5, G1 = 5, G_INC = 4;
// signal declaration
reg [1:0] state_reg, state_next;
reg [5:0] n_reg, n_next;
reg [5:0] i_reg, i_next;
reg [13:0] f_reg, f_next;
reg [13:0] g_reg, g_next;
// body
// FSM state and data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
n_reg <= 0;
i_reg <= 0;
f_reg <= 0;
g_reg <= 0;
end else begin
state_reg <= state_next;
n_reg <= n_next;
i_reg <= i_next;
f_reg <= f_next;
g_reg <= g_next;
end
// FSMD next-state logic
always @* begin
state_next = state_reg;
n_next = n_reg;
i_next = i_reg;
f_next = f_reg;
g_next = g_reg;
done_tick = 1'b0;
case (state_reg)
idle:
if (start) begin
state_next = calc;
n_next = in;
i_next = 0;
f_next = F0;
g_next = G1;
end
calc:
if (n_reg == i_reg) state_next = done;
else begin
i_next = i_reg + 1;
f_next = f_reg + g_reg;
g_next = g_reg + G_INC;
end
done: begin
state_next = idle;
done_tick = 1'b1;
end
default: state_next = idle;
endcase
end
// output
assign out[13:0] = f_reg;
assign out[19:14] = 0;
endmodule
| 7.453324 |
module babbage_engine_h (
input wire clk,
reset,
input wire start,
output reg done_tick,
input wire [ 5:0] in,
output wire [19:0] out
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, calc = 2'b01, done = 2'b10;
// constant declarations
localparam H0 = 1, F1 = 5, G2 = 10, G_INC = 6;
// signal declaration
reg [1:0] state_reg, state_next;
reg [5:0] n_reg, n_next;
reg [5:0] i_reg, i_next;
reg [19:0] h_reg, h_next;
reg [19:0] f_reg, f_next;
reg [19:0] g_reg, g_next;
// body
// FSM state and data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
n_reg <= 0;
i_reg <= 0;
h_reg <= 0;
f_reg <= 0;
g_reg <= 0;
end else begin
state_reg <= state_next;
n_reg <= n_next;
i_reg <= i_next;
h_reg <= h_next;
f_reg <= f_next;
g_reg <= g_next;
end
// FSMD next-state logic
always @* begin
state_next = state_reg;
n_next = n_reg;
i_next = i_reg;
h_next = h_reg;
f_next = f_reg;
g_next = g_reg;
done_tick = 1'b0;
case (state_reg)
idle:
if (start) begin
state_next = calc;
n_next = in;
i_next = 0;
h_next = H0;
f_next = F1;
g_next = G2;
end
calc:
if (n_reg == i_reg) state_next = done;
else begin
i_next = i_reg + 1;
h_next = h_reg + f_reg;
f_next = f_reg + g_reg;
g_next = g_reg + G_INC;
end
done: begin
state_next = idle;
done_tick = 1'b1;
end
default: state_next = idle;
endcase
end
// output
assign out = h_reg;
endmodule
| 7.453324 |
module babbage_engine_top (
input wire clk,
input wire btnD, // reset
input wire btnC, // start
input wire [5:0] sw,
input wire sw_sel,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire reset;
wire start;
reg calc_start, bcd_start;
wire bcd_done, calc_done, calc_done_f, calc_done_h;
wire calc_start_f, calc_start_h;
wire [19:0] calc_out, calc_out_f, calc_out_h;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
reg [3:0] dp_in;
// component instantiation
debounce db_start_unit (
.clk(clk),
.reset(reset),
.sw(btnC),
.db_level(),
.db_tick(start)
);
babbage_engine_f babbage_f_unit (
.clk(clk),
.reset(reset),
.start(calc_start_f),
.done_tick(calc_done_f),
.in(sw),
.out(calc_out_f)
);
babbage_engine_h babbage_h_unit (
.clk(clk),
.reset(reset),
.start(calc_start_h),
.done_tick(calc_done_h),
.in(sw),
.out(calc_out_h)
);
bin2bcd bin2bcd_unit (
.clk(clk),
.reset(reset),
.start(bcd_start),
.bin(calc_out[13:0]),
.ready(),
.done_tick(bcd_done),
.bcd3(bcd3),
.bcd2(bcd2),
.bcd1(bcd1),
.bcd0(bcd0)
);
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.dp_in(4'b1111),
.hex3(bcd3),
.hex2(bcd2),
.hex1(bcd1),
.hex0(bcd0),
.an(an),
.sseg(sseg)
);
// assignments and equation selection
assign reset = btnD;
assign calc_start_f = (sw_sel == 0) ? calc_start : 0;
assign calc_start_h = (sw_sel == 1) ? calc_start : 0;
assign calc_out = (sw_sel == 0) ? calc_out_f : calc_out_h;
assign calc_done = (sw_sel == 0) ? calc_done_f : calc_done_h;
// main control FSM
localparam [1:0] idle = 2'b00, calc = 2'b01, bin2bcd = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
// FSM state register
always @(posedge clk, posedge reset)
if (reset) state_reg <= idle;
else state_reg <= state_next;
// FSMD next-state logic
always @* begin
state_next = state_reg;
calc_start = 1'b0;
bcd_start = 1'b0;
case (state_reg)
idle:
if (start) begin
state_next = calc;
calc_start = 1'b1;
end
calc:
if (calc_done) begin
state_next = bin2bcd;
bcd_start = 1'b1;
end
bin2bcd: if (bcd_done) state_next = idle;
endcase
end
endmodule
| 7.453324 |
module line_ram (
input clk,
input [4:0] addr,
output reg [31:0] dout,
input [31:0] din,
input we,
input re
);
reg [31:0] ram[0:31];
initial $readmemh("lines.hex", ram);
always @(posedge clk) begin
if (we) ram[addr] <= din;
else if (re) dout <= ram[addr];
end
endmodule
| 7.304478 |
module GG (
input p0,
p1,
p2,
g0,
g1,
g2,
c0,
output N
);
wire w, f, m;
AO2 #(19, 17) G1 (
w,
p2,
g1,
g2
);
AO2 #(19, 17) G2 (
f,
p0,
c0,
g0
);
AND2 #(13, 17) G3 (
m,
p2,
p1
);
AO2 #(19, 17) G4 (
N,
w,
f,
m
);
endmodule
| 6.747396 |
module backAnimations (
animationClOCK,
BACK1X,
BACK1Y,
BACK2X,
BACK2Y,
score,
BACK1SKIPX,
BACK2SKIPX
);
input animationClOCK;
output [9:0] BACK1X;
output [9:0] BACK1Y;
output [9:0] BACK2X;
output [9:0] BACK2Y;
output [9:0] BACK1SKIPX;
output [9:0] BACK2SKIPX;
input [9:0] score;
localparam [9:0] minScrollSpeed = 100;
localparam [9:0] scrollPerScore = 30;
reg [19:0] realx;
always @(posedge animationClOCK) begin
if (realx < (minScrollSpeed + (scrollPerScore * score))) begin
realx = 640 * 100;
end else begin
realx = realx - (minScrollSpeed + (scrollPerScore * score));
end
end
assign BACK1X = realx / 100;
assign BACK1Y = 0;
assign BACK2X = 0;
assign BACK2Y = 0;
assign BACK1SKIPX = 0;
assign BACK2SKIPX = (640 - (realx / 100) <= 5) ? 0 : (640 - (realx / 100) - 5);
endmodule
| 7.261035 |
module BackGroundDelegate #(
parameter ratio = 1,
dx = -6'd20
) (
input wire moveClk,
input wire rst,
input wire [8:0] GroundY,
input wire [9:0] vgaX,
input wire [9:0] vgaY,
input wire [1:0] gameState,
output wire inGrey,
output wire inWhite
);
localparam groundDisplayOffset = 0;
// Draw horizon (Module: BackGround)
wire [3:0] horizonSEL; // Multiplexor
assign horizonSEL1 = 4'b0001; // 选择画地面
assign horizonSEL2 = 4'b0000;
reg signed [11:0] Ground_1_X;
reg signed [11:0] Ground_2_X;
wire [ 5:0] GroundH;
localparam GroundW = 11'd1200;
wire Ground_1_inGrey;
wire Ground_2_inGrey;
/* Move Ground 1 & 2 */
always @(posedge moveClk or posedge rst) begin
if (rst) begin
Ground_1_X <= 0;
Ground_2_X <= GroundW;
end else begin
case (gameState)
2'b00: begin
Ground_1_X <= 0;
Ground_2_X <= GroundW;
end
2'b10: begin
if (Ground_1_X == -1200) begin
Ground_1_X <= GroundW - 1;
Ground_2_X <= Ground_2_X - 1;
end else if (Ground_2_X == -1200) begin
Ground_2_X <= GroundW - 1;
Ground_1_X <= Ground_1_X - 1;
end else begin
Ground_1_X <= Ground_1_X - 1;
Ground_2_X <= Ground_2_X - 1;
end
end
2'b01: begin
Ground_1_X <= Ground_1_X;
Ground_2_X <= Ground_2_X;
end
default: begin
Ground_1_X <= 0;
Ground_2_X <= GroundW;
end
endcase
end
end
wire Ground1_grey;
wire Ground2_grey;
// Change ox oy to 12 bit here!
drawBackGround #(
.ratio(ratio)
) horizon1 (
.rst(rst),
.ox(Ground_1_X + 1200),
.oy(GroundY - groundDisplayOffset),
.X(vgaX + 1200),
.Y(vgaY),
.select(horizonSEL1),
.inGrey(Ground_1_inGrey)
);
drawBackGround #(
.ratio(ratio)
) horizon2 (
.rst(rst),
.ox(Ground_2_X + 1200),
.oy(GroundY - groundDisplayOffset),
.X(vgaX + 1200),
.Y(vgaY),
.select(horizonSEL2),
.inGrey(Ground_2_inGrey)
);
assign inGrey = Ground_1_inGrey | Ground_2_inGrey;
endmodule
| 7.613144 |
module background_effects (
pixel_color,
x,
y,
enable_effect,
clk,
slow_clk
);
output [3:0] pixel_color;
input [9:0] x;
input [8:0] y;
input [2:0] enable_effect;
input clk, slow_clk;
reg [2:0] pixel_color;
wire [4:0] h_count_sin;
reg [5:0] h_count_increment;
reg [5:0] increment;
wire [6:0] x_shift;
assign x_shift = x[6:0] - 6'b10_0000;
wire [383:0] image_mem_out;
image2 image (
.clka(clk), // input clka
.addra({enable_effect[2], y[6:0]}), // input [6 : 0] addra
.douta(image_mem_out) // output [383 : 0] douta
);
sin_lut sin_val (
h_count_sin,
h_count_increment
);
always @(posedge clk) begin
if ((y[8:4] < 8) & (x[9:4] > 33) & enable_effect[1]) begin
pixel_color <= ({
image_mem_out[{x_shift[6:0], 2'b00}], //9-2 = 7
image_mem_out[{x_shift[6:0], 2'b01}],
image_mem_out[{x_shift[6:0], 2'b10}]
});
end else begin
if ((y[8:4] == h_count_sin) & enable_effect[0]) begin
if (h_count_sin[3:1] == 3'b000) begin
pixel_color[0] <= 1;
end else begin
pixel_color[0] <= h_count_sin[3];
end
pixel_color[1] <= h_count_sin[1];
pixel_color[2] <= h_count_sin[2];
end else begin
pixel_color <= 3'b000;
end
if ((increment + x[9:4]) < 40) h_count_increment <= increment + x[9:4];
else h_count_increment <= increment + x[9:4] - 40;
end
end
always @(posedge slow_clk) begin
if (increment == 39) increment <= 0;
else increment <= increment + 1;
end
endmodule
| 6.584543 |
module background_engine (
input wire clk,
input wire video_on,
input wire [3:0] x_offset,
input wire [9:0] x,
y,
input wire [15:0] ram_data,
output reg [15:0] ram_addr,
output wire pixel_on,
output wire [11:0] color
);
reg [13:0] rom_addr;
reg [6:0] rom_x, rom_y;
wire [11:0] rom_data;
parameter TILE_WIDTH = 16;
parameter TILE_HEIGHT = 16;
parameter TILE_COLS = 640 / TILE_WIDTH;
parameter TILE_ROWS = 480 / TILE_HEIGHT;
`define TILE_COL ram_data[2:0]
`define TILE_ROW ram_data[5:3]
`define X_FILP ram_data[6:6]
`define Y_FLIP ram_data[7:7]
`define ENABLE ram_data[8:8]
`define POS_X ((x + x_offset) / TILE_WIDTH)
`define POS_Y (y / TILE_HEIGHT)
bg_rom bg_rom (
.clk(clk),
.video_on(video_on),
.x(rom_x),
.y(rom_y),
.color(rom_data)
);
always @* begin
ram_addr = `POS_X + `POS_Y * TILE_COLS;
if (`X_FILP == 0) rom_x = `TILE_COL * TILE_WIDTH + ((x + x_offset) % TILE_WIDTH);
else rom_x = `TILE_COL * TILE_WIDTH + (TILE_WIDTH - 1 - ((x + x_offset) % TILE_WIDTH));
if (`Y_FLIP == 0) rom_y = `TILE_ROW * TILE_HEIGHT + (y % TILE_HEIGHT);
else rom_y = `TILE_ROW * TILE_HEIGHT + TILE_HEIGHT - 1 - (y % TILE_HEIGHT);
end
assign pixel_on = ~(rom_data == 12'h00f | `ENABLE == 0);
assign color = (rom_data == 12'h00f | `ENABLE == 0) ? 12'b0 : rom_data;
endmodule
| 7.262815 |
module backlight (
input i_Clk,
input i_Touch,
output o_Light
);
localparam STATE_DISPLAY_OFF = 1'd0;
localparam STATE_DISPLAY_ON = 1'd1;
reg [33:0] r_Counter = 34'd0;
reg r_CurrentState = STATE_DISPLAY_ON;
reg r_NextState;
/* State transitions */
always @(posedge i_Clk) begin
r_CurrentState <= r_NextState;
end
always @(*) begin
r_NextState = r_CurrentState;
case (r_CurrentState)
STATE_DISPLAY_OFF: begin
if (i_Touch) r_NextState = STATE_DISPLAY_ON;
end
STATE_DISPLAY_ON: begin
if (r_Counter[33]) r_NextState = STATE_DISPLAY_OFF;
end
endcase
end
/* Idle counter */
always @(posedge i_Clk) begin
if (i_Touch) r_Counter <= 34'd0;
else r_Counter <= r_Counter + 1'd1;
end
/* Backlight control */
assign o_Light = (r_CurrentState == STATE_DISPLAY_ON);
endmodule
| 6.595377 |
module Backpack_tb ();
reg clk, res;
wire [15:0] max_value;
wire [ 7:0] cathodes;
wire [ 3:0] ano;
initial begin
clk <= 0;
res <= 1;
#10 res <= 0;
end
always begin //时钟信号
#5 clk <= ~clk;
end
top mytop (
clk,
res,
ano,
cathodes
);
/*iverilog */
initial begin
$dumpfile("Backpack.vcd"); //产生波形文件
$dumpvars(0, Backpack_tb);
#500 //仿真时间
$finish;
end
/*iverilog */
endmodule
| 6.51317 |
module frontReq_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 44 - 13 + 64 - 27;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
reg [DATA_WIDTH-1:0] ram[ADDR_COUNT-1:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (rst) read_addr_reg <= {ADDR_WIDTH{1'b0}};
else if (read_clkEn) read_addr_reg <= read_addr;
if (write_wen) ram[write_addr] <= write_data;
end
endmodule
| 8.003613 |
module front_strip_ECC (
dataIn,
dataOut,
par
);
input [39:1] dataIn;
output [31:0] dataOut;
output par;
assign dataOut = {dataIn[38:33], dataIn[31:17], dataIn[15:9], dataIn[7:5], dataIn[3]};
assign par = dataIn[39];
endmodule
| 7.488015 |
module backscatterv1 (
clk,
rst_n,
clkout1,
clkout2,
clkout3,
clkout4,
clkp,
key0,
led0
);
input clk, rst_n; //输入信号，其中clk连接到FPGA的C1脚，频率为12MHz
output clkout1,clkout2,clkout3,clkout4,clkp; //输出信号，可以连接到LED观察分频的时钟
input key0;
output led0;
wire [1:0] clk0; // 12 M
wire [1:0] clk1; // 100 M
// wire[1:0] clk2;
ppl m1 (
.inclk0(clk),
.c0(clk0),
.c1(clk1)
// .c2(clk2)
);
process the_proc (
.clk (clk1),
.rst_n(rst_n),
.sig (clkout1),
.ctrl1(clkout2),
.pwm (clkout3)
);
endmodule
| 6.998296 |
module BACKUP_APF (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [14:0] address_a;
input [14:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.numwords_b = 32768,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
| 6.845669 |
module BACKUP_APF (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [14:0] address_a;
input [14:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.845669 |
module BackwardMaccum #(
parameter NN = 7
, parameter NC = 11
, parameter WV = 5
, parameter BURST = "yes"
) (
input iValid_AM_Weight
, output oReady_AM_Weight
, input [ NC*NN*WV-1:0] iData_AM_Weight
, input iValid_AM_Delta0
, output oReady_AM_Delta0
, input [ NN*WV-1:0] iData_AM_Delta0
, output oValid_BM_Accum2
, input iReady_BM_Accum2
, output [NC*($clog2(NN)+WV)-1:0] oData_BM_Accum2
, input iRST
, input iCLK
);
wire [ NC-1:0] wvld_wsn;
wire [ NC-1:0] wrdy_wsn;
wire [NC*($clog2(NN)+WV)-1:0] wdata_wsn;
Maccum #(
.SIZE_A(NN)
, .SIZE_B(NC)
, .WIDTH (WV)
, .BURST (BURST)
) maccum (
.iValid_AM_W(iValid_AM_Weight)
, .oReady_AM_W(oReady_AM_Weight)
, .iData_AM_W(iData_AM_Weight)
, .iValid_AM_S(iValid_AM_Delta0)
, .oReady_AM_S(oReady_AM_Delta0)
, .iData_AM_S(iData_AM_Delta0)
, .oValid_BM_WS(wvld_wsn)
, .iReady_BM_WS(wrdy_wsn)
, .oData_BM_WS(wdata_wsn)
, .iRST(iRST)
, .iCLK(iCLK)
);
CombinerN #(
.SIZE (NC)
, .WIDTH($clog2(NN) + WV)
) combinerNA (
.iValid_AS(wvld_wsn)
, .oReady_AS(wrdy_wsn)
, .iData_AS (wdata_wsn)
, .oValid_BM(oValid_BM_Accum2)
, .iReady_BM(iReady_BM_Accum2)
, .oData_BM (oData_BM_Accum2)
);
endmodule
| 7.688029 |
module backwardskidbuffer #(
parameter L = 8,
parameter OPTREG = 0
) (
input clk,
input rst,
output reg ready_f,
input valid_f,
input [L-1:0] data_f,
input ready_b,
output reg valid_b,
output reg [L-1:0] data_b
);
reg state;
wire ready;
reg pre_valid;
reg [L-1:0] data_pre;
//reg buffer_valid;
//reg [L-1:0] data_buffer;
//reg ready_buffer;
always @(posedge clk) begin
if (!rst) begin
state <= 0;
end else if (!state) begin
if (ready) begin
valid_b <= valid_f;
data_b <= data_f;
ready_f <= 1'b1;
end else begin
pre_valid <= valid_f;
data_pre <= data_f;
ready_f <= 1'b0;
state <= !state;
end
end else if (ready) begin
valid_b <= pre_valid;
data_b <= data_pre;
ready_f <= 1'b1;
state <= !state;
end
end
//assign ready_f = ready_buffer ;
//assign data_b = data_buffer;
//assign valid_b = buffer_valid;
assign ready = ready_b || !valid_b;
endmodule
| 6.899775 |
module Backward_Registered #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
start,
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input start;
input src_vaild;
input [WIDTH-1:0] src_data_in;
input dst_ready;
output dst_vaild;
output [WIDTH-1:0] dst_data_out;
output reg src_ready;
reg data_flag;
reg data_flag_r1;
reg data_flag_r2;
reg [WIDTH-1:0] data_buff;
reg data_hold;
always @(posedge clk) begin
if (s_rst == 1'b1) begin
data_flag <= 1'b0;
data_flag_r1 <= 1'b0;
data_flag_r2 <= 1'b0;
end else begin
data_flag <= src_vaild;
data_flag_r1 <= data_flag;
data_flag_r2 <= data_flag_r1;
end
end
always @(posedge clk) begin
if (s_rst == 1'b1) src_ready <= 1'b0;
else src_ready <= dst_ready;
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
data_buff <= {WIDTH{1'b0}};
end else data_buff <= src_data_in;
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
data_hold <= 1'b0;
end else if (src_vaild & src_ready) begin
data_hold <= 1'b1;
end else begin
data_hold <= 1'b0;
end
end
assign dst_data_out = (src_ready == 1) ? src_data_in : data_buff;
assign dst_vaild = (src_vaild & !(!data_flag_r2 & data_flag_r1) ) | data_hold;//消去第三周期的dst_vaild信号，防止多存数据, data_hold,为了延长一个数据有效
endmodule
| 8.285036 |
module Backward_Registered_v1 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
idle, //原本start改为idle
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input idle;
input src_vaild;
input [WIDTH-1:0] src_data_in;
input dst_ready;
output dst_vaild;
output [WIDTH-1:0] dst_data_out;
output src_ready;
reg data_flag;
reg data_flag_r1;
reg data_flag_r2;
reg hold_ready;
reg hold_ready_flag;
reg idle_r;
reg src_ready_r;
reg idle_r1;
reg idle_r2;
reg delr;
//======== 异步转同步======
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
idle_r1 <= 1'b0;
idle_r2 <= 1'b0;
end else begin
idle_r1 <= idle;
idle_r2 <= idle_r1;
end
end
//============ end =========
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
idle_r <= 1'b0;
end else begin
idle_r <= idle_r2;
end
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
hold_ready <= 1'b0;
end else begin
hold_ready <= (!data_flag_r2 & data_flag_r1);
end
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
hold_ready_flag <= 1'b0;
end else if (src_vaild == 1'b0) begin
hold_ready_flag <= 1'b0;
end else if (hold_ready == 1'b1) begin
hold_ready_flag <= 1'b1;
end
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
data_flag <= 1'b0;
data_flag_r1 <= 1'b0;
data_flag_r2 <= 1'b0;
end else begin
data_flag <= src_vaild;
data_flag_r1 <= data_flag;
data_flag_r2 <= data_flag_r1;
end
end
always @(posedge clk) begin
if (s_rst == 1'b1) src_ready_r <= 1'b0;
else
src_ready_r <= dst_ready & dst_vaild | (hold_ready & idle_r); //修改部分，dst_vaild 没有的时候取消 (hold_ready & idle_r)去除多的高电平，防止让source多加
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
delr <= 1'b0;
end else if (hold_ready_flag) begin
delr <= dst_ready;
end
end
assign src_ready = ((hold_ready_flag && src_vaild && idle_r) | src_ready_r) & (!(delr && !dst_ready)) ;
//(!(delr && !dst_ready)) 去除多一拍 (hold_ready_flag && src_vaild && idle_r) 提前一拍
assign dst_data_out = src_data_in;
assign dst_vaild = (src_vaild & !(!data_flag_r2 & data_flag_r1) ) ;//消去第三周期的dst_vaild信号，防止多存数据,
endmodule
| 8.285036 |
module Backward_Registered_v3 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
idle, //原本start改为idle
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input idle;
input src_vaild;
input [WIDTH-1:0] src_data_in;
input dst_ready;
output dst_vaild;
output [WIDTH-1:0] dst_data_out;
output src_ready;
reg data_buffer_full;
reg [WIDTH-1:0] data_buffer_data;
//============================data buffer ===================
always @(posedge clk) begin
if (s_rst == 1'b1) begin
// reset
data_buffer_full <= 1'b0;
end else if ((src_vaild && src_ready) && (dst_vaild && !dst_ready)) begin
data_buffer_full <= 1'b1;
end else if (dst_ready == 1'b1) data_buffer_full <= 1'b0;
end
always @(posedge clk) begin
if (s_rst == 1'b1) begin
data_buffer_data <= 'd0;
end else if (src_ready) begin
data_buffer_data <= src_data_in;
end
end
//=============================== data buffer end====================================
assign src_ready = !data_buffer_full;//data buffer 没有数据的时候，拉高，取master数据
assign dst_data_out = (data_buffer_full == 1'b1) ? data_buffer_data : src_data_in; //
assign dst_vaild = data_buffer_full | src_vaild;
endmodule
| 8.285036 |
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