code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ax_pwm #(
parameter N = 16 //pwm bit width
) (
input clk,
input rst,
input [N - 1:0] period,
input [N - 1:0] duty,
output pwm_out
);
reg [N - 1:0] period_r;
reg [N - 1:0] duty_r;
reg [N - 1:0] period_cnt;
reg pwm_r;
assign pwm_out = pwm_r;
... | 6.821939 |
module aynDff (
D,
clr_n,
clk,
Q
);
input D;
input clr_n;
input clk;
output reg Q;
always @(negedge clr_n or posedge clk) begin
if (!clr_n) begin
Q <= 0;
end else Q <= D;
end
endmodule
| 7.467651 |
module aysnc_fifo_16_to_32 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [9:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`en... | 6.755726 |
module aysnc_fifo_32_to_16 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`en... | 6.625786 |
module AYUMU (
input CLK,
input [31:0] INPUT,
output [31:0] OUTPUT
);
reg [10:0] CLKS;
always @(posedge CLK) begin
case (CLKS)
5'b00001: CLKS <= 5'b00010;
5'b00010: CLKS <= 5'b00100;
5'b00100: CLKS <= 5'b01000;
5'b01000: CLKS <= 5'b10000;
5'b10000: CLKS <= 5'b00001;
... | 6.94234 |
module ayush_and_gate (
out,
a,
b
);
input a, b;
output reg out;
always @(a, b) begin
out = a & b;
end
endmodule
| 7.307613 |
module ay_model_channel // one of three identical AY channels
(
input wire f1, //
input wire _f1, // clock phases
input wire cnt_clk, //
input wire rst_1, // reset
input wire reg_wr, // common write/store strobes
input wire _reg_wr,
input wire sel_tone_lo, // select for t... | 8.127227 |
module ay_model_gpio // one of two identical AY gpio ports
(
inout wire [7:0] b,
inout tri1 [7:0] io,
input wire _reg_wr,
input wire wr_reg_1,
input wire _r7_b_1,
input wire _en_reg_rd
);
wire [7:0] int_output;
ay_model_latch out_latch (
.d(b),
.load(wr_reg_1),
.store(_r... | 6.509412 |
module ay_model_clk_ff // clock flipflop
#(
parameter UP_RST = 1
) (
input wire up_phase, // upper (on schematics) phase
input wire dn_phase, // lower (on schematics) phase
input wire set, // upper gate clear signal
input wire rst,
output reg q_up, // upper and lower (on schematics) output... | 8.220087 |
module ay_model_latch // 2-phase latch
#(
parameter WIDTH = 8
) (
input wire load, // when 1, latch is transparent
input wire store, // when 1, latch stores its last value
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q,
output wire [WIDTH-1:0] _q
);
trireg [WIDTH-1:0] inwire;
ass... | 8.729969 |
module ay_model_rw_latch // readable and writable latch
#(
parameter WIDTH = 8
) (
input wire gate, // input gating
input wire write, // write strobe (REG_WR on schematics)
input wire store, // store strobe (/REG_WR on schematics)
inout wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q,
o... | 8.361155 |
module ay_model_counter // async resettable counter with a comparator
#(
parameter WIDTH = 0
) (
input wire f1,
input wire _f1, // clocking phases
input wire rst, // async reset
input wire [WIDTH-1:0] period,
input wire [WIDTH-1:0] _period, // inverse copy of period
output wire carry_ou... | 9.090441 |
module ay_model_shiftreg #(
parameter WIDTH = 17
) (
input wire _f,
input wire f,
input wire rst,
input wire shift_in,
output wire [WIDTH-1:0] result
);
wire [WIDTH-1:0] shin;
trireg [WIDTH-1:0] l1;
trireg [WIDTH-1:0] l2;
// shift in
assign shin = {l2[WIDTH-2:0], shift_in};
ass... | 8.540725 |
module ay_note_ram (
addr,
data
);
input wire [6:0] addr;
output wire [11:0] data; //12 бит - максимум
reg [11:0] note_ram[0:127];
initial begin
note_ram[0] <= 12'd03977;
note_ram[1] <= 12'd03977;
note_ram[2] <= 12'd03977;
note_ram[3] <= 12'd03977;
note_ram[4] <= 12'd03977... | 6.655261 |
module hazard_f (
input wire a,
input wire b,
output wire f
);
assign f = ~a & b | a & b;
endmodule
| 6.577595 |
module hazard_e #(
// Retraso por defecto para las operaciones lógicas
/* Dentro de un módulo se pueden definir "parámetros". Los parámetros
* son constantes que pueden usarse dentro del módulo para facilitar el
* diseño. A diferencia de las macros declaradas con "`define", los
* parámetros son elem... | 9.031604 |
module: Az_toLSP_FSM
// Dependencies: L_mac.v, L_msu.v,L_shl,L_sub,add,mult,norm_s
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Az_LSP_Test_v;
`include "paramList.v"
// Inputs
reg clk;
reg res... | 7.260268 |
module a_4 (
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
key,
dout
);
input [31:0] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
input [127:0] key;
output [127:0] dout;
//col 1
a col_00 (
... | 6.66563 |
module a_block (
sum,
gen,
prop,
c_in,
a,
b
);
input a, b, c_in;
output sum, gen, prop;
wire w;
or (prop, a, b);
and (gen, a, b);
xor (w, a, b);
xor (sum, w, c_in);
endmodule
| 6.533783 |
module a_compress (
input clk,
input iq,
input signed [17:0] d_in,
output signed [17:0] d_out,
// Adjust saturation characteristics
(*external*)
input [15:0] sat_ctl // external
);
// Pipeline match
// "Free" spot for multiplier for overall gain setting (no added latency)
wire signed... | 6.90251 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end ... | 6.615218 |
module a_filter_reference_32x11 (
input [31:0] x_in,
input clk,
input [5:0] reset,
output [31:0] y_out
);
wire [10:0] a1_1;
wire [10:0] a1_2;
wire [10:0] a1_3;
wire [10:0] a1_4;
wire [10:0] b1;
// update coefficent
// h_fixp(i) = sign(h_fixp(i))*floor(abs(h_fixp(i))/M)*M;
assign a1_1 =... | 6.772869 |
module a_filter_reference_32x32 (
input [31:0] x_in,
input clk,
input [5:0] reset,
output [31:0] y_out
);
wire [31:0] a1_1;
wire [31:0] a1_2;
wire [31:0] a1_3;
wire [31:0] a1_4;
wire [31:0] b1;
// update coefficent
// h_fixp(i) = sign(h_fixp(i))*floor(abs(h_fixp(i))/M)*M;
assign a1_1 =... | 6.772869 |
module a_input_register (
load_zero,
load_sb,
zero,
sb,
a_out
);
input load_zero; //net: 984; aka zero_add
input load_sb; //net: 549; aka sb_add
input [7:0] zero; //all zeros
input [7:0] sb; //special data bus
output reg [7:0] a_out; //goes to the alu
always @(*) begin
if (load... | 7.009598 |
module alu (
ALU_out,
Carry_out,
A,
B,
ALU_sel,
clk
);
parameter n = 32;
input [n-1:0] A, B;
input [2:0] ALU_sel;
input clk;
output [n-1:0] ALU_out;
output Carry_out;
reg [n-1:0] ALU_result;
wire [n:0] temp, prod;
assign ALU_out = ALU_result;
assign temp = {1'b0, A} + {1'b0,... | 7.764211 |
module booth_multiplier (
ans,
m,
q,
clk,
start
);
parameter n = 16;
input [n-1:0] m, q;
output reg [2*n-1:0] ans;
input clk, start;
reg [2:0] state;
reg [5:0] cnt;
reg [n-1:0] ab, qb;
reg qm1;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
... | 6.943306 |
module a_model (
input clk,
input [1:0] subcycle,
input signed [17:0] coeff,
input signed [17:0] drive,
output signed [17:0] cavity,
output error
);
// subcycle = 2 coeff = drive coupling, drive input is valid
// subcycle = 3 coeff = cavity decay bandwidth
// subcycle = 0 or 1 other ... | 6.840715 |
module a_port_unit (
clk_core,
rst_x,
// port side
i_req,
i_we,
i_len,
o_ack,
i_strw,
o_ackw,
o_strr,
o_dbr,
// internal
i_cack,
o_wdata_read_end,
i_wdata_ack,
i_strr,
i_dbr
);
`include "polyphony_params.v"
////////////////////////////
// Paramet... | 7.91759 |
module A_reg (
clk,
a,
a_reg
);
input clk;
input [31:0] a;
output reg [31:0] a_reg;
always @(posedge clk) a_reg <= a;
endmodule
| 7.85871 |
module A_reg_module (
clk,
read_data1_in,
read_data1_out
);
input clk;
input [31:0] read_data1_in;
output [31:0] read_data1_out;
reg [31:0] read_data1_out;
always @(posedge clk) read_data1_out <= read_data1_in;
endmodule
| 7.124601 |
module a_up_counter (
L,
clk
);
input clk;
output [3:0] L;
wire qbar;
JK_FF ff1 (
1,
1,
L[0],
qbar,
clk
);
JK_FF ff2 (
1,
1,
L[1],
qbar,
~L[0]
);
JK_FF ff3 (
1,
1,
L[2],
qbar,
~L[1]
);
JK_FF ff4 (
... | 6.723838 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end ... | 6.615218 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b01_comb/b01_comb.opt (
line1_pad,
line2_pad,
\stato_reg[0]/NET0131 ,
\stato_reg[1]/NET0131 ,
\stato_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g220/_2_ ,
\g221/_0_ ,
\g222/_0_ ,
\g224/_0_ ,... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b02_comb/b02_comb.opt (
linea_pad,
\stato_reg[0]/NET0131 ,
\stato_reg[1]/NET0131 ,
\stato_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g110/_1_ ,
\g111/_0_ ,
\g112/_0_ ,
\g128/_0_
);
input linea... | 6.939825 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b06_comb/b06_comb.opt (
cont_eql_pad,
eql_pad,
\state_reg[0]/NET0131 ,
\state_reg[1]/NET0131 ,
\state_reg[2]/NET0131 ,
_al_n0,
_al_n1,
\g211/_0_ ,
\g212/_0_ ,
\g213/_0_ ,
\g218/_0_ ... | 6.939825 |
module b1 (
pi0,
pi1,
pi2,
po0,
po1,
po2,
po3
);
input pi0, pi1, pi2;
output po0, po1, po2, po3;
wire new_n11_, new_n12_;
assign po1 = ~new_n11_;
assign po2 = ~new_n12_;
assign po3 = ~pi2;
assign new_n11_ = ~pi0 ^ pi1;
assign new_n12_ = (pi0 & (~pi1 | pi2)) | (~pi0 & (pi1 | ~... | 7.122641 |
module eval_test;
parameter l=16;
reg clk, reset;
reg `L din;
wire `L dout, a;
wire `L d;
wire wr_b, rd_b, ble_b, bhe_b;
b16_eval flk10k30e(clk, reset, din, dout, a, d, wr_b, rd_b, ble_b, bhe_b);
integer oldtime;
always @(dout)
begin
$display("%d: dout <= %b", $time-oldtime, dou... | 6.710345 |
module test;
wire [15:0] a0, a1, d0, d1;
wire DP, DN, send0, send1;
reg clk, nreset;
assign {DP, DN} = (send0 | send1) ? 2'bzz : 2'b10;
b16_eval_usb #(16, "master.hex") core0 (
clk,
nreset,
a0,
d0,
wr_b0,
rd_b0,
ble_b0,
bhe_b0,
DP,
DN,
dif0,
... | 6.964054 |
module b16_eval_usb (
clk,
nreset,
a,
d,
wr_b,
rd_b,
ble_b,
bhe_b,
DP,
DN,
dif,
send,
dp,
dn
);
parameter l = 16, bootram = "b16.hex";
input clk, nreset;
output `L a;
inout `L d;
output wr_b, rd_b, ble_b, bhe_b;
input DP, DN, dif;
output send, dp, dn... | 6.742856 |
module b16_eval(clk, reset, din, dout, a, d, wr_b, rd_b, ble_b, bhe_b);
parameter l=16;
input clk, reset;
input `L din;
output `L dout, a;
inout `L d;
output wr_b, rd_b, ble_b, bhe_b;
wire `L addr, dwrite, a_out;
wire r, waits;
wire [1:0] w;
reg `L dout_out, data, a_old;
... | 7.023475 |
module for c16 core */
`define L [l-1:0]
`timescale 1ns / 1ns
module memory(reset, sel, addr, r, w, data, dout);
parameter l=16;
input reset;
input `L addr;
input sel, r;
input [1:0] w;
output `L data;
input `L dout;
reg `L mem[((1<<(l-1)))-1:0];
wire ... | 7.899441 |
module alu(res, carry, zero, T, N, c, inst);
parameter l=16;
input `L T, N;
input c;
input [2:0] inst;
output `L res;
output carry, zero;
wire prop, andor, selr;
assign #1 { prop, andor, selr } = inst;
wire `L sum, logic;
wire cout;
assign { cout, sum } =
... | 7.249315 |
module b16toBCD_tb;
reg [15:0] to_display;
reg enable;
wire [3:0] D5;
wire [3:0] D4;
wire [3:0] D3;
wire [3:0] D2;
wire [3:0] D1;
integer file, i, j, limit;
localparam period = 20;
b16toBCD UUT (
.to_display(to_display),
.enable(enable),
.D5(D5),
.D4(D4),
.D3(D3),
... | 6.969533 |
module b16_4to1_bridge //4时钟16bits合成 1时钟64bits
(
input wire clk_i,
input wire clk_i_div4,
input wire rst_n,
input wire [15: 0]d_i,
input wire d_i_en,//d_i_en使能期间必须保证有4的倍数个时钟
output wire clk_o, //clk_o与d_o,d_o_valid,d_i_en...相位不确定
output reg [63:0] d_o,
... | 6.907193 |
module b16_loom (
input clk,
input rst_n,
input sel,
input sign,
// in1, in2
input [15:0] in1,
input [15:0] in2,
input [31:0] in3,
// output
output [31:0] out
);
reg [15:0] in1_reg;
reg [15:0] in2_reg;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) be... | 7.781791 |
module b16_loom_AC1 (
input clk,
input rst_n,
// in1, in2
input [15:0] in1,
input [15:0] in2,
// output
output [19:0] out
);
wire [3:0] psum;
assign psum = in1[0] & in2[0]
+ in1[1] & in2[1]
+ in1[2] & in2[2]
+ in1[3] & in2[3]
+ in... | 6.855877 |
module b16_loom_AC2 (
input clk,
input rst_n,
// in1, in2
input [19:0] in1,
input [31:0] in2,
input sign,
input sel,
// output
output [31:0] out
);
wire [19:0] sign_in1;
assign sign_in1 = (sign == 1'b1) ? ~in1 : in1;
wire [31:0] sel_in2;
assign sel_in2 = (sel == 1'b1) ? in2... | 7.5071 |
module b16_loom_AC1 (
input clk,
input rst_n,
// in1, in2
input [15:0] in1,
input [15:0] in2,
// output
output [19:0] out
);
wire [3:0] psum;
assign psum = in1[0] & in2[0]
+ in1[1] & in2[1]
+ in1[2] & in2[2]
+ in1[3] & in2[3]
+ in... | 6.855877 |
module b16_loom_AC2 (
input clk,
input rst_n,
// in1, in2
input [19:0] in1,
input [31:0] in2,
input sign,
input sel,
// output
output [31:0] out
);
wire [19:0] sign_in1;
assign sign_in1 = (sign == 1'b1) ? ~in1 : in1;
wire [31:0] sel_in2;
assign sel_in2 = (sel == 1'b1) ? in2... | 7.5071 |
module b16_SIP (
input clk,
input rst_n,
//in1, in2,
input [15:0] in1_0,
input [15:0] in1_1,
input [15:0] in1_2,
input [15:0] in1_3,
input [15:0] in1_4,
input [15:0] in1_5,
input [15:0] in1_6,
input [15:0] in1_7,
input [15:0] in1_8,
input [15:0] in1_9,
input [15:... | 6.908117 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b1_comb/b1_comb.opt (
a_pad,
b_pad,
d_pad,
e_pad,
f_pad,
g_pad
);
input a_pad, b_pad, d_pad;
output e_pad, f_pad, g_pad;
assign e_pad = a_pad ^ b_pad;
assign f_pad = a_pad ? (b_pad & ~d_pad) : ... | 6.939825 |
module b1_demux_1_3_case (
input din,
input [1:0] sel,
output reg dout0,
output reg dout1,
output reg dout2
);
always @(*)
case (sel)
2'b00: begin
dout0 = din;
dout1 = 0;
dout2 = 0;
end
2'b01: begin
dout0 = 0;
... | 8.151336 |
module b1_demux_1_3_case_v2 (
input din,
input [1:0] sel,
output reg dout0,
output reg dout1,
output reg dout2
);
always @(*) begin
dout0 = 1'b0;
dout1 = 1'b0;
dout2 = 1'b0;
case (sel)
2'b00: dout0 = din;
2'b01: dout1 = din;
2'b10... | 8.151336 |
module b1_demux_1_3_shift (
input din,
input [1:0] sel,
output dout0,
output dout1,
output dout2
);
assign {dout2, dout1, dout0} = din << sel;
endmodule
| 8.151336 |
module b200_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
//... | 7.230123 |
module b200_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 =... | 7.230123 |
module b205_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
... | 7.108747 |
module b205_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 =... | 7.108747 |
module b222 (
BCLK,
WR_MRAM,
VADR,
MMU_DIN,
rd_addr,
rd_result
);
input BCLK;
input WR_MRAM;
input [31:0] VADR;
input [23:0] MMU_DIN;
input [1:0] rd_addr;
output [35:0] rd_result;
reg [31:0] VADR_R;
reg [35:0] MMU_TAGS[0:3];
always @(posedge BCLK) VADR_R <= VADR;
always @... | 6.879602 |
module b2bcd_99 (
input [19:0] din,
output [19:0] dout
);
assign dout = din + (din / 8'd10) * 8'd6;
endmodule
| 6.795267 |
module b2bcd_99_test;
reg [19:0] din;
wire [19:0] dout;
b2bcd_99 dut (
.din (din),
.dout(dout)
);
initial begin
din = 20'd23;
#500000 $stop;
end
endmodule
| 6.839372 |
module b2d #(
parameter dw = 16, // input data width in bits
parameter sim_mode = 0
) (
input clk,
input [dw-1:0] bdata,
input load,
output [3:0] nibble,
output nstrobe
);
// Hold the data in a shift register
reg [dw-1:0] sr;
wire shiftin;
always @(posedge clk) sr <= load ? bdata :... | 7.425536 |
module b2decimal #(
parameter dw = 16
) (
input clk,
input [dw-1:0] bdata,
input load,
output [3:0] nibble,
output nstrobe
);
// Hold the data in a shift register
reg [dw-1:0] sr;
wire shiftin;
always @(posedge clk) sr <= load ? bdata : {sr[dw-2:0], shiftin};
wire shiftout = sr[dw-1];... | 6.854576 |
module b2d_ssd (
BIN,
SSD
);
input [15:0] BIN;
output reg [0:6] SSD;
always begin
case (BIN)
0: SSD = 7'b0000001;
1: SSD = 7'b1001111;
2: SSD = 7'b0010010;
3: SSD = 7'b0000110;
4: SSD = 7'b1001100;
5: SSD = 7'b0100100;
6: SSD = 7'b0100000;
7: SSD = 7'b0... | 6.814137 |
module b2Yb (
input iClk,
input iReset_n,
input [7:0] iB,
output [4:0] oYB
);
//====================REGISTERS==================
reg [ 7:0] s1_iB;
//===============================================
//======================WIRES====================
wire [20:0] yb;
// Pre-Calculate
/... | 6.620707 |
module b2_demux_1_4_univ #(
parameter MODE = "CASE"
) (
input [1:0] din,
input [1:0] sel,
output [1:0] dout0,
output [1:0] dout1,
output [1:0] dout2,
output [1:0] dout3
);
// generate & parameter can be used to select one of module implementations
generate
// the 1st implementation... | 6.829371 |
module b2_mux_3_1_case_full (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All possible values of input signals should be provided
// or an inferred latch will be generated!
always @(*) begin
case (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b10: y... | 6.712042 |
module b2_mux_3_1_case (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All the possible input-output pairs should be provided!
// The first way to provide all possible values of input signals
// is to add the default value out of the 'case' block
always @(*) beg... | 6.712042 |
module b2_mux_3_1_case_default (
input [1:0] d0,
d1,
d2,
input [1:0] sel,
output reg [1:0] y
);
// All the possible input-output pairs should be provided!
// The second way to provide all possible values of input signals
// is to use the 'default' inside the 'case' block
always @(*... | 6.712042 |
module b2_mux_3_1_casez #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] d0,
d1,
d2,
input [ 1:0] sel,
output reg [WIDTH-1:0] y
);
always @(*)
casez (sel)
2'b00: y = d0;
2'b01: y = d1;
2'b1?: y = d2;
endcase
endmodule
| 6.712042 |
module b2_mux_4_1_case_one_hot (
input [1:0] d0,
input [1:0] d1,
input [1:0] d2,
input [1:0] d3,
input [3:0] sel,
output reg [1:0] y
);
always @(*)
case (sel)
4'b0001: y = d0;
4'b0010: y = d1;
4'b0100: y = d2;
4'b1000: y = d3;
default... | 7.2134 |
module b2_mux_4_1_casez_priority (
input [1:0] d0,
input [1:0] d1,
input [1:0] d2,
input [1:0] d3,
input [3:0] sel,
output reg [1:0] y
);
always @(*)
casez (sel)
4'b0001: y = d0;
4'b001?: y = d1;
4'b01??: y = d2;
4'b1???: y = d3;
defau... | 7.2134 |
module b8_SIP (
input clk,
input rst_n,
//in1, in2,
input [7:0] in1_0,
input [7:0] in1_1,
input [7:0] in1_2,
input [7:0] in1_3,
input [7:0] in1_4,
input [7:0] in1_5,
input [7:0] in1_6,
input [7:0] in1_7,
input [7:0] in1_8,
input [7:0] in1_9,
input [7:0] in1_10,
... | 6.663066 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/b9_comb/b9_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f0_pad,
f_pad,
g0_pad,
g_pad,
h0_pad,
h_pad,
i0_pad,
i_p... | 6.939825 |
module cntrl_jump_upto (
flagSet,
prevFlags,
jumpType,
jumpIndex,
jumpPredTk,
jumpTbufMiss,
indirMismatch,
jumpMisPred,
jumpTaken,
flagOut,
flagOutN,
flags0,
flags1,
flags2,
flags3,
flags4,
flags5,
flags6,
flags7,
flags8,
flags9
);
p... | 7.48293 |
module cntrl_get_shortIP (
baseIP,
srcIPOff,
jupd0_IP,
jupd0_en,
jupd1_IP,
jupd1_en
);
input [19:0] baseIP;
input [8:0] srcIPOff;
output [19:0] jupd0_IP;
input jupd0_en;
output [19:0] jupd1_IP;
input jupd1_en;
adder2o #(20 - 4) last_add (
baseIP[19:4],
{11'b0, srcIPOff... | 6.637794 |
module babbage_diff (
input clk,
rst_n,
input start,
input [5:0] i, //6 bit value f "n"
output [17:0] ans,
output reg ready,
done_tick
);
//babbage function values(3-order polynomial)
localparam f0 = 1, g1 = 5, h2 = 10, c = 6;
//FSM state declarations
localparam [1:0] idle = 2'd0, ... | 6.843682 |
module babbage_diff_TB;
// Inputs
reg clk;
reg rst_n;
reg start;
reg [5:0] i;
integer index;
// Outputs
wire [17:0] ans;
wire ready;
wire done_tick;
// Instantiate the Unit Under Test (UUT)
babbage_diff uut (
.clk(clk),
.rst_n(rst_n),
.start(start),
.i(i),
.ans(ans... | 7.340608 |
module babbage_diff_TEST (
input clk,
rst_n,
input sw0,
sw1, //active low
output [7:0] seg_out,
output [5:0] sel_out
);
//FSM state declarations
localparam [1:0] idle = 2'd0, babbage = 2'd1, bin2bcd = 2'd2;
reg [1:0] state_reg, state_nxt;
reg [5:0] mod64_reg, mod64_nxt;
reg start_babb... | 7.340608 |
module babbage_engine_f (
input wire clk,
reset,
input wire start,
output reg done_tick,
input wire [ 5:0] in,
output wire [19:0] out // length just to match the _h file
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, calc = 2'b01, done = 2'b... | 7.453324 |
module babbage_engine_h (
input wire clk,
reset,
input wire start,
output reg done_tick,
input wire [ 5:0] in,
output wire [19:0] out
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, calc = 2'b01, done = 2'b10;
// constant declarations
localparam... | 7.453324 |
module babbage_engine_top (
input wire clk,
input wire btnD, // reset
input wire btnC, // start
input wire [5:0] sw,
input wire sw_sel,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire reset;
wire start;
reg calc_start, bc... | 7.453324 |
module line_ram (
input clk,
input [4:0] addr,
output reg [31:0] dout,
input [31:0] din,
input we,
input re
);
reg [31:0] ram[0:31];
initial $readmemh("lines.hex", ram);
always @(posedge clk) begin
if (we) ram[addr] <= din;
else if (re) dout <= ram[addr];
end
endmodule
| 7.304478 |
module GG (
input p0,
p1,
p2,
g0,
g1,
g2,
c0,
output N
);
wire w, f, m;
AO2 #(19, 17) G1 (
w,
p2,
g1,
g2
);
AO2 #(19, 17) G2 (
f,
p0,
c0,
g0
);
AND2 #(13, 17) G3 (
m,
p2,
p1
);
AO2 #(19, 17) G4 (
N,
... | 6.747396 |
module backAnimations (
animationClOCK,
BACK1X,
BACK1Y,
BACK2X,
BACK2Y,
score,
BACK1SKIPX,
BACK2SKIPX
);
input animationClOCK;
output [9:0] BACK1X;
output [9:0] BACK1Y;
output [9:0] BACK2X;
output [9:0] BACK2Y;
output [9:0] BACK1SKIPX;
output [9:0] BACK2SKIPX;
input [9:0... | 7.261035 |
module BackGroundDelegate #(
parameter ratio = 1,
dx = -6'd20
) (
input wire moveClk,
input wire rst,
input wire [8:0] GroundY,
input wire [9:0] vgaX,
input wire [9:0] vgaY,
input wire [1:0] gameState,
output wire inGrey,
output wire inWhite
);
localparam groundDisplayOffset =... | 7.613144 |
module background_effects (
pixel_color,
x,
y,
enable_effect,
clk,
slow_clk
);
output [3:0] pixel_color;
input [9:0] x;
input [8:0] y;
input [2:0] enable_effect;
input clk, slow_clk;
reg [2:0] pixel_color;
wire [4:0] h_count_sin;
reg [5:0] h_count_increment;
reg [5:0] incr... | 6.584543 |
module background_engine (
input wire clk,
input wire video_on,
input wire [3:0] x_offset,
input wire [9:0] x,
y,
input wire [15:0] ram_data,
output reg [15:0] ram_addr,
output wire pixel_on,
output wire [11:0] color
);
reg [13:0] rom_addr;
reg [6:0] rom_x, rom_y;
wire [11:0] r... | 7.262815 |
module backlight (
input i_Clk,
input i_Touch,
output o_Light
);
localparam STATE_DISPLAY_OFF = 1'd0;
localparam STATE_DISPLAY_ON = 1'd1;
reg [33:0] r_Counter = 34'd0;
reg r_CurrentState = STATE_DISPLAY_ON;
reg r_NextState;
/* State transitions */
always @(posedge i_Clk) begin
r_Curre... | 6.595377 |
module Backpack_tb ();
reg clk, res;
wire [15:0] max_value;
wire [ 7:0] cathodes;
wire [ 3:0] ano;
initial begin
clk <= 0;
res <= 1;
#10 res <= 0;
end
always begin //时钟信号
#5 clk <= ~clk;
end
top mytop (
clk,
res,
ano,
cathodes
);
/*iverilog */
initial... | 6.51317 |
module frontReq_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 44 - 13 + 64 - 27;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr... | 8.003613 |
module front_strip_ECC (
dataIn,
dataOut,
par
);
input [39:1] dataIn;
output [31:0] dataOut;
output par;
assign dataOut = {dataIn[38:33], dataIn[31:17], dataIn[15:9], dataIn[7:5], dataIn[3]};
assign par = dataIn[39];
endmodule
| 7.488015 |
module backscatterv1 (
clk,
rst_n,
clkout1,
clkout2,
clkout3,
clkout4,
clkp,
key0,
led0
);
input clk, rst_n; //输入信号，其中clk连接到FPGA的C1脚，频率为12MHz
output clkout1,clkout2,clkout3,clkout4,clkp; //输出信号，可以连接到LED观察分频的时钟
input key0;
output led0;
wire [1:0] clk0; // 12 M
wire [... | 6.998296 |
module BACKUP_APF (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [14:0] address_a;
input [14:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
... | 6.845669 |
module BACKUP_APF (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [14:0] address_a;
input [14:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
i... | 6.845669 |
module BackwardMaccum #(
parameter NN = 7
, parameter NC = 11
, parameter WV = 5
, parameter BURST = "yes"
) (
input iValid_AM_Weight
, output oReady_AM_Weight
, input [ NC*NN*WV-1:0] iData_AM_Weight
, input ... | 7.688029 |
module backwardskidbuffer #(
parameter L = 8,
parameter OPTREG = 0
) (
input clk,
input rst,
output reg ready_f,
input valid_f,
input [L-1:0] data_f,
input ready_b,
output reg valid_b,
output reg [L-1:0] data_b
);
reg state;
wire ready;
reg pre_valid;
reg [L-1:0] data_... | 6.899775 |
module Backward_Registered #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
start,
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input start;
input src_vaild;
input [WIDTH-1:0] src_data_in;
input ... | 8.285036 |
module Backward_Registered_v1 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
idle, //原本start改为idle
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input idle;
input src_vaild;
input [WIDTH-1:0] src... | 8.285036 |
module Backward_Registered_v3 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
idle, //原本start改为idle
src_vaild,
src_data_in,
src_ready,
dst_ready,
dst_vaild,
dst_data_out
);
input clk;
input s_rst;
input idle;
input src_vaild;
input [WIDTH-1:0] src... | 8.285036 |
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