code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axi_fifo_51 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter TUSER_WIDTH = 8,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
input [TUSER_WIDTH-1:0] s_axis_t... | 7.573804 |
module axi_fifo_64 #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
input [8:0] delay,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
input m... | 8.202893 |
module axi_fifo_bram #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output reg [WIDTH-1:0] o_tdata = 'd0,
output reg o_tvalid = 1'b0,
input o_tready,
output reg [15:0] space,
outp... | 8.008711 |
module axi_fifo_cascade #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output [15:0] space,
output [15:0] occupied
);
... | 7.133169 |
module axi_fifo_fake #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output [17:0] space,
output [17:0] occupied
);
... | 6.535135 |
module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
// It extracts and indicates the header (first word) of a packet in the FIFO. The header and flag are pipelined
// for timing closure.
//
module axi_fifo_header
#(
parameter WIDTH=64 // Bit width of FIFO word.
... | 8.147278 |
module axi_fifo_legacy #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output reg [15:0] space,
output reg [15:0] occup... | 7.812887 |
module uses the SRLC32E primitive explicitly and as such
// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
//
module axi_fifo_short
#(parameter WIDTH=32)
(
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_trea... | 7.023134 |
module uses the SRLC32E primitive explicitly and as such
// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
//
module axi_fifo_short_al
#(parameter WIDTH=32)
(
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_t... | 7.023134 |
module axi_fir_filter_dec #(
parameter WIDTH = 24,
parameter COEFF_WIDTH = 18,
parameter NUM_COEFFS = 47,
parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = {
{1'b0, {(COEFF_WIDTH - 1) {1'b1}}}, {(COEFF_WIDTH * (NUM_COEFFS - 1)) {1'b0}}
},
parameter BLANK_OUTPUT = 0
) (
input clk,
... | 6.533817 |
module
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module axi_generator #(
parameter C_RATE = 125000000,
parameter C_PIXELS = 12
)(
// AXI Interface
input axi_clock,
input axi_reset,
output reg [31:0] ax... | 8.13663 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_hndshk_split (
ready_src,
valid_dst,
aclk,
aresetn,
valid_src,
ready_dst
);
parameter N_OUTPUTS = 2;
input aclk;
input aresetn;
input valid_src;
output logic ready_src;
output logic [N_OUTPUTS-1:0] valid_dst;
input [N_OUTPUTS-1:0] ready_dst;
logic [N_OUTPUTS-1:0... | 6.624263 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module axi_interconnect_v1_7_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
... | 6.850312 |
module axi_interconnect_v1_7_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
/////////////////... | 6.850312 |
module axi_interconnect_v1_7_carry #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for ... | 6.850312 |
module axi_interconnect_v1_7_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating param... | 6.850312 |
module axi_interconnect_v1_7_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating pa... | 6.850312 |
module axi_interconnect_v1_7_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating par... | 6.850312 |
module axi_interconnect_v1_7_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parame... | 6.850312 |
module axi_interconnect_v1_7_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire ... | 6.850312 |
module axi_interconnect_v1_7_comparator_mask #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input ... | 6.850312 |
module axi_interconnect_v1_7_comparator_mask_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (... | 6.850312 |
module axi_interconnect_v1_7_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input w... | 6.850312 |
module axi_interconnect_v1_7_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
... | 6.850312 |
module axi_interconnect_v1_7_comparator_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
... | 6.850312 |
module axi_interconnect_v1_7_mux #(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
) (
input wire [ ... | 6.850312 |
module axi_interconnect_v1_7_ndeep_srl #(
parameter C_FAMILY = "none", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire... | 6.850312 |
module axi_interconnect_v1_7_nto1_mux #(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL)... | 6.850312 |
module axi_interconnect_v1_7_splitter #(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
) (
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Maste... | 6.850312 |
module axi_interconnect_v1_7_wdata_mux #(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // ... | 6.850312 |
module axi_interconnect_v1_7_wdata_router #(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, ... | 6.850312 |
module to control
the input and output data flow from axi interface.
NOTICE: if you want to migrate the decompressor to other platform or other interface. Only the decompressor
module is needed.
********************************************/
`timescale 1ns/1ps
module axi_... | 7.851287 |
module axi_istr_bfm (
input wire clock_i, // Clock Input
input wire reset_i, // Reset Input
// ===============================================================================
// AXI 4 Stream Transmit Channel
output reg [3:0] tid_o,
output wire tvalid_o, // Receive Data channel valid
inp... | 7.065561 |
module axi_join #(
parameter INPUTS = 2
) (
input [INPUTS-1:0] i_tlast,
input [INPUTS-1:0] i_tvalid,
output [INPUTS-1:0] i_tready,
output o_tlast,
output o_tvalid,
input o_tready
);
wire all_here = &i_tvalid;
assign o_tvalid = all_here;
assign o_tlast = |i_tlast;
assign i_tready = ... | 7.584888 |
module axi_jtaguart (
input wire clock
, input wire reset
, output wire tx_ready
, input wire tx_valid
, input wire [7:0] tx_data
, input wire rx_ready
, output wire rx_valid
, output wire [7:0] rx_data
);
wire jtaguart_idle_o;
alt_jtag_atlantic jtag_... | 7.190045 |
module axi_lite_wrapper #(
// Users to add parameters here
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_LENGTH_WIDTH = 14,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI... | 6.785077 |
module axi_lite_generic_reg #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
) (
// Users to ... | 6.986845 |
module AXI_LITE_master_IP_v1_0 #(
// Users to add parameters here
parameter REG_DATA_VALUE_0 = 32'h00000000,
parameter REG_DATA_VALUE_1 = 32'h00000000,
parameter REG_DATA_VALUE_2 = 32'h00000000,
parameter REG_DATA_VALUE_3 = 32'h00000000,
// User parameters ends
// Do not modify the parameter... | 6.642195 |
module axi_lite_master #(
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
) (
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] ... | 6.775936 |
module axi_lite_slave_int #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 4
) (
// Users to add parameters here
output [ C_S_AXI_DATA_WIDTH-1:0] WDATA_O,
input [ C_S_AXI_DATA_WIDTH-1:0] RDATA_I,
output WENA_O,
output ... | 7.923453 |
module AXI_Lite_test (
ACLK,
ARESETN
);
input ACLK;
input ARESETN;
wire ACLK_1;
wire ARESETN_1;
wire [31:0] axi_lite_master_0_M_AXI_ARADDR;
wire axi_lite_master_0_M_AXI_ARREADY;
wire axi_lite_master_0_M_AXI_ARVALID;
wire [31:0] axi_lite_master_0_M_AXI_AWADDR;
wire axi_lite_master_0_M_AXI_AWRE... | 6.506887 |
module AXI_Lite_test_axi_lite_master_0_0 (
WCOMPLETE,
RCOMPLETE,
M_AXI_ACLK,
M_AXI_ARESETN,
M_AXI_AWADDR,
M_AXI_AWPROT,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BRESP,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARADD... | 6.506887 |
module AXI_Lite_test_axi_lite_slave_0_0 (
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AX... | 6.506887 |
module AXI_Lite_test_wrapper (
ACLK,
ARESETN
);
input ACLK;
input ARESETN;
wire ACLK;
wire ARESETN;
AXI_Lite_test AXI_Lite_test_i (
.ACLK(ACLK),
.ARESETN(ARESETN)
);
endmodule
| 6.506887 |
module axi_lite_write ( /*AUTOARG*/
// Outputs
wready,
bvalid,
bresp,
reg_data_addr,
reg_data_write,
reg_data,
// Inputs
clk,
reset,
awvalid,
awready,
wvalid,
wdata,
bready
);
parameter C_ADDR_WIDTH = 10;
parameter C_DATA_WIDTH = 32;
input clk;
input... | 6.724579 |
module axi_logpwr (
input clk,
input reset,
input [31:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [15:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
// Signals
reg ready;
reg valid_1;
wire valid_12;
wire last_12;
wire [31:0] rn... | 6.533255 |
module axi_loopback #(
parameter WIDTH = 64
) (
input clk,
input reset,
// Input AXIS
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
// Output AXIS
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDT... | 7.836661 |
module axi_master32_stub (
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RRE... | 7.901287 |
module axi_master_generic ( /*AUTOARG*/
// Outputs
awid,
awadr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
wid,
wrdata,
wstrb,
wlast,
wvalid,
bid,
bresp,
bvalid,
arid,
araddr,
arlen,
arsize,
arlock,
arcache,
... | 7.371913 |
module axi_master_ic_dec (
M0_AADDR,
M1_AADDR,
M2_AADDR,
M0_AID,
M1_AID,
M2_AID,
M0_ASLV,
M1_ASLV,
M2_ASLV,
M0_AIDOK,
M1_AIDOK,
M2_AIDOK
);
input [32-1:0] M0_AADDR;
input [32-1:0] M1_AADDR;
input [32-1:0] M2_AADDR;
input [4-1:0] M0_AID;
input [4-1:0] M1_AID;
... | 6.749778 |
module axi_master_read_stub (
output M2S_AXI_ACLK,
//Read M2S_AXI_transation
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M... | 8.03225 |
module axi_master_stub (
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREAD... | 7.836666 |
module axi_master_write_stub (
output M2S_AXI_ACLK,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_A... | 7.00851 |
module axi_mcb_simple_fifo #(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
) (
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable ... | 7.265372 |
module mig_7series_v4_2_axi_mc_simple_fifo #(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
) (
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FI... | 7.091312 |
module axi_mem_wrapper #(
parameter ID_WIDTH = 0,
parameter MEM_SIZE = 0,
parameter mem_clear = 0,
parameter INIT_FILE = ""
) (
input wire clk,
input wire rst_n,
input wire [ID_WIDTH-1:0] i_awid,
input wire [ 31:0] i_awaddr,
input wire [ 7:0] i_awlen,
input ... | 6.819355 |
module axi_mmu_v2_1_9_addr_decoder #(
parameter C_FAMILY = "rtl",
parameter integer C_NUM_RANGES = 1, // Number of address ranges [1..256]
parameter integer C_NUM_RANGES_LOG = 1, // Width of matching range index (min 1)
parameter integer C_ADDR_WIDTH = 32, // Width of address operand [2:64]
param... | 7.25219 |
module axi_mm_systemc ( /*AUTOARG*/
// Outputs
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awprot,
m_axi_awvalid,
m_axi_awlock,
m_axi_awcache,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
... | 6.956547 |
module axi_modbus_v1_0 #(
// Users to add parameters here
parameter INTR_CLOCK = 5,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S0_AXI
parameter integer C_S0_AXI_DATA_WIDTH = 32,
parameter integer C_S0_AXI_ADDR_WIDTH = 7... | 7.328772 |
module axi_multiplexer #(
parameter DATA_WIDTH = 64,
parameter N_IN = 16,
parameter SEL_WIDTH = $clog2(N_IN)
) (
IN_DATA,
OUT_DATA,
SEL
);
//parameter DATA_WIDTH = 64;
//parameter N_IN = 16;
//parameter SEL_WIDTH = $clog2(N_IN);
input wire [(N_IN * DATA_WIDTH) - 1:0] IN_DATA;
ou... | 8.058716 |
module axi_mux #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter PRE_FIFO_SIZE = 0,
parameter POST_FIFO_SIZE = 0,
parameter SIZE = 4
) (
input clk,
input reset,
input clear,
input [(WIDTH*SIZE)-1:0] i_tdata,
input [SIZE-1:0] i_tlast,
input [SIZE-1:0] i_tvalid,
output... | 6.885529 |
module axi_mux4 #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
... | 8.171347 |
module axi_mux8 #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
... | 6.922538 |
module axi_mux_select #(
parameter WIDTH = 32,
parameter PRE_FIFO_SIZE = 0,
parameter POST_FIFO_SIZE = 0,
parameter SWITCH_ON_LAST = 0, // Wait until tlast is asserted before updating
parameter SIZE = 4
) (
input clk,
input reset,
input clear,
input [$clog2(SIZE)-1:0] select,
in... | 7.675637 |
module axi_ostr_bfm (
input wire clock_i, // Clock Input
input wire reset_i, // Reset Input
// ===============================================================================
// AXI 4 Stream Transmit Channel
output reg [3:0] tid_o,
input wire tvalid_i, // Transmit data channel valid
out... | 7.458363 |
module axi_packet_mux #(
parameter NUM_INPUTS = 1,
parameter MUX_PRE_FIFO_SIZE = 0, // Use 0 (most efficient) unless there is need to compensate for unbalanced input path latencies
parameter MUX_POST_FIFO_SIZE = 0, // Generally leave at 0, similar effect as FIFO_SIZE
parameter FIFO_SIZE = 5 // Size o... | 6.789618 |
module rp_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
alw... | 6.765574 |
module rp_pcie_bram_7vx_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_S... | 6.590647 |
module rp_pcie_bram_7vx_cpl #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_... | 6.590647 |
module rp_pcie_bram_7vx_rep_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETI... | 6.590647 |
module rp_pcie_bram_7vx_rep #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_... | 6.590647 |
module rp_pcie_bram_7vx_req #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_... | 6.590647 |
module axi_pcie_mm_s_v1_04_a_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating param... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating pa... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating par... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parame... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire ... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input w... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
... | 6.771003 |
module axi_pcie_mm_s_v1_04_a_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
//... | 6.771003 |
module axi_pcie_v1_08_a_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter ... | 7.560006 |
module axi_pcie_v1_08_a_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating paramet... | 7.560006 |
module axi_pcie_v1_08_a_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating paramete... | 7.560006 |
module axi_pcie_v1_08_a_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter c... | 7.560006 |
module axi_pcie_v1_08_a_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DA... | 7.560006 |
module axi_pcie_v1_08_a_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [... | 7.560006 |
module axi_pcie_v1_08_a_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
i... | 7.560006 |
module axi_pcie_v1_08_a_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Rang... | 7.560006 |
module axi_pcie_v1_08_a_GTX_DRP_CHANALIGN_FIX_3752_V6 #(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
) (
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [ 7:0] daddr,
output reg [ 3:... | 7.560006 |
module for Spartan-6 PCIe Block
// The BRAM A port is the write port.
// The BRAM B port is the read port.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_pcie_v1_08_a_pcie_bram_s6 #(
parameter DOB_REG = 0, // 1 use the outpu... | 7.510734 |
module for Spartan-6 PCIe Block
//
// Given the selected core configuration, calculate the number of
// BRAMs and pipeline stages and instantiate the BRAMS.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_pcie_v1_08_a_pcie_bram... | 7.510734 |
module axi_pcie_v1_08_a_pcie_reset_delay_v6 #(
parameter PL_FAST_TRAIN = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter TCQ = 1
) (
input wire ref_clk,
input wire sys_reset_n,
output delayed_sys_reset_n
);
localparam TBIT = (PL_FA... | 7.560006 |
module axi_pcie_v1_08_a_pselect_f #(
parameter C_AB = 9,
parameter C_AW = 32,
parameter [0:C_AW - 1] C_BAR = 'bz,
parameter C_FAMILY = "nofamily"
) (
input [0:C_AW-1] A,
input AValid,
output CS
);
// Local Paramater... | 7.560006 |
module_profile.v
// Version : v5.0
// Description : register module having all the registers of axi performance
// monitor read and write logic. Address decoding is also
// implemented in this module based on which the corresponding
// read and write enables being gen... | 7.065413 |
module axi_perf_mon_v5_0_11_sync_fifo #(
parameter WIDTH = 8, // The width of the FIFO data
parameter DEPTH_LOG2 = 3 // Specify power-of-2 FIFO depth
) (
input rst_n,
input clk,
input wren,
input rden,
input [WI... | 6.932985 |
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