code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
modules below for axi connections
module axidelay #(
parameter MAX_DELAY = 3
) (
// Master interface. Connect to a slave interface
output reg m_valid,
input m_ready,
// Slave interface. Connect to a master interface
input s_valid,
output reg s_ready,
input clk,
input rst
);
generate
if (MAX_DELAY == 0) begin
always @* begin
s_ready = m_ready;
m_valid = s_valid;
end
end else begin
reg [$clog2(MAX_DELAY):0] counter;
always @(posedge clk, posedge rst) begin
if (rst) begin
counter <= 0;
end else begin
if (counter == 0 && m_valid && m_ready) begin
counter <= ($urandom % MAX_DELAY);
end
if (counter) counter <= counter - 1;
end
end
always @* begin
s_ready = 1'b0;
m_valid = 1'b0;
if (counter == 0) begin
s_ready = m_ready;
m_valid = s_valid;
end
end
end
endgenerate
endmodule
| 7.587638 |
module axidelayRead #(
parameter MAX_DELAY = 3
) (
// Connect directly to the same named axi read wires in the master interface
output m_rvalid,
input m_rready,
// Connect directly to the same named axi read wires in the slave interface
input s_rvalid,
output s_rready,
input clk,
input rst
);
axidelay #(
.MAX_DELAY(MAX_DELAY)
) Read (
.s_valid(s_rvalid),
.s_ready(s_rready),
.m_valid(m_rvalid),
.m_ready(m_rready),
.clk(clk),
.rst(rst)
);
endmodule
| 8.332032 |
module axidelayWrite #(
parameter MAX_DELAY = 3
) (
// Connect directly to the same named axi write wires in the master interface
input m_wvalid,
output m_wready,
// Connect directly to the same named axi write wires in the slave interface
output s_wvalid,
input s_wready,
input clk,
input rst
);
axidelay #(
.MAX_DELAY(MAX_DELAY)
) Write (
.s_valid(m_wvalid),
.s_ready(m_wready),
.m_valid(s_wvalid),
.m_ready(s_wready),
.clk(clk),
.rst(rst)
);
endmodule
| 8.202073 |
module axil2iob #(
parameter AXIL_ADDR_W = 32, // Width of address bus in bits
parameter AXIL_DATA_W = 32 // Width of data bus in bits
) (
// AXI-4 lite slave interface
`include "axil_s_port.vh"
// Native master interface
output valid,
output [ AXIL_ADDR_W-1:0] addr,
output [ AXIL_DATA_W-1:0] wdata,
output [AXIL_DATA_W/8-1:0] wstrb,
input [ AXIL_DATA_W-1:0] rdata,
input ready,
`include "iob_gen_if.vh"
);
reg awvalid_ack;
reg arvalid_ack;
assign axil_rdata = rdata;
// AXI IDs
assign axil_bid = `AXI_ID_W'd0;
assign axil_rid = `AXI_ID_W'd0;
// Response is always OK
assign axil_bresp = `AXI_RESP_W'd0;
assign axil_rresp = `AXI_RESP_W'd0;
assign valid = (axil_wvalid | axil_arvalid) & ~ready;
assign addr = axil_wvalid ? axil_awaddr : axil_araddr;
assign wstrb = axil_wvalid ? axil_wstrb : {(AXIL_DATA_W / 8) {1'b0}};
assign wdata = axil_wdata;
assign axil_awready = awvalid_ack & ready;
assign axil_wready = awvalid_ack & ready;
assign axil_arready = arvalid_ack & ready;
assign axil_rvalid = arvalid_ack & ready;
reg axil_bvalid_int;
assign axil_bvalid = axil_bvalid_int;
always @(posedge clk, posedge rst) begin
if (rst) begin
axil_bvalid_int <= 1'b0;
end else begin
axil_bvalid_int <= axil_wready;
end
end
always @(posedge clk, posedge rst) begin
if (rst) begin
awvalid_ack <= 1'b0;
end else if (axil_awvalid & ~awvalid_ack) begin
awvalid_ack <= 1'b1;
end else if (ready) begin
awvalid_ack <= 1'b0;
end
end
always @(posedge clk, posedge rst) begin
if (rst) begin
arvalid_ack <= 1'b0;
end else if (axil_arvalid & ~arvalid_ack) begin
arvalid_ack <= 1'b1;
end else if (ready) begin
arvalid_ack <= 1'b0;
end
end
endmodule
| 8.99491 |
module axil2native_adapter #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8)
) (
input clk,
input rst,
// AXI4-lite slave interface
input [ADDR_WIDTH-1:0] s_axil_awaddr,
input s_axil_awvalid,
output s_axil_awready,
input [DATA_WIDTH-1:0] s_axil_wdata,
input [STRB_WIDTH-1:0] s_axil_wstrb,
input s_axil_wvalid,
output s_axil_wready,
output [1:0] s_axil_bresp,
output s_axil_bvalid,
input s_axil_bready,
input [ADDR_WIDTH-1:0] s_axil_araddr,
input s_axil_arvalid,
output s_axil_arready,
output [DATA_WIDTH-1:0] s_axil_rdata,
output [ 1:0] s_axil_rresp,
output s_axil_rvalid,
input s_axil_rready,
// Native interface
output native_valid,
input native_ready,
output [ADDR_WIDTH-1:0] native_addr,
output [DATA_WIDTH-1:0] native_wdata,
output [STRB_WIDTH-1:0] native_wstrb,
input [DATA_WIDTH-1:0] native_rdata
);
reg wr_en;
reg wr_en_reg;
reg s_axil_wready_reg;
reg s_axil_arready_reg;
reg s_axil_rvalid_reg;
reg native_valid_reg;
reg [ADDR_WIDTH-1:0] native_addr_reg;
reg s_axil_wready_next;
reg s_axil_arready_next;
reg [DATA_WIDTH-1:0] s_axil_rdata_next;
reg s_axil_rvalid_next;
assign s_axil_awready = s_axil_wready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = 2'b00;
assign s_axil_bvalid = native_ready;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = native_rdata;
assign s_axil_rresp = 2'b00;
assign s_axil_rvalid = native_ready;
assign native_valid = native_valid_reg;
assign native_addr = native_addr_reg;
assign native_wdata = s_axil_wdata;
assign native_wstrb = s_axil_wstrb;
//WRITE
always @* begin
wr_en = wr_en_reg && !native_ready;
s_axil_wready_next = 1'b0;
if (rst) begin
wr_en = 1'b0;
end
else if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!native_ready)) begin
s_axil_wready_next = 1'b1;
wr_en = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_wready_reg <= 1'b0;
wr_en_reg <= 1'b0;
end else begin
s_axil_wready_reg <= s_axil_wready_next;
wr_en_reg <= wr_en;
end
end
//READ
always @* begin
s_axil_arready_next = 1'b0;
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready && !native_ready;
if (rst) begin
s_axil_rvalid_next = 1'b0;
end
else if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && !native_ready && !s_axil_wvalid && !s_axil_awvalid) begin
s_axil_arready_next = 1'b1;
s_axil_rvalid_next = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_arready_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
end else begin
s_axil_arready_reg <= s_axil_arready_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
end
end // always @ (posedge clk)
//ADDRESS/VALID MUX
always @* begin
native_addr_reg <= {ADDR_WIDTH{1'b0}};
native_valid_reg <= 1'b0;
if (wr_en) begin
native_addr_reg <= s_axil_awaddr;
native_valid_reg <= s_axil_wvalid;
end else begin
native_valid_reg <= s_axil_rvalid_reg | s_axil_arvalid;
native_addr_reg <= s_axil_araddr;
end
end // always @ (posedge clk)
endmodule
| 8.503186 |
module toggle_detect #(
parameter integer data_width = 8
) (
output reg [data_width-1:0] data_out,
input [data_width-1:0] data_in,
input clk,
input reset
);
reg [data_width-1:0] data_in_1;
reg [data_width-1:0] data_in_2;
always @(posedge clk) begin
if (reset) begin
{data_in_2, data_in_1} <= 0;
end else begin
{data_in_2, data_in_1} <= {data_in_1, data_in};
end
end
wire [data_width-1:0] data_out_comb;
assign data_out_comb = data_in_2 ^ data_in_1;
always @(posedge clk) begin
if (reset) begin
data_out <= 0;
end else begin
data_out <= data_out_comb;
end
end
endmodule
| 6.992692 |
module axiLite_debug (
input M_AXI_ACLK,
input M_AXI_ARESETN,
input [31:0] M_AXI_AWADDR,
input M_AXI_AWVALID,
input M_AXI_AWREADY,
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WVALID,
input M_AXI_WREADY,
input [ 1:0] M_AXI_BRESP,
input M_AXI_BVALID,
input M_AXI_BREADY,
input [31:0] M_AXI_ARADDR,
input M_AXI_ARVALID,
input M_AXI_ARREADY,
input [31:0] M_AXI_RDATA,
input [ 1:0] M_AXI_RRESP,
input M_AXI_RVALID,
input M_AXI_RREADY
);
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_ARESETN;
(* dont_touch = "true", mark_debug = "true" *)reg [31:0] dbg_M_AXI_AWADDR;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_AWVALID;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_AWREADY;
(* dont_touch = "true", mark_debug = "true" *)reg [31:0] dbg_M_AXI_WDATA;
(* dont_touch = "true", mark_debug = "true" *)reg [ 3:0] dbg_M_AXI_WSTRB;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_WVALID;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_WREADY;
(* dont_touch = "true", mark_debug = "true" *)reg [ 1:0] dbg_M_AXI_BRESP;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_BVALID;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_BREADY;
(* dont_touch = "true", mark_debug = "true" *)reg [31:0] dbg_M_AXI_ARADDR;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_ARVALID;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_ARREADY;
(* dont_touch = "true", mark_debug = "true" *)reg [31:0] dbg_M_AXI_RDATA;
(* dont_touch = "true", mark_debug = "true" *)reg [ 1:0] dbg_M_AXI_RRESP;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_RVALID;
(* dont_touch = "true", mark_debug = "true" *)reg dbg_M_AXI_RREADY;
always @(posedge M_AXI_ACLK) begin
dbg_M_AXI_ARESETN <= M_AXI_ARESETN;
dbg_M_AXI_AWADDR <= M_AXI_AWADDR;
dbg_M_AXI_AWVALID <= M_AXI_AWVALID;
dbg_M_AXI_AWREADY <= M_AXI_AWREADY;
dbg_M_AXI_WDATA <= M_AXI_WDATA;
dbg_M_AXI_WSTRB <= M_AXI_WSTRB;
dbg_M_AXI_WVALID <= M_AXI_WVALID;
dbg_M_AXI_WREADY <= M_AXI_WREADY;
dbg_M_AXI_BRESP <= M_AXI_BRESP;
dbg_M_AXI_BVALID <= M_AXI_BVALID;
dbg_M_AXI_BREADY <= M_AXI_BREADY;
dbg_M_AXI_ARADDR <= M_AXI_ARADDR;
dbg_M_AXI_ARVALID <= M_AXI_ARVALID;
dbg_M_AXI_ARREADY <= M_AXI_ARREADY;
dbg_M_AXI_RDATA <= M_AXI_RDATA;
dbg_M_AXI_RRESP <= M_AXI_RRESP;
dbg_M_AXI_RVALID <= M_AXI_RVALID;
dbg_M_AXI_RREADY <= M_AXI_RREADY;
end
endmodule
| 6.645668 |
module axilite_dev #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg0;
// Instantiation of Axi Bus Interface S00_AXI
axilite_dev_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axilite_dev_S00_AXI_inst (
.reg0(reg0),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.885181 |
module axilite_mux (
input [ 15:0] w_strb_in,
input [127:0] w_data_in,
input ar_valid_in,
input ar_ready_in,
input [ 31:0] ar_addr_in,
input user_clk,
input [ 31:0] r_data_in,
output [127:0] r_data_out,
output [ 31:0] w_data_out
);
reg [3:0] rd_addr_nibble = 4'd0;
//- Extract out valid write data based on strobe
assign w_data_out = w_strb_in[0] ? w_data_in[31:0] :
w_strb_in[4] ? w_data_in[63:32] :
w_strb_in[8] ? w_data_in[95:64] :
w_data_in[127:96];
//- Latch onto the read address lowest nibble
always @(posedge user_clk) if (ar_valid_in & ar_ready_in) rd_addr_nibble <= ar_addr_in[3:0];
//- Place the read 32-bit data into the appropriate 128-bit r_data_in
// location based on address nibble latched above
assign r_data_out = (rd_addr_nibble == 4'hC) ? {r_data_in,96'd0} :
(rd_addr_nibble == 4'h8) ? {32'd0,r_data_in,64'd0} :
(rd_addr_nibble == 4'h4) ? {64'd0,r_data_in,32'd0} :
{96'd0,r_data_in};
endmodule
| 7.920252 |
module axilite_naive_bridge (
input axi_clk,
input axi_resetn,
input [31:0] axi_awaddr,
input [0:0] axi_awvalid,
output reg [0:0] axi_awready,
input [31:0] axi_wdata,
input [3:0] axi_wstrb,
input [0:0] axi_wvalid,
output reg [0:0] axi_wready,
output [1:0] axi_bresp,
output reg [0:0] axi_bvalid,
input [0:0] axi_bready,
input [31:0] axi_araddr,
input [0:0] axi_arvalid,
output [0:0] axi_arready,
output [31:0] axi_rdata,
output [1:0] axi_rresp,
output [0:0] axi_rvalid,
input [0:0] axi_rready,
output reg wdata_en,
output reg [31:0] wdata_addr,
output reg [31:0] wdata,
output reg [3:0] wdata_byte_en
);
assign axi_arready = 1'b0;
assign axi_rdata = 32'd0;
assign axi_rresp = 2'b0;
assign axi_rvalid = 1'b0;
assign axi_bresp = 2'd0;
reg [1:0] status;
always @(posedge axi_clk) begin
if (axi_resetn == 1'b0) begin
axi_awready <= 1'b0;
axi_wready <= 1'b0;
axi_bvalid <= 1'b0;
status <= 0;
wdata_en <= 1'b0;
end else begin
case (status)
2'd0: begin
if (axi_awvalid & axi_wvalid) begin
axi_awready <= 1'b1;
axi_wready <= 1'b1;
wdata <= axi_wdata;
wdata_addr <= axi_awaddr;
wdata_en <= 1'b1;
wdata_byte_en <= axi_wstrb;
status <= 2'd1;
end
end
2'd1: begin
axi_awready <= 1'b0;
axi_wready <= 1'b0;
wdata_en <= 1'b0;
axi_bvalid <= 1'b1;
status <= 2'd2;
end
2'd2: begin
if (axi_bready) begin
axi_bvalid <= 1'b0;
status <= 2'd0;
end
end
default: status <= 2'd0;
endcase
end
end
endmodule
| 7.418709 |
module
*/
module axil_reg_if #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
(
input wire clk,
input wire rst,
/*
* AXI-Lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* Register interface
*/
output wire [ADDR_WIDTH-1:0] reg_wr_addr,
output wire [DATA_WIDTH-1:0] reg_wr_data,
output wire [STRB_WIDTH-1:0] reg_wr_strb,
output wire reg_wr_en,
input wire reg_wr_wait,
input wire reg_wr_ack,
output wire [ADDR_WIDTH-1:0] reg_rd_addr,
output wire reg_rd_en,
input wire [DATA_WIDTH-1:0] reg_rd_data,
input wire reg_rd_wait,
input wire reg_rd_ack
);
axil_reg_if_wr #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.TIMEOUT(TIMEOUT)
)
axil_reg_if_wr_inst (
.clk(clk),
.rst(rst),
/*
* AXI-Lite slave interface
*/
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
/*
* Register interface
*/
.reg_wr_addr(reg_wr_addr),
.reg_wr_data(reg_wr_data),
.reg_wr_strb(reg_wr_strb),
.reg_wr_en(reg_wr_en),
.reg_wr_wait(reg_wr_wait),
.reg_wr_ack(reg_wr_ack)
);
axil_reg_if_rd #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.TIMEOUT(TIMEOUT)
)
axil_reg_if_rd_inst (
.clk(clk),
.rst(rst),
/*
* AXI-Lite slave interface
*/
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
/*
* Register interface
*/
.reg_rd_addr(reg_rd_addr),
.reg_rd_en(reg_rd_en),
.reg_rd_data(reg_rd_data),
.reg_rd_wait(reg_rd_wait),
.reg_rd_ack(reg_rd_ack)
);
endmodule
| 8.343407 |
module (read)
*/
module axil_reg_if_rd #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
(
input wire clk,
input wire rst,
/*
* AXI-Lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* Register interface
*/
output wire [ADDR_WIDTH-1:0] reg_rd_addr,
output wire reg_rd_en,
input wire [DATA_WIDTH-1:0] reg_rd_data,
input wire reg_rd_wait,
input wire reg_rd_ack
);
parameter TIMEOUT_WIDTH = $clog2(TIMEOUT);
reg [TIMEOUT_WIDTH-1:0] timeout_count_reg = 0, timeout_count_next;
reg [ADDR_WIDTH-1:0] s_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, s_axil_araddr_next;
reg s_axil_arvalid_reg = 1'b0, s_axil_arvalid_next;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_rdata_next;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
reg reg_rd_en_reg = 1'b0, reg_rd_en_next;
assign s_axil_arready = !s_axil_arvalid_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = 2'b00;
assign s_axil_rvalid = s_axil_rvalid_reg;
assign reg_rd_addr = s_axil_araddr_reg;
assign reg_rd_en = reg_rd_en_reg;
always @* begin
timeout_count_next = timeout_count_reg;
s_axil_araddr_next = s_axil_araddr_reg;
s_axil_arvalid_next = s_axil_arvalid_reg;
s_axil_rdata_next = s_axil_rdata_reg;
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
if (reg_rd_en_reg && (reg_rd_ack || timeout_count_reg == 0)) begin
s_axil_arvalid_next = 1'b0;
s_axil_rdata_next = reg_rd_data;
s_axil_rvalid_next = 1'b1;
end
if (!s_axil_arvalid_reg) begin
s_axil_araddr_next = s_axil_araddr;
s_axil_arvalid_next = s_axil_arvalid;
timeout_count_next = TIMEOUT-1;
end
if (reg_rd_en && !reg_rd_wait && timeout_count_reg != 0)begin
timeout_count_next = timeout_count_reg - 1;
end
reg_rd_en_next = s_axil_arvalid_next && !s_axil_rvalid_next;
end
always @(posedge clk) begin
timeout_count_reg <= timeout_count_next;
s_axil_araddr_reg <= s_axil_araddr_next;
s_axil_arvalid_reg <= s_axil_arvalid_next;
s_axil_rdata_reg <= s_axil_rdata_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
reg_rd_en_reg <= reg_rd_en_next;
if (rst) begin
s_axil_arvalid_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
reg_rd_en_reg <= 1'b0;
end
end
endmodule
| 8.317208 |
module (write)
*/
module axil_reg_if_wr #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
(
input wire clk,
input wire rst,
/*
* AXI-Lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
/*
* Register interface
*/
output wire [ADDR_WIDTH-1:0] reg_wr_addr,
output wire [DATA_WIDTH-1:0] reg_wr_data,
output wire [STRB_WIDTH-1:0] reg_wr_strb,
output wire reg_wr_en,
input wire reg_wr_wait,
input wire reg_wr_ack
);
parameter TIMEOUT_WIDTH = $clog2(TIMEOUT);
reg [TIMEOUT_WIDTH-1:0] timeout_count_reg = 0, timeout_count_next;
reg [ADDR_WIDTH-1:0] s_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, s_axil_awaddr_next;
reg s_axil_awvalid_reg = 1'b0, s_axil_awvalid_next;
reg [DATA_WIDTH-1:0] s_axil_wdata_reg = {DATA_WIDTH{1'b0}}, s_axil_wdata_next;
reg [STRB_WIDTH-1:0] s_axil_wstrb_reg = {STRB_WIDTH{1'b0}}, s_axil_wstrb_next;
reg s_axil_wvalid_reg = 1'b0, s_axil_wvalid_next;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
reg reg_wr_en_reg = 1'b0, reg_wr_en_next;
assign s_axil_awready = !s_axil_awvalid_reg;
assign s_axil_wready = !s_axil_wvalid_reg;
assign s_axil_bresp = 2'b00;
assign s_axil_bvalid = s_axil_bvalid_reg;
assign reg_wr_addr = s_axil_awaddr_reg;
assign reg_wr_data = s_axil_wdata_reg;
assign reg_wr_strb = s_axil_wstrb_reg;
assign reg_wr_en = reg_wr_en_reg;
always @* begin
timeout_count_next = timeout_count_reg;
s_axil_awaddr_next = s_axil_awaddr_reg;
s_axil_awvalid_next = s_axil_awvalid_reg;
s_axil_wdata_next = s_axil_wdata_reg;
s_axil_wstrb_next = s_axil_wstrb_reg;
s_axil_wvalid_next = s_axil_wvalid_reg;
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
if (reg_wr_en_reg && (reg_wr_ack || timeout_count_reg == 0)) begin
s_axil_awvalid_next = 1'b0;
s_axil_wvalid_next = 1'b0;
s_axil_bvalid_next = 1'b1;
end
if (!s_axil_awvalid_reg) begin
s_axil_awaddr_next = s_axil_awaddr;
s_axil_awvalid_next = s_axil_awvalid;
timeout_count_next = TIMEOUT-1;
end
if (!s_axil_wvalid_reg) begin
s_axil_wdata_next = s_axil_wdata;
s_axil_wstrb_next = s_axil_wstrb;
s_axil_wvalid_next = s_axil_wvalid;
end
if (reg_wr_en && !reg_wr_wait && timeout_count_reg != 0)begin
timeout_count_next = timeout_count_reg - 1;
end
reg_wr_en_next = s_axil_awvalid_next && s_axil_wvalid_next && !s_axil_bvalid_next;
end
always @(posedge clk) begin
timeout_count_reg <= timeout_count_next;
s_axil_awaddr_reg <= s_axil_awaddr_next;
s_axil_awvalid_reg <= s_axil_awvalid_next;
s_axil_wdata_reg <= s_axil_wdata_next;
s_axil_wstrb_reg <= s_axil_wstrb_next;
s_axil_wvalid_reg <= s_axil_wvalid_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
reg_wr_en_reg <= reg_wr_en_next;
if (rst) begin
s_axil_awvalid_reg <= 1'b0;
s_axil_wvalid_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
reg_wr_en_reg <= 1'b0;
end
end
endmodule
| 7.575563 |
module axil_to_ni_regport #(
parameter RP_AWIDTH = 16,
parameter RP_DWIDTH = 32,
parameter TIMEOUT = 512
) (
input s_axi_aclk,
input s_axi_areset,
// AXI4lite interface
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
input s_axi_wvalid,
output s_axi_wready,
output [ 1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
// RegPort interface, the out vs in
// is seen from the slave device
// hooked up to the regport
output reg_port_in_rd,
output reg_port_in_wt,
output [RP_AWIDTH-1:0] reg_port_in_addr,
output [RP_DWIDTH-1:0] reg_port_in_data,
input [RP_DWIDTH-1:0] reg_port_out_data,
input reg_port_out_ready
);
localparam IDLE = 3'd0;
localparam READ_INIT = 3'd1;
localparam WRITE_INIT = 3'd2;
localparam READ_IN_PROGRESS = 3'd3;
localparam WRITE_IN_PROGRESS = 3'd4;
localparam WRITE_DONE = 3'd5;
localparam READ_DONE = 3'd6;
reg [RP_AWIDTH-1:0] addr;
reg [RP_DWIDTH-1:0] rb_data;
reg [RP_DWIDTH-1:0] wr_data;
reg [2:0] state;
reg [9:0] count;
reg [1:0] rresp;
reg [1:0] bresp;
always @(posedge s_axi_aclk) begin
if (s_axi_areset) begin
state <= IDLE;
addr <= 'd0;
rb_data <= 'd0;
wr_data <= 'd0;
count <= 10'd0;
rresp <= 2'd0;
bresp <= 2'd0;
end else
case (state)
IDLE: begin
if (s_axi_arvalid) begin
state <= READ_INIT;
addr <= s_axi_araddr[RP_AWIDTH-1:0];
end else if (s_axi_awvalid) begin
state <= WRITE_INIT;
addr <= s_axi_awaddr[RP_AWIDTH-1:0];
end
end
READ_INIT: begin
state <= READ_IN_PROGRESS;
count <= 10'd0;
rresp <= 2'b00;
end
READ_IN_PROGRESS: begin
if (reg_port_out_ready) begin
rb_data <= reg_port_out_data;
state <= READ_DONE;
end else if (count >= TIMEOUT) begin
state <= READ_DONE;
rresp <= 2'b10;
end else begin
count <= count + 1'b1;
end
end
READ_DONE: begin
if (s_axi_rready) begin
state <= IDLE;
end
end
WRITE_INIT: begin
if (s_axi_wvalid) begin
wr_data <= s_axi_wdata[RP_DWIDTH-1:0];
state <= WRITE_IN_PROGRESS;
count <= 10'd0;
bresp <= 2'b00;
end
end
WRITE_IN_PROGRESS: begin
if (reg_port_out_ready) begin
state <= WRITE_DONE;
end else if (count >= TIMEOUT) begin
state <= READ_DONE;
bresp <= 2'b10;
end else begin
count <= count + 1'b1;
end
end
WRITE_DONE: begin
if (s_axi_bready) state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
assign s_axi_awready = (state == IDLE);
assign s_axi_wready = (state == WRITE_INIT);
assign s_axi_bvalid = (state == WRITE_DONE);
assign s_axi_bresp = bresp;
assign s_axi_arready = (state == IDLE);
assign s_axi_rdata = rb_data;
assign s_axi_rvalid = (state == READ_DONE);
assign s_axi_rresp = rresp;
assign reg_port_in_wt = (state == WRITE_INIT) & s_axi_wvalid;
assign reg_port_in_data = (state == WRITE_INIT) ? s_axi_wdata : wr_data;
assign reg_port_in_addr = addr;
assign reg_port_in_rd = (state == READ_INIT);
endmodule
| 7.912545 |
module AxiModule #(
parameter DATA_WIDTH_SLAVE = 32,
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8,
parameter ADDRESS_WIDTH_SLAVE = 8,
parameter DATA_WIDTH_MASTER = 32,
parameter STROBE_WIDTH_MASTER = DATA_WIDTH_MASTER / 8,
parameter ADDRESS_WIDTH_MASTER = 8
) (
input read,
input write,
input aclk_axi,
input aresetn_axi
);
//master input
wire awready;
wire wready;
wire bvalid;
wire arready;
wire [DATA_WIDTH_MASTER-1:0] rdata;
wire rvalid;
//slave input
wire [ADDRESS_WIDTH_SLAVE-1:0] awaddr;
wire awvalid;
wire [DATA_WIDTH_SLAVE-1:0] wdata;
wire [STROBE_WIDTH_SLAVE-1:0] wstrb;
wire wvalid;
wire bready;
wire [ADDRESS_WIDTH_SLAVE-1:0] araddr;
wire [2:0] arprot;
wire arvalid;
wire rready;
//Master instance
MasterModule MM0 (
.aclk(aclk_axi),
.aresetn(aresetn_axi),
.awready(awready),
.wready(wready),
.bvalid(bvalid),
.arready(arready),
.rdata(rdata),
.rvalid(rvalid),
.awvalid(awvalid),
.wdata(wdata),
.wstrb(wstrb),
.wvalid(wvalid),
.bready(bready),
.arprot(arprot),
.arvalid(arvalid),
.rready(rready),
.read(read),
.write(write),
.awaddr(awaddr),
.araddr(araddr)
);
//Slave instance
SlaveModule SM0 (
.aclk(aclk_axi),
.aresetn(aresetn_axi),
.awaddr(awaddr),
.awvalid(awvalid),
.wdata(wdata),
.wstrb(wstrb),
.wvalid(wvalid),
.bready(bready),
.araddr(araddr),
.arprot(arprot),
.arvalid(arvalid),
.rready(rready),
.awready(awready),
.wready(wready),
.bvalid(bvalid),
.arready(arready),
.rdata(rdata),
.rvalid(rvalid)
);
endmodule
| 7.120443 |
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire [KEEP_WIDTH-1:0] axis_tkeep,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
input wire axis_tuser,
input wire avst_ready,
output wire avst_valid,
output wire [ DATA_WIDTH-1:0] avst_data,
output wire avst_startofpacket,
output wire avst_endofpacket,
output wire [EMPTY_WIDTH-1:0] avst_empty,
output wire avst_error
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
reg frame_reg = 1'b0;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign avst_data = axis_tdata;
end
endgenerate
reg [EMPTY_WIDTH-1:0] empty;
assign avst_empty = empty;
integer k;
always @* begin
empty = KEEP_WIDTH - 1;
for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
if (axis_tkeep[k]) begin
empty = KEEP_WIDTH - 1 - k;
end
end
end
assign avst_valid = axis_tvalid;
assign avst_startofpacket = axis_tvalid & !frame_reg;
assign avst_endofpacket = axis_tlast;
assign avst_error = axis_tuser;
assign axis_tready = avst_ready;
always @(posedge clk) begin
if (axis_tvalid && axis_tready) begin
frame_reg <= !axis_tlast;
end
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
| 7.419624 |
module axis2axi #(
parameter AXI_ADDR_W = 0,
parameter AXI_DATA_W = 32, // We currently only support 4 byte transfers
parameter AXI_LEN_W = 8,
parameter AXI_ID_W = 1,
parameter BURST_W = 0,
parameter BUFFER_W = BURST_W + 1
) (
// Configuration (AXIS In)
input [AXI_ADDR_W-1:0] config_in_addr_i,
input [ 1-1:0] config_in_valid_i,
output [ 1-1:0] config_in_ready_o,
// AXIS In
input [AXI_DATA_W-1:0] axis_in_data_i,
input [ 1-1:0] axis_in_valid_i,
output [ 1-1:0] axis_in_ready_o,
// Configuration (AXIS Out)
input [AXI_ADDR_W-1:0] config_out_addr_i,
input [AXI_ADDR_W-1:0] config_out_length_i,
input [ 1-1:0] config_out_valid_i,
output [ 1-1:0] config_out_ready_o,
// AXIS Out
output [AXI_DATA_W-1:0] axis_out_data_o,
output [ 1-1:0] axis_out_valid_o,
input [ 1-1:0] axis_out_ready_i,
// AXI master interface
`include "axi_m_port.vs"
// External memory interfaces
output [ 1-1:0] ext_mem_w_en_o,
output [AXI_DATA_W-1:0] ext_mem_w_data_o,
output [ BUFFER_W-1:0] ext_mem_w_addr_o,
output [ 1-1:0] ext_mem_r_en_o,
output [ BUFFER_W-1:0] ext_mem_r_addr_o,
input [AXI_DATA_W-1:0] ext_mem_r_data_i,
input clk_i,
input cke_i,
input rst_i,
input arst_i
);
axis2axi_in #(
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ID_W (AXI_ID_W),
.BURST_W (BURST_W)
) axis2axi_in_inst (
.config_in_addr_i (config_in_addr_i),
.config_in_valid_i(config_in_valid_i),
.config_in_ready_o(config_in_ready_o),
.ext_mem_w_en_o (ext_mem_w_en_o),
.ext_mem_w_data_o(ext_mem_w_data_o),
.ext_mem_w_addr_o(ext_mem_w_addr_o),
.ext_mem_r_en_o (ext_mem_r_en_o),
.ext_mem_r_addr_o(ext_mem_r_addr_o),
.ext_mem_r_data_i(ext_mem_r_data_i),
.axis_in_data_i (axis_in_data_i),
.axis_in_valid_i(axis_in_valid_i),
.axis_in_ready_o(axis_in_ready_o),
`include "axi_m_m_write_portmap.vs"
.clk_i (clk_i),
.cke_i (cke_i),
.rst_i (rst_i),
.arst_i(arst_i)
);
axis2axi_out #(
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ID_W (AXI_ID_W),
.BURST_W (BURST_W)
) axis2axi_out_inst (
.config_out_addr_i (config_out_addr_i),
.config_out_length_i(config_out_length_i),
.config_out_valid_i (config_out_valid_i),
.config_out_ready_o (config_out_ready_o),
.axis_out_data_o (axis_out_data_o),
.axis_out_valid_o(axis_out_valid_o),
.axis_out_ready_i(axis_out_ready_i),
`include "axi_m_m_read_portmap.vs"
.clk_i (clk_i),
.cke_i (cke_i),
.rst_i (rst_i),
.arst_i(arst_i)
);
endmodule
| 8.59901 |
module AXIS2VGA_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface params_AXI
parameter integer C_params_AXI_DATA_WIDTH = 32,
parameter integer C_params_AXI_ADDR_WIDTH = 4,
// Parameters of Axi Slave Bus Interface video_AXI
parameter integer C_video_AXI_TDATA_WIDTH = 32
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface params_AXI
input wire params_axi_aclk,
input wire params_axi_aresetn,
input wire [C_params_AXI_ADDR_WIDTH-1 : 0] params_axi_awaddr,
input wire [2 : 0] params_axi_awprot,
input wire params_axi_awvalid,
output wire params_axi_awready,
input wire [C_params_AXI_DATA_WIDTH-1 : 0] params_axi_wdata,
input wire [(C_params_AXI_DATA_WIDTH/8)-1 : 0] params_axi_wstrb,
input wire params_axi_wvalid,
output wire params_axi_wready,
output wire [1 : 0] params_axi_bresp,
output wire params_axi_bvalid,
input wire params_axi_bready,
input wire [C_params_AXI_ADDR_WIDTH-1 : 0] params_axi_araddr,
input wire [2 : 0] params_axi_arprot,
input wire params_axi_arvalid,
output wire params_axi_arready,
output wire [C_params_AXI_DATA_WIDTH-1 : 0] params_axi_rdata,
output wire [1 : 0] params_axi_rresp,
output wire params_axi_rvalid,
input wire params_axi_rready,
// Ports of Axi Slave Bus Interface video_AXI
input wire video_axi_aclk,
input wire video_axi_aresetn,
output wire video_axi_tready,
input wire [C_video_AXI_TDATA_WIDTH-1 : 0] video_axi_tdata,
input wire [(C_video_AXI_TDATA_WIDTH/8)-1 : 0] video_axi_tstrb,
input wire video_axi_tlast,
input wire video_axi_tvalid
);
// Instantiation of Axi Bus Interface params_AXI
AXIS2VGA_v1_0_params_AXI #(
.C_S_AXI_DATA_WIDTH(C_params_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_params_AXI_ADDR_WIDTH)
) AXIS2VGA_v1_0_params_AXI_inst (
.S_AXI_ACLK(params_axi_aclk),
.S_AXI_ARESETN(params_axi_aresetn),
.S_AXI_AWADDR(params_axi_awaddr),
.S_AXI_AWPROT(params_axi_awprot),
.S_AXI_AWVALID(params_axi_awvalid),
.S_AXI_AWREADY(params_axi_awready),
.S_AXI_WDATA(params_axi_wdata),
.S_AXI_WSTRB(params_axi_wstrb),
.S_AXI_WVALID(params_axi_wvalid),
.S_AXI_WREADY(params_axi_wready),
.S_AXI_BRESP(params_axi_bresp),
.S_AXI_BVALID(params_axi_bvalid),
.S_AXI_BREADY(params_axi_bready),
.S_AXI_ARADDR(params_axi_araddr),
.S_AXI_ARPROT(params_axi_arprot),
.S_AXI_ARVALID(params_axi_arvalid),
.S_AXI_ARREADY(params_axi_arready),
.S_AXI_RDATA(params_axi_rdata),
.S_AXI_RRESP(params_axi_rresp),
.S_AXI_RVALID(params_axi_rvalid),
.S_AXI_RREADY(params_axi_rready)
);
// Instantiation of Axi Bus Interface video_AXI
AXIS2VGA_v1_0_video_AXI #(
.C_S_AXIS_TDATA_WIDTH(C_video_AXI_TDATA_WIDTH)
) AXIS2VGA_v1_0_video_AXI_inst (
.S_AXIS_ACLK(video_axi_aclk),
.S_AXIS_ARESETN(video_axi_aresetn),
.S_AXIS_TREADY(video_axi_tready),
.S_AXIS_TDATA(video_axi_tdata),
.S_AXIS_TSTRB(video_axi_tstrb),
.S_AXIS_TLAST(video_axi_tlast),
.S_AXIS_TVALID(video_axi_tvalid)
);
// Add user logic here
// User logic ends
endmodule
| 7.330842 |
module axis2wb (
input wire i_clk,
input wire i_rst,
input wire [0:0] i_wb_sel,
input wire i_wb_stb,
output wire [9:0] o_wb_rdt,
output reg o_wb_ack,
input wire [7:0] i_tdata,
input wire i_tlast,
input wire i_tvalid,
output wire o_tready
);
always @(posedge i_clk) begin
o_wb_ack <= i_wb_stb & !o_wb_ack;
if (i_rst) o_wb_ack <= 1'b0;
end
assign o_tready = i_wb_sel[0] & o_wb_ack;
assign o_wb_rdt = {i_tvalid, i_tlast, i_tdata};
endmodule
| 7.702976 |
module axisFIFO (
m_aclk,
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tuser,
s_axis_tstrb,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tuser,
m_axis_tstrb,
m_axis_tlast
);
parameter C_AXIS_DATA_WIDTH = 32;
parameter C_AXIS_USER_WIDTH = 128;
input m_aclk;
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [C_AXIS_DATA_WIDTH-1 : 0] s_axis_tdata;
input [C_AXIS_DATA_WIDTH/8-1 : 0] s_axis_tstrb;
input [C_AXIS_USER_WIDTH-1 : 0] s_axis_tuser;
input s_axis_tlast;
output m_axis_tvalid;
input m_axis_tready;
output [C_AXIS_DATA_WIDTH-1 : 0] m_axis_tdata;
output [C_AXIS_DATA_WIDTH/8-1 : 0] m_axis_tstrb;
output [C_AXIS_USER_WIDTH-1 : 0] m_axis_tuser;
output m_axis_tlast;
wire nearly_full;
wire empty;
assign s_axis_tready = ~nearly_full;
assign m_axis_tvalid = ~empty;
fallthrough_small_async_fifo #(
.WIDTH(C_AXIS_DATA_WIDTH + C_AXIS_DATA_WIDTH / 8 + 1 + C_AXIS_USER_WIDTH),
.MAX_DEPTH_BITS(3)
) fifo (
.din({s_axis_tdata, s_axis_tstrb, s_axis_tlast, s_axis_tuser}), // Data in
.wr_en(s_axis_tvalid & s_axis_tready), // Write enable
.rd_en(m_axis_tvalid & m_axis_tready), // Read the next word
.dout({m_axis_tdata, m_axis_tstrb, m_axis_tlast, m_axis_tuser}), // Data out
.full(),
.nearly_full(nearly_full),
.empty(empty),
.reset (~s_aresetn),
.rd_clk(m_aclk),
.wr_clk(s_aclk)
);
endmodule
| 8.688696 |
module axislave_stub ( /*AUTOARG*/
// Outputs
s_axi_arready,
s_axi_awready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_rid,
s_axi_rdata,
s_axi_rlast,
s_axi_rresp,
s_axi_rvalid,
s_axi_wready,
// Inputs
s_axi_aclk,
s_axi_aresetn,
s_axi_arid,
s_axi_araddr,
s_axi_arburst,
s_axi_arcache,
s_axi_arlock,
s_axi_arlen,
s_axi_arprot,
s_axi_arqos,
s_axi_arsize,
s_axi_arvalid,
s_axi_awid,
s_axi_awaddr,
s_axi_awburst,
s_axi_awcache,
s_axi_awlock,
s_axi_awlen,
s_axi_awprot,
s_axi_awqos,
s_axi_awsize,
s_axi_awvalid,
s_axi_bready,
s_axi_rready,
s_axi_wid,
s_axi_wdata,
s_axi_wlast,
s_axi_wstrb,
s_axi_wvalid
);
parameter S_IDW = 12;
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aclk;
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
//read address chanel
assign s_axi_arready = 'b0;
//write address channel
assign s_axi_awready = 'b0;
//buffered write response
assign s_axi_bid[S_IDW-1:0] = 'b0;
assign s_axi_bresp[1:0] = 'b0;
//read channel
assign s_axi_rid[S_IDW-1:0] = 'b0;
assign s_axi_rdata[31:0] = 'b0;
assign s_axi_rlast = 'b0;
assign s_axi_rresp[1:0] = 'b0;
assign s_axi_rvalid = 'b0;
//write channel
assign s_axi_wready = 'b0;
endmodule
| 8.028731 |
module axisrandom #(
// {{{
localparam C_AXIS_DATA_WIDTH = 32
// }}}
) (
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
output reg M_AXIS_TVALID,
input wire M_AXIS_TREADY,
output reg [C_AXIS_DATA_WIDTH-1:0] M_AXIS_TDATA
// }}}
);
localparam INITIAL_FILL = {1'b1, {(C_AXIS_DATA_WIDTH - 1) {1'b0}}};
localparam LGPOLY = 31;
localparam [LGPOLY-1:0] CORE_POLY = {31'h00_00_20_01};
localparam [C_AXIS_DATA_WIDTH-1:0] POLY = {CORE_POLY, {(C_AXIS_DATA_WIDTH - 31) {1'b0}}};
// M_AXIS_TVALID
// {{{
initial M_AXIS_TVALID = 1'b0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN) M_AXIS_TVALID <= 1'b0;
else M_AXIS_TVALID <= 1'b1;
// }}}
// M_AXIS_TDATA
// {{{
//
// Note--this setup is *FAR* from cryptographically random.
//
initial M_AXIS_TDATA = INITIAL_FILL;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN) M_AXIS_TDATA <= INITIAL_FILL;
else if (M_AXIS_TREADY) begin
M_AXIS_TDATA <= M_AXIS_TDATA >> 1;
M_AXIS_TDATA[C_AXIS_DATA_WIDTH-1] <= ^(M_AXIS_TDATA & POLY);
end
// }}}
// Verilator lint_off UNUSED
// {{{
wire unused;
assign unused = &{1'b0};
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal properties used in verfiying this core
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge S_AXI_ACLK) f_past_valid <= 1'b1;
always @(*) if (!f_past_valid) assume (!S_AXI_ARESETN);
// Make certain this polynomial will never degenerate, and so that
// this random number stream will go on for ever--eventually repeating
// after 2^LGPOLY-1 (hopefully) elements.
always @(*) assert (M_AXIS_TDATA[C_AXIS_DATA_WIDTH-1:C_AXIS_DATA_WIDTH-LGPOLY] != 0);
// AXI stream has only one significant property
// {{{
// Here we'll modify it slightly for our purposes
always @(posedge S_AXI_ACLK)
if (!f_past_valid || $past(!S_AXI_ARESETN))
assert (!M_AXIS_TVALID);
else begin
assert (M_AXIS_TVALID);
if ($past(M_AXIS_TVALID && !M_AXIS_TREADY))
// Normally I'd assesrt M_AXIS_TVALID here, not above,
// but this core *ALWAYS* produces data
assert ($stable(
M_AXIS_TDATA
));
else if ($past(M_AXIS_TVALID))
// Insist that the data always changes otherwise
assert ($changed(
M_AXIS_TDATA
));
end
// }}}
`endif
// }}}
endmodule
| 8.692105 |
module axistream_add_tlast (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
add_tlast
);
parameter DATA_WIDTH = 8;
input clk;
input rst;
input src_tvalid;
output src_tready;
input [DATA_WIDTH-1:0] src_tdata;
output dest_tvalid;
input dest_tready;
output [DATA_WIDTH-1:0] dest_tdata;
output dest_tlast;
input add_tlast;
reg [DATA_WIDTH-1:0] data_buf;
reg buffered;
reg hold_tlast;
assign dest_tvalid = !rst && (
(src_tvalid && buffered)
|| (buffered && (add_tlast || hold_tlast))
);
assign src_tready = !rst;
assign dest_tlast = dest_tvalid && (add_tlast || hold_tlast);
assign dest_tdata = data_buf;
initial begin
buffered = 1'b0;
hold_tlast = 1'b0;
end
always @(posedge clk) begin
if (src_tvalid && src_tready) begin
data_buf <= src_tdata;
buffered <= 1'b1;
hold_tlast <= 1'b0;
end else if (dest_tvalid && dest_tready) begin
buffered <= 1'b0;
data_buf <= data_buf;
hold_tlast <= 1'b0;
end else begin
buffered <= buffered;
data_buf <= data_buf;
if (buffered && add_tlast) begin
hold_tlast <= 1'b1;
end else begin
hold_tlast <= 1'b0;
end
end
if (rst) begin
hold_tlast <= 1'b0;
buffered <= 1'b0;
end
end
endmodule
| 6.506958 |
module axistream_pack (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast, //! may only be raised on multiples of NUM_PACK of src
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
tlast_align_err //! src_tlast && src_tvalid at invalid time for src_tlast
);
parameter DATA_WIDTH = 8;
parameter NUM_PACK = 4;
parameter BIG_ENDIAN = 1'b0; //! most significant word comes first from src
input clk;
input rst;
input src_tvalid;
output src_tready;
input [DATA_WIDTH-1:0] src_tdata;
input src_tlast;
output dest_tvalid;
input dest_tready;
output [(DATA_WIDTH*NUM_PACK)-1:0] dest_tdata;
output dest_tlast;
output reg tlast_align_err;
reg [(NUM_PACK*DATA_WIDTH)-1:0] data_buf;
reg [ NUM_PACK-1:0] tlast_buf;
reg [ $clog2(NUM_PACK+1)-1:0] cnt;
assign dest_tvalid = (cnt == NUM_PACK) ? !rst : 1'b0;
assign src_tready = (cnt == NUM_PACK) ? dest_tvalid && dest_tready : !rst;
assign dest_tdata = data_buf;
assign dest_tlast = (!BIG_ENDIAN) ? tlast_buf[NUM_PACK-1] : tlast_buf[0];
initial begin
cnt = 0;
tlast_align_err = 1'b0;
end
always @(posedge clk) begin
//rst overrides cnt and tlast_align_err
if (src_tvalid && src_tready) begin
if (!BIG_ENDIAN) begin
data_buf[((NUM_PACK-1)*DATA_WIDTH)-1:0] <= data_buf[NUM_PACK*DATA_WIDTH-1:DATA_WIDTH];
data_buf[NUM_PACK*DATA_WIDTH-1:(NUM_PACK-1)*DATA_WIDTH] <= src_tdata;
tlast_buf[NUM_PACK-2:0] <= tlast_buf[NUM_PACK-1:1];
tlast_buf[NUM_PACK-1] <= src_tlast;
end else begin
data_buf[NUM_PACK*DATA_WIDTH-1:DATA_WIDTH] <= data_buf[((NUM_PACK-1)*DATA_WIDTH)-1:0];
data_buf[DATA_WIDTH-1 : 0] <= src_tdata;
tlast_buf[NUM_PACK-1:1] <= tlast_buf[NUM_PACK-2:0];
tlast_buf[0] <= src_tlast;
end
end else begin
data_buf <= data_buf;
tlast_buf <= tlast_buf;
end
if (src_tvalid && src_tready && dest_tvalid && dest_tready) begin
cnt <= 1;
end else if (dest_tvalid && dest_tready) begin
cnt <= 0;
end else if (src_tvalid && src_tready) begin
cnt <= cnt + 1;
end else begin
cnt <= cnt;
end
if (dest_tvalid && dest_tready) begin
if (!BIG_ENDIAN) begin
tlast_align_err <= (|tlast_buf[NUM_PACK-2:0]) ? 1'b1 : 1'b0;
end else begin
tlast_align_err <= (|tlast_buf[NUM_PACK-1:1]) ? 1'b1 : 1'b0;
end
end else begin
tlast_align_err <= 1'b0;
end
if (rst) begin
cnt <= 0;
tlast_align_err <= 1'b0;
end
end
endmodule
| 6.718493 |
module axistream_snooper # (parameter
DATA_WIDTH = 64,
ADDR_WIDTH = 9,
PESSIMISTIC = 0
)(
input wire clk,
//AXI Stream interface
input wire [DATA_WIDTH-1:0] TDATA,
input wire TVALID,
input wire TREADY, //Yes, this is an input. Remember that we're snooping!
input wire TLAST,
//Interface to packet mem
output wire [ADDR_WIDTH-1:0] wr_addr,
output wire [DATA_WIDTH-1:0] wr_data,
input wire mem_ready,
output wire wr_en,
output wire done
);
wire mem_ready_internal;
////////////////////////////////////////
////////// PESSIMISTIC MODE ////////////
////////////////////////////////////////
generate
if (PESSIMISTIC) begin
//Delay mem_ready by one cycle, in order to improve timing
//And also force this to zero right after snooper_done (since it
//has to "refill"
reg mem_ready_r = 0;
always @(posedge clk) mem_ready_r <= mem_ready && !done;
assign mem_ready_internal = mem_ready_r;
end
///////////////////////////////////////
////////// OPTIMISTIC MODE ////////////
///////////////////////////////////////
else begin
assign mem_ready_internal = mem_ready;
end
endgenerate
///////////////////////////////////////
//We should make this wait for a packet to start, right?
//As in, wait for TLAST, and only then start copying
//To be even more specific: the problem occurs when TREADY and TVALID are 1
//(meaning new data went through the bus) but mem_ready was low
reg need_to_wait = 0;
wire next_need_to_wait;
assign next_need_to_wait = TLAST ? 0 : ((TVALID && TREADY && !mem_ready_internal) ? 1 : need_to_wait);
always @(posedge clk) need_to_wait <= next_need_to_wait;
assign wr_data = TDATA; //TODO: make this work for arbitrary widths
reg [ADDR_WIDTH-1:0] addr = 0;
wire [ADDR_WIDTH-1:0] next_addr;
assign wr_en = (mem_ready_internal && TVALID && TREADY && !need_to_wait);
//make done = 1 on our last write
assign done = TLAST && wr_en;
assign next_addr = wr_en ? (done ? 0 : addr + 1) : addr;
always @(posedge clk) begin
addr <= next_addr;
end
assign wr_addr = addr;
endmodule
| 6.916855 |
module axistream_unpack (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast
);
parameter DATA_WIDTH = 8;
parameter NUM_PACK = 4;
parameter BIG_ENDIAN = 1'b0; //! if true, src's least signicant word is first
input clk;
input rst;
input src_tvalid;
output src_tready;
input [(DATA_WIDTH*NUM_PACK)-1:0] src_tdata;
input src_tlast;
output dest_tvalid;
input dest_tready;
output [DATA_WIDTH-1:0] dest_tdata;
output dest_tlast;
reg [(NUM_PACK*DATA_WIDTH)-1:0] data_buf;
wire [ DATA_WIDTH-1:0] data_arr [NUM_PACK-1:0];
reg tlast_buf;
reg is_nempty;
reg [ $clog2(NUM_PACK+1)-1:0] cnt;
reg [ $clog2(NUM_PACK+1)-1:0] inv_cnt;
assign dest_tvalid = is_nempty && !rst;
assign src_tready = !rst && (!is_nempty || (dest_tvalid && dest_tready && cnt == NUM_PACK - 1));
assign dest_tlast = tlast_buf && dest_tvalid;
genvar i;
generate
for (i = 0; i < NUM_PACK; i = i + 1) begin
assign data_arr[i] = data_buf[(i+1)*DATA_WIDTH-1:i*DATA_WIDTH];
end
endgenerate
assign dest_tdata = (BIG_ENDIAN) ? data_arr[inv_cnt] : data_arr[cnt];
initial begin
cnt = 0;
inv_cnt = NUM_PACK - 1;
is_nempty = 1'b0;
end
always @(posedge clk) begin
//rst at end of block, overrides cnt, inv_cnt, and is_nempty
if (src_tvalid && src_tready) begin
data_buf <= src_tdata;
tlast_buf <= src_tlast;
is_nempty <= 1'b1;
end else begin
data_buf <= data_buf;
tlast_buf <= tlast_buf;
if ((cnt == NUM_PACK - 1) && dest_tvalid && dest_tready) begin
is_nempty <= 1'b0;
end else begin
is_nempty <= is_nempty;
end
end
if (dest_tvalid && dest_tready) begin
cnt <= (cnt + 1) % NUM_PACK;
inv_cnt <= (inv_cnt == 0) ? NUM_PACK - 1 : inv_cnt - 1;
end else begin
cnt <= cnt;
inv_cnt <= inv_cnt;
end
if (rst) begin
cnt <= 0;
inv_cnt <= NUM_PACK - 1;
is_nempty <= 1'b0;
end
end
endmodule
| 7.782006 |
module axistream_wait_until (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
go //! raise to allow full packet of data through
);
parameter DATA_WIDTH = 8;
input clk;
input rst;
input src_tvalid;
output src_tready;
input [DATA_WIDTH-1:0] src_tdata;
input src_tlast;
output dest_tvalid;
input dest_tready;
output [DATA_WIDTH-1:0] dest_tdata;
output dest_tlast;
input go;
localparam SM_WAIT = 0;
localparam SM_GO = 1;
reg sm;
assign dest_tvalid = (sm == SM_GO) ? src_tvalid && !rst : 1'b0;
assign src_tready = (sm == SM_GO) ? dest_tready && !rst : 1'b0;
assign dest_tlast = (sm == SM_GO) ? src_tlast && dest_tvalid : 1'b0;
assign dest_tdata = src_tdata;
initial begin
sm = SM_WAIT;
end
always @(posedge clk) begin
case (sm)
SM_WAIT: sm <= (go) ? SM_WAIT : SM_GO;
SM_GO: sm <= (dest_tvalid && dest_tready && dest_tlast) ? SM_WAIT : SM_GO;
endcase
if (rst) begin
sm <= SM_WAIT;
end
end
endmodule
| 7.622848 |
module axis_2_fifo_adapter #(
parameter AXIS_DATA_WIDTH = 32,
parameter FIFO_DATA_WIDTH = AXIS_DATA_WIDTH
) (
input wire i_axis_tuser,
input wire i_axis_tvalid,
output wire o_axis_tready,
input wire i_axis_tlast,
input wire [AXIS_DATA_WIDTH - 1:0] i_axis_tdata,
output wire [FIFO_DATA_WIDTH - 1:0] o_fifo_data,
output wire o_fifo_w_stb,
input wire i_fifo_not_full
);
/* ===============================
* asynchronous logic
* =============================== */
assign o_fifo_data = i_axis_tdata;
assign o_axis_tready = i_fifo_not_full;
assign o_fifo_w_stb = i_axis_tvalid & o_axis_tready;
endmodule
| 7.467097 |
module axis_bitonic_comp #(
parameter DATA_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*2-1:0] s_axis_tdata,
input wire [USER_WIDTH*2-1:0] s_axis_tuser,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
output wire [DATA_WIDTH*2-1:0] m_axis_tdata,
output wire [USER_WIDTH*2-1:0] m_axis_tuser,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast
);
wire [DATA_WIDTH-1:0] data_a;
wire [DATA_WIDTH-1:0] data_b;
reg [DATA_WIDTH-1:0] data_h;
reg [DATA_WIDTH-1:0] data_l;
wire [USER_WIDTH-1:0] user_a;
wire [USER_WIDTH-1:0] user_b;
reg [USER_WIDTH-1:0] user_h;
reg [USER_WIDTH-1:0] user_l;
reg last;
reg op_done;
wire valid_i;
wire valid_o;
wire less;
assign valid_i = s_axis_tvalid & s_axis_tready;
assign valid_o = m_axis_tvalid & m_axis_tready;
assign s_axis_tready = (op_done ? m_axis_tready : 1'b1) & aresetn;
assign m_axis_tvalid = op_done & aresetn;
assign m_axis_tdata = {data_h, data_l};
assign m_axis_tuser = {user_h, user_l};
assign m_axis_tlast = last;
assign data_a = s_axis_tdata[DATA_WIDTH*1-1-:DATA_WIDTH];
assign data_b = s_axis_tdata[DATA_WIDTH*2-1-:DATA_WIDTH];
assign user_a = s_axis_tuser[USER_WIDTH*1-1-:USER_WIDTH];
assign user_b = s_axis_tuser[USER_WIDTH*2-1-:USER_WIDTH];
assign less = (SIGNED == 0) ? ($unsigned(
data_a
) < $unsigned(
data_b
)) : $signed(
data_a
) < $signed(
data_b
);
always @(posedge aclk) begin
if (aresetn == 1'b0) begin
data_h <= 0;
data_l <= 0;
user_h <= 0;
user_l <= 0;
last <= 1'b0;
end else begin
if (valid_i == 1'b1) begin
if (POLARITY == 0) begin
data_h <= (less) ? data_a : data_b;
data_l <= (less) ? data_b : data_a;
user_h <= (less) ? user_a : user_b;
user_l <= (less) ? user_b : user_a;
end else begin
data_h <= (less) ? data_b : data_a;
data_l <= (less) ? data_a : data_b;
user_h <= (less) ? user_b : user_a;
user_l <= (less) ? user_a : user_b;
end
last <= s_axis_tlast;
end
end
end
always @(posedge aclk) begin
if (aresetn == 1'b0) begin
op_done <= 1'b0;
end else begin
case ({
valid_i, valid_o
})
2'b01: op_done <= 1'b0;
2'b10: op_done <= 1'b1;
default: op_done <= op_done;
endcase
end
end
endmodule
| 7.872602 |
module axis_bitonic_node #(
parameter DATA_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] s_axis_tdata,
input wire [USER_WIDTH*2**(ORDER+1)-1:0] s_axis_tuser,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
output wire [DATA_WIDTH*2**(ORDER+1)-1:0] m_axis_tdata,
output wire [USER_WIDTH*2**(ORDER+1)-1:0] m_axis_tuser,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast
);
localparam COMP_NUM = 2 ** ORDER;
genvar i;
generate
for (i = 0; i < COMP_NUM; i = i + 1) begin : COMP
wire [DATA_WIDTH-1:0] data_a;
wire [DATA_WIDTH-1:0] data_b;
wire [DATA_WIDTH-1:0] data_h;
wire [DATA_WIDTH-1:0] data_l;
wire [USER_WIDTH-1:0] user_a;
wire [USER_WIDTH-1:0] user_b;
wire [USER_WIDTH-1:0] user_h;
wire [USER_WIDTH-1:0] user_l;
assign data_a = s_axis_tdata[DATA_WIDTH*(i+1+COMP_NUM*0)-1-:DATA_WIDTH];
assign data_b = s_axis_tdata[DATA_WIDTH*(i+1+COMP_NUM*1)-1-:DATA_WIDTH];
assign m_axis_tdata[DATA_WIDTH*(i+1+COMP_NUM*0)-1-:DATA_WIDTH] = data_h;
assign m_axis_tdata[DATA_WIDTH*(i+1+COMP_NUM*1)-1-:DATA_WIDTH] = data_l;
assign user_a = s_axis_tuser[USER_WIDTH*(i+1+COMP_NUM*0)-1-:USER_WIDTH];
assign user_b = s_axis_tuser[USER_WIDTH*(i+1+COMP_NUM*1)-1-:USER_WIDTH];
assign m_axis_tuser[USER_WIDTH*(i+1+COMP_NUM*0)-1-:USER_WIDTH] = user_h;
assign m_axis_tuser[USER_WIDTH*(i+1+COMP_NUM*1)-1-:USER_WIDTH] = user_l;
if (i == 0) begin
axis_bitonic_comp #(
.DATA_WIDTH(DATA_WIDTH),
.USER_WIDTH(USER_WIDTH),
.POLARITY(POLARITY),
.SIGNED(SIGNED)
) abc_inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tdata({data_b, data_a}),
.s_axis_tuser({user_b, user_a}),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.m_axis_tdata({data_h, data_l}),
.m_axis_tuser({user_h, user_l}),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast)
);
end else begin
axis_bitonic_comp #(
.DATA_WIDTH(DATA_WIDTH),
.USER_WIDTH(USER_WIDTH),
.POLARITY(POLARITY),
.SIGNED(SIGNED)
) abc_inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tdata({data_b, data_a}),
.s_axis_tuser({user_b, user_a}),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(s_axis_tlast),
.m_axis_tdata({data_h, data_l}),
.m_axis_tuser({user_h, user_l}),
.m_axis_tvalid(),
.m_axis_tready(m_axis_tready),
.m_axis_tlast()
);
end
end
endgenerate
endmodule
| 7.872602 |
module axis_bram_reader #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10,
parameter CONTINUOUS = "FALSE"
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
input wire m_axis_config_tready,
output wire m_axis_config_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg int_enbl_reg, int_enbl_next;
reg int_conf_reg, int_conf_next;
wire [BRAM_ADDR_WIDTH-1:0] sum_cntr_wire;
wire int_comp_wire, int_tlast_wire;
always @(posedge aclk) begin
if (~aresetn) begin
int_addr_reg <= {(BRAM_ADDR_WIDTH) {1'b0}};
int_enbl_reg <= 1'b0;
int_conf_reg <= 1'b0;
end else begin
int_addr_reg <= int_addr_next;
int_enbl_reg <= int_enbl_next;
int_conf_reg <= int_conf_next;
end
end
assign sum_cntr_wire = int_addr_reg + 1'b1;
assign int_comp_wire = int_addr_reg < cfg_data;
assign int_tlast_wire = ~int_comp_wire;
generate
if (CONTINUOUS == "TRUE") begin : CONTINUOUS
always @* begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if (~int_enbl_reg & int_comp_wire) begin
int_enbl_next = 1'b1;
end
if (m_axis_tready & int_enbl_reg & int_comp_wire) begin
int_addr_next = sum_cntr_wire;
end
if (m_axis_tready & int_enbl_reg & int_tlast_wire) begin
int_addr_next = {(BRAM_ADDR_WIDTH) {1'b0}};
end
end
end else begin : STOP
always @* begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
int_conf_next = int_conf_reg;
if (~int_enbl_reg & int_comp_wire) begin
int_enbl_next = 1'b1;
end
if (m_axis_tready & int_enbl_reg & int_comp_wire) begin
int_addr_next = sum_cntr_wire;
end
if (m_axis_tready & int_enbl_reg & int_tlast_wire) begin
int_enbl_next = 1'b0;
int_conf_next = 1'b1;
end
if (int_conf_reg & m_axis_config_tready) begin
int_conf_next = 1'b0;
end
end
end
endgenerate
assign sts_data = int_addr_reg;
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = int_enbl_reg;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
assign m_axis_config_tvalid = int_conf_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready & int_enbl_reg ? int_addr_next : int_addr_reg;
endmodule
| 6.708209 |
module axis_bram_writer #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [ BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [ BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH/8-1:0] bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_addr_reg <= {(BRAM_ADDR_WIDTH) {1'b0}};
int_enbl_reg <= 1'b0;
end else begin
int_addr_reg <= int_addr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @* begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if (~int_enbl_reg) begin
int_enbl_next = 1'b1;
end
if (s_axis_tvalid & int_enbl_reg) begin
int_addr_next = int_addr_reg + 1'b1;
end
end
assign sts_data = int_addr_reg;
assign s_axis_tready = int_enbl_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_addr_reg;
assign bram_porta_wrdata = s_axis_tdata;
assign bram_porta_we = {(BRAM_DATA_WIDTH / 8) {s_axis_tvalid & int_enbl_reg}};
endmodule
| 7.115728 |
module axis_cc_flow_ctrl (
input s_axis_clk,
input s_aresetn,
input s_axis_valid,
output s_axis_ready,
input m_axis_clk,
input m_aresetn,
output m_axis_valid,
input m_axis_ready
);
reg wa;
wire wb;
wire ra;
reg rb;
sync_reg s_to_m (
.clk(m_axis_clk),
.rst(~m_aresetn),
.in (wa),
.out(wb)
);
sync_reg m_to_s (
.clk(s_axis_clk),
.rst(~s_aresetn),
.in (rb),
.out(ra)
);
assign s_axis_ready = wa ^ ra ^ 1'b1;
assign m_axis_valid = wb ^ rb;
always @(posedge s_axis_clk) begin
if (~s_aresetn) begin
wa <= 1'b0;
end else if (s_axis_valid && s_axis_ready) begin
wa <= ~wa;
end
end
always @(posedge m_axis_clk) begin
if (~m_aresetn) begin
rb <= 1'b0;
end else if (m_axis_valid && m_axis_ready) begin
rb <= ~rb;
end
end
endmodule
| 7.543595 |
module axis_clock_converter_0 (
s_axis_aresetn,
m_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
s_axis_tuser,
m_axis_aclk,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
m_axis_tuser
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_RSTIF RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [127 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [15 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 16, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 33, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *)
input wire [32 : 0] s_axis_tuser;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_CLKIF CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [127 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [15 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 16, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 33, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *)
output wire [32 : 0] m_axis_tuser;
axis_clock_converter_v1_1_23_axis_clock_converter #(
.C_FAMILY("versal"),
.C_AXIS_TDATA_WIDTH(128),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(33),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000010011011),
.C_IS_ACLK_ASYNC(1),
.C_SYNCHRONIZER_STAGE(2),
.C_S_AXIS_ACLK_RATIO(1),
.C_M_AXIS_ACLK_RATIO(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_aclken(1'H1),
.m_axis_aclken(1'H1),
.s_axis_aclk(s_axis_aclk),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(16'HFFFF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(s_axis_tuser),
.m_axis_aclk(m_axis_aclk),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.595528 |
module axis_clock_converter_v1_1_23_axisc_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO - 1 : C_RATIO - 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *)reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY - 1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule
| 7.595528 |
module, you can! I only take care of this messy logic once.
And anyway, I'd like my cores to have conditional side channels anyway.
In the end, this module is noting more than wires, but it tricks Vivado into
doing what I want
Anyway, each side channel has an "in enable" and an "out enable". This means:
in | out | Meaning
------------------------------------
0 | d | The side channel is not present at the input
1 | 0 | The side channel is concatenated into output TDATA
1 | 0 | The side channel is present at input, but not concatenated
*/
/*
If you use this in another Verilog core and "pass up" the parameters to your
top-level core, add these TCL lines to your IP packaging script:
*/
`include "macros.vh"
/*
Unfortunately, due to problems with Vivado, I have to move all the
automatically derived parameters into macros instead of using localparam
Specifically, this happens because you can't use localparam to set a module's
port width, even if you use the K&R-style Verilog syntax:
module my_thing # (
parameter W = 2
) (a, b);
localparam WW = W+W;
input wire [W -1:0] a;
output wire [WW -1:0] b;
endmodule
| 6.556001 |
module axis_concat # (
parameter DATA_WIDTH = 32,
parameter IN_ENABLE_KEEP = 0,
parameter OUT_ENABLE_KEEP = 0,
parameter IN_ENABLE_LAST = 1,
parameter OUT_ENABLE_LAST = 1,
parameter IN_ENABLE_DEST = 0,
parameter OUT_ENABLE_DEST = 0,
parameter DEST_WIDTH = 16,
parameter IN_ENABLE_ID = 0,
parameter OUT_ENABLE_ID = 0,
parameter ID_WIDTH = 16,
parameter IN_ENABLE_USER = 0,
parameter OUT_ENABLE_USER = 0,
parameter USER_WIDTH = 16
) (
input wire clk, //Dummy clock to get rid of Vivado's annoying warning
input wire [DATA_WIDTH -1:0] left_TDATA,
input wire left_TVALID,
output wire left_TREADY,
input wire left_TLAST,
input wire [`IN_SAFE_KEEP_WIDTH -1:0] left_TKEEP,
input wire [`IN_SAFE_DEST_WIDTH -1:0] left_TDEST,
input wire [`IN_SAFE_ID_WIDTH -1:0] left_TID,
input wire [`IN_SAFE_USER_WIDTH -1:0] left_TUSER,
output wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
+ `CONCAT_KEEP_WIDTH
+ `CONCAT_DEST_WIDTH
+ `CONCAT_ID_WIDTH
+ `CONCAT_USER_WIDTH
-1:0] right_TDATA,
output wire right_TVALID,
input wire right_TREADY,
output wire right_TLAST,
output wire [`OUT_SAFE_KEEP_WIDTH -1:0] right_TKEEP,
output wire [`OUT_SAFE_DEST_WIDTH -1:0] right_TDEST,
output wire [`OUT_SAFE_ID_WIDTH -1:0] right_TID,
output wire [`OUT_SAFE_USER_WIDTH -1:0] right_TUSER
);
wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
-1:0] tmp_dl;
wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
+ `CONCAT_KEEP_WIDTH
-1:0] tmp_dlk;
wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
+ `CONCAT_KEEP_WIDTH
+ `CONCAT_DEST_WIDTH
-1:0] tmp_dlkd;
wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
+ `CONCAT_KEEP_WIDTH
+ `CONCAT_DEST_WIDTH
+ `CONCAT_ID_WIDTH
-1:0] tmp_dlkdi;
wire [DATA_WIDTH
+ `CONCAT_LAST_WIDTH
+ `CONCAT_KEEP_WIDTH
+ `CONCAT_DEST_WIDTH
+ `CONCAT_ID_WIDTH
+ `CONCAT_USER_WIDTH
-1:0] tmp_dlkdiu;
`genif (`CONCAT_LAST) begin
assign tmp_dl = {left_TDATA, left_TLAST};
`else_gen
assign tmp_dl = left_TDATA;
`endgen
`genif (`CONCAT_KEEP) begin
assign tmp_dlk = {tmp_dl, left_TKEEP};
`else_gen
assign tmp_dlk = tmp_dl;
`endgen
`genif (`CONCAT_DEST) begin
assign tmp_dlkd = {tmp_dlk, left_TDEST};
`else_gen
assign tmp_dlkd = tmp_dlk;
`endgen
`genif (`CONCAT_ID) begin
assign tmp_dlkdi = {tmp_dlkd, left_TID};
`else_gen
assign tmp_dlkdi = tmp_dlkd;
`endgen
`genif (`CONCAT_USER) begin
assign tmp_dlkdiu = {tmp_dlkdi, left_TUSER};
`else_gen
assign tmp_dlkdiu = tmp_dlkdi;
`endgen
assign right_TDATA = tmp_dlkdiu;
assign right_TVALID = left_TVALID;
assign left_TREADY = right_TREADY;
`genif (`PASSTHRU_LAST) begin
assign right_TLAST = left_TLAST;
`endgen
`genif (`PASSTHRU_KEEP) begin
assign right_TKEEP = left_TKEEP;
`endgen
`genif (`PASSTHRU_DEST) begin
assign right_TDEST = left_TDEST;
`endgen
`genif (`PASSTHRU_ID) begin
assign right_TID = left_TID;
`endgen
`genif (`PASSTHRU_USER) begin
assign right_TUSER = left_TUSER;
`endgen
endmodule
| 6.859422 |
module axis_conform_check #(
parameter tkeep_encoded = 0,
parameter axis_data_width = 256,
parameter axis_tkeep_width = axis_data_width / 8, // 32 bit
parameter axis_tkeep_encoded_width = $clog2(axis_tkeep_width), // 5 bit
parameter max_packet_size_counter = 65535,
parameter min_packet_size = 33, // in bytes
parameter max_packet_size = 9500 // in bytes
) (
input wire clk,
input wire reset,
input wire [ axis_tkeep_width-1:0] axis_tkeep,
input wire [axis_tkeep_encoded_width-1:0] axis_tkeep_encoded,
input wire axis_tlast,
input wire axis_tvalid,
input wire axis_tready,
output reg error,
output axis_conform_check_pkg::axi_errors_t error_vec
);
reg [$clog2(max_packet_size_counter+1)-1:0] packet_length;
reg [axis_tkeep_encoded_width:0] axis_tkeep_encoded_internal; // one bit wider than axis_tkeep_encoded (we count from 0 to 32)
generate
if (tkeep_encoded) begin
assign axis_tkeep_encoded_internal = axis_tkeep_encoded + 1;
end else begin
always_comb begin
axis_tkeep_encoded_internal = 0;
for (int i = 0; i < axis_tkeep_width; i++) begin
if (axis_tkeep[i] == 1'b1) axis_tkeep_encoded_internal++;
end
end
end
endgenerate
assign error = |error_vec;
logic last_axis_tvalid, last_axis_tready, last_reset;
always_ff @(posedge clk) begin
error_vec <= '0;
last_axis_tvalid <= axis_tvalid;
last_axis_tready <= axis_tready;
last_reset <= reset;
if (reset) begin
packet_length <= 0;
end else begin
if (axis_tvalid & axis_tready) begin
if (~axis_tlast) begin
if (packet_length < max_packet_size_counter - axis_tkeep_width)
packet_length <= packet_length + axis_tkeep_encoded_internal;
if (axis_tkeep_encoded_internal != axis_tkeep_width)
error_vec.packet_tkeep_not_continuous <= 1'b1;
end else begin
if (packet_length + axis_tkeep_encoded_internal < min_packet_size) begin
error_vec.packet_too_small <= 1'b1;
end
if (packet_length + axis_tkeep_encoded_internal > max_packet_size) begin
error_vec.packet_too_big <= 1'b1;
end
packet_length <= 0;
end
if (tkeep_encoded == 0) begin
for (int i = 0; i < axis_tkeep_width; i++) begin
if (axis_tkeep[i] == 1'b0) begin // found a zero => only zeros may follow
for (int j = i + 1; j < axis_tkeep_width; j++) begin
if (axis_tkeep[j] == 1'b1) error_vec.packet_tkeep_encoded_wrong <= 1'b1;
end
break;
end
end
end
if (~last_reset & ~axis_tvalid & last_axis_tvalid & ~last_axis_tready) begin
error_vec.packet_tvalid_deasserted <= 1'b1;
end
end
end
end
endmodule
| 6.932312 |
module axis_constant #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
assign m_axis_tdata = cfg_data;
assign m_axis_tvalid = 1'b1;
endmodule
| 6.777424 |
module axis_control_if #(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
) (
// Ports of Axi Master Bus Interface m_axis
input m_axis_txd_tvalid,
input m_axis_txd_tlast,
input m_axis_txd_tready,
input [11:0] tx_pkt_byte_cnt,
input tx_pkt_byte_cnt_vld,
input s_axis_rxs_aclk,
input s_axis_rxs_aresetn,
output s_axis_rxs_tready,
input [ C_S_AXIS_RXS_TDATA_WIDTH-1 : 0] s_axis_rxs_tdata,
input [(C_S_AXIS_RXS_TDATA_WIDTH/8)-1 : 0] s_axis_rxs_tkeep,
input s_axis_rxs_tlast,
input s_axis_rxs_tvalid,
input m_axis_txc_aclk,
input m_axis_txc_aresetn,
output reg m_axis_txc_tvalid,
output reg [ C_M_AXIS_TXC_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output reg [(C_M_AXIS_TXC_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
input m_axis_txc_tready
);
reg [2:0] tx_ctrl_state;
localparam WAIT_FOR_REQ = 1, SEND_CTRL_PKTS = 2, WAIT_FOR_NXT = 4;
reg [7:0] send_ctrl_words;
localparam WORD0 = 1, WORD1 = 2, WORD2 = 4, WORD3 = 8, WORD4 = 16, WORD5 = 32;
assign s_axis_rxs_tready = 1'b1;
reg len_fifo_rd_en;
wire [11:0] len_fifo_dout;
generate
if (ENABLE_LEN) begin
small_fifo #(
.WIDTH(12),
.MAX_DEPTH_BITS(5)
) pkt_len_fifo (
.clk(m_axis_txc_aclk),
.reset(!m_axis_txc_aresetn),
.din(tx_pkt_byte_cnt),
.wr_en(tx_pkt_byte_cnt_vld),
.rd_en(len_fifo_rd_en),
.dout(len_fifo_dout),
.full(),
.prog_full(),
.nearly_full(),
.empty()
);
end else begin
assign len_fifo_dout = 12'hFFF;
end
endgenerate
always @(posedge m_axis_txc_aclk)
if (!m_axis_txc_aresetn) len_fifo_rd_en <= 1'b0;
else if (tx_pkt_byte_cnt_vld) len_fifo_rd_en <= 1'b1;
else len_fifo_rd_en <= 0;
always @(posedge m_axis_txc_aclk)
if (!m_axis_txc_aresetn) begin
tx_ctrl_state <= WAIT_FOR_REQ;
send_ctrl_words <= WORD0;
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= 32'hFF_FF_FF_FF;
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
end else begin
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= {24'h50000, len_fifo_dout};
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
case (tx_ctrl_state)
WAIT_FOR_REQ: begin
if (m_axis_txd_tvalid) begin
m_axis_txc_tvalid <= 1'b1;
tx_ctrl_state <= SEND_CTRL_PKTS;
end
end
SEND_CTRL_PKTS: begin
m_axis_txc_tvalid <= 1'b1;
if (m_axis_txc_tready) begin
case (send_ctrl_words)
WORD0: send_ctrl_words <= WORD1;
WORD1: send_ctrl_words <= WORD2;
WORD2: send_ctrl_words <= WORD3;
WORD3: send_ctrl_words <= WORD4;
WORD4: begin
send_ctrl_words <= WORD0;
m_axis_txc_tlast <= 1'b1;
tx_ctrl_state <= WAIT_FOR_NXT;
end
endcase
end
end
WAIT_FOR_NXT: begin
if (m_axis_txd_tready && m_axis_txd_tlast) tx_ctrl_state <= WAIT_FOR_REQ;
end
default: tx_ctrl_state <= WAIT_FOR_REQ;
endcase
end
endmodule
| 8.842868 |
module axis_cpu_tb # (
parameter CODE_ADDR_WIDTH = 10,
parameter REG_ADDR_WIDTH = 4, //Seems good enough
parameter CPU_ID_WIDTH = 12,
parameter [CPU_ID_WIDTH-1:0] CPU_ID = 0, //Basically like a base address, used for AXIS register map
parameter PESS = 0
);
reg clk = 0;
reg rst = 0;
//Interface to outside world
`sim_in_axis_l(din, 32);
`sim_out_axis_l(dout, 32);
//Programming ports
reg [31:0] cmd_in_TDATA;
reg cmd_in_TVALID;
wire [31:0] cmd_out_TDATA;
wire cmd_out_TVALID;
//Debug ports
`sim_out_axis(to_guv, 80);
`sim_in_axis(from_guv, 80);
`auto_tb_decls;
initial begin
$dumpfile("axis_cpu.vcd");
$dumpvars;
$dumplimit(512000);
`open_drivers_file("axis_cpu_drivers.mem");
//Just to prevent simulation going forever
#10000
$display("Simulation timeout");
$finish;
end
always #5 clk <= ~clk;
`auto_tb_read_loop(clk)
`dummy = $fscanf(`fd, "%h%b%d%b%b%b%d%b%b%b",
cmd_in_TDATA,
cmd_in_TVALID,
din_TDATA,
din_TVALID,
din_TREADY_exp,
din_TLAST,
dout_TDATA_exp,
dout_TVALID_exp,
dout_TREADY,
dout_TLAST_exp
);
`auto_tb_read_end
`auto_tb_test_loop(clk)
`test(din_TREADY, din_TREADY_exp);
`test(dout_TVALID, dout_TVALID_exp);
if (`axis_flit(dout)) begin
`test(dout_TDATA, dout_TDATA_exp);
`test(dout_TLAST, dout_TLAST_exp);
end
`auto_tb_test_end
axis_cpu # (
.CODE_ADDR_WIDTH(CODE_ADDR_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.CPU_ID_WIDTH(CPU_ID_WIDTH),
.CPU_ID(0),
.PESS(PESS)
) DUT (
.clk(clk),
.rst(rst),
//Interface to outside world
`inst_axis_l(din, din),
`inst_axis_l(dout, dout),
//Programming ports
.cmd_in_TDATA(cmd_in_TDATA),
.cmd_in_TVALID(cmd_in_TVALID),
.cmd_out_TDATA(cmd_out_TDATA),
.cmd_out_TVALID(cmd_out_TVALID),
//Debug ports
`inst_axis(to_guv, to_guv),
`inst_axis(from_guv, from_guv)
);
endmodule
| 7.979105 |
module axis_ctrlport_reg #(
parameter ADDR = 0,
parameter USE_ADDR_LAST = 0,
parameter ADDR_LAST = ADDR + 1,
parameter DWIDTH = 32,
parameter USE_FIFO = 0,
parameter FIFm_SIZE = 5,
parameter DATA_AT_RESET = 0,
parameter VALID_AT_RESET = 0,
parameter LAST_AT_RESET = 0
) (
input clk,
input reset,
//---------------------------------------------------------------------------
// Control Port
//---------------------------------------------------------------------------
// Control Port Slave (Request)
input wire s_ctrlport_req_wr,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Control Port Slave (Response)
output reg s_ctrlport_resp_ack,
//---------------------------------------------------------------------------
// AXI-Stream Master
//---------------------------------------------------------------------------
// AXI-Stream Output
output [DWIDTH-1:0] m_tdata,
output m_tlast,
output m_tvalid,
input m_tready
);
reg [DWIDTH-1:0] m_tdata_int = DATA_AT_RESET;
reg m_tlast_int = VALID_AT_RESET;
reg m_tvalid_int = LAST_AT_RESET;
wire m_tready_int;
//---------------------------------------------------------------------------
// CtrlPort to AXI-Stream Logic
//---------------------------------------------------------------------------
always @(posedge clk) begin
if (reset) begin
m_tdata_int <= DATA_AT_RESET;
m_tvalid_int <= VALID_AT_RESET;
m_tlast_int <= LAST_AT_RESET;
s_ctrlport_resp_ack <= 1'b0;
end else begin
if (m_tvalid_int & m_tready_int) begin
s_ctrlport_resp_ack <= 1'b1;
m_tvalid_int <= 1'b0;
m_tlast_int <= 1'b0;
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
if (s_ctrlport_req_wr) begin
if (s_ctrlport_req_addr == ADDR) begin
m_tdata_int <= s_ctrlport_req_data;
m_tvalid_int <= 1'b1;
m_tlast_int <= 1'b0;
end else if (USE_ADDR_LAST && ADDR_LAST == s_ctrlport_req_addr) begin
m_tdata_int <= s_ctrlport_req_data;
m_tvalid_int <= 1'b1;
m_tlast_int <= 1'b1;
end
end
end
end
//---------------------------------------------------------------------------
// Output FIFO
//---------------------------------------------------------------------------
if (USE_FIFO) begin : gen_fifo
axi_fifo #(
.DWIDTH(DWIDTH + 1),
.SIZE (FIFm_SIZE)
) axi_fifo (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata ({m_tlast_int, m_tdata_int}),
.i_tvalid(m_tvalid_int),
.i_tready(m_tready_int),
.o_tdata ({m_tlast, m_tdata}),
.o_tvalid(m_tvalid),
.o_tready(m_tready),
.space (),
.occupied()
);
end else begin : nm_gen_fifo
assign m_tdata = m_tdata_int;
assign m_tlast = m_tlast_int;
assign m_tvalid = m_tvalid_int;
assign m_tready_int = m_tready;
end
endmodule
| 6.881535 |
module Axis_Ctrl_20BitWidth (
Clk,
gRst,
Addr,
MCUportL,
WR,
CS,
Din,
PosLock,
Ref,
Protect,
MO,
nStanby,
DRVRst,
PlsOut,
Dir,
Torque1,
Torque2,
DQtoMCU
);
/*
Axis_Ctrl Axis_Ctrl(
.Clk(),
.gRst(),
.Addr(),
.MCUportL(),
.WR(),
.CS(),
.Din(),
.PosLock(),
.Ref(),
.Protect(),
.MO(),
.nStanby(),
.DRVRst(),
.PlsOut(),
.Dir(),
.DQtoMCU()
);
*/
input Clk;
input gRst;
input [7:0] Addr;
input [15:0] MCUportL;
input WR;
input CS;
input [7:0] Din;
input PosLock;
input Ref;
input Protect;
input MO;
output nStanby;
output DRVRst;
output PlsOut;
output Dir;
output Torque1, Torque2;
output [7:0] DQtoMCU;
wire [15:0] AxisStateCmd;
wire [ 7:0] AxisPlsCmd;
wire [ 7:0] SpeedCmd;
wire [15:0] RefPos;
assign Torque1 = AxisStateCmd[0];
assign Torque2 = AxisStateCmd[1];
assign DirRev = AxisStateCmd[2];
assign DirCmd = AxisStateCmd[3];
wire Dir = ((~DirCmd) & DirRev) | ((DirCmd) & (~DirRev)); //xor ,ߵƽЧ
assign nStanby = AxisStateCmd[4]; //رоƬʡģʽ
assign DRVRst = AxisStateCmd[5]; //رоƬλ
assign RefEn_MCU = AxisStateCmd[8];
assign PlsClr = AxisPlsCmd[0];
assign StepPls = AxisPlsCmd[1];
assign RefClr = AxisPlsCmd[2];
wire SpeedSet;
wire SpeedSetDone;
wire WR_CS = WR | CS;
Axis_WR Axis_WR (
.Clk(WR_CS),
.Addr(Addr),
.MCUportL(MCUportL),
.Din(Din),
.SpeedSetDone(SpeedSetDone),
.SpeedSet(SpeedSet),
.AxisStateCmd(AxisStateCmd),
.AxisPlsCmd(AxisPlsCmd),
.SpeedCmd(SpeedCmd),
.RefPos(RefPos)
);
reg [19:0] PlsCnt;
reg RefDone;
wire [7:0] AxisState = {4'h0, Ref, RefDone, Protect, MO};
wire Continuepls;
assign PlsOut = StepPls | Continuepls;
Axis_RD Axis_RD (
.PClk(Continuepls),
.Addr(Addr),
.PosLock(PosLock),
.PlsCnt(PlsCnt[19:4]),
.Axis(AxisState),
.Din(Din),
.DQ(DQtoMCU)
);
PlsMaker PlsMaker (
.Clk(Clk),
.gRst(gRst),
// .DirCmd(DirCmd),
.SpeedCmd(SpeedCmd),
.SpeedSet(SpeedSet),
.SpeedSetDone(SpeedSetDone),
// .RefClr(RefClr),
// .PlsClr(PlsClr),
// .Ref(Ref),
// .RefPos(RefPos),
// .RefEn(RefEn_MCU),
.Pls_Out(Continuepls)
// .PlsCnt(PlsCnt),
// .RefDone(RefDone)
);
reg Ref0;
reg Ref1;
reg Refpls;
always @(posedge Clk) begin
Ref0 <= Ref;
Ref1 <= Ref0;
end
wire RefEn = (~RefDone) & RefEn_MCU;
always @(posedge Clk) begin
if (RefEn) Refpls <= (~Ref0) & Ref1;
else Refpls <= 1'b0;
end
wire RefDoneClr = gRst | RefClr;
always @(posedge RefDoneClr or posedge Refpls) begin
if (RefDoneClr) RefDone <= 1'b0;
else RefDone <= 1'b1;
end
wire PlsCntClr = PlsClr | gRst | Refpls;
always @(posedge Continuepls or posedge PlsCntClr) begin
if (PlsCntClr) PlsCnt <= 20'h0;
else if (DirCmd) PlsCnt <= PlsCnt + 1'b1;
else PlsCnt <= PlsCnt - 1'b1;
end
endmodule
| 6.586427 |
module axis_dac (
input wire clk,
input wire rst,
input wire [7:0] s_axis_tdata,
input wire s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tid,
input wire s_axis_tdest,
input wire s_axis_tuser,
output wire dac_out
);
wire [7:0] dac_data;
reg [7:0] dac_data_reg = 8'd0;
reg [7:0] dac_data_reg_r2 = 8'd0;
reg [7:0] dac_data_reg_r3 = 8'd0;
reg [9:0] divider_48k = 10'd0;
reg sample_tick = 1'b0;
always @(posedge clk) begin
sample_tick <= 1'b0;
divider_48k <= divider_48k + 10'd1;
if (divider_48k == 10'd999) begin
sample_tick <= 1'b1;
divider_48k <= 10'd0;
end
end
axis_fifo #(
.DEPTH(512), // TODO: Actual depth to be rounded up to BRAM size
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
) udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(dac_data),
.m_axis_tkeep(),
.m_axis_tvalid(),
.m_axis_tready(sample_tick),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow (),
.status_bad_frame (),
.status_good_frame()
);
always @(posedge clk) begin
dac_data_reg <= dac_data;
dac_data_reg_r3 <= dac_data_reg_r2;
if (sample_tick) begin
dac_data_reg_r2 <= dac_data_reg;
end
end
wire [7:0] signal_48M;
interpolator_1000x u_interpolator_1000x (
.clk(clk),
.rst(rst),
.signal_x0 (dac_data_reg_r3),
.signal_x1 (dac_data_reg),
.signal_48M(signal_48M)
);
/*
sddac inst_sddac (
.clk(clk),
.rst(rst),
.sig_in(signal_48M),
.sd_out(dac_out)
);
*/
/*
so_pdm inst_dac (
.i_clk(clk),
.i_res(1'b0),
.i_ce(1'b1),
.i_func(dac_data_reg),
.o_DAC(dac_out)
);
*/
pdm inst_dac (
.clk(clk),
.reset(rst),
.sample(signal_48M),
.dac_out(dac_out)
);
endmodule
| 6.860268 |
module axis_delay #(
parameter DELAY_WIDTH = 9 //Delay counter width
) (
input clk, //i-1
input reset_, //i-1
//AXIS Bus In
input axis_m_tvalid, //i-1, Valid signal from master
input axis_m_tlast, //i-1, Last signal from master
output axis_m_tready, //o-1, Ready signal to master
//AXIS Bus Out
output axis_s_tvalid, //o-1, Valid signal to slave
input axis_s_tready, //i-1, Ready signal from slave
//Control IO
input enable, //i-1, Enable the delay unit
input mode, //i-1, If asserted, delay triggers on valid/last, otherwise ready
input [DELAY_WIDTH-1:0] delay, //i-DELAY_WIDTH, Delay time in cycles
output active, //o-1, Asserted while the delay is currently active
//Debug
output test //o-1 debug
);
//================================================================//
// Internal Signals
reg [DELAY_WIDTH-1:0] counter;
reg trigger;
assign axis_m_tready = axis_s_tready && (counter == 0);
assign axis_s_tvalid = axis_m_tvalid && (counter == 0);
assign active = (counter > 0);
//Debug signal
assign test = 1'b0;
//================================================================//
// Register Logic
always @(posedge clk) begin
if (!reset_) begin
counter <= 'b0;
end else if (enable) begin
counter <= (trigger) ? delay : (counter > 0) ? counter - 1 : counter;
end
end
reg axis_m_tvalid_dly;
reg axis_m_tlast_dly;
reg axis_s_tready_dly;
always @(posedge clk) begin
axis_m_tvalid_dly <= axis_m_tvalid;
axis_m_tlast_dly <= axis_m_tlast;
axis_s_tready_dly <= axis_s_tready;
end
always @(negedge clk) begin
trigger <= (!reset_) ? 1'b0 :
(trigger) ? 1'b0 :
(enable) ? (
(mode) ? (axis_m_tvalid_dly & !axis_m_tvalid) | (axis_m_tlast_dly & !axis_m_tlast) :
(axis_s_tready_dly & !axis_s_tready)
):
1'b0;
end
endmodule
| 8.036454 |
module that narrows the input
// sample with by a factor of RATIO.
// NOTE: This module has end-to-end combanitorial paths. For a
// pipelined version, please use axis_width_conv
//
// Parameters:
// - OUT_DATA_W: The bitwidth of the output data bus. The width of the
// input data bus is OUT_DATA_W*RATIO
// - OUT_USER_W: The bitwidth of the output user bus. The width of the
// input user bus is OUT_USER_W*RATIO
// - RATIO: The downsizing ratio
//
// Signals:
// - s_axis_* : Input sample stream (AXI-Stream)
// - m_axis_* : Output sample stream (AXI-Stream)
module axis_downsizer #(
parameter OUT_DATA_W = 32,
parameter OUT_USER_W = 1,
parameter RATIO = 4
)(
// Clock, reset and settings
input wire clk, // Clock
input wire reset, // Reset
// Data In (AXI-Stream)
input wire [(OUT_DATA_W*RATIO)-1:0] s_axis_tdata, // Input stream tdata
input wire [(OUT_USER_W*RATIO)-1:0] s_axis_tuser, // Input stream tuser
input wire [RATIO-1:0] s_axis_tkeep, // Input stream tkeep
input wire s_axis_tlast, // Input stream tlast
input wire s_axis_tvalid, // Input stream tvalid
output wire s_axis_tready, // Input stream tready
// Data Out (AXI-Stream)
output wire [OUT_DATA_W-1:0] m_axis_tdata, // Output stream tdata
output wire [OUT_USER_W-1:0] m_axis_tuser, // Output stream tuser
output wire m_axis_tlast, // Output stream tlast
output wire m_axis_tvalid, // Output stream tvalid
input wire m_axis_tready // Output stream tready
);
genvar i;
generate if (RATIO != 1) begin
// Constants
localparam [$clog2(RATIO)-1:0] SEL_FIRST = 'd0;
localparam [$clog2(RATIO)-1:0] SEL_LAST = RATIO-1;
localparam [RATIO-1:0] KEEP_FIRST = {{(RATIO-1){1'b0}}, 1'b1};
localparam [RATIO-1:0] KEEP_ALL = {(RATIO){1'b1}};
// Keep a binary-coded and one-hot version of the current
// section of the input that is being processed.
reg [$clog2(RATIO)-1:0] select = SEL_FIRST;
reg [RATIO-1:0] keep = KEEP_FIRST;
// State machine to drive the select bits for the
// input selection MUX.
always @(posedge clk) begin
if (reset) begin
select <= SEL_FIRST;
keep <= KEEP_FIRST;
end else if (m_axis_tvalid & m_axis_tready) begin
select <= (select == SEL_LAST || m_axis_tlast) ? SEL_FIRST : (select + 'd1);
keep <= (keep == KEEP_ALL || m_axis_tlast) ? KEEP_FIRST : {keep[RATIO-2:0], 1'b1};
end
end
// The input selection MUX
wire [OUT_DATA_W-1:0] in_data[0:RATIO-1];
wire [OUT_USER_W-1:0] in_user[0:RATIO-1];
for (i = 0; i < RATIO; i=i+1) begin
assign in_data[i] = s_axis_tdata[i*OUT_DATA_W+:OUT_DATA_W];
assign in_user[i] = s_axis_tuser[i*OUT_USER_W+:OUT_USER_W];
end
assign m_axis_tdata = in_data[select];
assign m_axis_tuser = in_user[select];
assign m_axis_tlast = s_axis_tlast && (keep == s_axis_tkeep);
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tvalid && m_axis_tready && ((keep == KEEP_ALL) || m_axis_tlast);
end else begin // if (RATIO != 1)
// Passthrough
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tuser = s_axis_tuser;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
end endgenerate
endmodule
| 9.467984 |
module axis_dropper #(
parameter PORT_COUNT = 4,
parameter REG_FOR_DROP = 0,
parameter SAME_CYCLE_DROP = 0,
parameter DROP_CNT_WIDTH = 32
) (
input wire clk,
input wire rst,
input wire [ PORT_COUNT-1:0] drop,
output reg [PORT_COUNT*DROP_CNT_WIDTH-1:0] drop_count,
input wire [PORT_COUNT-1:0] s_axis_tvalid,
input wire [PORT_COUNT-1:0] s_axis_tlast,
output wire [PORT_COUNT-1:0] s_axis_tready,
output wire [PORT_COUNT-1:0] m_axis_tvalid,
output wire [PORT_COUNT-1:0] m_axis_tlast,
input wire [PORT_COUNT-1:0] m_axis_tready
);
// Register drop input if necessary
reg [PORT_COUNT-1:0] drop_r;
generate
if (REG_FOR_DROP) begin
always @(posedge clk)
if (rst) drop_r <= {PORT_COUNT{1'b0}};
else drop_r <= drop;
end else begin
always @(*) drop_r = drop;
end
endgenerate
// Detect Start of Packet or idle
reg [PORT_COUNT-1:0] SoP;
// Register to keep dropping state
reg [PORT_COUNT-1:0] dropping;
integer i;
wire [PORT_COUNT-1:0] s_axis_transaction = s_axis_tvalid & s_axis_tready;
always @(posedge clk)
if (rst) begin
SoP <= {PORT_COUNT{1'b1}};
dropping <= {PORT_COUNT{1'b0}};
end else begin
for (i = 0; i < PORT_COUNT; i = i + 1) begin
if (s_axis_transaction[i]) // If there was a transaction
SoP[i] <= s_axis_tlast[i]; // SoP becomes 1 only after tlast
// When drop is asserted, if we have SAME_CYCLE_DROP, on IDLE or actual SoP
// we start dropping, and if its in the middle of a packet we wait for tlast.
// If we ignore corner case of drop signal being asserted at the same cycle
// as SoP, we start dropping when IDLE or wait for tlast.
if (drop_r[i] && !dropping[i])
dropping[i] <= SAME_CYCLE_DROP ?
(SoP[i] || (s_axis_transaction[i] && s_axis_tlast[i])):
((SoP[i] && !s_axis_tvalid[i]) || (s_axis_transaction[i] && s_axis_tlast[i]));
// When drop is deasserted while dropping is set, if we have SAME_CYCLE_DROP,
// either SoP, IDLE or tlast would deasserted the dropping. If we ignore the
// corner case, only tlast or idle deasserts the dropping.
else if (!drop_r[i] && dropping[i])
dropping[i] <= SAME_CYCLE_DROP ?
!(SoP[i] || (s_axis_transaction[i] && s_axis_tlast[i])):
!((SoP[i] && !s_axis_tvalid[i]) || (s_axis_transaction[i] && s_axis_tlast[i]));
end
end //READY!
// Combinational logic for the outputs.
// If we have SAME_CYCLE_DROP, if actual Stop and drop_r happen in the same cycle
// we drop, and if SoP and deassertion of drop_r happen in the same cycle we ignore
// the dropping register. In case of ignoring the corner case of same cycle, we
// simply use the dropping register.
wire [PORT_COUNT-1:0] to_drop = SAME_CYCLE_DROP ?
(SoP & drop_r) | (dropping & ~(SoP & ~drop_r)) : dropping;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tvalid = s_axis_tvalid & ~to_drop;
assign s_axis_tready = m_axis_tready | to_drop;
integer j;
always @(posedge clk)
if (rst) drop_count <= {PORT_COUNT * DROP_CNT_WIDTH{1'b0}};
else
for (j = 0; j < PORT_COUNT; j = j + 1)
if (s_axis_transaction[j] && s_axis_tlast[j] && to_drop[j])
drop_count [j*DROP_CNT_WIDTH +: DROP_CNT_WIDTH] =
drop_count [j*DROP_CNT_WIDTH +: DROP_CNT_WIDTH] + 1;
endmodule
| 7.1209 |
module axis_endianness_converter #(
parameter DATA_WIDTH = 8,
parameter HAS_DATA = 1,
parameter HAS_KEEP = 0,
parameter HAS_LAST = 0,
parameter HAS_READY = 0,
parameter HAS_DEST = 0,
parameter HAS_USER = 0,
parameter HAS_ID = 0,
parameter HAS_STRB = 0,
parameter ID_WIDTH = 1,
parameter DEST_WIDTH = 1,
parameter USER_WIDTH = 1
) (
input wire clk,
input wire s_valid,
output wire s_ready,
input wire [DATA_WIDTH-1:0] s_data,
input wire [DATA_WIDTH/8-1:0] s_keep,
input wire s_last,
input wire [DEST_WIDTH-1:0] s_dest,
input wire [USER_WIDTH-1:0] s_user,
input wire [ID_WIDTH-1:0] s_id,
input wire [DATA_WIDTH/8-1:0] s_strb,
output wire m_valid,
input wire m_ready,
output wire [DATA_WIDTH-1:0] m_data,
output wire [DATA_WIDTH/8-1:0] m_keep,
output wire m_last,
output wire [DEST_WIDTH-1:0] m_dest,
output wire [USER_WIDTH-1:0] m_user,
output wire [ID_WIDTH-1:0] m_id,
output wire [DATA_WIDTH/8-1:0] m_strb
);
wire [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH/8-1:0] keep_in;
wire last_in;
wire [DEST_WIDTH-1:0] dest_in;
wire [USER_WIDTH-1:0] user_in;
wire [ID_WIDTH-1:0] id_in;
wire [DATA_WIDTH/8-1:0] strb_in;
genvar i;
generate
for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin : loop1
assign m_data[DATA_WIDTH-1-i*8:DATA_WIDTH-8-i*8] = data_in[i*8+7:i*8];
assign m_keep[DATA_WIDTH/8-1-i] = keep_in[i];
assign m_strb[DATA_WIDTH/8-1-i] = strb_in[i];
end
for (i = 0; i < DEST_WIDTH; i = i + 1) begin : loop2
assign m_dest[DEST_WIDTH-1-i] = dest_in[i];
end
for (i = 0; i < USER_WIDTH; i = i + 1) begin : loop3
assign m_user[USER_WIDTH-1-i] = user_in[i];
end
for (i = 0; i < ID_WIDTH; i = i + 1) begin : loop4
assign m_id[ID_WIDTH-1-i] = id_in[i];
end
endgenerate
assign m_valid = s_valid;
assign m_last = last_in;
assign s_ready = ready_in;
assign data_in = HAS_DATA ? s_data : {DATA_WIDTH{1'b0}};
assign keep_in = HAS_KEEP ? s_keep : {{DATA_WIDTH / 8} {1'b1}};
assign last_in = HAS_LAST ? s_last : 1'b1;
assign ready_in = HAS_READY ? m_ready : 1'b1;
assign dest_in = HAS_DEST ? s_dest : {DEST_WIDTH{1'b0}};
assign user_in = HAS_USER ? s_user : {USER_WIDTH{1'b0}};
assign id_in = HAS_ID ? s_id : {ID_WIDTH{1'b0}};
assign strb_in = HAS_STRB ? s_strb : {{DATA_WIDTH / 8} {1'b0}};
endmodule
| 7.098643 |
module axis_eth_fcs #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH / 8)
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* FCS output
*/
output wire [31:0] output_fcs,
output wire output_fcs_valid
);
// bus width assertions
initial begin
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] fcs_reg = 32'h00000000;
reg fcs_valid_reg = 1'b0;
wire [31:0] crc_next[KEEP_WIDTH-1:0];
assign s_axis_tready = 1;
assign output_fcs = fcs_reg;
assign output_fcs_valid = fcs_valid_reg;
generate
genvar n;
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin : crc
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH / KEEP_WIDTH * (n + 1)),
.STYLE("AUTO")
) eth_crc_inst (
.data_in (s_axis_tdata[DATA_WIDTH/KEEP_WIDTH*(n+1)-1:0]),
.state_in (crc_state),
.data_out (),
.state_out(crc_next[n])
);
end
endgenerate
integer i;
always @(posedge clk) begin
fcs_valid_reg <= 1'b0;
if (s_axis_tvalid) begin
crc_state <= crc_next[KEEP_WIDTH-1];
if (s_axis_tlast) begin
crc_state <= 32'hFFFFFFFF;
if (KEEP_ENABLE) begin
fcs_reg <= ~crc_next[0];
for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
if (s_axis_tkeep[i]) begin
fcs_reg <= ~crc_next[i];
end
end
end else begin
fcs_reg <= ~crc_next[KEEP_WIDTH-1];
end
fcs_valid_reg <= 1'b1;
end
end
if (rst) begin
crc_state <= 32'hFFFFFFFF;
fcs_valid_reg <= 1'b0;
end
end
endmodule
| 8.316486 |
module axis_fifo32 #(
parameter WIDTH = 32,
parameter DEEP_BITS = 5
) (
input clk,
input axisrst,
input [WIDTH-1:0] axis_rx_tdata,
input axis_rx_tvalid,
output axis_rx_tready,
output [WIDTH-1:0] axis_tx_tdata,
output axis_tx_tvalid,
input axis_tx_tready,
output [DEEP_BITS-1:0] fifo_used,
output reg fifo_empty
);
reg [DEEP_BITS-1:0] rpos;
assign fifo_used = rpos;
localparam FIFO_FULL = ((1 << DEEP_BITS) - 1);
assign axis_tx_tvalid = (~fifo_empty);
assign axis_rx_tready = (rpos != FIFO_FULL);
wire fifo_wr_strobe = axis_rx_tvalid && axis_rx_tready;
wire fifo_rd_strobe = axis_tx_tvalid && axis_tx_tready;
`ifdef SYM
localparam MAX_DEEP = 1 << DEEP_BITS;
reg [WIDTH-1:0] fifo[MAX_DEEP - 1:0];
always @(posedge clk) begin
if (fifo_wr_strobe) begin
fifo[0] <= axis_rx_tdata;
end
end
generate
genvar i;
for (i = 1; i < MAX_DEEP; i = i + 1) begin : srl
always @(posedge clk) begin
if (fifo_wr_strobe) fifo[i] <= fifo[i-1];
end
end
endgenerate
assign axis_tx_tdata = fifo[rpos];
`else
genvar i;
generate
if (DEEP_BITS == 5) begin
for (i = 0; i < WIDTH; i = i + 1) begin : srl32
SRLC32E #(
.INIT(32'h00000000)
) fifo32 (
.CLK(clk),
.CE (fifo_wr_strobe),
.D (axis_rx_tdata[i]),
.A (rpos),
.Q (axis_tx_tdata[i]),
.Q31()
);
end
end else if (DEEP_BITS == 4) begin
for (i = 0; i < WIDTH; i = i + 1) begin : srl16
SRL16E #(
.INIT(16'h0000)
) fifo16 (
.CLK(clk),
.CE (fifo_wr_strobe),
.D (axis_rx_tdata[i]),
.A0 (rpos[0]),
.A1 (rpos[1]),
.A2 (rpos[2]),
.A3 (rpos[3]),
.Q (axis_tx_tdata[i])
);
end
end
endgenerate
`endif
always @(posedge clk) begin
if (axisrst) begin
fifo_empty <= 1;
rpos <= 0;
end else begin
if (fifo_wr_strobe && fifo_rd_strobe) begin
end else if (fifo_wr_strobe) begin
if (fifo_empty) fifo_empty <= 1'b0;
else rpos <= rpos + 1;
end else if (fifo_rd_strobe) begin
if (rpos == 0) fifo_empty <= 1'b1;
else rpos <= rpos - 1;
end
end
end
endmodule
| 6.843848 |
module axis_fifo_tb (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) bus1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
`ifdef VER1
wire [1:0] size2;
axis_fifo_ver1 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER2
wire [1:0] size2;
axis_fifo_ver2 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER3
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver3 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER4
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver4 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) bus2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size2 + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size2 == $past(size2
+ (ivalid && iready) - (ovalid && oready)));
// just to make induction proof work
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule
| 6.696043 |
module axis_file_loader #(
parameter filename = "data.bin",
parameter data_width = 8,
parameter delay_tic = 100
) (
input axis_aclk,
input axis_aresetn,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [8*data_width-1:0] m_axis_tdata,
output reg [data_width-1:0] m_axis_tkeep,
output m_axis_tlast,
input cfg_prepared
);
integer data_file = 0, rv, i = 0;
reg eof = 0;
reg [7:0] buffer;
reg [63:0] tdata_buf[0:1];
reg [7:0] tkeep_buf[0:1];
localparam IDLE = 0;
localparam WAIT = 1;
localparam OPEN_FILE = 2;
localparam XFER = 3;
localparam XFER_LAST = 4;
integer state;
always @(posedge axis_aclk) begin
if (!axis_aresetn) state <= IDLE;
else
case (state)
IDLE: state <= WAIT;
WAIT: if (delay_tic == tic) state <= OPEN_FILE;
OPEN_FILE: begin
data_file = $fopen(filename, "rb");
for (i = 0; i < data_width; i = i + 1) begin
rv = $fread(buffer, data_file);
if (rv == 1) begin
tkeep_buf[0][i] = 1;
tdata_buf[0][8*i+7-:8] = buffer;
end else begin
tkeep_buf[0][i] = 0;
tdata_buf[0][8*i+7-:8] = 0;
end
end
state <= XFER;
end
XFER: begin
for (i = 0; i < data_width; i = i + 1) begin
rv = $fread(buffer, data_file);
tdata_buf[0][8*i+7-:8] = buffer;
if (rv == 1) tkeep_buf[0][i] = 1;
else tkeep_buf[0][i] = 0;
end
if ($feof(data_file)) state <= XFER_LAST;
end
XFER_LAST: begin
state <= IDLE;
$fclose(data_file);
end
default: state <= IDLE;
endcase
end
reg [31:0] tic;
wire tic_enb = state == WAIT ? 1 : 0;
wire tic_clr = state == XFER ? 1 : 0;
always @(posedge axis_aclk) begin
if (!axis_aresetn || tic_clr) tic <= 0;
else if (tic_enb) tic <= tic + 1;
end
// initial begin
// data_file = $fopen(filename,"rb");
// @(posedge cfg_prepared);
// # delay_ns;
// @(posedge axis_aclk);
// while (!$feof(data_file)) begin
// @(posedge axis_aclk);
// state = XFER;
// tdata_buf[0] = 0;
// tkeep_buf[0] = 0;
// for (i = 0;i < data_width;i = i+1) begin
// rv = $fread(buffer,data_file);
// tdata_buf[0][8*i+7-:8] = buffer;
// if(rv == 1)
// tkeep_buf[0][i] = 1;
// end
// end
// state = XFER_LAST;
// @(posedge axis_aclk);
// state = IDLE;
// $fclose(data_file);
// end
assign m_axis_tlast = state == XFER_LAST ? 1 : 0;
wire output_enb = state == XFER || state == XFER_LAST;
always @(posedge axis_aclk) begin
if (!axis_aresetn) begin
m_axis_tdata <= 0;
m_axis_tkeep <= 0;
end else if (output_enb) begin
m_axis_tdata <= tdata_buf[1];
m_axis_tkeep <= tkeep_buf[1];
end
end
always @(posedge axis_aclk) begin
if (!axis_aresetn) begin
tdata_buf[1] <= 0;
tkeep_buf[1] <= 0;
m_axis_tvalid <= 0;
end else begin
tdata_buf[1] <= tdata_buf[0];
tkeep_buf[1] <= tkeep_buf[0];
m_axis_tvalid <= state == XFER ? 1 : 0;
end
end
endmodule
| 6.992658 |
module axis_file_loader_tb ();
reg clk = 0;
reg rst = 1;
wire rst_n;
reg cfg_prepared = 0;
assign rst_n = !rst;
axis_file_loader loader_inst (
.axis_aclk(clk),
.axis_aresetn(rst_n),
.m_axis_tvalid(),
.m_axis_tready(1'b1),
.m_axis_tdata(),
.m_axis_tkeep(),
.m_axis_tlast(),
.cfg_prepared(cfg_prepared)
);
always begin
#5 clk = !clk;
end
initial begin
#100 rst = !rst;
@(posedge clk);
cfg_prepared = 1;
@(posedge clk);
cfg_prepared = 0;
end
endmodule
| 6.992658 |
module AXIS_FIR_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 16,
// Parameters of Axi Master Bus Interface M_AXIS
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_START_COUNT = 32
) (
// Users to add ports here
input wire [3:0] s_axis_tkeep,
output wire [3:0] m_axis_tkeep,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXIS
input wire s_axis_aclk,
input wire s_axis_aresetn,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] s_axis_tdata,
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] s_axis_tstrb,
input wire s_axis_tlast,
input wire s_axis_tvalid,
// Ports of Axi Master Bus Interface M_AXIS
input wire m_axis_aclk,
input wire m_axis_aresetn,
output wire m_axis_tvalid,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] m_axis_tdata,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready
);
wire [C_S_AXIS_TDATA_WIDTH-1 : 0] fir_data_in;
wire [C_M_AXIS_TDATA_WIDTH-1 : 0] fir_data_out;
// Instantiation of Axi Bus Interface S_AXIS
AXIS_FIR_v1_0_S_AXIS #(
.C_S_AXIS_TDATA_WIDTH(C_S_AXIS_TDATA_WIDTH)
) AXIS_FIR_v1_0_S_AXIS_inst (
.s_axis_tkeep(s_axis_tkeep),
.enable_fir(enable_fir),
.fir_data_in(fir_data_in),
.S_AXIS_ACLK(s_axis_aclk),
.S_AXIS_ARESETN(s_axis_aresetn),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.S_AXIS_TSTRB(s_axis_tstrb),
.S_AXIS_TLAST(s_axis_tlast),
.S_AXIS_TVALID(s_axis_tvalid)
);
// Instantiation of Axi Bus Interface M_AXIS
AXIS_FIR_v1_0_M_AXIS #(
.C_M_AXIS_TDATA_WIDTH(C_M_AXIS_TDATA_WIDTH),
.C_M_START_COUNT(C_M_AXIS_START_COUNT)
) AXIS_FIR_v1_0_M_AXIS_inst (
.m_axis_tkeep(m_axis_tkeep),
.enable_fir(enable_fir),
.fir_data_out(fir_data_out),
.M_AXIS_ACLK(s_axis_aclk),
.M_AXIS_ARESETN(s_axis_aresetn),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TDATA(m_axis_tdata),
.M_AXIS_TSTRB(m_axis_tstrb),
.M_AXIS_TLAST(m_axis_tlast),
.M_AXIS_TREADY(m_axis_tready)
);
// Add user logic here
FIR LPF_FIR_inst (
.clk(s_axis_aclk),
.reset(s_axis_aresetn),
.enable_fir(enable_fir),
.fir_data_in(fir_data_in), //16
.fir_data_out(fir_data_out) //32
);
// User logic ends
endmodule
| 9.155316 |
module is an AXI Stream passthrough, but with options to modify the
underlying stream. Supported operations:
- Injecting flits
- Forcing ready to low (i.e. pausing)
- Copying flits to another interface (i.e. logging)
- Dropping flits (while potentially logging them)
This module is designed to be used inside of an FSM which can, among other
things, accept commands to allow single-stepping, running to a "breakpoint" or
"watchpoint", repackage logged streams to move the side channels into TDATA,
etc. For now I just wanted to simulate this.
This module requires 2 LUTs for the glue logic, and whatever LUTs/MUXes are
needed for the multiplexers at the output
*/
//TODO: Find out how to selectively disable certain side channels
//Default widths correspond to Galapagos defaults
module axis_governor #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 16,
parameter ID_WIDTH = 16
) (
input wire clk,
//Input AXI Stream.
input wire [DATA_WIDTH-1:0] in_TDATA,
input wire in_TVALID,
output wire in_TREADY,
input wire [DATA_WIDTH/8 -1:0] in_TKEEP,
input wire [DEST_WIDTH -1:0] in_TDEST,
input wire [ID_WIDTH -1:0] in_TID,
input wire in_TLAST,
//Inject AXI Stream.
input wire [DATA_WIDTH-1:0] inj_TDATA,
input wire inj_TVALID,
output wire inj_TREADY,
input wire [DATA_WIDTH/8 -1:0] inj_TKEEP,
input wire [DEST_WIDTH -1:0] inj_TDEST,
input wire [ID_WIDTH -1:0] inj_TID,
input wire inj_TLAST,
//Output AXI Stream.
output wire [DATA_WIDTH-1:0] out_TDATA,
output wire out_TVALID,
input wire out_TREADY,
output wire [DATA_WIDTH/8 -1:0] out_TKEEP,
output wire [DEST_WIDTH -1:0] out_TDEST,
output wire [ID_WIDTH -1:0] out_TID,
output wire out_TLAST,
//Log AXI Stream.
output wire [DATA_WIDTH-1:0] log_TDATA,
output wire log_TVALID,
input wire log_TREADY,
output wire [DATA_WIDTH/8 -1:0] log_TKEEP,
output wire [DEST_WIDTH -1:0] log_TDEST,
output wire [ID_WIDTH -1:0] log_TID,
output wire log_TLAST,
//Control signals
input wire pause,
input wire drop,
input wire log_en
//input wire inject //Not needed; this is determined from inj_TVALID
);
//Perform the tricky management of valids and readies.
//This module is defined lower down in this file
axis_governor_glue_log glue(
.in_vld(in_TVALID),
.out_rdy(out_TREADY),
.log_en(log_en),
.log_rdy(log_TREADY),
.inj_vld(inj_TVALID),
.pause(pause),
.drop(drop),
.in_rdy(in_TREADY),
.out_vld(out_TVALID),
.log_vld(log_TVALID),
.inj_rdy(inj_TREADY)
);
//Connect remaining AXI Stream signals
assign out_TDATA = inj_TVALID ? inj_TDATA : in_TDATA;
assign out_TKEEP = inj_TVALID ? inj_TKEEP : in_TKEEP;
assign out_TDEST = inj_TVALID ? inj_TDEST : in_TDEST;
assign out_TID = inj_TVALID ? inj_TID : in_TID;
assign out_TLAST = inj_TVALID ? inj_TLAST : in_TLAST;
assign log_TDATA = in_TDATA;
assign log_TKEEP = in_TKEEP;
assign log_TDEST = in_TDEST;
assign log_TID = in_TID;
assign log_TLAST = in_TLAST;
endmodule
| 8.350248 |
module axis_governor_glue_log (
input wire in_vld,
input wire out_rdy,
input wire log_en,
input wire log_rdy,
input wire inj_vld,
input wire pause,
input wire drop,
output wire in_rdy,
output wire out_vld,
output wire log_vld,
output wire inj_rdy
);
//(~inj_vld && out_rdy) means the slave is ready to receive a flit from the
//master. OR'ing this with drop means the slave (and injector) cannot
//backpressure the master if drop is high.
//
//(log_rdy || ~log_en) means that the logger is not backpressuring the
//master
//
//Finally, in_rd is forced low if we are paused
assign in_rdy = ~pause && (log_rdy || ~log_en) && (drop || (~inj_vld && out_rdy));
//If the injector has valid data, it takes precedence
//The other condition means that the master is trying to send something to
//the slave, and that the logger is not backpressuring the master
assign out_vld = inj_vld || (in_vld && ~drop && ~pause && (~log_en || log_rdy));
//Note: this next line is written this way to let Vivado synthesize the logic
//in simple LUTs. However, it is better understood as
//
//assign log_vld = log_en && in_vld && s_rdy;
//
//Also note that log_vld depends on log_rdy. Technically, this violates the
//AXI Stream specification. In order for this to work, you need to connect
//the log AXI Stream channel to a core which does not have a combinational
//path from ready to valid (a register slice, for example)
assign log_vld = log_en && ~pause && in_vld && (drop || (~inj_vld && out_rdy));
//At least this is simple...
assign inj_rdy = out_rdy;
endmodule
| 8.099137 |
module axis_gpio_reader #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
inout wire [AXIS_TDATA_WIDTH-1:0] gpio_data,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_data_reg [1:0];
wire [AXIS_TDATA_WIDTH-1:0] int_data_wire;
genvar j;
generate
for (j = 0; j < AXIS_TDATA_WIDTH; j = j + 1) begin : GPIO
IOBUF gpio_iobuf (
.O (int_data_wire[j]),
.IO(gpio_data[j]),
.I (1'b0),
.T (1'b1)
);
end
endgenerate
always @(posedge aclk) begin
int_data_reg[0] <= int_data_wire;
int_data_reg[1] <= int_data_reg[0];
end
assign m_axis_tdata = int_data_reg[1];
assign m_axis_tvalid = 1'b1;
endmodule
| 7.502314 |
module axis_headerizer # (
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 16,
parameter ID_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter RESET_TYPE = `NO_RESET,
parameter ENABLE_TLAST_HACK = 0
) (
input wire clk,
input wire rst,
`in_axis_kl(sides, DATA_WIDTH),
input wire [DEST_WIDTH -1:0] sides_TDEST,
input wire [ID_WIDTH -1:0] sides_TID,
input wire [USER_WIDTH -1:0] sides_TUSER,
`out_axis_kl(hdr, DATA_WIDTH)
);
`localparam WAIT_FIRST_VLD = 0;
`localparam WAIT_LAST = 1;
reg state = WAIT_FIRST_VLD;
`wire_rst_sig;
`genif (RESET_TYPE == `NO_RESET) begin
always @(posedge clk) begin
case (state)
WAIT_FIRST_VLD:
state <= `axis_flit(hdr) ? WAIT_LAST : WAIT_FIRST_VLD;
WAIT_LAST:
state <= `axis_last(hdr) ? WAIT_FIRST_VLD : WAIT_LAST;
endcase
end
`else_gen
always @(posedge clk) begin
if (rst_sig) begin
state <= WAIT_FIRST_VLD;
end else begin
case (state)
WAIT_FIRST_VLD:
state <= `axis_flit(hdr) ? WAIT_LAST : WAIT_FIRST_VLD;
WAIT_LAST:
state <= `axis_last(hdr) ? WAIT_FIRST_VLD : WAIT_LAST;
endcase
end
end
`endgen
//TODO: Parameterize which sidechannels are present?
`localparam PAD_WIDTH = DATA_WIDTH - (1 + DEST_WIDTH + ID_WIDTH + USER_WIDTH);
wire [DATA_WIDTH -1:0] header = {{PAD_WIDTH{1'b0}}, sides_TLAST, sides_TDEST, sides_TID, sides_TUSER};
assign hdr_TDATA = (state == WAIT_LAST) ? sides_TDATA : header;
assign hdr_TVALID = sides_TVALID;
assign sides_TREADY = (state == WAIT_LAST) && hdr_TREADY;
assign hdr_TKEEP = (state == WAIT_LAST) ? sides_TKEEP : {(DATA_WIDTH/8){1'b1}};
`genif (ENABLE_TLAST_HACK == 0) begin
assign hdr_TLAST = (state == WAIT_LAST) && sides_TLAST;
`else_gen
assign hdr_TLAST = (state == WAIT_LAST);
`endgen
endmodule
| 6.637668 |
module axis_headerizer_tb #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 16,
parameter ID_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter RESET_TYPE = `NO_RESET
);
reg clk = 0;
reg rst = 0;
`sim_in_axis_kl(sides, DATA_WIDTH);
reg [DEST_WIDTH -1:0] sides_TDEST = 0;
reg [ ID_WIDTH -1:0] sides_TID = 0;
reg [USER_WIDTH -1:0] sides_TUSER = 0;
`sim_out_axis_kl(hdr, DATA_WIDTH);
initial begin
$dumpfile("axis_headerizer.vcd");
$dumpvars;
$dumplimit(512000);
sides_TVALID <= 1;
#2000 $finish;
end
always #5 clk <= ~clk;
always @(posedge clk) begin
if (`axis_flit(sides)) begin
sides_TDATA <= sides_TDATA + 3; //Could have done +1, but +3 more interesting
sides_TKEEP <= $random;
sides_TLAST <= $random;
sides_TDEST <= $random;
sides_TID <= $random;
sides_TUSER <= $random;
end
end
axis_headerizer #(
.DATA_WIDTH(DATA_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.ID_WIDTH (ID_WIDTH),
.USER_WIDTH(USER_WIDTH),
.RESET_TYPE(RESET_TYPE)
) DUT (
.clk(clk),
.rst(rst),
`inst_axis_kl(sides, sides),
.sides_TDEST(sides_TDEST),
.sides_TID (sides_TID),
.sides_TUSER(sides_TUSER),
`inst_axis_kl(hdr, hdr)
);
endmodule
| 6.637668 |
module axis_histogram #(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 14
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
output wire bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [BRAM_DATA_WIDTH-1:0] int_data_reg, int_data_next;
reg [2:0] int_case_reg, int_case_next;
reg int_tready_reg, int_tready_next;
reg int_wren_reg, int_wren_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_addr_reg <= {(BRAM_ADDR_WIDTH) {1'b0}};
int_data_reg <= {(BRAM_DATA_WIDTH) {1'b0}};
int_case_reg <= 3'd0;
int_tready_reg <= 1'b0;
int_wren_reg <= 1'b0;
end else begin
int_addr_reg <= int_addr_next;
int_data_reg <= int_data_next;
int_case_reg <= int_case_next;
int_tready_reg <= int_tready_next;
int_wren_reg <= int_wren_next;
end
end
always @* begin
int_addr_next = int_addr_reg;
int_data_next = int_data_reg;
int_case_next = int_case_reg;
int_tready_next = int_tready_reg;
int_wren_next = int_wren_reg;
case (int_case_reg)
0: begin
int_addr_next = {(BRAM_ADDR_WIDTH) {1'b0}};
int_data_next = {(BRAM_DATA_WIDTH) {1'b0}};
int_wren_next = 1'b1;
int_case_next = 3'd1;
end
1: begin
// write zeros
int_addr_next = int_addr_reg + 1'b1;
if (&int_addr_reg) begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 3'd2;
end
end
2: begin
if (s_axis_tvalid) begin
int_addr_next = s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
int_tready_next = 1'b0;
int_case_next = 3'd3;
end
end
3: begin
int_case_next = 3'd4;
end
4: begin
int_data_next = bram_porta_rddata + 1'b1;
int_wren_next = ~&bram_porta_rddata;
int_case_next = 3'd5;
end
5: begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 3'd2;
end
endcase
end
assign s_axis_tready = int_tready_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_wren_reg ? int_addr_reg : s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
assign bram_porta_wrdata = int_data_reg;
assign bram_porta_we = int_wren_reg;
endmodule
| 7.368018 |
module is used along with axis_img_border_gen.v to
* to remove the image boarder from the stream.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* ----------------------------------------------------------------------------
*/
`default_nettype none
`timescale 1ps / 1ps
module axis_img_border_remover #
(
parameter BYPASS_BIT_MASK = 16'h4000
)
(
input wire axis_aclk,
input wire axis_aresetn,
input wire [15:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg s_axis_tready = 1'b0,
input wire s_axis_tlast,
input wire s_axis_tuser,
output reg [15:0] m_axis_tdata = {16{1'b0}},
output reg m_axis_tvalid = 1'b0,
input wire m_axis_tready,
output reg m_axis_tlast = 1'b0,
output reg m_axis_tuser = 1'b0
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST_RST = 2'd0,
ST_GET = 2'd1,
ST_SEND = 2'd2;
reg [1:0] state = ST_RST;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
s_axis_tready <= 1'b1;
m_axis_tvalid <= 1'b0;
state <= ST_GET;
end
ST_GET: begin
if (s_axis_tvalid && (s_axis_tdata & BYPASS_BIT_MASK)) begin
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b1;
m_axis_tdata <= s_axis_tdata & (~BYPASS_BIT_MASK);
m_axis_tlast <= s_axis_tlast;
m_axis_tuser <= s_axis_tuser;
state <= ST_SEND;
end
end
ST_SEND: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b0;
s_axis_tready <= 1'b1;
state <= ST_GET;
end
end
default: begin
state <= ST_RST;
end
endcase
end
end
endmodule
| 8.785935 |
module axis_inf (
// adi interface
clk,
rst,
valid,
last,
data,
// xilinx interface
inf_valid,
inf_last,
inf_data,
inf_ready
);
// parameter for data width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adi interface
input clk;
input rst;
input valid;
input last;
input [DW:0] data;
// xil interface
output inf_valid;
output inf_last;
output [DW:0] inf_data;
input inf_ready;
// internal registers
reg [ 2:0] wcnt = 'd0;
reg wlast_0 = 'd0;
reg [DW:0] wdata_0 = 'd0;
reg wlast_1 = 'd0;
reg [DW:0] wdata_1 = 'd0;
reg wlast_2 = 'd0;
reg [DW:0] wdata_2 = 'd0;
reg wlast_3 = 'd0;
reg [DW:0] wdata_3 = 'd0;
reg wlast_4 = 'd0;
reg [DW:0] wdata_4 = 'd0;
reg wlast_5 = 'd0;
reg [DW:0] wdata_5 = 'd0;
reg wlast_6 = 'd0;
reg [DW:0] wdata_6 = 'd0;
reg wlast_7 = 'd0;
reg [DW:0] wdata_7 = 'd0;
reg [ 2:0] rcnt = 'd0;
reg inf_valid = 'd0;
reg inf_last = 'd0;
reg [DW:0] inf_data = 'd0;
// write interface
always @(posedge clk) begin
if (rst == 1'b1) begin
wcnt <= 'd0;
end else if (valid == 1'b1) begin
wcnt <= wcnt + 1'b1;
end
if ((wcnt == 3'd0) && (valid == 1'b1)) begin
wlast_0 <= last;
wdata_0 <= data;
end
if ((wcnt == 3'd1) && (valid == 1'b1)) begin
wlast_1 <= last;
wdata_1 <= data;
end
if ((wcnt == 3'd2) && (valid == 1'b1)) begin
wlast_2 <= last;
wdata_2 <= data;
end
if ((wcnt == 3'd3) && (valid == 1'b1)) begin
wlast_3 <= last;
wdata_3 <= data;
end
if ((wcnt == 3'd4) && (valid == 1'b1)) begin
wlast_4 <= last;
wdata_4 <= data;
end
if ((wcnt == 3'd5) && (valid == 1'b1)) begin
wlast_5 <= last;
wdata_5 <= data;
end
if ((wcnt == 3'd6) && (valid == 1'b1)) begin
wlast_6 <= last;
wdata_6 <= data;
end
if ((wcnt == 3'd7) && (valid == 1'b1)) begin
wlast_7 <= last;
wdata_7 <= data;
end
end
// read interface
always @(posedge clk) begin
if (rst == 1'b1) begin
rcnt <= 'd0;
inf_valid <= 'd0;
inf_last <= 'b0;
inf_data <= 'd0;
end else if ((inf_ready == 1'b1) || (inf_valid == 1'b0)) begin
if (rcnt == wcnt) begin
rcnt <= rcnt;
inf_valid <= 1'd0;
inf_last <= 1'b0;
inf_data <= 'd0;
end else begin
rcnt <= rcnt + 1'b1;
inf_valid <= 1'b1;
case (rcnt)
3'd0: begin
inf_last <= wlast_0;
inf_data <= wdata_0;
end
3'd1: begin
inf_last <= wlast_1;
inf_data <= wdata_1;
end
3'd2: begin
inf_last <= wlast_2;
inf_data <= wdata_2;
end
3'd3: begin
inf_last <= wlast_3;
inf_data <= wdata_3;
end
3'd4: begin
inf_last <= wlast_4;
inf_data <= wdata_4;
end
3'd5: begin
inf_last <= wlast_5;
inf_data <= wdata_5;
end
3'd6: begin
inf_last <= wlast_6;
inf_data <= wdata_6;
end
default: begin
inf_last <= wlast_7;
inf_data <= wdata_7;
end
endcase
end
end
end
endmodule
| 7.795894 |
module axis_infrastructure_v1_1_0_cdc_handshake #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_WIDTH = 32,
parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire from_clk,
input wire req,
output wire ack,
input wire [C_WIDTH-1:0] data_in,
input wire to_clk,
output wire [C_WIDTH-1:0] data_out
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire ack_synch;
wire req_synch;
wire data_en;
reg req_synch_d1;
reg [C_WIDTH-1:0] data_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Output ack from input req after being synchronized back and forth.
assign ack = ack_synch;
axis_infrastructure_v1_1_0_clock_synchronizer #(
.C_NUM_STAGES(C_NUM_SYNCHRONIZER_STAGES)
) inst_ack_synch (
.clk(from_clk),
.synch_in(req_synch),
.synch_out(ack_synch)
);
axis_infrastructure_v1_1_0_clock_synchronizer #(
.C_NUM_STAGES(C_NUM_SYNCHRONIZER_STAGES)
) inst_req_synch (
.clk(to_clk),
.synch_in(req),
.synch_out(req_synch)
);
// Output data from synchronized data reg from successful handshake
assign data_out = data_r;
always @(posedge to_clk) begin
data_r = data_en ? data_in : data_r;
end
// Save data only at transition
assign data_en = req_synch & ~req_synch_d1;
always @(posedge to_clk) begin
req_synch_d1 <= req_synch;
end
endmodule
| 7.431915 |
module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_clock_synchronizer # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_NUM_STAGES = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire synch_in ,
output wire synch_out
);
////////////////////////////////////////////////////////////////////////////////
// Local Parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer P_SYNCH_D_WIDTH = (C_NUM_STAGES > 0) ? C_NUM_STAGES : 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
(* ASYNC_REG = "TRUE" *) reg [P_SYNCH_D_WIDTH-1:0] synch_d = 'b0;
generate
if (C_NUM_STAGES > 0) begin : gen_synchronizer
genvar i;
always @(posedge clk) begin
synch_d[0] <= synch_in;
end
for (i = 1; i < C_NUM_STAGES ; i = i + 1) begin : gen_stage
always @(posedge clk) begin
synch_d[i] <= synch_d[i-1];
end
end
assign synch_out = synch_d[C_NUM_STAGES-1];
end
else begin : gen_no_synchronizer
assign synch_out = synch_in;
end
endgenerate
endmodule
| 7.670485 |
module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_clock_synchronizer # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_NUM_STAGES = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire synch_in ,
output wire synch_out
);
////////////////////////////////////////////////////////////////////////////////
// Local Parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
xpm_cdc_single #(
.DEST_SYNC_FF ( C_NUM_STAGES ) ,
.SRC_INPUT_REG ( 0 ) ,
.SIM_ASSERT_CHK ( 0 )
)
inst_xpm_cdc_single (
.src_clk ( 1'b0 ) ,
.src_in ( synch_in ) ,
.dest_out ( synch_out ) ,
.dest_clk ( clk )
);
endmodule
| 7.670485 |
module axis_infrastructure_v1_1_0_cdc_handshake #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_WIDTH = 32,
parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire from_clk,
input wire req,
output wire ack,
input wire [C_WIDTH-1:0] data_in,
input wire to_clk,
output wire data_valid,
output wire [C_WIDTH-1:0] data_out
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
xpm_cdc_handshake #(
.WIDTH (C_WIDTH),
.DEST_SYNC_FF (C_NUM_SYNCHRONIZER_STAGES),
.SRC_SYNC_FF (C_NUM_SYNCHRONIZER_STAGES),
.DEST_EXT_HSK (0),
.SIM_ASSERT_CHK(0)
) inst_xpm_cdc_handshake (
.src_in (data_in),
.src_send(req),
.src_rcv (ack),
.src_clk (from_clk),
.dest_out(data_out),
.dest_req(data_valid),
.dest_ack(1'b0),
.dest_clk(to_clk)
);
endmodule
| 7.431915 |
module axis_interconnect #(
parameter CHANNELS_IN = 4,
parameter CHANNELS_OUT = 1,
parameter DATA_WIDTH = 8,
parameter USER_WIDTH = 2
) (
input wire aclk,
input wire aresetn,
input wire [CHANNELS_IN*DATA_WIDTH-1:0] s_axis_tdata,
input wire [CHANNELS_IN*$clog2(CHANNELS_OUT)-1:0] s_axis_tdest,
input wire [CHANNELS_IN*USER_WIDTH-1:0] s_axis_tuser,
input wire [CHANNELS_IN-1:0] s_axis_tvalid,
output wire [CHANNELS_IN-1:0] s_axis_tready,
input wire [CHANNELS_IN-1:0] s_axis_tlast,
output wire [CHANNELS_OUT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [CHANNELS_OUT*USER_WIDTH-1:0] m_axis_tuser,
output wire [CHANNELS_OUT-1:0] m_axis_tvalid,
input wire [CHANNELS_OUT-1:0] m_axis_tready,
output wire [CHANNELS_OUT-1:0] m_axis_tlast
);
genvar g, h;
generate
wire [CHANNELS_IN*CHANNELS_OUT-1:0] arb_tready;
wire [CHANNELS_IN*CHANNELS_OUT-1:0] axis_tready;
for (g = 0; g < CHANNELS_OUT; g = g + 1) begin : ARBITER
for (h = 0; h < CHANNELS_IN; h = h + 1) begin
assign axis_tready[CHANNELS_OUT*h+g+:1] = arb_tready[CHANNELS_IN*g+h+:1];
end
axis_arbiter #(
.CHAN_NUM (CHANNELS_IN),
.DATA_WIDTH(DATA_WIDTH),
.DEST_INDEX(g),
.DEST_WIDTH($clog2(CHANNELS_OUT)),
.USER_WIDTH(USER_WIDTH)
) axis_arbiter_inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tuser(s_axis_tuser),
.s_axis_tdest(s_axis_tdest),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(arb_tready[CHANNELS_IN*(g+1)-1-:CHANNELS_IN]),
.s_axis_tlast(s_axis_tlast),
.m_axis_tdata(m_axis_tdata[DATA_WIDTH*(g+1)-1-:DATA_WIDTH]),
.m_axis_tuser(m_axis_tuser[USER_WIDTH*(g+1)-1-:USER_WIDTH]),
.m_axis_tvalid(m_axis_tvalid[g]),
.m_axis_tready(m_axis_tready[g]),
.m_axis_tlast(m_axis_tlast[g])
);
end
for (h = 0; h < CHANNELS_IN; h = h + 1) begin
assign s_axis_tready[h] = (axis_tready[CHANNELS_OUT*(h+1)-1-:CHANNELS_OUT] != 0);
end
endgenerate
endmodule
| 7.015684 |
module axis_arbiter #(
parameter CHAN_NUM = 4,
parameter DATA_WIDTH = 8,
parameter DEST_INDEX = 0,
parameter DEST_WIDTH = 4,
parameter USER_WIDTH = 2
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*CHAN_NUM-1:0] s_axis_tdata,
input wire [USER_WIDTH*CHAN_NUM-1:0] s_axis_tuser,
input wire [CHAN_NUM*DEST_WIDTH-1:0] s_axis_tdest,
input wire [CHAN_NUM-1:0] s_axis_tvalid,
output wire [CHAN_NUM-1:0] s_axis_tready,
input wire [CHAN_NUM-1:0] s_axis_tlast,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [USER_WIDTH-1:0] m_axis_tuser,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast
);
localparam PTR_WIDTH = $clog2(CHAN_NUM);
reg [PTR_WIDTH-1:0] curr;
reg curr_wrap;
reg [PTR_WIDTH-1:0] next;
reg act;
wire [CHAN_NUM-1:0] axis_tvalid;
integer i, j;
genvar g;
generate
for (g = 0; g < CHAN_NUM; g = g + 1) begin
if (DEST_WIDTH > 0) begin
wire dest_valid = (s_axis_tdest[DEST_WIDTH*(g+1)-1-:DEST_WIDTH] == DEST_INDEX);
assign s_axis_tready[g] = (dest_valid ? (curr == g ? m_axis_tready : 1'b0) : 1'b0) & aresetn;
assign axis_tvalid[g] = (dest_valid ? s_axis_tvalid[g] : 1'b0) & aresetn;
end else begin
assign s_axis_tready[g] = (curr == g ? m_axis_tready : 1'b0) & aresetn;
assign axis_tvalid[g] = s_axis_tvalid[g] & aresetn;
end
end
endgenerate
assign m_axis_tdata = axis_tvalid[curr] ? s_axis_tdata[DATA_WIDTH*(curr+1)-1-:DATA_WIDTH] : 0;
assign m_axis_tuser = axis_tvalid[curr] ? s_axis_tuser[USER_WIDTH*(curr+1)-1-:USER_WIDTH] : 0;
assign m_axis_tvalid = aresetn ? axis_tvalid[curr] : 1'b0;
assign m_axis_tlast = s_axis_tlast[curr] & axis_tvalid[curr];
always @(posedge aclk) begin
if (aresetn == 1'b0) begin
act <= 1'b0;
next <= 0;
end else begin
if (act == 1'b0) begin
if (m_axis_tvalid) begin
if (m_axis_tready & m_axis_tlast) begin
act <= 1'b0;
if (curr == (CHAN_NUM - 1)) begin
next <= 0;
end else begin
next <= curr + 1;
end
end else begin
act <= 1'b1;
next <= curr;
end
end
end else begin
if (m_axis_tvalid & m_axis_tready & m_axis_tlast) begin
act <= 1'b0;
if (curr == (CHAN_NUM - 1)) begin
next <= 0;
end else begin
next <= curr + 1;
end
end
end
end
end
always @(*) begin
curr = next;
curr_wrap = 1'b1;
if (act == 1'b0) begin
for (i = 0; i < CHAN_NUM; i = i + 1) begin
if (i == next) begin
for (j = (CHAN_NUM - 1); j >= i; j = j - 1) begin
if (axis_tvalid[j]) begin
curr = j;
curr_wrap = 1'b0;
end
end
if (curr_wrap == 1'b1) begin
for (j = i - 1; j >= 0; j = j - 1) begin
if (axis_tvalid[j]) begin
curr = j;
end
end
end
end
end
end
end
endmodule
| 6.947342 |
module axis_keyer #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
input wire key_flag,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [1:0] int_case_reg, int_case_next;
wire [1:0] int_comp_wire;
always @(posedge aclk) begin
if (~aresetn) begin
int_addr_reg <= {(BRAM_ADDR_WIDTH) {1'b0}};
int_case_reg <= 2'd0;
end else begin
int_addr_reg <= int_addr_next;
int_case_reg <= int_case_next;
end
end
assign int_comp_wire = {|int_addr_reg, int_addr_reg < cfg_data};
always @* begin
int_addr_next = int_addr_reg;
int_case_next = int_case_reg;
case (int_case_reg)
2'd0: begin
if (key_flag & int_comp_wire[0]) begin
int_case_next = 2'd1;
end
end
2'd1: begin
if (m_axis_tready) begin
if (int_comp_wire[0]) begin
int_addr_next = int_addr_reg + 1'b1;
end else begin
int_case_next = 2'd2;
end
end
end
2'd2: begin
if (~key_flag) begin
int_case_next = 2'd3;
end
end
2'd3: begin
if (m_axis_tready) begin
if (int_comp_wire[1]) begin
int_addr_next = int_addr_reg - 1'b1;
end else begin
int_case_next = 2'd0;
end
end
end
endcase
end
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = 1'b1;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready ? int_addr_next : int_addr_reg;
endmodule
| 7.592489 |
module axis_lfsr #(
parameter integer AXIS_TDATA_WIDTH = 64
) (
// System signals
input wire aclk,
input wire aresetn,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_lfsr_reg, int_lfsr_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_lfsr_reg <= 64'h5555555555555555;
int_enbl_reg <= 1'b0;
end else begin
int_lfsr_reg <= int_lfsr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @* begin
int_lfsr_next = int_lfsr_reg;
int_enbl_next = int_enbl_reg;
if (~int_enbl_reg) begin
int_enbl_next = 1'b1;
end
if (int_enbl_reg & m_axis_tready) begin
int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
end
end
assign m_axis_tdata = int_lfsr_reg;
assign m_axis_tvalid = int_enbl_reg;
endmodule
| 6.938058 |
module axis_ll_bridge #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
/*
* LocalLink output
*/
output wire [DATA_WIDTH-1:0] ll_data_out,
output wire ll_sof_out_n,
output wire ll_eof_out_n,
output wire ll_src_rdy_out_n,
input wire ll_dst_rdy_in_n
);
reg last_tlast = 1'b1;
always @(posedge clk) begin
if (rst) begin
last_tlast = 1'b1;
end else begin
if (s_axis_tvalid && s_axis_tready) last_tlast = s_axis_tlast;
end
end
// high for packet length 1 -> cannot set SOF and EOF in same cycle
// invalid packets are discarded
wire invalid = s_axis_tvalid && s_axis_tlast && last_tlast;
assign s_axis_tready = !ll_dst_rdy_in_n;
assign ll_data_out = s_axis_tdata;
assign ll_sof_out_n = !(last_tlast && s_axis_tvalid && !invalid);
assign ll_eof_out_n = !(s_axis_tlast && !invalid);
assign ll_src_rdy_out_n = !(s_axis_tvalid && !invalid);
endmodule
| 9.332818 |
module is to loopback the AXI4-Stream that is produced
// by the OPED to the stream that is consumed by the OPED. In this way, this
// module can stand-in for the OPED during development; and be repaled with
// Input/Output arbiters when ready. This module allows testing of the DMA
// capabilities of OPED block with mininal extra logic.
//
// + The 128b of TUSER are assigned as follows:
// TUSER[15:0] Transfer Length in Bytes (provided by OPED AXIS Master; ignored by OPED AXIS Slave - TLAST implicit length)
// TUSER[23:16] Source Port (SPT) (provided by OPED AXIS Master from DP0 opcode; ignored by OPED AXIS Slave)
// TUSER[31:24] Destination Port (DPT) (driven to 8'h01 by OPED AXIS Master; used by OPED AXIS Slave to make DP1 opcode)
// TUSER[127:32] User metadata bits, un-used by OPED. driven to 0 by OPED AXIS master; un-used by OPED AXIS slave
//
// Note that OPED is "port-encoding-agnostic" with respect to the values on SPT and DPT:
// a. In the case of packets moving downstream from host to NF10, OPED places DP0 opcode metadata on SPT
// b. In the case of packets moving upstream from NF10 to host, OPED captures DPT and places it in DP1 opcode
// The value 8'h01 is placed as a constant in the DPT output of the OPED AXIS Master
// Note that OPED does nothing with the TUSER[127:32] user metadata bits.
// a. It drives them to 0 on the AXIS Master
// b. it ignores them on the the AXIS Slave
module AXIS_LOOPBACK (
input wire ACLK,
input wire ARESETN,
input wire [32:0] S_AXIS_DAT_TDATA,
input wire S_AXIS_DAT_TVALID,
input wire [3:0] S_AXIS_DAT_TSTRB,
input wire [127:0] S_AXIS_DAT_TUSER,
input wire S_AXIS_DAT_TLAST,
output wire S_AXIS_DAT_TREADY,
output wire [32:0] M_AXIS_DAT_TDATA,
output wire M_AXIS_DAT_TVALID,
output wire [3:0] M_AXIS_DAT_TSTRB,
output wire [127:0] M_AXIS_DAT_TUSER,
output wire M_AXIS_DAT_TLAST,
input wire M_AXIS_DAT_TREADY
);
// Just loop the signals through...
assign M_AXIS_DAT_TDATA = S_AXIS_DAT_TDATA;
assign M_AXIS_DAT_TVALID = S_AXIS_DAT_TVALID;
assign M_AXIS_DAT_TSTRB = S_AXIS_DAT_TSTRB;
// Crossover the SPT and DPT bitfields so that the SPT input feeds the DPT output - otherwise opcode will be "lost"...
assign M_AXIS_DAT_TUSER = {S_AXIS_DAT_TUSER[127:32], S_AXIS_DAT_TUSER[23:16], S_AXIS_DAT_TUSER[31:24], S_AXIS_DAT_TUSER[15:0]};
assign M_AXIS_DAT_TLAST = S_AXIS_DAT_TLAST;
assign S_AXIS_DAT_TREADY = M_AXIS_DAT_TREADY;
endmodule
| 6.64491 |
module axis_loopback_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_header();
always @(end_trigger) display_header();
// And strobe signals at each clk
always @(posedge clk) display_signals();
`endif
// initial begin
// $dumpfile("result.vcd"); // Waveform file
// $dumpvars;
// end
/**
* Local parameters
*/
`ifdef TB_VERBOSE
initial $display("Testbench for unit 'axis_loopback'");
`endif
/**
* signals, registers and wires
*/
reg rst;
/**
* Unit under test
*/
axis_loopback
uut (
.clk (clk),
.rst_n ( ~rst)
);
/**
* Wave form display
*/
task display_signals;
$display(
"%d\t%d",
$time, rst,
);
endtask // display_signals
task display_header;
$display(
"\t\ttime\trst",
);
endtask
/**
* Testbench program
*/
initial begin
// init values
clk = 0;
rst = 0;
//end init
`ifdef TB_VERBOSE
$display("RESET");
`endif
repeat(6) @(negedge clk);
rst <= 1'b1;
repeat(6) @(negedge clk);
rst <= 1'b0;
@(negedge clk);
`ifdef TB_VERBOSE
$display("wait");
`endif
repeat(10) @(negedge clk);
`ifdef TB_VERBOSE
$display("END");
`endif
-> end_trigger;
end
endmodule
| 8.141849 |
module axis_m (
input areset_n,
input aclk,
input [31:0] data,
input send,
input tready,
output reg tvalid,
output tlast,
output reg [31:0] tdata,
output reg finish
);
reg [31:0] data_buf; // buffer to keep the send data from change
always @(posedge send or negedge areset_n)
if (~areset_n) data_buf <= 0;
else data_buf <= data;
reg send_pulse_1d, send_pulse_2d;
// just delay the send signal
always @(posedge aclk)
if (~areset_n) {send_pulse_1d, send_pulse_2d} <= 2'b00;
else {send_pulse_1d, send_pulse_2d} <= {send, send_pulse_1d};
// handshake happened between master and slave
wire handshake;
assign handshake = tvalid & tready;
// tdata
always @(posedge aclk)
if (~areset_n) tdata <= 1'b0;
else if (handshake) tdata <= 0;
else if (send_pulse_1d) tdata <= data_buf;
else tdata <= tdata;
// tvalid
// as soon as the fifo becomes no empty the tvalid goes high
always @(posedge aclk)
if (~areset_n) tvalid <= 1'b0;
else if (handshake) tvalid <= 1'b0;
else if (send_pulse_1d) tvalid <= 1'b1;
else tvalid <= tvalid;
// tlast
// same behavioral as tvalid
assign tlast = tvalid;
// finish
always @(posedge aclk)
if (~areset_n) finish <= 1'b0;
else if (send_pulse_1d) finish <= 1'b0;
else if (handshake) finish <= 1'b1;
else finish <= 1'b0;
endmodule
| 7.369554 |
module axis_master (
aclk,
aresetn,
tvalid,
tready,
tdata
);
input aclk, aresetn, tready;
output reg tvalid;
output reg [7:0] tdata;
reg [31:0] state;
always @(posedge aclk) begin
if (!aresetn) begin
state <= 314159265;
tvalid <= 0;
tdata <= 'bx;
end else begin
if (tvalid && tready) tvalid <= 0;
if (!tvalid || !tready) begin
// ^- should not be inverted!
state = state ^ state << 13;
state = state ^ state >> 7;
state = state ^ state << 17;
if (state[9:8] == 0) begin
tvalid <= 1;
tdata <= state;
end
end
end
end
endmodule
| 6.793576 |
module axis_mux4 (
input s_axis_clk,
input s_arstn,
input m_axis_tready,
output [63:0] m_axis_tdata,
output [ 7:0] m_axis_tkeep,
output m_axis_tlast,
output m_axis_tvalid,
output s0_axis_tready,
input [63:0] s0_axis_tdata,
input [ 7:0] s0_axis_tkeep,
input s0_axis_tlast,
input s0_axis_tvalid,
output s1_axis_tready,
input [63:0] s1_axis_tdata,
input [ 7:0] s1_axis_tkeep,
input s1_axis_tlast,
input s1_axis_tvalid,
output s2_axis_tready,
input [63:0] s2_axis_tdata,
input [ 7:0] s2_axis_tkeep,
input s2_axis_tlast,
input s2_axis_tvalid,
output s3_axis_tready,
input [63:0] s3_axis_tdata,
input [ 7:0] s3_axis_tkeep,
input s3_axis_tlast,
input s3_axis_tvalid
);
localparam MUX_S0 = 2'h0;
localparam MUX_S1 = 2'h1;
localparam MUX_S2 = 2'h2;
localparam MUX_S3 = 2'h3;
reg [1:0] state;
assign m_axis_tdata = (state == MUX_S0) ? s0_axis_tdata :
(state == MUX_S1) ? s1_axis_tdata :
(state == MUX_S2) ? s2_axis_tdata :
/*(state == MUX_S3) ?*/ s3_axis_tdata;
assign m_axis_tkeep = (state == MUX_S0) ? s0_axis_tkeep :
(state == MUX_S1) ? s1_axis_tkeep :
(state == MUX_S2) ? s2_axis_tkeep :
/*(state == MUX_S3) ?*/ s3_axis_tkeep;
assign m_axis_tvalid = (state == MUX_S0) ? s0_axis_tvalid :
(state == MUX_S1) ? s1_axis_tvalid :
(state == MUX_S2) ? s2_axis_tvalid :
(state == MUX_S3) ? s3_axis_tvalid :
1'b0;
assign m_axis_tlast = (state == MUX_S0) ? s0_axis_tlast :
(state == MUX_S1) ? s1_axis_tlast :
(state == MUX_S2) ? s2_axis_tlast :
/*(state == MUX_S3) ?*/ s3_axis_tlast;
assign s0_axis_tready = (state == MUX_S0) ? m_axis_tready : 1'b0;
assign s1_axis_tready = (state == MUX_S1) ? m_axis_tready : 1'b0;
assign s2_axis_tready = (state == MUX_S2) ? m_axis_tready : 1'b0;
assign s3_axis_tready = (state == MUX_S3) ? m_axis_tready : 1'b0;
wire [2:0] sel_prio_state = (s0_axis_tvalid) ? {1'b1, MUX_S0 } :
(s1_axis_tvalid) ? {1'b1, MUX_S1 } :
(s2_axis_tvalid) ? {1'b1, MUX_S2 } :
(s3_axis_tvalid) ? {1'b1, MUX_S3 } : {1'b0, MUX_S0 };
reg started;
wire last_transfer = m_axis_tready && m_axis_tvalid && m_axis_tlast;
always @(posedge s_axis_clk) begin
if (~s_arstn) begin
state <= MUX_S0;
started <= 1'b0;
end else begin
if (~started) begin
if (m_axis_tvalid) begin
started <= 1'b1;
end else begin
state <= sel_prio_state[1:0];
end
end
if (last_transfer) begin
state <= sel_prio_state[1:0];
started <= (state != sel_prio_state[1:0]) && sel_prio_state[2];
end
end
end
endmodule
| 7.905159 |
module axis_packet_generator_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S0_AXI
parameter integer C_S0_AXI_DATA_WIDTH = 32,
parameter integer C_S0_AXI_ADDR_WIDTH = 5,
// Parameters of Axi Master Bus Interface M0_AXIS
parameter integer C_M0_AXIS_TDATA_WIDTH = 32
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S0_AXI
input wire s0_axi_aclk,
input wire s0_axi_aresetn,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
input wire [2 : 0] s0_axi_awprot,
input wire s0_axi_awvalid,
output wire s0_axi_awready,
input wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input wire [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
input wire s0_axi_wvalid,
output wire s0_axi_wready,
output wire [1 : 0] s0_axi_bresp,
output wire s0_axi_bvalid,
input wire s0_axi_bready,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input wire [2 : 0] s0_axi_arprot,
input wire s0_axi_arvalid,
output wire s0_axi_arready,
output wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output wire [1 : 0] s0_axi_rresp,
output wire s0_axi_rvalid,
input wire s0_axi_rready,
// Ports of Axi Master Bus Interface M0_AXIS
input wire m0_axis_aclk,
input wire m0_axis_aresetn,
output wire m0_axis_tvalid,
output wire [C_M0_AXIS_TDATA_WIDTH-1 : 0] m0_axis_tdata,
//output wire [(C_M0_AXIS_TDATA_WIDTH/8)-1 : 0] m0_axis_tstrb,
output wire m0_axis_tlast,
input wire m0_axis_tready
);
wire start_packet_generator_d;
wire [31:0] start_delay_d;
wire [31:0] delay_between_packets_d;
wire [31:0] packet_size_d;
wire [31:0] packets_num_d;
wire packet_generator_complete_d;
// Instantiation of Axi Bus Interface S0_AXI
axis_packet_generator_v1_0_S0_AXI #(
.C_S_AXI_DATA_WIDTH(C_S0_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S0_AXI_ADDR_WIDTH)
) axis_packet_generator_v1_0_S0_AXI_inst (
.S_AXI_ACLK(s0_axi_aclk),
.S_AXI_ARESETN(s0_axi_aresetn),
.S_AXI_AWADDR(s0_axi_awaddr),
.S_AXI_AWPROT(s0_axi_awprot),
.S_AXI_AWVALID(s0_axi_awvalid),
.S_AXI_AWREADY(s0_axi_awready),
.S_AXI_WDATA(s0_axi_wdata),
.S_AXI_WSTRB(s0_axi_wstrb),
.S_AXI_WVALID(s0_axi_wvalid),
.S_AXI_WREADY(s0_axi_wready),
.S_AXI_BRESP(s0_axi_bresp),
.S_AXI_BVALID(s0_axi_bvalid),
.S_AXI_BREADY(s0_axi_bready),
.S_AXI_ARADDR(s0_axi_araddr),
.S_AXI_ARPROT(s0_axi_arprot),
.S_AXI_ARVALID(s0_axi_arvalid),
.S_AXI_ARREADY(s0_axi_arready),
.S_AXI_RDATA(s0_axi_rdata),
.S_AXI_RRESP(s0_axi_rresp),
.S_AXI_RVALID(s0_axi_rvalid),
.S_AXI_RREADY(s0_axi_rready),
.start_packet_generator_o(start_packet_generator_d),
.start_delay_o(start_delay_d),
.delay_between_packets_o(delay_between_packets_d),
.packet_size_o(packet_size_d),
.packets_num_o(packets_num_d),
.packet_generator_complete_i(packet_generator_complete_d)
);
// Instantiation of Axi Bus Interface M0_AXIS
axis_packet_generator_v1_0_M0_AXIS #(
.C_M_AXIS_TDATA_WIDTH(C_M0_AXIS_TDATA_WIDTH)
) axis_packet_generator_v1_0_M0_AXIS_inst (
.M_AXIS_ACLK(m0_axis_aclk),
.M_AXIS_ARESETN(m0_axis_aresetn),
.M_AXIS_TVALID(m0_axis_tvalid),
.M_AXIS_TDATA(m0_axis_tdata),
// .M_AXIS_TSTRB(m0_axis_tstrb),
.M_AXIS_TLAST(m0_axis_tlast),
.M_AXIS_TREADY(m0_axis_tready),
.start_packet_generator_i(start_packet_generator_d),
.start_delay_i(start_delay_d),
.delay_between_packets_i(delay_between_packets_d),
.packet_size_i(packet_size_d),
.packets_num_i(packets_num_d),
.packet_generator_complete_o(packet_generator_complete_d)
);
// Add user logic here
// User logic ends
endmodule
| 7.124541 |
modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module axis_phase_generator #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer PHASE_WIDTH = 30
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [PHASE_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [PHASE_WIDTH-1:0] int_cntr_reg = 0, int_cntr_next;
reg int_enbl_reg = 1'b0, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(PHASE_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg & m_axis_tready)
begin
int_cntr_next = int_cntr_reg + cfg_data;
end
end
assign m_axis_tdata = {{(AXIS_TDATA_WIDTH-PHASE_WIDTH){int_cntr_reg[PHASE_WIDTH-1]}}, int_cntr_reg};
assign m_axis_tvalid = int_enbl_reg;
endmodule
| 8.081644 |
module axis_red_pitaya_adc #(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,
input wire adc_clk_n,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_b,
// Master side
output wire m_axis_tvalid,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata
);
localparam PADDING_WIDTH = AXIS_TDATA_WIDTH / 2 - ADC_DATA_WIDTH;
reg [ADC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [ADC_DATA_WIDTH-1:0] int_dat_b_reg;
wire int_clk0;
wire int_clk;
IBUFGDS adc_clk_inst0 (
.I (adc_clk_p),
.IB(adc_clk_n),
.O (int_clk0)
);
BUFG adc_clk_inst (
.I(int_clk0),
.O(int_clk)
);
always @(posedge int_clk) begin
int_dat_a_reg <= adc_dat_a;
int_dat_b_reg <= adc_dat_b;
end
assign adc_clk = int_clk;
assign adc_csn = 1'b1;
assign m_axis_tvalid = 1'b1;
assign m_axis_tdata = {
{(PADDING_WIDTH + 1) {int_dat_b_reg[ADC_DATA_WIDTH-1]}},
~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
{(PADDING_WIDTH + 1) {int_dat_a_reg[ADC_DATA_WIDTH-1]}},
~int_dat_a_reg[ADC_DATA_WIDTH-2:0]
};
endmodule
| 8.024803 |
module axis_red_pitaya_dac #(
parameter integer DAC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// PLL signals
input wire aclk,
input wire ddr_clk,
input wire locked,
// DAC signals
output wire dac_clk,
output wire dac_rst,
output wire dac_sel,
output wire dac_wrt,
output wire [DAC_DATA_WIDTH-1:0] dac_dat,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [DAC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [DAC_DATA_WIDTH-1:0] int_dat_b_reg;
reg int_rst_reg;
wire [DAC_DATA_WIDTH-1:0] int_dat_a_wire;
wire [DAC_DATA_WIDTH-1:0] int_dat_b_wire;
assign int_dat_a_wire = s_axis_tdata[DAC_DATA_WIDTH-1:0];
assign int_dat_b_wire = s_axis_tdata[AXIS_TDATA_WIDTH/2+DAC_DATA_WIDTH-1:AXIS_TDATA_WIDTH/2];
genvar j;
always @(posedge aclk) begin
if (~locked | ~s_axis_tvalid) begin
int_dat_a_reg <= {(DAC_DATA_WIDTH) {1'b0}};
int_dat_b_reg <= {(DAC_DATA_WIDTH) {1'b0}};
end else begin
int_dat_a_reg <= {int_dat_a_wire[DAC_DATA_WIDTH-1], ~int_dat_a_wire[DAC_DATA_WIDTH-2:0]};
int_dat_b_reg <= {int_dat_b_wire[DAC_DATA_WIDTH-1], ~int_dat_b_wire[DAC_DATA_WIDTH-2:0]};
end
int_rst_reg <= ~locked | ~s_axis_tvalid;
end
ODDR ODDR_rst (
.Q (dac_rst),
.D1(int_rst_reg),
.D2(int_rst_reg),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_sel (
.Q (dac_sel),
.D1(1'b0),
.D2(1'b1),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_wrt (
.Q (dac_wrt),
.D1(1'b0),
.D2(1'b1),
.C (ddr_clk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_clk (
.Q (dac_clk),
.D1(1'b0),
.D2(1'b1),
.C (ddr_clk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
generate
for (j = 0; j < DAC_DATA_WIDTH; j = j + 1) begin : DAC_DAT
ODDR ODDR_inst (
.Q (dac_dat[j]),
.D1(int_dat_a_reg[j]),
.D2(int_dat_b_reg[j]),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
assign s_axis_tready = 1'b1;
endmodule
| 8.024803 |
module axis_register_slice_32 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [255 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [255 : 0] m_axis_tdata;
axis_register_slice_v1_1_22_axis_register_slice #(
.C_FAMILY("kintexuplus"),
.C_AXIS_TDATA_WIDTH(256),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
.C_REG_CONFIG(8),
.C_NUM_SLR_CROSSINGS(0),
.C_PIPELINES_MASTER(0),
.C_PIPELINES_SLAVE(0),
.C_PIPELINES_MIDDLE(0)
) inst (
.aclk(aclk),
.aclk2x(1'H0),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(32'HFFFFFFFF),
.s_axis_tkeep(32'HFFFFFFFF),
.s_axis_tlast(1'H1),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
| 7.186837 |
module axis_register_slice_v1_1_22_tdm_sample (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire slow_clk,
input wire fast_clk,
output wire sample_cycle
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_clk_div2 = 1'b0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg sample_cycle_d;
(* shreg_extract = "no" *)reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge slow_clk) begin
slow_clk_div2 <= ~slow_clk_div2;
end
// Find matching rising edges by clocking slow_clk_div2 onto faster clock
always @(posedge fast_clk) begin
posedge_finder_first <= slow_clk_div2;
end
always @(posedge fast_clk) begin
posedge_finder_second <= ~slow_clk_div2;
end
assign first_edge = slow_clk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d = first_edge | second_edge;
end
always @(posedge fast_clk) begin
sample_cycle_r <= sample_cycle_d;
end
assign sample_cycle = sample_cycle_r;
endmodule
| 7.186837 |
module axis_register_slice_v1_1_22_test_master #(
parameter integer C_DATA_WIDTH = 32
) (
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Master side
(* dont_touch="true" *) output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
(* dont_touch="true" *) output wire M_VALID,
input wire M_READY
);
//**********************************************
reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}};
reg tvalid_i = 1'b0;
assign M_VALID = tvalid_i;
assign M_PAYLOAD_DATA = payld_i;
always @(posedge ACLK) begin
if (ARESET) begin
tvalid_i <= 1'b0;
payld_i <= {C_DATA_WIDTH{1'b0}};
end else if (ACLKEN) begin
if (M_READY && tvalid_i) begin
tvalid_i <= 1'b0;
payld_i <= {payld_i[C_DATA_WIDTH-2 : 0], ~payld_i[C_DATA_WIDTH-1]};
end else begin
tvalid_i <= 1'b1;
end
end
end
endmodule
| 7.186837 |
module axis_register_slice_v1_1_22_test_slave #(
parameter integer C_DATA_WIDTH = 32
) (
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
(* dont_touch="true" *) output wire S_READY
);
reg valid_d = 1'b0;
reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}};
reg ready_i = 1'b0;
assign S_READY = ready_i;
always @(posedge ACLK) begin
if (ARESET) begin
ready_i <= 1'b0;
payld_i <= {C_DATA_WIDTH{1'b0}};
end else if (ACLKEN) begin
valid_d <= S_VALID;
if (S_VALID & ready_i) begin
payld_i <= S_PAYLOAD_DATA;
ready_i <= 1'b0;
end else begin
payld_i <= payld_i >> 1;
ready_i <= payld_i[0] ? valid_d : S_VALID;
end
end
end
endmodule
| 7.186837 |
module axis_register_slice_v1_1_22_srl_rtl #(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
) (
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire q // Output Data
);
localparam integer P_SRLDEPTH = 2 ** C_A_WIDTH;
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge clk) if (ce) shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
assign q = shift_reg[a];
endmodule
| 7.186837 |
module="yes" *)
module axis_register_slice_v1_1_22_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
wire handshake_pipe;
wire ready_pipe;
wire [C_DATA_WIDTH-1:0] payload_pipe;
(* keep="true" *) reg s_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg s_areset_resp = 1'b0;
(* keep="true" *) reg s_areset_resp2 = 1'b0;
(* keep="true" *) reg m_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg m_areset_resp = 1'b0;
(* keep="true" *) reg m_areset_resp2 = 1'b0;
// Global Reset pipelining
always @(posedge ACLK) begin
s_aclear <= ARESET;
s_areset_fwd <= ARESET;
s_areset_resp <= s_areset_fwd; // Auto-pipeline
s_areset_resp2 <= s_areset_resp; // Auto-pipeline
end
always @(posedge ACLK) begin
m_aclear <= ARESET;
m_areset_fwd <= ARESET;
m_areset_resp <= m_areset_fwd; // Auto-pipeline
m_areset_resp2 <= m_areset_resp; // Auto-pipeline
end
// Source-side submodule
axis_register_slice_v1_1_22_auto_src #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_src
(
.ACLK (ACLK),
.ACLKEN (ACLKEN) ,
.s_aclear (s_aclear),
.s_areset_resp2 (s_areset_resp2),
.S_VALID (S_VALID),
.S_READY (S_READY),
.S_PAYLOAD_DATA (S_PAYLOAD_DATA),
.ready_pipe (ready_pipe),
.handshake_pipe (handshake_pipe),
.payload_pipe (payload_pipe)
);
// Destination-side submodule
axis_register_slice_v1_1_22_auto_dest #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_dest
(
.ACLK (ACLK),
.ACLKEN (ACLKEN) ,
.m_aclear (m_aclear),
.m_areset_resp2 (m_areset_resp2),
.M_READY (M_READY),
.M_VALID (M_VALID),
.M_PAYLOAD_DATA (M_PAYLOAD_DATA),
.handshake_pipe (handshake_pipe),
.ready_pipe (ready_pipe),
.payload_pipe (payload_pipe)
);
endmodule
| 7.483958 |
module axis_register_slice_v1_1_22_auto_src #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire ACLKEN,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DATA_WIDTH-1:0] payload_pipe,
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r;
(* keep="true" *) reg [2:0] s_aresetn_resp4 = 3'b000;
wire s_aresetn_resp3;
wire s_aresetn_d;
wire s_aresetn_q;
wire s_handshake_d;
wire s_ready_i;
assign S_READY = s_ready_i & s_aresetn_q;
assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;
assign s_handshake_d = S_VALID & s_ready_i & ACLKEN & s_aresetn_q;
assign payload_pipe = payload_pipe_r;
always @(posedge ACLK or posedge s_aclear) begin
if (s_aclear) begin
s_aresetn_resp4 <= 3'b000;
end else begin
s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};
end
end
always @(posedge ACLK) begin
payload_pipe_r <= S_PAYLOAD_DATA;
end
FDCE #(
.INIT(1'b0)
) s_aresetn_resp3_inst (
.Q (s_aresetn_resp3),
.C (ACLK),
.CE (1'b1),
.CLR(1'b0),
.D (~s_areset_resp2)
);
// Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (s_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR(s_aclear),
.D (s_aresetn_d)
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *)
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (handshake_pipe),
.C (ACLK),
.CE (1'b1),
.CLR(s_aclear),
.D (s_handshake_d)
);
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (s_ready_i),
.C (ACLK),
.CE (ACLKEN),
.CLR(s_aclear),
.D (ready_pipe)
);
endmodule
| 7.186837 |
module axis_register_slice_v1_1_22_auto_dest #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire ACLKEN,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DATA_WIDTH-1:0] payload_pipe,
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
(* keep="true" *) reg [2:0] m_aresetn_resp4 = 3'b000;
wire m_aresetn_resp3;
wire m_aresetn_d;
wire m_aresetn_q;
wire m_valid_i;
wire pop;
wire m_ready_d;
wire m_handshake_q;
reg [C_DATA_WIDTH-1:0] m_payload_q;
assign M_VALID = m_valid_i;
assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;
assign m_ready_d = (M_READY | ~m_valid_i) & ACLKEN & m_aresetn_q;
assign pop = M_READY & m_valid_i & ACLKEN;
always @(posedge ACLK or posedge m_aclear) begin
if (m_aclear) begin
m_aresetn_resp4 <= 3'b000;
end else begin
m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};
end
end
always @(posedge ACLK) begin
m_payload_q <= payload_pipe;
end
FDCE #(
.INIT(1'b0)
) m_aresetn_resp3_inst (
.Q (m_aresetn_resp3),
.C (ACLK),
.CE (1'b1),
.CLR(1'b0),
.D (~m_areset_resp2)
);
// Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (m_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (m_aresetn_d)
);
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (m_handshake_q),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (handshake_pipe)
);
(* autopipeline_group="resp" *)
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (ready_pipe),
.C (ACLK),
.CE (1'b1),
.CLR(m_aclear),
.D (m_ready_d)
);
axis_register_slice_v1_1_22_axic_reg_srl_fifo #(
.C_FIFO_WIDTH(C_DATA_WIDTH),
.C_FIFO_SIZE (5)
) srl_fifo (
.aclk (ACLK),
.areset (~m_aresetn_q),
.aclear (m_aclear),
.s_mesg (m_payload_q),
.s_valid(m_handshake_q),
.m_mesg (M_PAYLOAD_DATA),
.m_valid(m_valid_i),
.m_ready(pop)
);
endmodule
| 7.186837 |
module axis_register_tb (
input wire clock,
input wire resetn,
output wire [1:0] size,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
axis_register axis_register_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size == $past(size
+ (ivalid && iready) - (ovalid && oready)));
// just to make induction proof work
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule
| 7.186837 |
module axis_reg_map # (
parameter REG_ADDR_WIDTH = 4,
parameter ADDR_WIDTH = 12,
parameter [ADDR_WIDTH -1:0] ADDR = 0, //Set this to be different for each
parameter RESET_TYPE = `NO_RESET,
parameter PIPE_STAGE = 1
) (
input wire clk,
input wire rst,
//Input command stream
input wire [31:0] cmd_in_TDATA,
input wire cmd_in_TVALID,
//All the reg_maps are daisy-chained.
output wire [31:0] cmd_out_TDATA,
output wire cmd_out_TVALID,
//Register update outputs used by whatever is instantiating this module
output wire [REG_ADDR_WIDTH -1:0] reg_addr,
output wire [31:0] reg_data,
output wire reg_strb
);
//Named subfields of command
wire [ADDR_WIDTH -1:0] cmd_core_addr = cmd_in_TDATA[ADDR_WIDTH + REG_ADDR_WIDTH -1 -: ADDR_WIDTH];
wire [REG_ADDR_WIDTH -1:0] cmd_reg_addr = cmd_in_TDATA[REG_ADDR_WIDTH -1:0];
//We need to know if this message was meant for us
wire msg_for_us = (cmd_core_addr == ADDR);
`wire_rst_sig;
`localparam [1:0] CMD_FSM_ADDR = 0;
`localparam [1:0] CMD_FSM_DATA = 1;
`localparam [1:0] CMD_FSM_IGNORE = 2;
reg [1:0] cmd_fsm_state = CMD_FSM_ADDR;
reg [REG_ADDR_WIDTH -1:0] saved_reg_addr = 0;
`genif (RESET_TYPE == `NO_RESET) begin
always @(posedge clk) begin
if (cmd_in_TVALID) begin
case (cmd_fsm_state)
CMD_FSM_ADDR: begin
cmd_fsm_state <= msg_for_us ?
CMD_FSM_DATA :
CMD_FSM_IGNORE
;
saved_reg_addr <= cmd_reg_addr;
end CMD_FSM_DATA: begin
cmd_fsm_state <= CMD_FSM_ADDR;
end CMD_FSM_IGNORE: begin
cmd_fsm_state <= CMD_FSM_ADDR;
end
endcase
end
end
`else_gen //HAS_RST
always @(posedge clk) begin
if (rst_sig) begin
cmd_fsm_state <= CMD_FSM_ADDR;
end else if (cmd_in_TVALID) begin
case (cmd_fsm_state)
CMD_FSM_ADDR: begin
cmd_fsm_state <= msg_for_us ?
CMD_FSM_DATA :
CMD_FSM_IGNORE
;
saved_reg_addr <= cmd_reg_addr;
end CMD_FSM_DATA: begin
cmd_fsm_state <= CMD_FSM_ADDR;
end CMD_FSM_IGNORE: begin
cmd_fsm_state <= CMD_FSM_ADDR;
end
endcase
end
end
`endgen
assign reg_addr = saved_reg_addr;
assign reg_data = cmd_in_TDATA;
assign reg_strb = cmd_in_TVALID && (cmd_fsm_state == CMD_FSM_DATA);
//Assign cmd_out according to whether the user turned on the pipe stage
`genif (PIPE_STAGE) begin
//Delay by one cycle for timing
reg [31:0] cmd_out_TDATA_r = 0;
reg cmd_out_TVALID_r = 0;
always @(posedge clk) begin
cmd_out_TDATA_r <= cmd_in_TDATA;
cmd_out_TVALID_r <= cmd_in_TVALID;
end
assign cmd_out_TDATA = cmd_out_TDATA_r;
assign cmd_out_TVALID = cmd_out_TVALID_r;
`else_gen
assign cmd_out_TDATA = cmd_in_TDATA;
assign cmd_out_TVALID = cmd_in_TVALID;
`endgen
endmodule
| 8.284532 |
module dbg_guv_tb #(
parameter REG_ADDR_WIDTH = 4,
parameter ADDR_WIDTH = 12,
parameter [ADDR_WIDTH -1:0] ADDR = 0, //Set this to be different for each
parameter RESET_TYPE = `NO_RESET,
parameter PIPE_STAGE = 1
);
reg clk = 0;
reg rst = 0;
//Input command stream
reg [31:0] cmd_in_TDATA = 0;
reg cmd_in_TVALID = 0;
//All the controllers are daisy-chained. If in incoming command is not for
//this controller, send it to the next one
wire [31:0] cmd_out_TDATA;
wire cmd_out_TVALID;
//Register update outputs, used by whatever is instantiating this module
wire [REG_ADDR_WIDTH -1:0] reg_addr0;
wire [31:0] reg_data0;
wire reg_strb0;
wire [REG_ADDR_WIDTH -1:0] reg_addr1;
wire [31:0] reg_data1;
wire reg_strb1;
wire [REG_ADDR_WIDTH -1:0] reg_addr2;
wire [31:0] reg_data2;
wire reg_strb2;
integer fd, dummy;
initial begin
$dumpfile("axis_reg_map.vcd");
$dumpvars;
$dumplimit(2048000);
fd = $fopen("axis_reg_map_drivers.mem", "r");
if (fd == 0) begin
$display("Could not open file");
$finish;
end
while ($fgetc(
fd
) != "\n") begin
if ($feof(fd)) begin
$display("Error: file is in incorrect format");
$finish;
end
end
end
always #5 clk <= ~clk;
always @(posedge clk) begin
if ($feof(fd)) begin
$display("Reached end of drivers file");
#20 $finish;
end
#0.01
dummy = $fscanf(fd, "%x%b", cmd_in_TDATA, cmd_in_TVALID);
//Skip comments at end of line
while (!$feof(fd) && $fgetc(fd) != "\n");
end
wire [31:0] cmd_out_data1;
wire cmd_out_vld_1;
wire [31:0] cmd_out_data2;
wire cmd_out_vld_2;
axis_reg_map #(
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.ADDR(0), //Set this to be different for each
.RESET_TYPE(RESET_TYPE),
.PIPE_STAGE(PIPE_STAGE)
) DUT0 (
.clk(clk),
.rst(rst),
//Input command stream
.cmd_in_TDATA (cmd_in_TDATA),
.cmd_in_TVALID(cmd_in_TVALID),
//All the reg_maps are daisy-chained.
.cmd_out_TDATA (cmd_out_data1),
.cmd_out_TVALID(cmd_out_vld_1),
//Register update outputs, used by whatever is instantiating this module
.reg_addr(reg_addr0),
.reg_data(reg_data0),
.reg_strb(reg_strb0)
);
axis_reg_map #(
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.ADDR(1), //Set this to be different for each
.RESET_TYPE(RESET_TYPE),
.PIPE_STAGE(PIPE_STAGE)
) DUT1 (
.clk(clk),
.rst(rst),
//Input command stream
.cmd_in_TDATA (cmd_out_data1),
.cmd_in_TVALID(cmd_out_vld_1),
//All the reg_maps are daisy-chained.
.cmd_out_TDATA (cmd_out_data2),
.cmd_out_TVALID(cmd_out_vld_2),
//Register update outputs, used by whatever is instantiating this module
.reg_addr(reg_addr1),
.reg_data(reg_data1),
.reg_strb(reg_strb1)
);
axis_reg_map #(
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.ADDR(2), //Set this to be different for each
.RESET_TYPE(RESET_TYPE),
.PIPE_STAGE(PIPE_STAGE)
) DUT2 (
.clk(clk),
.rst(rst),
//Input command stream
.cmd_in_TDATA (cmd_out_data2),
.cmd_in_TVALID(cmd_out_vld_2),
//All the reg_maps are daisy-chained.
.cmd_out_TDATA (cmd_out_TDATA),
.cmd_out_TVALID(cmd_out_TVALID),
//Register update outputs, used by whatever is instantiating this module
.reg_addr(reg_addr2),
.reg_data(reg_data2),
.reg_strb(reg_strb2)
);
endmodule
| 7.834213 |
module axis_s (
input areset_n,
aclk,
output reg [31:0] data, // data that axis slave will receive
input ready, // user app is ready to accept data, so slave can receive a data
output reg tready,
input tvalid,
input tlast,
input [31:0] tdata,
output reg finish // transaction is completed
);
// handshake happened between master and slave
wire handshake;
assign handshake = tvalid & tready;
// tready
always @(posedge aclk)
if (~areset_n) tready <= 1'b0;
else if (ready && ~tready) // first time ready comes
tready <= 1'b1;
else if (handshake) // handshake happened, ready goes low
tready <= 1'b0;
else if (tready && ~ready && ~tvalid) // keep tready high, when user disables ready
tready <= 1'b1;
else tready <= tready; // keep the value of tready
// data
always @(posedge aclk)
if (~areset_n) data <= 1'b0;
else if (handshake) data <= tdata;
else data <= data;
always @(posedge aclk)
if (~areset_n) finish <= 0;
else if (handshake) finish <= 1'b1;
else if (finish == 1 && ready) finish <= 0;
else finish <= finish;
endmodule
| 7.874444 |
module AXIS_SCALE #(
parameter AXIS_TDATA_WIDTH = 32,
parameter IL = 31, //PIG data is 32 bits wide
parameter IR = 0,
parameter OL = 13, //DAC is 14 bits wide
parameter OR = 0,
parameter SIGNED = 1
) (
input clk,
input rst,
// Slave side
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_RAW_tdata,
input S_AXIS_RAW_tvalid,
output S_AXIS_RAW_tready,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] M_AXIS_SCALED_tdata,
output wire M_AXIS_SCALED_tvalid,
input wire M_AXIS_SCALED_tready
);
localparam integer SIZE_DIFF = (IL - IR) - (OL - OR);
//reg [AXIS_TDATA_WIDTH-1:0] SCALED_DATA;
//reg [OL-OR:0] SCALED_DATA;
//reg [AXIS_TDATA_WIDTH-1:0] NEW_BUS;
//assign M_AXIS_SCALED_tdata = NEW_BUS;
assign M_AXIS_SCALED_tvalid = S_AXIS_RAW_tvalid;
assign S_AXIS_RAW_tready = M_AXIS_SCALED_tready;
generate
//Shift down or pad as needed
if (SIGNED) begin
if (SIZE_DIFF > 0) begin
wire signed [IL-IR:0] DATA = S_AXIS_RAW_tdata[IL:IR];
wire [OL-OR:0] SCALED_DATA = DATA >>> SIZE_DIFF; //Must scale down to accomodate
assign M_AXIS_SCALED_tdata = {SCALED_DATA,{AXIS_TDATA_WIDTH-(OL-OR+1){1'b0}}} >> AXIS_TDATA_WIDTH-OL-1;
end else begin
wire signed [IL-IR:0] DATA = S_AXIS_RAW_tdata[IL:IR];
wire signed [OL-OR:0] SCALED_DATA = {{-SIZE_DIFF{DATA[IL-IR]}}, DATA}; //Fill SB's
assign M_AXIS_SCALED_tdata = {SCALED_DATA,{AXIS_TDATA_WIDTH-(OL-OR+1){1'b0}}} >> AXIS_TDATA_WIDTH-OL-1;
end
end else begin
if (SIZE_DIFF > 0) begin
wire [IL-IR:0] DATA = S_AXIS_RAW_tdata[IL:IR];
wire [OL-OR:0] SCALED_DATA = DATA >> SIZE_DIFF;
assign M_AXIS_SCALED_tdata = {SCALED_DATA,{AXIS_TDATA_WIDTH-(OL-OR+1){1'b0}}} >> AXIS_TDATA_WIDTH-OL-1;
end else begin
wire [IL-IR:0] DATA = S_AXIS_RAW_tdata[IL:IR];
wire [OL-OR:0] SCALED_DATA = {{SIZE_DIFF{1'b0}}, DATA};
assign M_AXIS_SCALED_tdata = {SCALED_DATA,{AXIS_TDATA_WIDTH-(OL-OR+1){1'b0}}} >> AXIS_TDATA_WIDTH-OL-1;
end
end
endgenerate
endmodule
| 9.198098 |
module axis_sim_record #(
// Master AXI Stream Data Width
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter OUTPUT_FILE = "../../stream_data_out.axi"
) (
// Part 1: System side signals
// Global Ports
input axi_aclk,
// Slave Stream Ports (interface to data path)
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
output reg [10:0] counter,
output reg activity_rec
);
integer f;
integer bubble_count = 0;
reg [8*2-1:0] terminal_flag;
assign s_axis_tready = 1;
initial begin
f = $fopen(OUTPUT_FILE, "w");
counter = 0;
end
always @(posedge axi_aclk) begin
if (s_axis_tvalid == 1'b1) begin
if (bubble_count != 0) begin
$fwrite(f, "*%0d\n", bubble_count);
bubble_count <= 0;
end
if (s_axis_tlast == 1'b1) begin
terminal_flag = ".";
counter <= counter + 1;
activity_rec <= 1;
end else begin
terminal_flag = ",";
activity_rec <= 1;
end
$fwrite(f, "%x, %x, %x%0s # %0d ns\n", s_axis_tdata, s_axis_tkeep, s_axis_tuser,
terminal_flag, $time);
end else begin
bubble_count <= bubble_count + 1;
activity_rec <= 0;
end
end
endmodule
| 8.461891 |
module axis_slr_register_source #(
parameter WIDTH = 8
) (
input wire clk,
input wire rst,
input wire din_valid,
input wire [WIDTH-1:0] din,
output wire din_ready,
output wire dout_valid,
output wire [WIDTH-1:0] dout,
input wire dout_ready
);
(* USER_SLL_REG="true" *)reg sll_valid = 1'b0;
(* USER_SLL_REG="true", shreg_extract="no" *)reg [WIDTH-1:0] sll_data;
(* USER_SLL_REG="true", keep="true" *)reg sll_ready = 1'b0;
(* keep="true" *)reg sll_ready_r = 1'b0;
// Register input, including ready signal
always @(posedge clk) begin
sll_data <= din;
sll_valid <= din_valid & sll_ready_r;
sll_ready <= dout_ready;
sll_ready_r <= sll_ready;
if (rst) sll_ready_r <= 1'b0;
end
assign dout_valid = sll_valid;
assign dout = sll_data;
assign din_ready = sll_ready_r;
endmodule
| 7.672458 |
module axis_slr_register_dest #(
parameter WIDTH = 8,
parameter DEPTH = 16
) (
// System Signals
input wire clk,
input wire rst,
// Slave side
input wire din_valid,
input wire [WIDTH-1:0] din,
output wire din_ready,
// Master side
output wire dout_valid,
output wire [WIDTH-1:0] dout,
input wire dout_ready
);
// Make sure SLL Registers are used for crossing SLR boundary
(* USER_SLL_REG="true" *)reg sll_valid = 1'b0;
(* USER_SLL_REG="true", shreg_extract="no" *)reg [WIDTH-1:0] sll_data;
(* USER_SLL_REG="true", keep="true" *)reg sll_ready = 1'b0;
// If FIFO is empty or downstream can accept we ready the input to avoid overflow
always @(posedge clk) begin
sll_ready <= dout_ready | ~dout_valid;
sll_data <= din;
sll_valid <= din_valid;
end
wire dout_ready_n;
simple_axis_srl_fifo #(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
) srl_fifo (
.clk(clk),
.rst(rst),
.din (sll_data),
.din_valid(sll_valid),
.dout (dout),
.dout_valid(dout_valid),
.dout_ready(dout_ready_n),
.count()
);
assign din_ready = sll_ready;
assign dout_ready_n = dout_ready & dout_valid;
endmodule
| 7.672458 |
module axis_slr_register #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH + 7) / 8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// FIFO depth in cycles
parameter FIFO_DEPTH = 16
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
// Merge AXIS data signals
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
wire [WIDTH-1:0] s_axis, m_axis;
wire s_valid, m_valid;
wire s_ready, m_ready;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET+:KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET+:ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET+:DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET+:USER_WIDTH] = s_axis_tuser;
endgenerate
assign m_axis_tdata = m_axis[DATA_WIDTH-1:0];
assign m_axis_tkeep = KEEP_ENABLE ? m_axis[KEEP_OFFSET+:KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign m_axis_tlast = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis[ID_OFFSET+:ID_WIDTH] : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis[DEST_OFFSET+:DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis[USER_OFFSET+:USER_WIDTH] : {USER_WIDTH{1'b0}};
assign s_valid = s_axis_tvalid;
assign m_ready = m_axis_tready;
assign m_axis_tvalid = m_valid;
assign s_axis_tready = s_ready;
wire [WIDTH-1:0] slr_axis;
wire slr_valid;
wire slr_ready;
// Seperate source and destination to enable assigning to pblocks accross SLR boundary
axis_slr_register_source #(
.WIDTH(WIDTH)
) slr_source (
.clk(clk),
.rst(rst),
.din (s_axis),
.din_valid(s_valid),
.din_ready(s_ready),
.dout (slr_axis),
.dout_valid(slr_valid),
.dout_ready(slr_ready)
);
axis_slr_register_dest #(
.WIDTH(WIDTH),
.DEPTH(FIFO_DEPTH)
) slr_dest (
.clk(clk),
.rst(rst),
.din (slr_axis),
.din_valid(slr_valid),
.din_ready(slr_ready),
.dout (m_axis),
.dout_valid(m_valid),
.dout_ready(m_ready)
);
endmodule
| 7.672458 |
module takes a single AXI-Stream input and duplicates it onto
// multiple AXI-Stream outputs. This block correctly handles the somewhat
// tricky flow-control logic so that the AXI-Stream handshake protocol is
// honored at all top-level ports.
//
// The internal buffering is finite, so if the data from any of the output
// ports can't be consumed then the flow-control logic will cause the input
// to stall (i.e., s_axis_tready will deassert).
//
// Parameters:
//
// DATA_W : The bit width of tdata for all ports.
// NUM_PORTS : The number of output ports on which to duplicate the input.
// INPUT_REG : Set to 1 to add an input register stage to break combinatorial
// paths. Set to 0 to allow combinatorial input paths.
//
module axis_split #(
parameter DATA_W = 32,
parameter NUM_PORTS = 4,
parameter INPUT_REG = 0
) (
input wire clk,
input wire rst,
// Input AXI-Stream
input wire [DATA_W-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
// Output AXI-Streams
output wire [DATA_W*NUM_PORTS-1:0] m_axis_tdata,
output wire [ NUM_PORTS-1:0] m_axis_tvalid,
input wire [ NUM_PORTS-1:0] m_axis_tready
);
// Output of the input-register stage
wire [DATA_W-1:0] reg_tdata;
wire reg_tvalid;
wire reg_tready;
// Input to the Output FIFO stage
wire [DATA_W*NUM_PORTS-1:0] fifo_tdata;
wire [ NUM_PORTS-1:0] fifo_tvalid;
wire [ NUM_PORTS-1:0] fifo_tready;
// Indicates all output FIFOs are ready for a transfer
wire all_fifo_tready;
//---------------------------------------------------------------------------
// Optional Input Register
//---------------------------------------------------------------------------
if (INPUT_REG) begin : gen_input_reg
axi_fifo_flop2 #(
.WIDTH (DATA_W)
) axi_fifo_flop2_i (
.clk (clk),
.reset (rst),
.clear (1'b0),
.i_tdata (s_axis_tdata),
.i_tvalid (s_axis_tvalid),
.i_tready (s_axis_tready),
.o_tdata (reg_tdata),
.o_tvalid (reg_tvalid),
.o_tready (reg_tready),
.space (),
.occupied ()
);
end else begin : gen_no_input_reg
assign reg_tdata = s_axis_tdata;
assign reg_tvalid = s_axis_tvalid;
assign s_axis_tready = reg_tready;
end
//---------------------------------------------------------------------------
// Forking Logic
//---------------------------------------------------------------------------
assign all_fifo_tready = &fifo_tready;
// Data transfer occurs when we have valid data on the input and all output
// FIFOs are ready to accept data. Note that having tvalid depend on tready
// is normally not allowed, but the FIFO has been chosen to tolerate this.
assign reg_tready = all_fifo_tready;
assign fifo_tvalid = { NUM_PORTS {all_fifo_tready & reg_tvalid} };
assign fifo_tdata = { NUM_PORTS {reg_tdata} };
//---------------------------------------------------------------------------
// Output FIFOs
//---------------------------------------------------------------------------
genvar i;
for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ports
// We use axi_fifo_short specifically because it can tolerate tvalid
// de-asserting at any time. This is normally not allowed by AXI-Stream.
axi_fifo_short #(
.WIDTH (DATA_W)
) axi_fifo_short_i (
.clk (clk),
.reset (rst),
.clear (1'b0),
.i_tdata (fifo_tdata[i*DATA_W+:DATA_W]),
.i_tvalid (fifo_tvalid[i]),
.i_tready (fifo_tready[i]),
.o_tdata (m_axis_tdata[i*DATA_W+:DATA_W]),
.o_tvalid (m_axis_tvalid[i]),
.o_tready (m_axis_tready[i]),
.space (),
.occupied ()
);
end
endmodule
| 7.910804 |
module axis_srl_register #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [WIDTH-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
wire [WIDTH-1:0] s_axis;
wire [WIDTH-1:0] m_axis = data_reg[ptr_reg];
assign s_axis_tready = !full_reg;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET+:KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET+:ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET+:DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET+:USER_WIDTH] = s_axis_tuser;
endgenerate
assign m_axis_tvalid = valid_reg[ptr_reg];
assign m_axis_tdata = m_axis[DATA_WIDTH-1:0];
assign m_axis_tkeep = KEEP_ENABLE ? m_axis[KEEP_OFFSET+:KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign m_axis_tlast = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis[ID_OFFSET+:ID_WIDTH] : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis[DEST_OFFSET+:DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis[USER_OFFSET+:USER_WIDTH] : {USER_WIDTH{1'b0}};
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
end else begin
// transfer empty to full
full_reg <= !m_axis_tready && m_axis_tvalid;
// transfer in if not full
if (s_axis_tready) begin
data_reg[0] <= s_axis;
valid_reg[0] <= s_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (m_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
| 7.707802 |
module axis_stat #(
parameter KEEP_WIDTH = 8,
// If KEEP_ENABLE is not 1, byte_count represents word count
parameter KEEP_ENABLE = KEEP_WIDTH > 1,
parameter BYTE_COUNT_WIDTH = 32,
parameter FRAME_COUNT_WIDTH = 32
) (
input wire clk,
input wire rst,
input wire clear,
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
input wire monitor_drop_pulse,
output reg [ BYTE_COUNT_WIDTH-1:0] byte_count,
output reg [FRAME_COUNT_WIDTH-1:0] frame_count,
output reg [FRAME_COUNT_WIDTH-1:0] drop_count,
output reg [FRAME_COUNT_WIDTH-1:0] stall_count
);
integer i, bit_cnt;
always @(posedge clk) begin
// valid transfer cycle
if (monitor_axis_tready && monitor_axis_tvalid) begin
if (KEEP_ENABLE) begin
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH - i)) bit_cnt = i;
end
byte_count <= byte_count + bit_cnt;
end else begin
byte_count <= byte_count + 1;
end
if (monitor_axis_tlast) frame_count <= frame_count + 1;
end
if (!monitor_axis_tready && monitor_axis_tvalid) stall_count <= stall_count + 1;
if (monitor_drop_pulse) drop_count <= drop_count + 1;
if (rst || clear) begin
byte_count <= {BYTE_COUNT_WIDTH{1'b0}};
frame_count <= {FRAME_COUNT_WIDTH{1'b0}};
drop_count <= {FRAME_COUNT_WIDTH{1'b0}};
stall_count <= {FRAME_COUNT_WIDTH{1'b0}};
end
end
endmodule
| 7.012501 |
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