code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
modules below for axi connections
module axidelay #(
parameter MAX_DELAY = 3
) (
// Master interface. Connect to a slave interface
output reg m_valid,
input m_ready,
// Slave interface. Connect to a master interface
input s_valid,
output reg s_ready,
input clk,
input rst
);
ge... | 7.587638 |
module axidelayRead #(
parameter MAX_DELAY = 3
) (
// Connect directly to the same named axi read wires in the master interface
output m_rvalid,
input m_rready,
// Connect directly to the same named axi read wires in the slave interface
input s_rvalid,
output s_rready,
input clk,
... | 8.332032 |
module axidelayWrite #(
parameter MAX_DELAY = 3
) (
// Connect directly to the same named axi write wires in the master interface
input m_wvalid,
output m_wready,
// Connect directly to the same named axi write wires in the slave interface
output s_wvalid,
input s_wready,
input clk,
... | 8.202073 |
module axil2iob #(
parameter AXIL_ADDR_W = 32, // Width of address bus in bits
parameter AXIL_DATA_W = 32 // Width of data bus in bits
) (
// AXI-4 lite slave interface
`include "axil_s_port.vh"
// Native master interface
output valid,
output [ AXIL_ADDR_W-1:0] addr,... | 8.99491 |
module axil2native_adapter #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8)
) (
input clk,
input rst,
// AXI4-lite slave interf... | 8.503186 |
module toggle_detect #(
parameter integer data_width = 8
) (
output reg [data_width-1:0] data_out,
input [data_width-1:0] data_in,
input clk,
input reset
);
reg [data_width-1:0] data_in_1;
reg [data_width-1:0] data_in_2;
always @(posedge clk) begin
if (reset) begin
{data_in_2, data... | 6.992692 |
module axiLite_debug (
input M_AXI_ACLK,
input M_AXI_ARESETN,
input [31:0] M_AXI_AWADDR,
input M_AXI_AWVALID,
input M_AXI_AWREADY,
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WVALID,
input M_AXI_WREADY,
input [ 1:0] M_... | 6.645668 |
module axilite_dev #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports... | 6.885181 |
module axilite_mux (
input [ 15:0] w_strb_in,
input [127:0] w_data_in,
input ar_valid_in,
input ar_ready_in,
input [ 31:0] ar_addr_in,
input user_clk,
input [ 31:0] r_data_in,
output [127:0] r_data_out,
output [ 31:0] w_data_out
);
reg [3:0] rd_addr... | 7.920252 |
module axilite_naive_bridge (
input axi_clk,
input axi_resetn,
input [31:0] axi_awaddr,
input [0:0] axi_awvalid,
output reg [0:0] axi_awready,
input [31:0] axi_wdata,
input [3:0] axi_wstrb,
input [0:0] axi_wvalid,
output reg [0:0] axi_wready,
output [1:0] axi_bresp,
output r... | 7.418709 |
module
*/
module axil_reg_if #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
(
... | 8.343407 |
module (read)
*/
module axil_reg_if_rd #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOUT... | 8.317208 |
module (write)
*/
module axil_reg_if_wr #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Timeout delay (cycles)
parameter TIMEOU... | 7.575563 |
module axil_to_ni_regport #(
parameter RP_AWIDTH = 16,
parameter RP_DWIDTH = 32,
parameter TIMEOUT = 512
) (
input s_axi_aclk,
input s_axi_areset,
// AXI4lite interface
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wd... | 7.912545 |
module AxiModule #(
parameter DATA_WIDTH_SLAVE = 32,
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8,
parameter ADDRESS_WIDTH_SLAVE = 8,
parameter DATA_WIDTH_MASTER = 32,
parameter STROBE_WIDTH_MASTER = DATA_WIDTH_MASTER / 8,
parameter ADDRESS_WIDTH_MASTER = 8
) (
input read,
input w... | 7.120443 |
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
... | 7.419624 |
module axis2axi #(
parameter AXI_ADDR_W = 0,
parameter AXI_DATA_W = 32, // We currently only support 4 byte transfers
parameter AXI_LEN_W = 8,
parameter AXI_ID_W = 1,
parameter BURST_W = 0,
parameter BUFFER_W = BURST_W + 1
) (
// Configuration (AXIS In)
input [AXI_ADDR_... | 8.59901 |
module AXIS2VGA_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface params_AXI
parameter integer C_params_AXI_DATA_WIDTH = 32,
parameter integer C_params_AXI_ADDR_WIDTH = 4,
// Parameter... | 7.330842 |
module axis2wb (
input wire i_clk,
input wire i_rst,
input wire [0:0] i_wb_sel,
input wire i_wb_stb,
output wire [9:0] o_wb_rdt,
output reg o_wb_ack,
input wire [7:0] i_tdata,
input wire i_tlast,
input wire i_tvalid,
output wire o... | 7.702976 |
module axisFIFO (
m_aclk,
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tuser,
s_axis_tstrb,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tuser,
m_axis_tstrb,
m_axis_tlast
);
parameter C_AXIS_DATA_WIDTH = 32;
pa... | 8.688696 |
module axislave_stub ( /*AUTOARG*/
// Outputs
s_axi_arready,
s_axi_awready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_rid,
s_axi_rdata,
s_axi_rlast,
s_axi_rresp,
s_axi_rvalid,
s_axi_wready,
// Inputs
s_axi_aclk,
s_axi_aresetn,
s_axi_arid,
s_axi_arad... | 8.028731 |
module axisrandom #(
// {{{
localparam C_AXIS_DATA_WIDTH = 32
// }}}
) (
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
output reg M_AXIS_TVALID,
input wire M_AXIS_TREADY,
... | 8.692105 |
module axistream_add_tlast (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
add_tlast
);
parameter DATA_WIDTH = 8;
input clk;
input rst;
input src_tvalid;
output src_tready;
input [DATA_WIDTH-1:0] src_tdata;
out... | 6.506958 |
module axistream_pack (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast, //! may only be raised on multiples of NUM_PACK of src
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
tlast_align_err //! src_tlast && src_tvalid at invalid time for src_tlast
);
parame... | 6.718493 |
module axistream_snooper # (parameter
DATA_WIDTH = 64,
ADDR_WIDTH = 9,
PESSIMISTIC = 0
)(
input wire clk,
//AXI Stream interface
input wire [DATA_WIDTH-1:0] TDATA,
input wire TVALID,
input wire TREADY, //Yes, this is an input. Remember that we're snooping!
input wire TLAST,
//Interface to packet mem
outp... | 6.916855 |
module axistream_unpack (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast
);
parameter DATA_WIDTH = 8;
parameter NUM_PACK = 4;
parameter BIG_ENDIAN = 1'b0; //! if true, src's least signicant word is first
input... | 7.782006 |
module axistream_wait_until (
clk,
rst,
src_tvalid,
src_tready,
src_tdata,
src_tlast,
dest_tvalid,
dest_tready,
dest_tdata,
dest_tlast,
go //! raise to allow full packet of data through
);
parameter DATA_WIDTH = 8;
input clk;
input rst;
input src_tvalid;
output... | 7.622848 |
module axis_2_fifo_adapter #(
parameter AXIS_DATA_WIDTH = 32,
parameter FIFO_DATA_WIDTH = AXIS_DATA_WIDTH
) (
input wire i_axis_tuser,
input wire i_axis_tvalid,
output wire o_axis_tready,
input wire ... | 7.467097 |
module axis_bitonic_comp #(
parameter DATA_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*2-1:0] s_axis_tdata,
input wire [USER_WIDTH*2-1:0] s_axis_tuser,
input wire s_axis_tvalid,
... | 7.872602 |
module axis_bitonic_node #(
parameter DATA_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] s_axis_tdata,
input wire [USER_WIDTH*2**(ORDER+1)-1:0] ... | 7.872602 |
module axis_bram_reader #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10,
parameter CONTINUOUS = "FALSE"
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0]... | 6.708209 |
module axis_bram_writer #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Slave side
output wire ... | 7.115728 |
module axis_cc_flow_ctrl (
input s_axis_clk,
input s_aresetn,
input s_axis_valid,
output s_axis_ready,
input m_axis_clk,
input m_aresetn,
output m_axis_valid,
input m_axis_ready
);
reg wa;
wire wb;
wire ra;
reg rb;
sync_reg s_to_m (
.clk(m_axis_clk),
.rst... | 7.543595 |
module axis_clock_converter_0 (
s_axis_aresetn,
m_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
s_axis_tuser,
m_axis_aclk,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
m_axis_t... | 7.595528 |
module axis_clock_converter_v1_1_23_axisc_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
/////////... | 7.595528 |
module, you can! I only take care of this messy logic once.
And anyway, I'd like my cores to have conditional side channels anyway.
In the end, this module is noting more than wires, but it tricks Vivado into
doing what I want
Anyway, each side channel has an "in enable" and an "out enable". This means:
in | out ... | 6.556001 |
module axis_concat # (
parameter DATA_WIDTH = 32,
parameter IN_ENABLE_KEEP = 0,
parameter OUT_ENABLE_KEEP = 0,
parameter IN_ENABLE_LAST = 1,
parameter OUT_ENABLE_LAST = 1,
parameter IN_ENABLE_DEST = 0,
parameter OUT_ENABLE_DEST = 0,
parameter DEST_WIDTH = 16,
para... | 6.859422 |
module axis_conform_check #(
parameter tkeep_encoded = 0,
parameter axis_data_width = 256,
parameter axis_tkeep_width = axis_data_width / 8, // 32 bit
parameter axis_tkeep_encoded_width = $clog2(axis_tkeep_width), // 5 bit
parameter max_packet_size_counter = 6553... | 6.932312 |
module axis_constant #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
assign m_axis_tdata = c... | 6.777424 |
module axis_control_if #(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
) (
... | 8.842868 |
module axis_cpu_tb # (
parameter CODE_ADDR_WIDTH = 10,
parameter REG_ADDR_WIDTH = 4, //Seems good enough
parameter CPU_ID_WIDTH = 12,
parameter [CPU_ID_WIDTH-1:0] CPU_ID = 0, //Basically like a base address, used for AXIS register map
parameter PESS = 0
);
reg clk = 0;
reg rst = 0;
... | 7.979105 |
module axis_ctrlport_reg #(
parameter ADDR = 0,
parameter USE_ADDR_LAST = 0,
parameter ADDR_LAST = ADDR + 1,
parameter DWIDTH = 32,
parameter USE_FIFO = 0,
parameter FIFm_SIZE = 5,
parameter DATA_AT_RESET = 0,
parameter VALID_AT_RESET = 0,
paramete... | 6.881535 |
module Axis_Ctrl_20BitWidth (
Clk,
gRst,
Addr,
MCUportL,
WR,
CS,
Din,
PosLock,
Ref,
Protect,
MO,
nStanby,
DRVRst,
PlsOut,
Dir,
Torque1,
Torque2,
DQtoMCU
);
/*
Axis_Ctrl Axis_Ctrl(
.Clk(),
.gRst(),
.Addr(),
.MCUportL(),
.WR(... | 6.586427 |
module axis_dac (
input wire clk,
input wire rst,
input wire [7:0] s_axis_tdata,
input wire s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tid,
input wire s_axis_tdest,
input wire s_axis_tuser,
output wire dac_o... | 6.860268 |
module axis_delay #(
parameter DELAY_WIDTH = 9 //Delay counter width
) (
input clk, //i-1
input reset_, //i-1
//AXIS Bus In
input axis_m_tvalid, //i-1, Valid signal from master
input axis_m_tlast, //i-1, Last signal from master
output axis_m_tready, //o-1, Ready signal to master
... | 8.036454 |
module that narrows the input
// sample with by a factor of RATIO.
// NOTE: This module has end-to-end combanitorial paths. For a
// pipelined version, please use axis_width_conv
//
// Parameters:
// - OUT_DATA_W: The bitwidth of the output data bus. The width of the
// input data bus is O... | 9.467984 |
module axis_dropper #(
parameter PORT_COUNT = 4,
parameter REG_FOR_DROP = 0,
parameter SAME_CYCLE_DROP = 0,
parameter DROP_CNT_WIDTH = 32
) (
input wire clk,
input wire rst,
input wire [ PORT_COUNT-1:0] drop,
output reg [PORT_COUNT*DROP_CNT_WIDTH-1:0] drop_count... | 7.1209 |
module axis_endianness_converter #(
parameter DATA_WIDTH = 8,
parameter HAS_DATA = 1,
parameter HAS_KEEP = 0,
parameter HAS_LAST = 0,
parameter HAS_READY = 0,
parameter HAS_DEST = 0,
parameter HAS_USER = 0,
parameter HAS_ID = 0,
parameter HAS_STRB = 0,
parameter ID_WIDTH = 1,
... | 7.098643 |
module axis_eth_fcs #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH / 8)
) (
in... | 8.316486 |
module axis_fifo32 #(
parameter WIDTH = 32,
parameter DEEP_BITS = 5
) (
input clk,
input axisrst,
input [WIDTH-1:0] axis_rx_tdata,
input axis_rx_tvalid,
output axis_rx_tready,
output [WIDTH-1:0] axis_tx_tdata,
output axis_tx_tvalid,
input ... | 6.843848 |
module axis_fifo_tb (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) bus1 (
.clock(clock),
.resetn(resetn),
.data(idata),
... | 6.696043 |
module axis_file_loader #(
parameter filename = "data.bin",
parameter data_width = 8,
parameter delay_tic = 100
) (
input axis_aclk,
input axis_aresetn,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [8*data_width-1:0] m_axis_tdata,
output reg [data_width-1:0] m_axis_tk... | 6.992658 |
module axis_file_loader_tb ();
reg clk = 0;
reg rst = 1;
wire rst_n;
reg cfg_prepared = 0;
assign rst_n = !rst;
axis_file_loader loader_inst (
.axis_aclk(clk),
.axis_aresetn(rst_n),
.m_axis_tvalid(),
.m_axis_tready(1'b1),
.m_axis_tdata(),
.m_axis_tkeep(),
.m_a... | 6.992658 |
module AXIS_FIR_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 16,
// Parameters of Axi Master Bus Interface M_AXIS
parameter integer... | 9.155316 |
module is an AXI Stream passthrough, but with options to modify the
underlying stream. Supported operations:
- Injecting flits
- Forcing ready to low (i.e. pausing)
- Copying flits to another interface (i.e. logging)
- Dropping flits (while potentially logging them)
This module is designed to be used ... | 8.350248 |
module axis_governor_glue_log (
input wire in_vld,
input wire out_rdy,
input wire log_en,
input wire log_rdy,
input wire inj_vld,
input wire pause,
input wire drop,
output wire in_rdy,
output wire out_vld,
output wire log_vld,
output wire inj_rdy
);
//(~inj_vld && out_rdy... | 8.099137 |
module axis_gpio_reader #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
inout wire [AXIS_TDATA_WIDTH-1:0] gpio_data,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WID... | 7.502314 |
module axis_headerizer # (
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 16,
parameter ID_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter RESET_TYPE = `NO_RESET,
parameter ENABLE_TLAST_HACK = 0
) (
input wire clk,
input wire rst,
`in_axis_kl(sides, DATA_WIDTH),
input wir... | 6.637668 |
module axis_headerizer_tb #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 16,
parameter ID_WIDTH = 16,
parameter USER_WIDTH = 8,
parameter RESET_TYPE = `NO_RESET
);
reg clk = 0;
reg rst = 0;
`sim_in_axis_kl(sides, DATA_WIDTH);
reg [DEST_WIDTH -1:0] sides_TDEST = 0;
reg [ ID_WIDTH ... | 6.637668 |
module axis_histogram #(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 14
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
output wire s_axis_tready,
input wire [... | 7.368018 |
module is used along with axis_img_border_gen.v to
* to remove the image boarder from the stream.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "Lic... | 8.785935 |
module axis_inf (
// adi interface
clk,
rst,
valid,
last,
data,
// xilinx interface
inf_valid,
inf_last,
inf_data,
inf_ready
);
// parameter for data width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adi interface
input clk;
input rst;
... | 7.795894 |
module axis_infrastructure_v1_1_0_cdc_handshake #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_WIDTH = 32,
parameter inte... | 7.431915 |
module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
mod... | 7.670485 |
module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
mod... | 7.670485 |
module axis_infrastructure_v1_1_0_cdc_handshake #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_WIDTH = 32,
parameter inte... | 7.431915 |
module axis_interconnect #(
parameter CHANNELS_IN = 4,
parameter CHANNELS_OUT = 1,
parameter DATA_WIDTH = 8,
parameter USER_WIDTH = 2
) (
input wire aclk,
input wire aresetn,
input wire [CHANNELS_IN*DATA_WIDTH-1:0] s_axis_tdata,
input wire [CHANNELS_IN*$clog2(CHANNELS_OUT)-1:0] s_ax... | 7.015684 |
module axis_arbiter #(
parameter CHAN_NUM = 4,
parameter DATA_WIDTH = 8,
parameter DEST_INDEX = 0,
parameter DEST_WIDTH = 4,
parameter USER_WIDTH = 2
) (
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH*CHAN_NUM-1:0] s_axis_tdata,
input wire [USER_WIDTH*CHAN_NUM-1:0] s_a... | 6.947342 |
module axis_keyer #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
input wire key_flag,... | 7.592489 |
module axis_lfsr #(
parameter integer AXIS_TDATA_WIDTH = 64
) (
// System signals
input wire aclk,
input wire aresetn,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
... | 6.938058 |
module axis_ll_bridge #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,... | 9.332818 |
module is to loopback the AXI4-Stream that is produced
// by the OPED to the stream that is consumed by the OPED. In this way, this
// module can stand-in for the OPED during development; and be repaled with
// Input/Output arbiters when ready. This module allows testing of the DMA
// capabilities of OPED block with mi... | 6.64491 |
module axis_loopback_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_head... | 8.141849 |
module axis_m (
input areset_n,
input aclk,
input [31:0] data,
input send,
input tready,
output reg tvalid,
output tlast,
output reg [31:0] tdata,
output reg finish
);
reg [31:0] data_buf; // buffer to keep the send data from change
always @(posedge send or negedge areset_n)... | 7.369554 |
module axis_master (
aclk,
aresetn,
tvalid,
tready,
tdata
);
input aclk, aresetn, tready;
output reg tvalid;
output reg [7:0] tdata;
reg [31:0] state;
always @(posedge aclk) begin
if (!aresetn) begin
state <= 314159265;
tvalid <= 0;
tdata <= 'bx;
end else begin... | 6.793576 |
module axis_mux4 (
input s_axis_clk,
input s_arstn,
input m_axis_tready,
output [63:0] m_axis_tdata,
output [ 7:0] m_axis_tkeep,
output m_axis_tlast,
output m_axis_tvalid,
output s0_axis_tready,
input [63:0] s0_axis_tdata,
input [ 7:0] s0_axis_tke... | 7.905159 |
module axis_packet_generator_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S0_AXI
parameter integer C_S0_AXI_DATA_WIDTH = 32,
parameter integer C_S0_AXI_ADDR_WIDTH = 5,
// Paramete... | 7.124541 |
modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to ... | 8.081644 |
module axis_red_pitaya_adc #(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,
input wire ... | 8.024803 |
module axis_red_pitaya_dac #(
parameter integer DAC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// PLL signals
input wire aclk,
input wire ddr_clk,
input wire locked,
// DAC signals
output wire dac_clk,
output wire dac_rst... | 8.024803 |
module axis_register_slice_32 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xil... | 7.186837 |
module axis_register_slice_v1_1_22_tdm_sample (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire slow_clk,
input wire fast_clk,
output wire sample_cycl... | 7.186837 |
module axis_register_slice_v1_1_22_test_master #(
parameter integer C_DATA_WIDTH = 32
) (
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Master side
(* dont_touch="true" *) output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
(* dont_touch="true" *) output wire M_... | 7.186837 |
module axis_register_slice_v1_1_22_test_slave #(
parameter integer C_DATA_WIDTH = 32
) (
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
(* dont_touch="true" *) output wire S_REA... | 7.186837 |
module axis_register_slice_v1_1_22_srl_rtl #(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
) (
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire... | 7.186837 |
module="yes" *)
module axis_register_slice_v1_1_22_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ACLKEN,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
/... | 7.483958 |
module axis_register_slice_v1_1_22_auto_src #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire ACLKEN,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DA... | 7.186837 |
module axis_register_slice_v1_1_22_auto_dest #(
parameter integer C_DATA_WIDTH = 32
) (
input wire ACLK,
input wire ACLKEN,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DA... | 7.186837 |
module axis_register_tb (
input wire clock,
input wire resetn,
output wire [1:0] size,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst1 (
.clock(clo... | 7.186837 |
module axis_reg_map # (
parameter REG_ADDR_WIDTH = 4,
parameter ADDR_WIDTH = 12,
parameter [ADDR_WIDTH -1:0] ADDR = 0, //Set this to be different for each
parameter RESET_TYPE = `NO_RESET,
parameter PIPE_STAGE = 1
) (
input wire clk,
input wire rst,
//Input command stream
input... | 8.284532 |
module dbg_guv_tb #(
parameter REG_ADDR_WIDTH = 4,
parameter ADDR_WIDTH = 12,
parameter [ADDR_WIDTH -1:0] ADDR = 0, //Set this to be different for each
parameter RESET_TYPE = `NO_RESET,
parameter PIPE_STAGE = 1
);
reg clk = 0;
reg rst = 0;
//Input command stream
reg [31:0] cmd_in_TDATA = ... | 7.834213 |
module axis_s (
input areset_n,
aclk,
output reg [31:0] data, // data that axis slave will receive
input ready, // user app is ready to accept data, so slave can receive a data
output reg tready,
input tvalid,
input tlast,
... | 7.874444 |
module AXIS_SCALE #(
parameter AXIS_TDATA_WIDTH = 32,
parameter IL = 31, //PIG data is 32 bits wide
parameter IR = 0,
parameter OL = 13, //DAC is 14 bits wide
parameter OR = 0,
parameter SIGNED = 1
) (
input clk,
input rst,
// Slave s... | 9.198098 |
module axis_sim_record #(
// Master AXI Stream Data Width
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter OUTPUT_FILE = "../../stream_data_out.axi"
) (
// Part 1: System side signals
// Global Ports
input axi_aclk,
// Slave Stream Ports (interface to... | 8.461891 |
module axis_slr_register_source #(
parameter WIDTH = 8
) (
input wire clk,
input wire rst,
input wire din_valid,
input wire [WIDTH-1:0] din,
output wire din_ready,
output wire dout_valid,
output wire [WIDTH-1:0] dout,
input wire do... | 7.672458 |
module axis_slr_register_dest #(
parameter WIDTH = 8,
parameter DEPTH = 16
) (
// System Signals
input wire clk,
input wire rst,
// Slave side
input wire din_valid,
input wire [WIDTH-1:0] din,
output wire din_ready,
// Master side
output wire ... | 7.672458 |
module axis_slr_register #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH + 7) / 8),
// Propagate tlast signal
parameter L... | 7.672458 |
module takes a single AXI-Stream input and duplicates it onto
// multiple AXI-Stream outputs. This block correctly handles the somewhat
// tricky flow-control logic so that the AXI-Stream handshake protocol is
// honored at all top-level ports.
//
// The internal buffering is finite, so if the data from any of ... | 7.910804 |
module axis_srl_register #(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
// Propagate tlast signal
parameter LAST_EN... | 7.707802 |
module axis_stat #(
parameter KEEP_WIDTH = 8,
// If KEEP_ENABLE is not 1, byte_count represents word count
parameter KEEP_ENABLE = KEEP_WIDTH > 1,
parameter BYTE_COUNT_WIDTH = 32,
parameter FRAME_COUNT_WIDTH = 32
) (
input wire clk,
input wire rst,
input wire clear,
in... | 7.012501 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.