code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axis_stemlab_sdr_adc #(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
// ADC signals
output wire adc_csn,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_b,
// Master side
output wire m_axis_tvalid,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata
);
localparam PADDING_WIDTH = AXIS_TDATA_WIDTH / 2 - ADC_DATA_WIDTH;
reg [ADC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [ADC_DATA_WIDTH-1:0] int_dat_b_reg;
always @(posedge aclk) begin
int_dat_a_reg <= adc_dat_a;
int_dat_b_reg <= adc_dat_b;
end
assign adc_csn = 1'b1;
assign m_axis_tvalid = 1'b1;
assign m_axis_tdata = {
{(PADDING_WIDTH + 1) {int_dat_b_reg[ADC_DATA_WIDTH-1]}},
~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
{(PADDING_WIDTH + 1) {int_dat_a_reg[ADC_DATA_WIDTH-1]}},
~int_dat_a_reg[ADC_DATA_WIDTH-2:0]
};
endmodule
| 7.488347 |
module axis_stemlab_sdr_dac #(
parameter integer DAC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// PLL signals
input wire aclk,
input wire ddr_clk,
input wire wrt_clk,
input wire locked,
// DAC signals
output wire dac_clk,
output wire dac_rst,
output wire dac_sel,
output wire dac_wrt,
output wire [DAC_DATA_WIDTH-1:0] dac_dat,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [DAC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [DAC_DATA_WIDTH-1:0] int_dat_b_reg;
reg int_rst_reg;
wire [DAC_DATA_WIDTH-1:0] int_dat_a_wire;
wire [DAC_DATA_WIDTH-1:0] int_dat_b_wire;
assign int_dat_a_wire = s_axis_tdata[DAC_DATA_WIDTH-1:0];
assign int_dat_b_wire = s_axis_tdata[AXIS_TDATA_WIDTH/2+DAC_DATA_WIDTH-1:AXIS_TDATA_WIDTH/2];
genvar j;
always @(posedge aclk) begin
if (~locked | ~s_axis_tvalid) begin
int_dat_a_reg <= {(DAC_DATA_WIDTH) {1'b0}};
int_dat_b_reg <= {(DAC_DATA_WIDTH) {1'b0}};
end else begin
int_dat_a_reg <= {int_dat_a_wire[DAC_DATA_WIDTH-1], ~int_dat_a_wire[DAC_DATA_WIDTH-2:0]};
int_dat_b_reg <= {int_dat_b_wire[DAC_DATA_WIDTH-1], ~int_dat_b_wire[DAC_DATA_WIDTH-2:0]};
end
int_rst_reg <= ~locked | ~s_axis_tvalid;
end
ODDR ODDR_rst (
.Q (dac_rst),
.D1(int_rst_reg),
.D2(int_rst_reg),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_sel (
.Q (dac_sel),
.D1(1'b0),
.D2(1'b1),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_wrt (
.Q (dac_wrt),
.D1(1'b0),
.D2(1'b1),
.C (wrt_clk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
ODDR ODDR_clk (
.Q (dac_clk),
.D1(1'b0),
.D2(1'b1),
.C (ddr_clk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
generate
for (j = 0; j < DAC_DATA_WIDTH; j = j + 1) begin : DAC_DAT
ODDR ODDR_inst (
.Q (dac_dat[j]),
.D1(int_dat_a_reg[j]),
.D2(int_dat_b_reg[j]),
.C (aclk),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
assign s_axis_tready = 1'b1;
endmodule
| 7.488347 |
module axis_stepper #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire trg_flag,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
assign s_axis_tready = trg_flag;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tvalid = s_axis_tvalid;
endmodule
| 7.009722 |
module axis_stopper #(
parameter PORT_COUNT = 4,
parameter REG_FOR_EN = 0
) (
input wire clk,
input wire rst,
input wire [PORT_COUNT-1:0] enable,
input wire [PORT_COUNT-1:0] s_axis_tvalid,
input wire [PORT_COUNT-1:0] s_axis_tlast,
output wire [PORT_COUNT-1:0] s_axis_tready,
output wire [PORT_COUNT-1:0] m_axis_tvalid,
output wire [PORT_COUNT-1:0] m_axis_tlast,
input wire [PORT_COUNT-1:0] m_axis_tready
);
// Register enable input if necessary
reg [PORT_COUNT-1:0] enable_r;
generate
if (REG_FOR_EN) begin
always @(posedge clk)
if (rst) enable_r <= {PORT_COUNT{1'b1}};
else enable_r <= enable;
end else begin
always @(*) enable_r = enable;
end
endgenerate
// Detect Start of Packet
reg [PORT_COUNT-1:0] SoP;
integer i;
always @(posedge clk)
if (rst) SoP <= {PORT_COUNT{1'b1}};
else
for (i = 0; i < PORT_COUNT; i = i + 1)
if (s_axis_tvalid[i] && s_axis_tready[i]) // If there was a transaction
SoP[i] <= s_axis_tlast[i]; // SoP becomes 1 only after tlast
// Combinational logic for the outputs.
// Blocking happens only from start of a packet until enable is re-asserted
wire [PORT_COUNT-1:0] block = SoP & ~enable_r;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tvalid = s_axis_tvalid & ~block;
assign s_axis_tready = m_axis_tready & ~block;
endmodule
| 7.707302 |
module to monitor a an AXI-Stream link and gather various
// metric about packets and the stream in general
module axis_strm_monitor #(
parameter WIDTH = 64,
parameter COUNT_W = 32,
parameter PKT_LENGTH_EN = 0,
parameter PKT_CHKSUM_EN = 0,
parameter PKT_COUNT_EN = 0,
parameter XFER_COUNT_EN = 0
)(
// Clocks and resets
input wire clk,
input wire reset,
// Stream to monitor
input wire [WIDTH-1:0] axis_tdata,
input wire axis_tlast,
input wire axis_tvalid,
input wire axis_tready,
// Packet Stats
output wire sop,
output wire eop,
output reg [15:0] pkt_length = 16'd0,
output wire [WIDTH-1:0] pkt_chksum,
// Stream Stats
output reg [COUNT_W-1:0] pkt_count = {COUNT_W{1'b0}},
output reg [COUNT_W-1:0] xfer_count = {COUNT_W{1'b0}}
);
//----------------------------
// Packet specific
//----------------------------
reg pkt_head = 1'b1;
wire xfer = axis_tvalid & axis_tready;
assign sop = pkt_head & xfer;
assign eop = xfer & axis_tlast;
always @(posedge clk) begin
if (reset) begin
pkt_head <= 1'b1;
end else begin
if (pkt_head) begin
if (xfer)
pkt_head <= ~eop;
end else begin
if (eop)
pkt_head <= 1'b0;
end
end
end
generate if (PKT_LENGTH_EN) begin
// Count the number of lines (transfers) in a packet
always @(posedge clk) begin
if (reset | eop) begin
pkt_length <= 16'd1;
end else if (xfer) begin
pkt_length <= pkt_length + 1'b1;
end
end
end else begin
// Default packet length is 0
always @(*) pkt_length <= 16'd0;
end endgenerate
generate if (PKT_CHKSUM_EN) begin
// Compute the XOR checksum of the lines in a packet
reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
always @(posedge clk) begin
if (reset) begin
chksum_prev <= {WIDTH{1'b0}};
end else if (xfer) begin
chksum_prev <= pkt_chksum;
end
end
assign pkt_chksum = chksum_prev ^ axis_tdata;
end else begin
// Default checksum is 0
assign pkt_chksum = {WIDTH{1'b0}};
end endgenerate
//----------------------------
// Stream specific
//----------------------------
always @(posedge clk) begin
if (reset | (PKT_COUNT_EN == 0)) begin
pkt_count <= {COUNT_W{1'b0}};
end else if (eop) begin
pkt_count <= pkt_count + 1'b1;
end
end
always @(posedge clk) begin
if (reset | (XFER_COUNT_EN == 0)) begin
xfer_count <= {COUNT_W{1'b0}};
end else if (xfer) begin
xfer_count <= xfer_count + 1'b1;
end
end
endmodule
| 6.605169 |
module axis_switch_v1_1_22_axi_ctrl_read #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 7,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire aclk,
input wire areset,
// Slave Interface Read Address Ports
input wire arvalid,
output wire arready,
input wire [C_ADDR_WIDTH-1:0] araddr,
// Slave Interface Read Data Ports
output wire rvalid,
input wire rready,
output wire [C_DATA_WIDTH-1:0] rdata,
output wire [ 1:0] rresp,
input wire [16*C_DATA_WIDTH-1:0] reg_bank_0,
input wire [16*C_DATA_WIDTH-1:0] reg_bank_1,
input wire [ 160-1:0] ctrl_reg_debug
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// Outputs are encoded in register bits
// /--- RVALID
// |/-- ARREADY/READ
localparam [1:0] SM_IDLE = 2'b00;
localparam [1:0] SM_READ = 2'b01;
localparam [1:0] SM_RESP = 2'b10;
localparam integer LP_DEBUG_CTRL_REG = 0;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [ 1:0] state = 2'b0;
reg [ C_ADDR_WIDTH-1:0] addr_r = {C_ADDR_WIDTH{1'b0}};
wire [ 3:0] addr;
reg [ C_DATA_WIDTH-1:0] data = {C_ADDR_WIDTH{1'b0}};
wire sel;
wire [ C_DATA_WIDTH-1:0] sel_bank_0;
wire [ C_DATA_WIDTH-1:0] sel_bank_1;
wire read_enable;
wire [16*C_DATA_WIDTH-1:0] reg_bank_0_expanded;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Assign axi_outputs
assign arready = state[0];
assign rvalid = state[1];
assign rdata = data;
assign rresp = 2'b0;
// State machine for AXI
always @(posedge aclk) begin
if (areset) begin
state <= SM_IDLE;
end else begin
case (state)
SM_IDLE: if (arvalid) state <= SM_READ;
else state <= SM_IDLE;
SM_READ: state <= SM_RESP;
SM_RESP: if (rready) state <= SM_IDLE;
else state <= SM_RESP;
default: state <= SM_IDLE;
endcase
end
end
// Reg bank logic
always @(posedge aclk) begin
addr_r <= araddr;
end
assign addr = addr_r[2+:4];
assign sel = ~addr_r[6];
assign read_enable = state[0];
assign sel_bank_0 = reg_bank_0_expanded[addr*C_DATA_WIDTH+:C_DATA_WIDTH];
assign sel_bank_1 = reg_bank_1[addr*C_DATA_WIDTH+:C_DATA_WIDTH];
always @(posedge aclk) begin
if (read_enable) begin
data <= sel ? sel_bank_0 : sel_bank_1;
end
end
assign reg_bank_0_expanded[0+:C_DATA_WIDTH] = reg_bank_0[0+:C_DATA_WIDTH];
assign reg_bank_0_expanded[1*C_DATA_WIDTH+:5*C_DATA_WIDTH] = (LP_DEBUG_CTRL_REG) ? ctrl_reg_debug : 160'h0;
assign reg_bank_0_expanded[6*C_DATA_WIDTH+:10*C_DATA_WIDTH] = 320'h0;
endmodule
| 9.124016 |
module axis_switch_v1_1_22_axi_ctrl_write #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 7,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire aclk,
input wire areset,
input wire awvalid,
output wire awready,
input wire [C_ADDR_WIDTH-1:0] awaddr,
input wire wvalid,
output wire wready,
input wire [C_DATA_WIDTH-1:0] wdata,
output wire bvalid,
input wire bready,
output wire [ 1:0] bresp,
output wire [ 1:0] enable,
output wire [ 3:0] addr,
output wire [C_DATA_WIDTH-1:0] data,
input wire busy
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_SM_WIDTH = 3;
// Outputs are encoded in register bits
// /--- bvalid
// |/-- awready/wready/enable
localparam [LP_SM_WIDTH-1:0] SM_IDLE = 3'b000;
localparam [LP_SM_WIDTH-1:0] SM_WRITE = 3'b001;
localparam [LP_SM_WIDTH-1:0] SM_RESP = 3'b010;
localparam [LP_SM_WIDTH-1:0] SM_BUSY = 3'b100;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
(* fsm_encoding = "none" *)reg [ LP_SM_WIDTH-1:0] state = SM_IDLE;
reg [C_ADDR_WIDTH-1:0] addr_r = {C_ADDR_WIDTH{1'b0}};
reg [C_DATA_WIDTH-1:0] data_r = {C_DATA_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// State machine for AXI
always @(posedge aclk) begin
if (areset) begin
state <= SM_IDLE;
end else begin
case (state)
SM_IDLE: state <= (awvalid & wvalid & ~busy) ? SM_WRITE : SM_IDLE;
SM_WRITE: state <= SM_BUSY;
SM_BUSY: state <= busy ? SM_BUSY : SM_RESP;
SM_RESP: state <= bready ? SM_IDLE : SM_RESP;
default: state <= SM_IDLE;
endcase
end
end
assign awready = state[0];
assign wready = state[0];
assign bvalid = state[1];
assign bresp = 2'b0;
// Reg bank logic
always @(posedge aclk) begin
addr_r <= awaddr[0+:C_ADDR_WIDTH];
end
always @(posedge aclk) begin
data_r <= wdata;
end
assign addr = addr_r[2+:4];
assign data = data_r;
assign enable[0] = ~addr_r[6] ? state[0] : 1'b0;
assign enable[1] = addr_r[6] ? state[0] : 1'b0;
endmodule
| 9.124016 |
module axis_switch_v1_1_22_reg_bank_16x32 #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_ACTIVE_REG = 8, // 1+
// Bit mask of active bits in register set
parameter integer C_REG_MASK = 32'b1111_1111_1111_1111,
// Default init value
parameter [16*32-1:0] C_INIT = {16{32'b0}}
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk,
input wire areset,
input wire we,
input wire [ 3:0] waddr,
input wire [ 32-1:0] wdata,
output wire [16*32-1:0] rdata
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam LP_MAX = 16;
localparam LP_WIDTH = 32;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [(LP_MAX*LP_WIDTH)-1:0] reg_data = C_INIT;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
genvar i;
for (i = 0; i < LP_MAX; i = i + 1) begin : gen_reg
always @(posedge aclk) begin
if (areset) begin
reg_data[i*LP_WIDTH+:LP_WIDTH] <= C_INIT[i*LP_WIDTH+:LP_WIDTH];
end else if ((waddr == i) && we && (i < C_ACTIVE_REG)) begin
reg_data[i*LP_WIDTH+:LP_WIDTH] <= wdata;
end
end
end
endgenerate
assign rdata = reg_data;
endmodule
| 9.124016 |
module from libaxis repo
`default_nettype none
module axis_sync_fifo #
(
parameter DATA_WIDTH = 0,
parameter DEPTH_WIDTH = 0
)
(
input wire clk,
input wire [DATA_WIDTH-1:0] s_tdata,
input wire s_tvalid,
output wire s_tready,
output wire [DATA_WIDTH-1:0] m_tdata,
output wire m_tvalid,
input wire m_tready,
output wire [DEPTH_WIDTH-1:0] data_count,
input wire rst
);
// synthesis translate_off
initial begin
if ((DATA_WIDTH < 1) || (DEPTH_WIDTH < 1)) begin
$error("Error! DATA_WIDTH and DEPTH_WIDTH shoul be > 0");
$fatal();
end
end
// synthesis translate_on
wire wr_en;
wire rd_en;
wire full;
wire empty;
assign wr_en = ~full & s_tvalid;
assign s_tready = ~full;
assign m_tvalid = ~empty;
assign rd_en = ~empty & m_tready;
fifo_fwft #
(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH_WIDTH(DEPTH_WIDTH)
)
fifo_fwft_inst
(
.clk,
.rst,
.din ( s_tdata ),
.wr_en,
.full,
.dout ( m_tdata ),
.rd_en,
.empty,
.cnt ( data_count )
);
endmodule
| 7.857381 |
module axis_tagger #(
parameter integer AXIS_TDATA_WIDTH = 256
) (
// System signals
input wire aclk,
input wire tag_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg int_data_reg, int_flag_reg;
always @(posedge aclk) begin
int_data_reg <= tag_data;
if (tag_data & ~int_data_reg) begin
int_flag_reg <= 1'b1;
end else if (s_axis_tvalid) begin
int_flag_reg <= 1'b0;
end
end
assign s_axis_tready = m_axis_tready;
assign m_axis_tdata = {s_axis_tdata[255:209], int_flag_reg, s_axis_tdata[207:0]};
assign m_axis_tvalid = s_axis_tvalid;
endmodule
| 6.913304 |
module axis_tester #(
parameter C_AXIS_DATA_WIDTH = 32) //only 32-bit
(
////////////////////////////////////////////////////////////////////////////
// AXI-Lite Slave (data input)
input AXIS_RSTN,
input AXIS_CLK,
input S_AXIS_TVALID,
input S_AXIS_TLAST,
output S_AXIS_TREADY,
input [C_AXIS_DATA_WIDTH-1 : 0] S_AXIS_TDATA,
output M_AXIS_TVALID,
output reg M_AXIS_TLAST,
input M_AXIS_TREADY,
output [C_AXIS_DATA_WIDTH-1 : 0] M_AXIS_TDATA,
output reg [31:0] M_AXIS_LEN,
output reg [31:0] ERR_CNT
);
wire clk, rstn;
assign clk = AXIS_CLK;
assign rstn = AXIS_RSTN;
localparam C_AXIS_BYTE_WIDTH = (C_AXIS_DATA_WIDTH / 8);
localparam ST_IDLE = 4'b0000;
localparam ST_RX = 4'b0001;
localparam ST_TX = 4'b0010;
reg [3:0] stat;
reg [31:0] byte_cnt;
reg [31:0] counter;
reg [10:0] rand;
integer i;
always @ (posedge clk)
begin
if (!rstn)
begin
rand <= 11'b11;
stat <= ST_IDLE;
byte_cnt <= 'b0;
counter <= 'b0;
ERR_CNT <= 'b0;
M_AXIS_LEN <= 'b0;
M_AXIS_TLAST <= 1'b0;
end else begin
//random
rand <= {rand[9:0], rand[10]^rand[8]};
case (stat)
ST_IDLE : begin
if (S_AXIS_TVALID)
begin
ERR_CNT <= 'b0;
counter <= 1;
stat <= ST_RX;
end
end
ST_RX : begin
if (S_AXIS_TVALID && S_AXIS_TREADY)
begin
counter <= counter + 1;
if (S_AXIS_TDATA[31:0] != counter)
ERR_CNT <= ERR_CNT + 1'b1;
if (S_AXIS_TLAST)
begin
stat <= ST_TX;
counter <= 1;
byte_cnt <= {counter[29:0], 2'b00};
M_AXIS_LEN <= counter;
M_AXIS_TLAST <= 1'b0;
end
end
end
ST_TX : begin
if (M_AXIS_TVALID && M_AXIS_TREADY)
begin
counter <= counter + 1;
byte_cnt <= byte_cnt - C_AXIS_BYTE_WIDTH;
if (byte_cnt == C_AXIS_BYTE_WIDTH*2)
begin
M_AXIS_TLAST <= 1'b1;
end else if (byte_cnt == C_AXIS_BYTE_WIDTH)
begin
M_AXIS_TLAST <= 1'b0;
stat <= ST_IDLE;
end
end
end
default : begin
stat <= ST_IDLE;
end
endcase
end
end
assign S_AXIS_TREADY = (stat == ST_RX) && rand[10];
assign M_AXIS_TVALID = (stat == ST_TX) && rand[10];
assign M_AXIS_TDATA = (M_AXIS_TVALID) ? counter : 'b0;
endmodule
| 8.606215 |
module axis_timer #(
parameter integer CNTR_WIDTH = 64
) (
// System signals
input wire aclk,
input wire aresetn,
input wire run_flag,
input wire cfg_flag,
input wire [CNTR_WIDTH-1:0] cfg_data,
output wire trg_flag,
output wire [CNTR_WIDTH-1:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire s_axis_tvalid
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
wire int_enbl_wire;
always @(posedge aclk) begin
if (~aresetn) begin
int_cntr_reg <= {(CNTR_WIDTH) {1'b0}};
end else begin
int_cntr_reg <= int_cntr_next;
end
end
assign int_enbl_wire = run_flag & (int_cntr_reg > {(CNTR_WIDTH) {1'b0}});
always @* begin
int_cntr_next = int_cntr_reg;
if (cfg_flag) begin
int_cntr_next = cfg_data;
end else if (int_enbl_wire & s_axis_tvalid) begin
int_cntr_next = int_cntr_reg - 1'b1;
end
end
assign trg_flag = int_enbl_wire;
assign sts_data = int_cntr_reg;
assign s_axis_tready = 1'b1;
endmodule
| 6.556656 |
module axis_to_cvita (
input wire clk,
input wire [63:0] s_axis_tdata,
input wire s_axis_tlast,
input wire s_axis_tvalid,
output wire s_axis_tready,
output wire [63:0] o_tdata,
output wire o_tlast,
output wire o_tvalid,
input wire o_tready
);
assign s_axis_tready = o_tready;
assign o_tdata = {s_axis_tdata[31:0], s_axis_tdata[63:32]};
assign o_tlast = s_axis_tlast;
assign o_tvalid = s_axis_tvalid;
endmodule
| 6.714538 |
module axis_trigger #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter AXIS_TDATA_SIGNED = "FALSE"
) (
// System signals
input wire aclk,
input wire pol_data,
input wire [AXIS_TDATA_WIDTH-1:0] msk_data,
input wire [AXIS_TDATA_WIDTH-1:0] lvl_data,
output wire trg_flag,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [1:0] int_comp_reg;
wire int_comp_wire;
generate
if (AXIS_TDATA_SIGNED == "TRUE") begin : SIGNED
assign int_comp_wire = $signed(s_axis_tdata & msk_data) >= $signed(lvl_data);
end else begin : UNSIGNED
assign int_comp_wire = (s_axis_tdata & msk_data) >= lvl_data;
end
endgenerate
always @(posedge aclk) begin
if (s_axis_tvalid) begin
int_comp_reg <= {int_comp_reg[0], int_comp_wire};
end
end
assign s_axis_tready = 1'b1;
assign trg_flag = s_axis_tvalid & (pol_data ^ int_comp_reg[0]) & (pol_data ^ ~int_comp_reg[1]);
endmodule
| 6.780757 |
module's
port width, even if you use the K&R-style Verilog syntax:
module my_thing # (
parameter W = 2
) (a, b);
localparam WW = W+W;
input wire [W -1:0] a;
output wire [WW -1:0] b;
endmodule
| 7.777765 |
module axis_width_converter #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter BIG_ENDIAN = 1,
parameter WIDTH_IN = 8, // 8,16,32
parameter WIDTH_OUT = 16 // 8,16,32
) (
input wire s_axis_aclk,
input wire s_axis_aresetn,
input wire [WIDTH_IN-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire m_axis_aclk,
output wire [WIDTH_OUT-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast
);
localparam IN_RATIO = (WIDTH_IN > WIDTH_OUT) ? (WIDTH_IN / WIDTH_OUT) : 1;
localparam OUT_RATIO = (WIDTH_OUT > WIDTH_IN) ? (WIDTH_OUT / WIDTH_IN) : 1;
wire [WIDTH_OUT+OUT_RATIO-1:0] dout;
reg [WIDTH_IN+IN_RATIO-1:0] din;
wire empty;
wire full;
wire rd_rst_busy;
wire wr_rst_busy;
wire rd_en;
wire rst;
wire rd_clk;
wire wr_clk;
wire wr_en;
reg [WIDTH_OUT-1:0] m_data;
reg m_last;
assign wr_clk = s_axis_aclk;
assign rd_clk = m_axis_aclk;
assign rst = ~s_axis_aresetn;
assign wr_en = s_axis_tvalid & s_axis_tready;
assign rd_en = m_axis_tvalid & m_axis_tready;
assign s_axis_tready = ~full & ~wr_rst_busy;
assign m_axis_tvalid = ~empty & ~rd_rst_busy;
assign m_axis_tdata = m_data;
assign m_axis_tlast = m_last;
/* DATA IN */
always @(*) begin
if (BIG_ENDIAN) begin
case (IN_RATIO)
1: din <= {s_axis_tlast, s_axis_tdata};
2:
din <= {
s_axis_tlast,
{s_axis_tdata[WIDTH_IN/2-1-:WIDTH_IN/2], 1'b0, s_axis_tdata[WIDTH_IN-1-:WIDTH_IN/2]}
};
4:
din <= {
s_axis_tlast,
{
s_axis_tdata[WIDTH_IN/4-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[WIDTH_IN/2-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[3*WIDTH_IN/4-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[WIDTH_IN-1-:WIDTH_IN/4]
}
};
endcase
end else begin
case (IN_RATIO)
1: din <= {s_axis_tlast, s_axis_tdata};
2:
din <= {
s_axis_tlast,
{s_axis_tdata[WIDTH_IN/2-1-:WIDTH_IN/2], 1'b0, s_axis_tdata[WIDTH_IN-1-:WIDTH_IN/2]}
};
4:
din <= {
s_axis_tlast,
{
s_axis_tdata[WIDTH_IN-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[3*WIDTH_IN/4-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[WIDTH_IN/2-1-:WIDTH_IN/4],
1'b0,
s_axis_tdata[WIDTH_IN/4-1-:WIDTH_IN/4]
}
};
endcase
end
end
/* DATA OUT */
always @(*) begin
case (OUT_RATIO)
1: begin
m_data <= dout[WIDTH_OUT-1:0];
m_last <= dout[WIDTH_OUT];
end
2: begin
if (BIG_ENDIAN) begin
m_data <= {dout[WIDTH_IN-1-:WIDTH_IN], dout[WIDTH_IN*2-:WIDTH_IN]};
end else begin
m_data <= {dout[WIDTH_IN*2-:WIDTH_IN], dout[WIDTH_IN-1-:WIDTH_IN]};
end
m_last <= dout[WIDTH_IN*2+1] | dout[WIDTH_IN];
end
4: begin
if (BIG_ENDIAN) begin
m_data <= {
dout[WIDTH_IN-1-:WIDTH_IN],
dout[WIDTH_IN*2-:WIDTH_IN],
dout[WIDTH_IN*3+1-:WIDTH_IN],
dout[WIDTH_IN*4+2-:WIDTH_IN]
};
end else begin
m_data <= {
dout[WIDTH_IN*4+2-:WIDTH_IN],
dout[WIDTH_IN*3+1-:WIDTH_IN],
dout[WIDTH_IN*2-:WIDTH_IN],
dout[WIDTH_IN-1-:WIDTH_IN]
};
end
m_last <= dout[WIDTH_IN*4+3] | dout[WIDTH_IN*3+2] | dout[WIDTH_IN*2+1] | dout[WIDTH_IN];
end
endcase
end
arch_fifo_async #(
.FPGA_VENDOR (FPGA_VENDOR),
.FPGA_FAMILY (FPGA_FAMILY),
.RD_DATA_WIDTH(WIDTH_OUT + OUT_RATIO),
.WR_DATA_WIDTH(WIDTH_IN + IN_RATIO)
) arch_fifo_async_inst (
.dout(dout),
.empty(empty),
.full(full),
.rd_rst_busy(rd_rst_busy),
.wr_rst_busy(wr_rst_busy),
.din(din),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en)
);
endmodule
| 9.26688 |
module axis_variable #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg;
reg int_tvalid_reg, int_tvalid_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_tdata_reg <= {(AXIS_TDATA_WIDTH) {1'b0}};
int_tvalid_reg <= 1'b0;
end else begin
int_tdata_reg <= cfg_data;
int_tvalid_reg <= int_tvalid_next;
end
end
always @* begin
int_tvalid_next = int_tvalid_reg;
if (int_tdata_reg != cfg_data) begin
int_tvalid_next = 1'b1;
end
if (m_axis_tready & int_tvalid_reg) begin
int_tvalid_next = 1'b0;
end
end
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
| 7.012108 |
module axis_volume_controller #(
parameter SWITCH_WIDTH = 4, // WARNING: this module has not been tested with other values of SWITCH_WIDTH, it will likely need some changes
parameter DATA_WIDTH = 24
) (
input wire clk,
input wire [SWITCH_WIDTH-1:0] sw,
//AXIS SLAVE INTERFACE
input wire [DATA_WIDTH-1:0] s_axis_data,
input wire s_axis_valid,
output reg s_axis_ready = 1'b1,
input wire s_axis_last,
// AXIS MASTER INTERFACE
output reg [DATA_WIDTH-1:0] m_axis_data = 1'b0,
output reg m_axis_valid = 1'b0,
input wire m_axis_ready,
output reg m_axis_last = 1'b0
);
localparam MULTIPLIER_WIDTH = 24;
reg [MULTIPLIER_WIDTH+DATA_WIDTH-1:0] data[1:0];
reg [SWITCH_WIDTH-1:0] sw_sync_r[2:0];
wire [SWITCH_WIDTH-1:0] sw_sync = sw_sync_r[2];
// wire [SWITCH_WIDTH:0] m = {1'b0, sw_sync} + 1;
reg [MULTIPLIER_WIDTH:0] multiplier = 'b0; // range of 0x00:0x10 for width=4
wire m_select = m_axis_last;
wire m_new_word = (m_axis_valid == 1'b1 && m_axis_ready == 1'b1) ? 1'b1 : 1'b0;
wire m_new_packet = (m_new_word == 1'b1 && m_axis_last == 1'b1) ? 1'b1 : 1'b0;
wire s_select = s_axis_last;
wire s_new_word = (s_axis_valid == 1'b1 && s_axis_ready == 1'b1) ? 1'b1 : 1'b0;
wire s_new_packet = (s_new_word == 1'b1 && s_axis_last == 1'b1) ? 1'b1 : 1'b0;
reg s_new_packet_r = 1'b0;
always @(posedge clk) begin
sw_sync_r[2] <= sw_sync_r[1];
sw_sync_r[1] <= sw_sync_r[0];
sw_sync_r[0] <= sw;
// if (&sw_sync == 1'b1)
// multiplier <= {1'b1, {MULTIPLIER_WIDTH{1'b0}}};
// else
// multiplier <= {1'b0, sw, {MULTIPLIER_WIDTH-SWITCH_WIDTH{1'b0}}} + 1;
multiplier <= {sw_sync, {MULTIPLIER_WIDTH{1'b0}}} / {SWITCH_WIDTH{1'b1}};
s_new_packet_r <= s_new_packet;
end
always @(posedge clk)
if (s_new_word == 1'b1) // sign extend and register AXIS slave data
data[s_select] <= {{MULTIPLIER_WIDTH{s_axis_data[DATA_WIDTH-1]}}, s_axis_data};
else if (s_new_packet_r == 1'b1) begin
data[0] <= $signed(
data[0]
) * multiplier; // core volume control algorithm, infers a DSP48 slice
data[1] <= $signed(data[1]) * multiplier;
end
always @(posedge clk)
if (s_new_packet_r == 1'b1) m_axis_valid <= 1'b1;
else if (m_new_packet == 1'b1) m_axis_valid <= 1'b0;
always @(posedge clk)
if (m_new_packet == 1'b1) m_axis_last <= 1'b0;
else if (m_new_word == 1'b1) m_axis_last <= 1'b1;
always @(m_axis_valid, data[0], data[1], m_select)
if (m_axis_valid == 1'b1)
m_axis_data = data[m_select][MULTIPLIER_WIDTH+DATA_WIDTH-1:MULTIPLIER_WIDTH];
else m_axis_data = 'b0;
always @(posedge clk)
if (s_new_packet == 1'b1) s_axis_ready <= 1'b0;
else if (m_new_packet == 1'b1) s_axis_ready <= 1'b1;
endmodule
| 8.30282 |
module Axis_WR (
Clk,
Addr,
MCUportL,
Din,
SpeedSetDone,
SpeedSet,
AxisStateCmd,
AxisPlsCmd,
SpeedCmd,
TargetPos,
RefPos
);
input Clk;
input [7:0] Addr;
input [15:0] MCUportL;
input [7:0] Din;
output [15:0] AxisStateCmd;
output [7:0] AxisPlsCmd;
output [7:0] SpeedCmd;
output [15:0] TargetPos;
output [15:0] RefPos;
reg [7:0] AxisPlsCmd, SpeedCmd;
reg [15:0] AxisStateCmd;
reg [15:0] RefPos;
reg [15:0] TargetPos;
input SpeedSetDone;
output reg SpeedSet;
always @(posedge Clk or posedge SpeedSetDone) //add by tt
begin
if (SpeedSetDone) SpeedSet <= 1'b0;
else if (Addr[2:0] == 3'h2) SpeedSet <= 1'b1;
end
//Din: large fan-out.
/*
assign AxisStateCmd =((~Clk) & MCUportL[0]) ?Din :8'h00;
assign AxisPlsCmd =((~Clk) & MCUportL[1]) ?Din :8'h00;
/*
always @(AxisCmd)
begin
if(MCUportL[0])
AxisStateCmd <=AxisCmd;
if(MCUportL[1])
AxisPlsCmd <=AxisCmd;
if(MCUportL[2])
SpeedCmd <=AxisCmd;
if(MCUportL[3])
SpeedFallOut <=AxisCmd;
if(MCUportL[4])
TargetPos[7:0] <=AxisCmd;
if(MCUportL[5])
TargetPos[15:8] <=AxisCmd;
if(MCUportL[6])
RefPos[7:0] <=AxisCmd;
if(MCUportL[7])
RefPos[15:8] <=AxisCmd;
end
*/
always @(posedge Clk) begin
if (MCUportL[0]) AxisStateCmd[7:0] <= Din;
if (MCUportL[1]) AxisPlsCmd <= Din;
if (MCUportL[2]) SpeedCmd <= Din;
if (MCUportL[3]) AxisStateCmd[15:8] <= Din;
// if(MCUportL[4])
// TargetPos[7:0] <=Din;
// if(MCUportL[5])
// TargetPos[15:8] <=Din;
if (MCUportL[6]) RefPos[7:0] <= Din;
if (MCUportL[7]) RefPos[15:8] <= Din;
end
/*
always @(posedge Clk)
begin
case(Addr[2:0])
3'b000:
AxisStateCmd <=Din;
3'b001:
AxisPlsCmd <=Din;
3'b010:
SpeedCmd <=Din; //In case of the semi-stable state of the clock division module ,SpeedCmd should be stable before it is added to the sCnt every time it is writen.
3'b011:
SpeedFallOut <=Din;
3'b100:
TargetPos[7:0] <=Din;
3'b101:
TargetPos[15:8] <=Din;
3'b110:
RefPos[7:0] <=Din;
3'b111:
RefPos[15:8] <=Din;
endcase
end
*/
endmodule
| 6.829013 |
module axis_zeroer #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
assign s_axis_tready = m_axis_tready;
assign m_axis_tdata = s_axis_tvalid ? s_axis_tdata : {(AXIS_TDATA_WIDTH) {1'b0}};
assign m_axis_tvalid = 1'b1;
endmodule
| 7.330497 |
module axis_zmod_dac_v1_0 #(
parameter set_fs_i = 1'b1,
parameter set_fs_j = 1'b1
) (
input aclk, /* Clock input. This signal is corresponding with sample frequency */
input resetn, /* Reset input */
input enable_dac, /* enable dac output */
/* slave axis interface */
input [31:0] s_axis_tdata, /* {w14_data_i, 2'bx, w14_data_q, 2'bx} */
input s_axis_tvalid,
output s_axis_tready,
output signed [13:0] ddr_data, /* Parallel DDR data for ADC*/
output ddr_clk, /* DDR clock */
output rst_spi, /* DAC reset out*/
output spi_sck, /* DAC SPI clk out*/
output spi_cs, /* DAC SPI cs out*/
output spi_sdo, /* DAC SPI data IO out*/
output relay_output, /* zmod output relay */
output fsi_fs_output, /* gain i output */
output fsj_fs_output /* gain j output */
);
wire signed [13:0] w13_data_i; /* Data for ch i*/
wire signed [13:0] w13_data_q; /* Data for ch q*/
assign w13_data_i = s_axis_tdata[29-:14];
assign w13_data_q = s_axis_tdata[13:0];
assign s_axis_tready = 1'b1;
/* Output data management */
generate
for (genvar i = 0; i <= 13; i = i + 1)
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_DACDATA (
.Q (ddr_data[i]),
.C (aclk),
.CE(1'b1),
.D1(w13_data_i[i]),
.D2(w13_data_q[i]),
.R (!resetn),
.S (1'b0)
);
endgenerate
/* Clock forwarding */
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_DACCLK (
.Q (ddr_clk),
.C (aclk),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R (!resetn),
.S (1'b0)
);
/* Configure dac by gpio */
assign rst_spi = 1'b1; /* SPI_MODE = OFF*/
assign spi_sck = 1'b0; /* CLKIN = DCLKIO*/
assign spi_cs = 1'b0; /* PWRDWN = 0 */
assign spi_sdo = 1'b1; /* INPUT FORMAT = 2's complement */
/* configuration relays */
assign relay_output = enable_dac;
assign fsi_fs_output = set_fs_i;
assign fsj_fs_output = set_fs_j;
endmodule
| 7.48336 |
module AXI_top_design #(
parameter WIDTH,
SIZE
) (
input logic clk,
input logic resetn,
output logic [4095:0][7:0] slave_mem,
output logic [4095:0][7:0] master_mem,
axi intf,
// inputs to master from tb
input logic [WIDTH-1:0] awaddr,
input logic [(WIDTH/8)-1:0] awlen,
input logic [(WIDTH/8)-1:0] wstrb,
input logic [SIZE-1:0] awsize,
input logic [SIZE-2:0] awburst,
input logic [WIDTH-1:0] wdata,
input logic [(WIDTH/8)-1:0] awid,
input logic [WIDTH-1:0] araddr,
input logic [(WIDTH/8)-1:0] arid,
input logic [(WIDTH/8)-1:0] arlen,
input logic [SIZE-1:0] arsize,
input logic [SIZE-2:0] arburst
);
// Master instance
AXI_master #(
.WIDTH(32),
.SIZE (3)
) master_inst (
.clk(clk),
.resetn(resetn),
.axim(intf),
.read_mem(master_mem),
.awaddr(awaddr),
.awlen(awlen),
.wstrb(wstrb),
.awsize(awsize),
.awburst(awburst),
.wdata(wdata),
.awid(awid),
.araddr(araddr),
.arid(arid),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst)
);
// Slave instance
AXI_slave slave_inst (
.clk(clk),
.resetn(resetn),
.axis(intf),
.slave_mem(slave_mem)
);
endmodule
| 7.580887 |
module SramAddrGen (
input [31:0] CurAddr,
input [ 7:0] Len,
input [ 2:0] Size,
input [ 1:0] Burst,
output [31:0] NextAddr
);
wire [11:0] iCurAddr = CurAddr[11:0]; // @[SramAddrGen.scala 27:30]
wire [1:0] _iSize_T_3 = 3'h2 == Size ? 2'h2 : {{1'd0}, 3'h1 == Size}; // @[Mux.scala 81:58]
wire [1:0] _iSize_T_5 = 3'h3 == Size ? 2'h3 : _iSize_T_3; // @[Mux.scala 81:58]
wire [2:0] _iSize_T_7 = 3'h4 == Size ? 3'h4 : {{1'd0}, _iSize_T_5}; // @[Mux.scala 81:58]
wire [2:0] _iSize_T_9 = 3'h5 == Size ? 3'h5 : _iSize_T_7; // @[Mux.scala 81:58]
wire [2:0] _iSize_T_11 = 3'h6 == Size ? 3'h6 : _iSize_T_9; // @[Mux.scala 81:58]
wire [2:0] iSize = 3'h7 == Size ? 3'h7 : _iSize_T_11; // @[Mux.scala 81:58]
wire [11:0] wordAddress = iCurAddr >> iSize; // @[SramAddrGen.scala 34:32]
wire [11:0] _incrNextAddr_T_1 = wordAddress + 12'h1; // @[SramAddrGen.scala 37:37]
wire [18:0] _GEN_1 = {{7'd0}, _incrNextAddr_T_1}; // @[SramAddrGen.scala 37:44]
wire [18:0] incrNextAddr = _GEN_1 << iSize; // @[SramAddrGen.scala 37:44]
wire [3:0] _wrapBound_T_3 = ~Len[3:0]; // @[SramAddrGen.scala 40:68]
wire [3:0] _wrapBound_T_4 = wordAddress[3:0] & _wrapBound_T_3; // @[SramAddrGen.scala 40:66]
wire [11:0] _wrapBound_T_5 = {wordAddress[11:4], _wrapBound_T_4}; // @[Cat.scala 31:58]
wire [18:0] _GEN_2 = {{7'd0}, _wrapBound_T_5}; // @[SramAddrGen.scala 40:80]
wire [18:0] wrapBound = _GEN_2 << iSize; // @[SramAddrGen.scala 40:80]
wire [4:0] _totSize_T_1 = Len[3:0] + 4'h1; // @[SramAddrGen.scala 41:33]
wire [11:0] _GEN_3 = {{7'd0}, _totSize_T_1}; // @[SramAddrGen.scala 41:41]
wire [11:0] totSize = _GEN_3 << iSize; // @[SramAddrGen.scala 41:41]
wire [18:0] _GEN_0 = {{7'd0}, totSize}; // @[SramAddrGen.scala 42:55]
wire [18:0] _wrapNextAddr_T_1 = wrapBound + _GEN_0; // @[SramAddrGen.scala 42:55]
wire [18:0] wrapNextAddr = incrNextAddr == _wrapNextAddr_T_1 ? wrapBound : incrNextAddr; // @[SramAddrGen.scala 42:27]
wire [31:0] _iNextAddr_T_3 = 2'h1 == Burst ? {{13'd0}, incrNextAddr} : CurAddr; // @[Mux.scala 81:58]
wire [31:0] _iNextAddr_T_5 = 2'h2 == Burst ? {{13'd0}, wrapNextAddr} : _iNextAddr_T_3; // @[Mux.scala 81:58]
wire [11:0] iNextAddr = _iNextAddr_T_5[11:0]; // @[SramAddrGen.scala 28:27 44:15]
assign NextAddr = {CurAddr[31:12], iNextAddr}; // @[Cat.scala 31:58]
endmodule
| 6.786747 |
module SramArbiter (
input ACLK,
input ARESETn,
input WrValid,
output WrReady,
input RdValid,
output RdReady
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire reset = ~ARESETn; // @[SramArbiter.scala 26:34]
reg choice; // @[SramArbiter.scala 35:34]
wire [1:0] _T = {WrValid, RdValid}; // @[Cat.scala 31:58]
wire _choiceNext_T = ~choice; // @[SramArbiter.scala 60:32]
wire _GEN_1 = 2'h2 == _T | _choiceNext_T; // @[SramArbiter.scala 49:40 57:29]
assign WrReady = choice; // @[SramArbiter.scala 67:21]
assign RdReady = ~choice; // @[SramArbiter.scala 68:24]
always @(posedge ACLK or posedge reset) begin
if (reset) begin // @[SramArbiter.scala 49:40]
choice <= 1'h0; // @[SramArbiter.scala 51:29]
end else if (!(2'h0 == _T)) begin // @[SramArbiter.scala 49:40]
if (2'h1 == _T) begin
choice <= 1'h0;
end else begin
choice <= _GEN_1;
end
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
choice = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
choice = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.76663 |
module axi_10g_ethernet_0_axi_mux (
input mux_select,
// mux inputs
input [63:0] tdata0,
input [ 7:0] tkeep0,
input tvalid0,
input tlast0,
output reg tready0,
input [63:0] tdata1,
input [ 7:0] tkeep1,
input tvalid1,
input tlast1,
output reg tready1,
// mux outputs
output reg [63:0] tdata,
output reg [ 7:0] tkeep,
output reg tvalid,
output reg tlast,
input tready
);
always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or tkeep0 or tkeep1 or
tvalid1 or tlast1)
begin
if (mux_select) begin
tdata = tdata1;
tkeep = tkeep1;
tvalid = tvalid1;
tlast = tlast1;
end else begin
tdata = tdata0;
tkeep = tkeep0;
tvalid = tvalid0;
tlast = tlast0;
end
end
always @(mux_select or tready) begin
if (mux_select) begin
tready0 = 1'b1;
tready1 = tready;
end else begin
tready0 = tready;
tready1 = 1'b1;
end
end
endmodule
| 6.663917 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//---------------------------------------------------------------------------
`timescale 1ns / 1ps
module axi_10g_ethernet_0_ff_synchronizer_rst2 #(
parameter C_NUM_SYNC_REGS = 3,
parameter C_RVAL = 1'b0
)
(
input wire clk,
input wire rst,
input wire data_in,
output wire data_out
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{C_RVAL}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if(rst)
sync1_r <= {C_NUM_SYNC_REGS{C_RVAL}};
else
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
assign data_out = sync1_r[C_NUM_SYNC_REGS-1];
endmodule
| 9.028271 |
module axi_10g_ethernet_0_fifo_ram #(
parameter ADDR_WIDTH = 9
) (
input wire wr_clk,
input wire [(ADDR_WIDTH-1):0] wr_addr,
input wire [ 63:0] data_in,
input wire [ 3:0] ctrl_in,
input wire wr_allow,
input wire rd_clk,
input wire rd_sreset,
input wire [(ADDR_WIDTH-1):0] rd_addr,
output wire [ 63:0] data_out,
output wire [ 3:0] ctrl_out,
input wire rd_allow
);
localparam RAM_DEPTH = 2 ** ADDR_WIDTH;
(* ram_style = "block" *)
reg [ 67:0] ram [RAM_DEPTH-1:0];
reg [ 67:0] wr_data_pipe = 0;
reg wr_allow_pipe = 0;
reg [(ADDR_WIDTH-1):0] wr_addr_pipe = 0;
wire [ 67:0] wr_data;
reg [ 67:0] rd_data;
wire rd_allow_int;
assign wr_data[63:0] = data_in;
assign wr_data[67:64] = ctrl_in;
assign data_out = rd_data[63:0];
assign ctrl_out = rd_data[67:64];
// Block RAM must be enabled for synchronous reset to work.
assign rd_allow_int = (rd_allow | rd_sreset);
// For clean simulation
integer val;
initial begin
for (val = 0; val < RAM_DEPTH; val = val + 1) begin
ram[val] <= 64'd0;
end
end
//----------------------------------------------------------------------
// Infer BRAMs and connect them
// appropriately.
//--------------------------------------------------------------------//
always @(posedge wr_clk) begin
wr_data_pipe <= wr_data;
wr_allow_pipe <= wr_allow;
wr_addr_pipe <= wr_addr;
end
always @(posedge wr_clk) begin
if (wr_allow_pipe) begin
ram[wr_addr_pipe] <= wr_data_pipe;
end
end
always @(posedge rd_clk) begin
if (rd_allow_int) begin
if (rd_sreset) begin
rd_data <= 68'd0;
end else begin
rd_data <= ram[rd_addr];
end
end
end
endmodule
| 6.663917 |
module axi_10g_ethernet_0_shared_clocking_wrapper (
input reset,
input refclk_p,
input refclk_n,
input qpll0reset,
input dclk,
input txoutclk,
output txoutclk_out,
output coreclk,
input reset_tx_bufg_gt,
output wire areset_coreclk,
output wire areset_txusrclk2,
output gttxreset,
output gtrxreset,
output txuserrdy,
output txusrclk,
output txusrclk2,
output reset_counter_done,
output qpll0lock_out,
output qpll0outclk,
output qpll0outrefclk,
// DRP signals
input [ 8:0] gt_common_drpaddr,
input gt_common_drpclk,
input [15:0] gt_common_drpdi,
output [15:0] gt_common_drpdo,
input gt_common_drpen,
output gt_common_drprdy,
input gt_common_drpwe
);
/*-------------------------------------------------------------------------*/
// Signal declarations
wire qpll0lock;
wire refclk;
wire counter_done;
wire qpllreset;
assign qpll0lock_out = qpll0lock;
assign reset_counter_done = counter_done;
//---------------------------------------------------------------------------
// Instantiate the 10GBASER/KR GT Common block
//---------------------------------------------------------------------------
axi_10g_ethernet_0_gt_common #(
.WRAPPER_SIM_GTRESET_SPEEDUP("TRUE")
) //Does not affect hardware
gt_common_block_i (
.refclk (refclk),
.qpllreset (qpllreset),
.qpll0lock (qpll0lock),
.qpll0outclk (qpll0outclk),
.qpll0outrefclk (qpll0outrefclk),
// DRP signals
.gt_common_drpaddr(gt_common_drpaddr),
.gt_common_drpclk (gt_common_drpclk),
.gt_common_drpdi (gt_common_drpdi),
.gt_common_drpdo (gt_common_drpdo),
.gt_common_drpen (gt_common_drpen),
.gt_common_drprdy (gt_common_drprdy),
.gt_common_drpwe (gt_common_drpwe)
);
//---------------------------------------------------------------------------
// Instantiate the 10GBASER/KR shared clock/reset block
//---------------------------------------------------------------------------
axi_10g_ethernet_0_shared_clock_and_reset ethernet_shared_clock_reset_block_i (
.areset (reset),
.coreclk (coreclk),
.refclk_p (refclk_p),
.refclk_n (refclk_n),
.refclk (refclk),
.txoutclk (txoutclk),
.qplllock (qpll0lock),
.qpll0reset (qpll0reset),
.reset_tx_bufg_gt (reset_tx_bufg_gt),
.areset_coreclk (areset_coreclk),
.areset_txusrclk2 (areset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (txuserrdy),
.txusrclk (txusrclk),
.txusrclk2 (txusrclk2),
.qpllreset (qpllreset),
.reset_counter_done(counter_done)
);
endmodule
| 6.663917 |
module axi_10g_ethernet_0_shared_clock_and_reset (
input areset,
input refclk_p,
input refclk_n,
input qpll0reset,
output refclk,
input txoutclk,
output coreclk,
input qplllock,
input reset_tx_bufg_gt,
output wire areset_coreclk,
output wire areset_txusrclk2,
output gttxreset,
output gtrxreset,
output reg txuserrdy = 1'b0,
output txusrclk,
output txusrclk2,
output qpllreset,
output reset_counter_done
);
wire coreclk_buf;
wire qplllock_txusrclk2;
reg [8:0] reset_counter = 9'h000;
assign reset_counter_done = reset_counter[8];
reg [3:0] reset_pulse = 4'b1110;
wire gttxreset_txusrclk2;
wire refclkcopy;
IBUFDS_GTE3 ibufds_inst (
.O (refclk),
.ODIV2(refclkcopy),
.CEB (1'b0),
.I (refclk_p),
.IB (refclk_n)
);
BUFG_GT refclk_bufg_gt_i (
.I (refclkcopy),
.CE (1'b1),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK(1'b1),
.DIV (3'b000),
.O (coreclk)
);
BUFG_GT txoutclk_bufg_gt_i (
.I (txoutclk),
.CE (1'b1),
.CEMASK (1'b1),
.CLR (reset_tx_bufg_gt),
.CLRMASK(1'b0),
.DIV (3'b000),
.O (txusrclk)
);
BUFG_GT txusrclk2_bufg_gt_i (
.I (txoutclk),
.CE (1'b1),
.CEMASK (1'b1),
.CLR (reset_tx_bufg_gt),
.CLRMASK(1'b0),
.DIV (3'b001),
.O (txusrclk2)
);
// Asynch reset synchronizers...
axi_10g_ethernet_0_ff_synchronizer_rst2 #(
.C_NUM_SYNC_REGS(5),
.C_RVAL(1'b1)
) areset_coreclk_sync_i (
.clk (coreclk),
.rst (areset),
.data_in (1'b0),
.data_out(areset_coreclk)
);
axi_10g_ethernet_0_ff_synchronizer_rst2 #(
.C_NUM_SYNC_REGS(5),
.C_RVAL(1'b1)
) areset_txusrclk2_sync_i (
.clk(txusrclk2),
.rst(areset),
.data_in(1'b0),
.data_out(areset_txusrclk2)
);
axi_10g_ethernet_0_ff_synchronizer_rst2 #(
.C_NUM_SYNC_REGS(5),
.C_RVAL(1'b0)
) qplllock_txusrclk2_sync_i (
.clk (txusrclk2),
.rst (!qplllock),
.data_in (1'b1),
.data_out(qplllock_txusrclk2)
);
// Hold off the GT resets until 500ns after configuration.
// 128 ticks at 6.4ns period will be >> 500 ns.
// 256 ticks at the minimum possible 2.56ns period (390MHz) will be >> 500 ns.
always @(posedge coreclk) begin
if (!reset_counter[8]) reset_counter <= reset_counter + 1'b1;
else reset_counter <= reset_counter;
end
always @(posedge coreclk) begin
if (areset_coreclk == 1'b1) reset_pulse <= 4'b1110;
else if (reset_counter[8]) reset_pulse <= {1'b0, reset_pulse[3:1]};
end
assign qpllreset = qpll0reset;
assign gttxreset = reset_pulse[0];
assign gtrxreset = reset_pulse[0];
axi_10g_ethernet_0_ff_synchronizer_rst2 #(
.C_NUM_SYNC_REGS(5),
.C_RVAL(1'b1)
) gttxreset_txusrclk2_sync_i (
.clk (txusrclk2),
.rst (gttxreset),
.data_in (1'b0),
.data_out(gttxreset_txusrclk2)
);
always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) begin
if (gttxreset_txusrclk2) txuserrdy <= 1'b0;
else txuserrdy <= qplllock_txusrclk2;
end
endmodule
| 6.663917 |
module axi_10g_ethernet_0_sync_block #(
parameter C_NUM_SYNC_REGS = 5
) (
input wire clk,
input wire data_in,
output wire data_out
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b0}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk) begin
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
assign data_out = sync1_r[C_NUM_SYNC_REGS-1];
endmodule
| 6.663917 |
module axi_10g_ethernet_0_sync_reset (
input clk, // clock to be sync'ed to
input reset_in, // Reset to be 'synced'
output reset_out // synced reset
);
// Internal Signals
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async0 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async1 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async2 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async3 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async4 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_sync0 = 1'b1;
reg reset_sync1 = 1'b1;
// Synchroniser process.
// first five flops are asynchronously reset
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
reset_async0 <= 1'b1;
reset_async1 <= 1'b1;
reset_async2 <= 1'b1;
reset_async3 <= 1'b1;
reset_async4 <= 1'b1;
end else begin
reset_async0 <= 1'b0;
reset_async1 <= reset_async0;
reset_async2 <= reset_async1;
reset_async3 <= reset_async2;
reset_async4 <= reset_async3;
end
end
// second two flops are synchronously reset - this is used for all later flops
// and should ensure the reset is fully synchronous
always @(posedge clk) begin
if (reset_async4) begin
reset_sync0 <= 1'b1;
reset_sync1 <= 1'b1;
end else begin
reset_sync0 <= 1'b0;
reset_sync1 <= reset_sync0;
end
end
assign reset_out = reset_sync1;
endmodule
| 6.663917 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad6676_if (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [63:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output [31:0] adc_data_a,
output [31:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// internal registers
// internal signals
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
wire [63:0] rx_data_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = {adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = {adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]};
assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]};
assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]};
assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
// frame-alignment
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_maxis2wrfifo #(
parameter DATA_WIDTH = 16) (
input clk,
input rstn,
input sync_in,
// m_axis interface
input [DATA_WIDTH-1:0] m_axis_data,
output reg m_axis_ready,
input m_axis_valid,
output reg m_axis_xfer_req,
// write fifo interface
output reg fifo_wr_en,
output reg [DATA_WIDTH-1:0] fifo_wr_data,
output reg fifo_wr_sync,
input fifo_wr_xfer_req
);
always @(posedge clk) begin
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;
m_axis_xfer_req <= 1'b0;
fifo_wr_data <= 'b0;
fifo_wr_en <= 1'b0;
fifo_wr_sync <= 1'b0;
end else begin
m_axis_ready <= 1'b1;
m_axis_xfer_req <= fifo_wr_xfer_req;
fifo_wr_data <= m_axis_data;
fifo_wr_en <= m_axis_valid;
if (sync_in == 1'b1) begin
fifo_wr_sync <= 1'b1;
end else if ((m_axis_valid == 1'b1) &&
(fifo_wr_sync == 1'b1)) begin
fifo_wr_sync <= 1'b0;
end
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9152_if (
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk,
output reg [127:0] tx_data,
// dac interface
output dac_clk,
input dac_rst,
input [15:0] dac_data_0_0,
input [15:0] dac_data_0_1,
input [15:0] dac_data_0_2,
input [15:0] dac_data_0_3,
input [15:0] dac_data_1_0,
input [15:0] dac_data_1_1,
input [15:0] dac_data_1_2,
input [15:0] dac_data_1_3);
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 128'd0;
end else begin
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad9162_if (
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk,
output reg [255:0] tx_data,
// dac interface
output dac_clk,
input dac_rst,
input [255:0] dac_data);
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge tx_clk) begin
tx_data[255:248] <= dac_data[247:240];
tx_data[247:240] <= dac_data[183:176];
tx_data[239:232] <= dac_data[119:112];
tx_data[231:224] <= dac_data[ 55: 48];
tx_data[223:216] <= dac_data[255:248];
tx_data[215:208] <= dac_data[191:184];
tx_data[207:200] <= dac_data[127:120];
tx_data[199:192] <= dac_data[ 63: 56];
tx_data[191:184] <= dac_data[231:224];
tx_data[183:176] <= dac_data[167:160];
tx_data[175:168] <= dac_data[103: 96];
tx_data[167:160] <= dac_data[ 39: 32];
tx_data[159:152] <= dac_data[239:232];
tx_data[151:144] <= dac_data[175:168];
tx_data[143:136] <= dac_data[111:104];
tx_data[135:128] <= dac_data[ 47: 40];
tx_data[127:120] <= dac_data[215:208];
tx_data[119:112] <= dac_data[151:144];
tx_data[111:104] <= dac_data[ 87: 80];
tx_data[103: 96] <= dac_data[ 23: 16];
tx_data[ 95: 88] <= dac_data[223:216];
tx_data[ 87: 80] <= dac_data[159:152];
tx_data[ 79: 72] <= dac_data[ 95: 88];
tx_data[ 71: 64] <= dac_data[ 31: 24];
tx_data[ 63: 56] <= dac_data[199:192];
tx_data[ 55: 48] <= dac_data[135:128];
tx_data[ 47: 40] <= dac_data[ 71: 64];
tx_data[ 39: 32] <= dac_data[ 7: 0];
tx_data[ 31: 24] <= dac_data[207:200];
tx_data[ 23: 16] <= dac_data[143:136];
tx_data[ 15: 8] <= dac_data[ 79: 72];
tx_data[ 7: 0] <= dac_data[ 15: 8];
end
endmodule
| 8.180735 |
module axi_ad9234_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status
);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [63:0] adc_data_a;
output [63:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = {adc_data_a_s3_s, adc_data_a_s2_s, adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = {adc_data_b_s3_s, adc_data_b_s2_s, adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s3_s = {rx_data[31:24], rx_data[63:56]};
assign adc_data_a_s2_s = {rx_data[23:16], rx_data[55:48]};
assign adc_data_a_s1_s = {rx_data[15:8], rx_data[47:40]};
assign adc_data_a_s0_s = {rx_data[7:0], rx_data[39:32]};
assign adc_data_b_s3_s = {rx_data[95:88], rx_data[127:120]};
assign adc_data_b_s2_s = {rx_data[87:80], rx_data[119:112]};
assign adc_data_b_s1_s = {rx_data[79:72], rx_data[111:104]};
assign adc_data_b_s0_s = {rx_data[71:64], rx_data[103:96]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
| 7.781654 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9250_if (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [63:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output [27:0] adc_data_a,
output [27:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// internal registers
// internal signals
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
wire [63:0] rx_data_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s1_s = {rx_data_s[25:24], rx_data_s[23:16], rx_data_s[31:26]};
assign adc_data_a_s0_s = {rx_data_s[ 9: 8], rx_data_s[ 7: 0], rx_data_s[15:10]};
assign adc_data_b_s1_s = {rx_data_s[57:56], rx_data_s[55:48], rx_data_s[63:58]};
assign adc_data_b_s0_s = {rx_data_s[41:40], rx_data_s[39:32], rx_data_s[47:42]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
// frame-alignment
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9361_tdd_if#(
parameter LEVEL_OR_PULSE_N = 0) (
// clock
input clk,
input rst,
// control signals from the tdd control
input tdd_rx_vco_en,
input tdd_tx_vco_en,
input tdd_rx_rf_en,
input tdd_tx_rf_en,
// device interface
output ad9361_txnrx,
output ad9361_enable,
// interface status
output [ 7:0] ad9361_tdd_status);
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// internal registers
reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0;
wire ad9361_txnrx_s;
wire ad9361_enable_s;
// just one VCO can be enabled at a time
assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
generate
if (LEVEL_OR_PULSE_N == PULSE_MODE) begin
reg tdd_rx_rf_en_d = 1'b0;
reg tdd_tx_rf_en_d = 1'b0;
always @(posedge clk) begin
tdd_rx_rf_en_d <= tdd_rx_rf_en;
tdd_tx_rf_en_d <= tdd_tx_rf_en;
end
assign ad9361_enable_s = (tdd_rx_rf_en_d ^ tdd_rx_rf_en) ||
(tdd_tx_rf_en_d ^ tdd_tx_rf_en);
end else
assign ad9361_enable_s = (tdd_rx_rf_en | tdd_tx_rf_en);
endgenerate
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0;
end else begin
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
end
end
assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
assign ad9361_txnrx = ad9361_txnrx_s;
assign ad9361_enable = ad9361_enable_s;
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9680_if (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [127:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output [55:0] adc_data_a,
output [55:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// internal registers
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
wire [127:0] rx_data_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s3_s = {rx_data_s[ 57: 56], rx_data_s[ 31: 24], rx_data_s[ 63: 58]};
assign adc_data_a_s2_s = {rx_data_s[ 49: 48], rx_data_s[ 23: 16], rx_data_s[ 55: 50]};
assign adc_data_a_s1_s = {rx_data_s[ 41: 40], rx_data_s[ 15: 8], rx_data_s[ 47: 42]};
assign adc_data_a_s0_s = {rx_data_s[ 33: 32], rx_data_s[ 7: 0], rx_data_s[ 39: 34]};
assign adc_data_b_s3_s = {rx_data_s[121:120], rx_data_s[ 95: 88], rx_data_s[127:122]};
assign adc_data_b_s2_s = {rx_data_s[113:112], rx_data_s[ 87: 80], rx_data_s[119:114]};
assign adc_data_b_s1_s = {rx_data_s[105:104], rx_data_s[ 79: 72], rx_data_s[111:106]};
assign adc_data_b_s0_s = {rx_data_s[ 97: 96], rx_data_s[ 71: 64], rx_data_s[103: 98]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
// frame-alignment
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9963_rx_pnmon (
// adc interface
input adc_clk,
input adc_valid,
input [11:0] adc_data,
// pn out of sync and error
input [ 3:0] adc_pnseq_sel,
output adc_pn_oos,
output adc_pn_err);
// internal registers
reg [23:0] adc_pn_data_in = 'd0;
reg [23:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// bit reversal function
function [11:0] brfn;
input [11:0] din;
reg [11:0] dout;
begin
dout[11] = din[ 0];
dout[10] = din[ 1];
dout[ 9] = din[ 2];
dout[ 8] = din[ 3];
dout[ 7] = din[ 4];
dout[ 6] = din[ 5];
dout[ 5] = din[ 6];
dout[ 4] = din[ 7];
dout[ 3] = din[ 8];
dout[ 2] = din[ 9];
dout[ 1] = din[10];
dout[ 0] = din[11];
brfn = dout;
end
endfunction
// standard prbs functions
function [23:0] pn23;
input [23:0] din;
reg [23:0] dout;
begin
dout = {din[22:0], din[22] ^ din[17]};
pn23 = dout;
end
endfunction
// standard, runs on 24bit
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
if(adc_valid == 1'b1) begin
adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pattern_has_zero (1'b0),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
| 8.180735 |
module axi_address_remap (
input [33:0] s_hbm_araddr,
input [33:0] s_hbm_awaddr,
output [33:0] m_hbm_araddr,
output [33:0] m_hbm_awaddr,
input [33:0] start_address
);
assign m_hbm_araddr = s_hbm_araddr | start_address;
assign m_hbm_awaddr = s_hbm_awaddr | start_address;
endmodule
| 7.879843 |
module axi_addr_miter(i_last_addr, i_size, i_burst, i_len);
parameter AW = 32,
DW = 32;
input wire [AW-1:0] i_last_addr;
input wire [2:0] i_size; // 1b, 2b, 4b, 8b, etc
input wire [1:0] i_burst; // fixed, incr, wrap, reserved
input wire [7:0] i_len;
localparam DSZ = $clog2(DW)-3;
wire [7:0] ref_incr;
wire [AW-1:0] ref_next_addr;
faxi_addr #(.AW(AW))
ref(i_last_addr, i_size, i_burst, i_len,ref_incr,ref_next_addr);
wire [AW-1:0] uut_next_addr;
axi_addr #(.AW(AW), .DW(DW))
uut(i_last_addr, i_size, i_burst, i_len, uut_next_addr);
always @(*)
assert(DW == (1<<(DSZ+3)));
always @(*)
assume(i_burst != 2'b11);
always @(*)
assume(i_size <= DSZ);
always @(*)
if (i_burst == 2'b10)
begin
assume((i_len == 1)
||(i_len == 3)
||(i_len == 7)
||(i_len == 15));
end
reg aligned;
always @(*)
begin
aligned = 0;
case(DSZ)
3'b000: aligned = 1;
3'b001: aligned = (i_last_addr[0] == 0);
3'b010: aligned = (i_last_addr[1:0] == 0);
3'b011: aligned = (i_last_addr[2:0] == 0);
3'b100: aligned = (i_last_addr[3:0] == 0);
3'b101: aligned = (i_last_addr[4:0] == 0);
3'b110: aligned = (i_last_addr[5:0] == 0);
3'b111: aligned = (i_last_addr[6:0] == 0);
endcase
end
always @(*)
if (i_burst == 2'b10)
assume(aligned);
always @(*)
assert(uut_next_addr == ref_next_addr);
always @(*)
if (i_burst == 2'b01)
assume(i_last_addr[AW-1:12] == ref_next_addr[AW-1:12]);
endmodule
| 7.095801 |
module axi_add_preamble #(
parameter WIDTH = 64
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
//
output reg [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
function [0:0] cvita_get_has_time;
input [63:0] header;
cvita_get_has_time = header[61];
endfunction
//States
localparam IDLE = 0;
localparam PREAMBLE = 1;
localparam PASS = 3;
localparam EOP = 4;
localparam CRC = 5;
localparam PAYLOAD_WORDCOUNT_WIDTH = 16;
localparam PAYLOAD_CHKSUM_WIDTH = 32;
localparam CONTROL_CHKSUM_WIDTH = 16;
reg [2:0] state, next_state;
reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] word_count;
reg [PAYLOAD_WORDCOUNT_WIDTH-1:0] cntrl_length = 16'd2;
wire [PAYLOAD_CHKSUM_WIDTH-1:0] payload_chksum;
wire [CONTROL_CHKSUM_WIDTH-1:0] control_chksum;
// Payload LFSR
crc_xnor #(
.INPUT_WIDTH (WIDTH),
.OUTPUT_WIDTH(PAYLOAD_CHKSUM_WIDTH)
) payload_chksum_gen (
.clk(clk),
.rst(word_count <= cntrl_length),
.hold(~(i_tready && i_tvalid)),
.input_data(i_tdata),
.crc_out(payload_chksum)
);
// Control LFSR
crc_xnor #(
.INPUT_WIDTH (WIDTH),
.OUTPUT_WIDTH(CONTROL_CHKSUM_WIDTH)
) control_chksum_gen (
.clk(clk),
.rst(word_count == 'd0),
.hold(~(i_tready && i_tvalid) || word_count >= cntrl_length),
.input_data(i_tdata),
.crc_out(control_chksum)
);
//Update control length so control checksum is correct
always @(posedge clk) begin
if (state == IDLE && i_tvalid) cntrl_length <= cvita_get_has_time(i_tdata) ? 16'd2 : 16'd1;
end
//Note that word_count includes EOP
always @(posedge clk) begin
if (state == IDLE) begin
word_count <= 0;
end else if (i_tready && i_tvalid || (o_tready && state == EOP)) begin
word_count <= word_count + 1;
end
end
always @(posedge clk)
if (reset | clear) begin
state <= IDLE;
end else begin
state <= next_state;
end
always @(*) begin
case (state)
IDLE: begin
if (i_tvalid) begin
next_state = PREAMBLE;
end else begin
next_state = IDLE;
end
end
PREAMBLE: begin
if (o_tready) begin
next_state = PASS;
end else begin
next_state = PREAMBLE;
end
end
PASS: begin
if (i_tready && i_tvalid && i_tlast) begin
next_state = EOP;
end else begin
next_state = PASS;
end
end
EOP: begin
if (o_tready) begin
next_state = CRC;
end else begin
next_state = EOP;
end
end
CRC: begin
if (o_tready) begin
next_state = IDLE;
end else begin
next_state = CRC;
end
end
default: begin
next_state = IDLE;
end
endcase
end
//
// Muxes
//
always @* begin
case (state)
IDLE: o_tdata = 0;
PASS: o_tdata = i_tdata;
PREAMBLE: o_tdata = 64'h9E6774129E677412;
EOP: o_tdata = 64'h2A1D632F2A1D632F;
CRC: o_tdata = {control_chksum, word_count, payload_chksum};
default: o_tdata = 0;
endcase
end
assign o_tvalid = (state == PASS) ? i_tvalid : (state != IDLE);
assign i_tready = (state == PASS) ? o_tready : 1'b0;
endmodule
| 8.68711 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr_mstatus (
input up_rstn,
input up_clk,
input up_pll_locked_in,
input up_rst_done_in,
input up_pll_locked,
input up_rst_done,
output up_pll_locked_out,
output up_rst_done_out);
// parameters
parameter integer XCVR_ID = 0;
parameter integer NUM_OF_LANES = 8;
// internal registers
reg up_pll_locked_int = 'd0;
reg up_rst_done_int = 'd0;
// internal signals
wire up_pll_locked_s;
wire up_rst_done_s;
// daisy-chain the signals
assign up_pll_locked_out = up_pll_locked_int;
assign up_rst_done_out = up_rst_done_int;
assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1;
assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_pll_locked_int <= 1'd0;
up_rst_done_int <= 1'd0;
end else begin
up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s;
up_rst_done_int <= up_rst_done_in & up_rst_done_s;
end
end
endmodule
| 8.180735 |
module axi_alu_data_v1_0 #(
// Users to add parameters here
parameter SIZE = 16,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
) (
// Users to add ports here
output wire [SIZE-1:0] A,
output wire [SIZE-1:0] B,
output wire [2:0] code,
input wire [SIZE-1:0] Y,
input wire C_out,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
axi_alu_data_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axi_alu_data_v1_0_S00_AXI_inst (
.A(A),
.B(B),
.code(code),
.Y(Y),
.C_out(C_out),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 8.145305 |
module axi_apb_bridge_0_multiplexor (
m_apb_psel,
\GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ,
PSEL_i,
s_axi_aclk
);
output [0:0] m_apb_psel;
input \GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ;
input PSEL_i;
input s_axi_aclk;
wire \GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ;
wire PSEL_i;
wire [0:0] m_apb_psel;
wire s_axi_aclk;
FDRE \GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0] (
.C (s_axi_aclk),
.CE(1'b1),
.D (PSEL_i),
.Q (m_apb_psel),
.R (\GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 )
);
endmodule
| 7.048782 |
module axi_arbiter_stom_s2
// synopsys translate_off
`protect
// synopsys translate_on
#(parameter NUM = 2)
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input wire [NUM:0] BREADY
, output wire [NUM:0] BGRANT
//-----------------------------------------------------------
, input wire [NUM:0] RSELECT // selected by comparing trans_id
, input wire [NUM:0] RVALID
, input wire [NUM:0] RREADY
, input wire [NUM:0] RLAST
, output wire [NUM:0] RGRANT
);
//-----------------------------------------------------------
// read-data arbiter
//-----------------------------------------------------------
reg [NUM:0] rgrant_reg;
//-----------------------------------------------------------
reg stateR;
localparam STR_RUN = 'h0,
STR_WAIT = 'h1;
always @ (posedge ACLK or negedge ARESETn) begin
if (ARESETn==1'b0) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end else begin
case (stateR)
STR_RUN: begin
if (|RGRANT) begin
if (~|(RGRANT&RREADY&RLAST)) begin
rgrant_reg <= RGRANT;
stateR <= STR_WAIT;
end
end
end // STR_RUN
STR_WAIT: begin
if (|(RGRANT&RVALID&RREADY&RLAST)) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end
end // STR_WAIT
endcase
end
end
//-----------------------------------------------------------
assign RGRANT = (stateR==STR_RUN) ? priority_sel(RSELECT&RVALID)
: rgrant_reg;
//-----------------------------------------------------------
// write-response arbiter
//-----------------------------------------------------------
reg [NUM:0] bgrant_reg;
//-----------------------------------------------------------
reg stateB;
localparam STB_RUN = 'h0,
STB_WAIT = 'h1;
always @ (posedge ACLK or negedge ARESETn) begin
if (ARESETn==1'b0) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end else begin
case (stateB)
STB_RUN: begin
if (|BGRANT) begin
if (~|(BGRANT&BREADY)) begin
bgrant_reg <= BGRANT;
stateB <= STB_WAIT;
end
end
end // STB_RUN
STB_WAIT: begin
if (|(BGRANT&BVALID&BREADY)) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end
end // STB_WAIT
endcase
end
end
//-----------------------------------------------------------
assign BGRANT = (stateB==STB_RUN) ? priority_sel(BSELECT&BVALID)
: bgrant_reg;
//-----------------------------------------------------------
function [NUM:0] priority_sel;
input [NUM:0] request;
begin
casex (request)
3'b000: priority_sel = 3'b000;
3'bxx1: priority_sel = 3'b001;
3'bx10: priority_sel = 3'b010;
3'b100: priority_sel = 3'b100;
endcase
end
endfunction
//-----------------------------------------------------------
// synopsys translate_off
`endprotect
// synopsys translate_on
endmodule
| 7.648984 |
module axi_async_w #(
parameter aw = 4,
parameter w = 32
) (
input rst_n,
input clka,
input wvalida,
output wreadya,
input [aw-1:0] waddra,
input [w-1:0] wdataa,
input clkb,
output wvalidb,
input wreadyb,
output reg [aw-1:0] waddrb,
output reg [w-1:0] wdatab
);
reg [2:0] avalid;
reg [2:0] aready;
always @(posedge clka or negedge rst_n) begin
if (!rst_n) begin
aready[2:1] <= 2'b00;
avalid[0] <= 1'b0;
end else begin
aready[2:1] <= aready[1:0];
if (wreadya && wvalida) begin
avalid[0] <= !avalid[0];
waddrb <= waddra;
wdatab <= wdataa;
end
end
end
always @(posedge clkb or negedge rst_n) begin
if (!rst_n) begin
avalid[2:1] <= 2'b00;
aready[0] <= 1'b0;
end else begin
avalid[2:1] <= avalid[1:0];
if (wvalidb && wreadyb) begin
aready[0] <= !aready[0];
end
end
end
assign wreadya = (avalid[0] == aready[2]);
assign wvalidb = (avalid[2] != aready[0]);
endmodule
| 7.87238 |
module axi_axis_reader #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [ 1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [ 1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Slave side
output wire s_axis_tready,
input wire [AXI_DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH) {1'b0}};
end else begin
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @* begin
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if (s_axi_arvalid) begin
int_rvalid_next = 1'b1;
int_rdata_next = s_axis_tvalid ? s_axis_tdata : {(AXI_DATA_WIDTH) {1'b0}};
end
if (s_axi_rready & int_rvalid_reg) begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = 1'b1;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
assign s_axis_tready = s_axi_rready & int_rvalid_reg;
endmodule
| 7.262688 |
module axi_axis_writer #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [ 1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [ 1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Master side
output wire [AXI_DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg int_ready_reg, int_ready_next;
reg int_valid_reg, int_valid_next;
reg [AXI_DATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
always @(posedge aclk) begin
if (~aresetn) begin
int_valid_reg <= 1'b0;
end else begin
int_valid_reg <= int_valid_next;
end
end
always @* begin
int_valid_next = int_valid_reg;
if (s_axi_wvalid) begin
int_valid_next = 1'b1;
end
if (s_axi_bready & int_valid_reg) begin
int_valid_next = 1'b0;
end
end
assign s_axi_bresp = 2'd0;
assign s_axi_awready = 1'b1;
assign s_axi_wready = 1'b1;
assign s_axi_bvalid = int_valid_reg;
assign m_axis_tdata = s_axi_wdata;
assign m_axis_tvalid = s_axi_wvalid;
endmodule
| 7.828766 |
module axi_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers,
axreadym
);
parameter ADDR_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + ADDR_WIDTH + USER_WIDTH + 26;
input aclk;
input aresetn;
input axvalids;
output axreadys;
input [ID_WIDTH-1:0] axids;
input [ADDR_WIDTH-1:0] axaddrs;
input [3:0] axlens;
input [2:0] axsizes;
input [1:0] axbursts;
input [1:0] axlocks;
input [3:0] axcaches;
input [2:0] axprots;
input [3:0] axregions;
input [3:0] axqoss;
input [USER_WIDTH-1:0] axusers;
output axvalidm;
input axreadym;
output [ID_WIDTH-1:0] axidm;
output [ADDR_WIDTH-1:0] axaddrm;
output [3:0] axlenm;
output [2:0] axsizem;
output [1:0] axburstm;
output [1:0] axlockm;
output [3:0] axcachem;
output [2:0] axprotm;
output [3:0] axregionm;
output [3:0] axqosm;
output [USER_WIDTH-1:0] axuserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = axvalids;
assign payload_src = {
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers
};
assign axreadys = ready_src;
assign axvalidm = valid_dst;
assign {axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm} = payload_dst;
assign ready_dst = axreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.858387 |
module axi_bfm_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_TRANSACTIONS_NUM = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_init_axi_txn,
output wire m00_axi_error,
output wire m00_axi_txn_done,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
axi_bfm_v1_0_M00_AXI #(
.C_M_START_DATA_VALUE(C_M00_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M00_AXI_TRANSACTIONS_NUM)
) axi_bfm_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.ERROR(m00_axi_error),
.TXN_DONE(m00_axi_txn_done),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.770154 |
module axi_bfm_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (
.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_ERROR),
.M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN)
);
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
// Drive the BFM
initial begin
// Wait for end of reset
wait (tb_ARESETn === 0) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
wait (tb_ARESETn === 1) @(posedge tb_ACLK);
M00_AXI_INIT_AXI_TXN = 1'b0;
#500 M00_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M00_AXI:");
wait (M00_AXI_TXN_DONE == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if (M00_AXI_ERROR) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule
| 6.859338 |
module axi_bit_reduce #(
parameter WIDTH_IN = 48,
parameter WIDTH_OUT = 25,
parameter DROP_TOP = 6,
parameter VECTOR_WIDTH = 1
) // vector_width = 2 for complex, 1 for real
(
input [VECTOR_WIDTH*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [VECTOR_WIDTH*WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
genvar i;
generate
for (i = 0; i < VECTOR_WIDTH; i = i + 1)
assign o_tdata[(i+1)*WIDTH_OUT-1:i*WIDTH_OUT] = i_tdata[(i+1)*WIDTH_IN-DROP_TOP-1:i*WIDTH_IN+(WIDTH_IN-WIDTH_OUT)-DROP_TOP];
endgenerate
assign o_tlast = i_tlast;
assign o_tvalid = i_tvalid;
assign i_tready = o_tready;
endmodule
| 6.620806 |
module axi_bpsk_ctrl_v1_0 #(
// Users to add parameters here
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input wire clk, //ʱź
input wire rst_n, //λź
output wire ram_clk, //RAMʱ
input wire [data_width-1 : 0] ram_rd_data, //RAMж
output wire ram_en, //RAMʹź
output wire [addr_width-1 : 0] ram_addr, //RAMַ
output wire [ 3:0] ram_we, //RAMдź 1д 0
output wire [data_width-1 : 0] ram_wr_data, //RAMд
output wire ram_rst, //RAMλź,ߵƽЧ
output wire [ 1:0] interrupt_num, // 01b=ʹram1 10b=ʹram2
output wire gen_en,
output wire phase_ctrl,
output wire baud,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
axi_bpsk_ctrl_v1_0_S00_AXI #(
.data_width (data_width),
.frame_length (frame_length),
.addr_width (addr_width),
.ref_clk_freq (ref_clk_freq),
.baudrate (baudrate),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axi_bpsk_ctrl_v1_0_S00_AXI_inst (
.S_AXI_ACLK (s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR (s00_axi_awaddr),
.S_AXI_AWPROT (s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA (s00_axi_wdata),
.S_AXI_WSTRB (s00_axi_wstrb),
.S_AXI_WVALID (s00_axi_wvalid),
.S_AXI_WREADY (s00_axi_wready),
.S_AXI_BRESP (s00_axi_bresp),
.S_AXI_BVALID (s00_axi_bvalid),
.S_AXI_BREADY (s00_axi_bready),
.S_AXI_ARADDR (s00_axi_araddr),
.S_AXI_ARPROT (s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA (s00_axi_rdata),
.S_AXI_RRESP (s00_axi_rresp),
.S_AXI_RVALID (s00_axi_rvalid),
.S_AXI_RREADY (s00_axi_rready),
.clk (clk),
.rst_n (rst_n),
.ram_clk (ram_clk),
.ram_rd_data (ram_rd_data),
.ram_en (ram_en),
.ram_addr (ram_addr),
.ram_we (ram_we),
.ram_wr_data (ram_wr_data),
.ram_rst (ram_rst),
.interrupt_num(interrupt_num),
.gen_en (gen_en),
.phase_ctrl (phase_ctrl),
.baud (baud)
);
// Add user logic here
// User logic ends
endmodule
| 7.387489 |
module axi_bram_reader_v1_0 #(
// Users to add parameters here
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 13,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 15
) (
// Users to add ports here
//output wire [7:0] led_out,
// Ports for BRAM
output bram_porta_en,
input [BRAM_DATA_WIDTH-1:0] bram_porta_dout,
output [BRAM_DATA_WIDTH-1:0] bram_porta_din,
output [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output [3:0] bram_porta_we,
output bram_porta_clk,
output bram_porta_rst,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
bram_reader_v1_0_S00_AXI #(
.BRAM_DATA_WIDTH(BRAM_DATA_WIDTH),
.BRAM_ADDR_WIDTH(BRAM_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) bram_reader_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.bram_addr(bram_porta_addr),
.bram_data(bram_porta_dout)
);
// Add user logic here
assign bram_porta_en = 1;
assign bram_porta_we = 4'd0;
assign bram_porta_clk = s00_axi_aclk;
assign bram_porta_rst = ~s00_axi_aresetn;
assign bram_porta_din = {(BRAM_DATA_WIDTH) {1'b0}};
//assign led_out = bram_porta_addr;
// User logic ends
endmodule
| 7.060334 |
module axi_bram_writer #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [ AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [ AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [ 1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [ AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [ AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [ 1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [ BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [ BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH/8-1:0] bram_porta_we
);
function integer clogb2(input integer value);
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH / 8 - 1);
reg int_bvalid_reg, int_bvalid_next;
wire int_wvalid_wire;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
always @(posedge aclk) begin
if (~aresetn) begin
int_bvalid_reg <= 1'b0;
end else begin
int_bvalid_reg <= int_bvalid_next;
end
end
always @* begin
int_bvalid_next = int_bvalid_reg;
if (int_wvalid_wire) begin
int_bvalid_next = 1'b1;
end
if (s_axi_bready & int_bvalid_reg) begin
int_bvalid_next = 1'b0;
end
end
assign s_axi_bresp = 2'd0;
assign s_axi_awready = int_wvalid_wire;
assign s_axi_wready = int_wvalid_wire;
assign s_axi_bvalid = int_bvalid_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = s_axi_awaddr[ADDR_LSB+BRAM_ADDR_WIDTH-1:ADDR_LSB];
assign bram_porta_wrdata = s_axi_wdata;
assign bram_porta_we = int_wvalid_wire ? s_axi_wstrb : {(BRAM_DATA_WIDTH / 8) {1'b0}};
endmodule
| 7.308028 |
module axi_broadcast_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.543268 |
module axi_broadcast_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.543268 |
module axi_buffer #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 2,
parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH)
) (
clk_i,
rst_ni,
data_o,
valid_o,
ready_i,
valid_i,
data_i,
ready_o
);
//parameter DATA_WIDTH = 32;
//parameter BUFFER_DEPTH = 2;
//parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH);
input wire clk_i;
input wire rst_ni;
output wire [DATA_WIDTH - 1:0] data_o;
output wire valid_o;
input wire ready_i;
input wire valid_i;
input wire [DATA_WIDTH - 1:0] data_i;
output wire ready_o;
reg [LOG_BUFFER_DEPTH - 1:0] pointer_in;
reg [LOG_BUFFER_DEPTH - 1:0] pointer_out;
reg [LOG_BUFFER_DEPTH:0] elements;
reg [DATA_WIDTH - 1:0] buffer[BUFFER_DEPTH - 1:0];
wire full;
reg [31:0] loop1;
assign full = elements == BUFFER_DEPTH;
always @(posedge clk_i or negedge rst_ni) begin : elements_sequential
if (rst_ni == 1'b0) elements <= 0;
else if ((ready_i && valid_o) && (!valid_i || full)) elements <= elements - 1;
else if (((!valid_o || !ready_i) && valid_i) && !full) elements <= elements + 1;
end
always @(posedge clk_i or negedge rst_ni) begin : buffers_sequential
if (rst_ni == 1'b0) begin
for (loop1 = 0; loop1 < BUFFER_DEPTH; loop1 = loop1 + 1) buffer[loop1] <= 0;
end else if (valid_i && !full) buffer[pointer_in] <= data_i;
end
always @(posedge clk_i or negedge rst_ni) begin : sequential
if (rst_ni == 1'b0) begin
pointer_out <= 0;
pointer_in <= 0;
end else begin
if (valid_i && !full)
if (pointer_in == $unsigned(BUFFER_DEPTH - 1)) pointer_in <= 0;
else pointer_in <= pointer_in + 1;
if (ready_i && valid_o)
if (pointer_out == $unsigned(BUFFER_DEPTH - 1)) pointer_out <= 0;
else pointer_out <= pointer_out + 1;
end
end
assign data_o = buffer[pointer_out];
assign valid_o = elements != 0;
assign ready_o = ~full;
endmodule
| 8.345277 |
module axi_b_reg_slice (
bvalids,
bids,
bresps,
busers,
breadym,
aclk,
aresetn,
breadys,
bvalidm,
bidm,
brespm,
buserm
);
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + USER_WIDTH + 2;
input aclk;
input aresetn;
output bvalids;
input breadys;
output [ID_WIDTH-1:0] bids;
output [1:0] bresps;
output [USER_WIDTH-1:0] busers;
input bvalidm;
output breadym;
input [ID_WIDTH-1:0] bidm;
input [1:0] brespm;
input [USER_WIDTH-1:0] buserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = bvalidm;
assign breadym = ready_src;
assign payload_src = {bidm, brespm, buserm};
assign bvalids = valid_dst;
assign ready_dst = breadys;
assign {bids, bresps, busers} = payload_dst;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.240446 |
module axi_channel_split_slice (
ready_src,
valid_dst,
payload_dst,
aclk,
aresetn,
valid_src,
payload_src,
ready_dst
);
parameter N_OUTPUTS = 2;
parameter PAYLD_WIDTH = 8;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter BITS_PER_CHUNK = 8;
input aclk;
input aresetn;
input valid_src;
input [PAYLD_WIDTH-1:0] payload_src;
output ready_src;
output [N_OUTPUTS-1:0] valid_dst;
output [PAYLD_WIDTH-1:0] payload_dst;
input [N_OUTPUTS-1:0] ready_dst;
logic valid_int;
logic ready_int;
axi_channel_reg_slice #(
.PAYLD_WIDTH (PAYLD_WIDTH),
.HNDSHK_MODE (HNDSHK_MODE),
.BITS_PER_CHUNK(BITS_PER_CHUNK)
) u_reg_slice (
.ready_src (ready_src),
.valid_dst (valid_int),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_int)
);
axi_hndshk_split #(
.N_OUTPUTS(N_OUTPUTS)
) u_hndshk_split (
.ready_src(ready_int),
.valid_dst(valid_dst[N_OUTPUTS-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src(valid_int),
.ready_dst(ready_dst[N_OUTPUTS-1:0])
);
endmodule
| 7.146376 |
module axi_chdr_header_trigger #(
parameter WIDTH = 64,
parameter SID = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
input i_tready,
output trigger
);
reg state;
localparam IDLE = 0;
localparam RUN = 1;
always @(posedge clk)
if (reset | clear) state <= IDLE;
else
case (state)
IDLE: if (i_tvalid && i_tready) state <= RUN;
RUN: if (i_tready && i_tvalid && i_tlast) state <= IDLE;
default: state <= IDLE;
endcase // case (state)
assign trigger = i_tvalid && i_tready && (state == IDLE) && (i_tdata[15:0] != SID);
endmodule
| 6.903454 |
module axi_clip_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter FIFOSIZE = 0
) // leave at 0 for a single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH_OUT-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH_IN-1:0] ii_tdata, iq_tdata;
wire ii_tlast, ii_tvalid, ii_tready, iq_tlast, iq_tvalid, iq_tready;
wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata;
wire oi_tlast, oi_tvalid, oi_tready, oq_tlast, oq_tvalid, oq_tready;
split_complex #(
.WIDTH(WIDTH_IN)
) split_complex (
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
.oi_tdata (ii_tdata),
.oi_tlast (ii_tlast),
.oi_tvalid(ii_tvalid),
.oi_tready(ii_tready),
.oq_tdata (iq_tdata),
.oq_tlast (iq_tlast),
.oq_tvalid(iq_tvalid),
.oq_tready(iq_tready)
);
axi_clip #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.FIFOSIZE (FIFOSIZE)
) axi_clip_i (
.clk(clk),
.reset(reset),
.i_tdata(ii_tdata),
.i_tlast(ii_tlast),
.i_tvalid(ii_tvalid),
.i_tready(ii_tready),
.o_tdata(oi_tdata),
.o_tlast(oi_tlast),
.o_tvalid(oi_tvalid),
.o_tready(oi_tready)
);
axi_clip #(
.WIDTH_IN (WIDTH_IN),
.WIDTH_OUT(WIDTH_OUT),
.FIFOSIZE (FIFOSIZE)
) axi_clip_q (
.clk(clk),
.reset(reset),
.i_tdata(iq_tdata),
.i_tlast(iq_tlast),
.i_tvalid(iq_tvalid),
.i_tready(iq_tready),
.o_tdata(oq_tdata),
.o_tlast(oq_tlast),
.o_tvalid(oq_tvalid),
.o_tready(oq_tready)
);
join_complex #(
.WIDTH(WIDTH_OUT)
) join_complex (
.ii_tdata (oi_tdata),
.ii_tlast (oi_tlast),
.ii_tvalid(oi_tvalid),
.ii_tready(oi_tready),
.iq_tdata (oq_tdata),
.iq_tlast (oq_tlast),
.iq_tvalid(oq_tvalid),
.iq_tready(oq_tready),
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready)
);
endmodule
| 6.720438 |
module axi_clock_converter_v2_1_6_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO - 1 : C_RATIO - 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *)reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY - 1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule
| 7.39423 |
module axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO - 1 : C_RATIO - 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 1'b0;
reg posedge_finder_first = 1'b0;
reg posedge_finder_second = 1'b0;
wire first_edge;
wire second_edge;
wire any_edge;
reg [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};
(* shreg_extract = "no" *)reg sample_cycle_r = 1'b0;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
assign any_edge = first_edge | second_edge;
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY - 1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
if (i == P_DELAY - 1) begin
sample_cycle_d[i-1] <= any_edge;
end else begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= (P_DELAY > 1) ? sample_cycle_d[0] : any_edge;
end
assign SAMPLE_CYCLE_EARLY = (P_DELAY > 1) ? sample_cycle_d[0] : any_edge;
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule
| 7.39423 |
module axi_ms #
(
// 其他参数
parameter integer INST_ADDR_WIDTH =32,
// slave 接口参数
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4,
// master 接口参数
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
// cpu 接口
reg [0:INST_ADDR_WIDTH-1] inst_addr,
// axi-lite 的 slave 接口
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr,
input wire [2 : 0] s_axi_awprot,
input wire s_axi_awvalid,
output reg s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] s_axi_wstrb,
input wire s_axi_wvalid,
output reg s_axi_wready,
output reg [1 : 0] s_axi_bresp,
output reg s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr,
input wire [2 : 0] s_axi_arprot,
input wire s_axi_arvalid,
output reg s_axi_arready,
output reg [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_rdata,
output reg [1 : 0] s_axi_rresp,
output reg s_axi_rvalid,
input wire s_axi_rready,
// axi-lite 的 master 接口
input wire m_axi_aclk,
input wire m_axi_aresetn,
output reg [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output reg [2 : 0] m_axi_awprot,
output reg m_axi_awvalid,
input wire m_axi_awready,
output reg [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output reg [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output reg m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output reg m_axi_bready,
output reg [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr,
output reg [2 : 0] m_axi_arprot,
output reg m_axi_arvalid,
input wire m_axi_arready,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata,
input wire [1 : 0] m_axi_rresp,
input wire m_axi_rvalid,
output reg m_axi_rready
);
// 用来判断 slave 接口行为
reg is_s_read;
reg is_s_write;
// read 操作
axi_lite_master_read
// write 操作
endmodule
| 7.398281 |
module axi_conv #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8),
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter CNT_WIDTH = 9, //( 0- 511)
// to which number should the counter count?
parameter CNT_MAX = 511, //( 0 - 511)
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter KEEP_WIDTH = 1 //(
) (
input clk,
input rst_L,
/*
* AXI lite master interface
*/
output m_axis_tvalid,
input m_axis_tready,
input [DATA_WIDTH-1:0] i_data, //CONV
output o_fifo_en, //invokes next byte from fifo
output [DATA_WIDTH-1:0] m_axis_tdata,
output [KEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast
);
assign m_axis_tkeep = {KEEP_WIDTH{1'b1}};
reg [DATA_WIDTH-1:0] counter_r = 'h00;
reg last_r = 1'b0;
reg valid_r = 1'b0;
reg zeroflag_r = 1'b1;
reg [DATA_WIDTH-1:0] data_r; //CONV
reg fifo_en_r;
assign o_fifo_en = fifo_en_r;
//assign m_axis_tdata = counter_r;
assign m_axis_tdata = data_r; //CONV
//assign m_axis_tvalid = 1'b1; // Allways valid
assign m_axis_tvalid = valid_r;
assign m_axis_tlast = last_r;
always @(posedge clk or negedge rst_L) begin
fifo_en_r <= 1'b0; //default
if (~rst_L) begin
counter_r <= 32'h00;
last_r <= 1'b0;
valid_r <= 1'b0;
end else begin
if ( /*axi_tvalid == 1 && */ m_axis_tready == 1'b1) begin
if (zeroflag_r == 1'b1) begin
//counter_r <= 32'd0;
zeroflag_r <= 1'b0;
end else begin
data_r <= i_data; //CONV
counter_r <= counter_r + 1'd1;
fifo_en_r <= 1'b1; //loads next byte from fifo
end
valid_r <= 1'b1;
end
if (counter_r == (CNT_MAX - 1)) begin
last_r <= 1'b1;
end else begin
last_r <= 1'b0;
end
if (counter_r >= (CNT_MAX)) begin
last_r <= 1'b0;
//counter_r[CNT_WIDTH-1:0] <= {CNT_WIDTH{1'b1}};
counter_r <= 32'd0;
zeroflag_r <= 1'b1;
valid_r <= 1'b0;
end
// if (m_axis_tready) begin // Count if AXI slave is ready
// counter_r <= counter_r + 1;
// valid_r <= 1'b1;
// if (counter_r[CNT_WIDTH-1:0] == {CNT_WIDTH{1'b1}}) begin //{CNT_WIDTH{1'b1}}) // CNT_WIDTH'd512
// last_r <= 1'b1;
// end else begin
// last_r <= 1'b0;
// end
// end
end
end
endmodule
| 8.236837 |
module axi_counter #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8),
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter CNT_WIDTH = 9, //( 0- 511)
// to which number should the counter count?
parameter CNT_MAX = 511, //( 0 - 511)
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter KEEP_WIDTH = 1 //(
) (
input clk,
input rst_L,
/*
* AXI lite master interface
*/
output m_axis_tvalid,
input m_axis_tready,
output [DATA_WIDTH-1:0] m_axis_tdata,
output [KEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast
);
assign m_axis_tkeep = {KEEP_WIDTH{1'b1}};
reg [DATA_WIDTH-1:0] counter_r = 'h00;
reg last_r = 1'b0;
reg valid_r = 1'b0;
reg zeroflag_r = 1'b1;
assign m_axis_tdata = counter_r;
//assign m_axis_tvalid = 1'b1; // Allways valid
assign m_axis_tvalid = valid_r;
assign m_axis_tlast = last_r;
always @(posedge clk or negedge rst_L)
if (~rst_L) begin
counter_r <= 'h00;
last_r <= 1'b0;
valid_r <= 1'b0;
end else begin
if ( /*axi_tvalid == 1 && */ m_axis_tready == 1'b1) begin
if (zeroflag_r == 1'b1) begin
//counter_r <= 32'd0;
zeroflag_r <= 1'b0;
end else begin
counter_r <= counter_r + 1'd1;
end
valid_r <= 1'b1;
end
if (counter_r == (CNT_MAX - 1)) begin
last_r <= 1'b1;
end else begin
last_r <= 1'b0;
end
if (counter_r >= (CNT_MAX)) begin
last_r <= 1'b0;
//counter_r[CNT_WIDTH-1:0] <= {CNT_WIDTH{1'b1}};
counter_r <= 32'd0;
zeroflag_r <= 1'b1;
valid_r <= 1'b0;
end
// if (m_axis_tready) begin // Count if AXI slave is ready
// counter_r <= counter_r + 1;
// valid_r <= 1'b1;
// if (counter_r[CNT_WIDTH-1:0] == {CNT_WIDTH{1'b1}}) begin //{CNT_WIDTH{1'b1}}) // CNT_WIDTH'd512
// last_r <= 1'b1;
// end else begin
// last_r <= 1'b0;
// end
// end
end
endmodule
| 7.729896 |
module axi_counter_tb;
//input
reg clk;
reg rst_L;
reg m_axis_tready;
//output
wire m_axis_tvalid;
wire [32-1:0] m_axis_tdata;
wire [1-1:0] m_axis_tkeep;
wire m_axis_tlast;
// FPAG Clk gen
always begin
clk = 1'b1;
#5 clk = 1'b0;
#5;
end
// SPI Master Clk gena
// always begin
// i_SPI_Clk = 1'b1;
// #50 i_SPI_Clk = 1'b0;
// #50;
// end
axi_counter #(
.DATA_WIDTH(32),
.CNT_WIDTH(5),
.CNT_MAX(511),
.KEEP_WIDTH(1)
) uut (
.clk(clk), // i
.rst_L(rst_L), // i
.m_axis_tready(m_axis_tready), // i
.m_axis_tvalid(m_axis_tvalid), //o
.m_axis_tdata(m_axis_tdata), // o
.m_axis_tkeep(m_axis_tkeep), // o
.m_axis_tlast(m_axis_tlast) // o
);
initial begin
// Initialize Inputs
rst_L = 1'b1;
#10;
rst_L = 1'b0;
#10;
rst_L = 1'b1;
m_axis_tready = 1'b0;
#10;
m_axis_tready = 1'b1;
end
endmodule
| 6.532829 |
module axi_count_packets_in_fifo (
input clk,
input reset,
input in_axis_tvalid,
input in_axis_tready,
input in_axis_tlast,
input out_axis_tvalid,
input out_axis_tready,
input out_axis_tlast,
input pkt_tx_full,
output enable_tx
);
localparam WAIT_SOF = 0;
localparam WAIT_EOF = 1;
localparam WAIT_FULL = 0;
localparam DELAY_TO_EOF = 1;
localparam WAIT_SPACE = 2;
reg in_state, out_state;
reg [1:0] full_state;
reg pause_tx;
reg [7:0] pkt_count;
//
// Count packets arriving into large FIFO
//
always @(posedge clk)
if (reset) begin
in_state <= WAIT_SOF;
end else
case (in_state)
WAIT_SOF:
if (in_axis_tvalid && in_axis_tready) begin
in_state <= WAIT_EOF;
end else begin
in_state <= WAIT_SOF;
end
WAIT_EOF:
if (in_axis_tlast && in_axis_tvalid && in_axis_tready) begin
in_state <= WAIT_SOF;
end else begin
in_state <= WAIT_EOF;
end
endcase // case(in_state)
//
// Count packets leaving large FIFO
//
always @(posedge clk)
if (reset) begin
out_state <= WAIT_SOF;
end else
case (out_state)
WAIT_SOF:
if (out_axis_tvalid && out_axis_tready) begin
out_state <= WAIT_EOF;
end else begin
out_state <= WAIT_SOF;
end
WAIT_EOF:
if (out_axis_tlast && out_axis_tvalid && out_axis_tready) begin
out_state <= WAIT_SOF;
end else begin
out_state <= WAIT_EOF;
end
endcase // case(in_state)
//
// Count packets in FIFO.
// No protection on counter wrap,
// unclear how such an error could occur or how to gracefully deal with it.
//
always @(posedge clk)
if (reset) pkt_count <= 0;
else if (((out_state==WAIT_EOF) && out_axis_tlast && out_axis_tvalid && out_axis_tready)
&& ((in_state==WAIT_EOF) && in_axis_tlast && in_axis_tvalid && in_axis_tready))
pkt_count <= pkt_count;
else if ((out_state == WAIT_EOF) && out_axis_tlast && out_axis_tvalid && out_axis_tready)
pkt_count <= pkt_count - 1;
else if ((in_state == WAIT_EOF) && in_axis_tlast && in_axis_tvalid && in_axis_tready)
pkt_count <= pkt_count + 1;
//
// Guard against Tx MAC overflow (as indicated by pkt_tx_full)
//
always @(posedge clk)
if (reset) begin
pause_tx <= 0;
full_state <= WAIT_FULL;
end else begin
pause_tx <= 0;
case (full_state)
WAIT_FULL:
// Search for pkt_tx_full going asserted
if (pkt_tx_full && (out_state == WAIT_SOF)) begin
full_state <= WAIT_SPACE;
pause_tx <= 1;
end else if (pkt_tx_full && (out_state == WAIT_EOF)) begin
full_state <= DELAY_TO_EOF;
end
DELAY_TO_EOF:
// pkt_tx_full has gone asserted during Tx of a packet from FIFO.
// Wait until either FIFO has space again and transition direct to WAIT_FULL
// or at EOF if pkt_tx_full is still asserted the transition to WAIT_SPACE until
// MAC flags there is space again.
if (pkt_tx_full && out_axis_tlast && out_axis_tvalid && out_axis_tready) begin
full_state <= WAIT_SPACE;
pause_tx <= 1;
end else if (pkt_tx_full) begin
full_state <= DELAY_TO_EOF;
end else full_state <= WAIT_FULL;
WAIT_SPACE:
// Wait for MAC to flag space in internal Tx FIFO again then transition to WAIT_FULL.
if (pkt_tx_full) begin
full_state <= WAIT_SPACE;
pause_tx <= 1;
end else full_state <= WAIT_FULL;
endcase // case(full_state)
end
// Enable Tx to MAC
assign enable_tx = (pkt_count != 0) && ~pause_tx;
endmodule
| 7.23811 |
module axi_cpu (
input rst_n,
input clk,
output avalid,
input aready,
output awe,
output [31:2] aaddr,
output [31:0] adata,
output [3:0] astrb,
input bvalid,
input [31:0] bdata
);
wire io_addr_strobe, io_read_strobe, io_write_strobe;
wire [31:0] io_addr, io_write_data;
wire [3:0] io_byte_enable;
cpu cpu0 (
.Clk (clk),
.Reset(!rst_n),
.IO_Addr_Strobe(io_addr_strobe),
.IO_Read_Strobe(io_read_strobe),
.IO_Write_Strobe(io_write_strobe),
.IO_Address(io_addr),
.IO_Byte_Enable(io_byte_enable),
.IO_Write_Data(io_write_data),
.IO_Read_Data(bdata),
.IO_Ready(bvalid)
);
wire wr = io_addr_strobe && io_write_strobe;
wire rd = io_addr_strobe && io_read_strobe;
reg avalid_hold;
reg awe_hold;
reg [31:2] aaddr_hold;
reg [31:0] adata_hold;
reg [3:0] astrb_hold;
assign avalid = rd || wr || avalid_hold;
assign awe = wr || awe_hold;
assign aaddr = avalid_hold ? aaddr_hold : io_addr[31:2];
assign adata = avalid_hold ? adata_hold : io_write_data;
assign astrb = avalid_hold ? astrb_hold : io_byte_enable;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
avalid_hold <= 1'b0;
end else begin
if (!avalid_hold) begin
awe_hold <= wr;
aaddr_hold <= io_addr[31:2];
adata_hold <= io_write_data;
astrb_hold <= io_byte_enable;
end
avalid_hold <= avalid && !aready;
end
end
endmodule
| 7.388656 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dacfifo_address_buffer #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 16)(
input clk,
input rst,
input wea,
input [DATA_WIDTH-1:0] din,
input rea,
output [DATA_WIDTH-1:0] dout);
reg [ADDRESS_WIDTH-1:0] waddr;
reg [ADDRESS_WIDTH-1:0] raddr;
always @(posedge clk) begin
if (rst == 1'b1) begin
waddr <= 0;
raddr <= 0;
end else begin
waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr;
raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr;
end
end
ad_mem #(
.DATA_WIDTH (DATA_WIDTH),
.ADDRESS_WIDTH (ADDRESS_WIDTH))
i_mem (
.clka (clk),
.wea (wea),
.addra (waddr),
.dina (din),
.clkb (clk),
.reb (1'b1),
.addrb (raddr),
.doutb (dout));
endmodule
| 8.180735 |
module axi_data_fifo_v2_1_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG)
);
endmodule
| 6.855506 |
module axi_data_fifo_v2_1_ndeep_srl #(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH > P_SRLASIZE) ? (2 ** (C_A_WIDTH - P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2 ** C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i = 0; i < P_NUMSRLS; i = i + 1) begin : gen_srls
SRLC32E srl_inst (
.CLK(CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31(d_i[i+1])
);
end
if (C_A_WIDTH > P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #(
.C_RATIO (2 ** (C_A_WIDTH - P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH - P_SRLASIZE),
.C_DATAOUT_WIDTH(1),
.C_ONEHOT (0)
) srl_q_mux_inst (
.SEL_ONEHOT({2 ** (C_A_WIDTH - P_SRLASIZE) {1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
| 6.855506 |
module axi_data_fifo_v2_1_21_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_21_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG)
);
endmodule
| 6.855506 |
module axi_data_fifo_v2_1_21_ndeep_srl #(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH > P_SRLASIZE) ? (2 ** (C_A_WIDTH - P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2 ** C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i = 0; i < P_NUMSRLS; i = i + 1) begin : gen_srls
SRLC32E srl_inst (
.CLK(CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31(d_i[i+1])
);
end
if (C_A_WIDTH > P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_0_nto1_mux #(
.C_RATIO (2 ** (C_A_WIDTH - P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH - P_SRLASIZE),
.C_DATAOUT_WIDTH(1),
.C_ONEHOT (0)
) srl_q_mux_inst (
.SEL_ONEHOT({2 ** (C_A_WIDTH - P_SRLASIZE) {1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
| 6.855506 |
module axi_debug (
input reset,
input clk_sys,
output reg bridge_m0_waitrequest,
output wire [31:0] bridge_m0_readdata,
output reg bridge_m0_readdatavalid,
input wire [ 6:0] bridge_m0_burstcount,
input wire [31:0] bridge_m0_writedata,
input wire [19:0] bridge_m0_address,
input wire bridge_m0_write,
input wire bridge_m0_read,
input wire bridge_m0_byteenable,
output wire bridge_m0_clk,
output reg cpu_clken_dbg,
input fx68k_as_n_dbg,
input [31:0] reg0,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] reg3,
input [31:0] reg4,
input [31:0] reg5,
input [31:0] reg6,
input [31:0] reg7
);
assign bridge_m0_clk = clk_sys; // Core clock.
assign bridge_m0_readdata = (axi_addr==20'h00000) ? reg0 :
(axi_addr==20'h00004) ? reg1 :
(axi_addr==20'h00008) ? reg2 :
(axi_addr==20'h0000C) ? reg3 :
(axi_addr==20'h00010) ? reg4 :
(axi_addr==20'h00014) ? reg5 :
(axi_addr==20'h00018) ? reg6 :
(axi_addr==20'h0001C) ? reg7 :
32'hDEADBEEF;
//assign bridge_m0_readdatavalid = bridge_m0_read;
(*noprune*) reg [3:0] axi_state;
(*noprune*) reg [31:0] axi_cmd;
(*noprune*) reg [19:0] axi_addr;
reg fx68k_as_n_dbg_1;
always @(posedge clk_sys or posedge reset)
if (reset) begin
axi_state <= 4'd0;
cpu_clken_dbg <= 1'b1;
bridge_m0_waitrequest <= 1'b0;
bridge_m0_readdatavalid <= 1'b0;
end else begin
fx68k_as_n_dbg_1 <= fx68k_as_n_dbg;
bridge_m0_readdatavalid <= 1'b0;
case (axi_state)
0: begin
bridge_m0_waitrequest <= 1'b0; // Ready to accept AXI read/write.
if (bridge_m0_read) begin
bridge_m0_waitrequest <= 1'b1;
axi_addr <= bridge_m0_address;
axi_state <= axi_state + 4'd1;
end
if (bridge_m0_write) begin
bridge_m0_waitrequest <= 1'b1;
axi_cmd <= bridge_m0_writedata;
axi_state <= 4'd5;
end
end
// Read...
1: begin
bridge_m0_readdatavalid <= 1'b1;
axi_state <= axi_state + 4'd1;
end
2: begin
bridge_m0_readdatavalid <= 1'b1;
axi_state <= axi_state + 4'd1;
end
3: begin
bridge_m0_readdatavalid <= 1'b1;
axi_state <= axi_state + 4'd1;
end
4: begin
bridge_m0_readdatavalid <= 1'b1;
bridge_m0_waitrequest <= 1'b0;
axi_state <= 4'd0;
end
// Write...
5: begin
case (axi_cmd[31:24])
8'h00: begin
if (!fx68k_as_n_dbg_1 && fx68k_as_n_dbg) begin // Wait for the current CPU cycle to complete.
cpu_clken_dbg <= 1'b0; // Stop the CPU clock.
bridge_m0_waitrequest <= 1'b0;
axi_state <= 4'd0;
end
end
8'h01: begin
cpu_clken_dbg <= 1'b1; // Start the CPU clock.
bridge_m0_waitrequest <= 1'b0;
axi_state <= 4'd0;
end
8'h02: begin // Single-step the CPU.
cpu_clken_dbg <= 1'b1;
if (!fx68k_as_n_dbg_1 && fx68k_as_n_dbg) begin // Wait for the CPU cycle to complete.
cpu_clken_dbg <= 1'b0; // Stop the CPU clock.
bridge_m0_waitrequest <= 1'b0;
axi_state <= 4'd0;
end
end
endcase
end
endcase
end
endmodule
| 6.93872 |
module axi_decoder (
input [`AXI_ADDR_WIDTH - 1 : 0] addr,
output reg [2:0] slave_no
);
/*
//---------------------------------------------------------------------//
Block Name Address Range
Reserved for FLASH 0x0000_0000 ~ 0x3FFF_FFFF
KPLIC 0x4000_0000 ~ 0x43FF_FFFF
MTIMER 0x4400_0000 ~ 0x4FFF_FFFF
Reserved 0x5000_0000 ~ 0x6FFF_FFFF
APB 0x7000_0000 ~ 0x7FFF_FFFF
Reserved 0x8000_0000 ~ 0xFFFF_FFFF
//---------------------------------------------------------------------//
*/
wire [3:0] nibble_0 = addr[3:0];
wire [3:0] nibble_1 = addr[7:4];
wire [3:0] nibble_2 = addr[11:8];
wire [3:0] nibble_3 = addr[15:12];
wire [3:0] nibble_4 = addr[19:16];
wire [3:0] nibble_5 = addr[23:20];
wire [3:0] nibble_6 = addr[27:24];
wire [3:0] nibble_7 = addr[31:28];
wire SEL_S0 = ((nibble_7 < 4'h4));
wire SEL_S1 = ((nibble_7 == 4'h4) && (nibble_6 < 4'h4));
wire SEL_S2 = ((nibble_7 == 4'h4) && (nibble_6 >= 4'h4));
wire SEL_S3 = ((nibble_7 == 4'h5) || (nibble_7 == 4'h6));
wire SEL_S4 = (nibble_7 == 4'h7);
wire SEL_S5 = ((nibble_7 >= 4'h8));
always @* begin
if (SEL_S0) slave_no = 3'h0;
else if (SEL_S1) slave_no = 3'h1;
else if (SEL_S2) slave_no = 3'h2;
else if (SEL_S3) slave_no = 3'h3;
else if (SEL_S4) slave_no = 3'h4;
else if (SEL_S5) slave_no = 3'h5;
end
endmodule
| 6.928726 |
module AXI_DELAY #(
parameter REFCLK_FREQUENCY = 300,
parameter NATIVE_ADDR_WDITH = 1,
parameter NATIVE_DATA_WIDTH = 9,
parameter S_AXI_ADDR_WIDTH = 3,
parameter S_AXI_DATA_WIDTH = 32,
parameter MODE = "TIME"
) (
input REFCLK,
input REFCLK_RESET_N,
input S_AXI_DELAY_aclk,
input S_AXI_DELAY_aresetn,
input [ S_AXI_ADDR_WIDTH-1:0] S_AXI_DELAY_araddr,
output S_AXI_DELAY_arready,
input S_AXI_DELAY_arvalid,
input [ 2:0] S_AXI_DELAY_arprot,
input [ S_AXI_ADDR_WIDTH-1:0] S_AXI_DELAY_awaddr,
output S_AXI_DELAY_awready,
input S_AXI_DELAY_awvalid,
input [ 2:0] S_AXI_DELAY_awprot,
output [ 1:0] S_AXI_DELAY_bresp,
input S_AXI_DELAY_bready,
output S_AXI_DELAY_bvalid,
output [ S_AXI_DATA_WIDTH-1:0] S_AXI_DELAY_rdata,
input S_AXI_DELAY_rready,
output S_AXI_DELAY_rvalid,
output [ 1:0] S_AXI_DELAY_rresp,
input [ S_AXI_DATA_WIDTH-1:0] S_AXI_DELAY_wdata,
output S_AXI_DELAY_wready,
input S_AXI_DELAY_wvalid,
input [S_AXI_DATA_WIDTH/8-1:0] S_AXI_DELAY_wstrb,
input signal_in,
output signal_out,
output IDELAYCTRL_RST
);
wire NATIVE_CLK;
wire NATIVE_EN;
wire NATIVE_WR;
wire [NATIVE_ADDR_WDITH-1:0] NATIVE_ADDR;
wire [NATIVE_DATA_WIDTH-1:0] NATIVE_DATA_IN;
wire [NATIVE_DATA_WIDTH-1:0] NATIVE_DATA_OUT;
wire NATIVE_READY;
AXI_Core #(
.NATIVE_ADDR_WDITH(NATIVE_ADDR_WDITH),
.NATIVE_DATA_WIDTH(NATIVE_DATA_WIDTH),
.S_AXI_ADDR_WIDTH (S_AXI_ADDR_WIDTH),
.S_AXI_DATA_WIDTH (S_AXI_DATA_WIDTH)
) inst_AXI_Core (
.S_AXI_aclk (S_AXI_DELAY_aclk),
.S_AXI_aresetn (S_AXI_DELAY_aresetn),
.S_AXI_araddr (S_AXI_DELAY_araddr),
.S_AXI_arready (S_AXI_DELAY_arready),
.S_AXI_arvalid (S_AXI_DELAY_arvalid),
.S_AXI_arprot (S_AXI_DELAY_arprot),
.S_AXI_awaddr (S_AXI_DELAY_awaddr),
.S_AXI_awready (S_AXI_DELAY_awready),
.S_AXI_awvalid (S_AXI_DELAY_awvalid),
.S_AXI_awprot (S_AXI_DELAY_awprot),
.S_AXI_bresp (S_AXI_DELAY_bresp),
.S_AXI_bready (S_AXI_DELAY_bready),
.S_AXI_bvalid (S_AXI_DELAY_bvalid),
.S_AXI_rdata (S_AXI_DELAY_rdata),
.S_AXI_rready (S_AXI_DELAY_rready),
.S_AXI_rvalid (S_AXI_DELAY_rvalid),
.S_AXI_rresp (S_AXI_DELAY_rresp),
.S_AXI_wdata (S_AXI_DELAY_wdata),
.S_AXI_wready (S_AXI_DELAY_wready),
.S_AXI_wvalid (S_AXI_DELAY_wvalid),
.S_AXI_wstrb (S_AXI_DELAY_wstrb),
.NATIVE_CLK (NATIVE_CLK),
.NATIVE_EN (NATIVE_EN),
.NATIVE_WR (NATIVE_WR),
.NATIVE_ADDR (NATIVE_ADDR),
.NATIVE_DATA_IN (NATIVE_DATA_IN),
.NATIVE_DATA_OUT(NATIVE_DATA_OUT),
.NATIVE_READY (NATIVE_READY)
);
IMP_Core #(
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.NATIVE_ADDR_WDITH(NATIVE_ADDR_WDITH),
.NATIVE_DATA_WIDTH(NATIVE_DATA_WIDTH),
.MODE(MODE)
) inst_IMP_Core (
.REFCLK (REFCLK),
.NATIVE_CLK (NATIVE_CLK),
.NATIVE_EN (NATIVE_EN),
.NATIVE_WR (NATIVE_WR),
.NATIVE_ADDR (NATIVE_ADDR),
.NATIVE_DATA_IN (NATIVE_DATA_IN),
.NATIVE_DATA_OUT(NATIVE_DATA_OUT),
.NATIVE_READY (NATIVE_READY),
.rst_n (REFCLK_RESET_N),
.signal_in (signal_in),
.signal_out (signal_out),
.IDELAYCTRL_RST (IDELAYCTRL_RST)
);
endmodule
| 6.829539 |
module axi_delay_fifo #(
parameter DELAY = 4, // What to do when errors occur -- wait for next packet or next burst
parameter WIDTH = 32
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] i_tdata_d [0:DELAY];
wire [ DELAY:0] i_tvalid_d;
wire [ DELAY:0] i_tready_d;
genvar i;
generate
for (i = 1; i <= DELAY; i = i + 1) begin : loop
axi_fifo_flop2 #(
.WIDTH(WIDTH)
) axi_fifo_flop2 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(i_tdata_d[i-1]),
.i_tvalid(i_tvalid_d[i-1]),
.i_tready(i_tready_d[i-1]),
.o_tdata(i_tdata_d[i]),
.o_tvalid(i_tvalid_d[i]),
.o_tready(i_tready_d[i]),
.space(),
.occupied()
);
end
endgenerate
assign i_tdata_d[0] = i_tdata;
assign i_tvalid_d[0] = i_tvalid;
assign i_tready = i_tready_d[0];
assign i_tready_d[DELAY] = o_tready;
assign o_tdata = i_tdata_d[DELAY];
assign o_tvalid = i_tvalid_d[DELAY];
endmodule
| 6.992055 |
module axi_demo_tb ();
reg clk, reset;
wire done;
wire error;
localparam NUM_OF_RUNNING_CLOCK_CYCLES = 300;
axi_demo axi (
.clk (clk),
.reset(reset),
.done (done),
.error(error)
);
initial begin
$dumpfile("axi_demo_tb.vcd");
$dumpvars(0, axi_demo_tb);
clk = 0;
reset = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset = 1;
@(posedge clk);
@(posedge clk);
reset = 0;
repeat (NUM_OF_RUNNING_CLOCK_CYCLES) @(posedge clk);
$finish;
end
localparam clk_period = 5;
always @(*) #clk_period clk <= !clk;
endmodule
| 7.944191 |
module axi_demux4 #(
parameter ACTIVE_CHAN = 4'b1111, // ACTIVE_CHAN is a map of connected outputs
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
output [WIDTH-1:0] header,
input [1:0] dest,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0_tlast,
output o0_tvalid,
input o0_tready,
output [WIDTH-1:0] o1_tdata,
output o1_tlast,
output o1_tvalid,
input o1_tready,
output [WIDTH-1:0] o2_tdata,
output o2_tlast,
output o2_tvalid,
input o2_tready,
output [WIDTH-1:0] o3_tdata,
output o3_tlast,
output o3_tvalid,
input o3_tready
);
wire [WIDTH-1:0] i_tdata_int;
wire i_tlast_int, i_tvalid_int, i_tready_int;
generate
if (BUFFER == 0) begin
assign i_tdata_int = i_tdata;
assign i_tlast_int = i_tlast;
assign i_tvalid_int = i_tvalid;
assign i_tready = i_tready_int;
end else
axi_fifo_short #(
.WIDTH(WIDTH + 1)
) axi_fifo_short (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({i_tlast, i_tdata}),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata({i_tlast_int, i_tdata_int}),
.o_tvalid(i_tvalid_int),
.o_tready(i_tready_int),
.space(),
.occupied()
);
endgenerate
reg [3:0] dm_state;
localparam DM_IDLE = 4'b0000;
localparam DM_0 = 4'b0001;
localparam DM_1 = 4'b0010;
localparam DM_2 = 4'b0100;
localparam DM_3 = 4'b1000;
assign header = i_tdata_int;
always @(posedge clk)
if (reset | clear) dm_state <= DM_IDLE;
else
case (dm_state)
DM_IDLE:
if (i_tvalid_int)
case (dest)
2'b00: dm_state <= DM_0;
2'b01: dm_state <= DM_1;
2'b10: dm_state <= DM_2;
2'b11: dm_state <= DM_3;
endcase // case (i_tdata[1:0])
DM_0, DM_1, DM_2, DM_3: if (i_tvalid_int & i_tready_int & i_tlast_int) dm_state <= DM_IDLE;
default: dm_state <= DM_IDLE;
endcase // case (dm_state)
assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
assign i_tready_int = |(dm_state & ({o3_tready, o2_tready, o1_tready, o0_tready} | ~ACTIVE_CHAN));
assign {o0_tlast, o0_tdata} = {i_tlast_int, i_tdata_int};
assign {o1_tlast, o1_tdata} = {i_tlast_int, i_tdata_int};
assign {o2_tlast, o2_tdata} = {i_tlast_int, i_tdata_int};
assign {o3_tlast, o3_tdata} = {i_tlast_int, i_tdata_int};
endmodule
| 8.417115 |
module axi_demux8 #(
parameter ACTIVE_CHAN = 8'b11111111, // ACTIVE_CHAN is a map of connected outputs
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
output [WIDTH-1:0] header,
input [2:0] dest,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0_tlast,
output o0_tvalid,
input o0_tready,
output [WIDTH-1:0] o1_tdata,
output o1_tlast,
output o1_tvalid,
input o1_tready,
output [WIDTH-1:0] o2_tdata,
output o2_tlast,
output o2_tvalid,
input o2_tready,
output [WIDTH-1:0] o3_tdata,
output o3_tlast,
output o3_tvalid,
input o3_tready,
output [WIDTH-1:0] o4_tdata,
output o4_tlast,
output o4_tvalid,
input o4_tready,
output [WIDTH-1:0] o5_tdata,
output o5_tlast,
output o5_tvalid,
input o5_tready,
output [WIDTH-1:0] o6_tdata,
output o6_tlast,
output o6_tvalid,
input o6_tready,
output [WIDTH-1:0] o7_tdata,
output o7_tlast,
output o7_tvalid,
input o7_tready
);
wire [WIDTH-1:0] i_tdata_int0, i_tdata_int1;
wire i_tlast_int0, i_tlast_int1;
wire i_tvalid_int0, i_tvalid_int1;
wire i_tready_int0, i_tready_int1;
axi_demux4 #(
.ACTIVE_CHAN({2'b00, (|(ACTIVE_CHAN[7:4])), (|(ACTIVE_CHAN[3:0]))}),
.WIDTH(WIDTH),
.BUFFER(BUFFER)
) demux2 (
.clk(clk),
.reset(reset),
.clear(clear),
.header(header),
.dest({1'b0, dest[2]}),
.i_tdata(i_tdata),
.i_tlast(i_tlast),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o0_tdata(i_tdata_int0),
.o0_tlast(i_tlast_int0),
.o0_tvalid(i_tvalid_int0),
.o0_tready(i_tready_int0),
.o1_tdata(i_tdata_int1),
.o1_tlast(i_tlast_int1),
.o1_tvalid(i_tvalid_int1),
.o1_tready(i_tready_int1),
.o2_tdata(),
.o2_tlast(),
.o2_tvalid(),
.o2_tready(1'b0),
.o3_tdata(),
.o3_tlast(),
.o3_tvalid(),
.o3_tready(1'b0)
);
axi_demux4 #(
.ACTIVE_CHAN(ACTIVE_CHAN[3:0]),
.WIDTH(WIDTH),
.BUFFER(0)
) demux4_int0 (
.clk(clk),
.reset(reset),
.clear(clear),
.header(),
.dest(dest[1:0]),
.i_tdata(i_tdata_int0),
.i_tlast(i_tlast_int0),
.i_tvalid(i_tvalid_int0),
.i_tready(i_tready_int0),
.o0_tdata(o0_tdata),
.o0_tlast(o0_tlast),
.o0_tvalid(o0_tvalid),
.o0_tready(o0_tready),
.o1_tdata(o1_tdata),
.o1_tlast(o1_tlast),
.o1_tvalid(o1_tvalid),
.o1_tready(o1_tready),
.o2_tdata(o2_tdata),
.o2_tlast(o2_tlast),
.o2_tvalid(o2_tvalid),
.o2_tready(o2_tready),
.o3_tdata(o3_tdata),
.o3_tlast(o3_tlast),
.o3_tvalid(o3_tvalid),
.o3_tready(o3_tready)
);
axi_demux4 #(
.ACTIVE_CHAN(ACTIVE_CHAN[7:4]),
.WIDTH(WIDTH),
.BUFFER(0)
) demux4_int1 (
.clk(clk),
.reset(reset),
.clear(clear),
.header(),
.dest(dest[1:0]),
.i_tdata(i_tdata_int1),
.i_tlast(i_tlast_int1),
.i_tvalid(i_tvalid_int1),
.i_tready(i_tready_int1),
.o0_tdata(o4_tdata),
.o0_tlast(o4_tlast),
.o0_tvalid(o4_tvalid),
.o0_tready(o4_tready),
.o1_tdata(o5_tdata),
.o1_tlast(o5_tlast),
.o1_tvalid(o5_tvalid),
.o1_tready(o5_tready),
.o2_tdata(o6_tdata),
.o2_tlast(o6_tlast),
.o2_tvalid(o6_tvalid),
.o2_tready(o6_tready),
.o3_tdata(o7_tdata),
.o3_tlast(o7_tlast),
.o3_tvalid(o7_tvalid),
.o3_tready(o7_tready)
);
endmodule
| 8.216562 |
module axi_dma_r (
// system inputs
input clk,
input rst,
// Databus interface
output reg ready,
input valid,
input [`DDR_ADDR_W-1:0] addr,
output [ `MIG_BUS_W-1:0] rdata,
// DMA configuration
input [`AXI_LEN_W-1:0] len,
// Master Interface Read Address
output wire [ `AXI_ID_W-1:0] m_axi_arid,
output wire [ `DDR_ADDR_W-1:0] m_axi_araddr,
output wire [ `AXI_LEN_W-1:0] m_axi_arlen,
output wire [ `AXI_SIZE_W-1:0] m_axi_arsize,
output wire [`AXI_BURST_W-1:0] m_axi_arburst,
output wire [ `AXI_LOCK_W-1:0] m_axi_arlock,
output wire [`AXI_CACHE_W-1:0] m_axi_arcache,
output wire [ `AXI_PROT_W-1:0] m_axi_arprot,
output wire [ `AXI_QOS_W-1:0] m_axi_arqos,
output reg m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data
// input wire [`AXI_ID_W-1:0] m_axi_rid,
input wire [ `MIG_BUS_W-1:0] m_axi_rdata,
input wire [`AXI_RESP_W-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output reg m_axi_rready
);
// counter, state and error regs
reg [`AXI_LEN_W-1:0] counter_int, counter_int_nxt;
reg [`R_STATES_W-1:0] state, state_nxt;
reg error, error_nxt;
// register len and addr valid
reg [`AXI_LEN_W-1:0] len_r;
reg m_axi_arvalid_int;
// Address read constants
assign m_axi_arid = `AXI_ID_W'b0;
assign m_axi_araddr = addr;
assign m_axi_arlen = len_r; //number of trasfers per burst
assign m_axi_arsize = $clog2(`MIG_BUS_W / 8); //INCR interval
assign m_axi_arburst = `AXI_BURST_W'b01; //INCR
assign m_axi_arlock = `AXI_LOCK_W'b0;
assign m_axi_arcache = `AXI_CACHE_W'h2;
assign m_axi_arprot = `AXI_PROT_W'b010;
assign m_axi_arqos = `AXI_QOS_W'h0;
// Data read constant
assign rdata = m_axi_rdata;
// Counter, error, state and addr valid registers
always @(posedge clk, posedge rst)
if (rst) begin
state <= `R_ADDR_HS;
counter_int <= {`AXI_LEN_W{1'b0}};
error <= 1'b0;
m_axi_arvalid <= 1'b0;
end else begin
state <= state_nxt;
counter_int <= counter_int_nxt;
error <= error_nxt;
m_axi_arvalid <= m_axi_arvalid_int;
end
// register len
always @(posedge clk, posedge rst)
if (rst) len_r <= {`AXI_LEN_W{1'b0}};
else if (state == `R_ADDR_HS) len_r <= len;
// State machine
always @* begin
state_nxt = state;
error_nxt = error;
counter_int_nxt = counter_int;
ready = 1'b0;
m_axi_arvalid_int = 1'b0;
m_axi_rready = 1'b0;
case (state)
//addr handshake
`R_ADDR_HS: begin
counter_int_nxt <= {`AXI_LEN_W{1'b0}};
if (valid) begin
if (m_axi_arready == 1'b1) begin
state_nxt = `R_DATA;
end
m_axi_arvalid_int = 1'b1;
end
end
//data read
`R_DATA: begin
m_axi_rready = 1'b1;
if (m_axi_rvalid == 1'b1) begin
if (counter_int == len_r) begin
if (m_axi_rlast == 1'b1) error_nxt = 1'b0;
else error_nxt = 1'b1;
state_nxt = `R_ADDR_HS;
end
ready = 1'b1;
counter_int_nxt = counter_int + 1'b1;
end
end
endcase
end
endmodule
| 7.098171 |
module axi_drop_packet #(
parameter WIDTH = 32,
parameter MAX_PKT_SIZE = 1024
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
input i_tlast,
input i_terror,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
output o_tlast,
input o_tready
);
generate
// Packet size of 1 is efficiently implemented as a pass through with i_terror masking i_tvalid.
if (MAX_PKT_SIZE == 1) begin
assign o_tdata = i_tdata;
assign o_tlast = i_tlast;
assign o_tvalid = i_tvalid & ~i_terror;
assign i_tready = o_tready;
// All other packet sizes
end else begin
reg [WIDTH-1:0] int_tdata;
reg int_tlast, int_tvalid;
wire int_tready;
reg [$clog2(MAX_PKT_SIZE)-1:0] wr_addr, prev_wr_addr, rd_addr;
reg [$clog2(MAX_PKT_SIZE):0] in_pkt_cnt, out_pkt_cnt;
reg full = 1'b0, empty = 1'b1;
reg [WIDTH:0] mem[2**($clog2(MAX_PKT_SIZE))-1:0];
// Initialize RAM to all zeros
integer i;
initial begin
for (i = 0; i < (1 << $clog2(MAX_PKT_SIZE)); i = i + 1) begin
mem[i] = 'd0;
end
end
assign i_tready = ~full;
wire write = i_tvalid & i_tready;
wire read = ~empty & ~hold & int_tready;
wire almost_full = (wr_addr == rd_addr - 1'b1);
wire almost_empty = (wr_addr == rd_addr + 1'b1);
// Write logic
always @(posedge clk) begin
if (write) begin
mem[wr_addr] <= {i_tlast, i_tdata};
wr_addr <= wr_addr + 1'b1;
end
if (almost_full) begin
if (write & ~read) begin
full <= 1'b1;
end
end else begin
if (~write & read) begin
full <= 1'b0;
end
end
// Rewind logic
if (write & i_tlast) begin
if (i_terror) begin
wr_addr <= prev_wr_addr;
end else begin
in_pkt_cnt <= in_pkt_cnt + 1'b1;
prev_wr_addr <= wr_addr + 1'b1;
end
end
if (reset | clear) begin
wr_addr <= 0;
prev_wr_addr <= 0;
in_pkt_cnt <= 0;
full <= 1'b0;
end
end
// Read logic
wire hold = (in_pkt_cnt == out_pkt_cnt);
always @(posedge clk) begin
if (int_tready) begin
int_tdata <= mem[rd_addr][WIDTH-1:0];
int_tlast <= mem[rd_addr][WIDTH];
int_tvalid <= ~empty & ~hold;
end
if (read) begin
rd_addr <= rd_addr + 1;
end
if (almost_empty) begin
if (read & ~write) begin
empty <= 1'b1;
end
end else begin
if (~read & write) begin
empty <= 1'b0;
end
end
// Prevent output until we have a full packet
if (int_tvalid & int_tready & int_tlast) begin
out_pkt_cnt <= out_pkt_cnt + 1'b1;
end
if (reset | clear) begin
rd_addr <= 0;
out_pkt_cnt <= 0;
empty <= 1'b1;
int_tvalid <= 1'b0;
end
end
// Output register stage
// Added specifically to prevent Vivado synth from using a slice register instead
// of the block RAM primative's output register.
axi_fifo_flop2 #(
.WIDTH(WIDTH + 1)
) axi_fifo_flop2 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({int_tlast, int_tdata}),
.i_tvalid(int_tvalid),
.i_tready(int_tready),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
end
endgenerate
endmodule
| 7.3235 |
module axi_dummy (
// sys connect
input s_axi_aclk,
input s_axi_areset,
// axi4 lite slave port
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready
);
parameter DEC_ERR = 1'b1;
localparam IDLE = 3'b001;
localparam READ_IN_PROGRESS = 3'b010;
localparam WRITE_IN_PROGRESS = 3'b100;
reg [2:0] state;
always @(posedge s_axi_aclk) begin
if (s_axi_areset) begin
state <= IDLE;
end else
case (state)
IDLE: begin
if (s_axi_arvalid) state <= READ_IN_PROGRESS;
else if (s_axi_awvalid) state <= WRITE_IN_PROGRESS;
end
READ_IN_PROGRESS: begin
if (s_axi_rready) state <= IDLE;
end
WRITE_IN_PROGRESS: begin
if (s_axi_bready) state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
assign s_axi_awready = (state == IDLE);
assign s_axi_wready = (state == WRITE_IN_PROGRESS);
assign s_axi_bvalid = (state == WRITE_IN_PROGRESS);
assign s_axi_arready = (state == IDLE);
assign s_axi_rdata = 32'hdead_ba5e;
assign s_axi_rvalid = (state == READ_IN_PROGRESS);
assign s_axi_rresp = DEC_ERR ? 2'b11 : 2'b00;
assign s_axi_bresp = DEC_ERR ? 2'b11 : 2'b00;
endmodule
| 9.188688 |
module axi_embed_tlast #(
parameter WIDTH = 64,
parameter ADD_CHECKSUM = 0
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
//
output reg [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
localparam PASS = 0;
localparam ZERO = 1;
localparam ONE = 2;
localparam ESCAPE = 3;
localparam IDLE = 0;
localparam LAST = 1;
localparam ESC = 2;
localparam FINISH = 3;
reg [1:0] state, next_state;
reg [ 1:0] select;
wire [31:0] checksum;
generate
if (ADD_CHECKSUM == 1) begin
reg [31:0] checksum_reg;
always @(posedge clk) begin
if (reset | clear) begin
checksum_reg <= 0;
end else if (i_tready && i_tvalid && i_tlast) begin
checksum_reg <= 0;
end else if (i_tready && i_tvalid) begin
checksum_reg <= checksum_reg ^ i_tdata[31:0] ^ i_tdata[63:32];
end
end
assign checksum = checksum_reg;
end else begin
assign checksum = 32'h0;
end
endgenerate
always @(posedge clk)
if (reset | clear) begin
state <= IDLE;
end else begin
if (o_tready) state <= next_state;
end
always @(*) begin
case (state)
IDLE: begin
if (i_tlast && i_tvalid) begin
next_state = LAST;
select = ESCAPE;
end else if ((i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
next_state = ESC;
select = ESCAPE;
end else begin
next_state = IDLE;
select = PASS;
end
end // case: IDLE
LAST: begin
select = ONE;
next_state = FINISH;
end
ESC: begin
select = ZERO;
next_state = FINISH;
end
FINISH: begin
select = PASS;
if (i_tvalid) next_state = IDLE;
else next_state = FINISH;
end
endcase // case(state)
end // always @ (*)
//
// Muxes
//
always @* begin
case (select)
PASS: o_tdata = i_tdata;
ZERO: o_tdata = 0;
ONE: o_tdata = {checksum[31:0],32'h1};
ESCAPE: o_tdata = 64'hDEADBEEFFEEDCAFE;
endcase // case(select)
end
assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
assign i_tready = (select == PASS) ? o_tready : 1'b0;
endmodule
| 7.098611 |
module for Spartan-6 PCIe Block
// The BRAM A port is the write port.
// The BRAM B port is the read port.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_enhanced_pcie_v1_04_a_pcie_bram_s6 #(
parameter DOB_REG = 0, // 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36
) (
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [11:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [11:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 11 :
(WIDTH == 9) ? 10 :
(WIDTH == 18) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
5
);
localparam WRITE_MODE_INT = "NO_CHANGE";
//synthesis translate_off
initial begin
case (WIDTH)
4,9,18,36:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
wire [31:0] di_wire, do_wire;
wire [3:0] dip_wire, dop_wire;
generate
case (WIDTH)
36: begin : width_36
assign di_wire = wdata_i[31:0];
assign dip_wire = wdata_i[35:32];
assign rdata_o = {dop_wire, do_wire};
end
18: begin : width_18
assign di_wire = {16'd0, wdata_i[15:0]};
assign dip_wire = {2'd0, wdata_i[17:16]};
assign rdata_o = {dop_wire[1:0], do_wire[15:0]};
end
9: begin : width_9
assign di_wire = {24'd0, wdata_i[7:0]};
assign dip_wire = {3'd0, wdata_i[8]};
assign rdata_o = {dop_wire[0], do_wire[7:0]};
end
4: begin : width_4
assign di_wire = {28'd0, wdata_i[3:0]};
assign dip_wire = 4'd0;
assign rdata_o = do_wire[3:0];
end
endcase
endgenerate
RAMB16BWER #(
.SIM_DEVICE ("SPARTAN6"),
.DATA_WIDTH_A (WIDTH),
.DATA_WIDTH_B (WIDTH),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.WRITE_MODE_A (WRITE_MODE_INT),
.WRITE_MODE_B (WRITE_MODE_INT)
) ramb16 (
.CLKA (user_clk_i),
.RSTA (reset_i),
.DOA (),
.DOPA (),
.ADDRA ({waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DIA (di_wire),
.DIPA (dip_wire),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.REGCEA (1'b0),
.CLKB (user_clk_i),
.RSTB (reset_i),
.WEB (4'd0),
.DIB (32'd0),
.DIPB (4'd0),
.ADDRB ({raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DOB (do_wire),
.DOPB (dop_wire),
.ENB (ren_i),
.REGCEB (rce_i)
);
endmodule
| 7.510734 |
module for Spartan-6 PCIe Block
//
// Given the selected core configuration, calculate the number of
// BRAMs and pipeline stages and instantiate the BRAMS.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_enhanced_pcie_v1_04_a_pcie_bram_top_s6 #(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 20,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [11:0] mim_tx_waddr,
input [35:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [11:0] mim_tx_raddr,
output [35:0] mim_tx_rdata,
input mim_rx_wen,
input [11:0] mim_rx_waddr,
input [35:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [11:0] mim_rx_raddr,
output [35:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
512 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 2048) ? 1 :
(BYTES_TX <= 4096) ? 2 :
(BYTES_TX <= 8192) ? 4 :
9
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
9
);
axi_enhanced_pcie_v1_04_a_pcie_brams_s6 #(
.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
axi_enhanced_pcie_v1_04_a_pcie_brams_s6 #(
.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule
| 7.510734 |
module axi_extract_tlast #(
parameter WIDTH = 64,
parameter VALIDATE_CHECKSUM = 0
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output reg i_tready,
//
output [WIDTH-1:0] o_tdata,
output reg o_tlast,
output reg o_tvalid,
input o_tready,
//
output reg checksum_error
);
reg [1:0] state, next_state;
localparam IDLE = 0;
localparam EXTRACT1 = 1;
localparam EXTRACT2 = 2;
localparam EXTRACT3 = 3;
assign o_tdata = i_tdata;
reg checksum_error_pre;
reg [31:0] checksum, old_checksum;
always @(posedge clk)
if (reset | clear) begin
checksum <= 0;
old_checksum <= 0;
end else if (VALIDATE_CHECKSUM && o_tready && i_tvalid && o_tlast) begin
checksum <= 0;
old_checksum <= 0;
end else if (VALIDATE_CHECKSUM && i_tready && i_tvalid && (state == IDLE)) begin
checksum <= checksum ^ i_tdata[31:0] ^ i_tdata[63:32];
old_checksum <= checksum;
end
always @(posedge clk) checksum_error <= checksum_error_pre;
always @(posedge clk)
if (reset | clear) begin
state <= IDLE;
end else begin
state <= next_state;
end
always @(*) begin
checksum_error_pre = 0;
case (state)
//
// Search for Escape sequence "0xDEADBEEFFEEDCAFE"
// If ESC found don't pass data downstream but transition to next state.
// else pass data downstream.
//
IDLE: begin
o_tlast = 1'b0;
if ((i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
next_state = EXTRACT1;
o_tvalid = 1'b0;
i_tready = 1'b1;
end else begin
next_state = IDLE;
o_tvalid = i_tvalid;
i_tready = o_tready;
end // else: !if((i_tdata == 'hDEADBEEFFEEDCAFE) && i_tvalid)
end // case: IDLE
//
// Look at next data. If it's a 0x1 then o_tlast should be asserted with next data word.
// if it's 0x0 then it signals emulation of the Escape code in the original data stream
// and we should just pass the next data word through unchanged with no o_tlast indication.
//
EXTRACT1: begin
o_tvalid = 1'b0;
i_tready = 1'b1;
o_tlast = 1'b0;
if (i_tvalid) begin
if (i_tdata[31:0] == 'h1) begin
if (VALIDATE_CHECKSUM && (old_checksum != i_tdata[63:32])) checksum_error_pre = 1'b1;
next_state = EXTRACT2;
end else begin
// We assume emulation and don't look for illegal codes.
next_state = EXTRACT3;
end // else: !if(i_tdata == 'h1)
end else begin // if (i_tvalid)
next_state = EXTRACT1;
end // else: !if(i_tvalid)
end // case: EXTRACT1
//
// Assert o_tlast with data word.
//
EXTRACT2: begin
o_tvalid = i_tvalid;
i_tready = o_tready;
o_tlast = 1'b1;
if (i_tvalid & o_tready) next_state = IDLE;
else next_state = EXTRACT2;
end
//
// Emulation, don't assert o_tlast with dataword.
//
EXTRACT3: begin
o_tvalid = i_tvalid;
i_tready = o_tready;
o_tlast = 1'b0;
if (i_tvalid & o_tready) next_state = IDLE;
else next_state = EXTRACT2;
end
endcase // case(state)
end
endmodule
| 8.352477 |
module extracts the TLAST and TKEEP values that were embedded by the
// axi_embed_tlast_tkeep module. See axi_embed_tlast_tkeep for a description
// of how the data is encoded.
//
// Here are some extraction examples for DATA_W = 64.
//
// 0x1234567887654321 becomes
// 0x1234567887654321 (no changes)
//
// 0xDEADBEEF00000001 0x1234567887654321 becomes
// 0x1234567887654321 with TLAST=1 and TKEEP=0
//
// 0xDEADBEEF00000005 0x1234567887654321 becomes
// 0x1234567887654321 with TLAST=1 and TKEEP=2
//
// 0xDEADBEEF00000000 0xDEADBEEFFEEDCAFE
// 0xDEADBEEFFEEDCAFE without TLAST=0 and TKEEP=0 becomes
//
// 0xDEADBEEF00000002 0xDEADBEEFFEEDCAFE
// 0xDEADBEEFFEEDCAFE with TLAST=0 and TKEEP=1 becomes
//
module axi_extract_tlast_tkeep #(
parameter DATA_W = 64,
parameter KEEP_W = DATA_W /8
) (
input clk,
input rst,
// Input AXI-Stream
input [DATA_W-1:0] i_tdata,
input i_tvalid,
output reg i_tready,
// Output AXI-Stream
output reg [DATA_W-1:0] o_tdata,
output reg [KEEP_W-1:0] o_tkeep,
output reg o_tlast,
output reg o_tvalid,
input o_tready
);
localparam ESC_WORD_W = 32;
localparam [ESC_WORD_W-1:0] ESC_WORD = 'hDEADBEEF;
//---------------------------------------------------------------------------
// TKEEP and TLAST Holding Register
//---------------------------------------------------------------------------
reg save_flags;
reg tlast_saved;
reg [KEEP_W-1:0] tkeep_saved;
always @(posedge clk) begin
if (save_flags) begin
// Save the TLAST and TKEEP values embedded in the escape word
tlast_saved <= i_tdata[0];
tkeep_saved <= i_tdata[1 +: KEEP_W];
end
end
//--------------------------------------------------------------------------
// State Machine
//--------------------------------------------------------------------------
localparam ST_IDLE = 0;
localparam ST_DATA = 1;
reg [0:0] state = ST_IDLE;
reg [0:0] next_state;
always @(posedge clk) begin
if (rst) begin
state <= ST_IDLE;
end else begin
state <= next_state;
end
end
always @(*) begin
// Default assignments (pass through)
o_tdata = i_tdata;
o_tlast = 1'b0;
o_tkeep = {KEEP_W{1'b1}};
save_flags = 1'b0;
next_state = state;
o_tvalid = i_tvalid;
i_tready = o_tready;
case(state)
//
// Search for escape code. If found don't pass data downstream but
// transition to next state. Otherwise, pass data downstream.
//
ST_IDLE: begin
if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
save_flags = 1'b1;
next_state = ST_DATA;
o_tvalid = 1'b0;
i_tready = 1'b1;
end
end
//
// Output data word with the saved TLAST and TKEEP values
//
ST_DATA: begin
o_tlast = tlast_saved;
o_tkeep = tkeep_saved;
if (i_tvalid & o_tready) begin
next_state = ST_IDLE;
end
end
endcase
end
endmodule
| 7.368047 |
module axi_FanInPrimitive_Req #(
parameter AUX_WIDTH = 32,
parameter ID_WIDTH = 16
) (
RR_FLAG,
data_AUX0_i,
data_AUX1_i,
data_req0_i,
data_req1_i,
data_ID0_i,
data_ID1_i,
data_gnt0_o,
data_gnt1_o,
data_AUX_o,
data_req_o,
data_ID_o,
data_gnt_i,
lock_EXCLUSIVE,
SEL_EXCLUSIVE
);
//parameter AUX_WIDTH = 32;
//parameter ID_WIDTH = 16;
input wire RR_FLAG;
input wire [AUX_WIDTH - 1:0] data_AUX0_i;
input wire [AUX_WIDTH - 1:0] data_AUX1_i;
input wire data_req0_i;
input wire data_req1_i;
input wire [ID_WIDTH - 1:0] data_ID0_i;
input wire [ID_WIDTH - 1:0] data_ID1_i;
output reg data_gnt0_o;
output reg data_gnt1_o;
output reg [AUX_WIDTH - 1:0] data_AUX_o;
output reg data_req_o;
output reg [ID_WIDTH - 1:0] data_ID_o;
input wire data_gnt_i;
input wire lock_EXCLUSIVE;
input wire SEL_EXCLUSIVE;
reg SEL;
always @(*)
if (lock_EXCLUSIVE) begin
data_req_o = (SEL_EXCLUSIVE ? data_req1_i : data_req0_i);
data_gnt0_o = (SEL_EXCLUSIVE ? 1'b0 : data_gnt_i);
data_gnt1_o = (SEL_EXCLUSIVE ? data_gnt_i : 1'b0);
SEL = SEL_EXCLUSIVE;
end else begin
data_req_o = data_req0_i | data_req1_i;
data_gnt0_o = ((data_req0_i & ~data_req1_i) | (data_req0_i & ~RR_FLAG)) & data_gnt_i;
data_gnt1_o = ((~data_req0_i & data_req1_i) | (data_req1_i & RR_FLAG)) & data_gnt_i;
SEL = ~data_req0_i | (RR_FLAG & data_req1_i);
end
always @(*) begin : FanIn_MUX2
case (SEL)
1'b0: begin
data_AUX_o = data_AUX0_i;
data_ID_o = data_ID0_i;
end
1'b1: begin
data_AUX_o = data_AUX1_i;
data_ID_o = data_ID1_i;
end
endcase
end
endmodule
| 8.239046 |
module axi_fast_fifo #(
parameter WIDTH = 64
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output reg i_tready,
//
output [WIDTH-1:0] o_tdata,
output reg o_tvalid,
input o_tready
);
reg [WIDTH-1:0] data_reg1, data_reg2;
reg [1:0] state;
localparam EMPTY = 0;
localparam HALF = 1;
localparam FULL = 2;
always @(posedge clk)
if (reset | clear) begin
state <= EMPTY;
data_reg1 <= 0;
data_reg2 <= 0;
o_tvalid <= 1'b0;
i_tready <= 1'b0;
end else begin
case (state)
// Nothing in either register.
// Upstream can always push data to us.
// Downstream has nothing to take from us.
EMPTY: begin
if (i_tvalid) begin
data_reg1 <= i_tdata;
state <= HALF;
i_tready <= 1'b1;
o_tvalid <= 1'b1;
end else begin
state <= EMPTY;
i_tready <= 1'b1;
o_tvalid <= 1'b0;
end
end
// First Register Full.
// Upstream can always push data to us.
// Downstream can always read from us.
HALF: begin
if (i_tvalid && o_tready) begin
data_reg1 <= i_tdata;
state <= HALF;
i_tready <= 1'b1;
o_tvalid <= 1'b1;
end else if (i_tvalid) begin
data_reg1 <= i_tdata;
data_reg2 <= data_reg1;
state <= FULL;
i_tready <= 1'b0;
o_tvalid <= 1'b1;
end else if (o_tready) begin
state <= EMPTY;
i_tready <= 1'b1;
o_tvalid <= 1'b0;
end else begin
state <= HALF;
i_tready <= 1'b1;
o_tvalid <= 1'b1;
end
end // case: HALF
// Both Registers Full.
// Upstream can not push to us in this state.
// Downstream can always read from us.
FULL: begin
if (o_tready) begin
state <= HALF;
i_tready <= 1'b1;
o_tvalid <= 1'b1;
end else begin
state <= FULL;
i_tready <= 1'b0;
o_tvalid <= 1'b1;
end
end
endcase // case(state)
end // else: !if(reset | clear)
assign o_tdata = (state == FULL) ? data_reg2 : data_reg1;
endmodule
| 7.728121 |
module axi_fifo_18 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam [ADDR_WIDTH:0] high_thresh = ALMOST_FULL_THRESH;
reg [ADDR_WIDTH:0] data_cnt_s = {{ADDR_P1{{1'b0}}}};
reg [ADDR_P1:0] high_compare;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "distributed" *) reg [FIFO_MSB:0] buffer[DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_ptr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = s_axis_tdata;
assign m_axis_tdata = data_d1;
assign almost_full = high_compare[ADDR_WIDTH];
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
next_wr_addr = wr_addr + 1;
end
end
end
// Data Cnt Logic
always @(posedge clk) begin
data_cnt_s <= next_wr_ptr - next_rd_ptr + occ_reg[0];
high_compare <= high_thresh - data_cnt_s;
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= 0;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 7.71763 |
module axi_fifo_19 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
output m_axis_tlast,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH + 1;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam [ADDR_WIDTH:0] high_thresh = ALMOST_FULL_THRESH;
reg [ADDR_WIDTH:0] data_cnt_s = {{ADDR_P1{{1'b0}}}};
reg [ADDR_P1:0] high_compare;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "distributed" *) reg [FIFO_MSB:0] buffer[DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_ptr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = {s_axis_tlast, s_axis_tdata};
assign m_axis_tdata = data_d1[DATA_WIDTH-1:0];
assign m_axis_tlast = data_d1[FIFO_MSB];
assign almost_full = high_compare[ADDR_WIDTH];
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
next_wr_addr = wr_addr + 1;
end
end
end
// Data Cnt Logic
always @(posedge clk) begin
data_cnt_s <= next_wr_ptr - next_rd_ptr + occ_reg[0];
high_compare <= high_thresh - data_cnt_s;
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= 0;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 7.984769 |
module axi_fifo_2 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam [ADDR_WIDTH:0] high_thresh = ALMOST_FULL_THRESH;
reg [ADDR_WIDTH:0] data_cnt_s = {{ADDR_P1{{1'b0}}}};
reg [ADDR_P1:0] high_compare;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "block" *) reg [FIFO_MSB:0] buffer[DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_ptr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = s_axis_tdata;
assign m_axis_tdata = data_d1;
assign almost_full = high_compare[ADDR_WIDTH];
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
next_wr_addr = wr_addr + 1;
end
end
end
// Data Cnt Logic
always @(posedge clk) begin
data_cnt_s <= next_wr_ptr - next_rd_ptr + occ_reg[0];
high_compare <= high_thresh - data_cnt_s;
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= 0;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 7.388076 |
module axi_fifo_2clk #(
parameter WIDTH = 69,
SIZE = 9
) (
input reset,
input i_aclk,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
input o_aclk,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
wire write, read, empty, full;
assign i_tready = ~full;
assign write = i_tvalid & i_tready;
wire [71:0] tdata_int;
wire tvalid_int, tready_int;
assign tvalid_int = ~empty;
assign read = tvalid_int & tready_int;
wire [71:0] wr_data;
assign wr_data[WIDTH-1:0] = i_tdata;
wire [71:0] rd_data;
assign tdata_int = rd_data[WIDTH-1:0];
generate
if (WIDTH < 72) begin
assign wr_data[71:WIDTH] = 0;
end
endgenerate
generate
if (SIZE <= 5)
fifo_short_2clk fifo_short_2clk (
.rst(reset),
.wr_clk(i_aclk),
.din(wr_data), // input [71 : 0] din
.wr_en(write), // input wr_en
.full(full), // output full
.wr_data_count(), // output [9 : 0] wr_data_count
.rd_clk(o_aclk), // input rd_clk
.dout(rd_data), // output [71 : 0] dout
.rd_en(read), // input rd_en
.empty(empty), // output empty
.rd_data_count() // output [9 : 0] rd_data_count
);
else
fifo_4k_2clk fifo_4k_2clk (
.rst(reset),
.wr_clk(i_aclk),
.din(wr_data), // input [71 : 0] din
.wr_en(write), // input wr_en
.full(full), // output full
.wr_data_count(), // output [9 : 0] wr_data_count
.rd_clk(o_aclk), // input rd_clk
.dout(rd_data), // output [71 : 0] dout
.rd_en(read), // input rd_en
.empty(empty), // output empty
.rd_data_count() // output [9 : 0] rd_data_count
);
endgenerate
generate
if (SIZE > 9)
axi_fifo #(
.WIDTH(WIDTH),
.SIZE (SIZE)
) fifo_1clk (
.clk(o_aclk),
.reset(reset),
.clear(1'b0),
.i_tdata(tdata_int),
.i_tvalid(tvalid_int),
.i_tready(tready_int),
.o_tdata(o_tdata),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
else begin
assign o_tdata = tdata_int;
assign o_tvalid = tvalid_int;
assign tready_int = o_tready;
end
endgenerate
endmodule
| 6.993573 |
module axi_fifo_2clk_cascade #(
parameter WIDTH = 69,
SIZE = 9
) (
input reset,
input i_aclk,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
input o_aclk,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
// FIXME reset should be taken into each clock domain properly
wire [WIDTH-1:0] int1_tdata, int2_tdata;
wire int1_tvalid, int1_tready, int2_tvalid, int2_tready;
axi_fifo_short #(
.WIDTH(WIDTH)
) pre_fifo (
.clk(i_aclk),
.reset(reset),
.clear(1'b0),
.i_tdata(i_tdata),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata(int1_tdata),
.o_tvalid(int1_tvalid),
.o_tready(int1_tready),
.space(),
.occupied()
);
axi_fifo_2clk #(
.WIDTH(WIDTH),
.SIZE (SIZE)
) main_fifo_2clk (
.reset(reset),
.i_aclk(i_aclk),
.i_tdata(int1_tdata),
.i_tvalid(int1_tvalid),
.i_tready(int1_tready),
.o_aclk(o_aclk),
.o_tdata(int2_tdata),
.o_tvalid(int2_tvalid),
.o_tready(int2_tready)
);
axi_fifo_short #(
.WIDTH(WIDTH)
) post_fifo (
.clk(o_aclk),
.reset(reset),
.clear(1'b0),
.i_tdata(int2_tdata),
.i_tvalid(int2_tvalid),
.i_tready(int2_tready),
.o_tdata(o_tdata),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endmodule
| 6.993573 |
module axi_fifo_3 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
output m_axis_tlast,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH + 1;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam [ADDR_WIDTH:0] high_thresh = ALMOST_FULL_THRESH;
reg [ADDR_WIDTH:0] data_cnt_s = {{ADDR_P1{{1'b0}}}};
reg [ADDR_P1:0] high_compare;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "block" *) reg [FIFO_MSB:0] buffer[DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_ptr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = {s_axis_tlast, s_axis_tdata};
assign m_axis_tdata = data_d1[DATA_WIDTH-1:0];
assign m_axis_tlast = data_d1[FIFO_MSB];
assign almost_full = high_compare[ADDR_WIDTH];
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
next_wr_addr = wr_addr + 1;
end
end
end
// Data Cnt Logic
always @(posedge clk) begin
data_cnt_s <= next_wr_ptr - next_rd_ptr + occ_reg[0];
high_compare <= high_thresh - data_cnt_s;
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= 0;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 7.917595 |
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