code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axis_stemlab_sdr_adc #(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
// ADC signals
output wire adc_csn,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] ad... | 7.488347 |
module axis_stemlab_sdr_dac #(
parameter integer DAC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
) (
// PLL signals
input wire aclk,
input wire ddr_clk,
input wire wrt_clk,
input wire locked,
// DAC signals
output wire dac_clk,
output wire ... | 7.488347 |
module axis_stepper #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire trg_flag,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
... | 7.009722 |
module axis_stopper #(
parameter PORT_COUNT = 4,
parameter REG_FOR_EN = 0
) (
input wire clk,
input wire rst,
input wire [PORT_COUNT-1:0] enable,
input wire [PORT_COUNT-1:0] s_axis_tvalid,
input wire [PORT_COUNT-1:0] s_axis_tlast,
output wire [PORT_COUNT-1:0] s_axis_tready,
outp... | 7.707302 |
module to monitor a an AXI-Stream link and gather various
// metric about packets and the stream in general
module axis_strm_monitor #(
parameter WIDTH = 64,
parameter COUNT_W = 32,
parameter PKT_LENGTH_EN = 0,
parameter PKT_CHKSUM_EN = 0,
parameter PKT_COUNT_EN = 0,
parameter XFER_COUNT_E... | 6.605169 |
module axis_switch_v1_1_22_axi_ctrl_read #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 7,
... | 9.124016 |
module axis_switch_v1_1_22_axi_ctrl_write #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 7,... | 9.124016 |
module axis_switch_v1_1_22_reg_bank_16x32 #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_ACTIVE_REG = 8, // ... | 9.124016 |
module from libaxis repo
`default_nettype none
module axis_sync_fifo #
(
parameter DATA_WIDTH = 0,
parameter DEPTH_WIDTH = 0
)
(
input wire clk,
input wire [DATA_WIDTH-1:0] s_tdata,
input wire s_tvalid,
output wire s_tready,
... | 7.857381 |
module axis_tagger #(
parameter integer AXIS_TDATA_WIDTH = 256
) (
// System signals
input wire aclk,
input wire tag_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
... | 6.913304 |
module axis_tester #(
parameter C_AXIS_DATA_WIDTH = 32) //only 32-bit
(
////////////////////////////////////////////////////////////////////////////
// AXI-Lite Slave (data input)
input AXIS_RSTN,
input AXIS_CLK,
input S_AXIS_TVALID,
input S_AXIS_TLAST,
output S_AXIS_TREADY,
inpu... | 8.606215 |
module axis_timer #(
parameter integer CNTR_WIDTH = 64
) (
// System signals
input wire aclk,
input wire aresetn,
input wire run_flag,
input wire cfg_flag,
input wire [CNTR_WIDTH-1:0] cfg_data,
output wire trg_flag,
output wire [CN... | 6.556656 |
module axis_to_cvita (
input wire clk,
input wire [63:0] s_axis_tdata,
input wire s_axis_tlast,
input wire s_axis_tvalid,
output wire s_axis_tready,
output wire [63:0] o_tdata,
output wire o_tlast,
output wire o_tvalid,
input wire o_tre... | 6.714538 |
module axis_trigger #(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter AXIS_TDATA_SIGNED = "FALSE"
) (
// System signals
input wire aclk,
input wire pol_data,
input wire [AXIS_TDATA_WIDTH-1:0] msk_data,
input wire [AXIS_TDATA_WIDTH-1:0] lvl_data,
outp... | 6.780757 |
module's
port width, even if you use the K&R-style Verilog syntax:
module my_thing # (
parameter W = 2
) (a, b);
localparam WW = W+W;
input wire [W -1:0] a;
output wire [WW -1:0] b;
endmodule
| 7.777765 |
module axis_width_converter #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter BIG_ENDIAN = 1,
parameter WIDTH_IN = 8, // 8,16,32
parameter WIDTH_OUT = 16 // 8,16,32
) (
input wire s_axis_aclk,
input wire s_axis_aresetn,
input wire [WIDTH_IN-1:0] s_axis_t... | 9.26688 |
module axis_variable #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
o... | 7.012108 |
module axis_volume_controller #(
parameter SWITCH_WIDTH = 4, // WARNING: this module has not been tested with other values of SWITCH_WIDTH, it will likely need some changes
parameter DATA_WIDTH = 24
) (
input wire clk,
input wire [SWITCH_WIDTH-1:0] sw,
//AXIS SLAVE INTERFACE
input wire [DATA_WI... | 8.30282 |
module Axis_WR (
Clk,
Addr,
MCUportL,
Din,
SpeedSetDone,
SpeedSet,
AxisStateCmd,
AxisPlsCmd,
SpeedCmd,
TargetPos,
RefPos
);
input Clk;
input [7:0] Addr;
input [15:0] MCUportL;
input [7:0] Din;
output [15:0] AxisStateCmd;
output [7:0] AxisPlsCmd;
output [7:0] S... | 6.829013 |
module axis_zeroer #(
parameter integer AXIS_TDATA_WIDTH = 32
) (
// System signals
input wire aclk,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
inp... | 7.330497 |
module axis_zmod_dac_v1_0 #(
parameter set_fs_i = 1'b1,
parameter set_fs_j = 1'b1
) (
input aclk, /* Clock input. This signal is corresponding with sample frequency */
input resetn, /* Reset input */
input enable_dac, /* enable dac output */
/* slave axis interface */
input [31:0] s_axi... | 7.48336 |
module AXI_top_design #(
parameter WIDTH,
SIZE
) (
input logic clk,
input logic resetn,
output logic [4095:0][7:0] slave_mem,
output logic [4095:0][7:0] master_mem,
axi intf,
// inputs to master from tb
input logic [WIDTH-1:0] awaddr,
input logic [(WIDTH/8)-1:0] awlen,
input... | 7.580887 |
module SramAddrGen (
input [31:0] CurAddr,
input [ 7:0] Len,
input [ 2:0] Size,
input [ 1:0] Burst,
output [31:0] NextAddr
);
wire [11:0] iCurAddr = CurAddr[11:0]; // @[SramAddrGen.scala 27:30]
wire [1:0] _iSize_T_3 = 3'h2 == Size ? 2'h2 : {{1'd0}, 3'h1 == Size}; // @[Mux.scala 81:58]
wi... | 6.786747 |
module SramArbiter (
input ACLK,
input ARESETn,
input WrValid,
output WrReady,
input RdValid,
output RdReady
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire reset = ~ARESETn; // @[SramArbiter.scala 26:34]
reg choice; // @[SramArbiter.scala 35:34]
... | 6.76663 |
module axi_10g_ethernet_0_axi_mux (
input mux_select,
// mux inputs
input [63:0] tdata0,
input [ 7:0] tkeep0,
input tvalid0,
input tlast0,
output reg tready0,
input [63:0] tdata1,
input [ 7:0] tkeep1,
input tvalid1,... | 6.663917 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//------------------------------------------------... | 9.028271 |
module axi_10g_ethernet_0_fifo_ram #(
parameter ADDR_WIDTH = 9
) (
input wire wr_clk,
input wire [(ADDR_WIDTH-1):0] wr_addr,
input wire [ 63:0] data_in,
input wire [ 3:0] ctrl_in,
input wire wr_allow,
input wire ... | 6.663917 |
module axi_10g_ethernet_0_shared_clocking_wrapper (
input reset,
input refclk_p,
input refclk_n,
input qpll0reset,
input dclk,
input txoutclk,
output txoutclk_out,
output coreclk,
in... | 6.663917 |
module axi_10g_ethernet_0_shared_clock_and_reset (
input areset,
input refclk_p,
input refclk_n,
input qpll0reset,
output refclk,
input txoutclk,
output coreclk,
input qplllock,
input reset_tx_bufg_gt,
output wire areset_coreclk,
output wire areset_txusrclk2,
output gttxr... | 6.663917 |
module axi_10g_ethernet_0_sync_block #(
parameter C_NUM_SYNC_REGS = 5
) (
input wire clk,
input wire data_in,
output wire data_out
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b0}};
//------------------------------------------------... | 6.663917 |
module axi_10g_ethernet_0_sync_reset (
input clk, // clock to be sync'ed to
input reset_in, // Reset to be 'synced'
output reset_out // synced reset
);
// Internal Signals
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async0 = 1'b1;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *... | 6.663917 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_ad9234_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status
);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] r... | 7.781654 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_address_remap (
input [33:0] s_hbm_araddr,
input [33:0] s_hbm_awaddr,
output [33:0] m_hbm_araddr,
output [33:0] m_hbm_awaddr,
input [33:0] start_address
);
assign m_hbm_araddr = s_hbm_araddr | start_address;
assign m_hbm_awaddr = s_hbm_awaddr | start_address;
endmodule
| 7.879843 |
module axi_addr_miter(i_last_addr, i_size, i_burst, i_len);
parameter AW = 32,
DW = 32;
input wire [AW-1:0] i_last_addr;
input wire [2:0] i_size; // 1b, 2b, 4b, 8b, etc
input wire [1:0] i_burst; // fixed, incr, wrap, reserved
input wire [7:0] i_len;
localparam DSZ = $clog2(DW)-3;
wire [7:0] ref_incr;
w... | 7.095801 |
module axi_add_preamble #(
parameter WIDTH = 64
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
//
output reg [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
function [0:0] cvita_get_has... | 8.68711 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_alu_data_v1_0 #(
// Users to add parameters here
parameter SIZE = 16,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5... | 8.145305 |
module axi_apb_bridge_0_multiplexor (
m_apb_psel,
\GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ,
PSEL_i,
s_axi_aclk
);
output [0:0] m_apb_psel;
input \GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ;
input PSEL_i;
input s_axi_aclk;
wire \GEN_1_SELECT_SLAVE.M_APB_PSEL_i_reg[0]_0 ;
wire PSEL_i;
wire... | 7.048782 |
module axi_arbiter_stom_s2
// synopsys translate_off
`protect
// synopsys translate_on
#(parameter NUM = 2)
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by compa... | 7.648984 |
module axi_async_w #(
parameter aw = 4,
parameter w = 32
) (
input rst_n,
input clka,
input wvalida,
output wreadya,
input [aw-1:0] waddra,
input [w-1:0] wdataa,
input clkb,
output wvalidb,
input wreadyb,
output reg [aw-1:0] waddrb,
output reg [w-1:0] wdatab
);
... | 7.87238 |
module axi_axis_reader #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire ... | 7.262688 |
module axi_axis_writer #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire ... | 7.828766 |
module axi_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axca... | 7.858387 |
module axi_bfm_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
... | 6.770154 |
module axi_bfm_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (
.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI... | 6.859338 |
module axi_bit_reduce #(
parameter WIDTH_IN = 48,
parameter WIDTH_OUT = 25,
parameter DROP_TOP = 6,
parameter VECTOR_WIDTH = 1
) // vector_width = 2 for complex, 1 for real
(
input [VECTOR_WIDTH*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [VECTOR_WI... | 6.620806 |
module axi_bpsk_ctrl_v1_0 #(
// Users to add parameters here
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600,
// User parameters ends
// Do not... | 7.387489 |
module axi_bram_reader_v1_0 #(
// Users to add parameters here
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 13,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AX... | 7.060334 |
module axi_bram_writer #(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
) (
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [ AXI_ADDR_W... | 7.308028 |
module axi_broadcast_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wir... | 6.543268 |
module axi_broadcast_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
... | 6.543268 |
module axi_buffer #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 2,
parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH)
) (
clk_i,
rst_ni,
data_o,
valid_o,
ready_i,
valid_i,
data_i,
ready_o
);
//parameter DATA_WIDTH = 32;
//parameter BUFFER_DEPTH = 2;
//... | 8.345277 |
module axi_b_reg_slice (
bvalids,
bids,
bresps,
busers,
breadym,
aclk,
aresetn,
breadys,
bvalidm,
bidm,
brespm,
buserm
);
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + USER_WIDTH + 2... | 7.240446 |
module axi_channel_split_slice (
ready_src,
valid_dst,
payload_dst,
aclk,
aresetn,
valid_src,
payload_src,
ready_dst
);
parameter N_OUTPUTS = 2;
parameter PAYLD_WIDTH = 8;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter BITS_PER_CHUNK = 8;
input aclk;
input aresetn;
in... | 7.146376 |
module axi_chdr_header_trigger #(
parameter WIDTH = 64,
parameter SID = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
input i_tready,
output trigger
);
reg state;
localparam IDLE = 0;
localparam RUN = 1;
always ... | 6.903454 |
module axi_clip_complex #(
parameter WIDTH_IN = 24,
parameter WIDTH_OUT = 16,
parameter FIFOSIZE = 0
) // leave at 0 for a single flop
(
input clk,
input reset,
input [2*WIDTH_IN-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH_OUT-1:0] o_tdata,
... | 6.720438 |
module axi_clock_converter_v2_1_6_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
////////////... | 7.39423 |
module axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
///////////... | 7.39423 |
module axi_ms #
(
// 其他参数
parameter integer INST_ADDR_WIDTH =32,
// slave 接口参数
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4,
// master 接口参数
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
// cpu 接口
reg... | 7.398281 |
module axi_conv #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8),
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter CNT_WIDTH = 9, //( 0- 511)
// to which number should the... | 8.236837 |
module axi_counter #(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH / 8),
// Width of counter in bits (counts from = to 2^CNT_WIDTH-1 )
parameter CNT_WIDTH = 9, //( 0- 511)
// to which number should ... | 7.729896 |
module axi_counter_tb;
//input
reg clk;
reg rst_L;
reg m_axis_tready;
//output
wire m_axis_tvalid;
wire [32-1:0] m_axis_tdata;
wire [1-1:0] m_axis_tkeep;
wire m_axis_tlast;
// FPAG Clk gen
always begin
clk = 1'b1;
#5 clk = 1'b0;
#5;
end
// SPI Master Clk gena
// always begin... | 6.532829 |
module axi_count_packets_in_fifo (
input clk,
input reset,
input in_axis_tvalid,
input in_axis_tready,
input in_axis_tlast,
input out_axis_tvalid,
input out_axis_tready,
input out_axis_tlast,
input pkt_tx_full,
output enable_tx
);
localparam WAIT_SOF = 0;
localparam... | 7.23811 |
module axi_cpu (
input rst_n,
input clk,
output avalid,
input aready,
output awe,
output [31:2] aaddr,
output [31:0] adata,
output [3:0] astrb,
input bvalid,
input [31:0] bdata
);
wire io_addr_strobe, io_read_strobe, io_write_strobe;
wire [31:0] io_addr, io_write_data;
wi... | 7.388656 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module axi_data_fifo_v2_1_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
... | 6.855506 |
module axi_data_fifo_v2_1_ndeep_srl #(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire ... | 6.855506 |
module axi_data_fifo_v2_1_21_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
... | 6.855506 |
module axi_data_fifo_v2_1_21_ndeep_srl #(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire ... | 6.855506 |
module axi_debug (
input reset,
input clk_sys,
output reg bridge_m0_waitrequest,
output wire [31:0] bridge_m0_readdata,
output reg bridge_m0_readdatavalid,
input wire [ 6:0] bridge_m0_burstcount,
input wire [31:0] bridge_m0_writedata,
input wire [19:0] bridge_m0_addre... | 6.93872 |
module axi_decoder (
input [`AXI_ADDR_WIDTH - 1 : 0] addr,
output reg [2:0] slave_no
);
/*
//---------------------------------------------------------------------//
Block Name Address Range
Reserved for FLASH 0x0000_0000 ~ 0x3FFF_FFFF
KPLIC 0x4000_0000 ~ 0x43FF_FFFF
MTIMER 0x4400_0000 ~ 0x4FFF_FFFF
Re... | 6.928726 |
module AXI_DELAY #(
parameter REFCLK_FREQUENCY = 300,
parameter NATIVE_ADDR_WDITH = 1,
parameter NATIVE_DATA_WIDTH = 9,
parameter S_AXI_ADDR_WIDTH = 3,
parameter S_AXI_DATA_WIDTH = 32,
parameter MODE = "TIME"
) (
input REFCLK,
input ... | 6.829539 |
module axi_delay_fifo #(
parameter DELAY = 4, // What to do when errors occur -- wait for next packet or next burst
parameter WIDTH = 32
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tval... | 6.992055 |
module axi_demo_tb ();
reg clk, reset;
wire done;
wire error;
localparam NUM_OF_RUNNING_CLOCK_CYCLES = 300;
axi_demo axi (
.clk (clk),
.reset(reset),
.done (done),
.error(error)
);
initial begin
$dumpfile("axi_demo_tb.vcd");
$dumpvars(0, axi_demo_tb);
clk = 0;
... | 7.944191 |
module axi_demux4 #(
parameter ACTIVE_CHAN = 4'b1111, // ACTIVE_CHAN is a map of connected outputs
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
output [WIDTH-1:0] header,
input [1:0] dest,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input... | 8.417115 |
module axi_demux8 #(
parameter ACTIVE_CHAN = 8'b11111111, // ACTIVE_CHAN is a map of connected outputs
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
output [WIDTH-1:0] header,
input [2:0] dest,
input [WIDTH-1:0] i_tdata,
input i_tlast,
i... | 8.216562 |
module axi_dma_r (
// system inputs
input clk,
input rst,
// Databus interface
output reg ready,
input valid,
input [`DDR_ADDR_W-1:0] addr,
output [ `MIG_BUS_W-1:0] rdata,
// DMA configuration
input [`AXI_LEN_W-1:0] len,
/... | 7.098171 |
module axi_drop_packet #(
parameter WIDTH = 32,
parameter MAX_PKT_SIZE = 1024
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
input i_tlast,
input i_terror,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
output o_tlas... | 7.3235 |
module axi_dummy (
// sys connect
input s_axi_aclk,
input s_axi_areset,
// axi4 lite slave port
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
input s_axi_wvalid,
output ... | 9.188688 |
module axi_embed_tlast #(
parameter WIDTH = 64,
parameter ADD_CHECKSUM = 0
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
//
output reg [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
... | 7.098611 |
module for Spartan-6 PCIe Block
// The BRAM A port is the write port.
// The BRAM B port is the read port.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_enhanced_pcie_v1_04_a_pcie_bram_s6 #(
parameter DOB_REG = 0, // 1 use ... | 7.510734 |
module for Spartan-6 PCIe Block
//
// Given the selected core configuration, calculate the number of
// BRAMs and pipeline stages and instantiate the BRAMS.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_enhanced_pcie_v1_04_a_... | 7.510734 |
module axi_extract_tlast #(
parameter WIDTH = 64,
parameter VALIDATE_CHECKSUM = 0
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output reg i_tready,
//
output [WIDTH-1:0] o_tdata,
output reg o_tlast,
output reg o_tvalid,
in... | 8.352477 |
module extracts the TLAST and TKEEP values that were embedded by the
// axi_embed_tlast_tkeep module. See axi_embed_tlast_tkeep for a description
// of how the data is encoded.
//
// Here are some extraction examples for DATA_W = 64.
//
// 0x1234567887654321 becomes
// 0x1234567887654321 (no changes)
//
/... | 7.368047 |
module axi_FanInPrimitive_Req #(
parameter AUX_WIDTH = 32,
parameter ID_WIDTH = 16
) (
RR_FLAG,
data_AUX0_i,
data_AUX1_i,
data_req0_i,
data_req1_i,
data_ID0_i,
data_ID1_i,
data_gnt0_o,
data_gnt1_o,
data_AUX_o,
data_req_o,
data_ID_o,
data_gnt_i,
lock_EXCLU... | 8.239046 |
module axi_fast_fifo #(
parameter WIDTH = 64
) (
input clk,
input reset,
input clear,
//
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output reg i_tready,
//
output [WIDTH-1:0] o_tdata,
output reg o_tvalid,
input o_tready
);
reg [WIDTH-1:0] data_reg1, data_reg2;
reg [... | 7.728121 |
module axi_fifo_18 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DA... | 7.71763 |
module axi_fifo_19 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
output s_axis_tready,
output almost_full,
output m_axi... | 7.984769 |
module axi_fifo_2 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DAT... | 7.388076 |
module axi_fifo_2clk #(
parameter WIDTH = 69,
SIZE = 9
) (
input reset,
input i_aclk,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
input o_aclk,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
wire write, read, empty, full;
assign i_tready =... | 6.993573 |
module axi_fifo_2clk_cascade #(
parameter WIDTH = 69,
SIZE = 9
) (
input reset,
input i_aclk,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
input o_aclk,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready
);
// FIXME reset should be taken into each c... | 6.993573 |
module axi_fifo_3 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
output s_axis_tready,
output almost_full,
output m_axis... | 7.917595 |
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