code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module avg (
din,
reset,
clk,
ready,
dout
);
input [15:0] din;
output [15:0] dout;
input reset, clk;
output ready;
endmodule
| 6.69656 |
module aviso_boletas (
input clk,
input comprar,
input compra_exitosa,
output reg impresion
);
reg [27:0] count;
initial begin
count = 0;
impresion = 0;
end
always @(posedge clk) begin
if (comprar & compra_exitosa) begin
impresion = 1;
count = 1;
end else if (count > 200000000) begin
impresion = 0;
count = 0;
end else if (count) begin
count = count + 1;
end
end
endmodule
| 7.31417 |
module AvlStreamAdapter (
input i_avl_clock,
input i_avl_reset,
output o_avl_burstbegin,
output [ 7:0] o_avl_be,
output [25:0] o_avl_adr,
output [63:0] o_avl_dat,
output reg o_avl_wr_req,
output reg o_avl_rdt_req,
output [ 2:0] o_avl_size,
input [63:0] i_avl_rdt,
input i_avl_ready,
input i_avl_rdt_valid,
output reg o_stream_valid,
input o_stream_ready,
output [63:0] o_stream_payload_rdt,
input i_stream_valid,
output reg i_stream_ready,
input i_stream_payload_we,
input [25:0] i_stream_payload_adr,
input [63:0] i_stream_payload_dat,
input [ 7:0] i_stream_payload_sel,
input i_stream_payload_burstbegin,
input [ 2:0] i_stream_payload_size
);
wire when_AvlStreamAdapter_l67;
always @(*) begin
i_stream_ready = 1'b0;
if (i_avl_rdt_valid) begin
i_stream_ready = 1'b1;
end
if (when_AvlStreamAdapter_l67) begin
if (i_stream_payload_we) begin
i_stream_ready = 1'b1;
end
end
end
assign o_avl_burstbegin = i_stream_payload_burstbegin;
assign o_avl_be = i_stream_payload_sel;
assign o_avl_adr = i_stream_payload_adr;
assign o_avl_dat = i_stream_payload_dat;
always @(*) begin
o_avl_wr_req = 1'b0;
if (when_AvlStreamAdapter_l67) begin
o_avl_wr_req = i_stream_payload_we;
end
end
always @(*) begin
o_avl_rdt_req = 1'b0;
if (when_AvlStreamAdapter_l67) begin
o_avl_rdt_req = (!i_stream_payload_we);
end
end
assign o_avl_size = i_stream_payload_size;
always @(*) begin
o_stream_valid = 1'b0;
if (i_avl_rdt_valid) begin
o_stream_valid = 1'b1;
end
end
assign o_stream_payload_rdt = i_avl_rdt;
assign when_AvlStreamAdapter_l67 = (i_stream_valid && i_avl_ready);
endmodule
| 6.986663 |
module avl_adxcfg_0 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9:0] rcfg_in_address_0, // .address
input wire [31:0] rcfg_in_writedata_0, // .writedata
output wire [31:0] rcfg_in_readdata_0, // .readdata
output wire rcfg_in_waitrequest_0, // .waitrequest
output wire rcfg_out_read_0, // rcfg_m0.read
output wire rcfg_out_write_0, // .write
output wire [ 9:0] rcfg_out_address_0, // .address
output wire [31:0] rcfg_out_writedata_0, // .writedata
input wire [31:0] rcfg_out_readdata_0, // .readdata
input wire rcfg_out_waitrequest_0, // .waitrequest
input wire rcfg_in_read_1, // rcfg_s1.read
input wire rcfg_in_write_1, // .write
input wire [ 9:0] rcfg_in_address_1, // .address
input wire [31:0] rcfg_in_writedata_1, // .writedata
output wire [31:0] rcfg_in_readdata_1, // .readdata
output wire rcfg_in_waitrequest_1, // .waitrequest
output wire rcfg_out_read_1, // rcfg_m1.read
output wire rcfg_out_write_1, // .write
output wire [ 9:0] rcfg_out_address_1, // .address
output wire [31:0] rcfg_out_writedata_1, // .writedata
input wire [31:0] rcfg_out_readdata_1, // .readdata
input wire rcfg_out_waitrequest_1 // .waitrequest
);
endmodule
| 6.652439 |
module avl_adxcfg_1 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9:0] rcfg_in_address_0, // .address
input wire [31:0] rcfg_in_writedata_0, // .writedata
output wire [31:0] rcfg_in_readdata_0, // .readdata
output wire rcfg_in_waitrequest_0, // .waitrequest
output wire rcfg_out_read_0, // rcfg_m0.read
output wire rcfg_out_write_0, // .write
output wire [ 9:0] rcfg_out_address_0, // .address
output wire [31:0] rcfg_out_writedata_0, // .writedata
input wire [31:0] rcfg_out_readdata_0, // .readdata
input wire rcfg_out_waitrequest_0, // .waitrequest
input wire rcfg_in_read_1, // rcfg_s1.read
input wire rcfg_in_write_1, // .write
input wire [ 9:0] rcfg_in_address_1, // .address
input wire [31:0] rcfg_in_writedata_1, // .writedata
output wire [31:0] rcfg_in_readdata_1, // .readdata
output wire rcfg_in_waitrequest_1, // .waitrequest
output wire rcfg_out_read_1, // rcfg_m1.read
output wire rcfg_out_write_1, // .write
output wire [ 9:0] rcfg_out_address_1, // .address
output wire [31:0] rcfg_out_writedata_1, // .writedata
input wire [31:0] rcfg_out_readdata_1, // .readdata
input wire rcfg_out_waitrequest_1 // .waitrequest
);
endmodule
| 6.528295 |
module avl_adxcfg_2 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9:0] rcfg_in_address_0, // .address
input wire [31:0] rcfg_in_writedata_0, // .writedata
output wire [31:0] rcfg_in_readdata_0, // .readdata
output wire rcfg_in_waitrequest_0, // .waitrequest
output wire rcfg_out_read_0, // rcfg_m0.read
output wire rcfg_out_write_0, // .write
output wire [ 9:0] rcfg_out_address_0, // .address
output wire [31:0] rcfg_out_writedata_0, // .writedata
input wire [31:0] rcfg_out_readdata_0, // .readdata
input wire rcfg_out_waitrequest_0, // .waitrequest
input wire rcfg_in_read_1, // rcfg_s1.read
input wire rcfg_in_write_1, // .write
input wire [ 9:0] rcfg_in_address_1, // .address
input wire [31:0] rcfg_in_writedata_1, // .writedata
output wire [31:0] rcfg_in_readdata_1, // .readdata
output wire rcfg_in_waitrequest_1, // .waitrequest
output wire rcfg_out_read_1, // rcfg_m1.read
output wire rcfg_out_write_1, // .write
output wire [ 9:0] rcfg_out_address_1, // .address
output wire [31:0] rcfg_out_writedata_1, // .writedata
input wire [31:0] rcfg_out_readdata_1, // .readdata
input wire rcfg_out_waitrequest_1 // .waitrequest
);
endmodule
| 6.506539 |
module avl_adxcfg_3 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9:0] rcfg_in_address_0, // .address
input wire [31:0] rcfg_in_writedata_0, // .writedata
output wire [31:0] rcfg_in_readdata_0, // .readdata
output wire rcfg_in_waitrequest_0, // .waitrequest
output wire rcfg_out_read_0, // rcfg_m0.read
output wire rcfg_out_write_0, // .write
output wire [ 9:0] rcfg_out_address_0, // .address
output wire [31:0] rcfg_out_writedata_0, // .writedata
input wire [31:0] rcfg_out_readdata_0, // .readdata
input wire rcfg_out_waitrequest_0, // .waitrequest
input wire rcfg_in_read_1, // rcfg_s1.read
input wire rcfg_in_write_1, // .write
input wire [ 9:0] rcfg_in_address_1, // .address
input wire [31:0] rcfg_in_writedata_1, // .writedata
output wire [31:0] rcfg_in_readdata_1, // .readdata
output wire rcfg_in_waitrequest_1, // .waitrequest
output wire rcfg_out_read_1, // rcfg_m1.read
output wire rcfg_out_write_1, // .write
output wire [ 9:0] rcfg_out_address_1, // .address
output wire [31:0] rcfg_out_writedata_1, // .writedata
input wire [31:0] rcfg_out_readdata_1, // .readdata
input wire rcfg_out_waitrequest_1 // .waitrequest
);
endmodule
| 6.941456 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module avl_adxcvr_octet_swap #(
parameter NUM_OF_LANES = 1
) (
input clk,
input reset,
input in_valid,
output in_ready,
input [NUM_OF_LANES*32-1:0] in_data,
input [3:0] in_sof,
output out_valid,
input out_ready,
output [NUM_OF_LANES*32-1:0] out_data,
output [3:0] out_sof
);
assign in_ready = out_ready;
assign out_valid = in_valid;
generate
genvar i;
genvar j;
for (j = 0; j < 4; j = j + 1) begin: gen_octet
for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane
assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8];
end
assign out_sof[j] = in_sof[3-j];
end
endgenerate
endmodule
| 8.180735 |
module avl_dpram (
input csi_clk, // clock do avalon
input csi_clk500, // clock de 500 KHz
input rsi_reset_n, // reset do avalon
input avs_s0_read, // read
input avs_s0_write, // write
input [ 4:0] avs_s0_address, // address - diferenciar regs
input [31:0] avs_s0_writedata, // bus write_data
output [31:0] avs_s0_readdata // bus read_data
);
// instancia memória dual-port RAM na interface...
ram_port_2 ram_port_2_inst (
.address_a(avs_s0_address), // endereço do port A é do Avalon
.address_b(Loc_ramAddress), // end da ram port B é local
.clock_a (csi_clk), // clk do port A é do Avalon
.clock_b (Loc_ramclk), // clock do port B também local
.data_a (avs_s0_writedata), // dado para port A do Avalon
.data_b (Loc_writedata), // dado do port B é local
.wren_a (avs_s0_write), // Write_Enable do port A do Avalon
.wren_b (Loc_ramwrite), // write_Enable do port B local = '1'
.q_a (avs_s0_readdata), // QA é lido diretamente no Avalon
.q_b (Loc_readdata) // QB local deve ser guardado em um reg
);
// meu componente - escreve e lê RAM pelo port B
wire [31:0] Loc_writedata; // dados a serem gravados na RAM
wire [31:0] Loc_readdata; // dados a serem lidos da RAM
wire [ 4:0] Loc_ramAddress; // add local da memória
wire Loc_ramclk; // clock local da ram
wire Loc_ramread; // read
wire Loc_ramwrite; // write
guitar_effect guitar_effect_inst (
.clk(csi_clk500),
.reset(rsi_reset_n),
.loc_writedata(Loc_writedata),
.loc_readdata(Loc_readdata),
.loc_ramaddress(Loc_ramAddress),
.loc_ramclk(Loc_ramclk),
.loc_ramread(avs_s0_read),
.loc_ramwrite(Loc_ramwrite)
);
endmodule
| 7.973445 |
module generates a reset signal controlled by an Avalon-MM
* interface.
*
*/
module avmm_reset_hw #(
parameter ACTIVE_LOW_OUT = 0
)(
input clock,
input reset,
input write,
input [31:0] writedata,
input chipsel,
output user_reset
);
reg reset_gen;
always @ (posedge clock or posedge reset) begin
if (reset) begin
reset_gen <= 1'b0;
end else if (write && chipsel) begin
reset_gen <= writedata[0];
end
end
generate if (ACTIVE_LOW_OUT != 0) begin
assign user_reset = reset_gen;
end else begin
assign user_reset = !reset_gen;
end endgenerate
endmodule
| 7.414651 |
module sha3_tb ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] avs_s0_readdata; // From u_sha3 of avalon_sha3.v
wire avs_s0_waitrequest; // From u_sha3 of avalon_sha3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [7:0] avs_s0_address; // To u_sha3 of avalon_sha3.v
reg avs_s0_read; // To u_sha3 of avalon_sha3.v
reg avs_s0_write; // To u_sha3 of avalon_sha3.v
reg [31:0] avs_s0_writedata; // To u_sha3 of avalon_sha3.v
// reg avs_s0_chipselect; //
reg clk; // To u_sha3 of avalon_sha3.v
reg reset; // To u_sha3 of avalon_sha3.v
// End of automatics
initial begin
reset = 0;
#10;
reset = 1;
#100;
reset = 0;
// #1000000;
// $finish;
end
initial begin
clk = 0;
forever begin
#10;
clk = ~clk;
end
end
task write(input [7:0] addr, input [31:0] data);
begin
@(negedge clk);
avs_s0_address = addr;
avs_s0_writedata = data;
avs_s0_write = 1;
avs_s0_read = 0;
// avs_s0_chipselect = 0;
@(posedge clk);
end
endtask // write
task read(input [7:0] addr);
begin
@(negedge clk);
avs_s0_address = addr;
avs_s0_read = 1;
avs_s0_write = 0;
// avs_s0_chipselect = 0;
@(posedge clk);
end
endtask
task idle;
@(negedge clk);
endtask
initial begin : bfm
reg [9:0] addr;
reg [31:0] data;
reg [3:0] strb;
reg flag;
#200;
@(posedge clk);
forever begin
while (reset == 1'b1) begin
@(posedge clk);
end // while (reset == 1'b1)
case ($avl_try_next_item(
addr, strb, data, flag
))
0: begin : valid_transaction
if (flag == 1) begin // write
write(addr / 4, data);
end // if (flag == 1)
else begin
read(addr / 4);
end
while (avs_s0_waitrequest) begin
@(posedge clk);
end
@(negedge clk);
if (flag == 0) data = avs_s0_readdata;
avs_s0_address = 'bX;
avs_s0_read = 0;
avs_s0_writedata = 'bX;
avs_s0_write = 0;
// avs_s0_chipselect = 0;
if ($avl_item_done(0) != 0); // $finish;
if ($avl_put(addr, strb, data, flag) != 0) begin
// $finish;
end
end // block: valid_tr
default: begin : idle_transaction
@(negedge clk);
avs_s0_read = 1'b0;
avs_s0_write = 1'b0;
@(posedge clk);
end
// default: ; // $finish;
endcase
end // forever begin
end // initial begin
initial begin
$dumpfile("avmm_sha3.vcd");
$dumpvars(0, sha3_tb);
end // initial begin
avalon_sha3_wrapper u_sha3 ( /*AUTOINST*/
// Outputs
.avs_s0_readdata (avs_s0_readdata[31:0]),
.avs_s0_waitrequest(avs_s0_waitrequest),
// Inputs
.clk (clk),
.reset (reset),
// .avs_s0_chipselect (avs_s0_chipselect),
.avs_s0_address (avs_s0_address[7:0]),
.avs_s0_read (avs_s0_read),
.avs_s0_write (avs_s0_write),
.avs_s0_writedata (avs_s0_writedata[31:0])
);
endmodule
| 6.924456 |
module is simply a multiplexer for a data bus. Nothing particularly special.
*/
module avmm_width_adapter_mux #(
parameter MUX_SELECT_WIDTH = 2,
parameter SYMBOL_WIDTH = 32,
parameter MUX_INPUTS = (1<<MUX_SELECT_WIDTH)
)(
input [(MUX_INPUTS*SYMBOL_WIDTH)-1:0] in,
input [MUX_SELECT_WIDTH-1:0] select,
output [SYMBOL_WIDTH-1:0]out
);
wire [SYMBOL_WIDTH-1:0] mux [MUX_INPUTS-1:0];
genvar i;
generate for (i = 0; i < MUX_INPUTS; i=i+1) begin : mux_loop
localparam j = i * SYMBOL_WIDTH;
assign mux[i] = in[j+:SYMBOL_WIDTH]; //Connect all the symbols on the wider input. Each symbol goes to a different multiplexer input
end endgenerate
assign out = mux[select]; //Select which one we want!
endmodule
| 8.245224 |
module AvoidGoing (
input clk,
input CLK_1s,
input nCR,
input left,
input right,
input [19:0] dis,
output reg [1:0] AvoidSignal
);
reg [3:0] env;
wire stright;
parameter isBlock = 20'd200;
assign stright = dis[19:0] < isBlock ? 1'b1 : 1'b0; //dis less than isBlock -> 1
assign testLight = env;
always @(posedge CLK_1s or negedge nCR) begin
if (~nCR) begin
env <= 3'b000;
end else begin
env <= {stright, ~left, ~right};
end
end
always @(posedge clk or negedge nCR) begin
if (~nCR) begin
AvoidSignal <= 2'b00;
end else begin
case (env)
3'b000: begin //stright
AvoidSignal <= 2'b00;
end
3'b001: begin //stright
AvoidSignal <= 2'b00;
end
3'b010: begin //stright
AvoidSignal <= 2'b00;
end
3'b011: begin //stright
AvoidSignal <= 2'b00;
end
3'b100: begin //left
AvoidSignal <= 2'b10;
end
3'b101: begin //left
AvoidSignal <= 2'b10;
end
3'b110: begin //right
AvoidSignal <= 2'b01;
end
3'b111: begin //back
AvoidSignal <= 2'b11;
end
default: begin
AvoidSignal <= 2'b00;
end
endcase
end
end
endmodule
| 7.616419 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
left = 1'b0;
down = 1'b0;
right = 1'b0;
up = 1'b0;
case (scancode)
16'he06b: begin
left = 1'b1;
end
16'he072: begin
down = 1'b1;
end
16'he074: begin
right = 1'b1;
end
16'he075: begin
up = 1'b1;
end
endcase
end
endmodule
| 7.203305 |
module avoid_latch_else ();
reg q;
reg enable, d;
always @(enable or d)
if (enable) begin
q = d;
end else begin
q = 0;
end
initial begin
$monitor(" ENABLE = %b D = %b Q = %b", enable, d, q);
#1 enable = 0;
#1 d = 0;
#1 enable = 1;
#1 d = 1;
#1 d = 0;
#1 d = 1;
#1 d = 0;
#1 d = 1;
#1 enable = 0;
#1 $finish;
end
endmodule
| 6.820695 |
module avoid_latch_init ();
reg q;
reg enable, d;
always @(enable or d) begin
q = 0;
if (enable) begin
q = d;
end
end
initial begin
$monitor(" ENABLE = %b D = %b Q = %b", enable, d, q);
#1 enable = 0;
#1 d = 0;
#1 enable = 1;
#1 d = 1;
#1 d = 0;
#1 d = 1;
#1 d = 0;
#1 d = 1;
#1 enable = 0;
#1 $finish;
end
endmodule
| 6.746677 |
module avr109rx (
input rst,
input clk,
output [7:0] rx_data,
output rx_avail,
input rxd,
input rx_enabled
);
parameter CLK_FREQUENCY = 1000000;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
localparam BAUDDIV = (CLK_FREQUENCY / BAUD_RATE);
localparam LOG2_BAUDDIV = log2(BAUDDIV);
reg [7:0] rxshift_d, rxshift_q;
reg rx_active_d, rx_active_q;
reg rx_done_d, rx_done_q;
reg [3:0] rxcnt_d, rxcnt_q;
reg [LOG2_BAUDDIV-1:0] rxbaud_d, rxbaud_q;
assign rx_data = rxshift_q;
assign rx_avail = rx_done_q;
always @(*) begin
rx_active_d = rx_active_q;
rx_done_d = 1'b0;
if (rx_active_q) begin
rxshift_d = rxshift_q;
rxcnt_d = rxcnt_q;
if (rxbaud_q == BAUDDIV - 1) begin
if (rxcnt_q == 9) begin
if (rxd) begin
rx_active_d = 1'b0;
rx_done_d = 1'b1;
end
end else begin
rxshift_d = {rxd, rxshift_q[7:1]};
rxcnt_d = rxcnt_q + 1;
end
rxbaud_d = 0;
end else begin
rxbaud_d = rxbaud_q + 1;
end
end else begin
rxshift_d = {8{1'b0}};
rxcnt_d = 0;
rxbaud_d = BAUDDIV / 2;
if (~rxd) begin
rx_active_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (rst | ~rx_enabled) begin
rxshift_q <= {8{1'b0}};
rx_active_q <= 1'b0;
rx_done_q <= 1'b0;
rxcnt_q <= 0;
rxbaud_q <= 0;
end else begin
rxshift_q <= rxshift_d;
rx_active_q <= rx_active_d;
rx_done_q <= rx_done_d;
rxcnt_q <= rxcnt_d;
rxbaud_q <= rxbaud_d;
end
end
endmodule
| 6.903906 |
module avr109tx (
input rst,
input clk,
input [7:0] tx_data,
input tx_avail,
output txd,
output tx_ready
);
parameter CLK_FREQUENCY = 1000000;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
localparam BAUDDIV = (CLK_FREQUENCY / BAUD_RATE);
localparam LOG2_BAUDDIV = log2(BAUDDIV);
reg [8:0] txshift_d, txshift_q;
reg [3:0] txcnt_d, txcnt_q;
reg tx_active_d, tx_active_q;
reg [LOG2_BAUDDIV-1:0] txbaud_d, txbaud_q;
assign txd = txshift_q[0];
assign tx_ready = ~tx_active_q;
always @(*) begin
txshift_d = txshift_q;
txcnt_d = txcnt_q;
tx_active_d = tx_active_q;
txbaud_d = txbaud_q;
if (tx_active_q) begin
if (txbaud_q == BAUDDIV - 1) begin
txshift_d = {1'b1, txshift_q[8:1]};
if (txcnt_q == 9) tx_active_d = 0;
txcnt_d = txcnt_q + 1;
txbaud_d = 0;
end else begin
txbaud_d = txbaud_q + 1;
end
end else if (tx_avail) begin
txshift_d = {tx_data, 1'b0};
txcnt_d = 0;
txbaud_d = 0;
tx_active_d = 1;
end
end
always @(posedge clk) begin
if (rst) begin
txshift_q <= 9'b111111111;
txcnt_q <= 4'b0;
tx_active_q <= 1'b0;
txbaud_q <= {LOG2_BAUDDIV{1'b0}};
end else begin
txshift_q <= txshift_d;
txcnt_q <= txcnt_d;
tx_active_q <= tx_active_d;
txbaud_q <= txbaud_d;
end
end
endmodule
| 7.160051 |
module avRISC621_multicore_v (
Resetn_pin,
Clock_pin,
SW_pin,
PB_pin,
Display_pin
);
input Resetn_pin, Clock_pin;
// input I/OP
input [3:0] SW_pin;
input PB_pin;
// output I/OP
output [7:0] Display_pin;
wire [7:0] Master_out;
wire M_ack; // input to master, output from slave core
wire Request; // output from master, PB of slave core is used for request input
wire S_M_data_Req; // slave send request to master before sending data to the master
reg [9:0] S_M_Data; // data send from slave to master after computation
wire S_M_req0, S_M_req1, S_M_req2; // slave send request to master before sending data to the master
wire S_ack0, S_ack1, S_ack2;
wire Master_ack;
wire [9:0] Slave0_out, Slave1_out, Slave2_out; // data output from slave cores
//wire [1:0] Slave0_id, Slave1_id, Slave2_id;
wire [1:0] Slave_id;
// Master will send the data to all the salve cores at one time i.e. Broadcast communication to send the datat to slave cores
// Master Broadcasts the data only when it receives Ack from all the slave cores
assign Master_ack = (S_ack0 & S_ack1 & S_ack2);
//assign Master_ack = (S_ack1); // debug comment it for multicore
assign S_M_data_Req = (S_M_req0 | S_M_req1 | S_M_req2); // now master can send the data to slave
//assign Slave_id = (Slave0_id | Slave0_id | Slave0_id);
avRISC621pipe_v master (
Resetn_pin,
Clock_pin,
SW_pin,
PB_pin,
Master_ack,
S_M_data_Req,
S_M_Data,
Request,
Master_out,
Display_pin,
Slave_id
);
avRISC621pipe_slave0_v slave0 (
Resetn_pin,
Clock_pin,
Master_out[3:0],
Request,
S_M_req0,
S_ack0,
Slave0_out
);
avRISC621pipe_slave1_v slave1 (
Resetn_pin,
Clock_pin,
Master_out[3:0],
Request,
S_M_req1,
S_ack1,
Slave1_out
);
avRISC621pipe_slave2_v slave2 (
Resetn_pin,
Clock_pin,
Master_out[3:0],
Request,
S_M_req2,
S_ack2,
Slave2_out
);
// Behavioral part of the code
// Master core selects the data output from the slave core based on the slave core ID
// always@(posedge Clock_pin)
// begin
// if(Slave0_out[9:8] == 2'b00)
// S_M_Data = Slave0_out[7:0];
//
// else if(Slave1_out[9:8] == 2'b01)
// S_M_Data = Slave1_out[7:0];
//
// else if(Slave2_out[9:8] == 2'b10)
// S_M_Data = Slave2_out[7:0];
//
// else S_M_Data = 8'b00000000;
//
// end
always @(posedge Clock_pin) begin
if (Slave_id == 2'b00) S_M_Data = Slave0_out[7:0];
else if (Slave_id == 2'b01) S_M_Data = Slave1_out[7:0];
else if (Slave_id == 2'b10) S_M_Data = Slave2_out[7:0];
else S_M_Data = 8'b00000000;
end
endmodule
| 7.697296 |
module avr_cpu (
input clk,
input rst,
output [5:0] io_addr,
inout [7:0] io_data,
output io_read,
output io_write
);
wire [15:0] opcode;
wire opcode_cycle;
wire hold;
wire [11:0] rjmp;
avr_cpu_fetch fetch (
.clk(clk),
.rst(rst),
.opcode(opcode),
.opcode_cycle(opcode_cycle),
.hold(hold),
.rjmp(rjmp)
);
avr_cpu_exec exec (
.clk(clk),
.rst(rst),
.opcode(opcode),
.opcode_cycle(opcode_cycle),
.hold(hold),
.rjmp(rjmp),
.io_addr(io_addr),
.io_data(io_data),
.io_read(io_read),
.io_write(io_write)
);
endmodule
| 6.949914 |
module avr_cpu_alu (
input [3:0] opcode,
input [7:0] r_in,
input [7:0] d_in,
output reg [7:0] out
);
always @(opcode, r_in, d_in) begin
//default values
out = r_in;
case (opcode)
`ALU_OP_MOVE: begin //nothing to do, default behaviour
end
endcase
end
endmodule
| 7.285923 |
module avr_cpu_progmem #(
parameter ADDR_WIDTH = 9,
parameter DATA_WIDTH = 16,
parameter MEM_SIZE = 512
) (
input clk,
input [ADDR_WIDTH-1:0] addr,
output reg [DATA_WIDTH-1:0] data
);
reg [DATA_WIDTH-1:0] mem[0:MEM_SIZE-1];
initial begin
$readmemh("prog.hex", mem);
end
always @(posedge clk) begin
data <= mem[addr];
end
/*wire [15:0] data0;
wire [15:0] data1;
assign data = addr[8] ? data1 : data0;
SB_RAM256x16 ram0 (
.RDATA(data0),
.RADDR(addr[7:0]),
.RCLK(clk),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(7'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(16'b0),
.WE(1'b1),
.MASK(16'b0));
SB_RAM256x16 ram1 (
.RDATA(data0),
.RADDR(addr[7:0]),
.RCLK(clk),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(7'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(16'b0),
.WE(1'b1),
.MASK(16'b0));*/
endmodule
| 7.096648 |
module avr_cpu_register (
input clk,
input rst,
input [4:0] r_addr,
input [4:0] d_addr,
output [7:0] r_out,
output [7:0] d_out,
input [7:0] d_in
);
reg [7:0] register_bank[0:31];
assign r_out = register_bank[r_addr];
assign d_out = register_bank[d_addr];
integer i;
always @(posedge clk) begin
if (rst) for (i = 0; i < 32; i = i + 1) register_bank[i] <= 8'b0;
else register_bank[d_addr] <= d_in;
end
endmodule
| 6.687331 |
module avr_cpu_stack #(
parameter DATA_WIDTH = 9,
parameter STACK_DEPTH = 3,
parameter ADDR_WIDTH = $clog2(STACK_DEPTH + 1)
) (
input clk,
input rst,
input read,
input write,
inout [DATA_WIDTH-1:0] data
);
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] buffer[0:STACK_DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
assign data = read ? data_out : {DATA_WIDTH{1'bz}};
always @(posedge clk) begin
if (rst) addr <= 0;
else if (read) addr <= addr - 1;
else if (write) addr <= addr + 1;
if (write) buffer[addr] <= data;
data_out <= buffer[addr-1];
end
endmodule
| 7.700549 |
module avr_gpio #(
parameter IO_ADDR = 0,
parameter PORT_WIDTH = 8
) (
input clk,
input rst,
input [5:0] io_addr,
inout [7:0] io_data,
input io_write,
input io_read,
inout [PORT_WIDTH-1:0] gpio
);
reg [PORT_WIDTH-1:0] DDR;
reg [PORT_WIDTH-1:0] PORT;
wire [PORT_WIDTH-1:0] PIN;
reg [7:0] io_data_out;
assign io_data = io_read ? io_data_out : 8'bZ;
`ifdef SIMULATION
genvar i;
for (i = 0; i < PORT_WIDTH; i = i + 1) begin
assign gpio[i] = DDR[i] ? PORT[i] : 1'bZ;
end
assign PIN = gpio;
`endif
`ifdef ICE40_SYNTHESIS
genvar i;
for (i = 0; i < PORT_WIDTH; i = i + 1) begin
SB_IO #(
.PIN_TYPE(6'b100100), //{PIN_OUTPUT_REGISTERED_ENABLE, PIN_INPUT_REGISTERED}
.PULLUP (1'b0)
) portb0_pin (
.PACKAGE_PIN(gpio[i]),
.OUTPUT_ENABLE(DDR[i]),
.D_OUT_0(PORT[i]),
.OUTPUT_CLK(clk),
.D_IN_0(PIN[i]),
.INPUT_CLK(clk)
);
end
`endif
always @(posedge clk) begin
if (rst) begin
DDR <= {PORT_WIDTH{1'b0}};
PORT <= {PORT_WIDTH{1'b0}};
end else begin
if (io_write) begin
if (io_addr == (IO_ADDR + 1)) DDR <= io_data[PORT_WIDTH-1:0];
if (io_addr == (IO_ADDR + 2)) PORT <= io_data[PORT_WIDTH-1:0];
end
if (io_read) begin
if (io_addr == IO_ADDR) io_data_out <= {{8 - PORT_WIDTH{1'b0}}, PIN};
if (io_addr == (IO_ADDR + 1)) io_data_out <= {{8 - PORT_WIDTH{1'b0}}, DDR};
if (io_addr == (IO_ADDR + 2)) io_data_out <= {{8 - PORT_WIDTH{1'b0}}, PORT};
end
end
end
endmodule
| 9.021294 |
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
) (
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
// AVR Serial Signals
output tx,
input rx,
// ADC Interface Signals
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
reg [3:0] block_d, block_q;
reg busy_d, busy_q;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(
.CLK_RATE(CLK_RATE)
) cclk_detector (
.clk (clk),
.rst (rst),
.cclk (cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk (clk),
.rst (n_rdy),
.ss (spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck (spi_sck),
.done(spi_done),
.din (8'hff),
.dout(spi_dout)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE / SERIAL_BAUD_RATE));
serial_rx #(
.CLK_PER_BIT(CLK_PER_BIT)
) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(
.CLK_PER_BIT(CLK_PER_BIT)
) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(busy_q),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
// Output declarations
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
busy_d = busy_q;
block_d = {block_q[2:0], tx_block};
if (block_q[3] ^ block_q[2]) busy_d = 1'b0;
if (!tx_busy && new_tx_data) busy_d = 1'b1;
if (spi_ss) begin // device is not selected
byte_ct_d = 1'b0;
end
if (spi_done) begin // sent/received data from SPI
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
block_q <= block_d;
busy_q <= busy_d;
sample_channel_q <= sample_channel_d;
end
endmodule
| 8.050013 |
module avr_timer #(
parameter IO_ADDR = 0
) (
input clk,
input rst,
input [5:0] io_addr,
inout [7:0] io_data,
input io_write,
input io_read,
input T0
);
reg [2:0] TCCR;
reg [7:0] TCNT;
reg [9:0] prescaler;
wire prescaled_clk;
reg prescaled_clk_prev;
assign prescaled_clk =
TCCR == 3'b000 ? 1'b0 :
TCCR == 3'b001 ? clk :
TCCR == 3'b010 ? prescaler[2] :
TCCR == 3'b011 ? prescaler[5] :
TCCR == 3'b100 ? prescaler[7] :
TCCR == 3'b101 ? prescaler[9] :
TCCR == 3'b110 ? T0 :
~T0;
reg [7:0] io_data_out;
assign io_data = io_read ? io_data_out : 8'bZ;
always @(posedge clk) begin
if (rst) begin
prescaler <= 0;
TCCR <= 0;
TCNT <= 0;
end else begin
if (io_write) begin
if (io_addr == IO_ADDR) TCNT <= io_data;
if (io_addr == (IO_ADDR + 1)) TCCR <= io_data[2:0];
end
if (io_read) begin
if (io_addr == IO_ADDR) io_data_out <= TCNT;
if (io_addr == (IO_ADDR + 1)) io_data_out <= {5'b0, TCCR};
end
prescaler <= prescaler + 1;
prescaled_clk_prev <= prescaled_clk;
if (TCCR == 3'b001 || (prescaled_clk && !prescaled_clk_prev)) begin
TCNT <= TCNT + 1;
end
end
end
endmodule
| 7.195118 |
module avsdpll (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
inout vssd1, // User area 1 digital ground
`endif
output reg CLK,
input wire VCO_IN,
input wire ENb_CP,
input wire ENb_VCO,
input wire REF
);
`ifdef SIM
real period, lastedge, refpd;
initial begin
lastedge = 0.0;
period = 25.0; // 25ns period = 40MHz
CLK <= 0;
end
// Toggle clock at rate determined by period
always @(CLK or ENb_VCO) begin
if (ENb_VCO == 1'b1) begin
#(period / 2.0);
CLK <= (CLK === 1'b0);
end else if (ENb_VCO == 1'b0) begin
CLK <= 1'b0;
end else begin
CLK <= 1'bx;
end
end
// Update period on every reference rising edge
always @(posedge REF) begin
if (lastedge > 0.0) begin
refpd = $realtime - lastedge;
// Adjust period towards 1/8 the reference period
//period = (0.99 * period) + (0.01 * (refpd / 8.0));
period = (refpd / 8.0);
end
lastedge = $realtime;
end
`endif
endmodule
| 7.05919 |
module avst2axis #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
) (
input wire clk,
input wire rst,
output wire avst_ready,
input wire avst_valid,
input wire [ DATA_WIDTH-1:0] avst_data,
input wire avst_startofpacket,
input wire avst_endofpacket,
input wire [EMPTY_WIDTH-1:0] avst_empty,
input wire avst_error,
output wire [DATA_WIDTH-1:0] axis_tdata,
output wire [KEEP_WIDTH-1:0] axis_tkeep,
output wire axis_tvalid,
input wire axis_tready,
output wire axis_tlast,
output wire axis_tuser
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
assign avst_ready = axis_tready;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign axis_tdata[n*BYTE_WIDTH +: BYTE_WIDTH] = avst_data[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign axis_tdata = avst_data;
end
endgenerate
assign axis_tkeep = KEEP_ENABLE ? {KEEP_WIDTH{1'b1}} >> avst_empty : 0;
assign axis_tvalid = avst_valid;
assign axis_tlast = avst_endofpacket;
assign axis_tuser = avst_error;
endmodule
| 7.900295 |
module avst_keccak (
clk,
reset,
data_in,
end_in,
valid_in,
ready_in,
data_out,
end_out,
valid_out,
ready_out
);
input clk;
input reset;
input [7:0] data_in;
input end_in;
input valid_in;
output ready_in;
output [7:0] data_out;
output end_out;
output valid_out;
input ready_out;
reg in_ready; // To dut of keccak.v
// reg stage; // toggles to 1 once the output is ready
reg valid_out;
reg end_out;
reg [6:0] count_out;
reg ready_in;
wire buffer_full; // From dut of keccak.v
wire [511:0] out; // From dut of keccak.v
wire out_ready; // From dut of keccak.v
reg [7:0] out_reg;
wire [7:0] data_out;
wire ready_in_1;
assign data_out = out_reg;
assign ready_in_1 = end_out | ((~end_in) & ready_in);
always @(posedge clk)
if (reset) ready_in <= 1;
else ready_in <= ready_in_1;
always @(posedge clk) begin
if (reset) begin
out_reg <= 0;
count_out <= 0;
valid_out <= 0;
end_out <= 0;
end else if (out_ready == 1) begin
if (ready_out) begin
if (count_out == 'h40) begin
count_out <= 0;
valid_out <= 0;
end_out <= 1;
end else begin
out_reg[7] <= out[511-(count_out<<3)];
out_reg[6] <= out[510-(count_out<<3)];
out_reg[5] <= out[509-(count_out<<3)];
out_reg[4] <= out[508-(count_out<<3)];
out_reg[3] <= out[507-(count_out<<3)];
out_reg[2] <= out[506-(count_out<<3)];
out_reg[1] <= out[505-(count_out<<3)];
out_reg[0] <= out[504-(count_out<<3)];
if (count_out == 'h00) begin
valid_out <= 1;
end
count_out <= count_out + 1;
end
end
end
end
keccak dut (
.in (data_in[7:0]),
.clk (clk),
.reset (reset),
.in_ready (valid_in),
.is_last (end_in),
/*AUTOINST*/
// Outputs
.buffer_full (buffer_full),
.out (out[511:0]),
.out_ready (out_ready)
);
// Inputs
endmodule
| 6.881177 |
module avsvproc
#(parameter
NODE_NUM = 0,
AUTO_VALID_CSR = 0
)
(
input clk,
input rst_n,
// Avalon memory mapped master interface
output [31:0] avs_csr_address,
output avs_csr_write,
output [31:0] avs_csr_writedata,
output avs_csr_read,
input [31:0] avs_csr_readdata,
input avs_csr_readdatavalid,
// Interrupt
input irq
);
// Signals for VProc
wire update;
wire RD;
wire [31:0] Addr;
wire WE;
wire [31:0] DataOut;
wire [31:0] DataIn;
wire RDAck;
// Avalon bus protocol signals
wire avs_read;
reg RDLast;
reg avs_csr_readdatavalid_int;
// If auto-generation of read valid for CSR bus is selected, generate in cycle after avs_csr_read
generate
if (AUTO_VALID_CSR != 0)
// Generate a read data valid for the CSR bus, as the UUT does not do so
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
avs_csr_readdatavalid_int <= 1'b0;
else
begin
avs_csr_readdatavalid_int <= 1'b0;
if (avs_csr_read == 1'b1)
begin
avs_csr_readdatavalid_int <= 1'b1;
end
end
end
else
// If auto-generation of read valid for CSR bus is not selected, connect up the input port
always @(avs_csr_readdatavalid)
avs_csr_readdatavalid_int <= avs_csr_readdatavalid;
endgenerate
// Note. VProc produces byte addresses, but bus is 32 bit word addresses
assign avs_csr_read = avs_read;
assign avs_csr_write = WE;
assign avs_csr_writedata = DataOut;
assign avs_csr_address = {2'h0, Addr[31:2]};
assign DataIn = avs_csr_readdata;
assign RDAck = avs_csr_readdatavalid_int;
// ---------------------------------------
// VProc instantiation
// ---------------------------------------
VProc vproc_inst (
.Clk (clk),
.Addr (Addr),
.WE (WE),
.RD (RD),
.DataOut (DataOut),
.DataIn (DataIn),
.WRAck (WE),
.RDAck (RDAck),
.Interrupt ({2'h0, irq}),
.Update (update),
.UpdateResponse (update),
.Node (NODE_NUM[3:0])
);
// ---------------------------------------
// Generate a delayed version of the RD
// output of VProc
// ---------------------------------------
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
RDLast <= 1'b0;
else
RDLast <= RD;
end
// Pulse the AVS read signal only for the first cycles of RD, which won't be
// deasserted until the RDAck/avs_readdatavalid is returned.
assign avs_read = RD & ~RDLast;
endmodule
| 6.517283 |
module is grenerated using the site: https://bues.ch/cms/hacking/crcgen
#
# Licence
#############
# This code is Public Domain.
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
# RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
# NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
# USE OR PERFORMANCE OF THIS SOFTWARE.
# Poly in hex form: 0x04 C1 1D B7
# CRC polynomial coefficients: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
# Hexadecimal, reversed representation: 0xED B8 83 20 (hex)
# CRC width: 32 bits
# CRC shift direction: right
# OUTPUT Xor 0xffffffff
*/
// Design
// Avalon memory interface
module avs_mm_crc32_wraper(
clk, // clock.clk
reset, // reset.reset
// Memory mapped read/write slave interface
avs_address,
avs_read,
avs_write,
avs_writedata,
avs_readdata);
//Clk and reset
input clk;
input reset;
// Memory mapped read/write slave interface
input [7:0] avs_address;
input avs_read;
input avs_write;
input [31:0] avs_writedata;
output [31:0] avs_readdata;
//--- Internal Reg and fun
reg [31:0] out_data;
reg [31:0] crc32_sum;
reg [7:0] data;
wire [31:0] out;
reg rst;
crc crc32(.crcIn(crc32_sum),.data(data),.crcOut(out));
//When Read signal is issued put out data
// Writes the CRC32-sum and out_data
always @(posedge avs_read)
begin
//if ((avs_address == 8'h00) && (avs_read)) begin
if (avs_read)
case (avs_address )
8'h00 : out_data = out;
default : out_data = 8'hff;
endcase
end
// Writes the CRC32-data & crc32_sum
always @ (posedge avs_write or posedge reset)
begin
if (reset)
begin
rst=1; // Flag reset crc32 sum
end
else if ( avs_write ) begin
case (avs_address )
8'h00 : begin // Set CRC32-Sum and new input data
// If reset initiate CRC32 SUM
if(rst) begin
rst=0;
crc32_sum=32'hffffffff; //CRC32 Init
end else
crc32_sum=out;
data = avs_writedata & 8'hff; // Write new data to calculate crc32
end
//Writing to address 0x01 -> CRC32 RESET (set's crc32_sum to 0xffffffff when adding new data)
8'h01 : rst=1;
endcase
end
end // end write
// write data from reg to outport
assign avs_readdata = ~out_data; // Output is CRC32 sum inverted
endmodule
| 7.28505 |
module crc (
crcIn,
data,
crcOut
);
input [31:0] crcIn;
input [7:0] data;
output [31:0] crcOut;
assign crcOut[0] = (crcIn[2] ^ crcIn[8] ^ data[2]);
assign crcOut[1] = (crcIn[0] ^ crcIn[3] ^ crcIn[9] ^ data[0] ^ data[3]);
assign crcOut[2] = (crcIn[0] ^ crcIn[1] ^ crcIn[4] ^ crcIn[10] ^ data[0] ^ data[1] ^ data[4]);
assign crcOut[3] = (crcIn[1] ^ crcIn[2] ^ crcIn[5] ^ crcIn[11] ^ data[1] ^ data[2] ^ data[5]);
assign crcOut[4] = (crcIn[0] ^ crcIn[2] ^ crcIn[3] ^ crcIn[6] ^ crcIn[12] ^ data[0] ^ data[2] ^ data[3] ^ data[6]);
assign crcOut[5] = (crcIn[1] ^ crcIn[3] ^ crcIn[4] ^ crcIn[7] ^ crcIn[13] ^ data[1] ^ data[3] ^ data[4] ^ data[7]);
assign crcOut[6] = (crcIn[4] ^ crcIn[5] ^ crcIn[14] ^ data[4] ^ data[5]);
assign crcOut[7] = (crcIn[0] ^ crcIn[5] ^ crcIn[6] ^ crcIn[15] ^ data[0] ^ data[5] ^ data[6]);
assign crcOut[8] = (crcIn[1] ^ crcIn[6] ^ crcIn[7] ^ crcIn[16] ^ data[1] ^ data[6] ^ data[7]);
assign crcOut[9] = (crcIn[7] ^ crcIn[17] ^ data[7]);
assign crcOut[10] = (crcIn[2] ^ crcIn[18] ^ data[2]);
assign crcOut[11] = (crcIn[3] ^ crcIn[19] ^ data[3]);
assign crcOut[12] = (crcIn[0] ^ crcIn[4] ^ crcIn[20] ^ data[0] ^ data[4]);
assign crcOut[13] = (crcIn[0] ^ crcIn[1] ^ crcIn[5] ^ crcIn[21] ^ data[0] ^ data[1] ^ data[5]);
assign crcOut[14] = (crcIn[1] ^ crcIn[2] ^ crcIn[6] ^ crcIn[22] ^ data[1] ^ data[2] ^ data[6]);
assign crcOut[15] = (crcIn[2] ^ crcIn[3] ^ crcIn[7] ^ crcIn[23] ^ data[2] ^ data[3] ^ data[7]);
assign crcOut[16] = (crcIn[0] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[24] ^ data[0] ^ data[2] ^ data[3] ^ data[4]);
assign crcOut[17] = (crcIn[0] ^ crcIn[1] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[25] ^ data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[5]);
assign crcOut[18] = (crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[26] ^ data[0] ^ data[1] ^ data[2] ^ data[4] ^ data[5] ^ data[6]);
assign crcOut[19] = (crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[27] ^ data[1] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[7]);
assign crcOut[20] = (crcIn[3] ^ crcIn[4] ^ crcIn[6] ^ crcIn[7] ^ crcIn[28] ^ data[3] ^ data[4] ^ data[6] ^ data[7]);
assign crcOut[21] = (crcIn[2] ^ crcIn[4] ^ crcIn[5] ^ crcIn[7] ^ crcIn[29] ^ data[2] ^ data[4] ^ data[5] ^ data[7]);
assign crcOut[22] = (crcIn[2] ^ crcIn[3] ^ crcIn[5] ^ crcIn[6] ^ crcIn[30] ^ data[2] ^ data[3] ^ data[5] ^ data[6]);
assign crcOut[23] = (crcIn[3] ^ crcIn[4] ^ crcIn[6] ^ crcIn[7] ^ crcIn[31] ^ data[3] ^ data[4] ^ data[6] ^ data[7]);
assign crcOut[24] = (crcIn[0] ^ crcIn[2] ^ crcIn[4] ^ crcIn[5] ^ crcIn[7] ^ data[0] ^ data[2] ^ data[4] ^ data[5] ^ data[7]);
assign crcOut[25] = (crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[5] ^ data[6]);
assign crcOut[26] = (crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[6] ^ data[7]);
assign crcOut[27] = (crcIn[1] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[7] ^ data[1] ^ data[3] ^ data[4] ^ data[5] ^ data[7]);
assign crcOut[28] = (crcIn[0] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[4] ^ data[5] ^ data[6]);
assign crcOut[29] = (crcIn[0] ^ crcIn[1] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[5] ^ data[6] ^ data[7]);
assign crcOut[30] = (crcIn[0] ^ crcIn[1] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[6] ^ data[7]);
assign crcOut[31] = (crcIn[1] ^ crcIn[7] ^ data[1] ^ data[7]);
endmodule
| 7.40205 |
module avs_timing ( /*AUTOARG*/
// Outputs
avs_waitrequest,
// Inputs
sys_clk,
sys_rst,
avs_read,
avs_write
);
input sys_clk;
input sys_rst;
input avs_read;
input avs_write;
output avs_waitrequest;
reg register_ready_reg;
reg register_access_sreg;
always @(posedge sys_clk) begin
if (sys_rst || register_ready_reg) begin
register_access_sreg <= 1'b0;
end else if (avs_read | avs_write) begin
register_access_sreg <= 1'b1;
end
end // always @ (posedge unex_clk)
wire register_access;
assign register_access = register_access_sreg;
reg register_access_reg;
always @(posedge sys_clk) begin
if (sys_rst) begin
register_access_reg <= 1'b0;
end else begin
register_access_reg <= register_access;
end
end // always @ (posedge unex_clk)
wire register_access_rise;
assign register_access_rise = ~register_access_reg & register_access;
always @(posedge sys_clk) begin
if (sys_rst) begin
register_ready_reg <= 1'b0;
end else begin
register_ready_reg <= register_access_rise;
end
end
assign avs_waitrequest = ~register_ready_reg;
endmodule
| 8.074207 |
module av_CAM_v (
we_n,
rd_n,
din,
argin,
addrs,
dout,
mbits
);
parameter arg_max = 9,
// addrs_max=2,
bl_max = 4;
input we_n;
input rd_n; // this is used for debugging, to check what value in a particular location of CAM
input [1:0] addrs; // 2-bits to address 4 groups
input [arg_max-3:0] argin; // incoming TAG value (9-bit wide), but only using 7-bits for now
input [arg_max-3:0] din; // TAG values stored in CAM are 9-bit wide
output reg [arg_max-3:0] dout; // used for debugging with rd_n
output reg [3:0] mbits; // we have 4-groups so 4 1-bit match bit for each group
// declare CAM memory as an array of 4, 9-bit registers
reg [arg_max-3:0] cam_mem[3:0];
integer i, int_addrs, j;
//-- The INITIALIZE procedural block
initial begin
for (i = 0; i < 10; i = i + 1)
for (j = 0; j < 4; j = j + 1) cam_mem[j] = {(arg_max - 2) {1'b1}};
mbits = {bl_max{1'b0}};
j = j + 1;
end
/* Write procedural block
*
* This enables a new tag value to be written at a specific location,
* using a Write_enable, data input and address input busses as with any
* other memory.
*
* In the context of a cache, this happens when a new block is uploaded in the cache.
*/
always @(we_n, din, addrs) begin
int_addrs = addrs;
if(we_n == 1) // write is active low
begin
cam_mem[int_addrs] = din;
end
end
/* The READ procedural block.
* This allows a value at a specific location to be read out,
* using a RD, data output and address input busses as with any
* other memory.
*
* In the context of a cache, this is not necessary. This functionality
* is provided here for reference and debugging purposes.
*/
always @(rd_n, addrs, cam_mem) begin
int_addrs = addrs;
if(rd_n == 1) // read is also active low
begin
dout = cam_mem[int_addrs];
end else dout = {(arg_max - 2) {1'bz}}; // high impedance
end
/*
* Match logic -- actual CAM functionality
*
* an mbit is 1 if argument value is equal to content of CAM
*
*/
always @(argin, cam_mem) begin
mbits = 4'b0000; // initialized to all zeros
for (i = 0; i < 4; i = i + 1) begin
if (argin == cam_mem[i]) begin
mbits[i] = 1;
end
end
end
endmodule
| 8.519191 |
module operates 7-seg display based on mic input.
// Dependencies: NULL
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////
module AV_Indicator(
input DCLK, //6.25M
input RefSCLK, //20k
input SCLK, //
input [11:0] mic_in,
output [3:0] an,
output reg [6:0] SEG,
output [15:0] led,
output reg [3:0] volume
);
reg [11:0] mic_max;
reg [3:0] mask = 4'b0001;
reg digit = 1'b0;
reg [6:0] seg;
wire [3:0] vol_mod_10 = volume > 4'd9 ? volume - 4'd10 : volume;
wire maxstin = mic_max < mic_in;
assign an = ~(mask << digit); //shift 1/0 bit
assign led = (16'b1111111111111111 >> (5'd15 - volume));
reg [11:0] baseline = 12'b011111111111;
wire [11:0] mic_minus = mic_max > baseline ? mic_max - baseline : 12'b0;
reg [15:0] cnt = 16'b0000000000000000;
always @ (posedge RefSCLK) begin
volume <= (mic_minus >> 7);
digit = ~digit;
end
always @ (posedge SCLK) begin
mic_max <= maxstin ? mic_in : mic_max - 1;
seg = SEG;
end
always@(*)begin
if (digit) begin//10th
if(volume < 4'd10) SEG = 7'b1111111;
else SEG = 7'b1111001;
end else begin//1st
case (vol_mod_10)
4'd0: SEG = 7'b1000000;
4'd1: SEG = 7'b1111001;
4'd2: SEG = 7'b0100100;
4'd3: SEG = 7'b0110000;
4'd4: SEG = 7'b0011001;
4'd5: SEG = 7'b0010010;
4'd6: SEG = 7'b0000010 ;
4'd7: SEG = 7'b1111000;
4'd8: SEG = 7'b0000000;
4'd9: SEG = 7'b0010000;
endcase
end
end
endmodule
| 7.910961 |
module AV_integrator (
input clk65,
input pause,
input [12:0] menu_pixel,
input [12:0] score_pixel,
input [12:0] string1_pixel, //MSB is whether or not to use the pixel
input [12:0] string2_pixel,
input [12:0] string3_pixel,
input [12:0] string4_pixel,
input [12:0] string5_pixel,
input [12:0] string6_pixel,
input [11:0] bg_pixel,
output [11:0] pixel_out
);
wire [11:0] pixel;
assign pixel = menu_pixel[12] ? menu_pixel[11:0] :
score_pixel[12] ? score_pixel[11:0] :
string1_pixel[12] ? string1_pixel[11:0] :
string2_pixel[12] ? string2_pixel[11:0] :
string3_pixel[12] ? string3_pixel[11:0] :
string4_pixel[12] ? string4_pixel[11:0] :
string5_pixel[12] ? string5_pixel[11:0] :
string6_pixel[12] ? string6_pixel[11:0] :
bg_pixel[11:0];
assign pixel_out = pause ? ~pixel : pixel;
/*
always @(posedge clk65) begin //maybe make this assign and wires instead?
if( menu_pixel[12] == 1'b1 ) begin
pixel <= menu_pixel[11:0];
end
else if( score_pixel[12] == 1'b1 ) begin
pixel <= score_pixel[11:0];
end
else if( string1_pixel[12] == 1'b1 ) begin
pixel <= string1_pixel[11:0];
end
else if( string2_pixel[12] == 1'b1 ) begin
pixel <= string2_pixel[11:0];
end
else if( string3_pixel[12] == 1'b1 ) begin
pixel <= string3_pixel[11:0];
end
else if( string4_pixel[12] == 1'b1 ) begin
pixel <= string4_pixel[11:0];
end
else if( string5_pixel[12] == 1'b1 ) begin
pixel <= string5_pixel[11:0];
end
else if( string6_pixel[12] == 1'b1 ) begin
pixel <= string6_pixel[11:0];
end
else pixel <= bg_pixel[11:0];
end
*/
endmodule
| 6.758334 |
module AV_menu_graphics (
input clk65,
input pause,
input [10:0] hcount,
input [9:0] vcount,
output reg [12:0] menu_pixel
);
localparam WIDTH = 800;
localparam HEIGHT = 200;
localparam COLOR = 12'hD_D_D;
localparam startX = 100;
localparam startY = 50;
always @(posedge clk65) begin
if( hcount >= startX && hcount < (startX + WIDTH) &&
vcount >= startY && vcount < (startY + HEIGHT))
menu_pixel <= {pause, COLOR};
else menu_pixel <= 13'b0;
end
endmodule
| 6.661782 |
modules:
-- Function : This modules decodes Avalon MM transactions &
stalls each one by means of wait_req.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- $Header$
-- $Log$
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module av_slave_stalled
(
av_clk_ir, //Avalon clock
av_rst_il, //Active low reset
//Avalon MM Interface
av_read_ih, //1->Read xtn
av_write_ih, //1->Write xtn
av_begin_xfr_ih, //1->Begin xfr
av_wait_req_oh, //1->Wait/stall xtn
av_addr_id, //Address
av_write_data_id, //Write Data
av_read_data_od, //Read Data
//Local Bus interface
lb_rd_en_oh, //1->Read enable
lb_wr_en_oh, //1->Write enable
lb_addr_od, //Address input
lb_wr_data_od, //Write Data input
lb_rd_valid_id, //1->lb_rd_data_od is valid
lb_rd_data_id, //Read Data output
lb_wr_valid_id //1->write is valid
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
input av_clk_ir;
input av_rst_il;
input av_read_ih;
input av_write_ih;
input av_begin_xfr_ih;
input [11:0] av_addr_id;
input [15:0] av_write_data_id;
input lb_rd_valid_id;
input [15:0] lb_rd_data_id;
input lb_wr_valid_id;
//----------------------- Output Declarations -----------------------------
output av_wait_req_oh;
output [15:0] av_read_data_od;
output lb_rd_en_oh;
output lb_wr_en_oh;
output [11:0] lb_addr_od;
output [15:0] lb_wr_data_od;
//----------------------- Output Register Declaration ---------------------
reg [15:0] av_read_data_od;
//----------------------- Internal Register Declarations ------------------
reg xtn_valid_f;
//----------------------- Internal Wire Declarations ----------------------
//----------------------- Start of Code -----------------------------------
assign av_wait_req_oh = (av_read_ih | av_write_ih) & ~xtn_valid_f;
always@(posedge av_clk_ir, negedge av_rst_il)
begin
if(~av_rst_il)
begin
xtn_valid_f <= 1'b0;
av_read_data_od <= 16'd0;
end
else
begin
xtn_valid_f <= lb_wr_valid_id | lb_rd_valid_id;
av_read_data_od <= lb_rd_valid_id ? lb_rd_data_id : av_read_data_od;
end
end
assign lb_rd_en_oh = av_begin_xfr_ih & av_read_ih;
assign lb_wr_en_oh = av_begin_xfr_ih & av_write_ih;
assign lb_addr_od = av_addr_id;
assign lb_wr_data_od = av_write_data_id;
endmodule
| 7.517477 |
module av_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
av_pll_0002 av_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0(outclk_0), // outclk0.clk
.outclk_1(outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
| 7.047091 |
module av_pll2_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(3),
.output_clock_frequency0("140.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("25.200000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("18.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_2, outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.625355 |
module av_pll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("25.200000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("18.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.662034 |
module AV_sync_pipeline #(
parameter stages = 3
) (
input clk,
input hsync,
input vsync,
input blank,
output phsync,
output pvsync,
output pblank
);
reg [stages-1:0] h_pipe;
reg [stages-1:0] v_pipe;
reg [stages-1:0] b_pipe;
assign phsync = h_pipe[stages-1];
assign pvsync = v_pipe[stages-1];
assign pblank = b_pipe[stages-1];
always @(posedge clk) begin
h_pipe[stages-1:0] <= {h_pipe[stages-2:0], hsync};
v_pipe[stages-1:0] <= {v_pipe[stages-2:0], vsync};
b_pipe[stages-1:0] <= {b_pipe[stages-2:0], blank};
end
endmodule
| 6.71857 |
module AWGN_Pipelined (
output wire signed [15:0] awgn_out,
input wire clk,
input wire reset,
input wire [31:0] urng_seed1,
input wire [31:0] urng_seed2,
input wire [31:0] urng_seed3,
input wire [31:0] urng_seed4,
input wire [31:0] urng_seed5,
input wire [31:0] urng_seed6
);
wire [31:0] a;
wire [31:0] b;
wire [47:0] u0;
reg [47:0] u0_reg;
wire [15:0] u1;
reg [15:0] u1_reg;
wire [30:0] e;
reg [30:0] e_reg;
wire [16:0] f;
reg [16:0] f_reg;
wire signed [15:0] g0;
reg signed [15:0] g0_reg;
reg signed [15:0] g0_reg2;
wire signed [15:0] g1;
reg signed [15:0] g1_reg;
reg signed [15:0] g1_reg2;
wire signed [32:0] x0;
reg signed [15:0] x0_reg;
wire signed [32:0] x1;
reg signed [15:0] x1_reg;
reg half_clk;
reg out_select;
//can use a clock divider at the Taus and alternate between x0 and x1 every clock
taus urng_a (
a,
half_clk,
reset,
urng_seed1,
urng_seed2,
urng_seed3
);
taus urng_b (
b,
half_clk,
reset,
urng_seed4,
urng_seed5,
urng_seed6
);
assign u0 = {a, b[31:16]};
assign u1 = b[15:0];
//log module
log log_module (
e,
u0_reg
);
//sqrt module
sqrt sqrt_module (
f,
e_reg
);
//cos module
sincos cos_module (
g0,
g1,
u1_reg
);
assign x0 = $signed({1'b0, f_reg}) * g0_reg2;
assign x1 = $signed({1'b0, f_reg}) * g1_reg2;
assign awgn_out = out_select ? x1_reg : x0_reg;
//as we can output two noise samples for every f value, we need the output clock to be twice as fast as the pipeline clock to switch between samples
//While initial statements cannot be synthesized, it does not matter which value half_clk and out_select start with in a real implimentation
//The only difference is which order (x0 or x1 first) that the noise samples come out in
//attempting to add synthesisable reset behavior to these signals comes with significant overhead
initial begin
half_clk = 0;
out_select = 1;
end
always @(posedge clk) begin
half_clk <= !half_clk;
out_select <= !out_select;
end
always @(posedge half_clk) begin
u0_reg <= u0;
u1_reg <= u1;
e_reg <= e;
f_reg <= f;
g0_reg <= g0;
g1_reg <= g1;
//As u0 and u1 and their following operations are independant, we dont need to keep the two paths in sync
//however that would require regenerating the simulation data to include the 1 clk cycle offset
//instead an extra pipeline stage is added for g0 and g1 to keep them in sync with f
g0_reg2 <= g0_reg;
g1_reg2 <= g1_reg;
x1_reg <= x1[32:17];
x0_reg <= x0[32:17];
end
endmodule
| 6.50439 |
module AWGN_Pipelined_tb ();
wire signed [15:0] awgn_out;
reg clk;
reg reset;
reg [31:0] urng_seed1;
reg [31:0] urng_seed2;
reg [31:0] urng_seed3;
reg [31:0] urng_seed4;
reg [31:0] urng_seed5;
reg [31:0] urng_seed6;
reg signed [15:0] expected_x0;
reg signed [15:0] expected_x1;
AWGN_Pipelined dut (
awgn_out,
clk,
reset,
urng_seed1,
urng_seed2,
urng_seed3,
urng_seed4,
urng_seed5,
urng_seed6
);
integer x0_fd;
integer x1_fd;
integer status;
integer num_tests;
integer tests_passed;
integer largest_error;
initial begin
x0_fd = $fopen("../../../../MATLAB/x0.txt", "r");
if (x0_fd == 0) begin
$display("Failed to open x0.txt");
$finish;
end
x1_fd = $fopen("../../../../MATLAB/x1.txt", "r");
if (x1_fd == 0) begin
$display("Failed to open x1.txt");
$finish;
end
urng_seed1 = 64650448;
urng_seed2 = 83372788;
urng_seed3 = 21948290;
urng_seed4 = 64504248;
urng_seed5 = 8337978;
urng_seed6 = 21948180;
reset = 1;
clk = 0;
num_tests = 0;
tests_passed = 0;
largest_error = 0;
//clk must be toggled at least twice to get the synchronous reset to apply to the URNGs
//with the unknown initial state, it must be toggled 4 times for simulation but still only twice for an implimentation
//initial implimentation used asynchronous resests but vivado disliked it
#2 clk = 1;
#2 clk = 0;
#2 clk = 1;
#2 clk = 0;
reset = 0;
end
always begin
#100 #5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
#5 clk = 1;
#5 clk = 0;
while (!$feof(
x1_fd
) && !$feof(
x0_fd
)) begin
#5 clk = 1;
num_tests = num_tests + 2;
status = $fscanf(x0_fd, "%d\n", expected_x0);
status = $fscanf(x1_fd, "%d\n", expected_x1);
if (expected_x0 != awgn_out) begin
$display($time, ": x0 was %d when %d was expected (%d)", awgn_out, expected_x0,
expected_x0 - awgn_out);
if (expected_x0 - awgn_out > largest_error) begin
largest_error = expected_x0 - awgn_out;
end
end else begin
tests_passed = tests_passed + 1;
end
#5 clk = 0;
#5 clk = 1;
if (expected_x1 != awgn_out) begin
$display($time, ": x1 was %d when %d was expected (%d)", awgn_out, expected_x1,
expected_x1 - awgn_out);
if (expected_x1 - awgn_out > largest_error) begin
largest_error = expected_x1 - awgn_out;
end
end else begin
tests_passed = tests_passed + 1;
end
if (largest_error > 1) begin
$finish;
end
#5 clk = 0;
end
$display("%d / %d Tests Passed", tests_passed, num_tests);
$display("Largest error was %d", largest_error);
$finish;
end
endmodule
| 6.50439 |
module AWGN_tb ();
wire signed [15:0] x0;
wire signed [15:0] x1;
reg clk;
reg reset;
reg [31:0] urng_seed1;
reg [31:0] urng_seed2;
reg [31:0] urng_seed3;
reg [31:0] urng_seed4;
reg [31:0] urng_seed5;
reg [31:0] urng_seed6;
reg signed [15:0] expected_x0;
reg signed [15:0] expected_x1;
AWGN dut (
x0,
x1,
clk,
reset,
urng_seed1,
urng_seed2,
urng_seed3,
urng_seed4,
urng_seed5,
urng_seed6
);
integer x0_fd;
integer x1_fd;
integer status;
integer num_tests;
integer tests_passed;
integer largest_error;
initial begin
x0_fd = $fopen("../../../../MATLAB/x0.txt", "r");
if (x0_fd == 0) begin
$display("Failed to open x0.txt");
$finish;
end
x1_fd = $fopen("../../../../MATLAB/x1.txt", "r");
if (x1_fd == 0) begin
$display("Failed to open x1.txt");
$finish;
end
urng_seed1 = 64650448;
urng_seed2 = 83372788;
urng_seed3 = 21948290;
urng_seed4 = 64504248;
urng_seed5 = 8337978;
urng_seed6 = 21948180;
reset = 0;
clk = 0;
num_tests = 0;
tests_passed = 0;
largest_error = 0;
#2 reset = 1;
#2 reset = 0;
end
always begin
while (!$feof(
x1_fd
) && !$feof(
x0_fd
)) begin
#5 clk = 1;
num_tests = num_tests + 2;
status = $fscanf(x0_fd, "%d\n", expected_x0);
status = $fscanf(x1_fd, "%d\n", expected_x1);
if (expected_x0 != x0) begin
$display($time, ": x0 was %d when %d was expected (%d)", x0, expected_x0, expected_x0 - x0);
if (expected_x0 - x0 > largest_error) begin
largest_error = expected_x0 - x0;
end
end else begin
tests_passed = tests_passed + 1;
end
if (expected_x1 != x1) begin
$display($time, ": x1 was %d when %d was expected (%d)", x1, expected_x1, expected_x1 - x1);
if (expected_x1 - x1 > largest_error) begin
largest_error = expected_x1 - x1;
end
end else begin
tests_passed = tests_passed + 1;
end
if (largest_error > 1) begin
$finish;
end
#5 clk = 0;
end
$display("%d / %d Tests Passed", tests_passed, num_tests);
$display("Largest error was %d", largest_error);
$finish;
end
endmodule
| 7.243143 |
module controls ADC and four DPs via SPI interface. This module is interfaced with processing system 7 via a AXI GPIO with 2 channels ctri_i and ctrl_o.
// ctrl_i delivers four channel ADC values to processing system 7. Each ADC value is actually of 12bit but the value is packed as 8bit in ctrl_i.
// The four 8bit values packed in the ctrl_i are rudder control, main engine control, sub engine control, and rudder angle indication:
//
// ctrl_i = | rudder c | main eng | sub eng | rudder i|
// MSB LSB
//
// The values of ctrl_o is to be sat at each digital potentiometers (DPs). The bit layout is the same as ctrl_i.
//
// ctrl_o = | rudder c | main eng | sub eng | rudder i|
// MSB LSB
//
// The filter f_aws1_ctrl of aws switches contrl source between remote controller connected to ADC and aws.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module awsctrl(
ctrl_val,
sclk,
sdi,
sdo,
cs_n,
rst_n,
);
input [23:0] ctrl_val;
input sclk;
input sdi;
output sdo;
output [2:0] cs_n;
input rst_n;
wire [2:0] s_sdo;
reg [2:0] r_se;
reg [3:0] r_cnt;
dp_set dp_set_0(.rst_n(rst_n),
.se(r_se[0]),
.vec(ctrl_val[7:0]),
.sclk(sclk),
.sdo(s_sdo[0]),
.cs_n(cs_n[0]));
dp_set dp_set_1(.rst_n(rst_n),
.se(r_se[1]),
.vec(ctrl_val[15:8]),
.sclk(sclk),
.sdo(s_sdo[1]),
.cs_n(cs_n[1]));
dp_set dp_set_2(.rst_n(rst_n),
.se(r_se[2]),
.vec(ctrl_val[23:16]),
.sclk(sclk),
.sdo(s_sdo[2]),
.cs_n(cs_n[2]));
assign sdo = (r_se == 3'b001 ? s_sdo[0] :
(r_se == 3'b010 ? s_sdo[1] :
(r_se == 3'b100 ? s_sdo[2] : 1'b0)));
always @(posedge sclk or negedge rst_n) begin
if (rst_n == 1'b0) begin
r_se <= 3'b001;
r_cnt <= 4'd0;
end else begin
if(r_cnt == 4'd9) begin
r_cnt <= 4'd0;
end else begin
r_cnt <= r_cnt + 4'd1;
end
case(r_se)
3'b001: begin
if(r_cnt == 4'd9) begin
r_se <= 3'b010;
end
end
3'b010: begin
if(r_cnt == 4'd9) begin
r_se <= 3'b100;
end
end
3'b100: begin
if(r_cnt == 4'd9) begin
r_se <= 3'b001;
end
end
endcase
end
end
endmodule
| 7.73348 |
module ax309_mem (
input [13:0] addra,
input clka,
input [ 7:0] dina,
input wea,
output [ 7:0] douta
);
reg [ 7:0] mem [0:16383];
reg [13:0] areg;
reg wreg;
always @(posedge clka) begin
areg <= addra;
wreg <= wea;
if (wreg) mem[areg] <= dina;
end
assign douta = mem[areg];
//
// $readmemh synthezable in XST
// Use inferred block memory instead core generator (work too boring, difficult to change content)
//
initial begin
$readmemh("..\\..\\..\\tst\\rom\\memini.mem", mem, 0, 16383);
end
endmodule
| 7.195711 |
module ax309_mem (
input [12:0] addra,
input clka,
input [15:0] dina,
input wea,
input [ 1:0] byteena,
output [15:0] douta
);
reg [15:0] mem [0:8191];
reg [12:0] areg;
reg [ 1:0] wreg;
always @(posedge clka) begin
areg <= addra;
wreg[0] <= wea & byteena[0];
wreg[1] <= wea & byteena[1];
if (wreg[0]) mem[areg][7:0] <= dina[7:0];
if (wreg[1]) mem[areg][15:8] <= dina[15:8];
end
assign douta = mem[areg];
//
// $readmemh is synthezable in XST
// Use inferred block memory instead core generator
// (work too boring, difficult to change content)
//
initial begin
$readmemh(`CPU_TEST_MEMF, mem, 0, 8191);
end
endmodule
| 7.195711 |
module ax3_pll66 ( // Clock in ports
input inclk0,
// Clock out ports
output c0,
output c1,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(inclk0)
);
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
wire clkfx180;
DCM_SP #(
.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (3),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm_sp_inst
// Input clock
(
.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180(),
.CLKFX (clkfx),
.CLKFX180(clkfx180),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC(1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0)
);
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfb),
.I(clk0)
);
BUFG clkout1_buf (
.O(c0),
.I(clkfx)
);
BUFG clkout2_buf (
.O(c1),
.I(clkfx180)
);
endmodule
| 6.834641 |
module ax3_pll50 ( // Clock in ports
input inclk0,
// Clock out ports
output c0,
output c1,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(inclk0)
);
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
wire clkfx180;
DCM_SP #(
.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm_sp_inst
// Input clock
(
.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180(),
.CLKFX (clkfx),
.CLKFX180(clkfx180),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC(1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0)
);
assign locked = locked_int;
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf (
.O(c0),
.I(clkfx)
);
BUFG clkout2_buf (
.O(c1),
.I(clkfx180)
);
endmodule
| 6.797378 |
module ALU(out, in1, in2, op);
parameter BITS = 16;
output reg [BITS-1:0] out;
input `REGSIZE in1, in2;
input `OPERATION_BITS op;
reg `REGSIZE a;
reg `REGSIZE temp;
always @(in1 or in2 or op) begin #1
case(op)
`OPadd: begin out <= in1 + in2; end
`OPsub: begin out <= in1 - in2; end
`OPxor: begin out <= in1 ^ in2; end
`OPshr: begin out <= in1 >> in2; end
`OPor: begin out <= in1 | in2; end
`OPand: begin out <= in1 & in2; end
endcase
end
endmodule
| 6.767782 |
module AXA3 (
A,
B,
Cin,
Cout,
Sum
);
input A, B, Cin;
output Cout, Sum;
wire w1, w2, Vdd, Gnd;
assign Vdd = 1;
assign Gnd = 0;
pmos (w1, Vdd, A);
pmos (w2, w1, B);
nmos (w2, A, B);
nmos (w2, B, A);
nmos (Sum, Cin, w2);
pmos (Sum, Gnd, w2);
pmos (Cout, Cin, w2);
nmos (Cout, A, w2);
endmodule
| 6.788848 |
module ha (
input A,
B,
output S,
C
);
xor (S, A, B);
and (C, A, B);
endmodule
| 7.857591 |
module fa (
input A,
B,
Cin,
output Cout,
S
);
wire s1, c1, c2;
ha HA1 (
A,
B,
s1,
c1
);
ha HA2 (
s1,
Cin,
S,
c2
);
or OG1 (Cout, c1, c2);
endmodule
| 7.001699 |
module PREFIX_rd_fifo (
PORTS
);
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
port RGROUP_AXI_R;
input [DATA_BITS-1:0] HRDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input [ID_BITS-1:0] cmd_id;
input cmd_err;
input rdata_phase;
output rdata_ready;
input data_last;
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
reg RVALID;
reg [LOG2(CMD_DEPTH):0] burst_cnt;
wire axi_last;
wire ahb_last;
wire [ 1:0] cmd_resp;
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
assign rdata_ready = burst_cnt < 'd2;
assign data_push = rdata_phase & HREADY;
assign data_pop = RVALID & RREADY;
assign axi_last = RVALID & RREADY & RLAST;
assign ahb_last = rdata_phase & data_last;
always @(posedge clk or posedge reset)
if (reset) burst_cnt <= #FFD 'd0;
else if (axi_last | ahb_last) burst_cnt <= #FFD burst_cnt - axi_last + ahb_last;
prgen_fifo #(DATA_BITS + ID_BITS + 2 + 1, FIFO_LINES) data_fifo (
.clk (clk),
.reset(reset),
.push (data_push),
.pop (data_pop),
.din ({HRDATA, cmd_id, cmd_resp, ahb_last}),
.dout ({RDATA, RID, RRESP, RLAST}),
.empty(data_empty),
.full (data_full)
);
always @(posedge clk or posedge reset)
if (reset) RVALID <= #FFD 1'b0;
else if (axi_last) RVALID <= #FFD 1'b0;
else if (burst_cnt > 'd0) RVALID <= #FFD 1'b1;
else RVALID <= #FFD 1'b0;
endmodule
| 6.868724 |
module PREFIX_wr_fifo (
PORTS
);
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
port WGROUP_AXI_W;
port BGROUP_AXI_B;
output [DATA_BITS-1:0] HWDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input cmd_err;
input wdata_phase;
output wdata_ready;
input data_last;
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
wire resp_push;
wire resp_pop;
wire resp_empty;
wire resp_full;
reg [LOG2(CMD_DEPTH):0] burst_cnt;
wire burst_full;
wire axi_last;
wire ahb_last;
wire [ 1:0] cmd_resp;
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
assign wdata_ready = burst_cnt > 'd0;
assign WREADY = (~data_full) & (~burst_full);
assign data_push = WVALID & WREADY;
assign data_pop = wdata_phase & HREADY;
assign axi_last = WVALID & WREADY & WLAST;
assign ahb_last = wdata_phase & data_last;
assign burst_full = burst_cnt == {EXPR(LOG2(CMD_DEPTH) + 1) {1'b1}};
always @(posedge clk or posedge reset)
if (reset) burst_cnt <= #FFD 'd0;
else if (axi_last | ahb_last) burst_cnt <= #FFD burst_cnt + axi_last - ahb_last;
prgen_fifo #(DATA_BITS, FIFO_LINES) data_fifo (
.clk (clk),
.reset(reset),
.push (data_push),
.pop (data_pop),
.din ({WDATA}),
.dout ({HWDATA}),
.empty(data_empty),
.full (data_full)
);
assign resp_push = ahb_last;
assign resp_pop = BVALID & BREADY;
assign BVALID = (~resp_empty);
prgen_fifo #(2 + ID_BITS, CMD_DEPTH) resp_fifo (
.clk (clk),
.reset(reset),
.push (resp_push),
.pop (resp_pop),
.din ({cmd_resp, WID}),
.dout ({BRESP, BID}),
.empty(resp_empty),
.full (resp_full)
);
endmodule
| 7.16953 |
module PREFIX_mux (PORTS);
input clk;
input reset;
input [ADDR_BITS-1:0] cmd_addr;
input psel;
output [31:0] prdata;
output pready;
output pslverr;
output pselSX;
input preadySX;
input pslverrSX;
input [31:0] prdataSX;
parameter ADDR_MSB = EXPR(ADDR_BITS-1);
parameter ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);
reg pready;
reg pslverr_pre;
reg pslverr;
reg [31:0] prdata_pre;
reg [31:0] prdata;
reg [SLV_BITS-1:0] slave_num;
always @(*)
begin
casex (cmd_addr[ADDR_MSB:ADDR_LSB])
DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;
default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
endcase
end
assign pselSX = psel & (slave_num == SLV_BITS'dSX);
always @(*)
begin
case (slave_num)
SLV_BITS'dSX: pready = preadySX;
default : pready = 1'b1; //decode error
endcase
end
always @(*)
begin
case (slave_num)
SLV_BITS'dSX: pslverr_pre = pslverrSX;
default : pslverr_pre = 1'b1; //decode error
endcase
end
always @(*)
begin
case (slave_num)
SLV_BITS'dSX: prdata_pre = prdataSX;
default : prdata_pre = {32{1'b0}};
endcase
end
always @(posedge clk or posedge reset)
if (reset)
begin
prdata <= #FFD {32{1'b0}};
pslverr <= #FFD 1'b0;
end
else if (psel & pready)
begin
prdata <= #FFD prdata_pre;
pslverr <= #FFD pslverr_pre;
end
else if (~psel)
begin
prdata <= #FFD {32{1'b0}};
pslverr <= #FFD 1'b0;
end
endmodule
| 7.026796 |
module iob2axi #(
parameter AXI_ADDR_W = ADDR_W,
parameter AXI_DATA_W = DATA_W
) (
`include "s_axi_s_port.vh"
`include "m_axi_m_port.vh"
`include "iob_gen_if.vh"
);
`IOB_WIRE2WIRE(s_axi_awid, m_axi_awid, 1) //Address write channel ID
`IOB_WIRE2WIRE(s_axi_awaddr, m_axi_awaddr, AXI_ADDR_W) //Address write channel address
`IOB_WIRE2WIRE(s_axi_awlen, m_axi_awlen, 8) //Address write channel burst length
`IOB_WIRE2WIRE(
s_axi_awsize, m_axi_awsize,
3) //Address write channel burst size. This signal indicates the size of each transfer in the burst
`IOB_WIRE2WIRE(s_axi_awburst, m_axi_awburst, 2) //Address write channel burst type
`IOB_WIRE2WIRE(s_axi_awlock, m_axi_awlock, 1) //Address write channel lock type
`IOB_WIRE2WIRE(
s_axi_awcache, m_axi_awcache,
4) //Address write channel memory type. Transactions set with Normal Non-cacheable Modifiable and Bufferable (0011).
`IOB_WIRE2WIRE(
s_axi_awprot, m_axi_awprot,
3) //Address write channel protection type. Transactions set with Normal, Secure, and Data attributes (000).
`IOB_WIRE2WIRE(s_axi_awqos, m_axi_awqos, 4) //Address write channel quality of service
`IOB_WIRE2WIRE(s_axi_awvalid, m_axi_awvalid, 1) //Address write channel valid
`IOB_WIRE2WIRE(m_axi_awready, s_axi_awready, 1) //Address write channel ready
`IOB_WIRE2WIRE(s_axi_wid, m_axi_wid, 1) //Write channel ID
`IOB_WIRE2WIRE(s_axi_wdata, m_axi_wdata, AXI_DATA_W) //Write channel data
`IOB_WIRE2WIRE(s_axi_wstrb, m_axi_wstrb, (AXI_DATA_W / 8)) //Write channel write strobe
`IOB_WIRE2WIRE(s_axi_wlast, m_axi_wlast, 1) //Write channel last word flag
`IOB_WIRE2WIRE(s_axi_wvalid, m_axi_wvalid, 1) //Write channel valid
`IOB_WIRE2WIRE(m_axi_wready, s_axi_wready, 1) //Write channel ready
`IOB_WIRE2WIRE(m_axi_bid, s_axi_bid, 1) //Write response channel ID
`IOB_WIRE2WIRE(m_axi_bresp, s_axi_bresp, 2) //Write response channel response
`IOB_WIRE2WIRE(m_axi_bvalid, s_axi_bvalid, 1) //Write response channel valid
`IOB_WIRE2WIRE(s_axi_bready, m_axi_bready, 1) //Write response channel ready
`IOB_WIRE2WIRE(s_axi_arid, m_axi_arid, 1) //Address read channel ID
`IOB_WIRE2WIRE(s_axi_araddr, m_axi_araddr, AXI_ADDR_W) //Address read channel address
`IOB_WIRE2WIRE(s_axi_arlen, m_axi_arlen, 8) //Address read channel burst length
`IOB_WIRE2WIRE(
s_axi_arsize, m_axi_arsize,
3) //Address read channel burst size. This signal indicates the size of each transfer in the burst
`IOB_WIRE2WIRE(s_axi_arburst, m_axi_arburst, 2) //Address read channel burst type
`IOB_WIRE2WIRE(s_axi_arlock, m_axi_arlock, 1) //Address read channel lock type
`IOB_WIRE2WIRE(
s_axi_arcache, m_axi_arcache,
4) //Address read channel memory type. Transactions set with Normal Non-cacheable Modifiable and Bufferable (0011).
`IOB_WIRE2WIRE(
s_axi_arprot, m_axi_arprot,
3) //Address read channel protection type. Transactions set with Normal, Secure, and Data attributes (000).
`IOB_WIRE2WIRE(s_axi_arqos, m_axi_arqos, 4) //Address read channel quality of service
`IOB_WIRE2WIRE(s_axi_arvalid, m_axi_arvalid, 1) //Address read channel valid
`IOB_WIRE2WIRE(m_axi_arready, s_axi_arready, 1) //Address read channel ready
`IOB_WIRE2WIRE(m_axi_rid, s_axi_rid, 1) //Read channel ID
`IOB_WIRE2WIRE(m_axi_rdata, s_axi_rdata, AXI_DATA_W) //Read channel data
`IOB_WIRE2WIRE(m_axi_rresp, s_axi_rresp, 2) //Read channel response
`IOB_WIRE2WIRE(m_axi_rlast, s_axi_rlast, 1) //Read channel last word
`IOB_WIRE2WIRE(m_axi_rvalid, s_axi_rvalid, 1) //Read channel valid
`IOB_WIRE2WIRE(s_axi_rready, m_axi_rready, 1) //Read channel ready
endmodule
| 8.122056 |
module axi2bram (
input wire RESETn,
input wire CLK,
input wire [7:0] TDATA,
input wire TVALID,
input wire TLAST,
output reg TREADY,
output reg [4:0] R,
output reg [4:0] G,
output reg [4:0] B,
output reg [18:0] index,
output wire valid
);
reg toggle;
//for verif
reg [7:0] data1, data2;
reg we = 0;
assign valid = we;
initial begin
R = 0;
B = 0;
G = 0;
index = 0;
toggle = 0;
we = 0;
TREADY = 1;
end
always @(posedge CLK /*or negedge RESETn*/) begin
if (~RESETn) begin
R <= 0;
B <= 0;
G <= 0;
//index <= 0;
//toggle <= 0;
we <= 0;
end else begin
if (TVALID & TREADY) begin
//index <= (we) ? index + 1:index;
if (~toggle) begin
R[4:0] <= TDATA[7:3];
G[4:2] <= TDATA[2:0];
TREADY <= 1;
we <= 0;
data1 <= TDATA[7:0];
end else begin
G[1:0] <= TDATA[7:6];
B[4:0] <= TDATA[4:0];
TREADY <= 1;
we <= 1;
data2 <= TDATA[7:0];
end
end else begin
//R <= 0;
//B <= 0;
//G <= 0;
TREADY <= 1;
we <= 0;
end
end
end
/*
always @(TDATA or RESETn) begin
if(~RESETn) toggle = 0;
else if(TVALID) toggle = ~toggle;
end
*/
always @(posedge CLK) begin
if (~RESETn) toggle <= 0;
else if (TREADY & TVALID) toggle <= ~toggle;
end
always @(posedge CLK) begin
if (~RESETn) index <= 0;
//else if(index > 307199) index <= 0;
else if (index > 307199) index <= 0;
else if (we) begin
index <= index + 1;
end
end
endmodule
| 7.79679 |
module AXI2VGA (
input ACLK,
input ARESTN,
input [7:0] TDATA,
input TSTRB,
input TLAST,
input TVALID,
input TUSER,
output TREADY,
output reg H_SYNC,
output reg V_SYNC,
output DATA_EN,
output [7:0] pixel
);
// wire [7:0] pixel;
// reg H_SYNC, V_SYNC, DATA_EN;
assign TREADY = 1'b1;
assign pixel = TDATA;
always @(*) begin
if (~ARESTN) V_SYNC = 1'b0;
else begin
if (TVALID == 1'b1) V_SYNC = ~TUSER;
else V_SYNC = V_SYNC;
end
end
always @(*) begin
if (~ARESTN) H_SYNC = 1'b0;
else begin
if (TVALID == 1'b1) H_SYNC = ~TLAST;
else H_SYNC = H_SYNC;
end
end
assign DATA_EN = TVALID;
// always
// DATA_EN = H_SYNC & V_SYNC;
endmodule
| 6.974086 |
module AXI4_LITE (
inout [31:0] data, //data from rx to file register
output reg wr_rd_en,
output reg [31:0] add,
// Global Signals
input ACLK,
ARESETN,
//Read Address Channel
input [31:0] ARADDR,
input ARVALID,
output reg ARREADY,
//Read Data Channel
input RREADY,
output reg [31:0] RDATA,
output reg RRESP,
RVALID,
//Write Address Channel
input [31:0] AWADDR,
input AWVALID,
output reg AWREADY,
//Write Data Channel
input [31:0] WDATA,
input [3:0] WSTRB,
input WVALID,
output reg WREADY,
//Write Response Channel
input BREADY,
output reg BRESP,
BVALID
);
reg [31:0] data1;
assign data = data1;
//--------------------------------------------------------------
always @(posedge ACLK, negedge ARESETN) begin
//---Rest
if (ARESETN == 0) begin
wr_rd_en <= 1'bz;
add <= 32'b0;
ARREADY <= 0;
RDATA <= 32'b0;
RRESP <= 0;
RVALID <= 0;
AWREADY <= 0;
BRESP <= 0;
BVALID <= 0;
WREADY <= 0;
data1 <= 32'b0;
end //---READ Transaction
else if (ARVALID) begin
add <= ARADDR;
ARREADY <= 0;
wr_rd_en <= 1;
RDATA <= data;
wait (RDATA && RREADY) begin
RVALID <= 1;
ARREADY <= 1;
end
end //---WRITE Transaction
else if (AWVALID && BREADY && WVALID) begin
add <= ARADDR;
wr_rd_en <= 0;
case (WSTRB)
4'b0000: data1 <= 32'b0;
4'b0001: data1 = WDATA[7:0];
4'b0010: data1 = WDATA[15:8];
4'b0011: data1 = WDATA[15:0];
4'b0100: data1 = WDATA[23:16];
4'b0101: data1 = {8'b0, WDATA[23:16], 8'b0, WDATA[7:0]};
endcase
wait ((AWVALID || WVALID) && BREADY == 0) begin
BVALID <= 1;
#10 BVALID <= 0;
end
end else begin
wr_rd_en <= wr_rd_en;
add <= add;
ARREADY <= ARREADY;
RDATA <= RDATA;
RRESP <= RRESP;
RVALID <= RVALID;
AWREADY <= AWREADY;
BRESP <= BRESP;
BVALID <= BVALID;
WREADY <= WREADY;
end
end
endmodule
| 6.851971 |
module AXI4_LITE (
inout [31:0] data, //data from rx to file register
output reg wr_en,
rd_en,
output reg [31:0] add,
// Global Signals
input ACLK,
ARESETN,
//Read Address Channel
input [31:0] ARADDR,
input ARVALID,
output reg ARREADY,
//Read Data Channel
input RREADY,
output reg [31:0] RDATA,
output reg RRESP,
RVALID,
//Write Address Channel
input [31:0] AWADDR,
input AWVALID,
output reg AWREADY,
//Write Data Channel
input [31:0] WDATA,
input [3:0] WSTRB,
input WVALID,
output reg WREADY,
//Write Response Channel
input BREADY,
output reg BRESP,
BVALID
);
reg [31:0] data1;
assign data = data1;
//--------------------------------------------------------------
always @(posedge ACLK) begin
//---Rest
if (ARESETN == 0) begin
wr_en <= 0;
rd_en <= 0;
add <= 32'b0;
ARREADY <= 0;
RDATA <= 32'b0;
RRESP <= 0;
RVALID <= 0;
AWREADY <= 0;
BRESP <= 0;
BVALID <= 0;
WREADY <= 0;
data1 <= 32'b0;
end //---READ Transaction
else if (ARVALID) begin
add <= ARADDR;
ARREADY <= 0;
rd_en <= 1;
wr_en <= 0;
RDATA <= data;
if (RDATA && RREADY) begin
RVALID <= 1;
ARREADY <= 1;
end
end //---WRITE Transaction
else if (AWVALID && BREADY && WVALID) begin
add <= ARADDR;
wr_en <= 1;
rd_en <= 0;
case (WSTRB)
4'b0000: data1 <= 32'b0;
4'b0001: data1 <= WDATA[7:0];
4'b0010: data1 <= WDATA[15:8];
4'b0011: data1 <= WDATA[15:0];
4'b0100: data1 <= WDATA[23:16];
4'b0101: data1 <= {8'b0, WDATA[23:16], 8'b0, WDATA[7:0]};
4'b0110: data1 <= {8'b0, WDATA[23:16], WDATA[15:8], 8'b0};
4'b0111: data1 <= {8'b0, WDATA[23:16], WDATA[15:8], WDATA[7:0]};
4'b1000: data1 <= {WDATA[31:24], 8'b0, 8'b0, 8'b0};
4'b1001: data1 <= {WDATA[31:24], 8'b0, 8'b0, WDATA[7:0]};
4'b1010: data1 <= {WDATA[31:24], 8'b0, WDATA[15:8], 8'b0};
4'b1011: data1 <= {WDATA[31:24], 8'b0, WDATA[15:8], WDATA[7:0]};
4'b1111: data1 <= WDATA;
endcase
if ((AWVALID || WVALID) && BREADY == 0) begin
BVALID <= 1;
end
end //--------------------------------
else begin
wr_en <= wr_en;
rd_en <= rd_en;
add <= add;
ARREADY <= ARREADY;
RDATA <= RDATA;
RRESP <= RRESP;
RVALID <= RVALID;
AWREADY <= AWREADY;
BRESP <= BRESP;
BVALID <= BVALID;
WREADY <= WREADY;
end
end
endmodule
| 6.851971 |
module axi4_lite_slave #(
parameter ADDR_WIDTH = 8,
parameter ADDR_WIDTH_SLAVE = 5,
parameter DATA_WIDTH = 32,
parameter STRB_WIDTH = DATA_WIDTH / 8,
parameter AXI_SLAVE_ADDR = 3'b000
) (
input reset,
input clk,
//write address channel
input awvalid,
output reg awready,
input [ 1:0] awprot,
input [ ADDR_WIDTH-1:0] awaddr,
//write data channel
input wrvalid,
output reg wrready,
input [ STRB_WIDTH-1:0] wrstrb,
input [ DATA_WIDTH-1:0] wrdata,
//write response channel
input bready,
output reg bvalid,
output reg [ 1:0] bresp,
//read address channel
input arvalid,
output reg arready,
input [ ADDR_WIDTH-1:0] araddr,
input [ 1:0] arprot,
//read data channel
output reg [ DATA_WIDTH-1:0] rdata,
input rready,
output reg rvalid,
output reg [ 2:0] rresp,
//reg file interface
output reg rfwrcmd,
output reg rfrdcmd,
output reg [ADDR_WIDTH_SLAVE-1:0] rfrdaddr,
output reg [ADDR_WIDTH_SLAVE-1:0] rfwraddr,
output reg [ (DATA_WIDTH)-1:0] rfwrdata,
input [ (DATA_WIDTH)-1:0] rfrddata,
input rf_busy,
output reg slave_need_rf,
input rf_data_valid
);
localparam idle = 3'b000, write1 = 3'b001, write2 = 3'b010, read1 = 3'b100, read2 = 3'b101;
reg [2:0] statereg;
reg [DATA_WIDTH-1:0] datareg;
always @(posedge clk) begin
if (reset) begin
statereg <= idle;
end else begin
case (statereg)
idle: begin
bvalid <= 0;
wrready <= 1'b0;
arready <= 1'b0;
rdata <= 0;
rfrdaddr <= 1'b0;
rfwraddr <= 1'b0;
rvalid <= 1'b0;
rresp <= 2'b00;
awready <= 1'b0;
bresp <= 2'b00;
rfwrcmd <= 1'b0;
rfrdcmd <= 0;
rfwrdata <= 0;
statereg <= idle;
slave_need_rf <= 1'b0;
if (awvalid) begin
if (awaddr[7:5] == AXI_SLAVE_ADDR) begin
statereg <= write1;
rfwraddr <= awaddr[4:0];
awready <= 1'b1;
slave_need_rf <= 1'b1;
end
end
if (arvalid) begin
if (araddr[7:5] == AXI_SLAVE_ADDR) begin
statereg <= read1;
rfrdaddr <= araddr[4:0];
rfrdcmd <= 1'b1;
arready <= 1'b1;
slave_need_rf <= 1'b1;
end
end
end
read1: begin
arready <= 1'b0;
if (~rf_busy) begin
rfrdcmd <= 1'b0;
if (rf_data_valid) begin
rdata <= rfrddata;
rvalid <= 1'b1;
rresp <= 2'b00;
statereg <= read2;
slave_need_rf <= 1'b0;
end
end
end
read2: begin
if (rready) begin
rvalid <= 1'b0;
statereg <= idle;
end
end
write1: begin
awready <= 1'b0;
if (wrvalid) begin
wrready <= 1'b1;
rfwrdata <= wrdata;
statereg <= write2;
if (~rf_busy) begin
rfwrcmd <= 1'b1;
bresp <= 2'b00;
bvalid <= 1'b1;
end
end
end
write2: begin
rfwrcmd <= 1'b0;
wrready <= 1'b0;
bvalid <= 1'b1;
slave_need_rf <= 1'b0;
if (bready) begin
statereg <= idle;
bvalid <= 1'b0;
end
end
endcase
end
end
endmodule
| 7.522589 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input [11:0] io_push_payload_addr,
input [2:0] io_push_payload_prot,
output reg io_pop_valid,
input io_pop_ready,
output reg [11:0] io_pop_payload_addr,
output reg [2:0] io_pop_payload_prot,
input io_flush,
output [0:0] io_occupancy,
input S_AXI_ACLK,
input S_AXI_ARESETN
);
wire _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [14:0] _zz_2_;
wire [14:0] _zz_3_;
reg [14:0] _zz_4_;
assign _zz_5_ = (!empty);
always @(*) begin
_zz_1_ = 1'b0;
if (pushing) begin
_zz_1_ = 1'b1;
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
always @(*) begin
if (_zz_5_) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign _zz_2_ = _zz_3_;
always @(*) begin
if (_zz_5_) begin
io_pop_payload_addr = _zz_2_[11 : 0];
end else begin
io_pop_payload_addr = io_push_payload_addr;
end
end
always @(*) begin
if (_zz_5_) begin
io_pop_payload_prot = _zz_2_[14 : 12];
end else begin
io_pop_payload_prot = io_push_payload_prot;
end
end
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
risingOccupancy <= 1'b0;
end else begin
if ((pushing != popping)) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (_zz_1_) begin
_zz_4_ <= {io_push_payload_prot, io_push_payload_addr};
end
end
endmodule
| 7.046487 |
module StreamFifoLowLatency_1_ (
input io_push_valid,
output io_push_ready,
input [31:0] io_push_payload_data,
input [3:0] io_push_payload_strobe,
output reg io_pop_valid,
input io_pop_ready,
output reg [31:0] io_pop_payload_data,
output reg [3:0] io_pop_payload_strobe,
input io_flush,
output [0:0] io_occupancy,
input S_AXI_ACLK,
input S_AXI_ARESETN
);
wire _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [35:0] _zz_2_;
wire [35:0] _zz_3_;
reg [35:0] _zz_4_;
assign _zz_5_ = (!empty);
always @(*) begin
_zz_1_ = 1'b0;
if (pushing) begin
_zz_1_ = 1'b1;
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
always @(*) begin
if (_zz_5_) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign _zz_2_ = _zz_3_;
always @(*) begin
if (_zz_5_) begin
io_pop_payload_data = _zz_2_[31 : 0];
end else begin
io_pop_payload_data = io_push_payload_data;
end
end
always @(*) begin
if (_zz_5_) begin
io_pop_payload_strobe = _zz_2_[35 : 32];
end else begin
io_pop_payload_strobe = io_push_payload_strobe;
end
end
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
risingOccupancy <= 1'b0;
end else begin
if ((pushing != popping)) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (_zz_1_) begin
_zz_4_ <= {io_push_payload_strobe, io_push_payload_data};
end
end
endmodule
| 7.046487 |
module StreamFifo (
input io_push_valid,
output io_push_ready,
input [1:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [1:0] io_pop_payload,
input io_flush,
output [0:0] io_occupancy,
output [0:0] io_availability,
input S_AXI_ACLK,
input S_AXI_ARESETN
);
wire io_push_m2sPipe_valid;
wire io_push_m2sPipe_ready;
wire [1:0] io_push_m2sPipe_payload;
reg _zz_1_;
reg [1:0] _zz_2_;
assign io_push_ready = ((1'b1 && (!io_push_m2sPipe_valid)) || io_push_m2sPipe_ready);
assign io_push_m2sPipe_valid = _zz_1_;
assign io_push_m2sPipe_payload = _zz_2_;
assign io_pop_valid = io_push_m2sPipe_valid;
assign io_push_m2sPipe_ready = io_pop_ready;
assign io_pop_payload = io_push_m2sPipe_payload;
assign io_occupancy = io_pop_valid;
assign io_availability = (!io_pop_valid);
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
_zz_1_ <= 1'b0;
end else begin
if (io_push_ready) begin
_zz_1_ <= io_push_valid;
end
if (io_flush) begin
_zz_1_ <= 1'b0;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (io_push_ready) begin
_zz_2_ <= io_push_payload;
end
end
endmodule
| 7.784627 |
module StreamFifo_1_ (
input io_push_valid,
output io_push_ready,
input [31:0] io_push_payload_data,
input [1:0] io_push_payload_resp,
output io_pop_valid,
input io_pop_ready,
output [31:0] io_pop_payload_data,
output [1:0] io_pop_payload_resp,
input io_flush,
output [0:0] io_occupancy,
output [0:0] io_availability,
input S_AXI_ACLK,
input S_AXI_ARESETN
);
wire io_push_m2sPipe_valid;
wire io_push_m2sPipe_ready;
wire [31:0] io_push_m2sPipe_payload_data;
wire [1:0] io_push_m2sPipe_payload_resp;
reg _zz_1_;
reg [31:0] _zz_2_;
reg [1:0] _zz_3_;
assign io_push_ready = ((1'b1 && (!io_push_m2sPipe_valid)) || io_push_m2sPipe_ready);
assign io_push_m2sPipe_valid = _zz_1_;
assign io_push_m2sPipe_payload_data = _zz_2_;
assign io_push_m2sPipe_payload_resp = _zz_3_;
assign io_pop_valid = io_push_m2sPipe_valid;
assign io_push_m2sPipe_ready = io_pop_ready;
assign io_pop_payload_data = io_push_m2sPipe_payload_data;
assign io_pop_payload_resp = io_push_m2sPipe_payload_resp;
assign io_occupancy = io_pop_valid;
assign io_availability = (!io_pop_valid);
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
_zz_1_ <= 1'b0;
end else begin
if (io_push_ready) begin
_zz_1_ <= io_push_valid;
end
if (io_flush) begin
_zz_1_ <= 1'b0;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (io_push_ready) begin
_zz_2_ <= io_push_payload_data;
_zz_3_ <= io_push_payload_resp;
end
end
endmodule
| 7.097915 |
module axi4mm_register_slice_wrap #(
parameter C_AXI_ID_WIDTH = 4
) (
input wire aclk,
input wire aresetn,
output wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid,
output wire [ 255 : 0] s_axi_rdata,
output wire [ 1 : 0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
input wire [ 3 : 0] m_axi_rid,
input wire [ 255 : 0] m_axi_rdata,
input wire [ 1 : 0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
assign s_axi_rid = {C_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = 256'b0;
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
endmodule
| 8.357672 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [15:0] io_axi_arw_payload_addr,
input [ 3:0] io_axi_arw_payload_id,
input [ 3:0] io_axi_arw_payload_region,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 1:0] io_axi_arw_payload_burst,
input [ 0:0] io_axi_arw_payload_lock,
input [ 3:0] io_axi_arw_payload_cache,
input [ 3:0] io_axi_arw_payload_qos,
input [ 2:0] io_axi_arw_payload_prot,
input io_axi_arw_payload_write,
input io_axi_w_valid,
output io_axi_w_ready,
input [31:0] io_axi_w_payload_data,
input [ 3:0] io_axi_w_payload_strb,
input io_axi_w_payload_last,
output io_axi_b_valid,
input io_axi_b_ready,
output [ 3:0] io_axi_b_payload_id,
output [ 1:0] io_axi_b_payload_resp,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 3:0] io_axi_r_payload_id,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input clk,
input reset
);
reg consumeData;
reg sendReadRsp;
reg sendWriteRsp;
reg [3:0] id;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_arw_fire;
wire io_axi_w_fire;
wire when_Axi4ErrorSlave_l92;
wire io_axi_b_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_arw_ready = (!((consumeData || sendWriteRsp) || sendReadRsp));
assign io_axi_arw_fire = (io_axi_arw_valid && io_axi_arw_ready);
assign io_axi_w_ready = consumeData;
assign io_axi_w_fire = (io_axi_w_valid && io_axi_w_ready);
assign when_Axi4ErrorSlave_l92 = (io_axi_w_fire && io_axi_w_payload_last);
assign io_axi_b_valid = sendWriteRsp;
assign io_axi_b_payload_resp = 2'b11;
assign io_axi_b_payload_id = id;
assign io_axi_b_fire = (io_axi_b_valid && io_axi_b_ready);
assign io_axi_r_valid = sendReadRsp;
assign io_axi_r_payload_id = id;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge clk or posedge reset) begin
if (reset) begin
consumeData <= 1'b0;
sendReadRsp <= 1'b0;
sendWriteRsp <= 1'b0;
end else begin
if (io_axi_arw_fire) begin
consumeData <= io_axi_arw_payload_write;
sendReadRsp <= (!io_axi_arw_payload_write);
end
if (when_Axi4ErrorSlave_l92) begin
consumeData <= 1'b0;
sendWriteRsp <= 1'b1;
end
if (io_axi_b_fire) begin
sendWriteRsp <= 1'b0;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendReadRsp <= 1'b0;
end
end
end
end
end
always @(posedge clk) begin
if (io_axi_arw_fire) begin
remaining <= io_axi_arw_payload_len;
id <= io_axi_arw_payload_id;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 6.942764 |
module Axi4SharedSdramCtrlTester_tb (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [24:0] io_axi_arw_payload_addr,
input [1:0] io_axi_arw_payload_id,
input [7:0] io_axi_arw_payload_len,
input [2:0] io_axi_arw_payload_size,
input [1:0] io_axi_arw_payload_burst,
input io_axi_arw_payload_write,
input io_axi_w_valid,
output io_axi_w_ready,
input [31:0] io_axi_w_payload_data,
input [3:0] io_axi_w_payload_strb,
input io_axi_w_payload_last,
output io_axi_b_valid,
input io_axi_b_ready,
output [1:0] io_axi_b_payload_id,
output [1:0] io_axi_b_payload_resp,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [1:0] io_axi_r_payload_id,
output [1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input clk,
input reset
);
wire [12:0] io_sdram_ADDR;
wire [1:0] io_sdram_BA;
wire [15:0] io_sdram_DQ;
wire [15:0] io_sdram_DQ_read;
wire [15:0] io_sdram_DQ_write;
wire io_sdram_DQ_writeEnable;
wire [1:0] io_sdram_DQM;
wire io_sdram_CASn;
wire io_sdram_CKE;
wire io_sdram_CSn;
wire io_sdram_RASn;
wire io_sdram_WEn;
assign io_sdram_DQ_read = io_sdram_DQ;
assign io_sdram_DQ = io_sdram_DQ_writeEnable ? io_sdram_DQ_write : 16'bZZZZZZZZZZZZZZZZ;
mt48lc16m16a2 sdram (
.Dq(io_sdram_DQ),
.Addr(io_sdram_ADDR),
.Ba(io_sdram_BA),
.Clk(clk),
.Cke(io_sdram_CKE),
.Cs_n(io_sdram_CSn),
.Ras_n(io_sdram_RASn),
.Cas_n(io_sdram_CASn),
.We_n(io_sdram_WEn),
.Dqm(io_sdram_DQM)
);
Axi4SharedSdramCtrlTester uut (
.io_sdram_ADDR(io_sdram_ADDR),
.io_sdram_BA(io_sdram_BA),
.io_sdram_DQ_read(io_sdram_DQ_read),
.io_sdram_DQ_write(io_sdram_DQ_write),
.io_sdram_DQ_writeEnable(io_sdram_DQ_writeEnable),
.io_sdram_DQM(io_sdram_DQM),
.io_sdram_CASn(io_sdram_CASn),
.io_sdram_CKE(io_sdram_CKE),
.io_sdram_CSn(io_sdram_CSn),
.io_sdram_RASn(io_sdram_RASn),
.io_sdram_WEn(io_sdram_WEn),
.io_axi_arw_valid(io_axi_arw_valid),
.io_axi_arw_ready(io_axi_arw_ready),
.io_axi_arw_payload_addr(io_axi_arw_payload_addr),
.io_axi_arw_payload_id(io_axi_arw_payload_id),
.io_axi_arw_payload_len(io_axi_arw_payload_len),
.io_axi_arw_payload_size(io_axi_arw_payload_size),
.io_axi_arw_payload_burst(io_axi_arw_payload_burst),
.io_axi_arw_payload_write(io_axi_arw_payload_write),
.io_axi_w_valid(io_axi_w_valid),
.io_axi_w_ready(io_axi_w_ready),
.io_axi_w_payload_data(io_axi_w_payload_data),
.io_axi_w_payload_strb(io_axi_w_payload_strb),
.io_axi_w_payload_last(io_axi_w_payload_last),
.io_axi_b_valid(io_axi_b_valid),
.io_axi_b_ready(io_axi_b_ready),
.io_axi_b_payload_id(io_axi_b_payload_id),
.io_axi_b_payload_resp(io_axi_b_payload_resp),
.io_axi_r_valid(io_axi_r_valid),
.io_axi_r_ready(io_axi_r_ready),
.io_axi_r_payload_data(io_axi_r_payload_data),
.io_axi_r_payload_id(io_axi_r_payload_id),
.io_axi_r_payload_resp(io_axi_r_payload_resp),
.io_axi_r_payload_last(io_axi_r_payload_last),
.clk(clk),
.reset(reset)
);
// initial begin
// $dumpfile("wave.vcd");
// $dumpvars(0, SdramCtrlTester_tb);
//end
endmodule
| 6.869498 |
module axi4_arb_onehot2 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [1:0] request_i
// Outputs
, output [1:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [1:0] req_ffs_masked_w;
wire [1:0] req_ffs_unmasked_w;
wire [1:0] req_ffs_w;
reg [1:0] mask_next_q;
reg [1:0] grant_last_q;
wire [1:0] grant_new_w;
//-----------------------------------------------------------------
// ffs: Find first set
//-----------------------------------------------------------------
function [1:0] ffs;
input [1:0] request;
begin
ffs[0] = request[0];
ffs[1] = ffs[0] | request[1];
end
endfunction
assign req_ffs_masked_w = ffs(request_i & mask_next_q);
assign req_ffs_unmasked_w = ffs(request_i);
assign req_ffs_w = (|req_ffs_masked_w) ? req_ffs_masked_w : req_ffs_unmasked_w;
always @(posedge clk_i)
if (rst_i == 1'b1) begin
mask_next_q <= {2{1'b1}};
grant_last_q <= 2'b0;
end else begin
if (~hold_i) mask_next_q <= {req_ffs_w[0:0], 1'b0};
grant_last_q <= grant_o;
end
assign grant_new_w = req_ffs_w ^ {req_ffs_w[0:0], 1'b0};
assign grant_o = hold_i ? grant_last_q : grant_new_w;
endmodule
| 6.693687 |
module axi4_64_arb_onehot4 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [3:0] request_i
// Outputs
, output [3:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [3:0] req_ffs_masked_w;
wire [3:0] req_ffs_unmasked_w;
wire [3:0] req_ffs_w;
reg [3:0] mask_next_q;
reg [3:0] grant_last_q;
wire [3:0] grant_new_w;
//-----------------------------------------------------------------
// ffs: Find first set
//-----------------------------------------------------------------
function [3:0] ffs;
input [3:0] request;
begin
ffs[0] = request[0];
ffs[1] = ffs[0] | request[1];
ffs[2] = ffs[1] | request[2];
ffs[3] = ffs[2] | request[3];
end
endfunction
assign req_ffs_masked_w = ffs(request_i & mask_next_q);
assign req_ffs_unmasked_w = ffs(request_i);
assign req_ffs_w = (|req_ffs_masked_w) ? req_ffs_masked_w : req_ffs_unmasked_w;
always @(posedge clk_i)
if (rst_i == 1'b1) begin
mask_next_q <= {4{1'b1}};
grant_last_q <= 4'b0;
end else begin
if (~hold_i) mask_next_q <= {req_ffs_w[2:0], 1'b0};
grant_last_q <= grant_o;
end
assign grant_new_w = req_ffs_w ^ {req_ffs_w[2:0], 1'b0};
assign grant_o = hold_i ? grant_last_q : grant_new_w;
endmodule
| 6.983003 |
module axi4_arbiter_r (
input clk,
input rst,
input s0_ARVALID,
input s0_RREADY,
input s1_ARVALID,
input s1_RREADY,
input m_RVALID,
input m_RLAST,
// Bus grant
output [1:0] m_RGRNT
);
localparam [1:0] S_S0 = 2'b01;
localparam [1:0] S_S1 = 2'b10;
wire [1:0] fsm_state_ff;
reg [1:0] fsm_state_nxt;
wire s0_sel;
wire s1_sel;
wire s0_pending, s0_pending_clr;
wire s1_pending, s1_pending_clr;
reg s0_pending_set, s1_pending_set;
always @(*) begin
fsm_state_nxt = fsm_state_ff;
s0_pending_set = 1'b0;
s1_pending_set = 1'b0;
case (fsm_state_ff)
S_S0: begin
if (s0_ARVALID) begin
fsm_state_nxt = S_S0;
s0_pending_set = 1'b1;
end else if (s0_pending & ~s0_pending_clr) fsm_state_nxt = S_S0; // Lock the bus for slave0
else if (s0_pending & s0_pending_clr) fsm_state_nxt = S_S1; // Round-robin
else if (s1_ARVALID) begin
fsm_state_nxt = S_S1;
s1_pending_set = 1'b1;
end else fsm_state_nxt = S_S0;
end
S_S1: begin
if (s1_ARVALID) begin
fsm_state_nxt = S_S1;
s1_pending_set = 1'b1;
end else if (s1_pending & ~s1_pending_clr) fsm_state_nxt = S_S1; // Lock the bus for slave1
else if (s1_pending & s1_pending_clr) fsm_state_nxt = S_S0; // Round-robin
else if (s0_ARVALID) begin
fsm_state_nxt = S_S0;
s0_pending_set = 1'b1;
end else fsm_state_nxt = S_S1;
end
default: fsm_state_nxt = fsm_state_ff;
endcase
end
mDFF_r #(
.DW(2),
.RST_VECTOR(S_S0)
) ff_fsm_state (
.CLK(clk),
.RST(rst),
.D (fsm_state_nxt),
.Q (fsm_state_ff)
);
assign s0_sel = (fsm_state_ff == S_S0);
assign s1_sel = (fsm_state_ff == S_S1);
assign s0_pending_clr = (s0_sel & m_RLAST & m_RVALID & s0_RREADY);
assign s1_pending_clr = (s1_sel & m_RLAST & m_RVALID & s1_RREADY);
mDFF_lr #(
.DW(1)
) s0_pending_ff (
.CLK(clk),
.RST(rst),
.LOAD(s0_pending_set | s0_pending_clr),
.D(s0_pending_set | ~s0_pending_clr),
.Q(s0_pending)
);
mDFF_lr #(
.DW(1)
) s1_pending_ff (
.CLK(clk),
.RST(rst),
.LOAD(s1_pending_set | s1_pending_clr),
.D(s1_pending_set | ~s1_pending_clr),
.Q(s1_pending)
);
assign m_RGRNT = {s1_sel, s0_sel};
endmodule
| 8.128662 |
module axi4_arbiter_w (
input clk,
input rst,
input s0_AWVALID,
input s0_BREADY,
input s1_AWVALID,
input s1_BREADY,
input m_BVALID,
// Bus grant
output [1:0] m_WGRNT
);
localparam [1:0] S_S0 = 2'b01;
localparam [1:0] S_S1 = 2'b10;
wire [1:0] fsm_state_ff;
reg [1:0] fsm_state_nxt;
wire s0_sel;
wire s1_sel;
wire s0_pending, s0_pending_clr;
wire s1_pending, s1_pending_clr;
reg s0_pending_set, s1_pending_set;
always @(*) begin
fsm_state_nxt = fsm_state_ff;
s0_pending_set = 1'b0;
s1_pending_set = 1'b1;
case (fsm_state_ff)
S_S0: begin
if (s0_AWVALID) begin
fsm_state_nxt = S_S0;
s0_pending_set = 1'b1;
end else if (s0_pending & ~s0_pending_clr) fsm_state_nxt = S_S0; // Lock the bus for slave0
else if (s0_pending & s0_pending_clr) fsm_state_nxt = S_S1; // Round-robin
else if (s1_AWVALID) begin
fsm_state_nxt = S_S1;
s1_pending_set = 1'b1;
end else fsm_state_nxt = S_S0;
end
S_S1: begin
if (s1_AWVALID) begin
fsm_state_nxt = S_S1;
s1_pending_set = 1'b1;
end else if (s1_pending & ~s1_pending_clr) fsm_state_nxt = S_S1; // Lock the bus for slave1
else if (s1_pending & s1_pending_clr) fsm_state_nxt = S_S0; // Round-robin
else if (s0_AWVALID) begin
fsm_state_nxt = S_S0;
s0_pending_set = 1'b1;
end else fsm_state_nxt = S_S1;
end
default: fsm_state_nxt = fsm_state_ff;
endcase
end
mDFF_r #(
.DW(2),
.RST_VECTOR(S_S0)
) ff_fsm_state (
.CLK(clk),
.RST(rst),
.D (fsm_state_nxt),
.Q (fsm_state_ff)
);
assign s0_sel = (fsm_state_ff == S_S0);
assign s1_sel = (fsm_state_ff == S_S1);
assign s0_pending_clr = (s0_sel & m_BVALID & s0_BREADY);
assign s1_pending_clr = (s1_sel & m_BVALID & s1_BREADY);
mDFF_lr #(
.DW(1)
) s0_pending_ff (
.CLK(clk),
.RST(rst),
.LOAD(s0_pending_set | s0_pending_clr),
.D(s0_pending_set | ~s0_pending_clr),
.Q(s0_pending)
);
mDFF_lr #(
.DW(1)
) s1_pending_ff (
.CLK(clk),
.RST(rst),
.LOAD(s1_pending_set | s1_pending_clr),
.D(s1_pending_set | ~s1_pending_clr),
.Q(s1_pending)
);
assign m_WGRNT = {s1_sel, s0_sel};
endmodule
| 8.128662 |
module axi4_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers,
axreadym
);
parameter ADDR_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + ADDR_WIDTH + USER_WIDTH + 29;
input aclk;
input aresetn;
input axvalids;
output axreadys;
input [ID_WIDTH-1:0] axids;
input [ADDR_WIDTH-1:0] axaddrs;
input [7:0] axlens;
input [2:0] axsizes;
input [1:0] axbursts;
input axlocks;
input [3:0] axcaches;
input [2:0] axprots;
input [3:0] axregions;
input [3:0] axqoss;
input [USER_WIDTH-1:0] axusers;
output axvalidm;
input axreadym;
output [ID_WIDTH-1:0] axidm;
output [ADDR_WIDTH-1:0] axaddrm;
output [7:0] axlenm;
output [2:0] axsizem;
output [1:0] axburstm;
output axlockm;
output [3:0] axcachem;
output [2:0] axprotm;
output [3:0] axregionm;
output [3:0] axqosm;
output [USER_WIDTH-1:0] axuserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = axvalids;
assign payload_src = {
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers
};
assign axreadys = ready_src;
assign axvalidm = valid_dst;
assign {axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm} = payload_dst;
assign ready_dst = axreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.772393 |
module axi4_brdige (
input clk,
input rst,
//slave
input s_arvalid,
input [31:0] s_araddr,
input [7:0] s_arlen,
output reg s_rvalid,
output reg s_arready,
output reg [511:0] s_rdata,
input ddrWr,
input [31:0] ddrWrAddress,
input ddrWrEn,
input [511:0] ddrWrData,
input ddrWrDataValid,
input [31:0] ddrRdAddr,
input ddrRd,
output ddrRdAddrDone,
output [511:0] ddrRdData,
output ddrRdDataValid,
//master
output reg m_arvalid,
output reg [31:0] m_araddr,
output reg [7:0] m_arlen,
input m_arready,
input m_rvalid,
input [511:0] m_rdata
);
localparam IDLE = 1'b0, WAIT = 1'b1;
reg state;
always @(posedge clk) begin
if (rst) begin
s_arready <= 1'b0;
m_arvalid <= 1'b0;
s_rvalid <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
s_rvalid <= 1'b0;
m_arvalid <= 1'b0;
s_arready <= 1'b0;
if (s_arvalid) begin
m_arvalid <= 1'b1;
m_araddr <= s_araddr;
m_arlen <= s_arlen;
state <= WAIT;
end
end
WAIT: begin
s_arready <= 1'b0;
if (m_arready) begin
s_arready <= 1'b1;
m_arvalid <= 1'b0;
end
if (m_rvalid) begin
s_rdata <= m_rdata;
s_rvalid <= 1'b1;
state <= IDLE;
end
end
endcase
end
end
endmodule
| 7.563781 |
module axi4_lite_master_fsm #
(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter STRB_WIDTH = (DATA_WIDTH/8)
)(
input wire ACLK,
input wire ARESETn,
// WRITE Address Channel
input wire S_AXI_AWREADY,
output wire S_AXI_AWVALID,
output wire [ADDR_WIDTH-1:0] S_AXI_AWADDR,
// WRITE Data Channel
input wire S_AXI_WREADY,
output wire S_AXI_WVALID,
output wire [DATA_WIDTH-1:0] S_AXI_WDATA,
output wire [STRB_WIDTH-1:0] S_AXI_WSTRB,
//WRITE Response Channel
output wire S_AXI_BREADY,
input wire S_AXI_BVALID,
input wire [1:0] S_AXI_BRESP,
// READ Address Channel
// S_AXI_ARPROT
// S_AXI_ARCACHE
input wire S_AXI_ARREADY,
output wire S_AXI_ARVALID,
output wire [ADDR_WIDTH-1:0] S_AXI_ARADDR,
// READ Data Channel
output wire S_AXI_RREADY,
input wire S_AXI_RVALID,
input wire [1:0] S_AXI_RRESP,
input wire [DATA_WIDTH-1:0] S_AXI_RDATA,
input wire START_RD,
input wire START_WR
);
localparam SET_ADDR = 32'h4
localparam SET_OK = 2'b00;
localparam SET_HIGH = 1'b1;
localparam SET_LOW = 1'b0;
localparam S_IDLE = 2'd0,
S_RDATA = 2'd1,
S_RADDR = 2'd2,
S_WADDR = 2'd3,
S_WDATA = 2'd4,
S_WRESP = 2'd5;
//typedef enum logic [2 : 0] {IDLE, RADDR, RDATA, WADDR, WDATA, WRESP} state_type;
reg [3:0] STATE, NEXTSTATE;
reg[ADDR_WIDTH-1 : 0] ADDR = SET_ADDR;
reg[DATA_WIDTH-1 : 0] DATA = 32'hdeadbeef, RDATA;
reg START_READ, START_WRITE;
assign START_READ = START_RD;
assign START_WRITE = START_WR;
// AR
assign S_AXI_ARADDR = (STATE == S_RADDR) ? ADDR : 32'h0;
assign S_AXI_ARVALID = (STATE == S_RADDR) ? 1 : 0;
// R
assign S_AXI_RREADY = (STATE == S_RDATA) ? 1 : 0;
// AW
assign S_AXI_AWVALID = (STATE == S_WADDR) ? 1 : 0;
assign S_AXI_AWADDR = (STATE == S_WADDR) ? ADDR : 32'h0;
// W
assign S_AXI_WVALID = (STATE == S_WDATA) ? 1 : 0;
assign S_AXI_WDATA = (STATE == S_WDATA) ? DATA : 32'h0;
assign S_AXI_WSTRB = 4'b0000;
// B
assign S_AXI_BREADY = (STATE == S_WRESP) ? 1 : 0;
always @(posedge ACLK) begin
if (~areset_n) begin
rdata <= 0;
end else begin
if (state == RDATA) rdata <= m_axi_lite.rdata;
end
end
always @(posedge ACLK) begin
if (!ARESETn) begin
start_read_delay <= 0;
start_write_delay <= 0;
end else begin
start_read_delay <= start_read;
start_write_delay <= start_write;
end
end
always_comb begin
case (state)
S_IDLE : NEXTSTATE = (START_READ) ? RADDR : ((START_WRITE) ? S_WADDR : S_IDLE);
S_RADDR : if ( S_AXI_ARVALID && S_AXI_ARREADY ) NEXTSTATE = S_RDATA;
S_RDATA : if (m_axi_lite.rvalid && m_axi_lite.rready ) NEXTSTATE = S_IDLE;
S_WADDR : if (m_axi_lite.awvalid && m_axi_lite.awready) NEXTSTATE = S_WDATA;
S_WDATA : if (m_axi_lite.wvalid && m_axi_lite.wready ) NEXTSTATE = S_WRESP;
S_WRESP : if (m_axi_lite.bvalid && m_axi_lite.bready ) NEXTSTATE = S_IDLE;
default : NEXTSTATE = S_IDLE;
endcase
end
always @(posedge ACLK) begin
if (!ARESETn) begin
STATE <= S_IDLE;
end else begin
STATE <= NEXTSTATE;
end
end
endmodule
| 8.223194 |
module axi4_lite_slave_fsm #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter STRB_WIDTH = (DATA_WIDTH / 8)
) (
input wire ACLK,
input wire ARESETn,
// WRITE Address Channel
output wire S_AXI_AWREADY,
input wire S_AXI_AWVALID,
input wire [ADDR_WIDTH-1:0] S_AXI_AWADDR,
// WRITE Data Channel
output wire S_AXI_WREADY,
input wire S_AXI_WVALID,
input wire [DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [STRB_WIDTH-1:0] S_AXI_WSTRB,
//WRITE Response Channel
input wire S_AXI_BREADY,
output wire S_AXI_BVALID,
output wire [1:0] S_AXI_BRESP,
// READ Address Channel
// S_AXI_ARPROT
// S_AXI_ARCACHE
output wire S_AXI_ARREADY,
input wire S_AXI_ARVALID,
input wire [ADDR_WIDTH-1:0] S_AXI_ARADDR,
// READ Data Channel
input wire S_AXI_RREADY,
output wire S_AXI_RVALID,
output wire [ 1:0] S_AXI_RRESP,
output wire [DATA_WIDTH-1:0] S_AXI_RDATA
);
localparam SET_OK = 2'b00;
localparam SET_HIGH = 1'b1;
localparam SET_LOW = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] BRAM[(2**6)-1:0];
// WRITE
localparam S_WRIDLE = 2'd0, S_WRDATA = 2'd1, S_WRRESP = 2'd2;
// READ
localparam S_RDIDLE = 2'd0, S_RDDATA = 2'd1;
// WRITE
reg [1:0] WRITE_STATE, NEXT_WRITE_STATE;
reg [ADDR_WIDTH-1:0] WRITE_ADDR;
wire [ADDR_WIDTH-1:0] MASK;
wire ADDR_WRITE_EN, WRITE_EN;
// READ
reg [1:0] READ_STATE, NEXT_READ_STATE;
wire [ADDR_WIDTH-1:0] RADDR;
reg [ADDR_WIDTH-1:0] RDATA;
wire ar_hs;
// WRITE
assign S_AXI_AWREADY = (WRITE_STATE == S_WRIDLE);
assign S_AXI_WREADY = (WRITE_STATE == S_WRDATA);
assign S_AXI_BRESP = SET_OK;
assign S_AXI_BVALID = (WRITE_STATE == S_WRRESP);
assign MASK = {
{8{S_AXI_WSTRB[3]}}, {8{S_AXI_WSTRB[2]}}, {8{S_AXI_WSTRB[1]}}, {8{S_AXI_WSTRB[0]}}
};
assign ADDR_WRITE_EN = S_AXI_AWVALID & S_AXI_AWREADY;
assign WRITE_EN = S_AXI_WVALID & S_AXI_WREADY;
// WRITE
always @(posedge ACLK) begin
if (!ARESETn) WRITE_STATE <= S_WRIDLE;
else WRITE_STATE <= NEXT_WRITE_STATE;
end
// WRITE
always @(*) begin
case (WRITE_STATE)
S_WRIDLE: if (S_AXI_AWVALID) NEXT_WRITE_STATE = S_WRDATA;
else NEXT_WRITE_STATE = S_WRIDLE;
S_WRDATA: if (S_AXI_AWVALID) NEXT_WRITE_STATE = S_WRRESP;
else NEXT_WRITE_STATE = S_WRDATA;
S_WRRESP: if (S_AXI_BREADY) NEXT_WRITE_STATE = S_WRIDLE;
else NEXT_WRITE_STATE = S_WRRESP;
default: NEXT_WRITE_STATE = S_WRIDLE;
endcase
end
// WRITE
always @(posedge ACLK) begin
if (ADDR_WRITE_EN) WRITE_ADDR <= S_AXI_AWADDR[ADDR_WIDTH-1:0];
end
// READ
assign S_AXI_ARREADY = (READ_STATE == S_RDIDLE);
assign S_AXI_RDATA = RDATA;
assign S_AXI_RRESP = SET_OK;
assign S_AXI_RVALID = (READ_STATE == S_RDDATA);
assign ADDR_READ_EN = S_AXI_ARVALID & S_AXI_ARREADY;
assign RADDR = S_AXI_ARADDR[ADDR_WIDTH-1:0];
// READ
always @(posedge ACLK) begin
if (!ARESETn) READ_STATE <= S_RDIDLE;
else READ_STATE <= NEXT_READ_STATE;
end
// READ
always @(*) begin
case (READ_STATE)
S_RDIDLE: if (S_AXI_ARVALID) NEXT_READ_STATE = S_RDDATA;
else NEXT_READ_STATE = S_RDIDLE;
S_RDDATA: if (S_AXI_RREADY) NEXT_READ_STATE = S_RDIDLE;
else NEXT_READ_STATE = S_RDDATA;
default: NEXT_READ_STATE = S_RDIDLE;
endcase
end
// READ
always @(posedge ACLK) begin
if (!ARESETn) RDATA <= 0;
else if (ADDR_READ_EN) RDATA <= BRAM[RADDR];
end
// WRITE
always @(posedge ACLK) begin
if (!ARESETn) begin
WRITE_ADDR <= 0;
end else if (WRITE_EN) begin
BRAM[WRITE_ADDR] <= S_AXI_WDATA;
end
end
endmodule
| 7.522589 |
module axi4_lite_slave_pwm (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
output s_axi_rvalid_o,
output [31:0] s_axi_rdata_o,
// WRITE SIGNALS
// aw -> address write (address in)
// w -> write (data in)
// b -> response
input [31:0] s_axi_awaddr_i,
output s_axi_awready_o,
input s_axi_awvalid_i,
input [31:0] s_axi_wdata_i,
output s_axi_wready_o,
input [ 3:0] s_axi_wstrb_i,
input s_axi_wvalid_i,
input s_axi_bready_i,
output s_axi_bvalid_o,
output pwm1_o,
output pwm2_o,
input [3:0] read_size_i
);
// PWM
wire [1:0] pwm1_mode_w;
wire [31:0] pwm1_period_w;
wire [31:0] pwm1_threshold1_w;
wire [31:0] pwm1_threshold2_w;
wire [11:0] pwm1_step_w;
wire [1:0] pwm2_mode_w;
wire [31:0] pwm2_period_w;
wire [31:0] pwm2_threshold1_w;
wire [31:0] pwm2_threshold2_w;
wire [11:0] pwm2_step_w;
wire pwm1_w;
wire pwm2_w;
assign pwm1_o = pwm1_w;
assign pwm2_o = pwm2_w;
axi_interface_pwm axi_connection (
.s_axi_aclk_i(s_axi_aclk_i),
.s_axi_aresetn_i(s_axi_aresetn_i),
.s_axi_araddr_i(s_axi_araddr_i),
.s_axi_arready_o(s_axi_arready_o),
.s_axi_arvalid_i(s_axi_arvalid_i),
.s_axi_rready_i(s_axi_rready_i),
.s_axi_rvalid_o(s_axi_rvalid_o),
.s_axi_rdata_o(s_axi_rdata_o),
.s_axi_awaddr_i(s_axi_awaddr_i),
.s_axi_awready_o(s_axi_awready_o),
.s_axi_awvalid_i(s_axi_awvalid_i),
.s_axi_wdata_i(s_axi_wdata_i),
.s_axi_wready_o(s_axi_wready_o),
.s_axi_wstrb_i(s_axi_wstrb_i),
.s_axi_wvalid_i(s_axi_wvalid_i),
.s_axi_bready_i(s_axi_bready_i),
.s_axi_bvalid_o(s_axi_bvalid_o),
.read_size_i(read_size_i),
.pwm1_mode_o(pwm1_mode_w),
.pwm1_period_o(pwm1_period_w),
.pwm1_threshold1_o(pwm1_threshold1_w),
.pwm1_threshold2_o(pwm1_threshold2_w),
.pwm1_step_o(pwm1_step_w),
.pwm1_i(pwm1_w),
.pwm2_mode_o(pwm2_mode_w),
.pwm2_period_o(pwm2_period_w),
.pwm2_threshold1_o(pwm2_threshold1_w),
.pwm2_threshold2_o(pwm2_threshold2_w),
.pwm2_step_o(pwm2_step_w),
.pwm2_i(pwm2_w)
);
pwm1 pwm_connection1 (
.clk_i(s_axi_aclk_i),
.rst_i(s_axi_aresetn_i),
.pwm1_mode_i(pwm1_mode_w),
.pwm1_period_i(pwm1_period_w),
.pwm1_threshold1_i(pwm1_threshold1_w),
.pwm1_threshold2_i(pwm1_threshold2_w),
.pwm1_step_i(pwm1_step_w),
.pwm1_o(pwm1_w)
);
pwm2 pwm_connection2 (
.clk_i(s_axi_aclk_i),
.rst_i(s_axi_aresetn_i),
.pwm2_mode_i(pwm2_mode_w),
.pwm2_period_i(pwm2_period_w),
.pwm2_threshold1_i(pwm2_threshold1_w),
.pwm2_threshold2_i(pwm2_threshold2_w),
.pwm2_step_i(pwm2_step_w),
.pwm2_o(pwm2_w)
);
endmodule
| 7.522589 |
module axi4_lite_slave_spi (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
output s_axi_rvalid_o,
output [31:0] s_axi_rdata_o,
//output s_axi_rresp_o,
// WRITE SIGNALS
// aw -> address write (address in)
// w -> write (data in)
// b -> response
input [31:0] s_axi_awaddr_i,
output s_axi_awready_o,
input s_axi_awvalid_i,
input [31:0] s_axi_wdata_i,
output s_axi_wready_o,
input [ 3:0] s_axi_wstrb_i,
input s_axi_wvalid_i,
input s_axi_bready_i,
output s_axi_bvalid_o,
input [3:0] read_size_i,
output cs_o,
output sck_o,
output spi_mosi_o,
input spi_miso_i
);
wire [4:0] adres_bit_w;
wire islem_w;
wire islem_gecerli_w;
wire [1:0] read_type_w;
wire [1:0] write_type_w;
wire islem_bitti_w;
axi_interface_spi spi_connection (
.s_axi_aclk_i(s_axi_aclk_i),
.s_axi_aresetn_i(s_axi_aresetn_i),
.s_axi_araddr_i(s_axi_araddr_i),
.s_axi_arready_o(s_axi_arready_o),
.s_axi_arvalid_i(s_axi_arvalid_i),
.s_axi_rready_i(s_axi_rready_i),
.s_axi_rvalid_o(s_axi_rvalid_o),
.s_axi_awaddr_i(s_axi_awaddr_i),
.s_axi_awready_o(s_axi_awready_o),
.s_axi_awvalid_i(s_axi_awvalid_i),
.s_axi_wready_o(s_axi_wready_o),
.s_axi_wstrb_i(s_axi_wstrb_i),
.s_axi_wvalid_i(s_axi_wvalid_i),
.s_axi_bready_i(s_axi_bready_i),
.s_axi_bvalid_o(s_axi_bvalid_o),
.read_size_i(read_size_i),
.adres_bit_o(adres_bit_w),
.islem_o(islem_w),
.islem_gecerli_o(islem_gecerli_w),
.read_type_o(read_type_w),
.write_type_o(write_type_w),
.islem_bitti_i(islem_bitti_w)
);
spi spi (
.clk_i(s_axi_aclk_i),
.rst_i(s_axi_aresetn_i),
.adres_bit_i(adres_bit_w),
.islem_i(islem_w),
.islem_gecerli_i(islem_gecerli_w),
.read_type_i(read_type_w),
.write_type_i(write_type_w),
.veri_i(s_axi_wdata_i),
.islem_bitti_o(islem_bitti_w),
.veri_o(s_axi_rdata_o),
.cs_o(cs_o),
.sck_o(sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
endmodule
| 7.522589 |
module axi4_lite_slave_tb #(
parameter addr_width = 3,
parameter data_width = 32,
parameter strb_width = 4
) ();
// Global signals
reg aclk;
reg aresetn;
// write address channel
reg awvalid;
wire awready;
reg [addr_width-1:0] awaddr;
reg awprot;
// write data channel
reg wvalid;
wire wready;
reg [data_width-1:0] wdata;
reg [strb_width-1:0] wstrb;
// write response channel
wire bvalid;
reg bready;
wire [1:0] bresp;
// read address channel
reg arvalid;
wire arready;
reg [addr_width-1:0] araddr;
reg arprot;
// read data channel
wire rvalid;
reg rready;
wire [data_width-1:0] rdata;
wire [1:0] rresp;
// initialize
initial begin
aclk = 0;
aresetn = 1;
awvalid = 0;
awaddr = 0;
awprot = 0;
wvalid = 0;
wdata = 0;
wstrb = 0;
bready = 0;
arvalid = 0;
araddr = 0;
arprot = 0;
rready = 0;
#10 aresetn = 0;
#10 aresetn = 1;
end
// write data test
initial begin
#50 w_a_d(3'd1, 32'd100, 4'b1111);
#50 w_d_a(3'd2, 32'd200, 4'b1111);
#50 w_a_d(3'd3, 32'h1234_5678, 4'b1111);
#50 w_a_d(3'd3, 32'h9999_aaaa, 4'b1010);
#50 read(3'd1);
#50 read(3'd4);
end
// data after address
task w_a_d(input [addr_width-1:0] address, input [data_width-1:0] data,
input [strb_width-1:0] strb);
begin
@(posedge aclk) awvalid = 1'b1;
awaddr = address;
wstrb = strb;
@(posedge aclk) wvalid = 1'b1;
wdata = data;
@(posedge aclk) wvalid = 1'b1;
awvalid = 1'b0;
@(posedge aclk) bready = 1'b1;
wvalid = 1'b0;
@(posedge aclk) bready = 1'b0;
end
endtask
// address after data
task w_d_a(input [addr_width-1:0] address, input [data_width-1:0] data,
input [strb_width-1:0] strb);
begin
@(posedge aclk) wvalid = 1'b1;
wdata = data;
wstrb = strb;
@(posedge aclk) awvalid = 1'b1;
awaddr = address;
@(posedge aclk) wvalid = 1'b0;
awvalid = 1'b1;
@(posedge aclk) bready = 1'b1;
awvalid = 1'b0;
@(posedge aclk) bready = 1'b0;
end
endtask
// read process
task read(input [addr_width-1:0] address);
begin
@(posedge aclk) arvalid = 1'b1;
araddr = address;
@(posedge aclk) rready = 1'b1;
arvalid = 1'b0;
@(posedge aclk) rready = 1'b0;
end
endtask
// aclk generate
always #2 aclk <= ~aclk;
// connect dut
axi4_lite_slave slave (
// global signals
.aclk(aclk),
.aresetn(aresetn),
// write address channel
.awaddr (awaddr),
.awprot (awprot),
.awvalid(awvalid),
.awready(awready),
// write data channel
.wdata (wdata),
.wstrb (wstrb),
.wvalid(wvalid),
.wready(wready),
// write response channel
.bresp (bresp),
.bvalid(bvalid),
.bready(bready),
// read address channel
.araddr (araddr),
.arprot (arprot),
.arvalid(arvalid),
.arready(arready),
// read data channel
.rdata (rdata),
.rresp (rresp),
.rvalid(rvalid),
.rready(rready)
);
endmodule
| 7.522589 |
module axi4_lite_slave_uart (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
output s_axi_rvalid_o,
output [31:0] s_axi_rdata_o,
// WRITE SIGNALS
// aw -> address write (address in)
// w -> write (data in)
// b -> response
input [31:0] s_axi_awaddr_i,
output s_axi_awready_o,
input s_axi_awvalid_i,
input [31:0] s_axi_wdata_i,
output s_axi_wready_o,
input [ 3:0] s_axi_wstrb_i,
input s_axi_wvalid_i,
input s_axi_bready_i,
output s_axi_bvalid_o,
input [3:0] read_size_i,
output tx_o,
input rx_i
);
wire r_done_w;
wire rx_en_w;
wire t_done_w;
wire tx_en_w;
wire [15:0] baud_div_w;
wire [7:0] tx_w;
wire [7:0] rx_w;
axi_interface_uart axi_connection (
.s_axi_aclk_i(s_axi_aclk_i),
.s_axi_aresetn_i(s_axi_aresetn_i),
.s_axi_araddr_i(s_axi_araddr_i),
.s_axi_arready_o(s_axi_arready_o),
.s_axi_arvalid_i(s_axi_arvalid_i),
.s_axi_rready_i(s_axi_rready_i),
.s_axi_rvalid_o(s_axi_rvalid_o),
.s_axi_rdata_o(s_axi_rdata_o),
.s_axi_awaddr_i(s_axi_awaddr_i),
.s_axi_awready_o(s_axi_awready_o),
.s_axi_awvalid_i(s_axi_awvalid_i),
.s_axi_wdata_i(s_axi_wdata_i),
.s_axi_wready_o(s_axi_wready_o),
.s_axi_wstrb_i(s_axi_wstrb_i),
.s_axi_wvalid_i(s_axi_wvalid_i),
.s_axi_bready_i(s_axi_bready_i),
.s_axi_bvalid_o(s_axi_bvalid_o),
.read_size_i(read_size_i),
.r_done_i(r_done_w),
.t_done_i(t_done_w),
.baud_div_o(baud_div_w),
.tx_en_o(tx_en_w),
.rx_en_o(rx_en_w),
.tx_o(tx_w),
.rx_i(rx_w)
);
Uart uart_connection (
.clk_i(s_axi_aclk_i),
.rst_i(s_axi_aresetn_i),
.r_done_o(r_done_w),
.rx_en_i(rx_en_w),
.t_done_o(t_done_w),
.tx_en_i(tx_en_w),
.baud_div_i(baud_div_w),
.t_in_i(tx_w),
.r_out_o(rx_w),
.tx_o(tx_o),
.rx_i(rx_i)
);
endmodule
| 7.522589 |
module axi4_mem (
input clock,
input rst_n,
output io_slave_awready,
input io_slave_awvalid,
input [31:0] io_slave_awaddr,
input [ 3:0] io_slave_awid,
input [ 7:0] io_slave_awlen,
input [ 2:0] io_slave_awsize,
input [ 1:0] io_slave_awburst,
output io_slave_wready,
input io_slave_wvalid,
input [63:0] io_slave_wdata,
input [ 7:0] io_slave_wstrb,
input io_slave_wlast,
input io_slave_bready,
output io_slave_bvalid,
output [ 1:0] io_slave_bresp,
output [ 3:0] io_slave_bid,
output io_slave_arready,
input io_slave_arvalid,
input [31:0] io_slave_araddr,
input [ 3:0] io_slave_arid,
input [ 7:0] io_slave_arlen,
input [ 2:0] io_slave_arsize,
input [ 1:0] io_slave_arburst,
input io_slave_rready,
output io_slave_rvalid,
output [ 1:0] io_slave_rresp,
output [63:0] io_slave_rdata,
output io_slave_rlast,
output [ 3:0] io_slave_rid
);
reg [7:0] mem [0:2000];
reg [8:0] cnt;
initial begin
$readmemh("init_ram.mem", mem);
end
always @(posedge clock or negedge rst_n) begin
if (!rst_n) begin
cnt <= 63'd0;
end else if (cnt <= 200) begin
$display("mem[%0d]: %h", cnt, mem[cnt]);
if ((cnt + 1'd1) % 4 == 0 && cnt > 0) begin
$display("addr: %h inst: %h", 'h3000_0000 + (cnt - 3), {mem[cnt], mem[cnt-1], mem[cnt-2],
mem[cnt-3]});
end
cnt <= cnt + 1'd1;
end
end
assign io_slave_arready = 1'b1;
assign io_slave_rvalid = 1'b1;
assign io_slave_rresp = 1'b1;
assign io_slave_rdata = 64'h00000413;
assign io_slave_rlast = 1'b1;
assign io_slave_rid = 1'b0;
endmodule
| 7.19552 |
module sdram_axi_pmem_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [ WIDTH-1:0] ram [DEPTH-1:0];
reg [ ADDR_W-1:0] rd_ptr;
reg [ ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule
| 7.184129 |
modules
//-----------------------------------------------------------------
module axi4retime_fifo2x37
(
// Inputs
input clk_i
,input rst_i
,input [ 36:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 36:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [36:0] ram_q[1:0];
reg [0:0] rd_ptr_q;
reg [0:0] wr_ptr_q;
reg [1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
count_q <= 2'b0;
rd_ptr_q <= 1'b0;
wr_ptr_q <= 1'b0;
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1'd1;
end
// Pop
if (pop_i & valid_o)
begin
rd_ptr_q <= rd_ptr_q + 1'd1;
end
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
begin
count_q <= count_q + 2'd1;
end
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
begin
count_q <= count_q - 2'd1;
end
end
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = (count_q != 2'd0);
assign accept_o = (count_q != 2'd2);
assign data_out_o = ram_q[rd_ptr_q];
endmodule
| 7.831093 |
modules
//-----------------------------------------------------------------
module axi4_retime256_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
| 7.831093 |
module axi4_stream_reader #(
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
/* axi4-stream ports */
input wire S_AXIS_ACLK,
input wire S_AXIS_ARESETN,
output wire S_AXIS_TREADY,
input wire [ C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
input wire S_AXIS_TLAST,
input wire S_AXIS_TVALID,
/* control signals */
input wire ready,
output wire data_valid,
output wire [ C_S_AXIS_TDATA_WIDTH-1:0] data
// FIXME: data_last
);
/* io connections */
assign S_AXIS_TREADY = ready;
assign data_valid = S_AXIS_TVALID;
assign data = S_AXIS_TDATA;
endmodule
| 9.187641 |
module axi4_stream_slave #(
parameter DATABUSWIDTH = 16, //in bytes
parameter TDESTWIDTH = 2, // in bits
parameter TUSERWIDTH = 22, // in bits
parameter FIFODATAWIDTH = 132, // in bits
parameter TDESTADDR = 2'b01
) (
//common signals
input clk,
input reset,
//axi4stream signals
input s_axis_tvalid,
output reg s_axis_tready,
input [(8*DATABUSWIDTH-1):0] s_axis_tdata,
input [ (DATABUSWIDTH-1):0] s_axis_tkeep,
input s_axis_tlast,
input [ (TDESTWIDTH-1):0] s_axis_tdest,
//
//user signals
output reg [(FIFODATAWIDTH-1):0] fifo1_wr_data,
output reg fifo1_wr_en,
input fifo1_prog_full_flag,
input fifo1_full_flag,
input fifo1_empty_flag
);
localparam [2:0] idle = 3'b000, start = 3'b001, transmit = 3'b010, state0 = 3'b011;
reg [2:0] state_reg;
always @(posedge clk or posedge reset) begin
if (reset) begin
state_reg <= idle;
end else begin
case (state_reg)
idle: begin
fifo1_wr_en <= 1'b0;
fifo1_wr_data <= 0;
s_axis_tready <= 1'b0;
if(s_axis_tvalid & (s_axis_tdest == TDESTADDR) & (~fifo1_prog_full_flag) & (~(fifo1_full_flag & fifo1_empty_flag)))
begin
state_reg <= transmit;
s_axis_tready <= 1'b1;
end
end
state0: begin
state_reg <= transmit;
fifo1_wr_en <= 1'b1;
fifo1_wr_data[127:0] <= s_axis_tdata;
if (s_axis_tkeep[0]) begin
fifo1_wr_data[128] <= 1'b1;
end
if (s_axis_tkeep[4]) begin
fifo1_wr_data[129] <= 1'b1;
end
if (s_axis_tkeep[8]) begin
fifo1_wr_data[130] <= 1'b1;
end
if (s_axis_tkeep[12]) begin
fifo1_wr_data[131] <= 1'b1;
end
end
transmit: begin
fifo1_wr_en <= 1'b1;
fifo1_wr_data[127:0] <= s_axis_tdata;
if (s_axis_tkeep[0]) begin
fifo1_wr_data[128] <= 1'b1;
end
if (s_axis_tkeep[4]) begin
fifo1_wr_data[129] <= 1'b1;
end
if (s_axis_tkeep[8]) begin
fifo1_wr_data[130] <= 1'b1;
end
if (s_axis_tkeep[12]) begin
fifo1_wr_data[131] <= 1'b1;
end
if (s_axis_tlast) begin
s_axis_tready <= 1'b0;
state_reg <= idle;
end
end
endcase
end
end
endmodule
| 7.393094 |
module axi_stream_writer #(
parameter integer C_M_AXIS_TDATA_WIDTH = 32
) (
input wire start, // FIXME: sil
input wire [ C_M_AXIS_TDATA_WIDTH-1:0] data,
input wire data_valid,
input wire data_last,
output wire ready,
/* axi4-stream ports */
input wire M_AXIS_ACLK,
input wire M_AXIS_ARESETN,
output wire M_AXIS_TVALID,
output wire [ C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
output wire M_AXIS_TLAST,
input wire M_AXIS_TREADY
);
/* I/O connections */
assign M_AXIS_TVALID = data_valid;
assign M_AXIS_TDATA = data;
assign M_AXIS_TLAST = data_last;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH / 8) {1'b1}};
assign ready = M_AXIS_TREADY;
endmodule
| 8.69241 |
module AXI4_Template_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
AXI4_Template_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) AXI4_Template_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 7.074031 |
module axi4_tester #(
parameter P_TARGET_SLAVE_BASE_ADDR = 32'h0, //Base address of targeted slave
parameter integer P_WRITE_BURSTS = 1, //Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer P_READ_BURSTS = 16, //Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer P_ID_WIDTH = 6, //Thread ID Width
parameter integer P_ADDR_WIDTH = 32, //Width of Address Bus
parameter integer P_DATA_WIDTH = 256 //Width of Data Bus
) (
input wire CLOCK, //Global Clock Signal.
input wire RESET, //Global Reset Signal. This Signal is Active Low
input wire BEGIN_TEST,
output wire [P_ADDR_WIDTH - 1:0] WRITE_ADDR,
output wire [P_DATA_WIDTH - 1:0] WRITE_DATA,
output wire WRITE_START,
input wire WRITE_READY,
input wire WRITE_DONE, //Asserts when transaction is complete
input wire WRITE_ERROR //Asserts when ERROR is detected
);
//State machine parameters.
reg [3:0] current_state;
localparam [3:0] STATE_IDLE = 0;
localparam [3:0] STATE_WAIT1 = 1;
localparam [3:0] STATE_WAIT2 = 2;
localparam [3:0] STATE_WAIT3 = 3;
localparam [3:0] STATE_DONE = 4;
reg [P_ADDR_WIDTH - 1:0] m_waddr;
reg [P_DATA_WIDTH - 1:0] m_wdata;
reg m_wstart;
assign WRITE_START = m_wstart;
assign WRITE_ADDR = m_waddr;
assign WRITE_DATA = m_wdata;
always @(posedge CLOCK) begin
if (!RESET) begin
current_state <= STATE_IDLE;
m_wstart <= 0;
m_waddr <= 0;
m_wdata <= 0;
end else begin
case (current_state)
STATE_IDLE: begin
if (BEGIN_TEST) begin
current_state <= STATE_WAIT1;
m_wstart <= 1;
m_waddr <= 'h20;
m_wdata <= 'h1111_2222_3333_4444_5555_6666_7777_8888_1111_2222_3333_4444_5555_6666_7777_8888;
end
end
STATE_WAIT1: begin
if (WRITE_READY) begin
current_state <= STATE_WAIT2;
m_wstart <= 1;
m_waddr <= 'h40;
m_wdata <= 'h2222_3333_4444_5555_6666_7777_8888_1111_2222_3333_4444_5555_6666_7777_8888_1111;
end
end
STATE_WAIT2: begin
if (WRITE_READY) begin
current_state <= STATE_WAIT3;
m_wstart <= 1;
m_waddr <= 'h40;
m_wdata <= 'h2222_3333_4444_5555_6666_7777_8888_1111_2222_3333_4444_5555_6666_7777_8888_1111;
end
end
STATE_WAIT3: begin
if (WRITE_READY) begin
current_state <= STATE_DONE;
m_wstart <= 0;
m_waddr <= 'h0;
m_wdata <= 'h0;
end
end
STATE_DONE: begin
if (!BEGIN_TEST) begin
current_state <= STATE_IDLE;
m_wstart <= 0;
m_waddr <= 'h0;
m_wdata <= 'h0;
end
end
default: begin
current_state <= STATE_IDLE;
end
endcase
end
end
endmodule
| 8.655463 |
module AXI4_TO_PINGPONG #(
parameter ADDRBITS = 7,
DATABITS = 16,
MEMDEPTH = 128,
USETLAST = 0
) (
input clk,
input rst,
output [ADDRBITS-1:0] addra,
output wea,
output [DATABITS-1:0] dina,
output finisha,
input readya,
input [DATABITS-1:0] s_axis_data_tdata,
output s_axis_data_tready,
input s_axis_data_tvalid,
input s_axis_data_tlast
);
reg [ADDRBITS-1:0] addra_r0;
reg wea_r0;
reg [DATABITS-1:0] dina_r0;
reg finisha_r0;
reg [3:0] pingpongwaitcnt = 4'd0;
reg first = 1'd1;
//reg s_axis_data_tready_r0;
assign addra = addra_r0;
assign wea = wea_r0;
assign dina = dina_r0;
assign finisha = finisha_r0;
assign s_axis_data_tready = readya && pingpongwaitcnt == 4'd0;
always @(posedge clk) begin
if (rst) begin
addra_r0 <= 0;
wea_r0 <= 1'b0;
dina_r0 <= 0;
finisha_r0 <= 1'b0;
pingpongwaitcnt <= 4'd0;
first <= 1'd1;
//s_axis_data_tready_r0<=1'b0;
end else begin
if (pingpongwaitcnt == 4'd0) begin
if (s_axis_data_tready) begin
if (s_axis_data_tvalid) begin
wea_r0 <= 1'b1;
dina_r0 <= s_axis_data_tdata;
if (s_axis_data_tlast || addra_r0 == (MEMDEPTH - 2)) begin
pingpongwaitcnt <= 4'd5;
first <= 1'd1;
end else begin
first <= 1'd0;
end
if (first == 1'd0) addra_r0 <= addra_r0 + 1;
end else begin
wea_r0 <= 1'b0;
end
end else begin
wea_r0 <= 1'b0;
end
finisha_r0 <= 1'b0;
end else begin //waiting
pingpongwaitcnt <= pingpongwaitcnt - 4'd1;
if (pingpongwaitcnt == 4'd5) begin
wea_r0 <= 1'b1;
end else begin
wea_r0 <= 1'b0;
end
if (pingpongwaitcnt == 4'd2) begin
finisha_r0 <= 1'b1;
end else begin
finisha_r0 <= 1'b0;
end
end
end
end
endmodule
| 7.08562 |
module axi4_upconv256_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [ WIDTH-1:0] ram [DEPTH-1:0];
reg [ ADDR_W-1:0] rd_ptr;
reg [ ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i)
if (rst_i) begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule
| 7.078253 |
module axi4_w_reg_slice (
wreadys,
wvalidm,
wdatam,
wstrbm,
wlastm,
wuserm,
aclk,
aresetn,
wvalids,
wdatas,
wstrbs,
wlasts,
wusers,
wreadym
);
parameter DATA_WIDTH = 32;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter STRB_WIDTH = DATA_WIDTH / 8;
localparam PAYLD_WIDTH = DATA_WIDTH + USER_WIDTH + STRB_WIDTH + 1;
input aclk;
input aresetn;
input wvalids;
output wreadys;
input [DATA_WIDTH-1:0] wdatas;
input [STRB_WIDTH-1:0] wstrbs;
input wlasts;
input [USER_WIDTH-1:0] wusers;
output wvalidm;
input wreadym;
output [DATA_WIDTH-1:0] wdatam;
output [STRB_WIDTH-1:0] wstrbm;
output wlastm;
output [USER_WIDTH-1:0] wuserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = wvalids;
assign payload_src = {wdatas, wstrbs, wlasts, wusers};
assign wreadys = ready_src;
assign wvalidm = valid_dst;
assign {wdatam, wstrbm, wlastm, wuserm} = payload_dst;
assign ready_dst = wreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 8.13981 |
module axi64_to_ll8 #(
parameter START_BYTE = 6
) (
input clk,
input reset,
input clear,
input [63:0] axi64_tdata,
input axi64_tlast,
input [3:0] axi64_tuser,
input axi64_tvalid,
output axi64_tready,
output [7:0] ll_data,
output ll_eof,
output ll_src_rdy,
input ll_dst_rdy
);
reg [7:0] data_int;
wire eof_int, valid_int, ready_int;
reg [2:0] state = START_BYTE;
reg eof, done;
reg [3:0] occ;
always @(posedge clk)
if (reset | clear) state <= START_BYTE;
else if (valid_int & ready_int)
if (eof_int) state <= START_BYTE;
else state <= state + 3'd1;
assign valid_int = axi64_tvalid;
assign axi64_tready = ready_int & (eof_int | state == 7);
assign eof_int = axi64_tlast & (axi64_tuser[2:0] == (state + 3'd1));
always @*
case (state)
0: data_int <= axi64_tdata[63:56];
1: data_int <= axi64_tdata[55:48];
2: data_int <= axi64_tdata[47:40];
3: data_int <= axi64_tdata[39:32];
4: data_int <= axi64_tdata[31:24];
5: data_int <= axi64_tdata[23:16];
6: data_int <= axi64_tdata[15:8];
7: data_int <= axi64_tdata[7:0];
default: data_int <= axi64_tdata[7:0];
endcase // case (state)
axi_fifo_short #(
.WIDTH(9)
) ll8_fifo (
.clk(clk),
.reset(reset),
.clear(0),
.i_tdata({eof_int, data_int}),
.i_tvalid(valid_int),
.i_tready(ready_int),
.o_tdata({ll_eof, ll_data}),
.o_tvalid(ll_src_rdy),
.o_tready(ll_dst_rdy),
.space(),
.occupied()
);
endmodule
| 6.927426 |
module axi64_to_xge64 (
input clk,
input reset,
input clear,
input [63:0] s_axis_tdata,
input [3:0] s_axis_tuser,
input s_axis_tlast,
input s_axis_tvalid,
output s_axis_tready,
output [63:0] m_axis_tdata,
output [3:0] m_axis_tuser,
output m_axis_tlast,
output m_axis_tvalid,
input m_axis_tready
);
localparam STORE_FIRST = 0;
localparam FORWARD_FULL = 1;
localparam RELEASE_LAST = 2;
reg [1:0] state;
reg [15:0] saved;
reg [2:0] last_occ;
reg last_sof;
//on last line when eof and not finishing with 7 or 8 bytes as last word.
wire last_line = (s_axis_tlast && !(s_axis_tuser[2:0] == 3'b111 || s_axis_tuser[2:0] == 3'b000));
always @(posedge clk) begin
if (reset | clear) begin
last_sof <= 0;
last_occ <= 0;
state <= STORE_FIRST;
end else begin
if (s_axis_tvalid && s_axis_tready) begin
saved <= s_axis_tdata[15:0];
last_occ <= s_axis_tuser[2:0];
last_sof <= (state == STORE_FIRST);
end
case (state)
STORE_FIRST: begin
if (s_axis_tvalid && s_axis_tready) begin
state <= FORWARD_FULL;
end
end
FORWARD_FULL: begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
state <= last_line ? STORE_FIRST : RELEASE_LAST;
end
end
RELEASE_LAST: begin
if (m_axis_tvalid && m_axis_tready) begin
state <= STORE_FIRST;
end
end
endcase //state
end
end
assign m_axis_tdata[63:0] = {saved, s_axis_tdata[63:16]};
assign m_axis_tuser[3] = last_sof;
assign m_axis_tlast = (state == RELEASE_LAST) ? 1'b1 : last_line;
assign m_axis_tuser[2:0] = ((state == RELEASE_LAST)? last_occ : (last_line? s_axis_tuser[2:0] : 3'b110)) + 3'b010;
assign m_axis_tvalid = (state == STORE_FIRST) ? 0 : ((state == RELEASE_LAST) ? 1 : s_axis_tvalid);
assign s_axis_tready = (state == STORE_FIRST) ? 1 : ((state == RELEASE_LAST) ? 0 : m_axis_tready);
endmodule
| 9.061511 |
module AXIBridge (
input clk,
input rst_n,
// AXI slave interface
input [ 5:0] axi_arid,
input [31:0] axi_araddr,
input [ 7:0] axi_arlen,
input [ 2:0] axi_arsize,
input [ 1:0] axi_arburst,
input [ 1:0] axi_arlock,
input [ 3:0] axi_arcache,
input [ 2:0] axi_arprot,
input axi_arvalid,
output axi_arready,
output [ 5:0] axi_rid,
output [31:0] axi_rdata,
output [ 1:0] axi_rresp,
output axi_rlast,
output axi_rvalid,
input axi_rready,
input [ 5:0] axi_awid,
input [31:0] axi_awaddr,
input [ 7:0] axi_awlen,
input [ 2:0] axi_awsize,
input [ 1:0] axi_awburst,
input [ 1:0] axi_awlock,
input [ 3:0] axi_awcache,
input [ 2:0] axi_awprot,
input axi_awvalid,
output axi_awready,
input [ 5:0] axi_wid,
input [31:0] axi_wdata,
input [ 3:0] axi_wstrb,
input axi_wlast,
input axi_wvalid,
output axi_wready,
output [ 5:0] axi_bid,
output [ 1:0] axi_bresp,
output axi_bvalid,
input axi_bready,
// general peripheral interface
output gpi_read,
output gpi_write,
output [31:0] gpi_addr,
output [31:0] gpi_wdata,
input [31:0] gpi_rdata
);
reg busy, write, r_or_w;
wire ar_enter = axi_arvalid & axi_arready;
wire r_retire = axi_rvalid & axi_rready & axi_rlast;
wire r_valid = busy & r_or_w & !r_retire;
wire aw_enter = axi_awvalid & axi_awready;
wire w_enter = axi_wvalid & axi_wready & axi_wlast;
wire b_retire = axi_bvalid & axi_bready;
assign axi_arready = ~busy & (!r_or_w | !axi_awvalid);
assign axi_awready = ~busy & (r_or_w | !axi_arvalid);
reg [5 : 0] buf_id;
reg [ 31:0] buf_addr;
reg [7 : 0] buf_len;
reg [2 : 0] buf_size;
always @(posedge clk) begin
if (!rst_n) busy <= 1'b0;
else if (ar_enter | aw_enter) busy <= 1'b1;
else if (r_retire | b_retire) busy <= 1'b0;
end
always @(posedge clk) begin
if (!rst_n) begin
r_or_w <= 1'b0;
buf_id <= 6'b0;
buf_addr <= 32'h0;
buf_len <= 8'b0;
buf_size <= 3'b0;
end else if (ar_enter | aw_enter) begin
r_or_w <= ar_enter;
buf_id <= ar_enter ? axi_arid : axi_awid;
buf_addr <= ar_enter ? axi_araddr : axi_awaddr;
buf_len <= ar_enter ? axi_arlen : axi_awlen;
buf_size <= ar_enter ? axi_arsize : axi_awsize;
end
end
reg wready_reg;
assign axi_wready = wready_reg;
always @(posedge clk) begin
if (!rst_n) wready_reg <= 1'b0;
else if (aw_enter) wready_reg <= 1'b1;
else if (w_enter & axi_wlast) wready_reg <= 1'b0;
end
reg rvalid_reg;
reg rlast_reg;
assign axi_rdata = gpi_rdata;
assign axi_rvalid = rvalid_reg;
assign axi_rlast = rlast_reg;
always @(posedge clk) begin
if (!rst_n) begin
rvalid_reg <= 1'b0;
rlast_reg <= 1'b0;
end else if (r_valid) begin
rvalid_reg <= 1'b1;
rlast_reg <= 1'b1;
end else if (r_retire) begin
rvalid_reg <= 1'b0;
end
end
reg bvalid_reg;
assign axi_bvalid = bvalid_reg;
always @(posedge clk) begin
if (!rst_n) bvalid_reg <= 1'b0;
else if (w_enter) bvalid_reg <= 1'b1;
else if (b_retire) bvalid_reg <= 1'b0;
end
assign axi_rid = buf_id;
assign axi_bid = buf_id;
assign axi_bresp = 2'b0;
assign axi_rresp = 2'b0;
assign gpi_read = r_valid;
assign gpi_write = w_enter;
assign gpi_addr = gpi_read ? axi_araddr : gpi_write ? axi_awaddr : 32'h0;
assign gpi_wdata = axi_wdata;
endmodule
| 7.506279 |
module absorbs not-ready cycles from the AXI core as well as our own RX logic so that the two don't mess each other up.
// Once Xilinx fixes their bugs, this will probably be unnecessary.
`include "PicoDefines.v"
module AXIBuffer (
input clk,
input rst,
// AXI-S
input [127:0] s_axis_rx_tdata,
//input [15:0] s_axis_rx_tstrb,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output reg s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
// AXI-M
output [127:0] m_axis_rx_tdata,
//output [15:0] m_axis_rx_tstrb,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser
);
wire empty;
wire [15:0] dop;
wire wr = s_axis_rx_tvalid && s_axis_rx_tready;
wire rd = m_axis_rx_tready && ~empty;
assign m_axis_rx_tvalid = ~empty;
// note that this leaves tons of empty space in the fifo, but that's not going to slow anything down.
always @(posedge clk)
s_axis_rx_tready <= ~(|cnt[9:7]);//prog_full;
assign m_axis_rx_tlast = dop[3];
assign m_axis_rx_tuser[21] = dop[2];
assign m_axis_rx_tuser[14:13] = dop[1:0];
assign m_axis_rx_tuser[12:0] = {s_axis_rx_tuser[12:10], dop[11:4] /* bar hit */, s_axis_rx_tuser[1:0]};
assign m_axis_rx_tuser[20:15] = s_axis_rx_tuser[20:15];
// building our own "full" signal for the fifo provides better timing.
// it takes several cycles for writes to propagate to the fifo's output. don't advertise them too soon.
// (this is why we use a delayed copy of wr)
reg [5:0] wr_q;
reg [9:0] cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 10'h0;
wr_q <= 6'h0;
end else begin
wr_q <= {wr_q[4:0], wr};
if (rd && ~wr_q[5] && (cnt != 10'h0))
cnt <= cnt - 1;
else if (wr_q[5] && ~rd)
cnt <= cnt + 1;
end
end
assign empty = ~(|cnt);
//TODO make sure prog_full is set far enough back from the end.
fifo_512x128 fifo (
.clk(clk),
.rst(rst),
.din(s_axis_rx_tdata[127:0]),
.dinp({4'h0, s_axis_rx_tuser[9:2], s_axis_rx_tlast, s_axis_rx_tuser[21], s_axis_rx_tuser[14:13]}),
.wr_en(wr),
.rd_en(rd),
.dout(m_axis_rx_tdata[127:0]),
.doutp(dop[15:0]),
//.empty(empty),
.prog_full(prog_full)
);
endmodule
| 6.748701 |
module axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG)
);
endmodule
| 7.03357 |
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