code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module avg (
din,
reset,
clk,
ready,
dout
);
input [15:0] din;
output [15:0] dout;
input reset, clk;
output ready;
endmodule
| 6.69656 |
module aviso_boletas (
input clk,
input comprar,
input compra_exitosa,
output reg impresion
);
reg [27:0] count;
initial begin
count = 0;
impresion = 0;
end
always @(posedge clk) begin
if (comprar & compra_exitosa) begin
impresion = 1;
count = 1;
end else if (coun... | 7.31417 |
module AvlStreamAdapter (
input i_avl_clock,
input i_avl_reset,
output o_avl_burstbegin,
output [ 7:0] o_avl_be,
output [25:0] o_avl_adr,
output [63:0] o_avl_dat,
output reg o_avl_wr_req,
output reg o_avl_rdt_req,
output ... | 6.986663 |
module avl_adxcfg_0 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9... | 6.652439 |
module avl_adxcfg_1 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9... | 6.528295 |
module avl_adxcfg_2 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9... | 6.506539 |
module avl_adxcfg_3 (
input wire rcfg_clk, // rcfg_clk.clk
input wire rcfg_reset_n, // rcfg_reset_n.reset_n
input wire rcfg_in_read_0, // rcfg_s0.read
input wire rcfg_in_write_0, // .write
input wire [ 9... | 6.941456 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module avl_dpram (
input csi_clk, // clock do avalon
input csi_clk500, // clock de 500 KHz
input rsi_reset_n, // reset do avalon
input avs_s0_read, // read
input avs_s0_write, // write
input [ 4:0] avs_s0_address, // a... | 7.973445 |
module generates a reset signal controlled by an Avalon-MM
* interface.
*
*/
module avmm_reset_hw #(
parameter ACTIVE_LOW_OUT = 0
)(
input clock,
input reset,
input write,
input [31:0] writedata,
input chipsel,
output user_reset
);
reg ... | 7.414651 |
module sha3_tb ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] avs_s0_readdata; // From u_sha3 of avalon_sha3.v
wire avs_s0_waitrequest; // From u_sha3 of avalon_sha3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs ... | 6.924456 |
module is simply a multiplexer for a data bus. Nothing particularly special.
*/
module avmm_width_adapter_mux #(
parameter MUX_SELECT_WIDTH = 2,
parameter SYMBOL_WIDTH = 32,
parameter MUX_INPUTS = (1<<MUX_SELECT_WIDTH)
)(
input [(MUX_INPUTS*SYMBOL_WIDTH)-1:0] in,
input [MUX_SELECT_WIDTH-1:0] sele... | 8.245224 |
module AvoidGoing (
input clk,
input CLK_1s,
input nCR,
input left,
input right,
input [19:0] dis,
output reg [1:0] AvoidSignal
);
reg [3:0] env;
wire stright;
parameter isBlock = 20'd200;
assign stright = dis[19:0] < isBlock ? 1'b1 : 1'b0; //dis less than isBlock -> 1
ass... | 7.616419 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
left = 1'b0;
down = 1'b0;
right = 1'b0;
up = 1'b0;
case (scancode)
16'he06b: begin
left = 1'b1;
end
16'he072: begin
... | 7.203305 |
module avoid_latch_else ();
reg q;
reg enable, d;
always @(enable or d)
if (enable) begin
q = d;
end else begin
q = 0;
end
initial begin
$monitor(" ENABLE = %b D = %b Q = %b", enable, d, q);
#1 enable = 0;
#1 d = 0;
#1 enable = 1;
#1 d = 1;
#1 d = 0;
#1 d ... | 6.820695 |
module avoid_latch_init ();
reg q;
reg enable, d;
always @(enable or d) begin
q = 0;
if (enable) begin
q = d;
end
end
initial begin
$monitor(" ENABLE = %b D = %b Q = %b", enable, d, q);
#1 enable = 0;
#1 d = 0;
#1 enable = 1;
#1 d = 1;
#1 d = 0;
#1 d = 1;
... | 6.746677 |
module avr109rx (
input rst,
input clk,
output [7:0] rx_data,
output rx_avail,
input rxd,
input rx_enabled
);
parameter CLK_FREQUENCY = 1000000;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; ... | 6.903906 |
module avr109tx (
input rst,
input clk,
input [7:0] tx_data,
input tx_avail,
output txd,
output tx_ready
);
parameter CLK_FREQUENCY = 1000000;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; lo... | 7.160051 |
module avRISC621_multicore_v (
Resetn_pin,
Clock_pin,
SW_pin,
PB_pin,
Display_pin
);
input Resetn_pin, Clock_pin;
// input I/OP
input [3:0] SW_pin;
input PB_pin;
// output I/OP
output [7:0] Display_pin;
wire [7:0] Master_out;
wire M_ack; // input to master, output from slave core
... | 7.697296 |
module avr_cpu (
input clk,
input rst,
output [5:0] io_addr,
inout [7:0] io_data,
output io_read,
output io_write
);
wire [15:0] opcode;
wire opcode_cycle;
wire hold;
wire [11:0] rjmp;
avr_cpu_fetch fetch (
.clk(clk),
.rst(rst),
.opcode(opcode),
.opcode_cycle(... | 6.949914 |
module avr_cpu_alu (
input [3:0] opcode,
input [7:0] r_in,
input [7:0] d_in,
output reg [7:0] out
);
always @(opcode, r_in, d_in) begin
//default values
out = r_in;
case (opcode)
`ALU_OP_MOVE: begin //nothing to do, default behaviour
end
endcase
end
endmodule
| 7.285923 |
module avr_cpu_progmem #(
parameter ADDR_WIDTH = 9,
parameter DATA_WIDTH = 16,
parameter MEM_SIZE = 512
) (
input clk,
input [ADDR_WIDTH-1:0] addr,
output reg [DATA_WIDTH-1:0] data
);
reg [DATA_WIDTH-1:0] mem[0:MEM_SIZE-1];
initial begin
$readmemh("prog.hex", mem);
end
always @(... | 7.096648 |
module avr_cpu_register (
input clk,
input rst,
input [4:0] r_addr,
input [4:0] d_addr,
output [7:0] r_out,
output [7:0] d_out,
input [7:0] d_in
);
reg [7:0] register_bank[0:31];
assign r_out = register_bank[r_addr];
assign d_out = register_bank[d_addr];
integer i;
always @(pose... | 6.687331 |
module avr_cpu_stack #(
parameter DATA_WIDTH = 9,
parameter STACK_DEPTH = 3,
parameter ADDR_WIDTH = $clog2(STACK_DEPTH + 1)
) (
input clk,
input rst,
input read,
input write,
inout [DATA_WIDTH-1:0] data
);
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] buffer[0:STACK_DEPTH-1];
... | 7.700549 |
module avr_gpio #(
parameter IO_ADDR = 0,
parameter PORT_WIDTH = 8
) (
input clk,
input rst,
input [5:0] io_addr,
inout [7:0] io_data,
input io_write,
input io_read,
inout [PORT_WIDTH-1:0] gpio
);
reg [PORT_WIDTH-1:0] DDR;
reg [PORT_WIDTH-1:0] PORT;
wire [PORT_WIDTH-1:0] PIN;... | 9.021294 |
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
) (
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive t... | 8.050013 |
module avr_timer #(
parameter IO_ADDR = 0
) (
input clk,
input rst,
input [5:0] io_addr,
inout [7:0] io_data,
input io_write,
input io_read,
input T0
);
reg [2:0] TCCR;
reg [7:0] TCNT;
reg [9:0] prescaler;
wire prescaled_clk;
reg prescaled_clk_prev;
assign prescaled_clk = ... | 7.195118 |
module avsdpll (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
inout vssd1, // User area 1 digital ground
`endif
output reg CLK,
input wire VCO_IN,
input wire ENb_CP,
input wire ENb_VCO,
input wire REF
);
`ifdef SIM
real period, lastedge, refpd;
initial begin
laste... | 7.05919 |
module avst2axis #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter KEEP_ENABLE = (DATA_WIDTH > 8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
) (
input wire clk,
input wire rst,
output wire avst_ready,
... | 7.900295 |
module avst_keccak (
clk,
reset,
data_in,
end_in,
valid_in,
ready_in,
data_out,
end_out,
valid_out,
ready_out
);
input clk;
input reset;
input [7:0] data_in;
input end_in;
input valid_in;
output ready_in;
output [7:0] data_out;
output end_out;
output valid_ou... | 6.881177 |
module avsvproc
#(parameter
NODE_NUM = 0,
AUTO_VALID_CSR = 0
)
(
input clk,
input rst_n,
// Avalon memory mapped master interface
output [31:0] avs_csr_address,
output avs_csr_write,
output [31:0] avs_csr_writedata,
output avs_csr_read,
input [31:0] avs_csr_read... | 6.517283 |
module is grenerated using the site: https://bues.ch/cms/hacking/crcgen
#
# Licence
#############
# This code is Public Domain.
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL ... | 7.28505 |
module crc (
crcIn,
data,
crcOut
);
input [31:0] crcIn;
input [7:0] data;
output [31:0] crcOut;
assign crcOut[0] = (crcIn[2] ^ crcIn[8] ^ data[2]);
assign crcOut[1] = (crcIn[0] ^ crcIn[3] ^ crcIn[9] ^ data[0] ^ data[3]);
assign crcOut[2] = (crcIn[0] ^ crcIn[1] ^ crcIn[4] ^ crcIn[10] ^ data[0] ^... | 7.40205 |
module avs_timing ( /*AUTOARG*/
// Outputs
avs_waitrequest,
// Inputs
sys_clk,
sys_rst,
avs_read,
avs_write
);
input sys_clk;
input sys_rst;
input avs_read;
input avs_write;
output avs_waitrequest;
reg register_ready_reg;
reg register_access_sreg;
always @(posedge sys_clk)... | 8.074207 |
module av_CAM_v (
we_n,
rd_n,
din,
argin,
addrs,
dout,
mbits
);
parameter arg_max = 9,
// addrs_max=2,
bl_max = 4;
input we_n;
input rd_n; // this is used for debugging, to check what value in a particular location of CAM
input [1:0] addrs; // 2-bits to address 4 groups
... | 8.519191 |
module operates 7-seg display based on mic input.
// Dependencies: NULL
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////
module AV_Indicator(
input DCLK, //6.25M
input RefSCLK, //20k
input SCLK, ... | 7.910961 |
module AV_integrator (
input clk65,
input pause,
input [12:0] menu_pixel,
input [12:0] score_pixel,
input [12:0] string1_pixel, //MSB is whether or not to use the pixel
input [12:0] string2_pixel,
input [12:0] string3_pixel,
input [12:0] string4_pixel,
input [12:0] string5_pixel,
... | 6.758334 |
module AV_menu_graphics (
input clk65,
input pause,
input [10:0] hcount,
input [9:0] vcount,
output reg [12:0] menu_pixel
);
localparam WIDTH = 800;
localparam HEIGHT = 200;
localparam COLOR = 12'hD_D_D;
localparam startX = 100;
localparam startY = 50;
always @(posedge clk65) begin
... | 6.661782 |
modules:
-- Function : This modules decodes Avalon MM transactions &
stalls each one by means of wait_req.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- $Header$
-... | 7.517477 |
module av_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
av_pll_0002 av_pll_inst (
.refclk (refclk), // refclk.clk
.rst ... | 7.047091 |
module av_pll2_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wi... | 6.625355 |
module av_pll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_mul... | 6.662034 |
module AV_sync_pipeline #(
parameter stages = 3
) (
input clk,
input hsync,
input vsync,
input blank,
output phsync,
output pvsync,
output pblank
);
reg [stages-1:0] h_pipe;
reg [stages-1:0] v_pipe;
reg [stages-1:0] b_pipe;
assign phsync = h_pipe[stages-1];
assign pvsync = v_... | 6.71857 |
module AWGN_Pipelined (
output wire signed [15:0] awgn_out,
input wire clk,
input wire reset,
input wire [31:0] urng_seed1,
input wire [31:0] urng_seed2,
input wire [31:0] urng_seed3,
input wire [31:0] urng_seed4,
input wire [31:0] urng_seed5,
input wire [31:0] urng_seed6
);
wire ... | 6.50439 |
module AWGN_Pipelined_tb ();
wire signed [15:0] awgn_out;
reg clk;
reg reset;
reg [31:0] urng_seed1;
reg [31:0] urng_seed2;
reg [31:0] urng_seed3;
reg [31:0] urng_seed4;
reg [31:0] urng_seed5;
reg [31:0] urng_seed6;
reg signed [15:0] expected_x0;
reg signed [15:0] expected_x1;
AWGN_Pipelined du... | 6.50439 |
module AWGN_tb ();
wire signed [15:0] x0;
wire signed [15:0] x1;
reg clk;
reg reset;
reg [31:0] urng_seed1;
reg [31:0] urng_seed2;
reg [31:0] urng_seed3;
reg [31:0] urng_seed4;
reg [31:0] urng_seed5;
reg [31:0] urng_seed6;
reg signed [15:0] expected_x0;
reg signed [15:0] expected_x1;
AWGN dut... | 7.243143 |
module controls ADC and four DPs via SPI interface. This module is interfaced with processing system 7 via a AXI GPIO with 2 channels ctri_i and ctrl_o.
// ctrl_i delivers four channel ADC values to processing system 7. Each ADC value is actually of 12bit but the value is packed as 8bit in ctrl_i.
// The four 8bit valu... | 7.73348 |
module ax309_mem (
input [13:0] addra,
input clka,
input [ 7:0] dina,
input wea,
output [ 7:0] douta
);
reg [ 7:0] mem [0:16383];
reg [13:0] areg;
reg wreg;
always @(posedge clka) begin
areg <= addra;
wreg <= wea;
if (wreg) mem[areg] <= dina;
end
... | 7.195711 |
module ax309_mem (
input [12:0] addra,
input clka,
input [15:0] dina,
input wea,
input [ 1:0] byteena,
output [15:0] douta
);
reg [15:0] mem [0:8191];
reg [12:0] areg;
reg [ 1:0] wreg;
always @(posedge clka) begin
areg <= addra;
wreg[0] <= wea & byteena[0];
... | 7.195711 |
module ax3_pll66 ( // Clock in ports
input inclk0,
// Clock out ports
output c0,
output c1,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(inclk0)
);
// Clocking primitive
//--... | 6.834641 |
module ax3_pll50 ( // Clock in ports
input inclk0,
// Clock out ports
output c0,
output c1,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(inclk0)
);
// Clocking primitive
//-... | 6.797378 |
module ALU(out, in1, in2, op);
parameter BITS = 16;
output reg [BITS-1:0] out;
input `REGSIZE in1, in2;
input `OPERATION_BITS op;
reg `REGSIZE a;
reg `REGSIZE temp;
always @(in1 or in2 or op) begin #1
case(op)
`OPadd: begin out <= in1 + in2; end
`OPsub: begin out <= in1 - in2; end
`OPxor: begin out <= in1 ^ in2;... | 6.767782 |
module AXA3 (
A,
B,
Cin,
Cout,
Sum
);
input A, B, Cin;
output Cout, Sum;
wire w1, w2, Vdd, Gnd;
assign Vdd = 1;
assign Gnd = 0;
pmos (w1, Vdd, A);
pmos (w2, w1, B);
nmos (w2, A, B);
nmos (w2, B, A);
nmos (Sum, Cin, w2);
pmos (Sum, Gnd, w2);
pmos (Cout, Cin, w2);
nmos (Co... | 6.788848 |
module ha (
input A,
B,
output S,
C
);
xor (S, A, B);
and (C, A, B);
endmodule
| 7.857591 |
module fa (
input A,
B,
Cin,
output Cout,
S
);
wire s1, c1, c2;
ha HA1 (
A,
B,
s1,
c1
);
ha HA2 (
s1,
Cin,
S,
c2
);
or OG1 (Cout, c1, c2);
endmodule
| 7.001699 |
module PREFIX_rd_fifo (
PORTS
);
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
port RGROUP_AXI_R;
input [DATA_BITS-1:0] HRDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input [ID_BITS-1:0] cmd_id;
input cmd_e... | 6.868724 |
module PREFIX_wr_fifo (
PORTS
);
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
port WGROUP_AXI_W;
port BGROUP_AXI_B;
output [DATA_BITS-1:0] HWDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input cmd_err;
in... | 7.16953 |
module PREFIX_mux (PORTS);
input clk;
input reset;
input [ADDR_BITS-1:0] cmd_addr;
input psel;
output [31:0] prdata;
output pready;
output pslverr;
output ... | 7.026796 |
module iob2axi #(
parameter AXI_ADDR_W = ADDR_W,
parameter AXI_DATA_W = DATA_W
) (
`include "s_axi_s_port.vh"
`include "m_axi_m_port.vh"
`include "iob_gen_if.vh"
);
`IOB_WIRE2WIRE(s_axi_awid, m_axi_awid, 1) //Address write channel ID
`IOB_WIRE2WIRE(s_axi_awaddr, m_axi_awaddr, AXI_ADDR_W) //Ad... | 8.122056 |
module axi2bram (
input wire RESETn,
input wire CLK,
input wire [7:0] TDATA,
input wire TVALID,
input wire TLAST,
output reg TREADY,
output reg [4:0] R,
output reg [4:0] G,
output reg [4:0] B,
output reg [18:0] index,
output wire valid
);
reg toggle;
//for verif
reg [... | 7.79679 |
module AXI2VGA (
input ACLK,
input ARESTN,
input [7:0] TDATA,
input TSTRB,
input TLAST,
input TVALID,
input TUSER,
output TREADY,
output reg H_SYNC,
output reg V_SYNC,
output DATA_EN,
output [7:0] pixel
);
// wire [7:0] pixel;
// reg H_SYNC, V_SYNC, DATA_EN;
... | 6.974086 |
module AXI4_LITE (
inout [31:0] data, //data from rx to file register
output reg wr_rd_en,
output reg [31:0] add,
// Global Signals
input ACLK,
ARESETN,
//Read Address Channel
input [31:0] ARADDR,
input ARVALID,
output reg ARREADY,
//Read Data Channel
input RREADY,
... | 6.851971 |
module AXI4_LITE (
inout [31:0] data, //data from rx to file register
output reg wr_en,
rd_en,
output reg [31:0] add,
// Global Signals
input ACLK,
ARESETN,
//Read Address Channel
input [31:0] ARADDR,
input ARVALID,
output reg ARREADY,
//Read Data Channel
input RR... | 6.851971 |
module axi4_lite_slave #(
parameter ADDR_WIDTH = 8,
parameter ADDR_WIDTH_SLAVE = 5,
parameter DATA_WIDTH = 32,
parameter STRB_WIDTH = DATA_WIDTH / 8,
parameter AXI_SLAVE_ADDR = 3'b000
) (
input reset,
input clk,
//write address chan... | 7.522589 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input [11:0] io_push_payload_addr,
input [2:0] io_push_payload_prot,
output reg io_pop_valid,
input io_pop_ready,
output reg [11:0] io_pop_payload_addr,
output reg [2:0] io_pop_payload_prot,
input io_flush,
... | 7.046487 |
module StreamFifoLowLatency_1_ (
input io_push_valid,
output io_push_ready,
input [31:0] io_push_payload_data,
input [3:0] io_push_payload_strobe,
output reg io_pop_valid,
input io_pop_ready,
output reg [31:0] io_pop_payload_data,
output reg [3:0] io_pop_payload_strobe,
input io_flus... | 7.046487 |
module StreamFifo (
input io_push_valid,
output io_push_ready,
input [1:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [1:0] io_pop_payload,
input io_flush,
output [0:0] io_occupancy,
output [0:0] io_availability,
input S_AXI_ACLK,
input S_AXI_ARESETN
);
... | 7.784627 |
module StreamFifo_1_ (
input io_push_valid,
output io_push_ready,
input [31:0] io_push_payload_data,
input [1:0] io_push_payload_resp,
output io_pop_valid,
input io_pop_ready,
output [31:0] io_pop_payload_data,
output [1:0] io_pop_payload_resp,
input io_flush,
output [0:0] io_occ... | 7.097915 |
module axi4mm_register_slice_wrap #(
parameter C_AXI_ID_WIDTH = 4
) (
input wire aclk,
input wire aresetn,
output wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid,
output wire [ 255 : 0] s_axi_rdata,
output wire [ 1 : 0] s_axi_rresp,... | 8.357672 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [15:0] io_axi_arw_payload_addr,
input [ 3:0] io_axi_arw_payload_id,
input [ 3:0] io_axi_arw_payload_region,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
... | 6.942764 |
module Axi4SharedSdramCtrlTester_tb (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [24:0] io_axi_arw_payload_addr,
input [1:0] io_axi_arw_payload_id,
input [7:0] io_axi_arw_payload_len,
input [2:0] io_axi_arw_payload_size,
input [1:0] io_axi_arw_payload_burst,
input io_axi_arw_... | 6.869498 |
module axi4_arb_onehot2 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [1:0] request_i
// Outputs
, output [1:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//----------------------------------... | 6.693687 |
module axi4_64_arb_onehot4 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [3:0] request_i
// Outputs
, output [3:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-------------------------------... | 6.983003 |
module axi4_arbiter_r (
input clk,
input rst,
input s0_ARVALID,
input s0_RREADY,
input s1_ARVALID,
input s1_RREADY,
input m_RVALID,
input m_RLAST,
// Bus grant
output [1:0] m_RGRNT
);
localparam [1:0] S_S0 = 2'b01;
loca... | 8.128662 |
module axi4_arbiter_w (
input clk,
input rst,
input s0_AWVALID,
input s0_BREADY,
input s1_AWVALID,
input s1_BREADY,
input m_BVALID,
// Bus grant
output [1:0] m_WGRNT
);
localparam [1:0] S_S0 = 2'b01;
localparam [1:0] S_S1 = 2'b10;... | 8.128662 |
module axi4_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axc... | 7.772393 |
module axi4_brdige (
input clk,
input rst,
//slave
input s_arvalid,
input [31:0] s_araddr,
input [7:0] s_arlen,
output reg s_rvalid,
output reg s_arready,
output reg [511:0] s_rdata,
input ddrWr,
input [31:0] ddrWrAddress,
input ddrWrEn,
input [511:0] ddrWrData,
... | 7.563781 |
module axi4_lite_master_fsm #
(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter STRB_WIDTH = (DATA_WIDTH/8)
)(
input wire ACLK,
input wire ARESETn,
// WRITE Address Channel
input wire S_AXI_AWREADY,
output wire S_AXI_AWVALID,
o... | 8.223194 |
module axi4_lite_slave_fsm #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter STRB_WIDTH = (DATA_WIDTH / 8)
) (
input wire ACLK,
input wire ARESETn,
// WRITE Address Channel
output wire S_AXI_AWREADY,
input wire S_AXI_AWVALID,
input... | 7.522589 |
module axi4_lite_slave_pwm (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
output... | 7.522589 |
module axi4_lite_slave_spi (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
output... | 7.522589 |
module axi4_lite_slave_tb #(
parameter addr_width = 3,
parameter data_width = 32,
parameter strb_width = 4
) ();
// Global signals
reg aclk;
reg aresetn;
// write address channel
reg awvalid;
wire awready;
reg [addr_width-1:0] awaddr;
reg awprot;
// write data channel
reg wvalid;
w... | 7.522589 |
module axi4_lite_slave_uart (
input s_axi_aclk_i,
input s_axi_aresetn_i,
// READ SIGNALS
// ar -> address read (address in)
// r -> read (data out)
input [31:0] s_axi_araddr_i,
output s_axi_arready_o,
input s_axi_arvalid_i,
input s_axi_rready_i,
... | 7.522589 |
module axi4_mem (
input clock,
input rst_n,
output io_slave_awready,
input io_slave_awvalid,
input [31:0] io_slave_awaddr,
input [ 3:0] io_slave_awid,
input [ 7:0] io_slave_awlen,
input [ 2:0] io_slave_awsize,
input [ 1:0] io_slave_awburst,
out... | 7.19552 |
module sdram_axi_pmem_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-------------------------------------------------------------... | 7.184129 |
modules
//-----------------------------------------------------------------
module axi4retime_fifo2x37
(
// Inputs
input clk_i
,input rst_i
,input [ 36:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 36:0] data_out_o
,output ... | 7.831093 |
modules
//-----------------------------------------------------------------
module axi4_retime256_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ... | 7.831093 |
module axi4_stream_reader #(
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
/* axi4-stream ports */
input wire S_AXIS_ACLK,
input wire S_AXIS_ARESETN,
output wire S_AXIS_TREADY,
input wire [ ... | 9.187641 |
module axi4_stream_slave #(
parameter DATABUSWIDTH = 16, //in bytes
parameter TDESTWIDTH = 2, // in bits
parameter TUSERWIDTH = 22, // in bits
parameter FIFODATAWIDTH = 132, // in bits
parameter TDESTADDR = 2'b01
) (
//common signals
input clk,
input ... | 7.393094 |
module axi_stream_writer #(
parameter integer C_M_AXIS_TDATA_WIDTH = 32
) (
input wire start, // FIXME: sil
input wire [ C_M_AXIS_TDATA_WIDTH-1:0] data,
input wire data_valid,
input wire ... | 8.69241 |
module AXI4_Template_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to ad... | 7.074031 |
module axi4_tester #(
parameter P_TARGET_SLAVE_BASE_ADDR = 32'h0, //Base address of targeted slave
parameter integer P_WRITE_BURSTS = 1, //Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer P_READ_BURSTS = 16, ... | 8.655463 |
module AXI4_TO_PINGPONG #(
parameter ADDRBITS = 7,
DATABITS = 16,
MEMDEPTH = 128,
USETLAST = 0
) (
input clk,
input rst,
output [ADDRBITS-1:0] addra,
output wea,
output [DATABITS-1:0] dina,
output finisha,
input readya,
input [DATABITS-1:0] s_axis_data_tdata,
output s... | 7.08562 |
module axi4_upconv256_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//--------------------------------------------------------------... | 7.078253 |
module axi4_w_reg_slice (
wreadys,
wvalidm,
wdatam,
wstrbm,
wlastm,
wuserm,
aclk,
aresetn,
wvalids,
wdatas,
wstrbs,
wlasts,
wusers,
wreadym
);
parameter DATA_WIDTH = 32;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter STRB_WID... | 8.13981 |
module axi64_to_ll8 #(
parameter START_BYTE = 6
) (
input clk,
input reset,
input clear,
input [63:0] axi64_tdata,
input axi64_tlast,
input [3:0] axi64_tuser,
input axi64_tvalid,
output axi64_tready,
output [7:0] ll_data,
output ll_eof,
output ll_src_rdy,
input ll_dst... | 6.927426 |
module axi64_to_xge64 (
input clk,
input reset,
input clear,
input [63:0] s_axis_tdata,
input [3:0] s_axis_tuser,
input s_axis_tlast,
input s_axis_tvalid,
output s_axis_tready,
output [63:0] m_axis_tdata,
output [3:0] m_axis_tuser,
output m_axis_tlast,
output m_axis_tvali... | 9.061511 |
module AXIBridge (
input clk,
input rst_n,
// AXI slave interface
input [ 5:0] axi_arid,
input [31:0] axi_araddr,
input [ 7:0] axi_arlen,
input [ 2:0] axi_arsize,
input [ 1:0] axi_arburst,
input [ 1:0] axi_arlock,
input [ 3:0] axi_arcache,
input [ 2:0]... | 7.506279 |
module absorbs not-ready cycles from the AXI core as well as our own RX logic so that the two don't mess each other up.
// Once Xilinx fixes their bugs, this will probably be unnecessary.
`include "PicoDefines.v"
module AXIBuffer (
input clk,
input rst,
// AXI-S
input [127:0] s... | 6.748701 |
module axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] w... | 7.03357 |
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