code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module implements a basic slave configuration status interface
* compatible with the Altera Avalon Memory Mapped Interface standard.
*
* Such interfaces are typically used in large processor controlled
* systems to allow memory mapped access to peripherals. The Leeds SoC
* Computer design used for the ELEC5620M module makes use of a number
* of peripherals based around this interface style controlled by the
* ARM CPU on the Cyclone V SoC.
*/
module AvalonMMSlaveTemplate ( /*!\tikzmark{avmm_codeedge}!*/
input clock,
input reset,
//Typical CSR Interface
input [ 0:0] csr_address, //Lets say a 1-bit address. Can be any width
input csr_chipselect,
input csr_write,
input [31:0] csr_writedata, //We'll use a 32-bit data bus, common for CPUs
input [ 3:0] csr_byteenable, //32-bit = 4 bytes, so we need four enable bits
input csr_read,
output reg [31:0] csr_readdata //A 32-bit read data bus
);
//Internal Variables
reg [15:0] oneSignal; //We need registers for all signals that we will be writing
reg [ 7:0] twoSignal; //to in the CSR. They can be any width you want.
//Set up the Read Data Map for the CSR. /*!\tikzmark{avmm_readstart}!*/
//Input signals are mapped to correct bits at the correct addresses here.
wire [31:0] readMap [1:0];
assign readMap[0] = { 16'b0, oneSignal };
assign readMap[1] = { twoSignal, 24'b0 };
//... so on for other addresses
always @ (posedge clock) begin
if (csr_read && csr_chipselect) begin //when CSR read is asserted
csr_readdata <= dataToMaster[csr_address]; //Read from CSR map
end
end /*!\tikzmark{avmm_readend}!*/
//Convert byte enable signal into bit enable. Basically each group of 8 bits /*!\tikzmark{avmm_bestart}!*/
//is assigned to the value of the corresponding byte enable.
wire [31:0] bitenable;
assign bitenable = {{8{csr_byteenable[3]}},
{8{csr_byteenable[2]}},
{8{csr_byteenable[1]}},
{8{csr_byteenable[0]}}}; /*!\tikzmark{avmm_beend}!*/
//Next comes the Write logic /*!\tikzmark{avmm_writestart}!*/
wire [31:0] maskedWrite;
assign maskedWrite = csr_writedata & bitenable; //Mask off disabled bits
always @ (posedge clock or posedge reset) begin
if (reset) begin
oneSignal <= 16'b0;
twoSignal <= 8'b0;
end else if (csr_write && csr_chipselect) begin //When a write is issued
//update the registers at the corresponding address.
if (csr_address == 1'd0) begin //You could also use a case statement
oneSignal <= (oneSignal & ~bitenable[0+:16]) | maskedWrite[0+:16];
//We have one line here for each of the registers we can write to.
//Each clears bits being written, and then ORs in the write data
end
if (csr_address == 1'd1) begin
twoSignal <= (twoSignal & ~bitenable[24+:8]) | maskedWrite[24+:8];
end
end
end /*!\tikzmark{avmm_writeend}!*/
//... End CSR ...
endmodule
| 6.904081 |
module avalonslavetestbench (
input wire [63:0] avalon_writedata, // avalon.writedata
input wire [ 7:0] avalon_burstcount, // .burstcount
output wire [63:0] avalon_readdata, // .readdata
input wire [28:0] avalon_address, // .address
output wire avalon_waitrequest, // .waitrequest
input wire avalon_write, // .write
input wire avalon_read, // .read
input wire [ 7:0] avalon_byteenable, // .byteenable
output wire avalon_readdatavalid, // .readdatavalid
input wire clk_clk, // clk.clk
input wire reset_reset // reset.reset
);
altera_avalon_mm_slave_bfm #(
.AV_ADDRESS_W (29),
.AV_SYMBOL_W (8),
.AV_NUMSYMBOLS (8),
.AV_BURSTCOUNT_W (8),
.AV_READRESPONSE_W (8),
.AV_WRITERESPONSE_W (8),
.USE_READ (1),
.USE_WRITE (1),
.USE_ADDRESS (1),
.USE_BYTE_ENABLE (1),
.USE_BURSTCOUNT (1),
.USE_READ_DATA (1),
.USE_READ_DATA_VALID (1),
.USE_WRITE_DATA (1),
.USE_BEGIN_TRANSFER (0),
.USE_BEGIN_BURST_TRANSFER (0),
.USE_WAIT_REQUEST (1),
.USE_TRANSACTIONID (0),
.USE_WRITERESPONSE (0),
.USE_READRESPONSE (0),
.USE_CLKEN (0),
.AV_BURST_LINEWRAP (1),
.AV_BURST_BNDR_ONLY (1),
.AV_MAX_PENDING_READS (1),
.AV_MAX_PENDING_WRITES (0),
.AV_FIX_READ_LATENCY (0),
.AV_READ_WAIT_TIME (1),
.AV_WRITE_WAIT_TIME (0),
.REGISTER_WAITREQUEST (0),
.AV_REGISTERINCOMINGSIGNALS(0),
.VHDL_ID (0)
) mm_slave_bfm_0 (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.avs_writedata (avalon_writedata), // s0.writedata
.avs_burstcount (avalon_burstcount), // .burstcount
.avs_readdata (avalon_readdata), // .readdata
.avs_address (avalon_address), // .address
.avs_waitrequest (avalon_waitrequest), // .waitrequest
.avs_write (avalon_write), // .write
.avs_read (avalon_read), // .read
.avs_byteenable (avalon_byteenable), // .byteenable
.avs_readdatavalid (avalon_readdatavalid), // .readdatavalid
.avs_begintransfer (1'b0), // (terminated)
.avs_beginbursttransfer (1'b0), // (terminated)
.avs_arbiterlock (1'b0), // (terminated)
.avs_lock (1'b0), // (terminated)
.avs_debugaccess (1'b0), // (terminated)
.avs_transactionid (8'b00000000), // (terminated)
.avs_readid (), // (terminated)
.avs_writeid (), // (terminated)
.avs_clken (1'b1), // (terminated)
.avs_response (), // (terminated)
.avs_writeresponserequest(1'b0), // (terminated)
.avs_writeresponsevalid (), // (terminated)
.avs_readresponse (), // (terminated)
.avs_writeresponse () // (terminated)
);
endmodule
| 7.375926 |
module avalon_bridge (
clk,
reset_n,
avl_master_ready,
avl_master_addr,
avl_master_rdata_valid,
avl_master_rdata,
avl_master_wdata,
avl_master_be,
avl_master_read_req,
avl_master_write_req,
avl_master_size,
avl_slave_ready,
avl_slave_addr,
avl_slave_rdata_valid,
avl_slave_rdata,
avl_slave_wdata,
avl_slave_be,
avl_slave_read_req,
avl_slave_write_req,
avl_slave_size
);
// Parameters
parameter ADDR_WIDTH = 64;
parameter DATA_WIDTH_M = 64;
parameter BE_WIDTH_M = 8;
parameter DATA_WIDTH_S = 64;
parameter BE_WIDTH_S = 8;
parameter MAX_BSIZE = 1;
// Clock and reset
input clk;
input reset_n;
// Master interface
input avl_master_ready; // avl.waitrequest_n
output [ADDR_WIDTH-1:0] avl_master_addr; // .address
input avl_master_rdata_valid; // .readdatavalid
input [DATA_WIDTH_M-1:0] avl_master_rdata; // .readdata
output [DATA_WIDTH_M-1:0] avl_master_wdata; // .writedata
output [BE_WIDTH_M-1:0] avl_master_be; // .byteenable
output avl_master_read_req; // .read
output avl_master_write_req; // .write
output [MAX_BSIZE-1:0] avl_master_size;
// Slave Interface
output avl_slave_ready; // avl.waitrequest_n
input [ADDR_WIDTH-1:0] avl_slave_addr; // .address
output avl_slave_rdata_valid; // .readdatavalid
output [DATA_WIDTH_S-1:0] avl_slave_rdata; // .readdata
input [DATA_WIDTH_S-1:0] avl_slave_wdata; // .writedata
input [BE_WIDTH_S-1:0] avl_slave_be; // .byteenable
input avl_slave_read_req; // .read
input avl_slave_write_req; // .write
input [MAX_BSIZE-1:0] avl_slave_size;
assign avl_slave_ready = avl_master_ready;
assign avl_master_addr = avl_slave_addr;
assign avl_slave_rdata_valid = avl_master_rdata_valid;
assign avl_master_size = avl_slave_size;
generate
if (DATA_WIDTH_S < DATA_WIDTH_M) begin
assign avl_slave_rdata = avl_master_rdata[DATA_WIDTH_S-1:0];
assign avl_master_wdata = {{DATA_WIDTH_M - DATA_WIDTH_S{1'b0}}, avl_slave_wdata};
assign avl_master_be = {{BE_WIDTH_M - BE_WIDTH_S{1'b0}}, avl_slave_be};
end else begin
assign avl_slave_rdata = {{DATA_WIDTH_S - DATA_WIDTH_M{1'b0}}, avl_master_rdata};
assign avl_master_wdata = avl_slave_wdata[DATA_WIDTH_M-1:0];
assign avl_master_be = avl_slave_be[BE_WIDTH_M-1:0];
end
endgenerate
assign avl_master_read_req = avl_slave_read_req;
assign avl_master_write_req = avl_slave_write_req;
endmodule
| 9.232811 |
module avalon_combiner (
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [ 6:0] mixer_address, // ctl_mixer.address
output wire [ 3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0] mixer_writedata, // .writedata
input wire mixer_waitrequest, // .waitrequest
output wire [ 6:0] scaler_address, // ctl_scaler.address
output wire [ 3:0] scaler_byteenable, // .byteenable
input wire scaler_waitrequest, // .waitrequest
output wire scaler_write, // .write
output wire [31:0] scaler_writedata, // .writedata
output wire [ 7:0] video_address, // ctl_video.address
output wire [ 3:0] video_byteenable, // .byteenable
input wire video_waitrequest, // .waitrequest
output wire video_write, // .write
output wire [31:0] video_writedata, // .writedata
output wire clock, // control.clock
output wire reset, // .reset
input wire [ 8:0] address, // .address
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire waitrequest // .waitrequest
);
assign clock = clk;
assign reset = rst;
assign mixer_address = address[6:0];
assign scaler_address = address[6:0];
assign video_address = address[7:0];
assign mixer_byteenable = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable = 4'b1111;
wire en_scaler = (address[8:7] == 0);
wire en_mixer = (address[8:7] == 1);
wire en_video = address[8];
assign mixer_write = en_mixer & write;
assign scaler_write = en_scaler & write;
assign video_write = en_video & write;
assign mixer_writedata = writedata;
assign scaler_writedata = writedata;
assign video_writedata = writedata;
assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
endmodule
| 7.592648 |
module avalon_dc_fifo (
reset_ext_reset_n,
clk_int_clk,
reset_int_reset_n,
clk_ext_clk,
dc_fifo_in_data,
dc_fifo_in_valid,
dc_fifo_in_ready,
dc_fifo_out_data,
dc_fifo_out_valid,
dc_fifo_out_ready
);
input reset_ext_reset_n;
input clk_int_clk;
input reset_int_reset_n;
input clk_ext_clk;
input [63:0] dc_fifo_in_data;
input dc_fifo_in_valid;
output dc_fifo_in_ready;
output [63:0] dc_fifo_out_data;
output dc_fifo_out_valid;
input dc_fifo_out_ready;
endmodule
| 7.191061 |
module avalon_dvp_wch #(
parameter AM_DATA_WIDTH = 16,
parameter AM_MAX_BURST_COUNT = 4,
parameter AM_BURST_COUNT_WIDTH = 3,
parameter AM_ADDRESS_WIDTH = 32,
parameter AM_FIFO_DEPTH = 32,
parameter AM_FIFO_DEPTH_LOG2 = 5,
parameter AM_MEMORY_BASED_FIFO = 1 // set to 0 to use LEs instead
) (
input clk,
input reset,
// slave control register
input [ 1:0] as_address, //0x0-dvp_reset, 0x0-stream_address
input as_read,
output reg [31:0] as_readdata,
input as_write,
input [31:0] as_writedata,
// master write
output am_write,
output [ AM_DATA_WIDTH-1:0] am_writedata,
output [ AM_ADDRESS_WIDTH-1:0] am_address,
output [AM_BURST_COUNT_WIDTH-1:0] am_burstcount,
input am_waitrequest,
input pclk,
input href,
input vsync,
input [AM_DATA_WIDTH-1:0] raw
);
//mm control register
reg wch_reset;
reg [31:0] buff_addr;
reg [31:0] buff_size;
always @(posedge clk or posedge reset) begin
if (reset) begin
wch_reset <= 1;
buff_addr <= 0;
buff_size <= 0;
end else begin
if (as_read) begin
case (as_address)
2'd0: as_readdata <= {31'd0, wch_reset};
2'd1: as_readdata <= buff_addr;
2'd2: as_readdata <= buff_size;
default: as_readdata <= 0;
endcase
end
if (as_write) begin
case (as_address)
2'd0: wch_reset <= as_writedata[0];
2'd1: buff_addr <= as_writedata;
2'd2: buff_size <= as_writedata;
default: ;
endcase
end
end
end
// control inputs and outputs
reg prev_vsync;
always @(posedge clk) prev_vsync <= vsync;
reg control_go;
reg vsync_edge;
always @(posedge clk or posedge wch_reset) begin
if (wch_reset) begin
control_go <= 1'b0;
vsync_edge <= 1'b0;
end else if (!prev_vsync && vsync) begin
control_go <= 1'b1;
vsync_edge <= 1'b1;
end else begin
control_go <= 1'b0;
vsync_edge <= vsync_edge;
end
end
burst_write_master burst_write_master (
.clk(clk),
.reset(wch_reset),
.control_fixed_location(1'b0),
.control_write_base(buff_addr),
.control_write_length(buff_size),
.control_go(control_go),
.control_done(),
.user_write_clk(pclk),
.user_write_buffer(href & vsync_edge),
.user_buffer_data(raw),
.user_buffer_full(),
.master_address(am_address),
.master_write(am_write),
.master_byteenable(),
.master_writedata(am_writedata),
.master_burstcount(am_burstcount),
.master_waitrequest(am_waitrequest)
);
defparam burst_write_master.DATAWIDTH = AM_DATA_WIDTH;
defparam burst_write_master.MAXBURSTCOUNT = AM_MAX_BURST_COUNT;
defparam burst_write_master.BURSTCOUNTWIDTH = AM_BURST_COUNT_WIDTH;
defparam burst_write_master.BYTEENABLEWIDTH = AM_DATA_WIDTH / 8;
defparam burst_write_master.ADDRESSWIDTH = AM_ADDRESS_WIDTH;
defparam burst_write_master.FIFODEPTH = AM_FIFO_DEPTH;
defparam burst_write_master.FIFODEPTH_LOG2 = AM_FIFO_DEPTH_LOG2;
defparam burst_write_master.FIFOUSEMEMORY = AM_MEMORY_BASED_FIFO;
endmodule
| 9.18688 |
module avalon_gen (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0_debugaccess
);
input clk_clk;
input reset_reset_n;
output mm_bridge_s0_waitrequest;
output [31:0] mm_bridge_s0_readdata;
output mm_bridge_s0_readdatavalid;
input [0:0] mm_bridge_s0_burstcount;
input [31:0] mm_bridge_s0_writedata;
input [23:0] mm_bridge_s0_address;
input mm_bridge_s0_write;
input mm_bridge_s0_read;
input [3:0] mm_bridge_s0_byteenable;
input mm_bridge_s0_debugaccess;
endmodule
| 8.545607 |
module avalon_gen_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
//
tx_ready,
tx_data,
tx_valid,
tx_sop,
tx_eop,
tx_empty,
tx_error,
input_10g_data,
// outputs:
readdata
);
parameter INIT_FILE = "avalon_gen_onchip_memory2_0.hex";
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
input tx_ready; // Avalon-ST Ready Input
output wire [63:0] tx_data; // Avalon-ST TX Data
output wire tx_valid; // Avalon-ST TX Valid
output wire tx_sop; // Avalon-ST TX StartOfPacket
output wire tx_eop; // Avalon-ST TX EndOfPacket
output wire [2:0] tx_empty; // Avalon-ST TX Empty
output wire tx_error; // Avalon-ST TX Error
input wire [63:0] input_10g_data;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
//.q_a (readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//========================================================================================================
avalon_st_gen GEN (
// _______________________________________________________________
.clk (clk), // Tx clock
.reset (reset), // Reset signal
.address (address), // Avalon-MM Address
.write (wren), // Avalon-MM Write Strobe
.writedata(writedata), // Avalon-MM Write Data
//.read (avl_mm_read & blk_sel_gen), // Avalon-MM Read Strobe
.readdata (readdata), // Avalon-MM Read Data
//.waitrequest (waitrequest_gen),
.tx_data (tx_data), // Avalon-ST Data
.tx_valid (tx_valid), // Avalon-ST Valid
.tx_sop (tx_sop), // Avalon-ST StartOfPacket
.tx_eop (tx_eop), // Avalon-ST EndOfPacket
.tx_empty (tx_empty), // Avalon-ST Empty
.tx_error (tx_error), // Avalon-ST Error
.tx_ready (tx_ready),
.input_10g_data(input_10g_data)
);
// ___________________________________________________________________
endmodule
| 7.777361 |
module avalon_io12_4_switcher (
clk,
select,
sink_data_0,
sink_valid_0,
sink_error_0,
sink_data_1,
sink_valid_1,
sink_error_1,
sink_data_2,
sink_valid_2,
sink_error_2,
sink_data_3,
sink_valid_3,
sink_error_3,
source_data,
source_valid,
source_error
);
input wire clk;
input wire [1:0] select;
input wire [11:0] sink_data_0, sink_data_1, sink_data_2, sink_data_3;
input wire sink_valid_0, sink_valid_1, sink_valid_2, sink_valid_3;
input wire [1:0] sink_error_0, sink_error_1, sink_error_2, sink_error_3;
output reg [11:0] source_data;
output reg source_valid;
output reg [1:0] source_error;
// Mux between the four input Avalon data sinks
always @(posedge clk) begin
case (select)
2'b00: begin
source_data <= sink_data_0;
source_valid <= sink_valid_0;
source_error <= sink_error_0;
end
2'b01: begin
source_data <= sink_data_1;
source_valid <= sink_valid_1;
source_error <= sink_error_1;
end
2'b10: begin
source_data <= sink_data_2;
source_valid <= sink_valid_2;
source_error <= sink_error_2;
end
2'b11: begin
source_data <= sink_data_3;
source_valid <= sink_valid_3;
source_error <= sink_error_3;
end
default: begin
source_data <= sink_data_0;
source_valid <= sink_valid_0;
source_error <= sink_error_0;
end
endcase
end
endmodule
| 8.688105 |
module avalon_jtag_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.398354 |
module to simplify having a register of variable width and containing independent byte lanes
module register_with_bytelanes (
clk,
reset,
data_in,
write,
byte_enables,
data_out
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input [DATA_WIDTH-1:0] data_in;
input write;
input [(DATA_WIDTH/8)-1:0] byte_enables;
output reg [DATA_WIDTH-1:0] data_out;
// generating write logic for each group of 8 bits for 'data_out'
generate
genvar LANE;
for(LANE = 0; LANE < (DATA_WIDTH/8); LANE = LANE+1)
begin: register_bytelane_generation
always @ (posedge clk or posedge reset)
begin
if(reset == 1)
begin
data_out[(LANE*8)+7:(LANE*8)] <= 0;
end
else
begin
if((byte_enables[LANE] == 1) & (write == 1))
begin
data_out[(LANE*8)+7:(LANE*8)] <= data_in[(LANE*8)+7:(LANE*8)]; // write to each byte lane with write = 1 and the lane byteenable = 1
end
end
end
end
endgenerate
endmodule
| 8.882302 |
module avalon_mon (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0_debugaccess
);
input clk_clk;
input reset_reset_n;
output mm_bridge_s0_waitrequest;
output [31:0] mm_bridge_s0_readdata;
output mm_bridge_s0_readdatavalid;
input [0:0] mm_bridge_s0_burstcount;
input [31:0] mm_bridge_s0_writedata;
input [23:0] mm_bridge_s0_address;
input mm_bridge_s0_write;
input mm_bridge_s0_read;
input [3:0] mm_bridge_s0_byteenable;
input mm_bridge_s0_debugaccess;
endmodule
| 7.945003 |
module avalon_motor (
input pwm_clk,
data_clk,
input [11:0] ast_sink_data,
input [1:0] ast_sink_error,
input ast_sink_valid,
output reg outh,
outl,
output reg update
);
//
reg [11:0] last_valid_data;
reg [11:0] data_sync0, data_sync1, data_sync2;
reg signed [9:0] pwm_counter;
reg signed [9:0] pwm_target, next_pwm_target;
// Accept AST input in data_clk domain
always @(posedge data_clk) begin
if (ast_sink_valid) begin
last_valid_data <= ast_sink_data;
end else begin
last_valid_data <= last_valid_data;
end
end
// Clock domain transfer
// Requires f_{data_clk} < f_{pwm_clk} since ast_sink_valid is 1-cycle data_clk pulses
// Assumes that ast_sink_valid has infrequent edges since it's pulses
always @(posedge pwm_clk) begin
data_sync2 <= data_sync1;
data_sync1 <= data_sync0;
data_sync0 <= last_valid_data;
// Resultant signal for transfer, truncated down to 10 bits
next_pwm_target <= data_sync2[11:2];
end
// PWM generation
always @(posedge pwm_clk) begin
pwm_counter <= pwm_counter + 1'b1;
// Transfer to pwm_target at PWM cycle's desired value
if (pwm_counter == 0) begin
pwm_target <= next_pwm_target;
update <= 1'b1; // Indicate that the PWM updated
end else begin
pwm_target <= pwm_target;
update <= 1'b0;
end
// PWM comparator
if (pwm_counter < pwm_target) begin
outh <= 1'b0;
outl <= 1'b1;
end else begin
outh <= 1'b1;
outl <= 1'b0;
end
end
endmodule
| 7.309496 |
module avalon_ram #(
parameter ADW = 32, // data width
parameter ABW = ADW/8, // byte enable width
parameter ASZ = 1024, // memory size
parameter AAW = $clog2(ASZ/ABW) // address width
)(
// system signals
input clk, // clock
input rst, // reset
// Avalon MM interface
input read,
input write,
input [AAW-1:0] address,
input [ABW-1:0] byteenable,
input [ADW-1:0] writedata,
output [ADW-1:0] readdata,
output waitrequest
);
wire transfer;
reg [ADW-1:0] mem [0:ASZ-1];
reg [AAW-1:0] address_d;
reg data_valid;
//////////////////////////////////////////////////////////////////////////////
// memory implementation
//////////////////////////////////////////////////////////////////////////////
genvar i;
// write access (writedata is written the same clock period write is asserted)
generate for (i=0; i<ABW; i=i+1) begin : byte
// generate code for for each byte in a word
always @ (posedge clk)
if (write & byteenable[i]) mem[address][8*i+:8] <= writedata[8*i+:8];
end endgenerate
// read access (readdata is available one clock period after read is asserted)
always @ (posedge clk)
if (read) address_d <= address;
assign readdata = mem[address_d];
//////////////////////////////////////////////////////////////////////////////
// avalon interface code
//////////////////////////////////////////////////////////////////////////////
// transfer cycle end
assign transfer = (read | write) & ~waitrequest;
always @ (posedge clk)
data_valid <= read & ~data_valid;
// read, write cycle timing
assign waitrequest = ~(write | data_valid);
endmodule
| 9.267528 |
module avalon_rgb_led_bargraph_dpram512x8 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
| 7.640926 |
module avalon_rgb_led_bargraph_slave (
// clocks and resets
input wire clock,
input wire resetn,
// avalon bus
input wire read,
input wire write,
input wire chipselect,
input wire [3:0] address,
input wire [3:0] byteenable,
input wire [31:0] writedata,
output reg [31:0] readdata,
output reg mtrx_wr,
output reg [8:0] mtrx_wr_addr,
output reg [7:0] mtrx_wr_data,
output reg mtrx_buffer_select,
input wire mtrx_buffer_current,
output reg [8:0] mtrx_level,
output reg [23:0] timebase_reset_value,
input wire timebase_flag,
output reg timebase_flag_clear,
output reg [7:0] leds
);
reg [31:0] slv_reg0;
reg [31:0] slv_reg1;
reg [31:0] slv_reg2;
reg [31:0] slv_reg3;
reg [ 8:0] mtrx_addr;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
readdata <= 0;
mtrx_addr <= 0;
mtrx_wr <= 0;
mtrx_wr_addr <= 0;
mtrx_wr_data <= 0;
mtrx_buffer_select <= 0;
mtrx_level <= 9'h100;
timebase_reset_value <= 1_666_666;
timebase_flag_clear <= 0;
slv_reg0 <= 32'hdeadbeef;
slv_reg1 <= 32'hbeefcafe;
slv_reg2 <= 32'habad1dea;
slv_reg3 <= 32'hbad1dea5;
mtrx_addr <= 0;
leds <= 8'haa;
end else begin
mtrx_wr <= 0;
timebase_flag_clear <= (chipselect && write && (byteenable == 4'b1111)) && (address == 4'h05) && writedata[0];
if (chipselect && write && (byteenable == 4'b1111)) begin
case (address)
4'h0: mtrx_addr <= writedata[8:0];
4'h1: begin
mtrx_addr <= mtrx_addr + 1;
mtrx_wr <= 1;
mtrx_wr_addr <= mtrx_addr;
mtrx_wr_data <= writedata[7:0];
end
4'h2: mtrx_buffer_select <= writedata[0];
4'h3: mtrx_level <= writedata[8:0];
4'h4: timebase_reset_value <= writedata[23:0];
4'h6: leds <= writedata[7:0];
endcase
end
if (chipselect && read && (byteenable == 4'b1111)) begin
case (address)
4'h0 : readdata <= slv_reg0;
4'h1 : readdata <= slv_reg1;
4'h2 : readdata <= slv_reg2;
4'h3 : readdata <= slv_reg3;
4'h4 : readdata <= { 8'b0, timebase_reset_value };
4'h5 : readdata <= { 31'b0, timebase_flag };
default: readdata <= 0;
endcase
end
end
end
endmodule
| 7.640926 |
module avalon_sha3_wrapper (
clk, // clock.clk
reset, // reset.reset
// Memory mapped read/write slave interface
avs_s0_address,
avs_s0_read,
avs_s0_write,
avs_s0_writedata,
avs_s0_readdata,
avs_s0_waitrequest
);
input clk; // clock.clk
input reset; // reset.reset
// Memory mapped read/write slave interface
input [7:0] avs_s0_address;
input avs_s0_read;
input avs_s0_write;
input [31:0] avs_s0_writedata;
output [31:0] avs_s0_readdata;
output avs_s0_waitrequest;
wire [31:0] avs_s0_readdata;
wire avs_s0_waitrequest;
wire rst_n;
reg state_read;
wire cs;
wire we;
reg [31:0] write_data;
wire [31:0] read_data;
wire reg_status_valid;
assign rst_n = ~reset;
assign cs = (avs_s0_read || avs_s0_write);
assign we = avs_s0_write;
assign avs_s0_waitrequest = ~reg_status_valid && avs_s0_read;
sha3_wrapper sha3_wr (
.clk (clk),
.rst_n (rst_n),
.cs (cs),
.we (we),
.address (avs_s0_address),
.write_data (avs_s0_writedata),
.read_data (avs_s0_readdata),
.reg_status_valid(reg_status_valid)
);
endmodule
| 7.750582 |
module avalon_shell_rsa (
clk,
reset,
//avalon_MM_to_qsys
avm_m0_waitrequest,
avm_m0_address,
avm_m0_read,
avm_m0_write,
avm_m0_readdatavalid,
avm_m0_readdata,
avm_m0_writedata,
//avalon_MM_to_design
avm_design_m0_waitrequest,
avm_design_m0_address,
avm_design_m0_read,
avm_design_m0_write,
avm_design_m0_readdatavalid,
avm_design_m0_readdata,
avm_design_m0_writedata,
//avalon_MM_s0 to qsys
avs_s0_waitrequest,
avs_s0_address,
avs_s0_read,
avs_s0_write,
avs_s0_readdata,
avs_s0_writedata,
//avalon_MM_s0 to design
avm_design_s0_waitrequest,
avm_design_s0_address,
avm_design_s0_read,
avm_design_s0_write,
avm_design_s0_readdata,
avm_design_s0_writedata
);
//-------- input ---------------------------
input clk;
input reset;
//-------- avalon_MM_master --------------------------------------
input avm_m0_waitrequest;
output [31:0] avm_m0_address; //
output avm_m0_read; //
output avm_m0_write; //
input avm_m0_readdatavalid;
input [255:0] avm_m0_readdata;
output [255:0] avm_m0_writedata; //
//-------- avalon_MM_to_design --------------------------------------
output avm_design_m0_waitrequest;
input [31:0] avm_design_m0_address; //
input avm_design_m0_read; //
input avm_design_m0_write; //
output avm_design_m0_readdatavalid;
output [255:0] avm_design_m0_readdata;
input [255:0] avm_design_m0_writedata; //
//avalon_MM_s0 to qsys
output avs_s0_waitrequest;
input avs_s0_address;
input avs_s0_read;
input avs_s0_write;
output [127:0] avs_s0_readdata;
input [127:0] avs_s0_writedata;
//avalon_MM_s0 to design
input avm_design_s0_waitrequest;
output avm_design_s0_address;
output avm_design_s0_read;
output avm_design_s0_write;
input [7:0] avm_design_s0_readdata;
output [7:0] avm_design_s0_writedata;
assign avm_design_m0_waitrequest = avm_m0_waitrequest;
assign avm_m0_address = avm_design_m0_address; //
assign avm_m0_read = avm_design_m0_read; //
assign avm_m0_write = avm_design_m0_write; //
assign avm_design_m0_readdatavalid = avm_m0_readdatavalid;
assign avm_design_m0_readdata = avm_m0_readdata;
assign avm_m0_writedata = avm_design_m0_writedata; //
assign avs_s0_waitrequest = avm_design_s0_waitrequest;
assign avm_design_s0_address = avs_s0_address;
assign avm_design_s0_read = avs_s0_read;
assign avm_design_s0_write = avs_s0_write;
assign avs_s0_readdata = avm_design_s0_readdata;
assign avm_design_s0_writedata = avs_s0_writedata[7:0];
endmodule
| 7.769005 |
module avalon_slave ( /*AUTOARG*/
// Outputs
READDATA,
WAITREQUEST,
READDATAVALID,
// Inputs
CLK,
RESET,
ADDRESS,
BEGINTRANSFER,
BYTE_ENABLE,
READ,
WRITE,
WRITEDATA,
LOCK,
BURSTCOUNT,
BEGINBURSTTRANSFER
);
//
// Fundamental Signals
//
input CLK;
input RESET;
input [31:0] ADDRESS;
input BEGINTRANSFER;
input [3:0] BYTE_ENABLE;
input READ;
output [31:0] READDATA;
input WRITE;
input [31:0] WRITEDATA;
//
// Wait State Signals
//
input LOCK;
output WAITREQUEST;
//
// Pipline
//
output READDATAVALID;
input [2:0] BURSTCOUNT;
input BEGINBURSTTRANSFER;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] READDATA;
reg READDATAVALID;
// End of automatics
/*AUTOWIRE*/
wire WAITREQUEST;
reg WAITREQUEST_read;
reg WAITREQUEST_write;
reg [31:0] reg1;
reg [31:0] reg2;
//
//
//
assign WAITREQUEST = WAITREQUEST_read || WAITREQUEST_write;
//
// WRITE LOGIC
//
always @(posedge CLK)
if (RESET) begin
reg1 <= 32'b0;
reg2 <= 32'b0;
WAITREQUEST_write <= 1'b0;
end else if (!WAITREQUEST && WRITE) begin
WAITREQUEST_write <= 1'b0;
case (ADDRESS)
32'h0000_0004: begin
case (BYTE_ENABLE)
4'b1111: reg1[31:00] <= WRITEDATA[31:00];
4'b1100: reg1[31:16] <= WRITEDATA[31:16];
4'b0011: reg1[15:00] <= WRITEDATA[15:00];
4'b1000: reg1[31:24] <= WRITEDATA[31:24];
4'b0100: reg1[23:16] <= WRITEDATA[23:16];
4'b0010: reg1[15:08] <= WRITEDATA[15:08];
4'b0001: reg1[07:00] <= WRITEDATA[07:00];
endcase // case (BYTE_ENABLE)
end
32'h0000_0008: begin
reg2[31:24] <= BYTE_ENABLE[3] ? WRITEDATA[31:24] : reg2[31:24];
reg2[23:16] <= BYTE_ENABLE[2] ? WRITEDATA[23:16] : reg2[23:16];
reg2[15:08] <= BYTE_ENABLE[1] ? WRITEDATA[15:08] : reg2[15:08];
reg2[07:00] <= BYTE_ENABLE[0] ? WRITEDATA[07:00] : reg2[07:00];
end
endcase // case (ADDRESS)
end else begin
WAITREQUEST_write <= 1'b0;
end
//
// READ LOGIC
//
always @(posedge CLK)
if (RESET) begin
WAITREQUEST_read <= 1'b0;
end else if (!WAITREQUEST && READ) begin
WAITREQUEST_read <= 1'b0;
end else begin
WAITREQUEST_read <= 1'b0;
end
always @(*)
if (RESET) begin
READDATAVALID <= 1'b0;
READDATA <= 32'b0;
end else if (!WAITREQUEST && READ) begin
READDATAVALID <= 1'b1;
case (ADDRESS)
32'h0000_0004: READDATA <= reg1;
32'h0000_0008: READDATA <= reg2;
endcase // case (ADDRESS)
end else begin
READDATA <= 32'b0;
READDATAVALID <= 1'b0;
end
endmodule
| 7.687723 |
module avalon_slave_edid ( /*autoport*/
//inout
edid_scl,
edid_sda,
//output
slave_readdata,
//input
clk,
reset,
slave_address,
slave_read,
slave_write,
slave_writedata,
slave_byteenable
);
// most of the set values will only be used by the component .tcl file. The DATA_WIDTH and MODE_X = 3 influence the hardware created.
// ENABLE_SYNC_SIGNALS isn't used by this hardware at all but it provided anyway so that it can be exposed in the component .tcl file
// to control the stubbing of certain signals.
parameter DATA_WIDTH = 8; // word size of each input and output register
// clock interface
input clk;
input reset;
// slave interface
input [7:0] slave_address;
input slave_read;
input slave_write;
output wire [DATA_WIDTH-1:0] slave_readdata;
input [DATA_WIDTH-1:0] slave_writedata;
input [(DATA_WIDTH/8)-1:0] slave_byteenable;
// user interface
inout wire edid_scl;
inout wire edid_sda;
wire [7:0] addr_i2c;
wire [7:0] data_i2c;
edid_mem on_chip_edid (
.clock (clk),
.data (slave_writedata),
.wraddress(slave_address),
.wren (slave_write),
.q (data_i2c),
.rdaddress(addr_i2c)
);
i2cSlave edid_i2c (
.clk (clk),
.rst (reset),
.sda (edid_sda),
.scl (edid_scl),
.regAddr (addr_i2c),
.dataFromRegIF(data_i2c),
.writeEn (),
.dataToRegIF ()
);
assign slave_readdata = 0;
endmodule
| 9.427509 |
module avalon_slave_to_wb_master (
clk,
rst_n,
av_address,
av_chipselect,
av_byteenable,
av_read,
av_write,
av_readdata,
av_readdatavalid,
av_writedata,
av_waitrequest,
wb_cyc_o,
wb_stb_o,
wb_we_o,
wb_adr_o,
wb_dat_o,
wb_dat_i,
wb_sel_o,
wb_ack_i
);
parameter ADDR_WIDTH = 32;
parameter DATA_WIDTH = 32;
parameter DATA_BYTES = 4;
input clk, rst_n;
input [ADDR_WIDTH-1:0] av_address;
input av_chipselect;
input [DATA_BYTES-1:0] av_byteenable;
input av_read, av_write;
output [DATA_WIDTH-1:0] av_readdata;
output av_readdatavalid;
input [DATA_WIDTH-1:0] av_writedata;
output av_waitrequest;
output wb_cyc_o, wb_stb_o, wb_we_o;
output [ADDR_WIDTH-1:0] wb_adr_o;
output [DATA_WIDTH-1:0] wb_dat_o;
input [DATA_WIDTH-1:0] wb_dat_i;
output [DATA_BYTES-1:0] wb_sel_o;
input wb_ack_i;
reg [ADDR_WIDTH-1:0] wb_adr_o_reg;
reg [DATA_WIDTH-1:0] wb_dat_o_reg;
reg [DATA_BYTES-1:0] wb_sel_o_reg;
reg [1:0] state, next_state;
localparam IDLE = 2'b00;
localparam READ = 2'b01;
localparam WRITE = 2'b10;
assign wb_cyc_o = state == IDLE ? av_chipselect : 1'b1;
assign wb_stb_o = state == IDLE ? (av_chipselect & (av_read | av_write)) : 1'b1;
assign wb_we_o = state == IDLE ? (av_chipselect & av_write) : state == WRITE;
assign wb_adr_o = state == IDLE ? av_address : wb_adr_o_reg;
assign wb_dat_o = state == IDLE ? av_writedata : wb_dat_o_reg;
assign wb_sel_o = state == IDLE ? av_byteenable : wb_sel_o_reg;
assign av_readdata = wb_dat_i;
assign av_readdatavalid = state == READ && wb_ack_i;
assign av_waitrequest = state != IDLE;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= IDLE;
else state <= next_state;
end
always @(state or av_chipselect or av_read or av_write or wb_ack_i) begin
case (state)
IDLE: begin
if (av_chipselect & av_write) next_state = wb_ack_i ? IDLE : WRITE;
else if (av_chipselect & av_read) next_state = READ;
else next_state = IDLE;
end
READ: next_state = wb_ack_i ? IDLE : READ;
WRITE: next_state = wb_ack_i ? IDLE : WRITE;
default: next_state = IDLE;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wb_adr_o_reg <= 'd0;
wb_dat_o_reg <= 'd0;
wb_sel_o_reg <= 'd0;
end else if (state == IDLE) begin
wb_adr_o_reg <= av_address;
wb_dat_o_reg <= av_writedata;
wb_sel_o_reg <= av_byteenable;
end
end
endmodule
| 9.427509 |
module is the avalon mm master to the hps sdram
module avalon_source_tester
#(
//256MB buffer is 64Mword, 26 bits to address
parameter SIZE_OF_COUNTER = 26,
parameter SIZE_OF_PATTERN = 2
)
(
input reset_n,
input clk,
//avalon-st interface, source
output reg [31:0] st_data,
output reg st_valid,
input st_ready,
//control signals
input [SIZE_OF_PATTERN-1:0] pattern,
input start,
input [SIZE_OF_COUNTER-1:0] size
);
//param definitions
localparam SIZE_OF_STATE_REG = 1;
localparam STATE_IDLE = 1'd0;
localparam STATE_RUNNING = 1'd1;
//flop definitions
reg [SIZE_OF_COUNTER-1:0] counter;
reg [SIZE_OF_STATE_REG-1:0] state;
//procedural assignment definitions
reg [SIZE_OF_COUNTER-1:0] next_counter;
reg [SIZE_OF_STATE_REG-1:0] next_state;
//wire definitions
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= {SIZE_OF_COUNTER{1'b0}};
state <= STATE_IDLE;
end else begin
counter <= next_counter;
state <= next_state;
end
end
always @(*) begin
next_state = state;
next_counter = counter;
st_data = 32'd0;
st_valid = 1'b0;
case (state)
STATE_IDLE: begin
if (start) begin
next_state = STATE_RUNNING;
end
end
STATE_RUNNING: begin
st_valid = 1'b1;
if (counter < size) begin
if (st_ready) //else do not increment, default condition
next_counter <= counter + {{(SIZE_OF_COUNTER-1){1'b0}}, 1'b1};
end else begin
next_state = STATE_IDLE;
next_counter <= {SIZE_OF_COUNTER{1'b0}};
end
case (pattern)
//pattern = 0, count up from 0 by 1
{SIZE_OF_PATTERN{1'b0}}: begin
st_data = counter;
end
//pattern = 1, alternate words of 0 and 0xffffffff
{{(SIZE_OF_PATTERN-1){1'b0}}, 1'd1}: begin
st_data = {32{counter[0]}};
end
//pattern = 2,
{{(SIZE_OF_PATTERN-2){1'b0}}, 2'd2}: begin
st_data = ((32'd1)<<counter[4:0]);
end
endcase
end
endcase
end
endmodule
| 8.565313 |
module is the Pseudo-Random Bit Sequence 23 Block
// where g(x) = x^23 + x^18 + x^0
//
// use lsb of m 1st first
// k can be > N, but part of the sequence will be skipped
//
//-------------------------------------------------------------------------------
//
// Copyright 2007 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera
// turn off bogus verilog processor warnings
// altera message_off 10034 10035 10036 10037 10230
module prbs23 ( clk, rst_n, load, enable, seed, d, m);
parameter k = 23; //step value = a^k
parameter N = 23;
input clk;
input rst_n;
input load;
input enable;
input [N-1:0] seed;
input [N-1:0] d;
output [N-1:0] m;
reg [N-1:0] m;
reg [N-1:0] tmpa;
reg [N-1:0] tmpb;
integer i,j;
always @ (d)
begin
tmpa = d;
for (i=0; i<k; i=i+1)
begin
for (j=0; j<(N-1); j=j+1) begin tmpb[j] = tmpa[j+1]; end
tmpb[N-1] = tmpa[18] ^ tmpa[0]; //x^23 + x[18] + x[0]
tmpa = tmpb;
end
end
always @(posedge clk or negedge rst_n)
begin
begin
if (!rst_n) m <= 0;
else if (load) m <= seed;
else if (enable) m <= tmpb;
end
end
endmodule
| 7.109329 |
module avalon_st_multiplexer (
input wire clk_clk, // clk.clk
input wire [71:0] multiplexer_in0_data, // multiplexer_in0.data
input wire multiplexer_in0_endofpacket, // .endofpacket
output wire multiplexer_in0_ready, // .ready
input wire multiplexer_in0_startofpacket, // .startofpacket
input wire multiplexer_in0_valid, // .valid
input wire [71:0] multiplexer_in1_data, // multiplexer_in1.data
input wire multiplexer_in1_endofpacket, // .endofpacket
output wire multiplexer_in1_ready, // .ready
input wire multiplexer_in1_startofpacket, // .startofpacket
input wire multiplexer_in1_valid, // .valid
output wire multiplexer_out_channel, // multiplexer_out.channel
output wire [71:0] multiplexer_out_data, // .data
output wire multiplexer_out_endofpacket, // .endofpacket
input wire multiplexer_out_ready, // .ready
output wire multiplexer_out_startofpacket, // .startofpacket
output wire multiplexer_out_valid, // .valid
input wire reset_reset_n // reset.reset_n
);
avalon_st_multiplexer_0 avalon_st_multiplexer_0 (
.clk(clk_clk), // input, width = 1, clk.clk
.in0_data(multiplexer_in0_data), // input, width = 72, in0.data
.in0_endofpacket(multiplexer_in0_endofpacket), // input, width = 1, .endofpacket
.in0_ready(multiplexer_in0_ready), // output, width = 1, .ready
.in0_startofpacket (multiplexer_in0_startofpacket), // input, width = 1, .startofpacket
.in0_valid(multiplexer_in0_valid), // input, width = 1, .valid
.in1_data(multiplexer_in1_data), // input, width = 72, in1.data
.in1_endofpacket(multiplexer_in1_endofpacket), // input, width = 1, .endofpacket
.in1_ready(multiplexer_in1_ready), // output, width = 1, .ready
.in1_startofpacket (multiplexer_in1_startofpacket), // input, width = 1, .startofpacket
.in1_valid(multiplexer_in1_valid), // input, width = 1, .valid
.out_channel(multiplexer_out_channel), // output, width = 1, out.channel
.out_data(multiplexer_out_data), // output, width = 72, .data
.out_endofpacket(multiplexer_out_endofpacket), // output, width = 1, .endofpacket
.out_ready(multiplexer_out_ready), // input, width = 1, .ready
.out_startofpacket (multiplexer_out_startofpacket), // output, width = 1, .startofpacket
.out_valid(multiplexer_out_valid), // output, width = 1, .valid
.reset_n(reset_reset_n) // input, width = 1, reset.reset_n
);
endmodule
| 7.428888 |
module avalon_st_multiplexer_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [71:0] out_data, // out.data
output wire out_valid, // .valid
input wire out_ready, // .ready
output wire out_startofpacket, // .startofpacket
output wire out_endofpacket, // .endofpacket
output wire out_channel, // .channel
input wire [71:0] in0_data, // in0.data
input wire in0_valid, // .valid
output wire in0_ready, // .ready
input wire in0_startofpacket, // .startofpacket
input wire in0_endofpacket, // .endofpacket
input wire [71:0] in1_data, // in1.data
input wire in1_valid, // .valid
output wire in1_ready, // .ready
input wire in1_startofpacket, // .startofpacket
input wire in1_endofpacket // .endofpacket
);
avalon_st_multiplexer_0_multiplexer_181_oa4enca avalon_st_multiplexer_0 (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.out_data (out_data), // output, width = 72, out.data
.out_valid (out_valid), // output, width = 1, .valid
.out_ready (out_ready), // input, width = 1, .ready
.out_startofpacket(out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (out_endofpacket), // output, width = 1, .endofpacket
.out_channel (out_channel), // output, width = 1, .channel
.in0_data (in0_data), // input, width = 72, in0.data
.in0_valid (in0_valid), // input, width = 1, .valid
.in0_ready (in0_ready), // output, width = 1, .ready
.in0_startofpacket(in0_startofpacket), // input, width = 1, .startofpacket
.in0_endofpacket (in0_endofpacket), // input, width = 1, .endofpacket
.in1_data (in1_data), // input, width = 72, in1.data
.in1_valid (in1_valid), // input, width = 1, .valid
.in1_ready (in1_ready), // output, width = 1, .ready
.in1_startofpacket(in1_startofpacket), // input, width = 1, .startofpacket
.in1_endofpacket (in1_endofpacket) // input, width = 1, .endofpacket
);
endmodule
| 7.428888 |
module avalon_st_multiplexer_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [71:0] out_data, // out.data
output wire out_valid, // .valid
input wire out_ready, // .ready
output wire out_startofpacket, // .startofpacket
output wire out_endofpacket, // .endofpacket
output wire out_channel, // .channel
input wire [71:0] in0_data, // in0.data
input wire in0_valid, // .valid
output wire in0_ready, // .ready
input wire in0_startofpacket, // .startofpacket
input wire in0_endofpacket, // .endofpacket
input wire [71:0] in1_data, // in1.data
input wire in1_valid, // .valid
output wire in1_ready, // .ready
input wire in1_startofpacket, // .startofpacket
input wire in1_endofpacket // .endofpacket
);
endmodule
| 7.428888 |
module avalon_st_multiplexer (
input wire clk_clk, // clk.clk
input wire [71:0] multiplexer_in0_data, // multiplexer_in0.data
input wire multiplexer_in0_endofpacket, // .endofpacket
output wire multiplexer_in0_ready, // .ready
input wire multiplexer_in0_startofpacket, // .startofpacket
input wire multiplexer_in0_valid, // .valid
input wire [71:0] multiplexer_in1_data, // multiplexer_in1.data
input wire multiplexer_in1_endofpacket, // .endofpacket
output wire multiplexer_in1_ready, // .ready
input wire multiplexer_in1_startofpacket, // .startofpacket
input wire multiplexer_in1_valid, // .valid
output wire multiplexer_out_channel, // multiplexer_out.channel
output wire [71:0] multiplexer_out_data, // .data
output wire multiplexer_out_endofpacket, // .endofpacket
input wire multiplexer_out_ready, // .ready
output wire multiplexer_out_startofpacket, // .startofpacket
output wire multiplexer_out_valid, // .valid
input wire reset_reset_n // reset.reset_n
);
endmodule
| 7.428888 |
module avalon_st_to_crc_if_bridge (
CLK,
RESET_N,
AVST_READY,
AVST_VALID,
AVST_SOP,
AVST_DATA,
AVST_EOP,
AVST_EMPTY,
CRC_ENA,
CRC_INIT,
CRC_DATA,
CRC_DATA_SIZE,
CRC_OUT_LATCH
);
parameter DATA_WIDTH = 32; //8,32,64,16(optional)
parameter EMPTY_WIDTH = 2; //x,2 ,3 ,1
//FSM Parameter
localparam rst = 2'd0;
localparam init = 2'd1; //State init - Init the CRC32 Algorithm with 32'hffffffff
localparam ready = 2'd2; //Ready to transfer state
input CLK;
input RESET_N;
//Avalon ST Interface
output AVST_READY;
input AVST_VALID;
input AVST_SOP;
input [DATA_WIDTH-1:0] AVST_DATA;
input AVST_EOP;
input [EMPTY_WIDTH-1:0] AVST_EMPTY;
//CRC Interface
output CRC_ENA;
output CRC_INIT;
output [DATA_WIDTH-1:0] CRC_DATA;
output [EMPTY_WIDTH-1:0] CRC_DATA_SIZE;
//CRC Latch indication
output CRC_OUT_LATCH; //0 - CRC not valid, 1 - CRC is valid
reg CRC_ENA;
reg CRC_INIT;
reg [ DATA_WIDTH-1:0] CRC_DATA;
reg [EMPTY_WIDTH-1:0] CRC_DATA_SIZE;
reg [2:0] state, next;
reg CRC_OUT_LATCH;
reg AVST_READY;
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) AVST_READY <= 1'b0;
else if (next == ready) AVST_READY <= 1'b1;
else AVST_READY <= 1'b0;
//FSM Init Control
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) state <= rst;
else state <= next;
always @*
case (state)
rst: next = init;
init: next = ready;
ready: next = ready;
default: next = rst;
endcase
//CRC32 Interface
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_ENA <= 1'b0;
else if (next == init) CRC_ENA <= 1'b1;
else CRC_ENA <= AVST_VALID;
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_INIT <= 1'b0;
else if ((next == init) || (AVST_VALID && AVST_EOP)) CRC_INIT <= 1'b1;
else CRC_INIT <= 1'b0;
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_DATA <= {DATA_WIDTH{1'b0}};
else CRC_DATA <= AVST_DATA;
generate
if (DATA_WIDTH == 8) begin
always @(*) CRC_DATA_SIZE = {EMPTY_WIDTH{1'b0}};
end else if (DATA_WIDTH == 16) begin
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_DATA_SIZE <= {EMPTY_WIDTH{1'b0}};
else
case (AVST_EMPTY)
1'b0: CRC_DATA_SIZE <= 1'b1;
1'b1: CRC_DATA_SIZE <= 1'b0;
default: CRC_DATA_SIZE <= 1'b1;
endcase
end else if (DATA_WIDTH == 32) begin
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_DATA_SIZE <= {EMPTY_WIDTH{1'b0}};
else
case (AVST_EMPTY)
2'b00: CRC_DATA_SIZE <= 2'b11;
2'b01: CRC_DATA_SIZE <= 2'b10;
2'b10: CRC_DATA_SIZE <= 2'b01;
2'b11: CRC_DATA_SIZE <= 2'b00;
default: CRC_DATA_SIZE <= 2'b11;
endcase
end else if (DATA_WIDTH == 64) begin
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_DATA_SIZE <= {EMPTY_WIDTH{1'b0}};
else
case (AVST_EMPTY)
3'b000: CRC_DATA_SIZE <= 3'b111;
3'b001: CRC_DATA_SIZE <= 3'b110;
3'b010: CRC_DATA_SIZE <= 3'b101;
3'b011: CRC_DATA_SIZE <= 3'b100;
3'b100: CRC_DATA_SIZE <= 3'b011;
3'b101: CRC_DATA_SIZE <= 3'b010;
3'b110: CRC_DATA_SIZE <= 3'b001;
3'b111: CRC_DATA_SIZE <= 3'b000;
default: CRC_DATA_SIZE <= 3'b111;
endcase
end
endgenerate
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CRC_OUT_LATCH <= 1'b0;
else if ((state !== init) && CRC_ENA && CRC_INIT) CRC_OUT_LATCH <= 1'b1;
else CRC_OUT_LATCH <= 1'b0;
endmodule
| 9.535356 |
module avalon_sysctrl (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0_debugaccess
);
input clk_clk;
input reset_reset_n;
output mm_bridge_s0_waitrequest;
output [31:0] mm_bridge_s0_readdata;
output mm_bridge_s0_readdatavalid;
input [0:0] mm_bridge_s0_burstcount;
input [31:0] mm_bridge_s0_writedata;
input [23:0] mm_bridge_s0_address;
input mm_bridge_s0_write;
input mm_bridge_s0_read;
input [3:0] mm_bridge_s0_byteenable;
input mm_bridge_s0_debugaccess;
endmodule
| 7.40382 |
module avalon_sysctrl_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
sys_reset_req,
// outputs:
readdata
);
parameter INIT_FILE = "avalon_sysctrl_onchip_memory2_0.hex";
output [31:0] readdata;
input [7:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
output reg sys_reset_req;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 256,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
parameter ADDR_SYSRESET_REQ = 8'h0;
// ____________________________________________________________________________
// system reset setting register
// ____________________________________________________________________________
always @(posedge clk) begin
if (write && address == ADDR_SYSRESET_REQ) sys_reset_req <= writedata[0];
end
endmodule
| 7.40382 |
module avalon_to_wb_bridge #(
parameter DW = 32, // Data width
parameter AW = 32 // Address width
) (
input wb_clk_i,
input wb_rst_i,
// Avalon Slave input
input [ AW-1:0] s_av_address_i,
input [DW/8-1:0] s_av_byteenable_i,
input s_av_read_i,
output [ DW-1:0] s_av_readdata_o,
input [ 7:0] s_av_burstcount_i,
input s_av_write_i,
input [ DW-1:0] s_av_writedata_i,
output s_av_waitrequest_o,
output s_av_readdatavalid_o,
// Wishbone Master Output
output [ AW-1:0] wbm_adr_o,
output [ DW-1:0] wbm_dat_o,
output [DW/8-1:0] wbm_sel_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
output [ 2:0] wbm_cti_o,
output [ 1:0] wbm_bte_o,
input [ DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
input wbm_rty_i
);
reg read_access;
always @(posedge wb_clk_i)
if (wb_rst_i) read_access <= 0;
else if (wbm_ack_i | wbm_err_i) read_access <= 0;
else if (s_av_read_i) read_access <= 1;
reg readdatavalid;
reg [DW-1:0] readdata;
always @(posedge wb_clk_i) begin
readdatavalid <= (wbm_ack_i | wbm_err_i) & read_access;
readdata <= wbm_dat_i;
end
assign wbm_adr_o = s_av_address_i;
assign wbm_dat_o = s_av_writedata_i;
assign wbm_sel_o = s_av_byteenable_i;
assign wbm_we_o = s_av_write_i;
assign wbm_cyc_o = read_access | s_av_write_i;
assign wbm_stb_o = read_access | s_av_write_i;
assign wbm_cti_o = 3'b111; // TODO: support burst accesses
assign wbm_bte_o = 2'b00;
assign s_av_waitrequest_o = !(wbm_ack_i | wbm_err_i);
assign s_av_readdatavalid_o = readdatavalid;
assign s_av_readdata_o = readdata;
endmodule
| 9.295828 |
module avalon_vip #(
parameter BITS = 8,
parameter WIDTH = 1280,
parameter HEIGHT = 960
) (
input clk,
input reset,
// slave control register
input [ 5:0] as_address,
input as_read,
output reg [31:0] as_readdata,
input as_write,
input [31:0] as_writedata,
output irq,
input pclk,
input rst_n,
input in_href,
input in_vsync,
input [BITS-1:0] in_y,
input [BITS-1:0] in_u,
input [BITS-1:0] in_v,
output out_pclk,
output out_href,
output out_vsync,
output [BITS-1:0] out_r,
output [BITS-1:0] out_g,
output [BITS-1:0] out_b
);
localparam REG_RESET = 0;
localparam REG_TOP_EN = 1;
localparam REG_DSCALE_SCALE = 2;
localparam REG_INT_STATUS = 3;
localparam REG_INT_MASK = 4;
reg module_reset;
reg hist_equ_en, sobel_en, yuv2rgb_en, dscale_en;
reg [3:0] dscale_scale;
reg int_frame_done;
reg int_mask_frame_done;
assign irq = int_frame_done & (~int_mask_frame_done);
reg prev_vsync;
always @(posedge clk) prev_vsync <= out_vsync;
always @(posedge clk or posedge reset) begin
if (reset) begin
module_reset <= 1;
sobel_en <= 0;
yuv2rgb_en <= 1;
dscale_en <= 1;
dscale_scale <= 4'd1; //1/2
int_frame_done <= 0;
int_mask_frame_done <= 1;
end else begin
if (as_read) begin
case (as_address)
REG_RESET: as_readdata <= {31'd0, module_reset};
REG_TOP_EN: as_readdata <= {28'd0, dscale_en, yuv2rgb_en, sobel_en, hist_equ_en};
REG_DSCALE_SCALE: as_readdata <= {28'd0, dscale_scale};
REG_INT_STATUS: as_readdata <= {31'd0, int_frame_done};
REG_INT_MASK: as_readdata <= {31'd0, int_mask_frame_done};
default: as_readdata <= 0;
endcase
end else if (as_write) begin
case (as_address)
REG_RESET: module_reset <= as_writedata[0];
REG_TOP_EN: {dscale_en, yuv2rgb_en, sobel_en, hist_equ_en} <= as_writedata[3:0];
REG_DSCALE_SCALE: dscale_scale <= as_writedata[3:0];
REG_INT_STATUS: int_frame_done <= 1'd0;
REG_INT_MASK: int_mask_frame_done <= as_writedata[0];
default: ;
endcase
end else begin
if (out_vsync & (~prev_vsync)) int_frame_done <= 1'b1;
end
end
end
vip_top #(BITS, WIDTH, HEIGHT) vip_top_i0 (
.pclk (pclk),
.rst_n(rst_n & ~module_reset),
.in_href(in_href),
.in_vsync(in_vsync),
.in_y(in_y),
.in_u(in_u),
.in_v(in_v),
.out_pclk(out_pclk),
.out_href(out_href),
.out_vsync(out_vsync),
.out_r(out_r),
.out_g(out_g),
.out_b(out_b),
.hist_equ_en(hist_equ_en),
.sobel_en(sobel_en),
.yuv2rgb_en(yuv2rgb_en),
.dscale_en(dscale_en),
.dscale_scale(dscale_scale)
);
endmodule
| 8.436928 |
module AVConfig (
input wire [ 1:0] address, // avalon_av_config_slave.address
input wire [ 3:0] byteenable, // .byteenable
input wire read, // .read
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire [31:0] readdata, // .readdata
output wire waitrequest, // .waitrequest
input wire clk, // clk.clk
inout wire I2C_SDAT, // external_interface.SDAT
output wire I2C_SCLK, // .SCLK
input wire reset // reset.reset
);
AVConfig_audio_and_video_config_0 audio_and_video_config_0 (
.clk (clk), // clk.clk
.reset (reset), // reset.reset
.address (address), // avalon_av_config_slave.address
.byteenable (byteenable), // .byteenable
.read (read), // .read
.write (write), // .write
.writedata (writedata), // .writedata
.readdata (readdata), // .readdata
.waitrequest(waitrequest), // .waitrequest
.I2C_SDAT (I2C_SDAT), // external_interface.export
.I2C_SCLK (I2C_SCLK) // .export
);
endmodule
| 6.563077 |
module AVConfig (
address,
byteenable,
read,
write,
writedata,
readdata,
waitrequest,
clk,
I2C_SDAT,
I2C_SCLK,
reset
);
input [1:0] address;
input [3:0] byteenable;
input read;
input write;
input [31:0] writedata;
output [31:0] readdata;
output waitrequest;
input clk;
inout I2C_SDAT;
output I2C_SCLK;
input reset;
endmodule
| 6.563077 |
module averagefilter (
clk,
m11,
m12,
m13,
m21,
m22,
m23,
m31,
m32,
m33,
mid
);
parameter width = 8;
input clk;
input [width - 1:0] m11;
input [width - 1:0] m12;
input [width - 1:0] m13;
input [width - 1:0] m21;
input [width - 1:0] m22;
input [width - 1:0] m23;
input [width - 1:0] m31;
input [width - 1:0] m32;
input [width - 1:0] m33;
output [width - 1:0] mid;
wire [width - 1:0] mid;
wire [width + 2:0] tmp;
wire [width - 1:0] max1;
wire [width - 1:0] mid1;
wire [width - 1:0] min1;
wire [width - 1:0] max2;
wire [width - 1:0] mid2;
wire [width - 1:0] min2;
wire [width - 1:0] max3;
wire [width - 1:0] mid3;
wire [width - 1:0] min3;
wire [width - 1:0] max_min;
wire [width - 1:0] mid_mid;
wire [width - 1:0] min_max;
assign tmp = {3'b000, m11} + {3'b000, m12} + {3'b000, m13} + {3'b000, m21} + {3'b000, m22} + {3'b000, m23} + {3'b000, m31} + {3'b000, m32} ;
assign mid = tmp[width+2:3];
endmodule
| 6.676459 |
module averagefilter (
clk,
m11,
m12,
m13,
m21,
m22,
m23,
m31,
m32,
m33,
mid
);
parameter width = 8;
input clk;
input [width - 1:0] m11;
input [width - 1:0] m12;
input [width - 1:0] m13;
input [width - 1:0] m21;
input [width - 1:0] m22;
input [width - 1:0] m23;
input [width - 1:0] m31;
input [width - 1:0] m32;
input [width - 1:0] m33;
output [width - 1:0] mid;
wire [width - 1:0] mid;
wire [width + 2:0] tmp;
wire [width - 1:0] max1;
wire [width - 1:0] mid1;
wire [width - 1:0] min1;
wire [width - 1:0] max2;
wire [width - 1:0] mid2;
wire [width - 1:0] min2;
wire [width - 1:0] max3;
wire [width - 1:0] mid3;
wire [width - 1:0] min3;
wire [width - 1:0] max_min;
wire [width - 1:0] mid_mid;
wire [width - 1:0] min_max;
assign tmp = {3'b000, m11} + {3'b000, m12} + {3'b000, m13} + {3'b000, m21} + {3'b000, m22} + {3'b000, m23} + {3'b000, m31} + {3'b000, m32} ;
assign mid = tmp[width+2:3];
endmodule
| 6.676459 |
module cs_mealyfsm (
clk,
rst,
ready_sample,
ce,
en_comp,
wr_en,
rst_dev,
strobe_writer,
run,
state
);
//state symbols
parameter IDLE = 4'd0;
parameter WRITE_FIFO_S = 4'd1;
parameter STORE_SAMPLE = 4'd2;
parameter DETECTION = 4'd3;
parameter WAIT = 4'd4;
//state register
output reg [3:0] state;
//output to data path
output reg ce;
output reg rst_dev;
output reg en_comp;
output reg wr_en;
//input to controller
input clk, rst, strobe_writer, run;
input ready_sample;
//local register
reg rst_counter;
always @(posedge clk) begin
if (rst) begin
//CONTROL SIGNALS
en_comp <= 0; //disable comparator
wr_en <= 0; //disable writer into the fifo
rst_dev <= 1; //reset all fifos in the data path
//state transition
state <= IDLE; //go to writing
end else begin
case (state)
IDLE: begin
//CONTROL SIGNALS
en_comp <= 0; //disable comparator
wr_en <= 0; //disable writer into the fifo
rst_dev <= 0; //reset all fifos in the data path
//state transition
if (strobe_writer) begin
wr_en <= strobe_writer;
state <= WRITE_FIFO_S;
end else begin
wr_en <= 0;
state <= IDLE;
end
end
WRITE_FIFO_S: begin
//control
en_comp <= 0;
//note: at this point, strobe writer might be low, and i and q into the buffers might be zero,
//so, we should check if strobe write is low, and if it is, exit out!
wr_en <= strobe_writer;
rst_dev <= 0;
//state
if (ready_sample) begin
state <= STORE_SAMPLE;
rst_dev <= 0; //reset adder, divider-register should be empty already
end else state <= WRITE_FIFO_S;
end
STORE_SAMPLE: begin
//control
en_comp <= 0; //NEEDED ?
wr_en <= 0; //NEEDED ? SINCE DETECTION MAKES WR_EN ZERO !
rst_dev <= 0; //NEEDED ?
//state
state <= DETECTION;
end
DETECTION: begin
//control
en_comp <= 1;
wr_en <= 0;
rst_dev <= 1;
//state
state <= WAIT;
end
WAIT: begin
//control
en_comp <= 0;
rst_dev <= 0;
//state
state <= WRITE_FIFO_S;
end
endcase
end
end
endmodule
| 8.420452 |
module
average_pooling #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
ARITH_TYPE = 0
)
(
input clk,
input reset,
input pool_enable,
input [DATA_WIDTH - 1 : 0] pool_data_in_1,
input [DATA_WIDTH - 1 : 0] pool_data_in_2,
input [DATA_WIDTH - 1 : 0] pool_data_in_3,
input [DATA_WIDTH - 1 : 0] pool_data_in_4,
output reg [DATA_WIDTH - 1 : 0] pool_data_out_reg
);
wire [DATA_WIDTH - 1 : 0] sum_1_1;
wire [DATA_WIDTH - 1 : 0] sum_1_2;
wire [DATA_WIDTH - 1 : 0] sum_2_1;
reg [DATA_WIDTH - 1 : 0] reg_sum_1_1;
reg [DATA_WIDTH - 1 : 0] reg_sum_1_2;
reg [DATA_WIDTH - 1 : 0] reg_sum_2_1;
wire [DATA_WIDTH - 1 : 0] avgIFM;
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_1_1 (.in1(pool_data_in_1), .in2(pool_data_in_2), .out(sum_1_1));
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_1_2 (.in1(pool_data_in_3), .in2(pool_data_in_4), .out(sum_1_2));
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_2_1 (.in1(reg_sum_1_1), .in2(reg_sum_1_2), .out(sum_2_1));
always @(posedge clk , posedge reset)
if (reset)
begin
reg_sum_1_1 <= 0;
reg_sum_1_2 <= 0;
end
else if(pool_enable)
begin
reg_sum_1_1 <= sum_1_1 ;
reg_sum_1_2 <= sum_1_2 ;
end
always @(posedge clk, posedge reset)
begin
if(reset)
begin
reg_sum_2_1 <= 0;
end
else
begin
reg_sum_2_1 <= sum_2_1;
end
end
always @(posedge clk or posedge reset)
begin
if(reset)
pool_data_out_reg <= 0;
else
pool_data_out_reg <= avgIFM;
end
divider #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) div ( .in1(reg_sum_2_1), .out(avgIFM) );
endmodule
| 6.555487 |
module
average_pooling_S4 #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
ARITH_TYPE = 0
)
(
input clk,
input reset,
input pool_enable,
input [DATA_WIDTH - 1 : 0] pool_data_in_1,
input [DATA_WIDTH - 1 : 0] pool_data_in_2,
input [DATA_WIDTH - 1 : 0] pool_data_in_3,
input [DATA_WIDTH - 1 : 0] pool_data_in_4,
output reg [DATA_WIDTH - 1 : 0] pool_data_out_reg
);
wire [DATA_WIDTH - 1 : 0] sum_1_1;
wire [DATA_WIDTH - 1 : 0] sum_1_2;
wire [DATA_WIDTH - 1 : 0] sum_2_1;
reg [DATA_WIDTH - 1 : 0] reg_sum_1_1;
reg [DATA_WIDTH - 1 : 0] reg_sum_1_2;
reg [DATA_WIDTH - 1 : 0] reg_sum_2_1;
wire [DATA_WIDTH - 1 : 0] avgIFM;
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_1_1 (.in1(pool_data_in_1), .in2(pool_data_in_2), .out(sum_1_1));
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_1_2 (.in1(pool_data_in_3), .in2(pool_data_in_4), .out(sum_1_2));
adder #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) adr_2_1 (.in1(reg_sum_1_1), .in2(reg_sum_1_2), .out(sum_2_1));
always @(posedge clk , posedge reset)
if (reset)
begin
reg_sum_1_1 <= 0;
reg_sum_1_2 <= 0;
end
else if(pool_enable)
begin
reg_sum_1_1 <= sum_1_1 ;
reg_sum_1_2 <= sum_1_2 ;
end
always @(posedge clk, posedge reset)
begin
if(reset)
begin
reg_sum_2_1 <= 0;
end
else
begin
reg_sum_2_1 <= sum_2_1;
end
end
always @(posedge clk or posedge reset)
begin
if(reset)
pool_data_out_reg <= 0;
else
pool_data_out_reg <= avgIFM;
end
divider #(.DATA_WIDTH(DATA_WIDTH), .ARITH_TYPE(ARITH_TYPE)) div ( .in1(reg_sum_2_1), .out(avgIFM) );
endmodule
| 6.555487 |
module moving_average #(
parameter integer in_bits = 16,
parameter integer out_bits = 16,
parameter integer log2_samples = 8
) (
input wire [in_bits-1:0] in_data,
input wire clk,
output wire [out_bits-1:0] out_data
);
localparam integer samples = 2 ** log2_samples;
localparam integer reg_bits = in_bits + log2_samples;
reg [reg_bits-1:0] in_data2;
reg [reg_bits-1:0] buffer[samples-1:0];
reg [reg_bits-1:0] out_data2;
genvar i;
//Deal with buffer chain
generate
for (i = 0; i < samples - 1; i = i + 1) begin : gen_buffer
always @(posedge clk) begin
buffer[i][reg_bits-1:0] <= buffer[i+1][reg_bits-1:0];
end
end
endgenerate
//Deal with in and out data
always @(posedge clk) begin
in_data2 <= {{(log2_samples + 1) {in_data[in_bits-1]}}, in_data[in_bits-2:0]};
buffer[samples-1][reg_bits-1:0] <= in_data2;
//Update sum
out_data2 <= out_data2 + in_data2 - buffer[0][reg_bits-1:0];
end
//Assign to out, drop highest (non signing) bit - will always be 0 due to the nature of the numbers
assign out_data = {out_data2[reg_bits-1], out_data2[reg_bits-3:reg_bits-out_bits-1]};
endmodule
| 7.349406 |
module moving_average #(
parameter integer in_bits = 16,
parameter integer out_bits = 16,
parameter integer log2_samples = 8
) (
input wire [in_bits-1:0] in_data,
input wire clk,
output wire [out_bits-1:0] out_data
);
localparam integer reg_bits = in_bits + log2_samples;
reg [reg_bits-1:0] out_data2 = 0;
reg [reg_bits-1:0] in_data2 = 0;
genvar i;
//Deal with in and out data
always @(posedge clk) begin
in_data2 <= {{(log2_samples + 1) {in_data[in_bits-1]}}, in_data[in_bits-2:0]};
out_data2 <= out_data2 + in_data2 - {{(log2_samples+1){out_data2[reg_bits-1]}}, out_data2[reg_bits-2:log2_samples]};
end
//Assign to out, drop highest (non signing) bit - will always be 0 due to the nature of the numbers
assign out_data = out_data2[reg_bits-1:reg_bits-out_bits];
endmodule
| 7.349406 |
module two_clk_accum #(
parameter integer inc_bits = 32,
parameter integer count_bits = 32,
parameter integer out_bits = 32,
parameter integer out_bus_size = 32 //For AXI interfaces where bus size is a multiple of 8 regardless of number of bits
) (
input wire count_clk,
input wire out_clk,
input wire sync_i,
input wire [inc_bits-1:0] inc_in,
output wire [out_bus_size-1:0] count_out
);
reg [count_bits-1:0] count_reg;
reg [inc_bits-1:0] inc_reg;
reg [inc_bits-1:0] inc_reg2;
reg [out_bus_size-1:0] out_reg;
reg [out_bus_size-1:0] out_reg2;
//In buffer and count
always @(posedge count_clk) begin
inc_reg <= inc_in;
inc_reg2 <= inc_reg;
if (sync_i) begin //Reset to match phases
count_reg <= 0;
end else begin
count_reg <= count_reg + inc_reg2;
end
end
//Out buffer
always @(posedge out_clk) begin
out_reg[out_bits-1:0] <= count_reg[count_bits-1:count_bits-out_bits];
out_reg2 <= out_reg;
end
assign count_out = out_reg2;
endmodule
| 6.936444 |
module avg (
din,
reset,
clk,
ready,
dout
);
input reset, clk;
input [15:0] din;
output reg ready;
output reg [15:0] dout;
// ==========================================
// Enter your design below
// ==========================================
reg [15:0] mem[11:0];
reg [20:0] sum;
reg [3:0] i;
reg [3:0] j;
reg [15:0] avg;
reg [15:0] arrp;
reg [3:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (i = 0; i < 12; i = i + 1) mem[i] <= 0;
sum <= 0;
i <= 0;
ready <= 0;
count <= 0;
end else begin
for (i = 11; i > 0; i = i - 1) mem[i] <= mem[i-1];
mem[0] <= din;
sum <= sum - mem[11] + din;
if (ready == 0) begin
count = count + 1;
if (count == 11) ready = 1;
end else ready = 1;
end
end
always @(*) begin
if (ready == 1) begin
avg = sum / 12;
arrp = mem[0];
for (j = 0; j < 12; j = j + 1) begin
if(((avg >= mem[j])?avg-mem[j]:mem[j]-avg) < ((avg >= arrp)?avg-arrp:arrp-avg))
arrp = mem[j];
else if(((avg >= mem[j])?avg-mem[j]:mem[j]-avg) == ((avg >= arrp)?avg-arrp:arrp-avg) && arrp >= mem[j])
arrp = mem[j];
else arrp = arrp;
end
dout = arrp;
end
end
endmodule
| 6.69656 |
module avg2pw_reorder_addr_gen (
input clk_calc,
input [25:0] base_addr,
input [10:0] avg2pw_cnt,
output reg [25:0] avg2pw_reorder_addr
);
//一级
reg [25:0] avg2pw_reorder_addr_p;
always @(posedge clk_calc) begin
avg2pw_reorder_addr_p <= base_addr + avg2pw_cnt;
end
//二、三、四级
reg [25:0] avg2pw_reorder_addr_r1;
reg [25:0] avg2pw_reorder_addr_r2;
always @(posedge clk_calc) begin
avg2pw_reorder_addr_r1 <= avg2pw_reorder_addr_p;
avg2pw_reorder_addr_r2 <= avg2pw_reorder_addr_r1;
avg2pw_reorder_addr <= avg2pw_reorder_addr_r2;
end
endmodule
| 6.866184 |
module avg_calc (
input clk,
input rst,
input [7:0] data,
output reg [7:0] avg
);
reg [18:0] sum;
reg [20:0] cnt;
always @(posedge clk) begin
sum <= rst ? 0 : sum + data;
avg <= rst ? sum / cnt : avg;
cnt <= rst ? 0 : cnt + 1;
end
endmodule
| 7.041508 |
module Avg_pool #(
parameter integer BITWIDTH = 8,
parameter integer DATAWIDTH = 28,
parameter integer DATAHEIGHT = 28,
parameter integer DATACHANNEL = 3,
parameter integer KWIDTH = 2,
parameter integer KHEIGHT = 2
) (
//input clk,
//input clken,
input [BITWIDTH * DATAWIDTH * DATAHEIGHT * DATACHANNEL - 1 : 0] data,
output [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] result
);
wire [BITWIDTH - 1 : 0] dataArray[0 : DATACHANNEL - 1][0 : DATAHEIGHT-1][0 : DATAWIDTH - 1];
wire [BITWIDTH * KHEIGHT * KWIDTH - 1 : 0]paramArray [0: DATACHANNEL - 1][0: DATAHEIGHT / KHEIGHT - 1][0: DATAWIDTH / KWIDTH - 1];
//wire [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] out;
genvar i, j, k, m, n;
generate
for (i = 0; i < DATACHANNEL; i = i + 1) begin
for (j = 0; j < DATAHEIGHT; j = j + 1) begin
for (k = 0; k < DATAWIDTH; k = k + 1) begin
assign dataArray[i][j][k] = data[(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH];
end
end
end
endgenerate
generate
for (i = 0; i < DATACHANNEL; i = i + 1) begin
for (j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
for (k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
for (m = j * 2; m < j * 2 + KHEIGHT; m = m + 1) begin
for (n = k * 2; n < k * 2 + KWIDTH; n = n + 1) begin
assign paramArray[i][j][k][((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH + BITWIDTH - 1:((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH] = dataArray[i][m][n];
end
end
end
end
end
endgenerate
generate
for (i = 0; i < DATACHANNEL; i = i + 1) begin
for (j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
for (k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
Avg #(BITWIDTH, KHEIGHT * KWIDTH) avg (
paramArray[i][j][k],
result[(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH]
);
end
end
end
endgenerate
// always @(posedge clk) begin
// if(clken == 1) begin
// result = out;
// end
// end
endmodule
| 6.909449 |
module avg_pool_Add2i1s8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add_32Sx32S_33S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_And_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.016549 |
module avg_pool_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.016549 |
module avg_pool_DECODE_2U_12_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_DECODE_2U_12_4_0 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_DECODE_2U_12_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_Equal_8Sx7S_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_LtnLLs33_1 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
assign out1 = asc001;
endmodule
| 6.542886 |
module avg_pool_LtnLLs33_4 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
assign out1 = asc001;
endmodule
| 6.542886 |
module avg_pool_LtnLLs33_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
assign out1 = asc001;
endmodule
| 6.542886 |
module avg_pool_LtnLLs33_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
assign out1 = asc001;
endmodule
| 6.542886 |
module avg_pool_Muxi0Add2i1s8u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.699082 |
module avg_pool_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.676624 |
module avg_pool_N_Muxb_1_2_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Muxb_1_2_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Muxb_1_2_4_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Muxb_1_2_4_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_5_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_5_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_5_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_5_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_6_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_6_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_6_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_N_Mux_8_2_6_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.703286 |
module avg_pool_Or_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
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