code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module implements a basic slave configuration status interface
* compatible with the Altera Avalon Memory Mapped Interface standard.
*
* Such interfaces are typically used in large processor controlled
* systems to allow memory mapped access to peripherals. The Leeds SoC
* Computer design used for the ELEC5620M mo... | 6.904081 |
module avalonslavetestbench (
input wire [63:0] avalon_writedata, // avalon.writedata
input wire [ 7:0] avalon_burstcount, // .burstcount
output wire [63:0] avalon_readdata, // .readdata
input wire [28:0] avalon_address, // .address
output wire avalo... | 7.375926 |
module avalon_bridge (
clk,
reset_n,
avl_master_ready,
avl_master_addr,
avl_master_rdata_valid,
avl_master_rdata,
avl_master_wdata,
avl_master_be,
avl_master_read_req,
avl_master_write_req,
avl_master_size,
avl_slave_ready,
avl_slave_addr,
avl_slave_rdata_valid,... | 9.232811 |
module avalon_combiner (
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [ 6:0] mixer_address, // ctl_mixer.address
output wire [ 3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0... | 7.592648 |
module avalon_dc_fifo (
reset_ext_reset_n,
clk_int_clk,
reset_int_reset_n,
clk_ext_clk,
dc_fifo_in_data,
dc_fifo_in_valid,
dc_fifo_in_ready,
dc_fifo_out_data,
dc_fifo_out_valid,
dc_fifo_out_ready
);
input reset_ext_reset_n;
input clk_int_clk;
input reset_int_reset_n;
inp... | 7.191061 |
module avalon_dvp_wch #(
parameter AM_DATA_WIDTH = 16,
parameter AM_MAX_BURST_COUNT = 4,
parameter AM_BURST_COUNT_WIDTH = 3,
parameter AM_ADDRESS_WIDTH = 32,
parameter AM_FIFO_DEPTH = 32,
parameter AM_FIFO_DEPTH_LOG2 = 5,
parameter AM_MEMORY_BASED_FIFO = 1 // set to 0 to use LEs instead
) (... | 9.18688 |
module avalon_gen (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0_deb... | 8.545607 |
module avalon_gen_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
//
tx_ready,
tx_data,
tx_valid,
tx_sop,
tx_eop,
tx_empty,
tx_error,
input_10g_data,
// outputs:
... | 7.777361 |
module avalon_io12_4_switcher (
clk,
select,
sink_data_0,
sink_valid_0,
sink_error_0,
sink_data_1,
sink_valid_1,
sink_error_1,
sink_data_2,
sink_valid_2,
sink_error_2,
sink_data_3,
sink_valid_3,
sink_error_3,
source_data,
source_valid,
source_error
);
... | 8.688105 |
module avalon_jtag_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRES... | 7.398354 |
module to simplify having a register of variable width and containing independent byte lanes
module register_with_bytelanes (
clk,
reset,
data_in,
write,
byte_enables,
data_out
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input [DATA_WIDTH-1:0] data_in;
input write;
input [(DATA_WIDTH/8)-1:0... | 8.882302 |
module avalon_mon (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0_deb... | 7.945003 |
module avalon_motor (
input pwm_clk,
data_clk,
input [11:0] ast_sink_data,
input [1:0] ast_sink_error,
input ast_sink_valid,
output reg outh,
outl,
output reg update
);
//
reg [11:0] last_valid_data;
reg [11:0] data_sync0, data_sync1, data_sync2;
reg signed [9:0] pwm_counter;
... | 7.309496 |
module avalon_ram #(
parameter ADW = 32, // data width
parameter ABW = ADW/8, // byte enable width
parameter ASZ = 1024, // memory size
parameter AAW = $clog2(ASZ/ABW) // address width
)(
// system signals
input clk, // clock
input rst, ... | 9.267528 |
module avalon_rgb_led_bargraph_dpram512x8 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrcl... | 7.640926 |
module avalon_rgb_led_bargraph_slave (
// clocks and resets
input wire clock,
input wire resetn,
// avalon bus
input wire read,
input wire write,
input wire chipselect,
input wire [3:0] address,
input wire [3:0] byteenable,
input wire [31:0] writedata,
outpu... | 7.640926 |
module avalon_sha3_wrapper (
clk, // clock.clk
reset, // reset.reset
// Memory mapped read/write slave interface
avs_s0_address,
avs_s0_read,
avs_s0_write,
avs_s0_writedata,
avs_s0_readdata,
avs_s0_waitrequest
);
input clk; // clock.clk
input reset; // reset.reset
// Mem... | 7.750582 |
module avalon_shell_rsa (
clk,
reset,
//avalon_MM_to_qsys
avm_m0_waitrequest,
avm_m0_address,
avm_m0_read,
avm_m0_write,
avm_m0_readdatavalid,
avm_m0_readdata,
avm_m0_writedata,
//avalon_MM_to_design
avm_design_m0_waitrequest,
avm_design_m0_address,
avm_design_m... | 7.769005 |
module avalon_slave ( /*AUTOARG*/
// Outputs
READDATA,
WAITREQUEST,
READDATAVALID,
// Inputs
CLK,
RESET,
ADDRESS,
BEGINTRANSFER,
BYTE_ENABLE,
READ,
WRITE,
WRITEDATA,
LOCK,
BURSTCOUNT,
BEGINBURSTTRANSFER
);
//
// Fundamental Signals
//
input CLK;... | 7.687723 |
module avalon_slave_edid ( /*autoport*/
//inout
edid_scl,
edid_sda,
//output
slave_readdata,
//input
clk,
reset,
slave_address,
slave_read,
slave_write,
slave_writedata,
slave_byteenable
);
// most of the set values will only be used by the component .tcl file. T... | 9.427509 |
module avalon_slave_to_wb_master (
clk,
rst_n,
av_address,
av_chipselect,
av_byteenable,
av_read,
av_write,
av_readdata,
av_readdatavalid,
av_writedata,
av_waitrequest,
wb_cyc_o,
wb_stb_o,
wb_we_o,
wb_adr_o,
wb_dat_o,
wb_dat_i,
wb_sel_o,
wb_a... | 9.427509 |
module is the avalon mm master to the hps sdram
module avalon_source_tester
#(
//256MB buffer is 64Mword, 26 bits to address
parameter SIZE_OF_COUNTER = 26,
parameter SIZE_OF_PATTERN = 2
)
(
input reset_n,
input clk,
//avalon-st interface, source
output reg [31:0] ... | 8.565313 |
module is the Pseudo-Random Bit Sequence 23 Block
// where g(x) = x^23 + x^18 + x^0
//
// use lsb of m 1st first
// k can be > N, but part of the sequence will be skipped
//
//-------------------------------------------------------------------------------
//
// Copyright 2007 Altera Corporation. All rights reserved. A... | 7.109329 |
module avalon_st_multiplexer (
input wire clk_clk, // clk.clk
input wire [71:0] multiplexer_in0_data, // multiplexer_in0.data
input wire multiplexer_in0_endofpacket, // .endofpacket
output wire multiplexer_in0_ready, ... | 7.428888 |
module avalon_st_multiplexer_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [71:0] out_data, // out.data
output wire out_valid, // .valid
input wire out_ready, // .read... | 7.428888 |
module avalon_st_multiplexer_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [71:0] out_data, // out.data
output wire out_valid, // .valid
input wire out_ready, // .read... | 7.428888 |
module avalon_st_multiplexer (
input wire clk_clk, // clk.clk
input wire [71:0] multiplexer_in0_data, // multiplexer_in0.data
input wire multiplexer_in0_endofpacket, // .endofpacket
output wire multiplexer_in0_ready, ... | 7.428888 |
module avalon_st_to_crc_if_bridge (
CLK,
RESET_N,
AVST_READY,
AVST_VALID,
AVST_SOP,
AVST_DATA,
AVST_EOP,
AVST_EMPTY,
CRC_ENA,
CRC_INIT,
CRC_DATA,
CRC_DATA_SIZE,
CRC_OUT_LATCH
);
parameter DATA_WIDTH = 32; //8,32,64,16(optional)
parameter EMPTY_WIDTH = 2; //x... | 9.535356 |
module avalon_sysctrl (
clk_clk,
reset_reset_n,
mm_bridge_s0_waitrequest,
mm_bridge_s0_readdata,
mm_bridge_s0_readdatavalid,
mm_bridge_s0_burstcount,
mm_bridge_s0_writedata,
mm_bridge_s0_address,
mm_bridge_s0_write,
mm_bridge_s0_read,
mm_bridge_s0_byteenable,
mm_bridge_s0... | 7.40382 |
module avalon_sysctrl_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
sys_reset_req,
// outputs:
readdata
);
parameter INIT_FILE = "avalon_sysctrl_onchip_memory2_0.hex";
output [31:0] readdata;
i... | 7.40382 |
module avalon_to_wb_bridge #(
parameter DW = 32, // Data width
parameter AW = 32 // Address width
) (
input wb_clk_i,
input wb_rst_i,
// Avalon Slave input
input [ AW-1:0] s_av_address_i,
input [DW/8-1:0] s_av_byteenable_i,
input s_av_read_i,
... | 9.295828 |
module avalon_vip #(
parameter BITS = 8,
parameter WIDTH = 1280,
parameter HEIGHT = 960
) (
input clk,
input reset,
// slave control register
input [ 5:0] as_address,
input as_read,
output reg [31:0] as_readdata,
input as_write,
input [31... | 8.436928 |
module AVConfig (
input wire [ 1:0] address, // avalon_av_config_slave.address
input wire [ 3:0] byteenable, // .byteenable
input wire read, // .read
input wire write, // .write
input wire [31:... | 6.563077 |
module AVConfig (
address,
byteenable,
read,
write,
writedata,
readdata,
waitrequest,
clk,
I2C_SDAT,
I2C_SCLK,
reset
);
input [1:0] address;
input [3:0] byteenable;
input read;
input write;
input [31:0] writedata;
output [31:0] readdata;
output waitrequest;
i... | 6.563077 |
module averagefilter (
clk,
m11,
m12,
m13,
m21,
m22,
m23,
m31,
m32,
m33,
mid
);
parameter width = 8;
input clk;
input [width - 1:0] m11;
input [width - 1:0] m12;
input [width - 1:0] m13;
input [width - 1:0] m21;
input [width - 1:0] m22;
input [width - 1:0] m2... | 6.676459 |
module averagefilter (
clk,
m11,
m12,
m13,
m21,
m22,
m23,
m31,
m32,
m33,
mid
);
parameter width = 8;
input clk;
input [width - 1:0] m11;
input [width - 1:0] m12;
input [width - 1:0] m13;
input [width - 1:0] m21;
input [width - 1:0] m22;
input [width - 1:0] m2... | 6.676459 |
module cs_mealyfsm (
clk,
rst,
ready_sample,
ce,
en_comp,
wr_en,
rst_dev,
strobe_writer,
run,
state
);
//state symbols
parameter IDLE = 4'd0;
parameter WRITE_FIFO_S = 4'd1;
parameter STORE_SAMPLE = 4'd2;
parameter DETECTION = 4'd3;
parameter WAIT = 4'd4;
//state r... | 8.420452 |
module
average_pooling #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
ARITH_TYPE = 0
)
(
input clk,
input reset,
input pool_enable,
input [DATA_WIDTH - 1 : 0] pool_data_in_1,
input [DATA_WIDTH - 1 : 0] pool_data_in_2,
input [DATA_WIDTH - 1 : 0... | 6.555487 |
module
average_pooling_S4 #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
ARITH_TYPE = 0
)
(
input clk,
input reset,
input pool_enable,
input [DATA_WIDTH - 1 : 0] pool_data_in_1,
input [DATA_WIDTH - 1 : 0] pool_data_in_2,
input [DATA_WIDTH - 1 ... | 6.555487 |
module moving_average #(
parameter integer in_bits = 16,
parameter integer out_bits = 16,
parameter integer log2_samples = 8
) (
input wire [in_bits-1:0] in_data,
input wire clk,
output wire [out_bits-1:0] out_data
);
localparam integer samples = 2 ** log2_samples;
localparam integer reg_b... | 7.349406 |
module moving_average #(
parameter integer in_bits = 16,
parameter integer out_bits = 16,
parameter integer log2_samples = 8
) (
input wire [in_bits-1:0] in_data,
input wire clk,
output wire [out_bits-1:0] out_data
);
localparam integer reg_bits = in_bits + log2_samples;
reg [reg_bits-1:0... | 7.349406 |
module two_clk_accum #(
parameter integer inc_bits = 32,
parameter integer count_bits = 32,
parameter integer out_bits = 32,
parameter integer out_bus_size = 32 //For AXI interfaces where bus size is a multiple of 8 regardless of number of bits
) (
input wire count_clk,
input wire out_clk,
i... | 6.936444 |
module avg (
din,
reset,
clk,
ready,
dout
);
input reset, clk;
input [15:0] din;
output reg ready;
output reg [15:0] dout;
// ==========================================
// Enter your design below
// ==========================================
reg [15:0] mem[11:0];
reg [20:0] sum;... | 6.69656 |
module avg2pw_reorder_addr_gen (
input clk_calc,
input [25:0] base_addr,
input [10:0] avg2pw_cnt,
output reg [25:0] avg2pw_reorder_addr
);
//一级
reg [25:0] avg2pw_reorder_addr_p;
always @(posedge clk_calc) begin
avg2pw_reorder_addr_p <= base_addr + avg2pw_cnt;
end
//二、三、四级
reg [25:0] ... | 6.866184 |
module avg_calc (
input clk,
input rst,
input [7:0] data,
output reg [7:0] avg
);
reg [18:0] sum;
reg [20:0] cnt;
always @(posedge clk) begin
sum <= rst ? 0 : sum + data;
avg <= rst ? sum / cnt : avg;
cnt <= rst ? 0 : cnt + 1;
end
endmodule
| 7.041508 |
module Avg_pool #(
parameter integer BITWIDTH = 8,
parameter integer DATAWIDTH = 28,
parameter integer DATAHEIGHT = 28,
parameter integer DATACHANNEL = 3,
parameter integer KWIDTH = 2,
parameter integer KHEIGHT = 2
) (
//input clk,
//input clken,
input [BITWIDTH * DATAWIDTH * D... | 6.909449 |
module avg_pool_Add2i1s8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add2i1s8_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in1) + (8'B00000001);
assign out1 = asc001;
endmodule
| 6.632127 |
module avg_pool_Add_32Sx32S_33S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Sx32S_33S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +({in2[31], in2}) + ({in1[31], in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_32Ux32U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_33Ux33U_33U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_Add_8Sx2S_8S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;
assign asc001 = +(in2) + ({{6{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.584011 |
module avg_pool_And_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.016549 |
module avg_pool_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.016549 |
module avg_pool_DECODE_2U_12_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_DECODE_2U_12_4_0 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_DECODE_2U_12_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.071764 |
module avg_pool_Equal_8Sx7S_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_Equal_8Sx7S_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [6:0] in1;
output out1;
wire asc001;
assign asc001 = ({{6{in1[6]}}, in1} == {{5{in2[7]}}, in2});
assign out1 = asc001;
endmodule
| 6.666554 |
module avg_pool_LtnLLs33_1 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
... | 6.542886 |
module avg_pool_LtnLLs33_4 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
... | 6.542886 |
module avg_pool_LtnLLs33_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
... | 6.542886 |
module avg_pool_LtnLLs33_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [32:0] in1;
output out1;
wire asc001;
assign asc001 = ((38'B10000000000000000000000000000000000000 ^ 38'B11111110000000000000000000000000000000)>(38'B10000000000000000000000000000000000000
^ {{5{in1[32]}}, in1}));
... | 6.542886 |
module avg_pool_Muxi0Add2i1s8u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begi... | 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begi... | 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) be... | 6.699082 |
module avg_pool_Muxi0Add2i1s8u1_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001, asc003;
assign asc003 = +(in2) + (8'B00000001);
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) be... | 6.699082 |
module avg_pool_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.676624 |
module avg_pool_N_Muxb_1_2_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
defau... | 6.703286 |
module avg_pool_N_Muxb_1_2_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
defau... | 6.703286 |
module avg_pool_N_Muxb_1_2_4_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
def... | 6.703286 |
module avg_pool_N_Muxb_1_2_4_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
def... | 6.703286 |
module avg_pool_N_Mux_8_2_5_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000... | 6.703286 |
module avg_pool_N_Mux_8_2_5_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B00000000... | 6.703286 |
module avg_pool_N_Mux_8_2_5_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B000000... | 6.703286 |
module avg_pool_N_Mux_8_2_5_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 8'B000000... | 6.703286 |
module avg_pool_N_Mux_8_2_6_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc00... | 6.703286 |
module avg_pool_N_Mux_8_2_6_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc00... | 6.703286 |
module avg_pool_N_Mux_8_2_6_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc... | 6.703286 |
module avg_pool_N_Mux_8_2_6_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [7:0] in3, in2;
input ctrl1;
output [7:0] out1;
wire [7:0] asc001;
reg [7:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc... | 6.703286 |
module avg_pool_Or_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
module avg_pool_Or_1Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.049397 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.