code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module monitors the GTX to detect hard
// errors. All errors are reported to the Global Logic Interface.
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_ERR_DETECT
(
// Lane Init SM Interface
ENABLE_ERR_DETECT,
HARD_ERR_RESET,
// Global Logic Interface
HARD_ERR,
SOFT_ERR,
//Sym Decoder interface
ILLEGAL_BTF,
// GTX Interface
RX_BUF_ERR,
TX_BUF_ERR,
RX_CHAR_IS_K,
RX_RUN_DISP,
RXDATAVALID_IN,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// Lane Init SM Interface
input ENABLE_ERR_DETECT;
output HARD_ERR_RESET;
// Sym decoder Interface
input ILLEGAL_BTF;
// GTX Interface
input RX_BUF_ERR;
input TX_BUF_ERR;
input RX_CHAR_IS_K;
input RX_RUN_DISP;
input RXDATAVALID_IN;
// System Interface
input USER_CLK;
// Global Logic Interface
output HARD_ERR;
output SOFT_ERR;
//**************************External Register Declarations****************************
reg HARD_ERR;
reg SOFT_ERR;
//*********************************Main Body of Code**********************************
//____________________________ Error Processing _________________________________
// Detect Soft Errors
always @(posedge USER_CLK)
if(ENABLE_ERR_DETECT)
begin
SOFT_ERR <= `DLY (((RX_CHAR_IS_K == RX_RUN_DISP) | ILLEGAL_BTF) & RXDATAVALID_IN );
end
else
begin
SOFT_ERR <= `DLY 1'b0;
end
// Detect Hard Errors
always @(posedge USER_CLK)
if(ENABLE_ERR_DETECT)
begin
HARD_ERR <= `DLY (RX_BUF_ERR | TX_BUF_ERR);
end
else
begin
HARD_ERR <= `DLY 1'b0;
end
// Assert hard error reset when there is a hard error. This assignment
// just renames the two fanout branches of the hard error signal.
assign HARD_ERR_RESET = HARD_ERR;
endmodule
| 7.591032 |
module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_GLOBAL_LOGIC
(
// GTX Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
CHAN_BOND_RESET,
// Aurora Lane Interface
LANE_UP,
HARD_ERR,
GEN_NA_IDLES,
GEN_CH_BOND,
RESET_LANES,
GOT_NA_IDLES,
GOT_CCS,
REMOTE_READY,
GOT_CBS,
GOT_IDLES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
CHANNEL_HARD_ERR,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTX Interface
input [0:1] CH_BOND_DONE;
output EN_CHAN_SYNC;
output CHAN_BOND_RESET;
// Aurora Lane Interface
input [0:1] LANE_UP;
input [0:1] HARD_ERR;
input [0:1] GOT_NA_IDLES;
input [0:1] GOT_CCS;
input [0:1] REMOTE_READY;
input [0:1] GOT_CBS;
input [0:1] GOT_IDLES;
output GEN_NA_IDLES;
output [0:1] GEN_CH_BOND;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
input TXDATAVALID_IN;
output CHANNEL_UP;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire reset_channel_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_64b66b_v7_3_CHANNEL_INIT_SM channel_init_sm_i
(
// GTX Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
.CHAN_BOND_RESET(CHAN_BOND_RESET),
// Aurora Lane Interface
.GEN_NA_IDLES(GEN_NA_IDLES),
.RX_NA_IDLES(GOT_NA_IDLES),
.RX_CC(GOT_CCS),
.REMOTE_READY(REMOTE_READY),
.RX_CB(GOT_CBS),
.RX_IDLES(GOT_IDLES),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.LANE_UP(LANE_UP),
.CHANNEL_UP(CHANNEL_UP),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_64b66b_v7_3_CHANNEL_BOND_GEN channel_bond_gen_i
(
// Channel Init SM Interface
.CHANNEL_UP(CHANNEL_UP),
// Aurora Lane Interface
.GEN_CH_BOND(GEN_CH_BOND),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
// Channel Error Management module.
aurora_64b66b_v7_3_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_64b66b_v7_3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == {REM_WIDTH{1'b0}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 7.200193 |
module aurora_64b66b_v7_3_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
LINK_RESET_IN,
SYSTEM_RESET,
INIT_CLK_OUT,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input GT_RESET_IN;
input TX_LOCK_IN;
input PLL_NOT_LOCKED;
input LINK_RESET_IN;
output SYSTEM_RESET;
output GT_RESET_OUT;
output INIT_CLK_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r;
reg [0:3] debounce_gt_rst_r;
reg SYSTEM_RESET;
reg gsr_done_r;
reg gsr_done_2r;
reg [5:0] reset_counter;
reg [3:0] reset_pulse;
//********************************Wire Declarations**********************************
(* KEEP = "TRUE" *)wire init_clk_i;
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b1111;
else
//reset_debounce_r <= {!RESET,reset_debounce_r[0:2]}; //Note: Using active low reset
reset_debounce_r <= {
RESET, reset_debounce_r[0:2]
};
always @(posedge USER_CLK)
SYSTEM_RESET <= &reset_debounce_r || PLL_NOT_LOCKED || !TX_LOCK_IN || LINK_RESET_IN;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge INIT_CLK)
//debounce_gt_rst_r <= {!GT_RESET_IN,debounce_gt_rst_r[0:2]};
debounce_gt_rst_r <= {
GT_RESET_IN, debounce_gt_rst_r[0:2]
};
assign gt_rst_r = &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
assign INIT_CLK_OUT = INIT_CLK;
endmodule
| 7.200193 |
module takes regular data in Aurora format
// and transforms it to LocalLink formatted data
//
//
//
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_RX_STREAM_DATAPATH
(
//Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
//Flow control signals
// Global Logic
CHANNEL_UP,
//RX LocalLink Interface
RX_D,
RX_SRC_RDY_N,
//System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:127] RX_PE_DATA;
input [0:1] RX_PE_DATA_V;
// Global Logic
input CHANNEL_UP;
//LocalLink Interface
output [0:127] RX_D;
output RX_SRC_RDY_N;
//System Interface
input USER_CLK;
input RESET;
//****************************External Register Declarations**************************
reg [0:127] RX_D;
reg RX_SRC_RDY_N;
//*********************************Wire Declarations**********************************
wire src_rdy_n_c;
wire rx_pe_data_v_c;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
if(RESET)
RX_D <= `DLY 128'b0;
else if ( CHANNEL_UP & |RX_PE_DATA_V )
RX_D <= `DLY RX_PE_DATA;
assign rx_pe_data_v_c = & RX_PE_DATA_V;
assign src_rdy_n_c = (CHANNEL_UP & rx_pe_data_v_c);
//Register the SRC_RDY_N signal
always @(posedge USER_CLK)
if(RESET)
RX_SRC_RDY_N <= `DLY 1'b1;
else if( src_rdy_n_c )
RX_SRC_RDY_N <= `DLY 1'b0;
else
RX_SRC_RDY_N <= `DLY 1'b1;
endmodule
| 6.652678 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_TX_STREAM
(
// LocalLink Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// Clock Compensation Interface
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
TX_PE_DATA_V,
TX_PE_DATA,
GEN_CC,
// GTX Interface
TXDATAVALID_IN,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink Interface
input [0:127] TX_D;
input TX_SRC_RDY_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output [0:1] TX_PE_DATA_V;
output [0:127] TX_PE_DATA;
output [0:1] GEN_CC;
// GTX Interface
input TXDATAVALID_IN;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL_SM and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_64b66b_v7_3_TX_STREAM_DATAPATH tx_stream_datapath_i
(
// LocalLink Interface
.TX_D(TX_D),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.USER_CLK(USER_CLK)
);
// TX_STREAM_Control module
aurora_64b66b_v7_3_TX_STREAM_CONTROL_SM tx_stream_control_sm_i
(
// LocalLink Interface
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
// Aurora Lane Interface
.GEN_CC(GEN_CC),
// GTX Interface
.TXDATAVALID_IN(TXDATAVALID_IN),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module pipelines the data path in compliance
// with Local Link protocol. Provides data to Aurora Lane
// in the required format
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_TX_STREAM_DATAPATH
(
// LocalLink Interface
TX_D,
TX_SRC_RDY_N,
// Aurora Lane Interface
TX_PE_DATA_V,
TX_PE_DATA,
// TX_STREAM Control Module Interface
TX_DST_RDY_N,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink Interface
input [0:127] TX_D;
input TX_SRC_RDY_N;
// Aurora Lane Interface
output [0:1] TX_PE_DATA_V;
output [0:127] TX_PE_DATA;
// TX_STREAM Control Module Interface
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
//**************************External Register Declarations****************************
reg [0:127] TX_PE_DATA;
reg [0:1] TX_PE_DATA_V;
//******************************Internal Wire Declarations****************************
wire in_frame_c;
wire ll_valid_c;
wire [0:127] tx_pe_data_c;
wire [0:1] tx_pe_data_v_c;
//*********************************Main Body of Code**********************************
// LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
assign ll_valid_c = !TX_SRC_RDY_N && !TX_DST_RDY_N;
assign in_frame_c = ll_valid_c ;
// Multiplex between UFC Messages & User data
assign tx_pe_data_c = TX_D;
//Assign tx_pe_data_v_c based on Protocol rules
//IN SA=1 Following rules are followed
//1. Lanes higher than SEP can't have data
//2. UFCH is sent only on the last lane
assign tx_pe_data_v_c[0] = (ll_valid_c) ? 1'b1 :
1'b0 ;
assign tx_pe_data_v_c[1] = (ll_valid_c) ? 1'b1 :
1'b0 ;
// Implement the data out register.
always @(posedge USER_CLK)
begin
TX_PE_DATA <= `DLY tx_pe_data_c;
TX_PE_DATA_V <= `DLY tx_pe_data_v_c;
end
endmodule
| 7.885372 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 16 from gtx to 32 into the aurora.
/////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_WIDTH_CONVERSION #
(
parameter INPUT_WIDTH =2,
parameter OUTPUT_WIDTH=4
)
(
//Output to the Aurora Protocol interface
DATA_OUT,
//Input from the GTX
DATA_IN,
// Sync header from GTX Interface
HEADER_IN,
DATAVALID_IN,
// Sync header to Aurora
HEADER_OUT,
DATAVALID_OUT,
//Clock and reset
USER_CLK,
ENABLE,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
input RESET;
input USER_CLK;
input ENABLE;
input [INPUT_WIDTH*8-1:0] DATA_IN;
output [OUTPUT_WIDTH*8-1:0] DATA_OUT;
output [1:0] HEADER_OUT;
output DATAVALID_OUT;
//*****************************MGT Interface**************************
input [1:0] HEADER_IN;
input DATAVALID_IN;
//*****************************External Register Declarations**************************
reg [OUTPUT_WIDTH*8-1:0] DATA_OUT;
reg [1:0] HEADER_OUT;
//*****************************Internal Register Declarations**************************
reg [INPUT_WIDTH*8-1:0] data_in_r;
reg [INPUT_WIDTH*8-1:0] data_in_r2;
reg [1:0] header_in_r;
reg [1:0] header_in_r2;
reg datavalid_r;
reg datavalid_r2;
reg datavalid_neg_r;
reg datavalid_pos_r;
reg state;
//*****************************Beginning of Code *************************
always @(posedge USER_CLK)
begin
data_in_r <= `DLY DATA_IN;
data_in_r2 <= `DLY data_in_r;
header_in_r <= `DLY HEADER_IN;
header_in_r2 <= `DLY header_in_r;
end
always @(posedge USER_CLK)
begin
datavalid_r <= `DLY DATAVALID_IN;
datavalid_r2 <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
begin
if(RESET)
state <= `DLY 1'b1;
else if (ENABLE && datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b0;
else if (ENABLE && !datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b1;
end
always @(posedge USER_CLK)
if(ENABLE)
begin
datavalid_pos_r <= `DLY datavalid_r;
end
always @(negedge USER_CLK)
begin
datavalid_neg_r <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
if(RESET) DATA_OUT <= `DLY 32'b0;
else if(ENABLE)
begin
if(state)
DATA_OUT <= `DLY {data_in_r2,data_in_r};
else if(!state)
DATA_OUT <= `DLY {data_in_r,DATA_IN};
end
always @(posedge USER_CLK)
if (RESET) HEADER_OUT <= `DLY 2'b0;
else if(ENABLE)
begin
if(!state)
HEADER_OUT <= `DLY header_in_r;
else if(state)
HEADER_OUT <= `DLY header_in_r2;
end
assign DATAVALID_OUT = datavalid_pos_r;
endmodule
| 6.595174 |
module aurora_8b10b_1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP[0] + AXI4_S_IP_TX_TKEEP[1] + AXI4_S_IP_TX_TKEEP[2] + AXI4_S_IP_TX_TKEEP[3]) - 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_1_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg [0:1] soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r[0] |
soft_err_r[1];
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_1_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, the error count is incremented until it
// reaches its max value.
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_1_FRAME_CHECK
(
// User Interface
RX_D,
RX_SRC_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP,
ERR_COUNT
);
//***********************************Port Declarations*******************************
// User Interface
input [0:31] RX_D;
input RX_SRC_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
output [0:7] ERR_COUNT;
//***************************Internal Register Declarations***************************
reg [0:8] err_count_r;
// RX Data registers
reg [0:15] data_lfsr_r;
//*********************************Wire Declarations**********************************
wire reset_c;
wire [0:31] data_lfsr_concat_w;
wire data_valid_c;
wire data_err_detected_c;
reg data_err_detected_r;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Capture incoming data ___________________________
//Data is valid when RX_SRC_RDY_N is asserted
assign data_valid_c = !RX_SRC_RDY_N;
//generate expected RX_D using LFSR
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hD5E6; //random seed value
end
else if(data_valid_c)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
end
assign data_lfsr_concat_w = {2{data_lfsr_r}};
//___________________________ Check incoming data for errors __________________________
//An error is detected when LFSR generated RX data from the data_lfsr_concat_w register,
//does not match valid data from the RX_D port
assign data_err_detected_c = (data_valid_c && (RX_D != data_lfsr_concat_w));
//We register the data_err_detected_c signal for use with the error counter logic
always @(posedge USER_CLK)
data_err_detected_r <= `DLY data_err_detected_c;
//Compare the incoming data with calculated expected data.
//Increment the ERROR COUNTER if mismatch occurs.
//Stop the ERROR COUNTER once it reaches its max value (i.e. 255)
always @(posedge USER_CLK)
if(reset_c)
err_count_r <= `DLY 9'd0;
else if(&err_count_r)
err_count_r <= `DLY err_count_r;
else if(data_err_detected_r)
err_count_r <= `DLY err_count_r + 1;
//Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
//max value) to the module output
assign ERR_COUNT = err_count_r[1:8];
endmodule
| 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the pseudo-random
// data and lower bits of LFSR are connected to REM bus
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_1_FRAME_GEN
(
// User Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
//*****************************Parameter Declarations****************************
//***********************************Port Declarations*******************************
// User Interface
output [0:31] TX_D;
output TX_SRC_RDY_N;
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
//***************************External Register Declarations***************************
reg TX_SRC_RDY_N;
//***************************Internal Register Declarations***************************
reg [0:15] data_lfsr_r;
wire reset_c;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Transmit Data __________________________________
//Transmit data when TX_DST_RDY_N is asserted.
//Random data is generated using XNOR feedback LFSR
//TX_SRC_RDY_N is asserted on every cycle with data
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hABCD; //random seed value
TX_SRC_RDY_N <= `DLY 1'b1;
end
else if(!TX_DST_RDY_N)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
TX_SRC_RDY_N <= `DLY 1'b0;
end
//Connect TX_D to the DATA LFSR register
assign TX_D = {2{data_lfsr_r}};
endmodule
| 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_1_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:1] SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output GEN_A;
output [0:3] GEN_K;
output [0:3] GEN_R;
output [0:3] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_1_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_1_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_1_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == {REM_WIDTH{1'b1}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM + 1'b1)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module aurora_8b10b_1_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input GT_RESET_IN;
input TX_LOCK_IN;
input PLL_NOT_LOCKED;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r;
reg [0:3] debounce_gt_rst_r;
reg reset_debounce_r2;
reg reset_debounce_r3;
reg reset_debounce_r4;
wire SYSTEM_RESET;
//********************************Wire Declarations**********************************
wire init_clk_i;
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b1111;
else reset_debounce_r <= {!RESET, reset_debounce_r[0:2]}; //Note: Using active low reset
always @(posedge USER_CLK) begin
reset_debounce_r2 <= &reset_debounce_r;
reset_debounce_r3 <= reset_debounce_r2 || !TX_LOCK_IN;
reset_debounce_r4 <= reset_debounce_r3;
end
assign SYSTEM_RESET = reset_debounce_r4 || PLL_NOT_LOCKED;
// Assign an IBUFG to INIT_CLK
assign INIT_CLK = init_clk_i;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge init_clk_i) debounce_gt_rst_r <= {GT_RESET_IN, debounce_gt_rst_r[0:2]};
assign gt_rst_r = &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
endmodule
| 8.673171 |
module aurora_8b10b_2_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP[0] + AXI4_S_IP_TX_TKEEP[1] + AXI4_S_IP_TX_TKEEP[2] + AXI4_S_IP_TX_TKEEP[3]) - 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_2_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg [0:1] soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r[0] |
soft_err_r[1];
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_2_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, the error count is incremented until it
// reaches its max value.
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_2_FRAME_CHECK
(
// User Interface
RX_D,
RX_SRC_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP,
ERR_COUNT
);
//***********************************Port Declarations*******************************
// User Interface
input [0:31] RX_D;
input RX_SRC_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
output [0:7] ERR_COUNT;
//***************************Internal Register Declarations***************************
reg [0:8] err_count_r;
// RX Data registers
reg [0:15] data_lfsr_r;
//*********************************Wire Declarations**********************************
wire reset_c;
wire [0:31] data_lfsr_concat_w;
wire data_valid_c;
wire data_err_detected_c;
reg data_err_detected_r;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Capture incoming data ___________________________
//Data is valid when RX_SRC_RDY_N is asserted
assign data_valid_c = !RX_SRC_RDY_N;
//generate expected RX_D using LFSR
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hD5E6; //random seed value
end
else if(data_valid_c)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
end
assign data_lfsr_concat_w = {2{data_lfsr_r}};
//___________________________ Check incoming data for errors __________________________
//An error is detected when LFSR generated RX data from the data_lfsr_concat_w register,
//does not match valid data from the RX_D port
assign data_err_detected_c = (data_valid_c && (RX_D != data_lfsr_concat_w));
//We register the data_err_detected_c signal for use with the error counter logic
always @(posedge USER_CLK)
data_err_detected_r <= `DLY data_err_detected_c;
//Compare the incoming data with calculated expected data.
//Increment the ERROR COUNTER if mismatch occurs.
//Stop the ERROR COUNTER once it reaches its max value (i.e. 255)
always @(posedge USER_CLK)
if(reset_c)
err_count_r <= `DLY 9'd0;
else if(&err_count_r)
err_count_r <= `DLY err_count_r;
else if(data_err_detected_r)
err_count_r <= `DLY err_count_r + 1;
//Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
//max value) to the module output
assign ERR_COUNT = err_count_r[1:8];
endmodule
| 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the pseudo-random
// data and lower bits of LFSR are connected to REM bus
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_2_FRAME_GEN
(
// User Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
//*****************************Parameter Declarations****************************
//***********************************Port Declarations*******************************
// User Interface
output [0:31] TX_D;
output TX_SRC_RDY_N;
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
//***************************External Register Declarations***************************
reg TX_SRC_RDY_N;
//***************************Internal Register Declarations***************************
reg [0:15] data_lfsr_r;
wire reset_c;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Transmit Data __________________________________
//Transmit data when TX_DST_RDY_N is asserted.
//Random data is generated using XNOR feedback LFSR
//TX_SRC_RDY_N is asserted on every cycle with data
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hABCD; //random seed value
TX_SRC_RDY_N <= `DLY 1'b1;
end
else if(!TX_DST_RDY_N)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
TX_SRC_RDY_N <= `DLY 1'b0;
end
//Connect TX_D to the DATA LFSR register
assign TX_D = {2{data_lfsr_r}};
endmodule
| 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:1] SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output GEN_A;
output [0:3] GEN_K;
output [0:3] GEN_R;
output [0:3] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_2_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_2_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_2_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_2_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == {REM_WIDTH{1'b1}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM + 1'b1)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module aurora_8b10b_2_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input GT_RESET_IN;
input TX_LOCK_IN;
input PLL_NOT_LOCKED;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r;
reg [0:3] debounce_gt_rst_r;
reg reset_debounce_r2;
reg reset_debounce_r3;
reg reset_debounce_r4;
wire SYSTEM_RESET;
//********************************Wire Declarations**********************************
wire init_clk_i;
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b1111;
else reset_debounce_r <= {!RESET, reset_debounce_r[0:2]}; //Note: Using active low reset
always @(posedge USER_CLK) begin
reset_debounce_r2 <= &reset_debounce_r;
reset_debounce_r3 <= reset_debounce_r2 || !TX_LOCK_IN;
reset_debounce_r4 <= reset_debounce_r3;
end
assign SYSTEM_RESET = reset_debounce_r4 || PLL_NOT_LOCKED;
// Assign an IBUFG to INIT_CLK
assign INIT_CLK = init_clk_i;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge init_clk_i) debounce_gt_rst_r <= {GT_RESET_IN, debounce_gt_rst_r[0:2]};
assign gt_rst_r = &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
endmodule
| 8.673171 |
module aurora_8b10b_AXI_TO_LL_EXDES #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter BC = DATA_WIDTH/8, //Byte count
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
wire [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP_i;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign AXI4_S_IP_TX_TKEEP_i = AXI4_S_IP_TX_TKEEP;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP_i[0] + AXI4_S_IP_TX_TKEEP_i[1] + AXI4_S_IP_TX_TKEEP_i[2] + AXI4_S_IP_TX_TKEEP_i[3] + AXI4_S_IP_TX_TKEEP_i[4] + AXI4_S_IP_TX_TKEEP_i[5] + AXI4_S_IP_TX_TKEEP_i[6] + AXI4_S_IP_TX_TKEEP_i[7] + AXI4_S_IP_TX_TKEEP_i[8] + AXI4_S_IP_TX_TKEEP_i[9] + AXI4_S_IP_TX_TKEEP_i[10] + AXI4_S_IP_TX_TKEEP_i[11] + AXI4_S_IP_TX_TKEEP_i[12] + AXI4_S_IP_TX_TKEEP_i[13] + AXI4_S_IP_TX_TKEEP_i[14] + AXI4_S_IP_TX_TKEEP_i[15]) - 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_fmc1,aurora_8b10b_v10_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTXQ5,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=1,c_gt_loc_22=2,c_gt_loc_23=3,c_gt_loc_24=4,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=44000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=275000,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=false,flow_mode=None,interface_mode=Streaming,dataflow_config=Duplex}" *)
module aurora_8b10b_fmc1_CLOCK_MODULE
(
INIT_CLK_IN,
INIT_CLK_O,
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input INIT_CLK_IN;
output INIT_CLK_O;
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
// Assign an IBUFDS to INIT_CLK
assign INIT_CLK_O = INIT_CLK_IN;
endmodule
| 6.806955 |
module aurora_8b10b_fmc1_SUPPORT_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK_IN,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK_IN;
input GT_RESET_IN;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
(* ASYNC_REG = "true" *) (* shift_extract = "{no}" *)reg [0:3] debounce_gt_rst_r = 4'd0;
reg [0:3] reset_debounce_r;
reg reset_debounce_r2;
reg gt_rst_r;
//********************************Wire Declarations**********************************
wire gt_rst_sync;
wire SYSTEM_RESET;
//*********************************Main Body of Code**********************************
//Reset sync from INIT_CLK to USER_CLK
aurora_8b10b_fmc1_cdc_sync_exdes #(
.c_cdc_type (1),
.c_flop_input (0),
.c_reset_state (0),
.c_single_bit (1),
.c_vector_width(2),
.c_mtbf_stages (3)
) gt_rst_r_cdc_sync (
.prmry_aclk (INIT_CLK_IN),
.prmry_rst_n (1'b1),
.prmry_in (gt_rst_r),
.prmry_vect_in (2'd0),
.scndry_aclk (USER_CLK),
.scndry_rst_n (1'b1),
.prmry_ack (),
.scndry_out (gt_rst_sync),
.scndry_vect_out()
);
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_sync)
if (gt_rst_sync) reset_debounce_r <= 4'b1111;
else reset_debounce_r <= {RESET, reset_debounce_r[0:2]};
always @(posedge USER_CLK) reset_debounce_r2 <= &reset_debounce_r;
assign SYSTEM_RESET = reset_debounce_r2;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge INIT_CLK_IN) debounce_gt_rst_r <= {GT_RESET_IN, debounce_gt_rst_r[0:2]};
always @(posedge INIT_CLK_IN) gt_rst_r <= &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
endmodule
| 8.673171 |
module aurora_8b10b_gtx1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx1,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ1,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=1,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx1_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx1_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx1_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx1_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx1_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx1_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx1_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx1_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx1_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx1_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx1_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx2_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx2,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ1,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=1,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx2_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx2_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx2_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx2_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx2_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx2_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx2_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx2_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx2_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx2_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx2_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx2_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx3,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=1,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx3_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx3_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx3_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx3_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx3_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx3_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx3_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx3_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx3_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx3_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx4_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx4,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx4_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx4_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx4_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx4_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx4_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx4_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx4_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx4_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx4_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx4_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx4_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx4_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx5_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx5,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx5_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx5_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx5_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx5_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx5_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx5_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx5_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx5_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx5_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx5_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx5_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx5_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx6_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx6,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx6_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx6_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx6_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx6_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx6_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx6_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx6_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx6_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx6_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx6_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx6_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx6_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx7_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx7,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx7_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx7_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx7_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx7_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx7_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx7_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx7_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx7_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx7_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx7_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx7_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx7_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_gtx8_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_gtx8,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=1,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_gtx8_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_gtx8_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_gtx8_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_gtx8_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_gtx8_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_gtx8_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_gtx8_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_gtx8_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_gtx8_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_gtx8_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_gtx8_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_gtx8_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module aurora_8b10b_LL_TO_AXI_EXDES #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC
parameter BC = DATA_WIDTH / 8, //Byte count
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
wire [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP_i;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TKEEP = AXI4_S_OP_TKEEP_i;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP_i = (LL_IP_REM == {REM_WIDTH{1'b1}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM + 1'b1)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
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