code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module monitors the GTX to detect hard
// errors. All errors are reported to the Global Logic Interface.
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_ERR_DETECT
(
// Lane Init SM Interface
ENABLE_ERR_DETECT,
... | 7.591032 |
module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_GLOBAL_LOGIC
(
// GTX Interface
CH_BOND_DONE,
EN_CHAN_... | 8.183782 |
module aurora_64b66b_v7_3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL... | 7.200193 |
module aurora_64b66b_v7_3_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
LINK_RESET_IN,
SYSTEM_RESET,
INIT_CLK_OUT,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*********************... | 7.200193 |
module takes regular data in Aurora format
// and transforms it to LocalLink formatted data
//
//
//
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_RX_STREAM_DATAPATH
(
//Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
//Flow control signals
// Global Logic
CHA... | 6.652678 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_TX_STREAM
(
// LocalLink Interfac... | 6.878357 |
module pipelines the data path in compliance
// with Local Link protocol. Provides data to Aurora Lane
// in the required format
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_TX_STREAM_DATAPATH
(
// ... | 7.885372 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 16 from gtx to 32 into the aurora.
/////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_WIDTH_CO... | 6.595174 |
module aurora_8b10b_1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_1_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//**************... | 7.382845 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, th... | 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the p... | 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_1_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora ... | 8.183782 |
module aurora_8b10b_1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_... | 8.673171 |
module aurora_8b10b_1_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
... | 8.673171 |
module aurora_8b10b_2_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_2_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//**************... | 7.382845 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, th... | 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the p... | 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora ... | 8.183782 |
module aurora_8b10b_2_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_... | 8.673171 |
module aurora_8b10b_2_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
... | 8.673171 |
module aurora_8b10b_AXI_TO_LL_EXDES #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter BC = DATA_WIDTH/8, //Byte count
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NF... | 8.673171 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module aurora_8b10b_fmc1_SUPPORT_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK_IN,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input ... | 8.673171 |
module aurora_8b10b_gtx1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx1_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx1_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx1_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx2_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx2_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx2_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx2_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx2_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx3_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx3_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx4_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx4_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx4_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx4_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx4_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx5_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx5_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx5_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx5_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx5_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx6_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx6_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx6_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx6_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx6_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx7_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx7_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx7_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx7_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx7_TX_LL
(... | 6.878357 |
module aurora_8b10b_gtx8_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_gtx8_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_gtx8_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_gtx8_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_gtx8_TX_LL
(... | 6.878357 |
module aurora_8b10b_LL_TO_AXI_EXDES #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC... | 8.673171 |
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