code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module attiny11 (
input clk,
input rst,
inout [5:0] portb,
input T0
);
wire [5:0] io_addr;
wire [7:0] io_data;
wire io_read;
wire io_write;
wire rst_inv;
avr_cpu cpu (
.clk(clk),
.rst(~rst_inv),
.io_addr(io_addr),
.io_data(io_data),
.io_read(io_read),
.... | 6.780749 |
module attosoc (
input clk,
output reg [7:0] led,
output uart_tx,
input uart_rx
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 8192;
parameter [31:0] STACKADDR = 32'h0000_0000 + (4 *... | 6.579166 |
modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = r... | 7.300142 |
module attrib01_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.308584 |
module attrib02_bar (
clk,
rst,
inp,
out
);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
input wire rst;
input wire inp;
(* an_output_register = 1*)
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.659062 |
module attrib02_foo (
clk,
rst,
inp,
out
);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
attrib02_bar bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 7.371222 |
module attrib03_bar (
clk,
rst,
inp,
out
);
(* bus_width *)
parameter WIDTH = 2;
(* an_attribute_on_localparam = 55 *)
localparam INCREMENT = 5;
input wire clk;
input wire rst;
input wire [WIDTH-1:0] inp;
output reg [WIDTH-1:0] out;
always @(posedge clk)
if (rst) out <= 0;
... | 8.69639 |
module attrib03_foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp;
output wire [7:0] out;
attrib03_bar #(
.WIDTH(8)
) bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 7.081502 |
module attrib04_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
(* this_is_a_prescaler *)
reg [7:0] counter;
(* temp_wire *)
wire out_val;
always @(posedge clk) counter <= counter + 1;
assign out_val = inp ^ counter[4];
always @(pose... | 7.386468 |
module attrib04_foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output wire out;
attrib04_bar bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 6.666588 |
module foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (
(* clock_connected *)
clk,
rst, (* this_is_the_input *)
inp,
out
);
endmodule
| 7.455869 |
module attrib06_bar (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp_a + (* ripple_adder *) inp_b;
endmodule
| 7.848172 |
module attrib06_foo (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
attrib06_bar bar_instance (
clk,
rst,
inp_a,
inp_b,
out
);
endmodule
| 6.74449 |
module foo (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
endmodule
| 7.455869 |
module attrib08_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.442618 |
module attrib09_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire [1:0] inp;
output reg [1:0] out;
always @(inp)
(* full_case, parallel_case *) case (inp)
2'd0: out <= 2'd3;
2'd1: out <= 2'd2;
2'd2: out <= 2'd1;
2'd3: out <= 2'd0;
endcase
... | 6.969608 |
module block_ram #(
parameter DATA_WIDTH = 4,
ADDRESS_WIDTH = 10
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
lo... | 7.663566 |
module distributed_ram #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);... | 7.433368 |
module distributed_ram_manual #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDT... | 7.433368 |
module distributed_ram_manual_syn #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_... | 7.433368 |
module attr_rom (
input [9:0] addr,
output [7:0] data_out
);
reg [7:0] store[0:1023] /* verilator public_flat */;
initial begin
$readmemh("attr.mem", store);
end
assign data_out = store[addr];
endmodule
| 7.974822 |
module attr_set (
output [1:0] out
);
assign out = 2'd2;
endmodule
| 7.106979 |
module aTx (
clk,
rst,
iStart,
iDataIn,
iNtxB,
oByteCnt,
oTx,
oStop
);
//-----PARAMETERS------------------------
parameter FCLK = 10000; // [kHz] System clock frequency, max freq = 50000 kHz
parameter BRATE = 115200; // [baud] Baudrate, min brate = 9600 baud
parameter STOP_HO... | 7.865136 |
module auction #(
parameter N = 2,
W = 2
) ( //b = W, n = 2^N
input [(2**N)*W-1:0] bid,
output [N-1:0] winner,
output [W-1:0] winning_bid
);
genvar i;
wire [W-1:0] B[2**N-1:0];
generate
for (i = 0; i < 2 ** N; i = i + 1) begin
assign B[i] = bid[(i+1)*W-1:i*W];
end
endgenerate... | 7.385357 |
module auction_BMR //b = W, n = 2^N
#(
parameter N = 2,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.07434 |
module auction_BMR_2_16 #(
parameter N = 2,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.954014 |
module auction_BMR_2_32 #(
parameter N = 2,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.954014 |
module auction_BMR_3_16 #(
parameter N = 3,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.969339 |
module auction_BMR_3_32 #(
parameter N = 3,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.969339 |
module auction_BMR_4_16 #(
parameter N = 4,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.989207 |
module auction_BMR_4_32 #(
parameter N = 4,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.989207 |
module auction_tb;
parameter N = 3, W = 3;
wire [(2**N)*W-1:0] bid;
wire [N-1:0] winner;
wire [W-1:0] winning_bid;
reg [W-1:0] B[2**N-1:0];
genvar i;
generate
for (i = 0; i < 2 ** N; i = i + 1) assign bid[(i+1)*W-1:i*W] = B[i];
endgenerate
reg clk;
always #5 clk = ~clk;
initial begin
... | 6.72648 |
module aud (
aud_data,
aud_lrck,
aud_bck,
rst,
smpl,
clk
);
output aud_data;
output reg aud_lrck;
output reg aud_bck;
input rst;
input [15:0] smpl;
input clk;
parameter REF_CLK = 18_432_000; /* 18.432MHz */
parameter SMPL_RATE = 48000;
parameter SMPL_SIZE = 16;
parameter CH... | 6.762015 |
module audio3 (
// Clock Input (50 MHz)
input CLOCK_50, // 50 MHz
input CLOCK_27, // 27 MHz
// Push Buttons
input [1:0] KEY,
// TV Decoder
output TD_RESET, // TV Decoder Reset
// I2C
inout I2C_SDAT, // I2C Data
output I2C_SCLK, // I2C Clock
// Audio CODEC
output/*inou... | 8.672979 |
module AudioADC (
input clk, //50Mhz
input rst, //reset
input AUD_BCLK, //Audio chip clock
input AUD_ADCLRCK, //Will go high when ready for data.
input AUD_ADCDAT, //The data to receive on each pulse
output reg done, //Pulses high on done
output reg [31:0] data //The full data we wan... | 7.189319 |
module for the 44.1 kHz clock project from section 4.4.3
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AudioClockTop(
input clk,
output [7:0] JB
);
AudioClock... | 7.518202 |
module AudioCodec (
input wire [15:0] to_dac_left_channel_data, // avalon_left_channel_sink.data
input wire to_dac_left_channel_valid, // .valid
output wire to_dac_left_channel_ready, // .ready
input wire from_... | 7.02599 |
module AudioCodec (
to_dac_left_channel_data,
to_dac_left_channel_valid,
to_dac_left_channel_ready,
from_adc_left_channel_ready,
from_adc_left_channel_data,
from_adc_left_channel_valid,
to_dac_right_channel_data,
to_dac_right_channel_valid,
to_dac_right_channel_ready,
from_adc_ri... | 7.02599 |
module AudioDAC (
input clk, //50Mhz
input rst, //reset
input AUD_BCLK, //Audio chip clock
input AUD_DACLRCK, //Will go high when ready for data.
input [31:0] data, //The full data we want to send.
output reg done, //Pulses high on done
output reg AUD_DACDAT //The data to send out on... | 7.144818 |
module audiodac_dsmod #(
parameter BW = 16
) (
input [BW-1:0] data_i,
output wire data_rd_o,
output reg ds_o,
output wire ds_n_o,
input rst_n_i,
input clk_i,
input mode_i,
input [3:0] scale_i, // 0 = off, 15 = max scale
input [1:0] osr_i // 0 = 32; 1 = 64,... | 7.522957 |
module audiodac_fifo #(
parameter WIDTH = 16,
FIFO_SIZE = 5,
FIFO_ASYNC = 1
) (
// 0=sync, 1=async write I/F
input [WIDTH-1:0] fifo_indata_i,
input fifo_indata_rdy_i,
// note that fifo_indata_i and fifo_indata_rdy_i could originate from
// an asynchronous clk do... | 8.649418 |
module audiodac_python_tb;
localparam SIM_MODE = `SIM_MODE;
localparam SIM_OSR = `SIM_OSR;
localparam SIM_VOLUME = `SIM_VOLUME;
localparam DATA_SAMPLES = `SIM_DATA_SAMPLES;
// large memory to hold the audio
reg signed [15:0] DATA_IN [ 0:DATA_SAMPLES-1];
// output resu... | 7.959826 |
module audiodac_sinegen #(
parameter BW = 16,
parameter LUT_SIZE = 6,
parameter SINE_AMPL = 0.9
) (
output wire signed [BW-1:0] data_o,
input data_rd_i,
input rst_n_i,
input clk_i,
input tst_sinegen_en_i,
... | 6.74019 |
module audiodac_tb;
localparam SIM_MODE = 0;
localparam SIM_OSR = 2;
localparam SIM_VOLUME = 0;
// housekeeping for getting data in
`ifdef SIM_LONG
localparam DATA_SAMPLES = 44100 * 10;
`endif
`ifdef SIM_SHORT
localparam DATA_SAMPLES = 44100 * 1;
`endif
reg [15:0] DATA_IN[0:DATA_SAMPLES-1]; // large m... | 7.794899 |
module AudioInit (
input rst,
input clk,
input initPulse,
inout SDAT, //i2c data line
output SDCLK, //i2c clock out.
output reg doneInit, //Goes high when the module is done doing its thing
output [3:0] audioInitError,
input manualSend, //Pulse high to send i2c data manually.
in... | 6.832796 |
module AudioInterface (
input clk,
input reset,
input ADC_SDATA,
output DAC_SDATA,
output BCLK,
output MCLK,
output LRCLK,
inout SCL,
inout SDA,
output error,
input [23:0] LeftPlayData,
input [23:0] RightPlayData,
output [23:0] LeftRecData,
output [23:0] RightRecD... | 6.957491 |
module ClkDivider (
clk,
clk_div
);
localparam constantNumber = 37500000; //10Hz, FOR THE BOARD
//localparam constantNumber = 2; //FOR THE SIMULATION
input clk;
output clk_div;
reg [31:0] count = 0;
reg clk_div = 0;
always @(posedge (clk)) begin
if (count == constantNumber - 1) count <= 3... | 6.643482 |
module
//////////////////////////////////////////////////////////////////////////////////
module AudioMux(
input clk,
input reset_n,
input run,
input [1:0] select,
input l_i2sToPcm_d_en,
input r_i2sToPcm_d_en,
... | 6.558648 |
module AudioOutput (
input reset_n,
clk,
ce2Hd,
input [15:0] BA,
input CIOn,
BRWn,
input [7:0] BD,
input COCKTAIL,
input STARTJMP1,
STARTJMP2,
output [7:0] pokey_to_cpu,
output [7:0] SOUT
);
wire cs_pokey3B = ~CIOn & ~BA[9];
wire cs_pokey3D = ~CIOn & BA[9];
wir... | 7.17775 |
module AudioOut_1b (
clk,
butt_1,
butt_2,
butt_3,
butt_4,
oct,
audio_out
);
input clk;
input butt_1;
input butt_2;
input butt_3;
input butt_4;
output reg audio_out;
integer count1;
//integer count2;
//integer count3;
//integer count4;
//reg countTo;
integer note_1;... | 7.032128 |
module AudioPLL_audio_pll_0 (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire audio_clk_clk, // audio_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire audio_pll_locked_export; // audio_pll:locked -> re... | 6.585036 |
module AudioPLL_audio_pll_0_audio_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_... | 6.585036 |
module AudioPWM (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////// KEY /... | 7.386683 |
module audioqsys_a_fefifo_7cf (
r_sync_rst,
b_full1,
b_non_empty1,
counter_reg_bit_3,
counter_reg_bit_2,
counter_reg_bit_0,
counter_reg_bit_1,
counter_reg_bit_4,
counter_reg_bit_5,
t_ena,
rvalid,
wreq,
clock
) /* synthesis synthesis_greybox=1 */;
input r_sync_rst;
... | 6.559673 |
module audioqsys_a_fefifo_7cf_1 (
r_sync_rst,
counter_reg_bit_3,
counter_reg_bit_0,
counter_reg_bit_2,
counter_reg_bit_1,
b_full1,
counter_reg_bit_5,
counter_reg_bit_4,
b_non_empty1,
r_val,
wreq,
clock
) /* synthesis synthesis_greybox=1 */;
input r_sync_rst;
output c... | 6.559673 |
module audioqsys_decode_msa (
src_data_51,
src_data_52,
wren,
w_anode1088w_2,
w_anode1096w_2,
w_anode1075w_2,
w_anode1104w_2
) /* synthesis synthesis_greybox=1 */;
input src_data_51;
input src_data_52;
input wren;
output w_anode1088w_2;
output w_anode1096w_2;
output w_anode1075w... | 6.970696 |
module audioqsys_ENABLE_HEADBANG (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input ... | 6.925956 |
module audioqsys_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.666974 |
module audioqsys_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 6.666974 |
module audioqsys_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [3... | 6.666974 |
module audioqsys_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
inpu... | 6.666974 |
module audioqsys_nios2_gen2_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 6.617016 |
module audioqsys_nios2_gen2_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [27:0] cp... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switc... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or ... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty ... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
outp... | 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_performance_monitors;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take... | 6.617016 |
module audioqsys_nios2_gen2_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input r... | 6.617016 |
module audioqsys_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audioqsys_onchip_memory2.hex";
output [31:0] readdata;
input [14:0] address;
... | 6.81412 |
module audioqsys_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [61:0] rd_data;
input clk;
input... | 6.705995 |
module AudioRam_controller (
input iReset,
input iStartLoad,
input iWriteClock,
input [ BITS-1:0] iSample,
input iReadClock,
input [LBITS-1:0] iReadAddr,
input iWindow,
output [ BITS-1:0] o... | 6.802602 |
module audiosystem (
input wire i_rstn,
input wire i_mck,
input wire i_bck,
input wire i_ws,
input wire i_sdi,
output wire o_sdo_l,
output wire o_sdo_r,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_b0,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_b1,
input wire signed [`c_COEF... | 7.268402 |
module, and an incredibly crude one
// Operates at the baseline clock frequency, TX only
// ////////////////////////////////////////////////////////
module audioUART
( input wire i_clk,
input wire i_rst,
input wire [7:0] i_data,
input wire i_valid,
output wire o_ready,
output wire o_serial
);
//10 possib... | 7.482665 |
module
// Needs to check:
// That data will be written correctly
// That continuous streaming (`assign o_ready = i_valid`) is fine
// That the module can be stalled for a time.
// ////////////////////////////////////////////////////////////////
`timescale 100ns/1ns
module audioUART_tb;
//Module constants and IO
re... | 6.537105 |
module AUDIOVOLUME #(
parameter BIT = 24,
parameter VOL_BIT = 8
) (
CLK,
in_L,
in_R,
out_L,
out_R,
Volume
);
input signed [BIT-1:0] in_L, in_R;
input [VOL_BIT-1:0] Volume;
input CLK;
output signed [BIT-1:0] out_L, out_R;
wire signed [BIT-1:0] out_L, out_R;
reg signed [BIT+... | 7.109332 |
module Audio_0 (
// inputs:
iCLK_18_4,
iDATA,
iRST_N,
iWR,
iWR_CLK,
// outputs:
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
oDATA
);
output oAUD_BCK;
output oAUD_DATA;
output oAUD_LRCK;
output oAUD_XCK;
output [15:0] oDATA;
input iCLK_18_4;
input [15:0] iDAT... | 7.160131 |
module AUDIO_ADC (
// host
clk,
reset,
read,
readdata,
//available,
empty,
clear,
// dac
bclk,
adclrc,
adcdat
);
/*****************************************************************************
* Parameter Declarations ... | 7.501448 |
module AUDIO_DAC_ADC (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_inL,
oAUD_inR,
iAUD_ADCDAT,
iAUD_extR,
iAUD_extL,
// Control Signals
iCLK_18_4,
iRST_N
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 32000; // 32 KHz
parameter DATA_WIDTH = 16;... | 7.83142 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps... | 7.702374 |
module converts serial MIC input into a 12-bit parallel register [11:0]sample.
//
// The audio input is sampled by PmodMIC3, the sampling rate of which is assigned to Pin 1 ChipSelect (cs).
// The Analog-to-Digital Concertor (ADC) on PmodMIC3 converts the audio analog signal into a 16-bit digital form
// ... | 7.210574 |
module audio_clk (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
audio_clk_0002 audio_clk_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
... | 6.73134 |
module ROM (
clk,
addr,
data
);
parameter ADDR_W = 8;
parameter DATA_W = 24;
parameter ROM_DATA = "undef";
input clk;
input [ADDR_W-1:0] addr;
output reg [DATA_W-1:0] data;
reg [DATA_W-1:0] rom[0:2**ADDR_W-1];
initial $readmemh(ROM_DATA, rom);
always @(posedge clk) data <= rom[addr];
end... | 7.434902 |
module Audio_Config (
CLOCK,
I2C_SCLK,
I2C_SDAT
);
input CLOCK;
inout I2C_SDAT;
output I2C_SCLK;
wire CLOCK;
wire PRE_CLOCK;
wire START_TX;
wire TX_DONE;
wire ACK;
wire [23:0] DATA;
parameter prescale = 2500;
// Audio Config Data
// I based the choice of configuration optio... | 8.413577 |
module audio_converter (
// Audio side
input AUD_BCK, // Audio bit clock
input AUD_LRCK, // left-right clock
input AUD_ADCDAT,
output AUD_DATA,
// Controller side
input iRST_N, // reset
input [15:0] AUD_outL,
input [15:0] AUD_outR,
output reg [15:0] AUD_inL,
output reg [15... | 6.875774 |
module AUDIO_DAC (
// host
clk,
reset,
write,
writedata,
full,
clear,
// dac
bclk,
daclrc,
dacdat
);
/*****************************************************************************
* Parameter Declarations *
*************... | 7.505814 |
module
// add audio I/O from top-level module
// modifed by Bruce Land, Cornell University 2007
/////////////////////////////////////////////////////////////////////////
module AUDIO_DAC_ADC (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_inL,
oAUD_inR,
iAUD_ADCDAT,
iAUD_extR,
iAUD_ex... | 7.896826 |
module AUDIO_DAC_FIFO ( // FIFO Side
iDATA,
iWR,
iWR_CLK,
oDATA,
// Audio Side
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
// Control Signals
iCLK_18_4,
iRST_N
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_... | 7.848626 |
module audio_driver (
clk,
rst_n,
snd_sel,
audio_o
);
input clk;
input rst_n;
input wire [1:0] snd_sel;
output reg audio_o;
reg [14:0] timer_1ms;
reg msec;
reg [ 3:0] cycle_cnt;
reg [3:0] t1, t2, t3, t4;
reg [3:0] on_time, off_time;
always @(posedge clk) begin
if (!rst... | 7.033101 |
module audio_echo_effect #(
parameter audio_width = 16,
delay_samples = 1024
) (
input wire reset,
input wire clk,
input wire i_valid,
output wire i_ready,
input wire i_is_left,
input wire [audio_width-1:0] i_audio,
output wire o_valid,
input wire o_ready,
output wire o_is_le... | 8.977306 |
module audio_echo_effect_top (
input wire sclk,
input wire lrclk,
input wire sdin,
input wire clk256,
input wire nreset,
output wire spdif
);
localparam audio_width = 16;
localparam delay_samples = 4096;
GSR GST_INST (.GSR_N(nreset));
wire reset = !nreset;
wire clk;
OSCA #(
... | 8.977306 |
module audio_echo_processor_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 1; // 44.1KHz * 32
localparam audio_width = 16;
initial begin
$dumpfile("audio_echo_processor_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
... | 6.780136 |
module audio_equalizer (
CLOCK_50,
KEY,
I2C_SCLK,
I2C_SDAT,
AUD_XCK,
AUD_DACLRCK,
AUD_ADCLRCK,
AUD_BCLK,
AUD_ADCDAT,
AUD_DACDAT
);
input CLOCK_50;
input KEY;
// I2C Audio/Video config interface
output I2C_SCLK;
inout I2C_SDAT;
// Audio CODEC
output AUD_XCK;
input... | 7.622664 |
module int2fp (
fp_out,
int_in,
scale_in
);
input signed [9:0] int_in;
input signed [7:0] scale_in;
output wire [17:0] fp_out;
wire [9:0] abs_int;
reg sign;
reg [8:0] mout; // mantissa
reg [7:0] eout; // exponent
reg [7:0] num_zeros; // count leading zeros in input integer
// get abso... | 7.895551 |
module fp2int (
int_out,
fp_in,
scale_in
);
output signed [9:0] int_out;
input signed [7:0] scale_in;
input wire [17:0] fp_in;
wire [9:0] abs_int;
wire sign;
wire [8:0] m_in; // mantissa
wire [7:0] e_in; // exponent
//reg [7:0] num_zeros ; // count leading zeros in input integer
assig... | 7.886289 |
module HexDigit (
segs,
num
);
input [3:0] num; //the hex digit to be displayed
output [6:0] segs; //actual LED segments
reg [6:0] segs;
always @(num) begin
case (num)
4'h0: segs = 7'b1000000;
4'h1: segs = 7'b1111001;
4'h2: segs = 7'b0100100;
4'h3: segs = 7'b0110000;
... | 7.890881 |
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