code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module attiny11 (
input clk,
input rst,
inout [5:0] portb,
input T0
);
wire [5:0] io_addr;
wire [7:0] io_data;
wire io_read;
wire io_write;
wire rst_inv;
avr_cpu cpu (
.clk(clk),
.rst(~rst_inv),
.io_addr(io_addr),
.io_data(io_data),
.io_read(io_read),
.io_write(io_write)
);
avr_gpio #(
.IO_ADDR(22),
.PORT_WIDTH(6)
) portb_gpio (
.clk(clk),
.rst(~rst_inv),
.io_addr(io_addr),
.io_data(io_data),
.io_read(io_read),
.io_write(io_write),
.gpio(portb)
);
avr_timer #(
.IO_ADDR(50)
) timer0 (
.clk(clk),
.rst(~rst_inv),
.io_addr(io_addr),
.io_data(io_data),
.io_read(io_read),
.io_write(io_write),
.T0(T0)
);
`ifdef SIMULATION
assign rst_inv = ~rst;
`endif
`ifdef ICE40_SYNTHESIS
SB_IO #(
.PIN_TYPE(6'b000000),
.PULLUP (1'b1)
) rst_pin (
.PACKAGE_PIN(rst),
.D_IN_0(rst_inv),
.INPUT_CLK(clk)
);
`endif
endmodule
| 6.780749 |
module attosoc (
input clk,
output reg [7:0] led,
output uart_tx,
input uart_rx
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 8192;
parameter [31:0] STACKADDR = 32'h0000_0000 + (4 * MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h0000_0000; // start of memory
reg [31:0] ram[0:MEM_WORDS-1];
initial $readmemh("firmware.hex", ram);
reg [31:0] ram_rdata;
reg ram_ready;
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
always @(posedge clk) begin
ram_ready <= 1'b0;
if (mem_addr[31:24] == 8'h00 && mem_valid) begin
if (mem_wstrb[0]) ram[mem_addr[23:2]][7:0] <= mem_wdata[7:0];
if (mem_wstrb[1]) ram[mem_addr[23:2]][15:8] <= mem_wdata[15:8];
if (mem_wstrb[2]) ram[mem_addr[23:2]][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) ram[mem_addr[23:2]][31:24] <= mem_wdata[31:24];
ram_rdata <= ram[mem_addr[23:2]];
ram_ready <= 1'b1;
end
end
wire iomem_valid;
reg iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
always @(posedge clk) begin
iomem_ready <= 1'b0;
if (iomem_valid && iomem_wstrb[0] && mem_addr == 32'h02000000) begin
led <= iomem_wdata[7:0];
iomem_ready <= 1'b1;
end
end
assign mem_ready = (iomem_valid && iomem_ready) ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait) ||
ram_ready;
assign mem_rdata = simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do :
ram_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(1),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk),
.resetn (resetn),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
simpleuart simpleuart (
.clk (clk),
.resetn(resetn),
.ser_tx(uart_tx),
.ser_rx(uart_rx),
.reg_div_we(simpleuart_reg_div_sel ? mem_wstrb : 4'b0000),
.reg_div_di(mem_wdata),
.reg_div_do(simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
endmodule
| 6.579166 |
modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
| 7.300142 |
module attrib01_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.308584 |
module attrib02_bar (
clk,
rst,
inp,
out
);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
input wire rst;
input wire inp;
(* an_output_register = 1*)
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.659062 |
module attrib02_foo (
clk,
rst,
inp,
out
);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
attrib02_bar bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 7.371222 |
module attrib03_bar (
clk,
rst,
inp,
out
);
(* bus_width *)
parameter WIDTH = 2;
(* an_attribute_on_localparam = 55 *)
localparam INCREMENT = 5;
input wire clk;
input wire rst;
input wire [WIDTH-1:0] inp;
output reg [WIDTH-1:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp + INCREMENT;
endmodule
| 8.69639 |
module attrib03_foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp;
output wire [7:0] out;
attrib03_bar #(
.WIDTH(8)
) bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 7.081502 |
module attrib04_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
(* this_is_a_prescaler *)
reg [7:0] counter;
(* temp_wire *)
wire out_val;
always @(posedge clk) counter <= counter + 1;
assign out_val = inp ^ counter[4];
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= out_val;
endmodule
| 7.386468 |
module attrib04_foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output wire out;
attrib04_bar bar_instance (
clk,
rst,
inp,
out
);
endmodule
| 6.666588 |
module foo (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (
(* clock_connected *)
clk,
rst, (* this_is_the_input *)
inp,
out
);
endmodule
| 7.455869 |
module attrib06_bar (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp_a + (* ripple_adder *) inp_b;
endmodule
| 7.848172 |
module attrib06_foo (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
attrib06_bar bar_instance (
clk,
rst,
inp_a,
inp_b,
out
);
endmodule
| 6.74449 |
module foo (
clk,
rst,
inp_a,
inp_b,
out
);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
endmodule
| 7.455869 |
module attrib08_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
| 7.442618 |
module attrib09_bar (
clk,
rst,
inp,
out
);
input wire clk;
input wire rst;
input wire [1:0] inp;
output reg [1:0] out;
always @(inp)
(* full_case, parallel_case *) case (inp)
2'd0: out <= 2'd3;
2'd1: out <= 2'd2;
2'd2: out <= 2'd1;
2'd3: out <= 2'd0;
endcase
endmodule
| 6.969608 |
module block_ram #(
parameter DATA_WIDTH = 4,
ADDRESS_WIDTH = 10
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory[0:DEPTH];
always @(posedge clk) begin
if (write_enable) memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule
| 7.663566 |
module distributed_ram #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory[0:DEPTH];
always @(posedge clk) begin
if (write_enable) memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule
| 7.433368 |
module distributed_ram_manual #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
(* ram_style = "block" *) reg [WORD:0] memory[0:DEPTH];
always @(posedge clk) begin
if (write_enable) memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule
| 7.433368 |
module distributed_ram_manual_syn #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
) (
input wire write_enable,
clk,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
(* synthesis, ram_block *) reg [WORD:0] memory[0:DEPTH];
always @(posedge clk) begin
if (write_enable) memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule
| 7.433368 |
module attr_rom (
input [9:0] addr,
output [7:0] data_out
);
reg [7:0] store[0:1023] /* verilator public_flat */;
initial begin
$readmemh("attr.mem", store);
end
assign data_out = store[addr];
endmodule
| 7.974822 |
module attr_set (
output [1:0] out
);
assign out = 2'd2;
endmodule
| 7.106979 |
module aTx (
clk,
rst,
iStart,
iDataIn,
iNtxB,
oByteCnt,
oTx,
oStop
);
//-----PARAMETERS------------------------
parameter FCLK = 10000; // [kHz] System clock frequency, max freq = 50000 kHz
parameter BRATE = 115200; // [baud] Baudrate, min brate = 9600 baud
parameter STOP_HOLD_TIME = 50; // [us] Stop signal hold time
parameter BUF_WIDTH = 8; // Buffer size Width, Size = 2**BUF_WIDTH
// parameter [BUF_WIDTH:0] iNtxB = 256; // Byte quantity
parameter CRC_ENA = 1; // Enable crc calculation
parameter CRC_POLY = 16'hA001; // Modbus standart crc polynom
//-----I/O-------------------------------
input clk;
input rst;
input iStart;
input [7:0] iDataIn;
input [BUF_WIDTH:0] iNtxB;
output reg [BUF_WIDTH-1:0] oByteCnt = 0;
output reg oTx = 1;
output reg oStop = 0;
//-----VARIABLES-------------------------
reg [ 2:0] state = 0;
reg [ 2:0] next_state = 0;
reg [ 7:0] Tx_data = 0;
reg [23:0] brateCnt = 0;
reg [ 3:0] bitCnt = 0;
reg [15:0] crc = 0;
reg [ 2:0] crcFlag = 0;
always @(posedge rst or posedge clk) begin
if (rst) begin
state <= 0;
end else begin
if (iNtxB == 0) state <= 0;
else state <= next_state;
end
end
always @(*) begin
case (state)
0: begin
if (iStart) next_state = 1;
else next_state = 0;
end
1: begin
next_state = 2;
end
2: begin
if (brateCnt >= (FCLK * 1000 / BRATE) - 1) next_state = 3;
else next_state = 2;
end
3: begin
next_state = 4;
end
4: begin
if (bitCnt >= 9) next_state = 5;
else next_state = 2;
end
5: begin
if (brateCnt >= (FCLK * 1000 / BRATE) - 1) next_state = 6;
else next_state = 5;
end
6: begin
if ((!CRC_ENA && crcFlag[0]) || (CRC_ENA && crcFlag[2])) next_state = 7;
else next_state = 1;
end
7: begin
if (brateCnt > (FCLK * STOP_HOLD_TIME / 1000)) next_state = 0;
else next_state = 7;
end
default: next_state = 0;
endcase
end
always @(negedge clk) begin
case (state)
0: // Reset
begin
oTx <= 1'b1;
brateCnt <= 0;
bitCnt <= 0;
oByteCnt <= 0;
Tx_data <= 0;
oStop <= 0;
if (CRC_ENA) crc <= 16'hFFFF;
crcFlag <= 0;
end
1: begin
oTx <= 0;
if (CRC_ENA) begin
if (crcFlag[1]) begin
Tx_data <= crc[15:8];
end else if (crcFlag[0]) begin
Tx_data <= crc[7:0];
end else begin
Tx_data <= iDataIn;
crc <= crc ^ {8'b0, iDataIn};
end
end else begin
Tx_data <= iDataIn;
end
end
2: begin
brateCnt <= brateCnt + 1'b1;
end
3: begin
brateCnt <= 0;
oTx <= Tx_data[0];
end
4: begin
Tx_data[7] <= 1'b1;
Tx_data[6:0] <= Tx_data[7:1];
bitCnt <= bitCnt + 1'b1;
if (CRC_ENA && (bitCnt > 0) && !crcFlag[0])
crc <= crc[0] ? {1'b0, crc[15:1]} ^ CRC_POLY : {1'b0, crc[15:1]};
end
5: begin
bitCnt <= 0;
oTx <= 1;
brateCnt <= brateCnt + 1'b1;
end
6: begin
brateCnt <= 0;
if (oByteCnt < iNtxB - 1) begin
oByteCnt <= oByteCnt + 1'b1;
end else begin
crcFlag[0] <= 1'b1;
crcFlag[2:1] <= crcFlag[1:0];
end
end
7: begin
brateCnt <= brateCnt + 1'b1;
oStop <= 1;
end
endcase
end
endmodule
| 7.865136 |
module auction #(
parameter N = 2,
W = 2
) ( //b = W, n = 2^N
input [(2**N)*W-1:0] bid,
output [N-1:0] winner,
output [W-1:0] winning_bid
);
genvar i;
wire [W-1:0] B[2**N-1:0];
generate
for (i = 0; i < 2 ** N; i = i + 1) begin
assign B[i] = bid[(i+1)*W-1:i*W];
end
endgenerate
genvar j, k;
wire [W-1:0] WV[N:0][2**N-1:0];
wire [2**(N-1)-1:0] WID[N-1:0];
generate
for (k = 0; k < 2 ** N; k = k + 1) begin
assign WV[0][k] = B[k];
end
endgenerate
generate
for (j = 0; j < N; j = j + 1) begin : col
for (k = 0; k < 2 ** (N - 1 - j); k = k + 1) begin : row
COMP #(
.N(W)
) COMP_ (
.A(WV[j][2*k+1]),
.B(WV[j][2*k]),
.O(WID[j][k])
);
MUX #(
.N(W)
) MUX_ (
.A(WV[j][2*k]),
.B(WV[j][2*k+1]),
.S(WID[j][k]),
.O(WV[j+1][k])
);
end
end
endgenerate
assign winning_bid = WV[N][0];
assign winner[N-1] = WID[N-1][0];
generate
for (j = N - 2; j >= 0; j = j - 1) begin : mux_
mod_mux #(
.N(N - j - 1)
) mod_mux_ (
.A(WID[j][(2**(N-j-1))-1:0]),
.S(winner[N-1:j+1]),
.O(winner[j])
);
end
endgenerate
endmodule
| 7.385357 |
module auction_BMR //b = W, n = 2^N
#(
parameter N = 2,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.07434 |
module auction_BMR_2_16 #(
parameter N = 2,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.954014 |
module auction_BMR_2_32 #(
parameter N = 2,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.954014 |
module auction_BMR_3_16 #(
parameter N = 3,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.969339 |
module auction_BMR_3_32 #(
parameter N = 3,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.969339 |
module auction_BMR_4_16 #(
parameter N = 4,
parameter W = 16
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.989207 |
module auction_BMR_4_32 #(
parameter N = 4,
parameter W = 32
) (
input [(2**N)*W-1:0] p_input,
output [N+W-1:0] o
);
auction #(
.N(N),
.W(W)
) auction_ (
.bid(p_input),
.winning_bid(o[N+W-1:N]),
.winner(o[N-1:0])
);
endmodule
| 7.989207 |
module auction_tb;
parameter N = 3, W = 3;
wire [(2**N)*W-1:0] bid;
wire [N-1:0] winner;
wire [W-1:0] winning_bid;
reg [W-1:0] B[2**N-1:0];
genvar i;
generate
for (i = 0; i < 2 ** N; i = i + 1) assign bid[(i+1)*W-1:i*W] = B[i];
endgenerate
reg clk;
always #5 clk = ~clk;
initial begin
clk = 0;
B[0] = 6; //1
B[1] = 0; //7
B[2] = 1; //6
B[3] = 4; //3
B[4] = 7; //4
B[5] = 3; //0
B[6] = 5; //2
B[7] = 2; //5
#20 B[0] = 7; //1
B[1] = 0; //7
B[2] = 1; //6
B[3] = 4; //3
B[4] = 6; //4
B[5] = 3; //0
B[6] = 5; //2
B[7] = 2; //5
#20 B[0] = 6; //1
B[1] = 0; //7
B[2] = 1; //6
B[3] = 7; //3
B[4] = 4; //4
B[5] = 3; //0
B[6] = 5; //2
B[7] = 2; //5
#20 B[0] = 6; //1
B[1] = 0; //7
B[2] = 1; //6
B[3] = 4; //3
B[4] = 5; //4
B[5] = 3; //0
B[6] = 5; //2
B[7] = 7; //5
#20 B[0] = 6; //1
B[1] = 7; //7
B[2] = 1; //6
B[3] = 4; //3
B[4] = 7; //4
B[5] = 3; //0
B[6] = 5; //2
B[7] = 2; //5
#20 $stop;
end
auction #(
.N(N),
.W(W)
) dut (
.bid(bid),
.winner(winner),
.winning_bid(winning_bid)
);
endmodule
| 6.72648 |
module aud (
aud_data,
aud_lrck,
aud_bck,
rst,
smpl,
clk
);
output aud_data;
output reg aud_lrck;
output reg aud_bck;
input rst;
input [15:0] smpl;
input clk;
parameter REF_CLK = 18_432_000; /* 18.432MHz */
parameter SMPL_RATE = 48000;
parameter SMPL_SIZE = 16;
parameter CHANS = 2;
reg [7:0] lrck_cnt;
reg [2:0] bck_cnt;
reg [3:0] smpl_bit;
always @(posedge clk or posedge rst) begin
if (rst) begin
lrck_cnt <= 0;
aud_lrck <= 0;
end else begin
lrck_cnt = lrck_cnt + 1;
if (lrck_cnt == REF_CLK / (SMPL_RATE * 2)) begin
lrck_cnt <= 0;
aud_lrck <= ~aud_lrck;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
bck_cnt <= 0;
aud_bck <= 0;
end else begin
bck_cnt = bck_cnt + 1;
if (bck_cnt == REF_CLK / (SMPL_RATE * SMPL_SIZE * CHANS * 2)) begin
bck_cnt <= 0;
aud_bck <= ~aud_bck;
end
end
end
always @(negedge aud_bck or posedge rst) begin
if (rst) begin
smpl_bit <= 0;
end else begin
smpl_bit <= smpl_bit + 1;
end
end
assign aud_data = smpl[~smpl_bit];
endmodule
| 6.762015 |
module audio3 (
// Clock Input (50 MHz)
input CLOCK_50, // 50 MHz
input CLOCK_27, // 27 MHz
// Push Buttons
input [1:0] KEY,
// TV Decoder
output TD_RESET, // TV Decoder Reset
// I2C
inout I2C_SDAT, // I2C Data
output I2C_SCLK, // I2C Clock
// Audio CODEC
output/*inout*/ AUD_ADCLRCK, // Audio CODEC ADC LR Clock
input AUD_ADCDAT, // Audio CODEC ADC Data
output /*inout*/ AUD_DACLRCK, // Audio CODEC DAC LR Clock
output AUD_DACDAT, // Audio CODEC DAC Data
inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
output AUD_XCK, // Audio CODEC Chip Clock
// GPIO Connections
inout [35:0] GPIO_0,
GPIO_1,
input play
);
// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire [6:0] myclock;
wire RST;
//assign RST = KEY[1];
assign RST = ~play;
// reset delay gives some time for peripherals to initialize
wire DLY_RST;
Reset_Delay r0 (
.iCLK (CLOCK_50),
.oRESET(DLY_RST)
);
assign TD_RESET = 1'b1; // Enable 27 MHz
VGA_Audio_PLL p1 (
.areset(~DLY_RST),
.inclk0(CLOCK_27),
.c0(VGA_CTRL_CLK),
.c1(AUD_CTRL_CLK),
.c2(VGA_CLK)
);
I2C_AV_Config u3 (
// Host Side
.iCLK(CLOCK_50),
//.iRST_N(KEY[1]),
.iRST_N(~play),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT)
);
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
audio_clock u4 (
// Audio Side
.oAUD_BCK(AUD_BCLK),
.oAUD_LRCK(AUD_DACLRCK),
// Control Signals
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY_RST)
);
audio_converter u5 (
// Audio side
.AUD_BCK (AUD_BCLK), // Audio bit clock
.AUD_LRCK (AUD_DACLRCK), // left-right clock
.AUD_ADCDAT(AUD_ADCDAT),
.AUD_DATA (AUD_DACDAT),
// Controller side
.iRST_N (DLY_RST), // reset
.AUD_outL (audio_outL),
.AUD_outR (audio_outR),
.AUD_inL (audio_inL),
.AUD_inR (audio_inR)
);
wire [15:0] audio_inL, audio_inR;
wire [15:0] audio_outL, audio_outR;
wire [15:0] signal;
//set up DDS frequency
//Use switches to set freq
wire [31:0] dds_incr;
wire [31:0] freq = 830.61;
assign dds_incr = freq * 91626; //91626 = 2^32/46875 so SW is in Hz
reg [31:0] dds_phase;
always @(negedge AUD_DACLRCK or negedge DLY_RST)
if (!DLY_RST) dds_phase <= 0;
else dds_phase <= dds_phase + dds_incr;
wire [7:0] index = dds_phase[31:24];
sine_table sig1 (
.index (index),
.signal(audio_outR)
);
//audio_outR <= audio_inR;
//always @(posedge AUD_DACLRCK)
assign audio_outL = 15'h0000;
endmodule
| 8.672979 |
module AudioADC (
input clk, //50Mhz
input rst, //reset
input AUD_BCLK, //Audio chip clock
input AUD_ADCLRCK, //Will go high when ready for data.
input AUD_ADCDAT, //The data to receive on each pulse
output reg done, //Pulses high on done
output reg [31:0] data //The full data we want to send.
);
initial data = 32'd0;
parameter START = 4'd0, WAIT = 4'd1, BITS = 4'd2, DONE = 4'd3, BAD = 4'd4;
reg [3:0] s;
reg [3:0] ns;
//The current bit we're receiving
reg [4:0] countADCBits;
initial countADCBits = 5'd31;
reg [31:0] tempData;
always @(posedge AUD_BCLK or negedge rst) begin
if (rst == 0) begin
s <= START;
countADCBits <= 5'd31;
end else begin
s <= ns;
case (s)
BITS: begin
countADCBits <= countADCBits - 5'd1;
tempData[countADCBits] <= AUD_ADCDAT;
end
DONE: begin
countADCBits <= 5'd31;
data <= tempData;
end
endcase
end
end
always @(*) begin
done = 1'b0;
case (s)
START: begin
ns = WAIT;
end
WAIT: begin
ns = WAIT;
if (AUD_ADCLRCK == 1) ns = BITS;
end
BITS: begin
ns = BITS;
//data[countADCBits] = AUD_ADCDAT;
if (countADCBits == 0) ns = DONE;
end
DONE: begin
//This will pulse done high for one cycle.
done = 1'b1;
ns = WAIT;
end
BAD: begin
ns = BAD;
end
default: begin
ns = BAD;
end
endcase
end
endmodule
| 7.189319 |
module for the 44.1 kHz clock project from section 4.4.3
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AudioClockTop(
input clk,
output [7:0] JB
);
AudioClock MyAudioClock (.clk (clk),
.audio_clk (JB[0])
);
endmodule
| 7.518202 |
module AudioCodec (
input wire [15:0] to_dac_left_channel_data, // avalon_left_channel_sink.data
input wire to_dac_left_channel_valid, // .valid
output wire to_dac_left_channel_ready, // .ready
input wire from_adc_left_channel_ready, // avalon_left_channel_source.ready
output wire [15:0] from_adc_left_channel_data, // .data
output wire from_adc_left_channel_valid, // .valid
input wire [15:0] to_dac_right_channel_data, // avalon_right_channel_sink.data
input wire to_dac_right_channel_valid, // .valid
output wire to_dac_right_channel_ready, // .ready
input wire from_adc_right_channel_ready, // avalon_right_channel_source.ready
output wire [15:0] from_adc_right_channel_data, // .data
output wire from_adc_right_channel_valid, // .valid
input wire clk, // clk.clk
input wire AUD_ADCDAT, // external_interface.ADCDAT
input wire AUD_ADCLRCK, // .ADCLRCK
input wire AUD_BCLK, // .BCLK
output wire AUD_DACDAT, // .DACDAT
input wire AUD_DACLRCK, // .DACLRCK
input wire reset // reset.reset
);
AudioCodec_audio_0 audio_0 (
.clk(clk), // clk.clk
.reset(reset), // reset.reset
.from_adc_left_channel_ready (from_adc_left_channel_ready), // avalon_left_channel_source.ready
.from_adc_left_channel_data(from_adc_left_channel_data), // .data
.from_adc_left_channel_valid (from_adc_left_channel_valid), // .valid
.from_adc_right_channel_ready (from_adc_right_channel_ready), // avalon_right_channel_source.ready
.from_adc_right_channel_data (from_adc_right_channel_data), // .data
.from_adc_right_channel_valid (from_adc_right_channel_valid), // .valid
.to_dac_left_channel_data(to_dac_left_channel_data), // avalon_left_channel_sink.data
.to_dac_left_channel_valid(to_dac_left_channel_valid), // .valid
.to_dac_left_channel_ready(to_dac_left_channel_ready), // .ready
.to_dac_right_channel_data(to_dac_right_channel_data), // avalon_right_channel_sink.data
.to_dac_right_channel_valid(to_dac_right_channel_valid), // .valid
.to_dac_right_channel_ready(to_dac_right_channel_ready), // .ready
.AUD_ADCDAT(AUD_ADCDAT), // external_interface.export
.AUD_ADCLRCK(AUD_ADCLRCK), // .export
.AUD_BCLK(AUD_BCLK), // .export
.AUD_DACDAT(AUD_DACDAT), // .export
.AUD_DACLRCK(AUD_DACLRCK) // .export
);
endmodule
| 7.02599 |
module AudioCodec (
to_dac_left_channel_data,
to_dac_left_channel_valid,
to_dac_left_channel_ready,
from_adc_left_channel_ready,
from_adc_left_channel_data,
from_adc_left_channel_valid,
to_dac_right_channel_data,
to_dac_right_channel_valid,
to_dac_right_channel_ready,
from_adc_right_channel_ready,
from_adc_right_channel_data,
from_adc_right_channel_valid,
clk,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
reset
);
input [15:0] to_dac_left_channel_data;
input to_dac_left_channel_valid;
output to_dac_left_channel_ready;
input from_adc_left_channel_ready;
output [15:0] from_adc_left_channel_data;
output from_adc_left_channel_valid;
input [15:0] to_dac_right_channel_data;
input to_dac_right_channel_valid;
output to_dac_right_channel_ready;
input from_adc_right_channel_ready;
output [15:0] from_adc_right_channel_data;
output from_adc_right_channel_valid;
input clk;
input AUD_ADCDAT;
input AUD_ADCLRCK;
input AUD_BCLK;
output AUD_DACDAT;
input AUD_DACLRCK;
input reset;
endmodule
| 7.02599 |
module AudioDAC (
input clk, //50Mhz
input rst, //reset
input AUD_BCLK, //Audio chip clock
input AUD_DACLRCK, //Will go high when ready for data.
input [31:0] data, //The full data we want to send.
output reg done, //Pulses high on done
output reg AUD_DACDAT //The data to send out on each pulse.
);
parameter START = 4'd0, WAIT = 4'd1, BITS = 4'd2, DONE = 4'd3, BAD = 4'd4;
reg [3:0] s;
reg [3:0] ns;
//For sending audio
reg [4:0] countDACBits;
initial countDACBits = 5'd31;
reg [31:0] dataCopy;
always @(posedge AUD_BCLK or negedge rst) begin
if (rst == 0) begin
s <= START;
countDACBits <= 5'd31;
end else begin
s <= ns;
case (s)
WAIT: begin
if (AUD_DACLRCK == 1) dataCopy <= data;
end
BITS: begin
countDACBits <= countDACBits - 5'd1;
end
DONE: begin
countDACBits <= 5'd31;
end
endcase
end
end
always @(*) begin
done = 1'b0;
case (s)
START: begin
ns = WAIT;
end
WAIT: begin
ns = WAIT;
if (AUD_DACLRCK == 1) ns = BITS;
end
BITS: begin
ns = BITS;
if (countDACBits == 0) ns = DONE;
end
DONE: begin
done = 1'b1;
ns = WAIT;
end
BAD: begin
ns = BAD;
end
default: begin
ns = BAD;
end
endcase
end
always @(*) begin
AUD_DACDAT = dataCopy[countDACBits];
end
endmodule
| 7.144818 |
module audiodac_dsmod #(
parameter BW = 16
) (
input [BW-1:0] data_i,
output wire data_rd_o,
output reg ds_o,
output wire ds_n_o,
input rst_n_i,
input clk_i,
input mode_i,
input [3:0] scale_i, // 0 = off, 15 = max scale
input [1:0] osr_i // 0 = 32; 1 = 64, 2 = 128, 3 = 256
);
reg [BW-1:0] accu1;
reg [BW-1:0] accu2;
reg [1:0] accu3;
wire [BW-1:0] data_scaled; // input data treated with scaling
wire signed [BW-1:0] data_calc; // 1b more is needed here
reg [7:0] fetch_ctr; // clock divideid by osr
reg [1:0] mod2_ctr; // clk divide by 4 for 1st stage of 2nd order mod
reg [1:0] mod2_out; // output 1st stage
localparam [7:0] CTR_OSR_32 = 8'd31;
localparam [7:0] CTR_OSR_64 = 8'd63;
localparam [7:0] CTR_OSR_128 = 8'd127;
localparam [7:0] CTR_OSR_256 = 8'd255;
localparam [1:0] OSR_32 = 2'd0;
localparam [1:0] OSR_64 = 2'd1;
localparam [1:0] OSR_128 = 2'd2;
localparam [1:0] OSR_256 = 2'd3;
localparam MODE_ORD1 = 1'd0;
localparam MODE_ORD2 = 1'd1;
localparam [3:0] SCALE_OFF = 4'd15;
localparam [3:0] SCALE_MAX = 4'd0;
localparam [BW-1:0] DATA_MID = {1'b1, {(BW - 1) {1'b0}}};
// provide out and out_n
assign ds_n_o = ~ds_o;
// we provide scaling in 6dB steps, 0=min (off), 15=max (unchanged)
// scaling is a bit tricky as we have UINT coming in, so we do the scaling in signed INT
// so that we stay around the midscale at 0x8000 when the amplitude is reduced
assign data_calc = (($signed(data_i) - $signed(DATA_MID)) >>> scale_i) + $signed(DATA_MID);
assign data_scaled = (scale_i == SCALE_OFF) ? DATA_MID :
(scale_i == SCALE_MAX) ? data_i :
$unsigned(
data_calc[BW-1:0]
);
// the fetch counter controls the read of the next sample from the FIFO
// the counter runs down so decoding is easier for different counter
// cycles (reloads at 0)
assign data_rd_o = (fetch_ctr == 8'd0);
always @(posedge clk_i) begin
if (!rst_n_i) begin
// reset all registers
accu1 <= {BW{1'b0}};
accu2 <= {BW{1'b0}};
accu3 <= 2'b0;
ds_o <= 1'b0;
fetch_ctr <= 8'b0;
mod2_ctr <= 2'b0;
mod2_out <= 2'b0;
end else begin
// sd-modulator is running
if (fetch_ctr == 8'd0) begin
// fetch_ctr finished, restart with proper cycle count
// depending on osr
case (osr_i)
OSR_32: fetch_ctr <= CTR_OSR_32;
OSR_64: fetch_ctr <= CTR_OSR_64;
OSR_128: fetch_ctr <= CTR_OSR_128;
OSR_256: fetch_ctr <= CTR_OSR_256;
default: fetch_ctr <= 8'bx;
endcase
end else
//just keep counting down
fetch_ctr <= fetch_ctr - 1'b1;
if (mode_i == MODE_ORD1) begin
// delta-sigma modulator 1st order
// this simple structure works if everything
// is UINT
{ds_o, accu1} <= data_scaled + accu1;
end else if (mode_i == MODE_ORD2) begin
// delta-sigma modulator 2nd order
// the first stage runs on clk/4, the second
// stage runs on clk
if (mod2_ctr == 2'b0) begin
// this only happens every 4th clk
// cycle
{mod2_out,accu1} <= {2'b00,data_scaled}
+ {1'b0,accu1,1'b0}
+ {2'b01,{BW{1'b0}}}
- {2'b0,accu2};
accu2 <= accu1;
end
// this is the clk divider for the 1st stage
mod2_ctr <= mod2_ctr + 1'b1;
// this simple structure is the 2nd stage
// running on clk
{ds_o, accu3} <= mod2_out + accu3;
end
end
end
endmodule
| 7.522957 |
module audiodac_fifo #(
parameter WIDTH = 16,
FIFO_SIZE = 5,
FIFO_ASYNC = 1
) (
// 0=sync, 1=async write I/F
input [WIDTH-1:0] fifo_indata_i,
input fifo_indata_rdy_i,
// note that fifo_indata_i and fifo_indata_rdy_i could originate from
// an asynchronous clk domain, so potentially needs to be synchronized
// use FIFO_ASYNC=1 to select the proper behaviour
output reg fifo_indata_ack_o,
output wire fifo_full_o,
output wire fifo_empty_o,
output wire [WIDTH-1:0] fifo_outdata_o,
input fifo_outdata_rd_i,
input rst_n_i,
input clk_i,
input tst_fifo_loop_i
);
reg [FIFO_SIZE-1:0] read_ptr, write_ptr;
wire [FIFO_SIZE-1:0] next_write;
reg [WIDTH-1:0] fifo_store[0:(1<<FIFO_SIZE)-1];
// needed for asynch. I/F synchronization (2 stages)
reg fifo_rdy_del1, fifo_rdy_del2;
reg [WIDTH-1:0] fifo_data_del1, fifo_data_del2;
wire fifo_rdy;
wire [WIDTH-1:0] fifo_data;
assign fifo_full_o = (next_write == read_ptr);
assign fifo_empty_o = (write_ptr == read_ptr);
assign fifo_outdata_o = fifo_store[read_ptr];
assign next_write = write_ptr + 1'b1;
assign fifo_rdy = FIFO_ASYNC ? fifo_rdy_del2 : fifo_indata_rdy_i;
assign fifo_data = FIFO_ASYNC ? fifo_data_del2 : fifo_indata_i;
always @(posedge clk_i) begin
if (!rst_n_i) begin
// reset all registers
fifo_indata_ack_o <= 1'b0;
read_ptr <= {FIFO_SIZE{1'b0}};
write_ptr <= {FIFO_SIZE{1'b0}};
// only first FIFO input needs to be reset, we put in a midscale UINT
fifo_store[0] <= {1'b1, {(WIDTH - 1) {1'b0}}};
fifo_rdy_del1 <= 1'b0;
fifo_rdy_del2 <= 1'b0;
fifo_data_del1 <= {WIDTH{1'b0}};
fifo_data_del2 <= {WIDTH{1'b0}};
end else begin
// use two stages to sync-in fifo_indata_rdy_i
fifo_rdy_del2 <= fifo_rdy_del1;
fifo_rdy_del1 <= fifo_indata_rdy_i;
// use two stages to sync-in fifo_indata_i
fifo_data_del2 <= fifo_data_del1;
fifo_data_del1 <= fifo_indata_i;
// manage the FIFO read process, if fifo_outdata_rd_i is asserted
// the read pointer location is increased, as long as
// the FIFO is not empty. note that there is an inherent
// wrap-around due to truncation.
if (fifo_outdata_rd_i && (!fifo_empty_o || tst_fifo_loop_i)) read_ptr <= read_ptr + 1'b1;
// manage the FIFO write process. if fifo_rdy is
// asserted, and the FIFO is not full, the write
// pointer is increased and the datum is written into
// the FIFO. further the transfer is acknowledged
if (fifo_rdy && !fifo_indata_ack_o && !fifo_full_o) begin
write_ptr <= next_write;
fifo_store[next_write] <= fifo_data;
fifo_indata_ack_o <= 1'b1;
end
if (!fifo_rdy) fifo_indata_ack_o <= 1'b0;
end
end
endmodule
| 8.649418 |
module audiodac_python_tb;
localparam SIM_MODE = `SIM_MODE;
localparam SIM_OSR = `SIM_OSR;
localparam SIM_VOLUME = `SIM_VOLUME;
localparam DATA_SAMPLES = `SIM_DATA_SAMPLES;
// large memory to hold the audio
reg signed [15:0] DATA_IN [ 0:DATA_SAMPLES-1];
// output results written to file
reg DATA_OUT [0:(DATA_SAMPLES*(32*(2**SIM_OSR))-1)];
integer DATA_IN_CTR = 0;
integer DATA_OUT_CTR = 0;
// configuration bits
reg MODE = SIM_MODE;
reg [ 1:0] OSR = SIM_OSR;
reg [ 3:0] VOLUME = SIM_VOLUME;
// inputs
reg RESET_N = 1'b0;
reg CLK = 1'b0;
reg TST_FIFO_LOOP = 1'b0;
reg TST_SINEGEN_EN = 1'b0;
reg [ 4:0] TST_SINEGEN_STEP = 5'd2;
// outputs
wire FIFO_FULL, FIFO_EMPTY, FIFO_ACK, DS_OUT, DS_OUT_N;
// instantiate DUT
audiodac dac (
.fifo_i(DATA),
.fifo_rdy_i(DATA_RDY),
.fifo_ack_o(FIFO_ACK),
.fifo_full_o(FIFO_FULL),
.fifo_empty_o(FIFO_EMPTY),
.rst_n_i(RESET_N),
.clk_i(CLK),
.mode_i(MODE),
.volume_i(VOLUME),
.osr_i(OSR),
.ds_o(DS_OUT),
.ds_n_o(DS_OUT_N),
.tst_fifo_loop_i(TST_FIFO_LOOP),
.tst_sinegen_en_i(TST_SINEGEN_EN),
.tst_sinegen_step_i(TST_SINEGEN_STEP)
);
// make a clock
always #1 CLK = ~CLK;
// handle FIFO input data
reg signed [15:0] DATA = 16'b0;
reg DATA_RDY = 1'b0;
// flag to signal a wait for the next write burst
reg WAIT_FOR_EMPTY = 1'b0;
always @(negedge CLK) begin
// handling of simulation input and output data is done at falling CLK edge
// IP block is clocked by rising edge
// provide input data
if (!DATA_RDY && !FIFO_FULL && !FIFO_ACK && !WAIT_FOR_EMPTY && RESET_N) begin
DATA <= DATA_IN[DATA_IN_CTR];
DATA_IN_CTR = DATA_IN_CTR < DATA_SAMPLES ? DATA_IN_CTR + 1 : DATA_IN_CTR;
// signal to FIFO that data is ready
DATA_RDY <= 1'b1;
end
// no more input data left and fifo empty? write result and exit
if (DATA_IN_CTR == DATA_SAMPLES && FIFO_EMPTY) begin
$writememh("verilog_bin_out.txt", DATA_OUT);
$finish;
end
// de-assert data_rdy when data transfer ack'd by FIFO
if (FIFO_ACK) DATA_RDY <= 1'b0;
// The FIFO data write-in is done in a bursty nature, like a
// host system would likely do. When the FIFO is empty we write
// until the FIFO is full, then we wait for the FIFO to get
// empty again--then we do another bursty data transfer. This
// is meant to put less burden on the host system, so just an
// interrupt service routine is required, no constant polling
// of the data_rdy line, instead fifo_empty can trigger the ISR.
// stall data write-in when FIFO is already full
if (FIFO_FULL) WAIT_FOR_EMPTY <= 1'b1;
// if FIFO is empty re-engage with data write-in
if (FIFO_EMPTY) WAIT_FOR_EMPTY <= 1'b0;
// store simulation result into memory for later dump
if (RESET_N) begin
DATA_OUT[DATA_OUT_CTR] <= DS_OUT;
DATA_OUT_CTR = DATA_OUT_CTR + 1;
end
end
// here is all the initiliaztion work for the simulation
initial begin
// print out simulation state
$display("------------------------------");
$display("SIM MODE = ", SIM_MODE);
$display("SIM_OSR = ", SIM_OSR);
$display("SIM_VOLUME = ", SIM_VOLUME);
$display("------------------------------");
$readmemh("audiodac_test_data.txt", DATA_IN);
`ifndef SIM_NO_VCD
$dumpfile("audiodac_tb.vcd");
$dumpvars;
`endif
// de-assert reset
#5 RESET_N = 1'b1;
end
endmodule
| 7.959826 |
module audiodac_sinegen #(
parameter BW = 16,
parameter LUT_SIZE = 6,
parameter SINE_AMPL = 0.9
) (
output wire signed [BW-1:0] data_o,
input data_rd_i,
input rst_n_i,
input clk_i,
input tst_sinegen_en_i,
input [LUT_SIZE-2:0] tst_sinegen_step_i
);
/*
* Function to calculate a single sine-value.
* Input: Sine-angle in degrees (integer value)
* Output: Sine value (signed bitvector)
*/
function signed [BW-1:0] calc_sine_value;
input integer angle; //in degrees
/* verilator lint_off UNUSED */
integer temp;
/* verilator lint_on UNUSED */
begin
temp = $rtoi(SINE_AMPL * $itor(2 ** (BW - 1) - 1) * $sin($itor(angle) * 3.1415926 / 180.0));
calc_sine_value = temp[BW-1:0];
end
endfunction
/*
* Function to generate the LUT
*/
/* verilator lint_off LITENDIAN */
function [0:(BW*(2**LUT_SIZE)-1)] calc_sine_values;
/* verilator lint_off UNUSED */
input dummy; //dummy input, since a function needs at least one input
/* verilator lint_on UNUSED */
integer i;
begin
for (i = 0; i < 2 ** LUT_SIZE; i = i + 1)
calc_sine_values[i*BW+:BW] = calc_sine_value($rtoi(360.0 / $itor(2 ** LUT_SIZE) * $itor(i)));
end
endfunction
/* verilator lint_on LITENDIAN */
reg [LUT_SIZE-1:0] read_ptr, next_read_ptr; //pointer for the LUT
// Generate the LUT table as an flattend array
/* verilator lint_off LITENDIAN */
wire [0:(BW*(2**LUT_SIZE)-1)] SINE_CONST = calc_sine_values(0);
/* verilator lint_on LITENDIAN */
//Set the output data
assign data_o = tst_sinegen_en_i ? SINE_CONST[read_ptr*BW+:BW] : 0;
// Register process
always @(posedge clk_i) begin
if (!rst_n_i) begin
// reset all registers
read_ptr <= 0;
end else begin
read_ptr <= next_read_ptr;
end
end
// Combinatorial process
always @(*) begin
next_read_ptr = (tst_sinegen_en_i && data_rd_i) ?
(read_ptr + {1'b0,tst_sinegen_step_i}) :
read_ptr;
end
endmodule
| 6.74019 |
module audiodac_tb;
localparam SIM_MODE = 0;
localparam SIM_OSR = 2;
localparam SIM_VOLUME = 0;
// housekeeping for getting data in
`ifdef SIM_LONG
localparam DATA_SAMPLES = 44100 * 10;
`endif
`ifdef SIM_SHORT
localparam DATA_SAMPLES = 44100 * 1;
`endif
reg [15:0] DATA_IN[0:DATA_SAMPLES-1]; // large memory to hold the audio
reg DATA_OUT[0:(DATA_SAMPLES*(32*2^SIM_OSR)-1)]; // output results written to file
integer DATA_IN_CTR = 0;
integer DATA_OUT_CTR = 0;
// configuration bits
reg MODE = SIM_MODE;
reg [1:0] OSR = SIM_OSR;
reg [3:0] VOLUME = SIM_VOLUME;
// inputs
reg RESET_N = 1'b0;
reg CLK = 1'b0;
reg TST_FIFO_LOOP = 1'b0;
reg TST_SINEGEN_EN = 1'b0;
reg [4:0] TST_SINEGEN_STEP = 5'd2;
// outputs
wire FIFO_FULL, FIFO_EMPTY, FIFO_ACK, DS_OUT, DS_OUT_N;
// instantiate DUT
audiodac dac (
.fifo_i(DATA),
.fifo_rdy_i(DATA_RDY),
.fifo_ack_o(FIFO_ACK),
.fifo_full_o(FIFO_FULL),
.fifo_empty_o(FIFO_EMPTY),
.rst_n_i(RESET_N),
.clk_i(CLK),
.mode_i(MODE),
.volume_i(VOLUME),
.osr_i(OSR),
.ds_o(DS_OUT),
.ds_n_o(DS_OUT_N),
.tst_fifo_loop_i(TST_FIFO_LOOP),
.tst_sinegen_en_i(TST_SINEGEN_EN),
.tst_sinegen_step_i(TST_SINEGEN_STEP)
);
// make a clock
always #1 CLK = ~CLK;
// handle FIFO input data
reg [15:0] DATA = 16'b0;
reg DATA_RDY = 1'b0;
reg WAIT_FOR_EMPTY = 1'b0; // flag to signal a wait for the next write burst
always @(negedge CLK) begin
// provide input data
if (!DATA_RDY && !FIFO_FULL && !FIFO_ACK && !WAIT_FOR_EMPTY && RESET_N) begin
// option 1: just use a simple counter as data
//#1 DATA <= DATA + 1;
// option 2: use data from file
DATA <= DATA_IN[DATA_IN_CTR];
DATA_IN_CTR = DATA_IN_CTR + 1;
// signal to FIFO that data is ready
DATA_RDY <= 1'b1;
// no more input data left? write result and exit
if (DATA_IN_CTR == DATA_SAMPLES) begin
$writememh("verilog_bin_out.txt", DATA_OUT);
$finish;
end
end
// de-assert data_rdy when data transfer ack'd by FIFO
if (FIFO_ACK) DATA_RDY <= 1'b0;
// The FIFO data write-in is done in a bursty nature, like a
// host system would likely do. When the FIFO is empty we write
// until the FIFO is full, then we wait for the FIFO to get
// empty again--then we do another bursty data transfer. This
// is meant to put less burden on the host system, so just an
// interrupt service routine is required, no constant polling
// of the data_rdy line, instead fifo_empty can trigger the ISR.
// stall data write-in when FIFO is already full
if (FIFO_FULL) WAIT_FOR_EMPTY <= 1'b1;
// if FIFO is empty re-engage with data write-in
if (FIFO_EMPTY) WAIT_FOR_EMPTY <= 1'b0;
// store simulation result into memory for later dump
if (RESET_N) begin
DATA_OUT[DATA_OUT_CTR] <= DS_OUT;
DATA_OUT_CTR = DATA_OUT_CTR + 1;
end
end
// here is all the initiliaztion work for the simulation
initial begin
// print out simulation state
$display("------------------------------");
`ifdef SIM_SHORT
$display("Running short (1s) simulation.");
`elsif SIM_LONG
$display("Running long (10s) simulation.");
`endif
$display("------------------------------");
$display("SIM MODE = ", SIM_MODE);
$display("SIM_OSR = ", SIM_OSR);
$display("SIM_VOLUME = ", SIM_VOLUME);
$display("------------------------------");
// read in the testdata into the memory
`ifdef SIM_LONG
$readmemh("../../ver/verilog_testaudio_10s.txt", DATA_IN);
`elsif SIM_SHORT
$readmemh("../../ver/verilog_testaudio_1s.txt", DATA_IN);
`endif
// dump signals into VCD for debug
`ifdef SIM_SHORT
$dumpfile("audiodac_tb.vcd");
$dumpvars;
`endif
// de-assert reset
#5 RESET_N = 1'b1;
// provide an online output for tracking sim progress
//$monitor("At time %t, ds_out = %h", $time, DS_OUT);
end
endmodule
| 7.794899 |
module AudioInit (
input rst,
input clk,
input initPulse,
inout SDAT, //i2c data line
output SDCLK, //i2c clock out.
output reg doneInit, //Goes high when the module is done doing its thing
output [3:0] audioInitError,
input manualSend, //Pulse high to send i2c data manually.
input [6:0] manualRegister,
input [8:0] manualData,
output reg manualDone
);
parameter ADDRESS = 7'b0011010;
reg [6:0] REGISTERS[0:5];
reg [8:0] DATA[0:5];
reg [3:0] currentInit;
reg [2:0] initState;
//i2c interface
reg i2cEnable;
initial i2cEnable = 1'b0;
reg [6:0] i2cRegister;
reg [8:0] i2cData;
wire [3:0] i2cError;
wire i2cDone;
i2c myI2c (
.rst(i2cEnable),
.clk(clk),
.address(ADDRESS), //Same address every time: the sound chip.
.register(i2cRegister),
.data(i2cData),
.rw(1'b0), //We're always writing. Can't read from this device.
.error(i2cError), //This will output an error if something goes wrong.
.SDAT(SDAT), //This is the i2c data line.
.SDCLK(SDCLK),
.done(i2cDone) //Will go high when i2c is done.
);
always @(posedge clk or negedge rst) begin
if (rst == 0) begin
initState <= 0;
end else begin
case (initState)
3'd0: begin
DATA[0] <= 9'b0_000_1_0000; //Power *most* on.
DATA[1] <= 9'b0_0_1_0_1_00_11; //Audio format
DATA[2] <= 9'b0000_11_000; //DACSEL ON, BYPASS on.
DATA[3] <= 9'b0000_0_0_00_0; //DACMU[te] off
DATA[4] <= 9'b000000001; //Activate
DATA[5] <= 9'b0_000_0_0000; //Power all the way on.
REGISTERS[0] <= 7'b0000110; //Power Control
REGISTERS[1] <= 7'b0000111; //Digital Audio Interface (Audio format)
REGISTERS[2] <= 7'b0000100; //Analog Audio Path Control (BYPASS, DACSEL)
REGISTERS[3] <= 7'b0000101; //Digital Audio Path Control
REGISTERS[4] <= 7'b0001001; //Activate Control
REGISTERS[5] <= 7'b0000110; //Power Control
//Wait for the go signal.
if (initPulse) begin
initState <= initState + 1'b1;
end
end
3'd1: begin
i2cEnable <= 1;
i2cRegister <= REGISTERS[currentInit];
i2cData <= DATA[currentInit];
//Go to next state to wait
initState <= initState + 1'b1;
end
3'd2: begin
//Wait for completion
if (i2cDone) begin
initState <= initState + 1'b1;
end else begin
//Keep waiting
end
end
3'd3: begin
//Disable i2c.
i2cEnable <= 1'b0;
//Do we have more to do?
if (currentInit < 5) begin
//Setup next register.
currentInit <= currentInit + 1'b1;
//Go back to beginning
initState <= 3'd1;
end else begin
//Stay here forever.
//"Remove" this module from the circuit too.
initState = 3'd4;
end
end
3'd4: begin
//Stay here forever.
doneInit <= 1;
manualDone <= 1'b0;
i2cEnable <= 1'b0;
//Unless we want to send data manually...
if (manualSend == 1'b1) begin
//Send i2c data manually.
i2cEnable <= 1'b1;
i2cData <= manualData;
i2cRegister <= manualRegister;
//Go to a wait state.
initState <= 3'd5;
end
end
3'd5: begin
if (i2cDone) begin
//Go to a finished state
initState <= 3'd6;
end
end
3'd6: begin
//Done
i2cEnable <= 1'b0;
manualDone <= 1'b1;
initState <= 3'd4;
end
default: begin
end
endcase
end
end
assign audioInitError = i2cError;
endmodule
| 6.832796 |
module AudioInterface (
input clk,
input reset,
input ADC_SDATA,
output DAC_SDATA,
output BCLK,
output MCLK,
output LRCLK,
inout SCL,
inout SDA,
output error,
input [23:0] LeftPlayData,
input [23:0] RightPlayData,
output [23:0] LeftRecData,
output [23:0] RightRecData,
output NewFrame
);
endmodule
| 6.957491 |
module ClkDivider (
clk,
clk_div
);
localparam constantNumber = 37500000; //10Hz, FOR THE BOARD
//localparam constantNumber = 2; //FOR THE SIMULATION
input clk;
output clk_div;
reg [31:0] count = 0;
reg clk_div = 0;
always @(posedge (clk)) begin
if (count == constantNumber - 1) count <= 32'b0;
else count <= count + 1;
end
always @(posedge (clk)) begin
if (count == constantNumber - 1) clk_div <= ~clk_div;
else clk_div <= clk_div;
end
endmodule
| 6.643482 |
module
//////////////////////////////////////////////////////////////////////////////////
module AudioMux(
input clk,
input reset_n,
input run,
input [1:0] select,
input l_i2sToPcm_d_en,
input r_i2sToPcm_d_en,
input [23:0] l_i2sToPcm_d,
input [23:0] r_i2sToPcm_d,
input l_interp_d_en,
input r_interp_d_en,
input [23:0] l_interp_d,
input [23:0] r_interp_d,
input sin_wave_d_en,
input [23:0] sin_wave_d,
input l_eq_d_en,
input r_eq_d_en,
input [23:0] l_eq_d,
input [23:0] r_eq_d,
output reg l_pcmToI2s_d_valid,
output reg r_pcmToI2s_d_valid,
output reg [23:0] l_pcmToI2s_d,
output reg [23:0] r_pcmToI2s_d
);
always @ (posedge clk) begin
if (!reset_n || !run) begin
l_pcmToI2s_d <= 0;
r_pcmToI2s_d <= 0;
l_pcmToI2s_d_valid <= 0;
r_pcmToI2s_d_valid <= 0;
end
else begin
case (select)
2'b00: begin
l_pcmToI2s_d_valid <= l_i2sToPcm_d_en;
r_pcmToI2s_d_valid <= r_i2sToPcm_d_en;
if (l_i2sToPcm_d_en)
l_pcmToI2s_d <= l_i2sToPcm_d;
else
l_pcmToI2s_d <= l_pcmToI2s_d;
if (r_i2sToPcm_d_en)
r_pcmToI2s_d <= r_i2sToPcm_d;
else
r_pcmToI2s_d <= r_pcmToI2s_d;
end
2'b01: begin
l_pcmToI2s_d_valid <= l_interp_d_en;
r_pcmToI2s_d_valid <= r_interp_d_en;
if (l_interp_d_en)
l_pcmToI2s_d <= l_interp_d;
else
l_pcmToI2s_d <= l_pcmToI2s_d;
if (r_interp_d_en)
r_pcmToI2s_d <= r_interp_d;
else
r_pcmToI2s_d <= r_pcmToI2s_d;
end
2'b10: begin
l_pcmToI2s_d_valid <= sin_wave_d_en;
r_pcmToI2s_d_valid <= sin_wave_d_en;
if (sin_wave_d_en) begin
l_pcmToI2s_d <= sin_wave_d;
r_pcmToI2s_d <= sin_wave_d;
end
else begin
l_pcmToI2s_d <= l_pcmToI2s_d;
r_pcmToI2s_d <= r_pcmToI2s_d;
end
end
2'b11: begin
l_pcmToI2s_d_valid <= l_eq_d_en;
r_pcmToI2s_d_valid <= r_eq_d_en;
if (l_eq_d_en)
l_pcmToI2s_d <= l_eq_d;
else
l_pcmToI2s_d <= l_pcmToI2s_d;
if (r_eq_d_en)
r_pcmToI2s_d <= r_eq_d;
else
r_pcmToI2s_d <= r_pcmToI2s_d;
end
endcase
end
end
endmodule
| 6.558648 |
module AudioOutput (
input reset_n,
clk,
ce2Hd,
input [15:0] BA,
input CIOn,
BRWn,
input [7:0] BD,
input COCKTAIL,
input STARTJMP1,
STARTJMP2,
output [7:0] pokey_to_cpu,
output [7:0] SOUT
);
wire cs_pokey3B = ~CIOn & ~BA[9];
wire cs_pokey3D = ~CIOn & BA[9];
wire [5:0] snd1, snd2;
wire [7:0] DIP = {1'b0, 1'b0, COCKTAIL, STARTJMP2, STARTJMP1, 1'b0, 1'b0, 1'b0};
wire [7:0] rdt3B, rdt3D;
PokeyW ic3D (
.clk(clk),
.ce(ce2Hd),
.rst_n(reset_n),
.ad(BA[3:0]),
.cs(cs_pokey3D),
.we(~BRWn),
.data_to_pokey(BD),
.data_from_pokey(rdt3D),
.snd(snd1),
.p(DIP)
);
PokeyW ic3B (
.clk(clk),
.ce(ce2Hd),
.rst_n(reset_n),
.ad(BA[3:0]),
.cs(cs_pokey3B),
.we(~BRWn),
.data_to_pokey(BD),
.data_from_pokey(rdt3B),
.snd(snd2),
.p(8'd0)
);
assign SOUT = {2'b00, snd1} + {2'b00, snd2};
assign pokey_to_cpu = cs_pokey3D ? rdt3D : rdt3B;
endmodule
| 7.17775 |
module AudioOut_1b (
clk,
butt_1,
butt_2,
butt_3,
butt_4,
oct,
audio_out
);
input clk;
input butt_1;
input butt_2;
input butt_3;
input butt_4;
output reg audio_out;
integer count1;
//integer count2;
//integer count3;
//integer count4;
//reg countTo;
integer note_1;
integer note_2;
integer note_3;
integer note_4;
input [2:0] oct;
initial begin
count1 = 1;
note_1 = 191113;
note_2 = 151686;
note_3 = 95556;
note_4 = 75843;
//countTo = 0;
end
//integer count1000hz;
always @(posedge clk) begin
/*
case(oct)
0:
begin //"C" octaves
note_1 = 191113;
note_2 = 95556;
note_3 = 47778;
note_4 = 23889;
end
1:
begin // "D" octaves
note_1 = 170262;
note_2 = 85131;
note_3 = 42566;
note_4 = 21283;
end
2:
begin // "E" octaves
note_1 = 151686;
note_2 = 75843;
note_3 = 37922;
note_4 = 18961;
end
endcase
*/
///////////////////
if (butt_1) begin
if (count1 >= note_1) begin
audio_out = ~audio_out;
count1 = 0;
end
count1 = count1 + 1;
end
if (butt_2) begin
if (count1 >= note_2) begin
audio_out = ~audio_out;
count1 = 0;
end
count1 = count1 + 1;
end
if (butt_3) begin
if (count1 >= note_3) begin
audio_out = ~audio_out;
count1 = 0;
end
count1 = count1 + 1;
end
if (butt_4) begin
if (count1 >= note_4) begin
audio_out = ~audio_out;
count1 = 0;
end
count1 = count1 + 1;
end
//////////////
/*
if(note_1)
begin
countTo = 191113;
end
if(note_2)
begin
countTo = 180386;
end
if(note_3)
begin
countTo = 170262;
end
if(note_4)
begin
countTo = 160706;
end
count1 = count1 + 1;
if (count1 == countTo)
begin
audio_out = ~audio_out;
count1 = 0;
countTo = -1;
end
*/
/*
if(~note_1)
begin
count1 = 0;
audio_out = 0;
end
else //if enable button is pressed, then make a sound
begin
if(count1 == 191113) //count 1/500th seconds
begin
audio_out = ~audio_out; //make a sound
count1 = 0; //reset counter
end
count1 = count1 + 1; //increment counter
end
*/
//////////////
end
endmodule
| 7.032128 |
module AudioPLL_audio_pll_0 (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire audio_clk_clk, // audio_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire audio_pll_locked_export; // audio_pll:locked -> reset_from_locked:locked
AudioPLL_audio_pll_0_audio_pll audio_pll (
.refclk (ref_clk_clk), // refclk.clk
.rst (ref_reset_reset), // reset.reset
.outclk_0(audio_clk_clk), // outclk0.clk
.locked (audio_pll_locked_export) // locked.export
);
altera_up_avalon_reset_from_locked_signal reset_from_locked (
.reset (reset_source_reset), // reset_source.reset
.locked(audio_pll_locked_export) // locked.export
);
endmodule
| 6.585036 |
module AudioPLL_audio_pll_0_audio_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("12.288135 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.585036 |
module AudioPWM (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////// KEY //////////
input [1:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW,
//////////// VGA //////////
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
//////////// GPIO, GPIO connect to GPIO Default //////////
inout [35:0] GPIO
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire clk_audio;
pll_audio pll (
.inclk0(MAX10_CLK1_50),
.c0(clk_audio),
.locked(LEDR[0])
); // remains at 50MHz
PWM_Controller pwm (
.PWM_CW(SW[9:0]),
.PWM_out(LEDR[1]),
.clk(clk_audio)
);
//=======================================================
// Structural coding
//=======================================================
endmodule
| 7.386683 |
module audioqsys_a_fefifo_7cf (
r_sync_rst,
b_full1,
b_non_empty1,
counter_reg_bit_3,
counter_reg_bit_2,
counter_reg_bit_0,
counter_reg_bit_1,
counter_reg_bit_4,
counter_reg_bit_5,
t_ena,
rvalid,
wreq,
clock
) /* synthesis synthesis_greybox=1 */;
input r_sync_rst;
output b_full1;
output b_non_empty1;
output counter_reg_bit_3;
output counter_reg_bit_2;
output counter_reg_bit_0;
output counter_reg_bit_1;
output counter_reg_bit_4;
output counter_reg_bit_5;
input t_ena;
input rvalid;
input wreq;
input clock;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
wire \_~4_combout ;
wire \b_full~0_combout ;
wire \b_full~1_combout ;
wire \b_full~2_combout ;
wire \b_non_empty~0_combout ;
wire \_~2_combout ;
wire \_~3_combout ;
wire \b_non_empty~1_combout ;
audioqsys_cntr_do7 count_usedw (
.r_sync_rst(r_sync_rst),
.counter_reg_bit_3(counter_reg_bit_3),
.counter_reg_bit_2(counter_reg_bit_2),
.counter_reg_bit_0(counter_reg_bit_0),
.counter_reg_bit_1(counter_reg_bit_1),
.counter_reg_bit_4(counter_reg_bit_4),
.counter_reg_bit_5(counter_reg_bit_5),
.updown(wreq),
._(\_~4_combout ),
.clock(clock)
);
cycloneive_lcell_comb \_~4 (
.dataa(t_ena),
.datab(b_full1),
.datac(rvalid),
.datad(gnd),
.cin(gnd),
.combout(\_~4_combout ),
.cout()
);
defparam \_~4 .lut_mask = 16'h9696; defparam \_~4 .sum_lutc_input = "datac";
dffeas b_full (
.clk(clock),
.d(\b_full~2_combout ),
.asdata(vcc),
.clrn(!r_sync_rst),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.q(b_full1),
.prn(vcc)
);
defparam b_full.is_wysiwyg = "true"; defparam b_full.power_up = "low";
dffeas b_non_empty (
.clk(clock),
.d(\b_non_empty~1_combout ),
.asdata(vcc),
.clrn(!r_sync_rst),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.q(b_non_empty1),
.prn(vcc)
);
defparam b_non_empty.is_wysiwyg = "true"; defparam b_non_empty.power_up = "low";
cycloneive_lcell_comb \b_full~0 (
.dataa(b_non_empty1),
.datab(counter_reg_bit_3),
.datac(counter_reg_bit_4),
.datad(counter_reg_bit_5),
.cin(gnd),
.combout(\b_full~0_combout ),
.cout()
);
defparam \b_full~0 .lut_mask = 16'hFFFE; defparam \b_full~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_full~1 (
.dataa(counter_reg_bit_2),
.datab(counter_reg_bit_0),
.datac(counter_reg_bit_1),
.datad(t_ena),
.cin(gnd),
.combout(\b_full~1_combout ),
.cout()
);
defparam \b_full~1 .lut_mask = 16'hFFFE; defparam \b_full~1 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_full~2 (
.dataa(b_full1),
.datab(\b_full~0_combout ),
.datac(\b_full~1_combout ),
.datad(rvalid),
.cin(gnd),
.combout(\b_full~2_combout ),
.cout()
);
defparam \b_full~2 .lut_mask = 16'hFEFF; defparam \b_full~2 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_non_empty~0 (
.dataa(b_full1),
.datab(t_ena),
.datac(gnd),
.datad(b_non_empty1),
.cin(gnd),
.combout(\b_non_empty~0_combout ),
.cout()
);
defparam \b_non_empty~0 .lut_mask = 16'hEEFF; defparam \b_non_empty~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \_~2 (
.dataa(counter_reg_bit_3),
.datab(counter_reg_bit_2),
.datac(counter_reg_bit_1),
.datad(counter_reg_bit_0),
.cin(gnd),
.combout(\_~2_combout ),
.cout()
);
defparam \_~2 .lut_mask = 16'hFEFF; defparam \_~2 .sum_lutc_input = "datac";
cycloneive_lcell_comb \_~3 (
.dataa(counter_reg_bit_4),
.datab(counter_reg_bit_5),
.datac(wreq),
.datad(\_~2_combout ),
.cin(gnd),
.combout(\_~3_combout ),
.cout()
);
defparam \_~3 .lut_mask = 16'hFFFE; defparam \_~3 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_non_empty~1 (
.dataa(\b_non_empty~0_combout ),
.datab(b_non_empty1),
.datac(\_~3_combout ),
.datad(rvalid),
.cin(gnd),
.combout(\b_non_empty~1_combout ),
.cout()
);
defparam \b_non_empty~1 .lut_mask = 16'hFEFF; defparam \b_non_empty~1 .sum_lutc_input = "datac";
endmodule
| 6.559673 |
module audioqsys_a_fefifo_7cf_1 (
r_sync_rst,
counter_reg_bit_3,
counter_reg_bit_0,
counter_reg_bit_2,
counter_reg_bit_1,
b_full1,
counter_reg_bit_5,
counter_reg_bit_4,
b_non_empty1,
r_val,
wreq,
clock
) /* synthesis synthesis_greybox=1 */;
input r_sync_rst;
output counter_reg_bit_3;
output counter_reg_bit_0;
output counter_reg_bit_2;
output counter_reg_bit_1;
output b_full1;
output counter_reg_bit_5;
output counter_reg_bit_4;
output b_non_empty1;
input r_val;
input wreq;
input clock;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
wire \_~0_combout ;
wire \b_full~0_combout ;
wire \b_full~1_combout ;
wire \b_full~2_combout ;
wire \b_non_empty~0_combout ;
wire \b_non_empty~1_combout ;
wire \b_non_empty~2_combout ;
audioqsys_cntr_do7_1 count_usedw (
.r_sync_rst(r_sync_rst),
.counter_reg_bit_3(counter_reg_bit_3),
.counter_reg_bit_0(counter_reg_bit_0),
.counter_reg_bit_2(counter_reg_bit_2),
.counter_reg_bit_1(counter_reg_bit_1),
.counter_reg_bit_5(counter_reg_bit_5),
.counter_reg_bit_4(counter_reg_bit_4),
.updown(wreq),
._(\_~0_combout ),
.clock(clock)
);
cycloneive_lcell_comb \_~0 (
.dataa(gnd),
.datab(gnd),
.datac(wreq),
.datad(r_val),
.cin(gnd),
.combout(\_~0_combout ),
.cout()
);
defparam \_~0 .lut_mask = 16'h0FF0; defparam \_~0 .sum_lutc_input = "datac";
dffeas b_full (
.clk(clock),
.d(\b_full~2_combout ),
.asdata(vcc),
.clrn(!r_sync_rst),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.q(b_full1),
.prn(vcc)
);
defparam b_full.is_wysiwyg = "true"; defparam b_full.power_up = "low";
dffeas b_non_empty (
.clk(clock),
.d(\b_non_empty~2_combout ),
.asdata(vcc),
.clrn(!r_sync_rst),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.q(b_non_empty1),
.prn(vcc)
);
defparam b_non_empty.is_wysiwyg = "true"; defparam b_non_empty.power_up = "low";
cycloneive_lcell_comb \b_full~0 (
.dataa(counter_reg_bit_5),
.datab(counter_reg_bit_4),
.datac(wreq),
.datad(b_non_empty1),
.cin(gnd),
.combout(\b_full~0_combout ),
.cout()
);
defparam \b_full~0 .lut_mask = 16'hFFFE; defparam \b_full~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_full~1 (
.dataa(counter_reg_bit_3),
.datab(counter_reg_bit_0),
.datac(counter_reg_bit_2),
.datad(counter_reg_bit_1),
.cin(gnd),
.combout(\b_full~1_combout ),
.cout()
);
defparam \b_full~1 .lut_mask = 16'hFFFE; defparam \b_full~1 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_full~2 (
.dataa(b_full1),
.datab(\b_full~0_combout ),
.datac(\b_full~1_combout ),
.datad(r_val),
.cin(gnd),
.combout(\b_full~2_combout ),
.cout()
);
defparam \b_full~2 .lut_mask = 16'hFEFF; defparam \b_full~2 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_non_empty~0 (
.dataa(counter_reg_bit_2),
.datab(counter_reg_bit_1),
.datac(counter_reg_bit_5),
.datad(counter_reg_bit_4),
.cin(gnd),
.combout(\b_non_empty~0_combout ),
.cout()
);
defparam \b_non_empty~0 .lut_mask = 16'hFFFE; defparam \b_non_empty~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_non_empty~1 (
.dataa(counter_reg_bit_3),
.datab(\b_non_empty~0_combout ),
.datac(counter_reg_bit_0),
.datad(r_val),
.cin(gnd),
.combout(\b_non_empty~1_combout ),
.cout()
);
defparam \b_non_empty~1 .lut_mask = 16'hEFFF; defparam \b_non_empty~1 .sum_lutc_input = "datac";
cycloneive_lcell_comb \b_non_empty~2 (
.dataa(b_full1),
.datab(wreq),
.datac(b_non_empty1),
.datad(\b_non_empty~1_combout ),
.cin(gnd),
.combout(\b_non_empty~2_combout ),
.cout()
);
defparam \b_non_empty~2 .lut_mask = 16'hFFFE; defparam \b_non_empty~2 .sum_lutc_input = "datac";
endmodule
| 6.559673 |
module audioqsys_decode_msa (
src_data_51,
src_data_52,
wren,
w_anode1088w_2,
w_anode1096w_2,
w_anode1075w_2,
w_anode1104w_2
) /* synthesis synthesis_greybox=1 */;
input src_data_51;
input src_data_52;
input wren;
output w_anode1088w_2;
output w_anode1096w_2;
output w_anode1075w_2;
output w_anode1104w_2;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
cycloneive_lcell_comb \w_anode1088w[2]~0 (
.dataa(src_data_51),
.datab(gnd),
.datac(src_data_52),
.datad(wren),
.cin(gnd),
.combout(w_anode1088w_2),
.cout()
);
defparam \w_anode1088w[2]~0 .lut_mask = 16'hAFFF;
defparam \w_anode1088w[2]~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \w_anode1096w[2]~0 (
.dataa(src_data_52),
.datab(gnd),
.datac(src_data_51),
.datad(wren),
.cin(gnd),
.combout(w_anode1096w_2),
.cout()
);
defparam \w_anode1096w[2]~0 .lut_mask = 16'hAFFF;
defparam \w_anode1096w[2]~0 .sum_lutc_input = "datac";
cycloneive_lcell_comb \w_anode1075w[2] (
.dataa(src_data_52),
.datab(src_data_51),
.datac(wren),
.datad(gnd),
.cin(gnd),
.combout(w_anode1075w_2),
.cout()
);
defparam \w_anode1075w[2] .lut_mask = 16'h7F7F;
defparam \w_anode1075w[2] .sum_lutc_input = "datac";
cycloneive_lcell_comb \w_anode1104w[2]~0 (
.dataa(src_data_52),
.datab(src_data_51),
.datac(gnd),
.datad(wren),
.cin(gnd),
.combout(w_anode1104w_2),
.cout()
);
defparam \w_anode1104w[2]~0 .lut_mask = 16'hEEFF;
defparam \w_anode1104w[2]~0 .sum_lutc_input = "datac";
endmodule
| 6.970696 |
module audioqsys_ENABLE_HEADBANG (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.925956 |
module audioqsys_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.666974 |
module audioqsys_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
audioqsys_jtag_uart_sim_scfifo_w the_audioqsys_jtag_uart_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.666974 |
module audioqsys_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.666974 |
module audioqsys_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
audioqsys_jtag_uart_sim_scfifo_r the_audioqsys_jtag_uart_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.666974 |
module audioqsys_nios2_gen2_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [27:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//audioqsys_nios2_gen2_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
audioqsys_nios2_gen2_cpu_nios2_oci_td_mode audioqsys_nios2_gen2_cpu_nios2_oci_trc_ctrl_td_mode (
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_performance_monitors;
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
| 6.617016 |
module audioqsys_nios2_gen2_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.617016 |
module audioqsys_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audioqsys_onchip_memory2.hex";
output [31:0] readdata;
input [14:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.81412 |
module audioqsys_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [61:0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [61:0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1:0] entries;
reg [61:0] entry_0;
reg [61:0] entry_1;
wire full;
reg rd_address;
reg [61:0] rd_data;
wire [ 1:0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address) begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full) begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty) begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk) begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
| 6.705995 |
module AudioRam_controller (
input iReset,
input iStartLoad,
input iWriteClock,
input [ BITS-1:0] iSample,
input iReadClock,
input [LBITS-1:0] iReadAddr,
input iWindow,
output [ BITS-1:0] oValue,
output reg oLoadComplete,
output reg state
);
parameter BITS = 16;
parameter LBITS = 10;
//reg state;
parameter WAIT = 1'b0;
parameter WRITE = 1'b1;
reg [LBITS:0] wraddr;
reg wren, shot, reshot;
// look for start signal
always @(posedge iStartLoad or posedge reshot) begin
if (iStartLoad) shot <= 1'b1;
else shot <= 1'b0;
end
// write state machine
always @(posedge iWriteClock) begin
if (iReset) begin
state <= WAIT;
wraddr <= 0;
wren <= 1'b0;
oLoadComplete <= 1'b0;
end else begin
case (state)
WAIT: begin
wren <= 1'b0;
if (shot == 1'b1) begin
reshot <= 1'b1;
wraddr <= 0;
state <= WRITE;
end else state <= WAIT;
end
WRITE: begin
reshot <= 1'b0;
if (wraddr < 1024) begin
wren <= 1'b1;
wraddr <= wraddr + 11'b1;
state <= WRITE;
oLoadComplete <= 1'b0;
end else begin
wren <= 1'b0;
state <= WAIT;
oLoadComplete <= 1'b1;
end
end
endcase
end
end
wire [31:0] hammval, hannval;
wire [15:0] hamm, hann, hammtop, hanntop, datain;
assign hammval = hamm * iSample;
assign hannval = hann * iSample;
assign hammtop = {hammval[31], hammval[27:13]};
assign hanntop = {hannval[31], hannval[27:13]};
assign datain = (iWindow == 1'b1) ? hanntop : hammtop;
hammingrom hammrom (
.iAddress(wraddr),
.oHamming(hamm)
);
hanningrom hannrom (
.iAddress(wraddr),
.oHanning(hann)
);
ram1024x16 aud_samp_ram (
.data(iSample),
.rdaddress(iReadAddr),
.rdclock(iReadClock),
.wraddress(wraddr),
.wrclock(iWriteClock),
.wren(wren),
.q(oValue)
);
endmodule
| 6.802602 |
module audiosystem (
input wire i_rstn,
input wire i_mck,
input wire i_bck,
input wire i_ws,
input wire i_sdi,
output wire o_sdo_l,
output wire o_sdo_r,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_b0,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_b1,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_b2,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_a1,
input wire signed [`c_COEFF_NBITS-1:0] i_lp0_a2,
input wire signed [`c_COEFF_NBITS-1:0] i_lp1_b0,
input wire signed [`c_COEFF_NBITS-1:0] i_lp1_b1,
input wire signed [`c_COEFF_NBITS-1:0] i_lp1_b2,
input wire signed [`c_COEFF_NBITS-1:0] i_lp1_a1,
input wire signed [`c_COEFF_NBITS-1:0] i_lp1_a2,
input wire signed [`c_COEFF_NBITS-1:0] i_hp0_b0,
input wire signed [`c_COEFF_NBITS-1:0] i_hp0_b1,
input wire signed [`c_COEFF_NBITS-1:0] i_hp0_b2,
input wire signed [`c_COEFF_NBITS-1:0] i_hp0_a1,
input wire signed [`c_COEFF_NBITS-1:0] i_hp0_a2,
input wire signed [`c_COEFF_NBITS-1:0] i_hp1_b0,
input wire signed [`c_COEFF_NBITS-1:0] i_hp1_b1,
input wire signed [`c_COEFF_NBITS-1:0] i_hp1_b2,
input wire signed [`c_COEFF_NBITS-1:0] i_hp1_a1,
input wire signed [`c_COEFF_NBITS-1:0] i_hp1_a2
);
//i2s data control signals
wire s_sync;
// IIR i/o signals
wire signed [`c_DATA_NBITS-1:0] s_iir_l_in;
wire signed [`c_DATA_NBITS-1:0] s_iir_r_in;
wire signed [`c_DATA_NBITS-1:0] s_iir_l_lp_out;
wire signed [`c_DATA_NBITS-1:0] s_iir_l_hp_out;
wire signed [`c_DATA_NBITS-1:0] s_iir_r_lp_out;
wire signed [`c_DATA_NBITS-1:0] s_iir_r_hp_out;
i2s_rxtx_slave inst_i2s_rxtx_slave (
.i_rstn(i_rstn),
.i_mck (i_mck),
.i_bck (i_bck),
.i_ws (i_ws),
.i_sdi(i_sdi),
.o_l24(s_iir_l_in), // serial to parallel input to IIR filter left channel
.o_r24(s_iir_r_in), // serial to parallel input to IIR filter right channel
.o_sync(s_sync), // parallel o_l24 and o_r24 data valid input to IIR filters
.i_l_lp_24(s_iir_l_lp_out), // parallel output from IIR filter left LPF
.i_l_hp_24(s_iir_l_hp_out), // parallel output from IIR filter left HPF
.i_r_lp_24(s_iir_r_lp_out), // parallel output from IIR filter right LPF
.i_r_hp_24(s_iir_r_hp_out), // parallel output from IIR filter right HPF
.o_sdo_l(o_sdo_l), // serial I2S stream left channel LPF on ws=0, HPF on ws=1
.o_sdo_r(o_sdo_r) // serial I2S stream right channel LPF on ws=0, HPF on ws=1
);
xover_iir inst_xover_iir_left (
.i_mck(i_mck),
.i_iir(s_iir_l_in),
.i_sample_valid(s_sync),
.o_iir_hpf(s_iir_l_hp_out),
.o_iir_lpf(s_iir_l_lp_out),
.o_sample_valid(),
.o_busy(),
// LPF coefficients
.i_lp0_b0(i_lp0_b0),
.i_lp0_b1(i_lp0_b1),
.i_lp0_b2(i_lp0_b2),
.i_lp0_a1(i_lp0_a1),
.i_lp0_a2(i_lp0_a2),
.i_lp1_b0(i_lp1_b0),
.i_lp1_b1(i_lp1_b1),
.i_lp1_b2(i_lp1_b2),
.i_lp1_a1(i_lp1_a1),
.i_lp1_a2(i_lp1_a2),
// HPF coefficeints
.i_hp0_b0(i_hp0_b0),
.i_hp0_b1(i_hp0_b1),
.i_hp0_b2(i_hp0_b2),
.i_hp0_a1(i_hp0_a1),
.i_hp0_a2(i_hp0_a2),
.i_hp1_b0(i_hp1_b0),
.i_hp1_b1(i_hp1_b1),
.i_hp1_b2(i_hp1_b2),
.i_hp1_a1(i_hp1_a1),
.i_hp1_a2(i_hp1_a2)
);
xover_iir inst_xover_iir_right (
.i_mck(i_mck),
.i_iir(s_iir_r_in),
.i_sample_valid(s_sync),
.o_iir_hpf(s_iir_r_hp_out),
.o_iir_lpf(s_iir_r_lp_out),
.o_sample_valid(),
.o_busy(),
// LPF coefficients
.i_lp0_b0(i_lp0_b0),
.i_lp0_b1(i_lp0_b1),
.i_lp0_b2(i_lp0_b2),
.i_lp0_a1(i_lp0_a1),
.i_lp0_a2(i_lp0_a2),
.i_lp1_b0(i_lp1_b0),
.i_lp1_b1(i_lp1_b1),
.i_lp1_b2(i_lp1_b2),
.i_lp1_a1(i_lp1_a1),
.i_lp1_a2(i_lp1_a2),
// HPF coefficeints
.i_hp0_b0(i_hp0_b0),
.i_hp0_b1(i_hp0_b1),
.i_hp0_b2(i_hp0_b2),
.i_hp0_a1(i_hp0_a1),
.i_hp0_a2(i_hp0_a2),
.i_hp1_b0(i_hp1_b0),
.i_hp1_b1(i_hp1_b1),
.i_hp1_b2(i_hp1_b2),
.i_hp1_a1(i_hp1_a1),
.i_hp1_a2(i_hp1_a2)
);
endmodule
| 7.268402 |
module, and an incredibly crude one
// Operates at the baseline clock frequency, TX only
// ////////////////////////////////////////////////////////
module audioUART
( input wire i_clk,
input wire i_rst,
input wire [7:0] i_data,
input wire i_valid,
output wire o_ready,
output wire o_serial
);
//10 possible states - Start, Stop/Idle, data[7:0]
//Increment, remembering that UART is little endian bitwise
//Integer FSM, I don't need to run this very fast
localparam l_START = 9;
localparam l_STOP = 8;
integer r_state = l_START;
reg r_ready;
reg r_serial;
reg [7:0] r_data; //Buffer data during process.
assign o_ready = r_ready;
assign o_serial = r_serial;
always @ (posedge i_clk, posedge i_rst)
begin
if (i_rst == 1'b1)
begin
r_state <= l_STOP;
r_data <= 8'b00001111;
r_serial <= 1'b0;
r_ready <= 1'b0;
end
else if (i_clk == 1'b1)
begin
case (r_state) //Deals with transitions
//The Stop bit/idle state
l_START: if (i_valid == 1'b1 && r_ready == 1'b1)
begin
r_ready <= 1'b0;
r_data <= i_data;
r_serial <= 1'b0;
r_state <= 0;
end
l_STOP: begin
r_state <= l_START;
r_ready <= 1'b1;
r_serial <= 1'b1;
end
default: begin
r_state <= r_state + 1;
r_ready <= (r_state == 7) ? 1'b1 : 1'b0;
r_serial <= r_data[r_state];
end
endcase
end
end
endmodule
| 7.482665 |
module
// Needs to check:
// That data will be written correctly
// That continuous streaming (`assign o_ready = i_valid`) is fine
// That the module can be stalled for a time.
// ////////////////////////////////////////////////////////////////
`timescale 100ns/1ns
module audioUART_tb;
//Module constants and IO
reg r_clk;
localparam l_rstLen = 1;
localparam l_halfClk = 100; //ns
reg r_rst;
reg [7:0] r_input;
reg r_valid;
wire w_serial;
wire w_ready;
//File loading declarations!
integer file;
integer r = 1;
reg [7:0] r_cycles;
//Loading data from file (also clocking)
initial
begin
file = $fopen("C:/Users/Alexander Greer/Documents/simpleArray/input_audioUART.txt", "r");
while (r > 0) // sfgets returns 0 at EoF
begin
//Load the data, number of cycles to run, and r_valid signal
r = $fscanf(file,"%x %d %b\n", r_input, r_cycles ,r_valid);
if (r > 0)
begin
while (r_cycles > 0)
begin
r_cycles = r_cycles - 1;
r_clk = 1'b0;
#l_halfClk;
r_clk = 1'b1;
#l_halfClk;
end
end
end
$fclose(file);
end
//Startup reset
initial
begin
r_rst = 1'b1;
#l_rstLen;
r_rst = 1'b0;
end
//component instantiation
audioUART UUT (.i_clk(r_clk), .i_rst(r_rst), .i_data(r_input), .i_valid(r_valid),
.o_ready(w_ready), .o_serial(w_serial));
endmodule
| 6.537105 |
module AUDIOVOLUME #(
parameter BIT = 24,
parameter VOL_BIT = 8
) (
CLK,
in_L,
in_R,
out_L,
out_R,
Volume
);
input signed [BIT-1:0] in_L, in_R;
input [VOL_BIT-1:0] Volume;
input CLK;
output signed [BIT-1:0] out_L, out_R;
wire signed [BIT-1:0] out_L, out_R;
reg signed [BIT+VOL_BIT-1:0] temp_L, temp_R;
assign out_L = temp_L[BIT+VOL_BIT-1:VOL_BIT-1];
assign out_R = temp_R[BIT+VOL_BIT-1:VOL_BIT-1];
always @(posedge CLK) begin
temp_L <= ($signed({{VOL_BIT{in_L[BIT-1]}}, in_L}) * $signed({1'b0, Volume}));
temp_R <= ($signed({{VOL_BIT{in_R[BIT-1]}}, in_R}) * $signed({1'b0, Volume}));
end
endmodule
| 7.109332 |
module Audio_0 (
// inputs:
iCLK_18_4,
iDATA,
iRST_N,
iWR,
iWR_CLK,
// outputs:
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
oDATA
);
output oAUD_BCK;
output oAUD_DATA;
output oAUD_LRCK;
output oAUD_XCK;
output [15:0] oDATA;
input iCLK_18_4;
input [15:0] iDATA;
input iRST_N;
input iWR;
input iWR_CLK;
wire oAUD_BCK;
wire oAUD_DATA;
wire oAUD_LRCK;
wire oAUD_XCK;
wire [15:0] oDATA;
AUDIO_DAC_FIFO the_AUDIO_DAC_FIFO (
.iCLK_18_4(iCLK_18_4),
.iDATA (iDATA),
.iRST_N (iRST_N),
.iWR (iWR),
.iWR_CLK (iWR_CLK),
.oAUD_BCK (oAUD_BCK),
.oAUD_DATA(oAUD_DATA),
.oAUD_LRCK(oAUD_LRCK),
.oAUD_XCK (oAUD_XCK),
.oDATA (oDATA)
);
defparam the_AUDIO_DAC_FIFO.CHANNEL_NUM = 2, the_AUDIO_DAC_FIFO.DATA_WIDTH = 16,
the_AUDIO_DAC_FIFO.REF_CLK = 18432000, the_AUDIO_DAC_FIFO.SAMPLE_RATE = 48000;
endmodule
| 7.160131 |
module AUDIO_ADC (
// host
clk,
reset,
read,
readdata,
//available,
empty,
clear,
// dac
bclk,
adclrc,
adcdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input read;
output [(DATA_WIDTH-1):0] readdata;
output empty;
input clear;
input bclk;
input adclrc;
input adcdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
reg [ 4:0] bit_index; //0~31
reg valid_bit;
reg reg_adc_left;
reg [(DATA_WIDTH-1):0] reg_adc_serial_data;
reg [(DATA_WIDTH-1):0] adcfifo_writedata;
reg adcfifo_write;
wire adcfifo_full;
reg wait_one_clk;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//===== Serialize data (I2S) to ADC-FIFO =====
wire is_left_ch;
assign is_left_ch = ~adclrc;
always @(posedge bclk) begin
if (reset || clear) begin
bit_index = DATA_WIDTH;
reg_adc_left = is_left_ch;
adcfifo_write = 1'b0;
valid_bit = 0;
end else begin
if (adcfifo_write) adcfifo_write = 1'b0; // disable write at second cycle
if (reg_adc_left ^ is_left_ch) begin // channel change
reg_adc_left = is_left_ch;
valid_bit = 1'b1;
wait_one_clk = 1'b1;
if (reg_adc_left) bit_index = DATA_WIDTH;
end
// serial bit to adcfifo
if (valid_bit && wait_one_clk) wait_one_clk = 1'b0;
else if (valid_bit && !wait_one_clk) begin
bit_index = bit_index - 1'b1;
reg_adc_serial_data[bit_index] = adcdat;
if ((bit_index == 0) || (bit_index == (DATA_WIDTH / 2))) begin
if (bit_index == 0 && !adcfifo_full) begin // write data to adcfifo
adcfifo_writedata = reg_adc_serial_data;
adcfifo_write = 1'b1; // enable write at first cycle
end
valid_bit = 0;
end
end
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo adc_fifo (
// write (adc write to fifo)
.wrclk(bclk),
.wrreq(adcfifo_write),
.data(adcfifo_writedata),
.wrfull(adcfifo_full),
.aclr(clear), // sync with wrclk
// read (host read from fifo)
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdempty(empty)
);
endmodule
| 7.501448 |
module AUDIO_DAC_ADC (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_inL,
oAUD_inR,
iAUD_ADCDAT,
iAUD_extR,
iAUD_extL,
// Control Signals
iCLK_18_4,
iRST_N
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 32000; // 32 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// audio input FROM top-level module
input signed [DATA_WIDTH-1:0] iAUD_extR, iAUD_extL;
// audio output TO top-level module
output signed [DATA_WIDTH-1:0] oAUD_inL, oAUD_inR;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
input iAUD_ADCDAT;
// Control Signals
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
// to DAC and from ADC
reg signed [DATA_WIDTH-1:0] AUD_outL, AUD_outR;
reg signed [DATA_WIDTH-1:0] AUD_inL, AUD_inR;
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
wire [3:0] bit_in;
//////////////////////////////////////////////////
//////////// AUD_BCK Generator //////////////
/////////////////////////////////////////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end else begin
if (BCK_DIV >= REF_CLK / (SAMPLE_RATE * DATA_WIDTH * CHANNEL_NUM * 2) - 1) begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end else BCK_DIV <= BCK_DIV + 4'd1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
//oAUD_LRCK is high for left and low for right////
//////////////////////////////////////////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end else begin
// LRCK 1X
if (LRCK_1X_DIV >= REF_CLK / (SAMPLE_RATE * 2) - 1) begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end else LRCK_1X_DIV <= LRCK_1X_DIV + 9'd1;
// LRCK 2X
if (LRCK_2X_DIV >= REF_CLK / (SAMPLE_RATE * 4) - 1) begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end else LRCK_2X_DIV <= LRCK_2X_DIV + 8'd1;
// LRCK 4X
if (LRCK_4X_DIV >= REF_CLK / (SAMPLE_RATE * 8) - 1) begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end else LRCK_4X_DIV <= LRCK_4X_DIV + 7'd1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// 16 Bits - MSB First //////////////////
/// Clocks in the ADC input
/// and sets up the output bit selector
/// and clocks out the DAC data
//////////////////////////////////////////////////
// first the ADC
always @(negedge oAUD_BCK or negedge iRST_N) begin
if (!iRST_N) SEL_Cont <= 0;
else begin
SEL_Cont <= SEL_Cont + 4'd1; // 4 bit counter, so it wraps at 16
if (LRCK_1X) AUD_inL[~(SEL_Cont)] <= iAUD_ADCDAT;
else AUD_inR[~(SEL_Cont)] <= iAUD_ADCDAT;
end
end
assign oAUD_inL = AUD_inL;
assign oAUD_inR = AUD_inR;
// now the DAC -- output the DAC bit-stream
assign oAUD_DATA = (LRCK_1X) ? AUD_outL[~SEL_Cont] : AUD_outR[~SEL_Cont];
// register the inputs
always @(negedge LRCK_1X) begin
AUD_outL <= iAUD_extL;
end
always @(posedge LRCK_1X) begin
AUD_outR <= iAUD_extR;
end
endmodule
| 7.83142 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module audio_amplifier (
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
input wire avalon_left_sink_valid, // avalon_left_sink.valid
output wire avalon_left_sink_ready, // .ready
input wire [23:0] avalon_left_sink_data, // .data
input wire [23:0] avalon_right_sink_data, // avalon_right_sink.data
output wire avalon_right_sink_ready, // .ready
input wire avalon_right_sink_valid, // .valid
output wire [23:0] avalon_left_source_data, // avalon_left_source.data
input wire avalon_left_source_ready, // .ready
output wire avalon_left_source_valid, // .valid
output wire avalon_right_source_valid, // avalon_right_source.valid
input wire avalon_right_source_ready, // .ready
output wire [23:0] avalon_right_source_data, // .data
input wire [1:0] key_signal, // key.key_signal
output wire [6:0] hex_signal, // hex.hex_signal
output wire [9:0] led_signal // led.led_signal
);
wire[3:0] gain;
wire change_up, change_down;
assign avalon_left_sink_ready = avalon_left_source_ready;
assign avalon_right_sink_ready = avalon_right_source_ready;
key_sync key_up(change_up, clock_clk, ~key_signal[0]);
key_sync key_down(change_down, clock_clk, ~key_signal[1]);
get_gain get(gain, clock_clk, change_up, change_down);
gain_led gled(led_signal, gain);
status_hex shex(hex_signal, avalon_left_source_ready, avalon_right_source_ready, avalon_left_sink_valid, avalon_right_sink_valid);
amplifier amp_left(avalon_left_source_data, avalon_left_source_valid, avalon_left_sink_data, avalon_left_sink_valid & avalon_left_source_ready, clock_clk, reset_reset, gain);
amplifier amp_right(avalon_right_source_data, avalon_right_source_valid, avalon_right_sink_data, avalon_right_sink_valid & avalon_right_source_ready, clock_clk, reset_reset, gain);
endmodule
| 7.702374 |
module converts serial MIC input into a 12-bit parallel register [11:0]sample.
//
// The audio input is sampled by PmodMIC3, the sampling rate of which is assigned to Pin 1 ChipSelect (cs).
// The Analog-to-Digital Concertor (ADC) on PmodMIC3 converts the audio analog signal into a 16-bit digital form
// (4-bit leading zeros + 12-bit voice data). The 16 bits are output at PmodMIC3 Pin 3 (MISO) in serial (bit-by-bit)
// according to a serial clock (sclk) that is assigned to PmodMIC3 Pin 4.
//
// This module first generates sclk which is to be fed into PmodMIC3 Pin 4. Meanwhile it reads the 16 bits individually
// while they are available and joins them into a 16-bit register temp. [11:0] sample is the final output represents the
// 12-bit MIC input sample.
//
//
//////////////////////////////////////////////////////////////////////////////////
module Audio_Capture(
input CLK, // 100MHz clock
input cs, // sampling clock, 20kHz
input MISO, // J_MIC3_Pin3, serial mic input
output clk_samp, // J_MIC3_Pin1
output reg sclk, // J_MIC3_Pin4, MIC3 serial clock
output reg [11:0]sample // 12-bit audio sample data
);
reg [11:0]count2 = 0;
reg [11:0]temp = 0;
initial begin
sclk = 0;
end
assign clk_samp = cs;
//Creating SPI clock signals
always @ (posedge CLK) begin
count2 <= (cs == 0) ? count2 + 1 : 0;
sclk <= (count2 == 50 || count2 == 100 || count2 == 150 || count2 == 200 || count2 == 250 || count2 == 300 || count2 == 350 || count2 == 400 || count2 == 450 || count2 == 500 || count2 == 550 || count2 == 600 || count2 == 650 || count2 == 700 || count2 == 750 || count2 == 800 || count2 == 850 || count2 == 900 || count2 == 950 || count2 == 1000 ||count2 == 1050 || count2 == 1100 || count2 == 1150 || count2 == 1200 || count2 == 1250 || count2 == 1300 || count2 == 1350 || count2 == 1400 || count2 == 1450 || count2 == 1500 || count2 == 1550 || count2 == 1600) ? ~sclk : sclk ;
end
always @ (negedge sclk) begin
temp <= temp<<1 | MISO;
end
always @ (posedge cs) begin
sample <= temp[11:0];
end
endmodule
| 7.210574 |
module audio_clk (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
audio_clk_0002 audio_clk_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0(outclk_0), // outclk0.clk
.locked (locked) // locked.export
);
endmodule
| 6.73134 |
module ROM (
clk,
addr,
data
);
parameter ADDR_W = 8;
parameter DATA_W = 24;
parameter ROM_DATA = "undef";
input clk;
input [ADDR_W-1:0] addr;
output reg [DATA_W-1:0] data;
reg [DATA_W-1:0] rom[0:2**ADDR_W-1];
initial $readmemh(ROM_DATA, rom);
always @(posedge clk) data <= rom[addr];
endmodule
| 7.434902 |
module Audio_Config (
CLOCK,
I2C_SCLK,
I2C_SDAT
);
input CLOCK;
inout I2C_SDAT;
output I2C_SCLK;
wire CLOCK;
wire PRE_CLOCK;
wire START_TX;
wire TX_DONE;
wire ACK;
wire [23:0] DATA;
parameter prescale = 2500;
// Audio Config Data
// I based the choice of configuration options pretty heavily on the example code given. I've removed some of their unnecessary stuff.
parameter dev_addr = 8'h34;
parameter audio_path = 16'h0A04;
parameter dac_sel = 16'h0810;
parameter power = 16'h0C00;
parameter data_format = 16'h0E01;
parameter sampling = 16'h1002;
parameter activate = 16'h1201;
parameter num_states = 11;
reg start_tx;
reg [23:0] data;
reg [7:0] state;
reg [3:0] step;
initial begin
state = 0;
data[23:0] <= {dev_addr, audio_path};
start_tx <= 1;
end
always @(posedge ACK) begin
state <= state + 1'b1;
end
always @(posedge TX_DONE) begin
start_tx <= 0;
case (state)
1: begin
data[23:0] <= {dev_addr, dac_sel};
start_tx <= 1'b1;
end
2: begin
data[23:0] <= {dev_addr, power};
start_tx <= 1'b1;
end
3: begin
data[23:0] <= {dev_addr, data_format};
start_tx <= 1'b1;
end
4: begin
data[23:0] <= {dev_addr, sampling};
start_tx <= 1'b1;
end
5: begin
data[23:0] <= {dev_addr, activate};
start_tx <= 1'b1;
end
/*
4:
begin
data[23:0] <= {dev_addr, e};
start_tx <=1'b1;
end
5:
begin
data[23:0] <= {dev_addr, f};
start_tx <=1'b1;
end
6:
begin
data[23:0] <= {dev_addr, g};
start_tx <=1'b1;
end
7:
begin
data[23:0] <= {dev_addr, h};
start_tx <=1'b1;
end
8:
begin
data[23:0] <= {dev_addr, i};
start_tx <=1'b1;
end
9:
begin
data[23:0] <= {dev_addr, j};
start_tx <=1'b1;
end
10:
begin
data[23:0] <= {dev_addr, k};
start_tx <=1'b1;
end
*/
endcase
end
assign DATA = data;
assign START_TX = start_tx;
PRESCALER i2c_pre (
CLOCK,
PRE_CLOCK,
prescale
);
I2C_Control i2c_ctrl (
PRE_CLOCK,
I2C_SCLK,
I2C_SDAT,
DATA,
START_TX,
TX_DONE,
ACK
);
endmodule
| 8.413577 |
module audio_converter (
// Audio side
input AUD_BCK, // Audio bit clock
input AUD_LRCK, // left-right clock
input AUD_ADCDAT,
output AUD_DATA,
// Controller side
input iRST_N, // reset
input [15:0] AUD_outL,
input [15:0] AUD_outR,
output reg [15:0] AUD_inL,
output reg [15:0] AUD_inR
);
// 16 Bits - MSB First
// Clocks in the ADC input
// and sets up the output bit selector
reg [3:0] SEL_Cont;
always @(negedge AUD_BCK or negedge iRST_N) begin
if (!iRST_N) SEL_Cont <= 4'h0;
else begin
SEL_Cont <= SEL_Cont + 1'b1; //4 bit counter, so it wraps at 16
if (AUD_LRCK) AUD_inL[~(SEL_Cont)] <= AUD_ADCDAT;
else AUD_inR[~(SEL_Cont)] <= AUD_ADCDAT;
end
end
// output the DAC bit-stream
assign AUD_DATA = (AUD_LRCK) ? AUD_outL[~SEL_Cont] : AUD_outR[~SEL_Cont];
endmodule
| 6.875774 |
module AUDIO_DAC (
// host
clk,
reset,
write,
writedata,
full,
clear,
// dac
bclk,
daclrc,
dacdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input write;
input [(DATA_WIDTH-1):0] writedata;
output full;
input clear;
input bclk;
input daclrc;
output dacdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Note. Left Justified Mode
reg request_bit;
reg bit_to_dac;
reg [ 4:0] bit_index; //0~31
reg dac_is_left;
reg [(DATA_WIDTH-1):0] data_to_dac;
reg [(DATA_WIDTH-1):0] shift_data_to_dac;
//
wire dacfifo_empty;
wire dacfifo_read;
wire [(DATA_WIDTH-1):0] dacfifo_readdata;
wire is_left_ch;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//////////// read data from fifo
assign dacfifo_read = (dacfifo_empty) ? 1'b0 : 1'b1;
always @(negedge is_left_ch) begin
if (dacfifo_empty) data_to_dac = 0;
else data_to_dac = dacfifo_readdata;
end
//////////// streaming data(32-bits) to dac chip(I2S 1-bits port)
assign is_left_ch = ~daclrc;
always @(negedge bclk) begin
if (reset || clear) begin
request_bit = 0;
bit_index = 0;
dac_is_left = is_left_ch;
bit_to_dac = 1'b0;
end else begin
if (dac_is_left ^ is_left_ch) begin // channel change
dac_is_left = is_left_ch;
request_bit = 1;
if (dac_is_left) begin
shift_data_to_dac = data_to_dac;
bit_index = DATA_WIDTH;
end
end
// serial data to dac
if (request_bit) begin
bit_index = bit_index - 1'b1;
bit_to_dac = shift_data_to_dac[bit_index]; // MSB as first bit
if ((bit_index == 0) || (bit_index == (DATA_WIDTH / 2))) request_bit = 0;
end else bit_to_dac = 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign dacdat = bit_to_dac;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo dac_fifo (
// write
.wrclk(clk),
.wrreq(write),
.data(writedata),
.wrfull(full),
.aclr(clear), // sync with wrclk
// read
//.rdclk(bclk),
.rdclk(is_left_ch),
.rdreq(dacfifo_read),
.q(dacfifo_readdata),
.rdempty(dacfifo_empty)
);
endmodule
| 7.505814 |
module
// add audio I/O from top-level module
// modifed by Bruce Land, Cornell University 2007
/////////////////////////////////////////////////////////////////////////
module AUDIO_DAC_ADC (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_inL,
oAUD_inR,
iAUD_ADCDAT,
iAUD_extR,
iAUD_extL,
// Control Signals
iCLK_18_4,
iRST_N
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// audio input FROM top-level module
input signed [DATA_WIDTH-1:0] iAUD_extR, iAUD_extL;
// audio output TO top-level module
output signed [DATA_WIDTH-1:0] oAUD_inL, oAUD_inR;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
input iAUD_ADCDAT;
// Control Signals
//input [1:0] iSrc_Select;
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
// to DAC and from ADC
reg signed [DATA_WIDTH-1:0] AUD_outL, AUD_outR ;
reg signed [DATA_WIDTH-1:0] AUD_inL, AUD_inR ;
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
wire [3:0] bit_in;
//////////////////////////////////////////////////
//////////// AUD_BCK Generator //////////////
/////////////////////////////////////////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
//oAUD_LRCK is high for left and low for right////
//////////////////////////////////////////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
// LRCK 4X
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// 16 Bits - MSB First //////////////////
/// Clocks in the ADC input
/// and sets up the output bit selector
/// and clocks out the DAC data
//////////////////////////////////////////////////
// first the ADC
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N) SEL_Cont <= 0;
else
begin
SEL_Cont <= SEL_Cont+1; //4 bit counter, so it wraps at 16
if (LRCK_1X)
AUD_inL[~(SEL_Cont)] <= iAUD_ADCDAT;
else
AUD_inR[~(SEL_Cont)] <= iAUD_ADCDAT;
end
end
assign oAUD_inL = AUD_inL;
assign oAUD_inR = AUD_inR;
// now the DAC -- output the DAC bit-stream
assign oAUD_DATA = (LRCK_1X)? AUD_outL[~SEL_Cont]: AUD_outR[~SEL_Cont] ;
//assign oAUD_DATA = (LRCK_1X)? iAUD_extL[~SEL_Cont]: iAUD_extR[~SEL_Cont] ;
// register the inputs
always@(posedge LRCK_1X) //oAUD_LRCK -- posedge LRCK_1X
begin
AUD_outR <= iAUD_extR;
AUD_outL <= iAUD_extL ;
end
//assign AUD_outR = iAUD_extR ;
//assign AUD_outL = iAUD_extL ;
endmodule
| 7.896826 |
module AUDIO_DAC_FIFO ( // FIFO Side
iDATA,
iWR,
iWR_CLK,
oDATA,
// Audio Side
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
// Control Signals
iCLK_18_4,
iRST_N
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// FIFO Side
input [DATA_WIDTH-1:0] iDATA;
input iWR;
input iWR_CLK;
output [DATA_WIDTH-1:0] oDATA;
wire [DATA_WIDTH-1:0] mDATA;
reg mDATA_RD;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output oAUD_BCK;
output oAUD_XCK;
reg oAUD_BCK;
// Control Signals
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [ 3:0] BCK_DIV;
reg [ 8:0] LRCK_1X_DIV;
reg [ 7:0] LRCK_2X_DIV;
reg [ 3:0] SEL_Cont;
////////////////////////////////////
reg [DATA_WIDTH-1:0] DATA_Out;
reg [DATA_WIDTH-1:0] DATA_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
FIFO_16_256 u0 (
.data(iDATA),
.wrreq(iWR),
.rdreq(mDATA_RD),
.rdclk(iCLK_18_4),
.wrclk(iWR_CLK),
.aclr(~iRST_N),
.q(mDATA),
.wrfull(oDATA[0])
);
assign oAUD_XCK = ~iCLK_18_4;
//////////// AUD_BCK Generator //////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end else begin
if (BCK_DIV >= REF_CLK / (SAMPLE_RATE * DATA_WIDTH * CHANNEL_NUM * 2) - 1) begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end else BCK_DIV <= BCK_DIV + 1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
end else begin
// LRCK 1X
if (LRCK_1X_DIV >= REF_CLK / (SAMPLE_RATE * 2) - 1) begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end else LRCK_1X_DIV <= LRCK_1X_DIV + 1;
// LRCK 2X
if (LRCK_2X_DIV >= REF_CLK / (SAMPLE_RATE * 4) - 1) begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end else LRCK_2X_DIV <= LRCK_2X_DIV + 1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Read Signal Generator //////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
mDATA_RD <= 0;
end else begin
if (LRCK_1X_DIV == REF_CLK / (SAMPLE_RATE * 2) - 1) mDATA_RD <= 1;
else mDATA_RD <= 0;
end
end
//////////////////////////////////////////////////
////////////// DATA Latch //////////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) DATA_Out_Tmp <= 0;
else begin
if (LRCK_2X_DIV == REF_CLK / (SAMPLE_RATE * 4) - 1) DATA_Out_Tmp <= mDATA;
end
end
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) DATA_Out <= 0;
else begin
if (LRCK_2X_DIV == REF_CLK / (SAMPLE_RATE * 4) - 3) DATA_Out <= DATA_Out_Tmp;
end
end
//////////////////////////////////////////////////
////////// 16 Bits PISO MSB First //////////////
always @(negedge oAUD_BCK or negedge iRST_N) begin
if (!iRST_N) SEL_Cont <= 0;
else SEL_Cont <= SEL_Cont + 1;
end
assign oAUD_DATA = DATA_Out[~SEL_Cont];
//////////////////////////////////////////////////
endmodule
| 7.848626 |
module audio_driver (
clk,
rst_n,
snd_sel,
audio_o
);
input clk;
input rst_n;
input wire [1:0] snd_sel;
output reg audio_o;
reg [14:0] timer_1ms;
reg msec;
reg [ 3:0] cycle_cnt;
reg [3:0] t1, t2, t3, t4;
reg [3:0] on_time, off_time;
always @(posedge clk) begin
if (!rst_n) begin
timer_1ms <= 15999;
end else begin
timer_1ms <= (timer_1ms == 0) ? 15999 : timer_1ms - 1;
end
end
always @(posedge clk) begin
if (!rst_n) begin
msec <= 0;
end else begin
msec <= (timer_1ms == 1) ? 1'b1 : 1'b0;
end
end
reg [1:0] snd;
reg [3:0] state;
always @(posedge clk) begin
if (!rst_n) begin
snd <= 0;
t1 <= 0;
t2 <= 0;
t3 <= 0;
t4 <= 0;
audio_o <= 0;
cycle_cnt <= 0;
on_time <= 0;
off_time <= 0;
state <= 0;
end else begin
if (snd_sel != 0 && state == 0) begin
cycle_cnt <= 10;
state <= 1;
case (snd_sel)
0: begin //Nothing
t1 <= 0;
t2 <= 0;
t3 <= 0;
t4 <= 0;
end
1: begin //Player missed
on_time <= 3;
//t1 <= 4; t2 <= 2;
//t3 <= 1; t4 <= 11;
t1 <= 3;
t2 <= 1;
t3 <= 0;
t4 <= 10;
end
2: begin //Ball Bounce
on_time <= 3;
t1 <= 3;
t2 <= 1;
t3 <= 0;
t4 <= 0;
end
3: begin //Ball Hit
on_time <= 0;
t1 <= 0;
t2 <= 2;
t3 <= 2;
t4 <= 2;
end
endcase
end else begin
if (msec == 1) begin
case (state)
1: begin
audio_o <= 1'b1;
on_time <= (on_time == 0) ? 0 : on_time - 1;
if (on_time == 0) begin
state <= 2;
off_time <= t2;
end
end
2: begin
audio_o <= 1'b0;
off_time <= (off_time == 0) ? 0 : off_time - 1;
if (off_time == 0) begin
cycle_cnt <= (cycle_cnt == 0) ? 0 : cycle_cnt - 1;
if (cycle_cnt == 0) begin
state <= 3;
on_time <= t3;
cycle_cnt <= 10;
end else begin
state <= 1;
on_time <= t1;
end
end
end
3: begin
audio_o <= 1'b1;
on_time <= (on_time == 0) ? 0 : on_time - 1;
if (on_time == 0) begin
state <= 4;
off_time <= t4;
end
end
4: begin
audio_o <= 1'b0;
off_time <= (off_time == 0) ? 0 : off_time - 1;
if (off_time == 0) begin
cycle_cnt <= (cycle_cnt == 0) ? 0 : cycle_cnt - 1;
if (cycle_cnt == 0) begin
state <= 0;
on_time <= 0;
off_time <= 0;
end else begin
state <= 3;
on_time <= t3;
end
end
end
endcase
end //if(msec==1)
end //if(snd_sel!=0)
end //if(!rst_n)
end
endmodule
| 7.033101 |
module audio_echo_effect #(
parameter audio_width = 16,
delay_samples = 1024
) (
input wire reset,
input wire clk,
input wire i_valid,
output wire i_ready,
input wire i_is_left,
input wire [audio_width-1:0] i_audio,
output wire o_valid,
input wire o_ready,
output wire o_is_left,
output wire [audio_width-1:0] o_audio
);
wire parallelizer_valid;
wire parallelizer_ready;
wire [audio_width-1:0] parallelizer_left;
wire [audio_width-1:0] parallelizer_right;
stereo_audio_parallelizer #(
.audio_width(audio_width)
) parallelizer_ (
.reset(reset),
.clk(clk),
.i_valid(i_valid),
.i_ready(i_ready),
.i_is_left(i_is_left),
.i_audio(i_audio),
.o_valid(parallelizer_valid),
.o_ready(parallelizer_ready),
.o_left(parallelizer_left),
.o_right(parallelizer_right)
);
wire processor_valid;
wire processor_ready;
wire [audio_width-1:0] processor_left;
wire [audio_width-1:0] processor_right;
sample_processor #(
.audio_width (audio_width),
.delay_samples(delay_samples)
) processor_ (
.reset(reset),
.clk(clk),
.i_valid(parallelizer_valid),
.i_ready(parallelizer_ready),
.i_left(parallelizer_left),
.i_right(parallelizer_right),
.o_valid(processor_valid),
.o_ready(processor_ready),
.o_left(processor_left),
.o_right(processor_right)
);
wire serializer_valid;
wire serializer_ready;
wire serializer_is_left;
wire [audio_width-1:0] serializer_audio;
stereo_audio_serializer #(
.audio_width(audio_width)
) stereo_audio_serializer_ (
.reset(reset),
.clk(clk),
.i_valid(processor_valid),
.i_ready(processor_ready),
.i_left(processor_left),
.i_right(processor_right),
.o_valid(o_valid),
.o_ready(o_ready),
.o_is_left(o_is_left),
.o_audio(o_audio)
);
endmodule
| 8.977306 |
module audio_echo_effect_top (
input wire sclk,
input wire lrclk,
input wire sdin,
input wire clk256,
input wire nreset,
output wire spdif
);
localparam audio_width = 16;
localparam delay_samples = 4096;
GSR GST_INST (.GSR_N(nreset));
wire reset = !nreset;
wire clk;
OSCA #(
.HF_OSC_EN ("ENABLED"),
.HF_CLK_DIV("10")
) OSC_INST (
.HFOUTEN (1'b1),
.HFSDSCEN(1'b0),
.HFCLKOUT(clk)
);
// Decoder
wire decoder_valid;
wire decoder_ready;
wire decoder_is_left;
wire [audio_width-1:0] decoder_audio;
wire decoder_is_error;
serial_audio_decoder #(
.audio_width(audio_width)
) decoder_ (
.sclk(sclk),
.reset(reset),
.lrclk(lrclk),
.sdin(sdin),
.is_i2s(1'b1),
.lrclk_polarity(1'b0),
.is_error(decoder_is_error),
.o_valid(decoder_valid),
.o_ready(decoder_ready),
.o_is_left(decoder_is_left),
.o_audio(decoder_audio)
);
wire reset_with_error = reset | decoder_is_error;
// Synchronize sclk to clk domain
wire decoder_sync_ready;
wire decoder_sync_valid;
wire decoder_sync_is_left;
wire [audio_width-1:0] decoder_sync_audio;
dual_clock_buffer #(
.width(audio_width + 1)
) decoder_sync_ (
.reset (reset_with_error),
.i_clk (sclk),
.i_valid(decoder_valid),
.i_ready(decoder_ready),
.i_data ({decoder_is_left, decoder_audio}),
.o_clk (clk),
.o_valid(decoder_sync_valid),
.o_ready(decoder_sync_ready),
.o_data ({decoder_sync_is_left, decoder_sync_audio})
);
// Process (echo)
wire echo_valid;
wire echo_ready;
wire echo_is_left;
wire [audio_width-1:0] echo_audio;
audio_echo_effect #(
.audio_width (audio_width),
.delay_samples(delay_samples)
) echo_ (
.reset(reset_with_error),
.clk(clk),
.i_valid(decoder_sync_valid),
.i_ready(decoder_sync_ready),
.i_is_left(decoder_sync_is_left),
.i_audio(decoder_sync_audio),
.o_valid(echo_valid),
.o_ready(echo_ready),
.o_is_left(echo_is_left),
.o_audio(echo_audio)
);
spdif_audio_encoder #(
.audio_width(audio_width)
) encoder_ (
.reset(reset_with_error),
.clk(clk),
.clk256(clk256),
.i_valid(echo_valid),
.i_ready(echo_ready),
.i_is_left(echo_is_left),
.i_audio(echo_audio),
.spdif(spdif)
);
endmodule
| 8.977306 |
module audio_echo_processor_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 1; // 44.1KHz * 32
localparam audio_width = 16;
initial begin
$dumpfile("audio_echo_processor_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
end
end
reg reset;
reg i_valid;
wire i_ready;
reg [audio_width-1:0] i_left;
reg [audio_width-1:0] i_right;
wire o_valid;
reg o_ready;
wire [audio_width-1:0] o_left;
wire [audio_width-1:0] o_right;
audio_echo_processor #(
.audio_width (16),
.delay_samples(4)
) processor_ (
.reset(reset),
.clk(clk),
.i_valid(i_valid),
.i_ready(i_ready),
.i_left(i_left),
.i_right(i_right),
.o_valid(o_valid),
.o_ready(o_ready),
.o_left(o_left),
.o_right(o_right)
);
always @(posedge clk or reset) begin
if (reset) begin
end else begin
if (o_valid) begin
$write("l = %08h, r = %08h\n", o_left, o_right);
end
end
end
task out_data(input [audio_width-1:0] left, input [audio_width-1:0] right);
begin
i_valid <= 1'b1;
i_left <= left;
i_right <= right;
wait (i_ready) @(posedge clk);
i_valid <= 1'b0;
@(posedge clk);
end
endtask
initial begin
reset = 1;
i_valid = 0;
o_ready = 1;
i_left = 0;
i_right = 0;
repeat (2) @(posedge clk) reset = 1'b1;
repeat (2) @(posedge clk) reset = 1'b0;
out_data(16'hC000, 16'h1100);
out_data(16'h2000, 16'h2100);
out_data(16'h3000, 16'h3100);
out_data(16'h4000, 16'h4100);
out_data(16'hE001, 16'h0101);
out_data(16'h0002, 16'h0102);
out_data(16'h0003, 16'h0103);
out_data(16'h0004, 16'h0104);
out_data(16'h0005, 16'h0105);
out_data(16'h0006, 16'h0106);
out_data(16'h0007, 16'h0107);
out_data(16'h0008, 16'h0108);
repeat (16) @(posedge clk);
$finish;
end
endmodule
| 6.780136 |
module audio_equalizer (
CLOCK_50,
KEY,
I2C_SCLK,
I2C_SDAT,
AUD_XCK,
AUD_DACLRCK,
AUD_ADCLRCK,
AUD_BCLK,
AUD_ADCDAT,
AUD_DACDAT
);
input CLOCK_50;
input KEY;
// I2C Audio/Video config interface
output I2C_SCLK;
inout I2C_SDAT;
// Audio CODEC
output AUD_XCK;
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
input AUD_ADCDAT;
output AUD_DACDAT;
// Local wires.
wire read_ready, write_ready, read, write;
wire [23:0] readdata_left, readdata_right;
wire [23:0] writedata_left, writedata_right;
wire reset = ~KEY;
assign writedata_left = (write) ? readdata_left : 24'b0;
assign writedata_right = (write) ? readdata_right : 24'b0;
assign read = (read_ready) ? 1'b1 : 1'b0;
assign write = (write_ready) ? 1'b1 : 1'b0;
/////////////////////////////////////////////////////////////////////////////////
// Audio CODEC interface.
//
// The interface consists of the following wires:
// read_ready, write_ready - CODEC ready for read/write operation
// readdata_left, readdata_right - left and right channel data from the CODEC
// read - send data from the CODEC (both channels)
// writedata_left, writedata_right - left and right channel data to the CODEC
// write - send data to the CODEC (both channels)
// AUD_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio CODEC
// I2C_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio/Video Config module
/////////////////////////////////////////////////////////////////////////////////
clock_generator my_clock_gen (
// inputs
CLOCK_50,
reset,
// outputs
AUD_XCK
);
audio_and_video_config cfg (
// Inputs
CLOCK_50,
reset,
// Bidirectionals
I2C_SDAT,
I2C_SCLK
);
audio_codec codec (
// Inputs
CLOCK_50,
reset,
read,
write,
writedata_left,
writedata_right,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
read_ready,
write_ready,
readdata_left,
readdata_right,
AUD_DACDAT
);
endmodule
| 7.622664 |
module int2fp (
fp_out,
int_in,
scale_in
);
input signed [9:0] int_in;
input signed [7:0] scale_in;
output wire [17:0] fp_out;
wire [9:0] abs_int;
reg sign;
reg [8:0] mout; // mantissa
reg [7:0] eout; // exponent
reg [7:0] num_zeros; // count leading zeros in input integer
// get absolute value of int_in
assign abs_int = (int_in[9]) ? (~int_in) + 10'd1 : int_in;
// build output
assign fp_out = {sign, eout, mout};
// detect leading zeros of absolute value
// detect leading zeros
// normalize and form exponent including leading zero shift and scaling
always @(*) begin
if (abs_int[8:0] == 0) begin // zero value
eout = 0;
mout = 0;
sign = 0;
num_zeros = 8'd0;
end else // not zero
begin
casex (abs_int[8:0])
9'b1xxxxxxxx: num_zeros = 8'd0;
9'b01xxxxxxx: num_zeros = 8'd1;
9'b001xxxxxx: num_zeros = 8'd2;
9'b0001xxxxx: num_zeros = 8'd3;
9'b00001xxxx: num_zeros = 8'd4;
9'b000001xxx: num_zeros = 8'd5;
9'b0000001xx: num_zeros = 8'd6;
9'b00000001x: num_zeros = 8'd7;
9'b000000001: num_zeros = 8'd8;
default: num_zeros = 8'd9;
endcase
mout = abs_int[8:0] << num_zeros;
eout = scale_in + (8'h89 - num_zeros); // h80 is offset, h09 normalizes
sign = int_in[9];
end // if int_in!=0
end // always @
endmodule
| 7.895551 |
module fp2int (
int_out,
fp_in,
scale_in
);
output signed [9:0] int_out;
input signed [7:0] scale_in;
input wire [17:0] fp_in;
wire [9:0] abs_int;
wire sign;
wire [8:0] m_in; // mantissa
wire [7:0] e_in; // exponent
//reg [7:0] num_zeros ; // count leading zeros in input integer
assign sign = (m_in[8]) ? fp_in[17] : 1'h0;
assign m_in = fp_in[8:0];
assign e_in = fp_in[16:9];
//
assign abs_int = (e_in > 8'h80) ? (m_in >> (8'h89 - e_in)) : 10'd0;
//assign int_out = (m_in[8])? {sign, (sign? (~abs_int)+9'd1 : abs_int)} : 10'd0 ;
assign int_out = (sign ? (~abs_int) + 10'd1 : abs_int);
//assign int_out = {sign, sign? (~abs_int)+9'd1 : abs_int} ;
endmodule
| 7.886289 |
module HexDigit (
segs,
num
);
input [3:0] num; //the hex digit to be displayed
output [6:0] segs; //actual LED segments
reg [6:0] segs;
always @(num) begin
case (num)
4'h0: segs = 7'b1000000;
4'h1: segs = 7'b1111001;
4'h2: segs = 7'b0100100;
4'h3: segs = 7'b0110000;
4'h4: segs = 7'b0011001;
4'h5: segs = 7'b0010010;
4'h6: segs = 7'b0000010;
4'h7: segs = 7'b1111000;
4'h8: segs = 7'b0000000;
4'h9: segs = 7'b0010000;
4'ha: segs = 7'b0001000;
4'hb: segs = 7'b0000011;
4'hc: segs = 7'b1000110;
4'hd: segs = 7'b0100001;
4'he: segs = 7'b0000110;
4'hf: segs = 7'b0001110;
default segs = 7'b1111111;
endcase
end
endmodule
| 7.890881 |
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