code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module asyn_128_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [92:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [92:0] q = sub_wire0[92:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 128, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 93,
dcfifo_component.lpm_widthu = 7, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 6.625995 |
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [ 7:0] sub_wire1;
wire [133:0] q = sub_wire0[133:0];
wire [ 7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.wrusedw(sub_wire1),
.rdempty(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull()
);
defparam dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 7.068635 |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [138:0] sub_wire0;
wire [ 7:0] sub_wire1;
wire [138:0] q = sub_wire0[138:0];
wire [ 7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.wrusedw(sub_wire1),
.rdempty(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull()
);
defparam dcfifo_component.intended_device_family = "Arria II GX", dcfifo_component.lpm_numwords =
256, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 139, dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.909672 |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.909672 |
module asyn_256_64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw
);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output [7:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire [63:0] q = sub_wire0[63:0];
wire rdempty = sub_wire1;
wire [7:0] rdusedw = sub_wire2[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.rdfull(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 64,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 6.699918 |
module asyn_32_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [92:0] sub_wire0;
wire sub_wire1;
wire [92:0] q = sub_wire0[92:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 32, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 93,
dcfifo_component.lpm_widthu = 5, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 6.538429 |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [5:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [5:0] sub_wire2;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
wire [5:0] rdusedw = sub_wire2[5:0];
dcfifo dcfifo_component (
.rdclk(rdclk),
.wrclk(wrclk),
.wrreq(wrreq),
.aclr(aclr),
.data(data),
.rdreq(rdreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.rdfull(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Arria II GX", dcfifo_component.lpm_numwords =
64, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1, dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.598485 |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.598485 |
module asyn_bridge_top #(
parameter ADDR_WD = 32,
parameter DATA_WD = 32,
parameter STRB_WD = 4,
parameter PROT_WD = 3
) (
input a_pclk,
input a_prst_n,
input a_psel,
input a_penable,
input a_pwrite,
input [ADDR_WD-1 : 0] a_paddr,
input [DATA_WD-1 : 0] a_pwdata,
input [PROT_WD-1 : 0] a_pprot,
input [STRB_WD-1 : 0] a_pstrb,
output [DATA_WD-1 : 0] a_prdata,
output a_pready,
input b_pclk,
input b_prst_n,
output b_psel,
output b_penable,
output b_pwrite,
output [ADDR_WD-1 : 0] b_paddr,
output [DATA_WD-1 : 0] b_pwdata,
output [PROT_WD-1 : 0] b_pprot,
output [STRB_WD-1 : 0] b_pstrb,
input [DATA_WD-1 : 0] b_prdata,
input b_pready
);
wire a_apb_req;
wire write;
wire [ADDR_WD-1 : 0] addr;
wire [DATA_WD-1 : 0] wdata;
wire [PROT_WD-1 : 0] prot;
wire [STRB_WD-1 : 0] strb;
wire b_ready_req;
wire [DATA_WD-1 : 0] rdata;
high_frequency_apb #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) high_frequency (
.a_pclk(a_pclk),
.a_prst_n(a_prst_n),
.a_psel(a_psel),
.a_penable(a_penable),
.a_pwrite(a_pwrite),
.a_paddr(a_paddr),
.a_pwdata(a_pwdata),
.a_pprot(a_pprot),
.a_pstrb(a_pstrb),
.a_prdata(a_prdata),
.a_pready(a_pready),
.a_apb_req(a_apb_req),
.write(write),
.addr(addr),
.wdata(wdata),
.prot(prot),
.strb(strb),
.b_ready_req(b_ready_req),
.rdata(rdata)
);
low_frequency_apb #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) low_frequency (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(b_psel),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(b_prdata),
.b_pready(b_pready),
.a_apb_req(a_apb_req),
.write(write),
.addr(addr),
.wdata(wdata),
.prot(prot),
.strb(strb),
.b_ready_req(b_ready_req),
.rdata(rdata)
);
endmodule
| 8.468535 |
module asyn_comp #(
parameter ADDR_WIDTH = 4
) (
input wire rst_n,
output wire asyn_full,
input wire [ADDR_WIDTH-1 : 0] w_ptr,
output wire asyn_empty,
input wire [ADDR_WIDTH-1 : 0] r_ptr
);
wire dirset;
wire dirclr;
assign dirset = (w_ptr[ADDR_WIDTH-1] ^ r_ptr[ADDR_WIDTH-2]) & (~(w_ptr[ADDR_WIDTH-2] ^ r_ptr[ADDR_WIDTH-1]));
assign dirclr = (~(w_ptr[ADDR_WIDTH-1] ^ r_ptr[ADDR_WIDTH-2])) & (w_ptr[ADDR_WIDTH-2] ^ r_ptr[ADDR_WIDTH-1]);
wire direction;
assign direction = ~((~(dirset | direction)) | dirclr | (~rst_n));
assign asyn_empty = ~((w_ptr == r_ptr) && (direction == 1'b0));
assign asyn_full = ~((w_ptr == r_ptr) && (direction == 1'b1));
endmodule
| 8.482329 |
module asyn_dff (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 6.700381 |
module asyn_dff_err_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 7.451812 |
module asyn_dff_err_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff_err_setup dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Generates a reset signal and the rising edge is effective
//
initial begin
t_rst = 0;
#10;
t_rst = 1;
#20;
t_rst = 0;
end
//
// Control signal
//
initial begin
t_d = 1;
#20 t_d = 0;
#40 t_d = 1;
#30 t_d = 0;
#30 t_d = 1;
#30 t_d = 0;
#30 t_d = 1;
#30 $finish;
end
endmodule
| 7.451812 |
module asyn_dff_good_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 6.5815 |
module asyn_dff_good_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Generates a reset signal and the rising edge is effective
//
initial begin
t_rst = 0;
#10;
t_rst = 1;
#20;
t_rst = 0;
end
//
// Control signal
//
initial begin
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
$finish;
/*
@( negedge t_clk);
t_d = 0;
@( negedge t_clk);
t_d = 1;
@( negedge t_clk);
t_d = 0;
@( negedge t_clk);
t_d = 1;
@( negedge t_clk);
t_d = 0;
@( negedge t_clk);
t_d = 1;
@( negedge t_clk);
$finish;
*/
end
endmodule
| 6.5815 |
module asyn_dff_ok_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 7.351348 |
module asyn_dff_ok_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff_ok_setup dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Generates a reset signal and the rising edge is effective
//
initial begin
t_rst = 0;
#10;
t_rst = 1;
#20;
t_rst = 0;
end
//
// Control signal
//
initial begin
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
t_d = 0;
@(posedge t_clk) #1;
t_d = 1;
@(posedge t_clk) #1;
$finish;
end
endmodule
| 7.351348 |
module asyn_dff_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
//
// Asynchronous DFF
//
asyn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Generates a reset signal and the rising edge is effective
//
initial begin
t_rst = 0;
#10;
t_rst = 1;
#20;
t_rst = 0;
end
//
// Control signal
//
initial begin
t_d = 1;
#25 t_d = 0;
#15 t_d = 1;
#25 t_d = 0;
#25 t_d = 1;
#25 t_d = 0;
#30 t_d = 1;
#20 $finish;
end
endmodule
| 7.014844 |
module asyn_dual_8x16ram (
d_out,
d_in,
clear,
wr_clk,
rd_clk,
we,
re,
wr_addr,
rd_addr
);
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
output reg [DATA_WIDTH-1:0] d_out;
input [DATA_WIDTH-1:0] d_in;
input [DATA_ADDR-1:0] wr_addr, rd_addr;
input clear, wr_clk, rd_clk, we, re;
reg [DATA_WIDTH-1:0] ram[0:DATA_DEPTH-1];
integer i;
// write operation
always @(posedge wr_clk, posedge clear) begin
if (clear == 1) begin
for (i = 0; i < DATA_DEPTH; i = i + 1) ram[i] <= 0;
end else if (we == 1) ram[wr_addr] <= d_in;
end
//read operation
always @(posedge rd_clk, posedge clear) begin
if (clear == 1) d_out <= 16'h0000;
else if (re == 1) begin
d_out <= ram[rd_addr];
end
end
endmodule
| 7.537807 |
module asyn_dual_8x16ram_tb ();
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
reg [DATA_WIDTH-1:0] d_in;
reg [DATA_ADDR-1:0] wr_addr, rd_addr;
reg clear, wr_clk, rd_clk, we, re;
wire [DATA_WIDTH-1:0] d_out;
asyn_dual_8x16ram DUT (
d_out,
d_in,
clear,
wr_clk,
rd_clk,
we,
re,
wr_addr,
rd_addr
);
//write clock t=10
always begin
wr_clk = 1'b0;
forever #5 wr_clk = ~wr_clk;
end
//read clock t=20
always begin
rd_clk = 1'b0;
forever #10 rd_clk = ~rd_clk;
end
task initialize;
begin
d_in = 16'h0000;
{we, re} = 2'b00;
{wr_addr, rd_addr} = 6'b000000;
end
endtask
task clearip;
begin
clear = 1'b1;
#20;
clear = 1'b0;
end
endtask
task write(input [DATA_WIDTH-1:0] wd, input [DATA_ADDR-1:0] wa);
begin
@(negedge wr_clk) we = 1'b1;
d_in <= wd;
wr_addr <= wa;
end
endtask
task read(input [DATA_ADDR-1:0] ra);
begin
@(negedge rd_clk) re = 1'b1;
rd_addr <= ra;
end
endtask
initial begin
initialize;
clearip;
write(16'h1111, 3'b111);
#10;
read(3'b111);
#10;
write(16'hFFFF, 3'b100);
#10;
read(3'b100);
write(16'h1010, 3'b101);
#10;
read(3'b101);
clearip;
end
initial begin
$monitor(
"clear=%b ,wr_clk=%b ,rd_clk=%b, we=%b, wr_addr=%d, re=%b, rd_addr=%d, d_in=%d, d_out=%d ",
clear, wr_clk, rd_clk, we, wr_addr, re, rd_addr, d_in, d_out);
end
initial begin
#300 $finish;
end
endmodule
| 7.537807 |
module asyn_fifo_tb ();
parameter addr_size = 3, word_width = 8;
reg r_clk;
reg w_clk;
// read and write command
reg rd;
reg wr;
reg reset_n;
reg [word_width-1:0] data_in;
wire [word_width-1:0] data_out;
wire full;
wire empty;
asyn_fifo_top #(
.addr_size (addr_size),
.word_width(word_width)
) fifo_tb (
.r_clk(r_clk),
.w_clk(w_clk),
.rd(rd),
.wr(wr),
.reset_n(reset_n),
.data_in(data_in),
.data_out(data_out),
.full(full),
.empty(empty)
);
// initial condition
initial begin
r_clk = 1'b0;
w_clk = 1'b0;
rd = 1'b0;
wr = 1'b0;
data_in = 'd104;
end
// generating the clocks
always #8 r_clk = ~r_clk;
always #3 w_clk = ~w_clk; //writing clock is faster
//reset block
initial begin
reset_n = 1'b1;
#1 reset_n = 1'b0;
#1 reset_n = 1'b1;
end
// testing
initial begin // it's empty at the begin
// write untill it's full
#2.5
if (full != 1) begin
data_in = 'd104;
wr = 1'b1;
end //st word h
#3.5
if (full == 0) begin
data_in = 'd100;
wr = 1'b0;
end // shouldn't write d
#6
if (full == 0) begin
wr = 1'b1;
data_in = 'd105;
end
//2nd word i
#6 if (full == 0) data_in = 'd95;
//third _
#6 if (full == 0) data_in = 'd116;
//forth t
#6 if (full == 0) data_in = 'd104;
//fifh h
#6 if (full == 0) data_in = 'd101;
//sixth e
#6 if (full == 0) data_in = 'd114;
//sevinth r
#6 if (full == 0) data_in = 'd101;
//last word it should indicate full here e
wait (full);
wr = 1'b0;
/// reading
// will begin two clock later cause of syncroizing
#2 rd = 1'b1; //will read until it's empty
//after 2 cycle of
wait (empty);
// reading and writing simultaneously
//it's reading cause rd is one
#6
if (full == 0) begin
data_in = 'd79;
wr = 1'b1;
end
#6 if (full == 0) data_in = 'd114;
#6 if (full == 0) data_in = 'd105;
#6 if (full == 0) data_in = 'd103;
#6 if (full == 0) data_in = 'd105;
#6 if (full == 0) data_in = 'd110;
#6 if (full == 0) data_in = 'd97;
#6 if (full == 0) data_in = 'd108;
#6 if (full == 0) data_in = 'd95;
#6 if (full == 0) data_in = 'd70;
#6 if (full == 0) data_in = 'd73;
#6 if (full == 0) data_in = 'd70;
#6 if (full == 0) data_in = 'd73;
#6 if (full == 0) data_in = 'd73;
#2 wr = 1'b0;
wait (empty);
#5 $finish;
end
endmodule
| 8.204821 |
module asyn_fifo_top #(
parameter addr_size = 3,
word_width = 8
) (
input r_clk,
input w_clk,
// read and write command
input rd,
input wr,
input reset_n,
input [word_width-1:0] data_in,
output [word_width-1:0] data_out,
output full,
output empty
);
//declaration needed
wire [addr_size-1:0] addr_r, addr_w;
wire we_enable, rd_enable;
wire [addr_size:0] ptr_r;
wire [addr_size:0] ptr_w;
//initialize control unit
fifo_control_unit #(
.addr_size(addr_size)
) fifo_ctrl (
.reset_n(reset_n),
.w_clk(w_clk),
.r_clk(r_clk),
.rd(rd),
.wr(wr),
.addr_r(addr_r),
.addr_w(addr_w),
.full(full),
.empty(empty),
.we_enable(we_enable),
.rd_enable(rd_enable)
);
// initialize memory register
reg_memory_file #(addr_size, word_width) fifo_memory (
.we_s(we_enable),
.clk(w_clk),
.addr_r(addr_r),
.addr_w(addr_w),
.data_w(data_in),
.data_r(data_out)
);
endmodule
| 8.621526 |
module Asyn_fifo_v1 #(
parameter DATA_SIZE = 8,
parameter ARRAY_SIZE = 4
) (
output [DATA_SIZE-1:0] rdata,
output wfull,
output rempty,
input [DATA_SIZE-1:0] wdata,
input winc,
wclk,
wrst_n,
input rinc,
rclk,
rrst_n
);
wire [ARRAY_SIZE-1:0] waddr, raddr;
wire [ARRAY_SIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w sync_r2w (
.wq2_rptr(wq2_rptr),
.rptr(rptr),
.wclk(wclk),
.wrst_n(wrst_n)
);
sync_w2r sync_w2r (
.rq2_wptr(rq2_wptr),
.wptr(wptr),
.rclk(rclk),
.rrst_n(rrst_n)
);
fifomem #(DATA_SIZE, ARRAY_SIZE) fifomem (
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken(winc),
.wfull (wfull),
.wclk (wclk)
);
rptr_empty #(ARRAY_SIZE) rptr_empty (
.rempty(rempty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n)
);
wptr_full #(ARRAY_SIZE) wptr_full (
.wfull(wfull),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n)
);
endmodule
| 7.45862 |
module asyn_fifo_v2 #(
parameter DATA_WIDTH = 16,
ADDR_WIDTH = 4
) (
input wire reset_l,
input wire wr_clk, //дʱ
input wire wr_en, //дʹ
output wire full, //asyn_full == 0 ʾ 1ʾ
input wire [15:0] write_data, //д
input wire rd_clk, //ʱ
input wire rd_en, //ʹ
output wire empty, //͵ƽʹasyn_empty == 0 ʾգ1ʾǿ
output wire [15:0] read_data // w_req
);
wire [ADDR_WIDTH-1:0] wr_addr;
wire [ADDR_WIDTH-1:0] rd_addr;
dp_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(2 ** ADDR_WIDTH)
) U1_dp_ram (
.wr_clk (wr_clk),
.write_data(write_data),
.wr_addr (wr_addr),
.rd_clk (rd_clk),
.read_data(read_data),
.rd_addr (rd_addr)
);
asyn_comp #(
.ADDR_WIDTH(ADDR_WIDTH)
) U2_asyn_comp (
.rst_n(reset_l),
.asyn_full(full),
.w_ptr (wr_addr),
.asyn_empty(empty),
.r_ptr (rd_addr)
);
write_ptr #(
.ADDR_WIDTH(ADDR_WIDTH)
) U3_write_ptr (
.reset_l(reset_l),
.wr_addr (wr_addr),
.wr_clk (wr_clk),
.write_en(wr_en)
);
read_ptr #(
.ADDR_WIDTH(ADDR_WIDTH)
) U4_read_ptr (
.reset_l(reset_l),
.rd_addr(rd_addr),
.rd_en (rd_en),
.rd_clk (rd_clk)
);
endmodule
| 8.554777 |
module async_fifo_tb;
reg rst;
reg wr_clk;
reg wr_en;
reg [15:0] din;
reg rd_clk;
reg rd_en;
wire valid;
wire [15:0] dout;
wire empty;
wire full;
reg [15:0] test_cnt;
reg err;
async_fifo #(
.WIDTH(16),
.DEPTH(5)
) async_fifo_u (
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.din(din),
.rd_clk(rd_clk),
.rd_en(rd_en),
.valid(valid),
.dout(dout),
.empty(empty),
.full(full)
);
//clk and rst
initial begin
wr_clk = 1'b0;
forever begin
wr_clk = 1'b0;
#(`WR_CLK / 2);
wr_clk = 1'b1;
#(`WR_CLK / 2);
end
end
initial begin
rd_clk = 1'b0;
forever begin
rd_clk = 1'b0;
#(`RD_CLK / 2);
rd_clk = 1'b1;
#(`RD_CLK / 2);
end
end
initial begin
rst = 1'b1;
#500;
rst = 1'b0;
end
//write
initial begin
wr_en = 1'b0;
while (rst !== 1'b0) #0.01;
#100;
repeat (32) @(posedge wr_clk) wr_en <= 1'b1;
@(posedge wr_clk) wr_en <= 1'b0;
#1000 forever @(posedge wr_clk) wr_en <= ~full;
end
always @(posedge wr_clk or posedge rst) begin
if (rst) din <= 'd0;
else if (wr_en && !full) din <= din + 1'd1;
else;
end
//read and check
initial begin
rd_en = 1'b0;
while (rst !== 1'b0) #0.01;
#100;
#500 repeat (32) @(posedge rd_clk) rd_en <= 1'b1;
@(posedge rd_clk) rd_en <= 1'b0;
#500 forever @(posedge rd_clk) rd_en <= ~empty;
end
always @(posedge rd_clk or posedge rst) begin
if (rst) err <= 1'b0;
else if (valid)
if (test_cnt != dout) err <= 1'b1;
else;
else;
end
always @(posedge rd_clk or posedge rst) begin
if (rst) test_cnt <= 16'd0;
else if (valid) test_cnt <= test_cnt + 1'd1;
else;
end
initial begin
#20000 $stop;
end
endmodule
| 6.523155 |
module ASYN_RESET (
input clk,
input rst_n,
input in,
output reg out
);
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0) out <= 1'b0;
else out <= in;
endmodule
| 7.287386 |
module ASYN_RESET_SYN_RELEASE_T;
reg clk;
reg rst_n;
wire rst_n_syn;
always #5 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b1;
#2 rst_n = 1'b0;
#15 rst_n = 1'b1;
#25 rst_n = 1'b0;
#25 $stop;
end
ASYN_RESET_SYN_RELEASE ASYN_RESET_SYN_RELEASE_T (
.clk(clk),
.rst_n(rst_n),
.rst_n_syn(rst_n_syn)
);
endmodule
| 7.563577 |
module ASYN_RESET_SYN_RELEASE (
input clk,
input rst_n,
output reg rst_n_syn
);
reg rst_n_d1;
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0) {rst_n_syn, rst_n_d1} <= 2'b00;
else {rst_n_syn, rst_n_d1} <= {rst_n_d1, 1'b1};
endmodule
| 7.563577 |
module asyn_single_8x16ram (
data,
addr_in,
we_in,
en_in
);
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
input we_in, en_in;
input [DATA_ADDR-1:0] addr_in;
inout [DATA_WIDTH-1:0] data;
reg [DATA_WIDTH-1:0] ram[0:DATA_DEPTH-1];
always @(data, we_in, en_in, addr_in) begin
if (we_in && !en_in) ram[addr_in] <= data;
end
assign data = (en_in && !we_in) ? ram[addr_in] : 16'hzz;
endmodule
| 6.707116 |
module asyn_single_8x16ram_tb();
wire [15:0] data;
reg [2:0] addr_in;
reg we_in,en_in;
reg [15:0] tempd;
integer l;
asyn_single_8x16ram DUT(data,addr_in,we_in,en_in);
assign data=(we_in && !en_in) ? tempd : 8'hzz;
task initialize();
begin
we_in=1'b0; en_in=1'b0; tempd=8'h00;
end
endtask
begin
addr_in=i;
tempd=j;
end
endtask
task write();
begin
we_in=1'b1;
en_in=1'b0;
end
endtask
task read();
begin
we_in=1'b0;
en_in=1'b1;
end
endtask
task delay;
begin
#10;
end
endtask
//Process to generate stimulus using for loop
initial
begin
initialize;
delay;
write;
for(l=0;l<8;l=l+1)
begin
stimulus(l,l);
delay;
end
initialize;
delay;
read;
for(l=0;l<8;l=l+1)
begin
stimulus(l,l);
delay;
end
delay;
end
initial begin
$monitor("we_in=%b , en_in=%b , addr_in=%b %d, data=%b %d",we_in,en_in,addr_in,addr_in,data,data);
end
initial begin
#200 $finish;
end
endmodule
| 6.707116 |
module asyn_spram_4x1 (
clk,
addr_0,
addr_1,
d_in,
wr_en,
d_out
);
input wire clk;
input wire addr_0;
input wire addr_1;
input wire d_in;
input wire wr_en;
output wire d_out;
wire [1:0] addr;
reg [3:0] mem;
assign addr = {addr_1, addr_0};
assign d_out = (addr == 2'd0)? mem[0]:
(addr == 2'd1)? mem[1]:
(addr == 2'd2)? mem[2]: mem[3];
always @(posedge clk) begin
if (wr_en) begin
mem[addr] <= d_in;
end
end
endmodule
| 7.132512 |
module asy_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [138:0] sub_wire0;
wire [ 7:0] sub_wire1;
wire [138:0] q = sub_wire0[138:0];
wire [ 7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.wrusedw(sub_wire1),
.rdempty(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull()
);
defparam dcfifo_component.intended_device_family = "Arria II GX", dcfifo_component.lpm_numwords =
256, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 139, dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.563891 |
module asy_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Arria II GX", dcfifo_component.lpm_numwords =
64, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1, dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.77794 |
module Asy_Rst_Syn (
input clk_50m,
input rst_n,
output asy_rst_n
);
//----------------------------------------------
reg [1:0] rst_shift;
always @(posedge clk_50m or negedge rst_n) begin
if (!rst_n) rst_shift[1:0] <= 2'b00;
else rst_shift[1:0] <= {rst_shift[0], 1'b1};
end
assign asy_rst_n = rst_shift[1];
endmodule
| 8.242034 |
module as_reg16b (
input [ 8:0] address,
output [15:0] result
);
reg [15:0] int_reg[511:0];
assign result = int_reg[address];
initial $readmemh("microcode.txt", int_reg);
endmodule
| 6.874577 |
module ata (
input CLK,
input AS,
input RW,
input [23:0] A,
input WAIT,
output [1:0] IDECS,
output IOR,
output IOW,
output DTACK,
output ACCESS
);
/* Timing Diagram
S0 S1 S2 S3 S4 S5 W W S6 S7
__ __ __ __ __ __ __ __ __ __ __ __
CLK | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
_________________ _____________________________
AS \\\_____________________/
_______________ _____________________________
CS \__________________________/
______________________ _____________________________
IOR \___________________/
_____________________________ ___________________________________
IOW \______/
_____________________________ ___________________________________
DTACK \______/
_________________________ ________________________________________
WAIT \_____/
*/
// decode directly from AS and Address Bus.
`ifndef ATARI
wire GAYLE_IDE = ({A[23:15]} != {8'hDA, 1'b0});
`else
wire GAYLE_IDE = ({A[23:16]} != {8'hF0});
`endif
reg ASDLY = 1'b1;
reg ASDLY2 = 1'b1;
reg DTACK_INT = 1'b1;
reg IOR_INT = 1'b1;
reg IOW_INT = 1'b1;
always @(posedge CLK or posedge AS) begin
if (AS == 1'b1) begin
ASDLY <= 1'b1;
ASDLY2 <= 1'b1;
end else begin
ASDLY <= AS;
ASDLY2 <= ASDLY;
end
end
always @(negedge CLK or posedge AS) begin
if (AS == 1'b1) begin
IOR_INT <= 1'b1;
IOW_INT <= 1'b1;
DTACK_INT <= 1'b1;
end else begin
IOR_INT <= ~RW | ASDLY | GAYLE_IDE;
IOW_INT <= RW | ASDLY2 | GAYLE_IDE;
DTACK_INT <= ASDLY | GAYLE_IDE;
end
end
assign IOR = IOR_INT;
assign IOW = IOW_INT;
assign DTACK = DTACK_INT;
`ifndef ATARI
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE};
`else
assign IDECS = A[5] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE};
`endif
assign ACCESS = GAYLE_IDE;
endmodule
| 6.974379 |
module ATAN_ROM - ROM pre-loaded with the arctangent( 2^-i )
Summary
This module implements the arc-tangent lookup-table (a ROM) required
for the sequential CORDIC module. The initialization datafile is located
in folder ../simdata is created by the Matlab program ../matlab/genatanlut.m
Two data files can be used to initialize the lookup-table, depending on
the desired angle units (degrees or radians). The file is set by
the parameter ATANLUT_FILENAME:
"../simdata/atanLUTd.hex": the arctangents in degrees, represented
with 8 integer bits and 24 fractional bits
"../simdata/atanLUT.hex": the arctangents in radians, represented
with 1 integer bit and 31 fractional bits
----------------------------------------------------------------------
Date created: 4 Oct 2019
Author: jca@fe.up.pt
----------------------------------------------------------------------
This Verilog code is property of the University of Porto, Portugal
Its utilization beyond the scope of the course Digital Systems Design
(Projeto de Sistemas Digitais) of the Integrated Master in Electrical
and Computer Engineering requires explicit authorization from the author.
*/
module ATAN_ROM(
input [ 3:0] addr,
output [15:0] data
);
parameter ROMSIZE = 16;
parameter ATANLUT_FILENAME = "../simdata/atanLUTd.hex";
reg [15:0] atanLUT[ 0 : ROMSIZE-1 ];
initial
begin
$readmemh( ATANLUT_FILENAME, atanLUT );
end
assign data = atanLUT[ addr ];
endmodule
| 8.408436 |
module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
data_a,
byteena_a,
wren_b,
data_b,
byteena_b,
q_b,
q_a
);
parameter width_a = 1'd0;
parameter widthad_a = 1'd0;
parameter numwords_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_b = 1'd0;
parameter latency = 1;
parameter init_file = "UNUSED";
parameter width_be_a = 1'd0;
parameter width_be_b = 1'd0;
localparam output_registered = (latency == 1)? "UNREGISTERED" : "CLOCK0";
input clk;
input clken;
input [(widthad_a-1):0] address_a;
output wire [(width_a-1):0] q_a;
wire [(width_a-1):0] q_a_wire;
input [(widthad_b-1):0] address_b;
output wire [(width_b-1):0] q_b;
wire [(width_b-1):0] q_b_wire;
input wren_a;
input [(width_a-1):0] data_a;
input [width_be_a-1:0] byteena_a;
input wren_b;
input [(width_b-1):0] data_b;
input [width_be_b-1:0] byteena_b;
reg clk_wire;
altsyncram altsyncram_component (
.address_a (address_a),
.clock0 (clk_wire),
.clock1 (1'd1),
.clocken0 (clken),
.clocken1 (1'd1),
.clocken2 (1'd1),
.clocken3 (1'd1),
.aclr0 (1'd0),
.aclr1 (1'd0),
.addressstall_a (1'd0),
.eccstatus (),
.rden_a (clken),
.q_a (q_a),
.address_b (address_b),
.addressstall_b (1'd0),
.rden_b (clken),
.q_b (q_b),
.wren_a (wren_a),
.data_a (data_a),
.wren_b (wren_b),
.data_b (data_b),
.byteena_b (byteena_b),
.byteena_a (byteena_a)
);
defparam
altsyncram_component.width_byteena_a = width_be_a,
altsyncram_component.width_byteena_b = width_be_b,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.init_file = init_file,
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.intended_device_family = "CycloneV",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = output_registered,
altsyncram_component.numwords_b = numwords_b,
altsyncram_component.widthad_b = widthad_b,
altsyncram_component.width_b = width_b,
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = output_registered,
altsyncram_component.numwords_a = numwords_a,
altsyncram_component.widthad_a = widthad_a,
altsyncram_component.width_a = width_a;
always @(*) begin
clk_wire = clk;
end
endmodule
| 8.296277 |
module tb;
reg t_a;
reg t_b;
wire t_w, t_x, t_y, t_z;
//instatiate
and1 a1 (
.a(t_a),
.b(t_b),
.w(t_w),
.x(t_x),
.y(t_y),
.z(t_z)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb);
end
initial begin
$monitor(t_a, t_b, t_w, t_x, t_y, t_z); //displays the content of the register
t_a = 1'b0; //1 bit input
t_b = 1'b0;
#10 //time nanosecs
t_a = 1'b0; //1 bit input
t_b = 1'b1;
#10 //time nanosecs
t_a = 1'b1; //1 bit input
t_b = 1'b0;
#10 //time nanosecs
t_a = 1'b1; //1 bit input
t_b = 1'b1;
#10 //time nanosecs
t_a = 0; //inorder to see the last input
t_b = 0;
end
endmodule
| 7.02078 |
module atkState (
input clk
, input game_clk
, input [4:0] direction
, input state
, input [2:0] monster
, output reset
, output [9:0] xPlayer
, output [9:0] yPlayer
, output [6:0] hpPlayer
, output [6:0] hpMonster
, output changeState
);
reg [9:0] xCurrent;
reg [9:0] yCurrent;
reg [6:0] VhpMonster;
reg left_right;
reg stop;
reg prevState;
//reg state = 1;
wire [6:0] damage;
reg [9:0] counterHp;
reg [9:0] counterStop;
reg VChangeState;
assign changeState = VChangeState;
initial begin
xCurrent = 320;
yCurrent = 393;
stop = 0;
left_right = 1; //right
VhpMonster = 100; //min 0 max 100
counterHp = 0;
counterStop = 0;
end
assign xPlayer = xCurrent;
assign yPlayer = yCurrent;
assign hpMonster = VhpMonster;
damageCompute dc (
.game_clk(game_clk),
.xCurrent(xCurrent),
.monster (monster),
.damage (damage)
);
always @(posedge game_clk) begin
if (state) begin
case (direction)
5'b10000: begin
xCurrent = xCurrent; //Spacebar , attack
if ((VhpMonster <= damage) && (!stop)) begin
VhpMonster = 0; //win
end else if ((VhpMonster > damage) && (!stop)) begin
VhpMonster = VhpMonster - damage;
end
stop = 1;
end
endcase
end
//reset hpMonster
if (VhpMonster == 0 && counterHp <= 200) counterHp = (counterHp + 1); //count 0-61
else if (VhpMonster == 0 && counterHp > 200) begin
VhpMonster = 100;
counterHp = 0;
end
//change stop
if (stop == 1 && counterStop <= 200) counterStop = (counterStop + 1); //count 0-91
else if (stop == 1 && counterStop > 200) begin
stop = 0;
counterStop = 0;
end
if (!stop && state) begin
if (left_right == 1)//right
begin
xCurrent <= xCurrent + 1;
if (xCurrent >= 544) begin
left_right = 0; //left
end
end
else if (left_right == 0) //left
begin
xCurrent <= xCurrent - 1;
if (xCurrent <= 96) begin
left_right = 1; //right
end
end
end
end
// always @(posedge game_clk)
// begin
// if (state) begin
// if (!stop)
// begin
// if (left_right == 1)//right
// begin
// xCurrent <= xCurrent+1;
// if (xCurrent >= 544)
// begin
// left_right = 0; //left
// end
// end
// else if (left_right == 0) //left
// begin
// xCurrent <= xCurrent-1;
// if (xCurrent <= 96)
// begin
// left_right = 1; //right
// end
// end
// end
// end
// end
endmodule
| 6.548777 |
module atmega_eep #(
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_DATA_LEN = 8,
parameter EEARH_ADDR = 'h20,
parameter EEARL_ADDR = 'h21,
parameter EEDR_ADDR = 'h22,
parameter EECR_ADDR = 'h23,
parameter EEP_SIZE = 512
) (
input rst_i,
input clk_i,
input [BUS_ADDR_DATA_LEN-1:0] addr_i,
input wr_i,
input rd_i,
input [7:0] bus_i,
output reg [7:0] bus_o,
output int_o,
input int_ack_i,
input [16:0] ext_eep_addr_i,
input [7:0] ext_eep_data_i,
input ext_eep_data_wr_i,
output [7:0] ext_eep_data_o,
input ext_eep_data_rd_i,
input ext_eep_data_en_i,
output reg content_modifyed_o,
output [4:0] debug_o
);
(* ram_style="block" *)
reg [7:0] eep[EEP_SIZE -1 : 0];
reg [7:0] EEARH;
reg [7:0] EEARL;
reg [7:0] EEDR_WRITE;
reg [7:0] EEDR_READ;
reg [7:0] EECR;
reg [2:0] eempe_timeout_cnt;
reg eep_wr;
reg [7:0] dat_to_write;
reg [7:0] read_tmp;
reg int_p;
reg int_n;
integer clear_cnt;
initial begin
for (clear_cnt = 0; clear_cnt < EEP_SIZE; clear_cnt = clear_cnt + 1) begin : CLEAR_EEP
eep[clear_cnt] = 8'h00;
end
end
always @* begin
bus_o = 8'h00;
if (rd_i) begin
case (addr_i)
EEARH_ADDR: bus_o = EEARH;
EEARL_ADDR: bus_o = EEARL;
EEDR_ADDR: bus_o = EEDR_READ;
EECR_ADDR: bus_o = EECR;
endcase
end
end
always @(posedge clk_i) begin
if (rst_i) begin
EEARH <= 8'h00;
EEARL <= 8'h00;
EEDR_READ <= 8'h00;
EEDR_WRITE <= 8'h00;
EECR <= 8'h00;
content_modifyed_o <= 1'b0;
eempe_timeout_cnt <= 3'h0;
int_p <= 1'b0;
int_n <= 1'b0;
dat_to_write <= 1'b0;
eep_wr <= 1'b0;
end else begin
content_modifyed_o <= 1'b0;
eep_wr <= 1'b0;
if (eempe_timeout_cnt) begin
eempe_timeout_cnt <= eempe_timeout_cnt - 1;
end
if (wr_i) begin
case (addr_i)
EEARH_ADDR: EEARH <= bus_i;
EEARL_ADDR: EEARL <= bus_i;
EEDR_ADDR: EEDR_WRITE <= bus_i;
EECR_ADDR: begin
EECR <= bus_i;
if (EECR[2] | bus_i[1]) begin
eempe_timeout_cnt <= 3'h4;
end
end
endcase
end
if ((&EECR[2:1])) begin
if (|eempe_timeout_cnt) begin
case (EECR[5:4])
2'h0, 2'h2: begin
dat_to_write <= ~EEDR_WRITE;
eep_wr <= 1'b1;
end
2'h1: begin
dat_to_write <= 8'h00;
eep_wr <= 1'b1;
end
endcase
end
EECR[2:1] <= 2'b00;
if (int_p == int_n) begin
int_p <= ~int_p;
end
end
if (EECR[0]) begin
EEDR_READ <= ~read_tmp;
EECR[0] <= 1'b0;
end
if (int_ack_i) begin
int_n <= int_p;
end
if (eep_wr) begin
content_modifyed_o <= content_modifyed_o | 1'b1;
end
end
end
always @(posedge clk_i) begin
if (eep_wr) begin
eep[ext_eep_data_en_i ? ext_eep_addr_i : {EEARH, EEARL}] <= ext_eep_data_en_i ? ~ext_eep_data_i : dat_to_write;
end
read_tmp <= eep[ext_eep_data_en_i?ext_eep_addr_i : {EEARH, EEARL}];
end
assign ext_eep_data_o = (ext_eep_data_rd_i & ext_eep_data_en_i) ? ~read_tmp : 8'h00;
assign int_o = EECR[3] ? (int_p ^ int_n) : 1'b0;
endmodule
| 6.706772 |
modules. */
/************************************************************/
`timescale 1ns / 1ps
module atmega_pio # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_DATA_LEN = 8,
parameter PORT_WIDTH = 8,
parameter USE_CLEAR_SET = "FALSE",
parameter PORT_OUT_ADDR = 'h00,
parameter DDR_ADDR = 'h03,
parameter PIN_ADDR = 'h04,
parameter PORT_CLEAR_ADDR = 'h01,
parameter PORT_SET_ADDR = 'h02,
parameter PINMASK = 'hFF,
parameter PULLUP_MASK = 'h0,
parameter PULLDN_MASK = 'h0,
parameter INVERSE_MASK = 'h0,
parameter OUT_ENABLED_MASK = 'hFF,
parameter INITIAL_OUTPUT_VALUE = 'h00,
parameter INITIAL_DIR_VALUE = 'h00
)(
input rst_i,
input clk_i,
input [BUS_ADDR_DATA_LEN-1:0]addr_i,
input wr_i,
input rd_i,
input [PORT_WIDTH - 1:0]bus_i,
output reg [PORT_WIDTH - 1:0]bus_o,
input [PORT_WIDTH - 1:0]io_i,
output [PORT_WIDTH - 1:0]io_o,
output [PORT_WIDTH - 1:0]pio_out_io_connect_o
);
reg [PORT_WIDTH - 1:0]DDR;
reg [PORT_WIDTH - 1:0]PORT;
reg [PORT_WIDTH - 1:0]PIN;
localparam BUS_LEN_SHIFT = PORT_WIDTH > 16 ? 2 : (PORT_WIDTH > 8 ? 1 : 0);
integer cnt_int;
always @ (posedge clk_i)
begin
if(rst_i)
begin
DDR <= INITIAL_DIR_VALUE;
PORT <= INITIAL_OUTPUT_VALUE;
PIN <= 0;
end
else
begin
for (cnt_int = 0; cnt_int < PORT_WIDTH; cnt_int = cnt_int + 1)
begin
if (PINMASK[cnt_int])
begin
PIN[cnt_int] <= io_i[cnt_int];
if(wr_i)
begin
case(addr_i[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT])
DDR_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]: DDR[cnt_int] <= bus_i[cnt_int];
PORT_OUT_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]: PORT[cnt_int] <= bus_i[cnt_int];
PORT_CLEAR_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]:
begin
if(USE_CLEAR_SET == "TRUE")
PORT[cnt_int] <= PORT[cnt_int] & ~bus_i[cnt_int];
end
PORT_SET_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]:
begin
if(USE_CLEAR_SET == "TRUE")
PORT[cnt_int] <= PORT[cnt_int] | bus_i[cnt_int];
end
endcase
end
end
end
end
end
always @ *
begin
for (cnt_int = 0; cnt_int < PORT_WIDTH; cnt_int = cnt_int + 1)
begin
if (PINMASK[cnt_int])
begin
bus_o[cnt_int] = 1'b0;
if(rd_i & ~rst_i)
begin
case(addr_i[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT])
PORT_OUT_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]: bus_o[cnt_int] = PORT[cnt_int];
DDR_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]: bus_o[cnt_int] = DDR[cnt_int];
PIN_ADDR[BUS_ADDR_DATA_LEN-1 : BUS_LEN_SHIFT]: bus_o[cnt_int] = INVERSE_MASK[cnt_int] ? ~PIN[cnt_int] : PIN[cnt_int];
endcase
end
end
else
bus_o[cnt_int] = 1'b0;
end
end
genvar cnt;
generate
for (cnt = 0; cnt < PORT_WIDTH; cnt = cnt + 1)
begin:OUTS_CONNECT
assign pio_out_io_connect_o[cnt] = (PINMASK[cnt] & OUT_ENABLED_MASK[cnt]) ? DDR[cnt] : 1'b0;
end
for (cnt = 0; cnt < PORT_WIDTH; cnt = cnt + 1)
begin:OUTS
if (PINMASK[cnt] & OUT_ENABLED_MASK[cnt])
begin
assign io_o[cnt] = DDR[cnt] ? (INVERSE_MASK[cnt] ? ~PORT[cnt] : PORT[cnt]) : 1'bz;
end
else
begin
assign io_o[cnt] = 1'bz;
end
end
for (cnt = 0; cnt < PORT_WIDTH; cnt = cnt + 1)
begin:PULLUPS
if (PULLUP_MASK[cnt] & PINMASK[cnt])
begin
if (PLATFORM == "XILINX")
begin
PULLUP PULLUP_inst (
.O(io_o[cnt]) // PullUp output (connect directly to top-level port)
);
end
end
end
for (cnt = 0; cnt < PORT_WIDTH; cnt = cnt + 1)
begin:PULLDOWNS
if (PULLDN_MASK[cnt] & PINMASK[cnt])
begin
if (PLATFORM == "XILINX")
begin
PULLDOWN PULLDOWN_inst (
.O(io_o[cnt]) // PullDown output (connect directly to top-level port)
);
end
end
end
endgenerate
endmodule
| 8.338405 |
module rtc #(
parameter PERIOD_STATIC = 0,
parameter CNT_SIZE = 10
) (
input rst_i,
input clk_i,
input clk_cnt_i,
input [CNT_SIZE - 1:0] top_i,
output int_o,
input int_ack_i
);
reg int_rst_int_p;
reg int_rst_int_n;
reg [CNT_SIZE-1:0] CNT;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) int_rst_int_n <= 'h0;
else if (int_ack_i & int_o) int_rst_int_n <= ~int_rst_int_n;
end
always @(posedge clk_cnt_i) begin
if (rst_i) begin
CNT <= 'h00;
int_rst_int_p <= 'h0;
end else begin
if (CNT >= (PERIOD_STATIC != 0 ? PERIOD_STATIC : top_i) - 1) begin
CNT <= 'h0;
if ((PERIOD_STATIC != 0 ? PERIOD_STATIC : top_i)) begin
if (~int_o) begin
int_rst_int_p <= ~int_rst_int_p;
end
end
end else if ((PERIOD_STATIC != 0 ? PERIOD_STATIC : top_i)) begin
CNT <= CNT + 1;
end
end
end
assign int_o = int_rst_int_n ^ int_rst_int_p;
endmodule
| 7.350277 |
module atmega_eep # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_IO_LEN = 16,
parameter EEARH_ADDR = 0,
parameter EEARL_ADDR = 1,
parameter EEDR_ADDR = 2,
parameter EECR_ADDR = 3,
parameter EEP_SIZE = 512
)(
input rst,
input clk,
input [BUS_ADDR_IO_LEN-1:0]addr,
input wr,
input rd,
input [7:0]bus_in,
output reg [7:0]bus_out,
output int,
input int_rst,
input [16:0]ext_load_read_eep_addr,
input [7:0]ext_eep_data_in,
input ext_eep_data_wr,
output [7:0]ext_eep_data_out,
input ext_eep_data_rd,
input ext_eep_data_en,
output reg content_modifyed,
output [4:0]debug
);
(* ram_style="block" *)
reg [7:0]eep[EEP_SIZE -1 : 0];
reg [7:0]EEARH;
reg [7:0]EEARL;
reg [7:0]EEDR_WRITE;
reg [7:0]EEDR_READ;
reg [7:0]EECR;
reg[2:0]eempe_timeout_cnt;
reg eep_wr;
reg [7:0]dat_to_write;
reg [7:0]read_tmp;
reg int_p;
reg int_n;
integer clear_cnt;
initial begin
for(clear_cnt = 0; clear_cnt < EEP_SIZE; clear_cnt = clear_cnt + 1)
begin : CLEAR_EEP
eep[clear_cnt] = 8'h00;
end
end
always @ *
begin
bus_out = 8'h00;
if(rd)
begin
case(addr)
EEARH_ADDR: bus_out = EEARH;
EEARL_ADDR: bus_out = EEARL;
EEDR_ADDR: bus_out = EEDR_READ;
EECR_ADDR: bus_out = EECR;
endcase
end
end
always @ (posedge clk)
begin
if(rst)
begin
EEARH <= 8'h00;
EEARL <= 8'h00;
EEDR_READ <= 8'h00;
EEDR_WRITE <= 8'h00;
EECR <= 8'h00;
content_modifyed <= 1'b0;
eempe_timeout_cnt <= 3'h0;
int_p <= 1'b0;
int_n <= 1'b0;
dat_to_write <= 1'b0;
eep_wr <= 1'b0;
end
else
begin
eep_wr <= 1'b0;
if(eempe_timeout_cnt)
begin
eempe_timeout_cnt <= eempe_timeout_cnt - 1;
end
if(wr)
begin
case(addr)
EEARH_ADDR: EEARH <= bus_in;
EEARL_ADDR: EEARL <= bus_in;
EEDR_ADDR: EEDR_WRITE <= bus_in;
EECR_ADDR:
begin
EECR <= bus_in;
if(EECR[2] | bus_in[1])
begin
eempe_timeout_cnt <= 3'h4;
end
end
endcase
end
if((&EECR[2:1]) )
begin
if(|eempe_timeout_cnt)
begin
case(EECR[5:4])
2'h0, 2'h2:
begin
dat_to_write <= ~EEDR_WRITE;
eep_wr <= 1'b1;
end
2'h1:
begin
dat_to_write <= 8'h00;
eep_wr <= 1'b1;
end
endcase
end
EECR[2:1] <= 2'b00;
if(int_p == int_n)
begin
int_p <= ~int_p;
end
end
if(EECR[0])
begin
EEDR_READ <= ~read_tmp;
EECR[0] <= 1'b0;
end
if(int_rst)
begin
int_n <= int_p;
end
if(eep_wr)
begin
content_modifyed <= content_modifyed | 1'b1;
end
end
end
always @ (posedge clk)
begin
if(eep_wr)
begin
eep[ext_eep_data_en ? ext_load_read_eep_addr : {EEARH, EEARL}] <= ext_eep_data_en ? ~ext_eep_data_in : dat_to_write;
end
read_tmp <= eep[ext_eep_data_en ? ext_load_read_eep_addr : {EEARH, EEARL}];
end
assign ext_eep_data_out = (ext_eep_data_rd & ext_eep_data_en) ? ~read_tmp : 8'h00;
assign int = EECR[3] ? (int_p ^ int_n) : 1'b0;
endmodule
| 6.549021 |
modules. */
/************************************************************/
`timescale 1ns / 1ps
module atmega_pio # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_IO_LEN = 16,
parameter PORT_ADDR = 0,
parameter DDR_ADDR = 1,
parameter PIN_ADDR = 2,
parameter PINMASK = 8'hFF,
parameter PULLUP_MASK = 8'h0,
parameter PULLDN_MASK = 8'h0,
parameter INVERSE_MASK = 8'h0,
parameter OUT_ENABLED_MASK = 8'hFF
)(
input rst,
input clk,
input [BUS_ADDR_IO_LEN-1:0]addr,
input wr,
input rd,
input [7:0]bus_in,
output reg [7:0]bus_out,
input [7:0]io_in,
output [7:0]io_out,
output [7:0]pio_out_io_connect,
output [4:0]debug
);
reg [7:0]DDR;
reg [7:0]PORT;
reg [7:0]PIN;
assign debug = PIN[7:3];
assign pio_out_io_connect = DDR;
always @ (posedge rst or posedge clk)
begin
if(rst)
begin
DDR <= 8'h00;
PORT <= 8'h00;
PIN <= 8'h00;
end
else
begin
PIN <= io_in;
if(wr)
begin
case(addr)
DDR_ADDR: DDR <= bus_in;
PORT_ADDR: PORT <= bus_in;
endcase
end
end
end
integer cnt_;
always @ *
begin
bus_out = 8'h00;
if(rd & ~rst)
begin
case(addr)
PORT_ADDR: bus_out = PORT;
DDR_ADDR: bus_out = DDR;
PIN_ADDR:
begin
for(cnt_ = 0; cnt_ < 8; cnt_ = cnt_ + 1)
begin
if (PINMASK[cnt_])
begin
bus_out[cnt_] = INVERSE_MASK[cnt_] ? ~PIN[cnt_] : PIN[cnt_];
end
end
end
endcase
end
end
genvar cnt;
generate
for (cnt = 0; cnt < 8; cnt = cnt + 1)
begin:OUTS
if (PINMASK[cnt] && OUT_ENABLED_MASK[cnt])
begin
assign io_out[cnt] = DDR[cnt] ? (INVERSE_MASK[cnt] ? ~PORT[cnt] : PORT[cnt]) : 1'bz;
end
else
begin
assign io_out[cnt] = 1'bz;
end
end
for (cnt = 0; cnt < 8; cnt = cnt + 1)
begin:PULLUPS
if (PULLUP_MASK[cnt] && PINMASK[cnt])
begin
if (PLATFORM == "XILINX")
begin
PULLUP PULLUP_inst (
.O(io_out[cnt]) // PullUp output (connect directly to top-level port)
);
end
end
end
for (cnt = 0; cnt < 8; cnt = cnt + 1)
begin:PULLDOWNS
if (PULLDN_MASK[cnt] && PINMASK[cnt])
begin
if (PLATFORM == "XILINX")
begin
PULLDOWN PULLDOWN_inst (
.O(io_out[cnt]) // PullDown output (connect directly to top-level port)
);
end
end
end
endgenerate
endmodule
| 8.338405 |
module spi_sim(
);
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0]addr = 0;
reg [7:0]bus_in = 0;
wire [7:0]bus_out;
reg wr;
reg rd;
reg ss;
wire dat;
wire int;
reg int_rst;
initial begin
addr <= 0;
bus_in <= 8'h00;
ss <= 1'b1;
rd <= 1'b0;
wr <= 1'b0;
int_rst <= 1'b0;
wait(clk);
wait(~clk);
rst = 1;
wait(~clk);
wait(clk);
#0.1; // Insert real logick delay because, always signals arrive after clock.
rst = 0;
#10;
addr <= 0;
bus_in <= 8'b11010000;
wr <= 1'b1;
#2;
wr <= 1'b0;
#10;
ss <= 1'b0;
#2;
addr <= 2;
bus_in <= 8'haa;
wr <= 1'b1;
#2; // Send first byte.
wr <= 1'b0;
#2;
addr <= 1;
rd <= 1'b1;
wait(`USE_INTERRUPT == "TRUE" ? int : bus_out[7]); // Wait for byte to be sent.
rd <= 1'b0;
#2;
rd <= 1'b1;
#2;
rd <= 1'b0;
#2;
if(`USE_INTERRUPT == "TRUE")
begin
int_rst <= 1'b1;
#2;
int_rst <= 1'b0;
#6;
end
addr <= 2;
rd <= 1'b1;
#2; // Read the received byte.
rd <= 1'b0;
#2;
addr <= 2;
bus_in <= 8'h55;
wr <= 1'b1;
#2; // Send second byte.
wr <= 1'b0;
#2;
addr <= 1;
rd <= 1'b1;
wait(`USE_INTERRUPT == "TRUE" ? int : bus_out[7]); // Wait for byte to be sent.
rd <= 1'b0;
#2;
rd <= 1'b1;
#2;
rd <= 1'b0;
#2;
if(`USE_INTERRUPT == "TRUE")
begin
int_rst <= 1'b1;
#2;
int_rst <= 1'b0;
#6;
end
addr <= 2;
rd <= 1'b1;
#2; // Read the received byte.
rd <= 1'b0;
#2;
#10000;
//sw = 2;
#10;
//sw = 0;
#100000;
$finish;
end
atmega_spi_m # (
.PLATFORM("XILINX"),
.BUS_ADDR_DATA_LEN(6),
.SPCR_ADDR(6'h0),
.SPSR_ADDR(6'h1),
.SPDR_ADDR(6'h2),
.DINAMIC_BAUDRATE("TRUE"),
.BAUDRATE_DIVIDER(0)
)spi_inst(
.rst(rst),
.clk(clk),
.addr(addr),
.wr(wr),
.rd(rd),
.bus_in(bus_in),
.bus_out(bus_out),
.int(int),
.int_rst(int_rst),
.io_connect(),
.scl(),
.miso(dat),
.mosi(dat)
);
endmodule
| 6.780304 |
module atmega_tim_8bit_sim ();
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0] io_addr = 0;
reg [7:0] io_bus_in = 0;
reg io_wr;
reg io_rd;
reg [7:0] data_addr = 0;
reg [7:0] data_bus_in = 0;
reg data_wr;
reg data_rd;
wire tov_int;
reg tov_int_rst;
wire ocra_int;
reg ocra_int_rst;
wire ocrb_int;
reg ocrb_int_rst;
wire ocrc_int;
reg ocrc_int_rst;
wire ocrd_int;
reg ocrd_int_rst;
wire oca;
wire ocb;
wire occ;
wire ocd;
initial begin
io_addr = 0;
io_bus_in = 8'h00;
io_rd = 1'b0;
io_wr = 1'b0;
data_addr = 'h00;
data_bus_in = 8'h00;
data_wr = 1'b0;
data_rd = 1'b0;
tov_int_rst = 1'b0;
ocra_int_rst = 1'b0;
ocrb_int_rst = 1'b0;
ocrc_int_rst = 1'b0;
ocrd_int_rst = 1'b0;
wait (clk);
wait (~clk);
rst = 1;
wait (~clk);
wait (clk);
#0.1; // Insert real logick delay because, always signals arrive after clock.
rst = 0;
#10;
data_addr = 'h89; // OCRAH
data_bus_in = 8'h00;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h88; // OCRAL
data_bus_in = 8'h7F;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8B; // OCRBH
data_bus_in = 8'h00;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8A; // OCRBL
data_bus_in = 8'h3F;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8D; // OCRCH
data_bus_in = 8'h00;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8C; // OCRCL
data_bus_in = 8'h1F;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8F; // OCRDH
data_bus_in = 8'h00;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h8E; // OCRDL
data_bus_in = 8'h0F;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h6F; // TIMSK
data_bus_in = 8'b00011111;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h80; // TCCRA
data_bus_in = 8'b10101000;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
data_addr = 'h81; // TCCRB
data_bus_in = 8'b00001001;
data_wr = 1'b1;
#2;
data_wr = 1'b0;
#4;
while (1) begin
if (tov_int) begin
#2;
tov_int_rst = 1'b1;
#2;
tov_int_rst = 1'b0;
end
if (ocra_int) begin
#2;
ocra_int_rst = 1'b1;
#2;
ocra_int_rst = 1'b0;
end
if (ocrb_int) begin
#2;
ocrb_int_rst = 1'b1;
#2;
ocrb_int_rst = 1'b0;
end
if (ocrc_int) begin
#2;
ocrc_int_rst = 1'b1;
#2;
ocrc_int_rst = 1'b0;
end
if (ocrd_int) begin
#2;
ocrd_int_rst = 1'b1;
#2;
ocrd_int_rst = 1'b0;
end
#2;
end
end
wire clk8;
wire clk64;
wire clk256;
wire clk1024;
tim_013_prescaller tim_013_prescaller_inst (
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024)
);
wire [7:0] io_tim0_d_out;
wire [7:0] dat_tim0_d_out;
atmega_tim_16bit #(
.PLATFORM("XILINX"),
.USE_OCRB("TRUE"),
.USE_OCRC("TRUE"),
.USE_OCRD("FALSE"),
.BUS_ADDR_IO_LEN(6),
.BUS_ADDR_DATA_LEN(8),
.GTCCR_ADDR('h23),
.TCCRA_ADDR('h80),
.TCCRB_ADDR('h81),
.TCCRC_ADDR('h82),
.TCCRD_ADDR('h0),
.TCNTL_ADDR('h84),
.TCNTH_ADDR('h85),
.ICRL_ADDR('h86),
.ICRH_ADDR('h87),
.OCRAL_ADDR('h88),
.OCRAH_ADDR('h89),
.OCRBL_ADDR('h8A),
.OCRBH_ADDR('h8B),
.OCRCL_ADDR('h8C),
.OCRCH_ADDR('h8D),
.OCRDL_ADDR('h0),
.OCRDH_ADDR('h0),
.TIMSK_ADDR('h6F),
.TIFR_ADDR('h16),
.DINAMIC_BAUDRATE("TRUE"),
.BAUDRATE_DIVIDER(1)
) tim_1_sim (
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024),
.addr_io(io_addr),
.wr_io(io_wr),
.rd_io(io_rd),
.bus_io_in(io_bus_in),
.bus_io_out(io_tim0_d_out),
.addr_dat(data_addr[7:0]),
.wr_dat(data_wr),
.rd_dat(data_rd),
.bus_dat_in(data_bus_in),
.bus_dat_out(dat_tim0_d_out),
.tov_int(tov_int),
.tov_int_rst(tov_int_rst),
.ocra_int(ocra_int),
.ocra_int_rst(ocra_int_rst),
.ocrb_int(ocrb_int),
.ocrb_int_rst(ocrb_int_rst),
.ocrc_int(ocrc_int),
.ocrc_int_rst(ocrc_int_rst),
.ocrd_int(ocrd_int),
.ocrd_int_rst(ocrd_int_rst),
.t(),
.oca(oca),
.ocb(ocb),
.occ(occ),
.ocd(ocd),
.oca_io_connect(),
.ocb_io_connect(),
.occ_io_connect(),
.ocd_io_connect()
);
endmodule
| 6.911264 |
module atmega_tim_8bit_sim ();
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0] io_addr = 0;
reg [7:0] io_bus_in = 0;
reg io_wr;
reg io_rd;
reg [7:0] data_addr = 0;
reg [7:0] data_bus_in = 0;
wire [7:0] data_bus_out;
reg data_wr;
reg data_rd;
wire tov_int;
reg tov_int_rst;
wire ocra_int;
reg ocra_int_rst;
wire ocrb_int;
reg ocrb_int_rst;
wire oca;
wire ocb;
initial begin
io_addr <= 0;
io_bus_in <= 8'h00;
io_rd <= 1'b0;
io_wr <= 1'b0;
tov_int_rst <= 1'b0;
ocra_int_rst <= 1'b0;
ocrb_int_rst <= 1'b0;
wait (clk);
wait (~clk);
rst = 1;
wait (~clk);
wait (clk);
#0.1; // Insert real logick delay because, always signals arrive after clock.
rst = 0;
#10;
io_addr <= 'h27; // OCRA
io_bus_in <= 8'h1F;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
io_addr <= 'h28; // OCRB
io_bus_in <= 8'h0F;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
data_addr <= 'h6E; // TIMSK
data_bus_in <= 8'b00000111;
data_wr <= 1'b1;
#2;
data_wr <= 1'b0;
#4;
io_addr <= 'h24; // TCCRA
io_bus_in <= 8'b10100001;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
io_addr <= 'h25; // TCCRB
io_bus_in <= 8'b00000010;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
while (1) begin
if (tov_int) begin
#2;
tov_int_rst <= 1'b1;
#2;
tov_int_rst <= 1'b0;
end
if (ocra_int) begin
#2;
ocra_int_rst <= 1'b1;
#2;
ocra_int_rst <= 1'b0;
end
if (ocrb_int) begin
#2;
ocrb_int_rst <= 1'b1;
#2;
ocrb_int_rst <= 1'b0;
end
#2;
end
end
wire clk8;
wire clk64;
wire clk256;
wire clk1024;
tim_013_prescaller tim_013_prescaller_inst (
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024)
);
wire [7:0] io_tim0_d_out;
wire [7:0] dat_tim0_d_out;
atmega_tim_8bit #(
.PLATFORM("XILINX"),
.USE_OCRB("TRUE"),
.BUS_ADDR_IO_LEN(6),
.BUS_ADDR_DATA_LEN(8),
.GTCCR_ADDR('h23),
.TCCRA_ADDR('h24),
.TCCRB_ADDR('h25),
.TCNT_ADDR('h26),
.OCRA_ADDR('h27),
.OCRB_ADDR('h28),
.TIMSK_ADDR('h6E),
.TIFR_ADDR('h15),
.DINAMIC_BAUDRATE("TRUE"),
.BAUDRATE_DIVIDER(1)
) tim_0_sim (
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024),
.addr_io(io_addr),
.wr_io(io_wr),
.rd_io(io_rd),
.bus_io_in(io_bus_in),
.bus_io_out(io_tim0_d_out),
.addr_dat(data_addr[7:0]),
.wr_dat(data_wr),
.rd_dat(data_rd),
.bus_dat_in(data_bus_in),
.bus_dat_out(dat_tim0_d_out),
.tov_int(tov_int),
.tov_int_rst(tov_int_rst),
.ocra_int(ocra_int),
.ocra_int_rst(ocra_int_rst),
.ocrb_int(ocrb_int),
.ocrb_int_rst(ocrb_int_rst),
.t(),
.oca(oca),
.ocb(ocb),
.oca_io_connect(),
.ocb_io_connect()
);
endmodule
| 6.911264 |
module PasswordAndIdChecker (
Password,
ID,
IndexOutput,
PassAuthorized
);
input [7:0] Password;
input wire [7:0] ID;
output reg PassAuthorized;
output reg [3:0] IndexOutput;
reg [7:0] authorized_passwords_ROM[0:9];
reg [7:0] authorized_id_ROM[0:9];
parameter OFF = 1'b0;
parameter ON = 1'b1;
// loading passwords rom
//
initial begin
$readmemb("authorized_passwordsROM.mem", authorized_passwords_ROM);
$readmemb("authorized_idROM.mem", authorized_id_ROM);
end
// finding out is the pass inputed is in ram
//
integer i;
always @(Password or ID) begin
PassAuthorized = OFF;
for (i = 0; i < 10; i = i + 1) begin
if (ID == authorized_id_ROM[i]) begin
IndexOutput = i;
end
if (Password == authorized_passwords_ROM[i] & ID == authorized_id_ROM[i]) begin
PassAuthorized = ON;
IndexOutput = i;
end
end
end
endmodule
| 6.822896 |
module PasswordAndIdCheckerTESTBENCH ();
wire PassAuthorized;
wire [3:0] IndexOutput;
reg [7:0] ID;
reg [7:0] Password;
PasswordAndIdChecker somerandomname (
Password,
ID,
IndexOutput,
PassAuthorized
);
initial begin
// no currect pass no currect id
ID = 8'b11110000;
Password = 8'b10111011;
#20
// currect pass no currect id
ID = 8'b11110000;
Password = 8'b10111101;
#20
// no currect pass currect id
ID = 8'b10111101;
Password = 8'b11110000;
#20
// another no currect pass currect id
ID = 8'b10111110;
Password = 8'b11110000;
#20
// currect pass currect id
ID = 8'b10111101;
Password = 8'b10111000;
#20
// no currect pass no currect id
ID = 8'b10010000;
Password = 8'b10111011;
#20
// another currect pass currect id
ID = 8'b11101000;
Password = 8'b10110010;
#20 $stop;
end
endmodule
| 6.822896 |
module AtoD_analog (
cosSAR,
sinSAR,
ana_cos,
ana_sin,
smpl,
gt_cos,
gt_sin
);
input [11:0] cosSAR, sinSAR;
// from A2D digital, acts as DAC input
input [11:0] ana_cos, ana_sin;
// 12-bit representation of analog input
input smpl;
// sample input from A2D digital
output gt_cos, gt_sin; // represents comparator output of both sin and cos channels.
reg [11:0] ana_cos_smpld, ana_sin_smpld; // sampled versions of "analog" inputs
always @(negedge smpl) begin
ana_cos_smpld = ana_cos;
ana_sin_smpld = ana_sin;
end
assign gt_cos = (cosSAR > ana_cos_smpld) ? 1'b1 : 1'b0;
assign gt_sin = (sinSAR > ana_sin_smpld) ? 1'b1 : 1'b0;
endmodule
| 7.916269 |
module atomicity (
clk, //INPUT
pc, //INPUT
irq,
//pc_en,
reset //OUTPUT
);
input clk;
input [15:0] pc;
input irq;
//input pc_en;
output reset;
// FSM States //////////////////////////////////////////////////////////
parameter notRC = 3'b000;
parameter fstRC = 3'b001;
parameter lastRC = 3'b010;
parameter midRC = 3'b011;
parameter kill = 3'b100;
///////////////////////////////////////////////////////////////////////
parameter RESET_HANDLER = 16'hfffe;
// MACROS ///////////////////////////////////////////
parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;
parameter LAST_SMEM_ADDR = SMEM_BASE + SMEM_SIZE - 2;
/////////////////////////////////////////////////////
reg [2:0] pc_state; // 3 bits for 5 states
reg atomicity_res;
initial begin
pc_state = kill;
atomicity_res = 1'b1;
end
wire is_mid_rom = pc > SMEM_BASE && pc < LAST_SMEM_ADDR;
wire is_first_rom = pc == SMEM_BASE;
wire is_last_rom = pc == LAST_SMEM_ADDR;
wire is_in_rom = is_mid_rom | is_first_rom | is_last_rom;
wire is_outside_rom = pc < SMEM_BASE | pc > LAST_SMEM_ADDR;
always @(posedge clk) begin
case (pc_state)
notRC:
if (is_outside_rom) pc_state <= notRC;
else if (is_first_rom) pc_state <= fstRC;
else if (is_mid_rom || is_last_rom) pc_state <= kill;
else // only necessary if we include if(pc_en)
pc_state <= pc_state;
midRC:
if (is_mid_rom) pc_state <= midRC;
else if (is_last_rom) pc_state <= lastRC;
else if (is_outside_rom || is_first_rom) pc_state <= kill;
//else if (pc_en && is_first_rom)
//pc_state = fstRC;
else
pc_state <= pc_state;
fstRC:
if (is_mid_rom) pc_state <= midRC;
else if (is_first_rom) pc_state = fstRC;
else if (is_outside_rom || is_first_rom || is_last_rom) pc_state <= kill;
//else if (pc_en && is_last_rom)
//pc_state = lastRC;
else
pc_state <= pc_state;
lastRC:
if (is_outside_rom) pc_state <= notRC;
else if (is_last_rom) pc_state = lastRC;
//else if (pc_en && is_first_rom)
//pc_state = firstRC;
//else if (pc_en && is_mid_rom)
//pc_state = midRC;
else if (is_first_rom || is_last_rom || is_mid_rom) pc_state <= kill;
else pc_state <= pc_state;
kill:
if (pc == RESET_HANDLER) pc_state <= notRC;
else pc_state <= pc_state;
endcase
end
////////////// OUTPUT LOGIC //////////////////////////////////////
always @(posedge clk) begin
if ( (
(pc_state == fstRC && !is_mid_rom && !is_first_rom) ||
(pc_state == lastRC && !is_outside_rom && !is_last_rom) ||
(pc_state == midRC && !is_last_rom && !is_mid_rom) ||
(pc_state == notRC && !is_outside_rom && !is_first_rom)||
(pc_state == kill && pc != RESET_HANDLER)
)
)begin
atomicity_res <= 1'b1;
end else begin
atomicity_res <= 1'b0;
end
end
assign reset = atomicity_res;
endmodule
| 7.171265 |
module delreg_varbits_vardel #(
parameter data_width = 64,
clock_cycles = 16
) (
input clk,
input en,
input [data_width-1 : 0] data_in,
output reg [data_width-1 : 0] data_out = {data_width * 1'b0}
);
reg [clock_cycles-1:0] shift_reg[data_width-1:0];
integer srl_index;
initial
for (srl_index = 0; srl_index < data_width; srl_index = srl_index + 1)
shift_reg[srl_index] = {clock_cycles{1'b0}};
wire [data_width-1 : 0] data_out_r;
genvar i;
generate
for (i = 0; i < data_width; i = i + 1) begin : del_reg
always @(posedge clk) if (en) shift_reg[i] <= {shift_reg[i][clock_cycles-2:0], data_in[i]};
assign data_out_r[i] = shift_reg[i][clock_cycles-1];
end
endgenerate
always @(posedge clk) if (en) data_out <= data_out_r;
endmodule
| 6.902147 |
module atri_event_fifo (
input clk_i,
inout [`EVIF_SIZE-1:0] interface_io
);
wire fifo_clk_o = clk_i;
wire irs_clk_i;
wire fifo_full_o;
wire fifo_empty_o;
wire fifo_wr_i;
wire fifo_rd_i;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [1:0] type_i;
wire [1:0] type_o;
wire prog_empty_o = 0;
wire [13:0] read_data_count;
wire [15:0] fifo_nwords_o = {{2{1'b0}}, read_data_count};
wire fifo_rst_i;
event_interface_fifo evif (
.interface_io(interface_io),
.fifo_clk_i(fifo_clk_o),
.irs_clk_o(irs_clk_i),
.fifo_empty_i(fifo_empty_o),
.fifo_full_i(fifo_full_o),
.fifo_wr_o(fifo_wr_i),
.fifo_rd_o(fifo_rd_i),
.dat_o(dat_i),
.dat_i(dat_o),
.type_o(type_i),
.type_i(type_o),
.prog_empty_i(prog_empty_o),
.fifo_nwords_i(fifo_nwords_o),
.fifo_rst_o(fifo_rst_i)
);
atri_event_fifo_core fifo (
.wr_clk(irs_clk_i),
.rd_clk(fifo_clk_o),
.wr_en(fifo_wr_i),
.rd_en(fifo_rd_i),
.din({type_i, dat_i}),
.dout({type_o, dat_o}),
.full(fifo_full_o),
.empty(fifo_empty_o),
.rst(fifo_rst_i),
.rd_data_count(read_data_count)
);
endmodule
| 6.732884 |
module atri_i2c_rom (
input clk,
output [17:0] instruction,
input [9:0] address,
output reset,
input jump_wr_stb,
input [7:0] ram_data_in,
output [7:0] ram_data_out,
input [7:0] ram_address,
input ram_wr_stb
);
wire WEA = ram_wr_stb | jump_wr_stb;
wire [10:0] ADDRA = (jump_wr_stb) ? 11'h6FE : {3'b111, ram_address};
RAMB16_S9_S18 #(
`include "atrii2c_rom.vh"
) bram (
.CLKB (clk),
.WEB (1'b0),
.ENB (1'b1),
.ADDRB(address),
.DIPB (2'b00),
.DIB (16'h0000),
.DOB (instruction[15:0]),
.DOPB (instruction[17:16]),
.SSRB (1'b0),
.CLKA (clk),
.WEA (WEA),
.ENA (1'b1),
.ADDRA(ADDRA),
.DIPA (jump_wr_stb),
.DIA (ram_data_in),
.DOA (ram_data_out),
.SSRA (1'b0)
);
endmodule
| 7.436585 |
module atri_readout_rom (
input clk,
output [17:0] instruction,
input [9:0] address
);
wire [31:0] doa;
wire [ 3:0] dopa;
RAMB16BWER #(
.DATA_WIDTH_A(18),
.DATA_WIDTH_B(0),
`include "atrireadout_rom.vh"
) bram (
.CLKA (clk),
.WEA (1'b0),
.ENA (1'b1),
.ADDRA({address, 4'b0}),
.DOA (doa),
.DOPA (dopa),
.RSTA (1'b0)
);
assign instruction[15:0] = doa[15:0];
assign instruction[17:16] = dopa[1:0];
endmodule
| 7.030736 |
module atri_samplemon_rom (
input clk,
output [17:0] instruction,
input [9:0] address
);
wire [31:0] doa;
wire [ 3:0] dopa;
RAMB16BWER #(
.DATA_WIDTH_A(18),
.DATA_WIDTH_B(0),
`include "atrisamplemon_rom.vh"
) bram (
.CLKA (clk),
.WEA (1'b0),
.ENA (1'b1),
.ADDRA({address, 4'b0}),
.DOA (doa),
.DOPA (dopa),
.RSTA (1'b0)
);
assign instruction[15:0] = doa[15:0];
assign instruction[17:16] = dopa[1:0];
endmodule
| 7.253228 |
module atri_sample_monitor (
input clk_i,
input rst_i,
input en_i,
input [3:0] sample_mon_i,
input sync_i,
input sst_i,
output [7:0] irs1_mon_o,
output [7:0] irs2_mon_o,
output [7:0] irs3_mon_o,
output [7:0] irs4_mon_o,
output [52:0] debug_o
);
// screw this, we just use an IDDR2 now and deserialize ourselves.
irs_sample_mon_v2 smon (
.sample_mon_i(sample_mon_i),
.clk_i(clk_i),
.en_i(en_i),
.rst_i(rst_i),
.sync_i(sync_i),
.sst_i(sst_i),
.irs1_mon_o(irs1_mon_o),
.irs2_mon_o(irs2_mon_o),
.irs3_mon_o(irs3_mon_o),
.irs4_mon_o(irs4_mon_o),
.debug_o(debug_o)
);
endmodule
| 6.558939 |
module atr_controller (
input clk_i,
input rst_i,
input [5:0] adr_i,
input [3:0] sel_i,
input [31:0] dat_i,
output reg [31:0] dat_o,
input we_i,
input stb_i,
input cyc_i,
output reg ack_o,
input run_rx,
input run_tx,
output [31:0] ctrl_lines
);
reg [ 3:0] state;
reg [31:0] atr_ram[0:15]; // DP distributed RAM
// WB Interface
always @(posedge clk_i)
if (we_i & stb_i & cyc_i) begin
if (sel_i[3]) atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24];
if (sel_i[2]) atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16];
if (sel_i[1]) atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
if (sel_i[0]) atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
always @(posedge clk_i) dat_o <= atr_ram[adr_i[5:2]];
always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o;
// Control side of DP RAM
assign ctrl_lines = atr_ram[state];
// Put a more complex state machine with time delays and multiple states here
// if daughterboard requires more complex sequencing
localparam ATR_IDLE = 4'd0;
localparam ATR_TX = 4'd1;
localparam ATR_RX = 4'd2;
localparam ATR_FULL_DUPLEX = 4'd3;
always @(posedge clk_i)
if (rst_i) state <= ATR_IDLE;
else
case ({
run_rx, run_tx
})
2'b00: state <= ATR_IDLE;
2'b01: state <= ATR_TX;
2'b10: state <= ATR_RX;
2'b11: state <= ATR_FULL_DUPLEX;
endcase // case({run_rx,run_tx})
endmodule
| 8.146591 |
module atr_controller16 (
input clk_i,
input rst_i,
input [5:0] adr_i,
input [1:0] sel_i,
input [15:0] dat_i,
output reg [15:0] dat_o,
input we_i,
input stb_i,
input cyc_i,
output reg ack_o,
input run_rx,
input run_tx,
output [31:0] ctrl_lines
);
reg [3:0] state;
reg [31:0] atr_ram[0:15]; // DP distributed RAM
wire [3:0] sel_int = {
(sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1])
};
// WB Interface
always @(posedge clk_i)
if (we_i & stb_i & cyc_i) begin
if (sel_int[3]) atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
if (sel_int[2]) atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
if (sel_int[1]) atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
if (sel_int[0]) atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
always @(posedge clk_i)
dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o;
// Control side of DP RAM
assign ctrl_lines = atr_ram[state];
// Put a more complex state machine with time delays and multiple states here
// if daughterboard requires more complex sequencing
localparam ATR_IDLE = 4'd0;
localparam ATR_TX = 4'd1;
localparam ATR_RX = 4'd2;
localparam ATR_FULL_DUPLEX = 4'd3;
always @(posedge clk_i)
if (rst_i) state <= ATR_IDLE;
else
case ({
run_rx, run_tx
})
2'b00: state <= ATR_IDLE;
2'b01: state <= ATR_TX;
2'b10: state <= ATR_RX;
2'b11: state <= ATR_FULL_DUPLEX;
endcase // case({run_rx,run_tx})
endmodule
| 8.146591 |
module attack_ind (
clk,
gameClk, // auto driven by gameclk
x,
y,
rgb,
damage
);
parameter BUS_WIDTH = 12;
parameter TOP = 330;
parameter LEFT = 240;
parameter RIGHT = 400;
parameter THICCNESS = 3;
parameter HEIGHT = 30;
input wire clk;
input wire gameClk; // auto driven by gameclk
input wire [9:0] x;
input wire [9:0] y;
output wire [BUS_WIDTH-1:0] rgb;
output wire [7:0] damage;
reg [BUS_WIDTH-1:0] rgb_reg;
reg [7:0] damage_reg;
wire [9:0] middle = (LEFT + RIGHT) / 2; // to lzay to declare param
reg [9:0] markerPos = LEFT;
reg right = 0;
always @(posedge gameClk) begin
if (markerPos <= LEFT) begin
right = 1;
markerPos = LEFT;
end else if (markerPos >= RIGHT) begin
right = 0;
markerPos = RIGHT;
end
markerPos = right ? markerPos + 3 : markerPos - 3;
end
always @(posedge clk) begin
if (markerPos-THICCNESS <= x && x <= markerPos+THICCNESS &&
TOP-HEIGHT <= y && y <= TOP+HEIGHT
)
rgb_reg <= 5'd3;
else if (TOP - THICCNESS <= y && y <= TOP + THICCNESS)
if ((middle > x ? middle - x : x - middle) <= 10) rgb_reg <= 5'd8;
else if ((middle > x ? middle - x : x - middle) <= 30) rgb_reg <= 5'd9;
else if ((middle > x ? middle - x : x - middle) <= 45) rgb_reg <= 5'd10;
else if ((middle > x ? middle - x : x - middle) <= 77) // (400-240)/2 - thiccness
rgb_reg <= 5'd11;
else rgb_reg <= 5'd0;
else rgb_reg <= 5'd0;
if ((middle > markerPos ? middle - markerPos : markerPos - middle) <= 10) damage_reg <= 8'd40;
else if ((middle > markerPos ? middle - markerPos : markerPos - middle) <= 30)
damage_reg <= 8'd30;
else if ((middle > markerPos ? middle - markerPos : markerPos - middle) <= 45)
damage_reg <= 8'd15;
else damage_reg <= 0;
end
assign damage = damage_reg;
assign rgb = rgb_reg;
endmodule
| 6.727504 |
module attack_shift_amount (
input clock,
input reset,
input [3:0] attack_value,
output [3:0] shift_amount,
output done
);
wire [31:0] count_up_to;
attack_rom ar0 (
clock,
attack_value,
count_up_to
);
wire enable;
rate_divider rd0 (
clock,
reset,
count_up_to,
enable
);
shift_amount_reducer sar0 (
clock,
reset,
enable,
shift_amount,
done
);
endmodule
| 7.295944 |
module shift_amount_reducer (
clock,
reset,
enable,
shift_amount,
shift_done
);
input clock;
input reset;
input enable;
output reg [3:0] shift_amount;
output reg shift_done;
always @(posedge clock) begin
if (reset) begin
shift_done <= 0;
shift_amount <= 4'd15;
end else if (enable) begin
shift_done <= shift_done;
shift_amount <= shift_amount - 1;
end else if (shift_amount == 4'd0) begin
shift_done <= 1;
shift_amount <= 4'd15;
end
end
endmodule
| 6.646294 |
module atta_system #(
parameter firmware_file = "../../firmware/MMX.hex",
parameter firmware_ram_depth = 65536 // 64KB
) (
input clk_i,
input rst_i,
// picorv signals
output trap_o,
output trace_valid_o,
output [35:0] trace_data_o,
output mem_instr_o,
input [31:0] irq_i,
// external modules
output [31:0] gpio_o
);
////////////////////////////////////////////////////////////////////////
// Modules interconnections
////////////////////////////////////////////////////////////////////////
`include "wb_intercon.vh"
// These are used by wb_intercon instantiatred by the "wb_intercon.vh" macro
assign wb_clk = clk_i;
assign wb_rst = rst_i;
wire rst_n = ~rst_i;
////////////////////////////////////////////////////////////////////////
// Picorv32
////////////////////////////////////////////////////////////////////////
picorv32_wb #(
.ENABLE_REGS_DUALPORT(1),
.ENABLE_MUL (1),
.ENABLE_DIV (1),
.ENABLE_TRACE (1),
// Enable support for compressed instr. set. Must match firmware options
// in Makefile
.COMPRESSED_ISA (1),
.BARREL_SHIFTER (1),
.ENABLE_PCPI (1),
.ENABLE_IRQ (0)
) cmp_picorv32 (
.wb_clk_i(clk_i),
.wb_rst_i(rst_i),
.wbm_adr_o(wb_m2s_picorv32_adr),
.wbm_dat_i(wb_s2m_picorv32_dat),
.wbm_stb_o(wb_m2s_picorv32_stb),
.wbm_ack_i(wb_s2m_picorv32_ack),
.wbm_cyc_o(wb_m2s_picorv32_cyc),
.wbm_dat_o(wb_m2s_picorv32_dat),
.wbm_we_o (wb_m2s_picorv32_we),
.wbm_sel_o(wb_m2s_picorv32_sel),
.pcpi_wr (1'b0),
.pcpi_rd (32'b0),
.pcpi_wait (1'b0),
.pcpi_ready(1'b0),
.trap (trap_o),
.irq (irq_i),
.trace_valid(trace_valid_o),
.trace_data (trace_data_o),
.mem_instr (mem_instr_o)
);
assign wb_m2s_picorv32_cti = 3'b000;
assign wb_m2s_picorv32_bte = 2'b00;
////////////////////////////////////////////////////////////////////////
// RAM
////////////////////////////////////////////////////////////////////////
wb_ram #(
.memfile(firmware_file),
.depth (firmware_ram_depth)
) cmp_wb_ram (
//Wishbone Master interface
.wb_clk_i(clk_i),
.wb_rst_i(rst_i),
.wb_cyc_i(wb_m2s_ram_cyc),
.wb_dat_i(wb_m2s_ram_dat),
.wb_sel_i(wb_m2s_ram_sel),
.wb_we_i (wb_m2s_ram_we),
.wb_bte_i(wb_m2s_ram_bte),
.wb_cti_i(wb_m2s_ram_cti),
.wb_adr_i(wb_m2s_ram_adr),
.wb_stb_i(wb_m2s_ram_stb),
.wb_dat_o(wb_s2m_ram_dat),
.wb_ack_o(wb_s2m_ram_ack)
);
assign wb_s2m_ram_err = 1'b0;
assign wb_s2m_ram_rty = 1'b0;
////////////////////////////////////////////////////////////////////////
// LEDs
////////////////////////////////////////////////////////////////////////
wb_leds cmp_wb_leds (
// Clock/Resets
.clk_i (clk_i),
.rst_n_i(rst_n),
// Wishbone signals
.wb_cyc_i(wb_m2s_leds_cyc),
.wb_dat_i(wb_m2s_leds_dat),
.wb_sel_i(wb_m2s_leds_sel),
.wb_we_i (wb_m2s_leds_we),
.wb_adr_i(wb_m2s_leds_adr),
.wb_stb_i(wb_m2s_leds_stb),
.wb_dat_o(wb_s2m_leds_dat),
.wb_ack_o(wb_s2m_leds_ack),
// LEDs
.leds_o(gpio_o)
);
assign wb_s2m_leds_err = 1'b0;
assign wb_s2m_leds_rty = 1'b0;
endmodule
| 7.562774 |
module atta_tb #(
parameter VERBOSE = 0
);
reg clk = 1;
reg rst_n = 0;
wire trap;
always #5 clk = ~clk;
wire rst = ~rst_n;
initial begin
repeat (100) @(posedge clk);
rst_n <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, dut);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/MMX.hex";
$readmemh(firmware_file, dut.cmp_wb_ram.ram0.mem);
end
integer cycle_counter;
always @(posedge clk) begin
cycle_counter <= !rst ? cycle_counter + 1 : 0;
if (!rst && trap) begin
repeat (10) @(posedge clk);
$display("TRAP after %1d clock cycles", cycle_counter);
if ($test$plusargs("noerror")) $finish;
$stop;
end
end
reg [31:0] irq = 0;
atta_system #(
.firmware_file("")
) dut (
.clk_i(clk),
.rst_i(rst),
.trap_o (trap),
.trace_valid_o(trace_valid),
.trace_data_o (trace_data),
.mem_instr_o (),
.irq_i (irq),
.gpio_o()
);
endmodule
| 7.154119 |
module atta_top #(
parameter firmware_file = "../../firmware/MMX.hex"
) (
input sysclk_i,
output [4:0] gpio_led_o
);
wire clk_100;
wire locked;
// Should be more robust than this, but it will do for now
wire rst = ~locked;
sys_clk #(
.DIFF_CLKIN ("FALSE"),
.CLKIN_PERIOD(10.000),
.MULT (10.000),
.DIV0 (10)
) cmp_sys_clk (
.sysclk_p_i(sysclk_i),
.sysclk_n_i(1'b0),
.rst_i (1'b0),
.clk_out0_o(clk_100),
.locked_o (locked)
);
wire [31:0] gpio;
wire trap;
wire trace_valid;
wire [35:0] trace_data;
reg [31:0] irq = 0;
atta_system #(
.firmware_file(firmware_file)
) cmp_atta_system (
.clk_i (clk_100),
.rst_i (rst),
.trap_o (trap),
.trace_valid_o(trace_valid),
.trace_data_o (trace_data),
.mem_instr_o (mem_instr),
.irq_i (irq),
.gpio_o (gpio)
);
assign gpio_led_o[0] = gpio[0];
assign gpio_led_o[1] = gpio[1];
assign gpio_led_o[2] = gpio[2];
assign gpio_led_o[3] = gpio[3];
assign gpio_led_o[4] = trap;
endmodule
| 6.523119 |
module divideby8 (
input [`DATA_WIDTH-1:0] data,
output reg [`DATA_WIDTH-1:0] out
);
reg [`DATA_WIDTH-1:0] mask;
always @(*) begin
if (data[`DATA_WIDTH-1] == 1) mask = 16'b1110000000000000;
else mask = 0;
out = mask | (data >> 3);
end
endmodule
| 7.698216 |
module vecmat_add_32 #(
parameter arraysize = 512,
parameter vectdepth = 32
) (
input clk,
reset,
input [arraysize-1:0] mulout,
output reg [15:0] data_out
);
wire [15:0] tmp0, tmp1 ,tmp2 ,tmp3 ,tmp4 ,tmp5 ,tmp6 ,tmp7 ,tmp8 ,tmp9 ,tmp10 ,tmp11 ,tmp12 ,tmp13 ,tmp14 ,tmp15 ,tmp16 ,tmp17 ,tmp18 ,tmp19 ,tmp20 ,tmp21 ,tmp22 ,tmp23 ,tmp24 ,tmp25 ,tmp26 ,tmp27 ,tmp28 ,tmp29 ,tmp30 ,tmp31 ,tmp32 ,tmp33 ,tmp34 ,tmp35 ,tmp36 ,tmp37 ,tmp38 ,tmp39 ,tmp40 ,tmp41 ,tmp42 ,tmp43 ,tmp44 ,tmp45 ,tmp46 ,tmp47 ,tmp48 ,tmp49 ,tmp50,tmp51 ,tmp52 ,tmp53,tmp54 ,tmp55 ,tmp56 ,tmp57 ,tmp58, tmp59 ,tmp60 ,tmp61,tmp62;
reg [31:0] i;
reg [15:0]
ff1, ff3, ff5, ff7, ff9, ff11, ff13, ff15, ff17, ff19, ff21, ff23, ff25, ff27, ff29, ff31;
always @(posedge clk) begin
if (~reset) begin
data_out <= tmp57;
//adding a flop pipeline stage
ff1 <= tmp1;
ff3 <= tmp3;
ff5 <= tmp5;
ff7 <= tmp7;
ff9 <= tmp9;
ff11 <= tmp11;
ff13 <= tmp13;
ff15 <= tmp15;
end
end
// fixed point addition
qadd2 Add_u0 (
.a(mulout[16*0+:16]),
.b(mulout[16*1+:16]),
.c(tmp0)
);
qadd2 Add_u2 (
.a(mulout[16*2+:16]),
.b(mulout[16*3+:16]),
.c(tmp2)
);
qadd2 Add_u4 (
.a(mulout[16*4+:16]),
.b(mulout[16*5+:16]),
.c(tmp4)
);
qadd2 Add_u6 (
.a(mulout[16*6+:16]),
.b(mulout[16*7+:16]),
.c(tmp6)
);
qadd2 Add_u8 (
.a(mulout[16*8+:16]),
.b(mulout[16*9+:16]),
.c(tmp8)
);
qadd2 Add_u10 (
.a(mulout[16*10+:16]),
.b(mulout[16*11+:16]),
.c(tmp10)
);
qadd2 Add_u12 (
.a(mulout[16*12+:16]),
.b(mulout[16*13+:16]),
.c(tmp12)
);
qadd2 Add_u14 (
.a(mulout[16*14+:16]),
.b(mulout[16*15+:16]),
.c(tmp14)
);
qadd2 Add_u16 (
.a(mulout[16*16+:16]),
.b(mulout[16*17+:16]),
.c(tmp16)
);
qadd2 Add_u18 (
.a(mulout[16*18+:16]),
.b(mulout[16*19+:16]),
.c(tmp18)
);
qadd2 Add_u20 (
.a(mulout[16*20+:16]),
.b(mulout[16*21+:16]),
.c(tmp20)
);
qadd2 Add_u22 (
.a(mulout[16*22+:16]),
.b(mulout[16*23+:16]),
.c(tmp22)
);
qadd2 Add_u24 (
.a(mulout[16*24+:16]),
.b(mulout[16*25+:16]),
.c(tmp24)
);
qadd2 Add_u26 (
.a(mulout[16*26+:16]),
.b(mulout[16*27+:16]),
.c(tmp26)
);
qadd2 Add_u28 (
.a(mulout[16*28+:16]),
.b(mulout[16*29+:16]),
.c(tmp28)
);
qadd2 Add_u30 (
.a(mulout[16*30+:16]),
.b(mulout[16*31+:16]),
.c(tmp30)
);
qadd2 Add_u1 (
.a(tmp0),
.b(tmp2),
.c(tmp1)
);
qadd2 Add_u3 (
.a(tmp4),
.b(tmp6),
.c(tmp3)
);
qadd2 Add_u5 (
.a(tmp8),
.b(tmp10),
.c(tmp5)
);
qadd2 Add_u7 (
.a(tmp12),
.b(tmp14),
.c(tmp7)
);
qadd2 Add_u9 (
.a(tmp16),
.b(tmp18),
.c(tmp9)
);
qadd2 Add_u11 (
.a(tmp20),
.b(tmp22),
.c(tmp11)
);
qadd2 Add_u13 (
.a(tmp24),
.b(tmp26),
.c(tmp13)
);
qadd2 Add_u15 (
.a(tmp28),
.b(tmp30),
.c(tmp15)
);
qadd2 Add_u33 (
.a(ff1),
.b(ff3),
.c(tmp33)
);
qadd2 Add_u35 (
.a(ff5),
.b(ff7),
.c(tmp35)
);
qadd2 Add_u37 (
.a(ff9),
.b(ff11),
.c(tmp37)
);
qadd2 Add_u39 (
.a(ff13),
.b(ff15),
.c(tmp39)
);
qadd2 Add_u49 (
.a(tmp33),
.b(tmp35),
.c(tmp49)
);
qadd2 Add_u51 (
.a(tmp37),
.b(tmp39),
.c(tmp51)
);
qadd2 Add_u57 (
.a(tmp49),
.b(tmp51),
.c(tmp57)
);
endmodule
| 6.599206 |
module signedmul (
input clk,
input [15:0] a,
input [15:0] b,
output [15:0] c
);
wire [31:0] result;
wire [15:0] a_new;
wire [15:0] b_new;
reg [15:0] a_ff;
reg [15:0] b_ff;
reg [31:0] result_ff;
reg a_sign, b_sign, a_sign_ff, b_sign_ff;
assign c = (b_sign_ff == a_sign_ff) ? result_ff[26:12] : (~result_ff[26:12] + 1'b1);
assign a_new = a[15] ? (~a + 1'b1) : a;
assign b_new = b[15] ? (~b + 1'b1) : b;
assign result = a_ff * b_ff;
always @(posedge clk) begin
a_ff <= a_new;
b_ff <= b_new;
a_sign <= a[15];
b_sign <= b[15];
a_sign_ff <= a_sign;
b_sign_ff <= b_sign;
result_ff <= result;
end
endmodule
| 6.6402 |
module qadd2 (
input [15:0] a,
input [15:0] b,
output [15:0] c
);
assign c = a + b;
endmodule
| 7.287735 |
module dpram (
input clk,
input [4:0] address_a,
input [4:0] address_b,
input wren_a,
input wren_b,
input [(`VECTOR_BITS-1):0] data_a,
input [(`VECTOR_BITS-1):0] data_b,
output reg [(`VECTOR_BITS-1):0] out_a,
output reg [(`VECTOR_BITS-1):0] out_b
);
`ifdef SIMULATION_MEMORY
reg [`VECTOR_BITS-1:0] ram[`NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.613656 |
module dpram_t (
input clk,
input [5:0] address_a,
input [5:0] address_b,
input wren_a,
input wren_b,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_a,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_b,
output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_a,
output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_b
);
`ifdef SIMULATION_MEMORY
reg [(`NUM_WORDS*`DATA_WIDTH)-1:0] ram[`VECTOR_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.034874 |
module dpram_small (
input clk,
input [8:0] address_a,
input [8:0] address_b,
input wren_a,
input wren_b,
input [`DATA_WIDTH-1:0] data_a,
input [`DATA_WIDTH-1:0] data_b,
output reg [`DATA_WIDTH-1:0] out_a,
output reg [`DATA_WIDTH-1:0] out_b
);
`ifdef SIMULATION_MEMORY
reg [`DATA_WIDTH-1:0] ram[`OUT_RAM_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.64722 |
module wordwise_bram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`BUF_AWIDTH-1:0] addr0;
input [`BUF_AWIDTH-1:0] addr1;
input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0;
input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1;
input [`BUF_LOC_SIZE-1:0] we0;
input [`BUF_LOC_SIZE-1:0] we1;
output reg [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q0;
output reg [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q1;
input clk;
`ifdef SIMULATION_MEMORY
reg [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] ram[((1<<`BUF_AWIDTH)-1):0];
reg [3:0] i;
always @(posedge clk) begin
if (we0 == 0) begin //read
for (i = 0; i < `BUF_LOC_SIZE; i = i + 1) begin
q0[i*`DATA_WIDTH+:`DATA_WIDTH] <= ram[addr0][i*`DATA_WIDTH+:`DATA_WIDTH];
end
end else begin //write
for (i = 0; i < `BUF_LOC_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0][i*`DATA_WIDTH+:`DATA_WIDTH] <= d0[i*`DATA_WIDTH+:`DATA_WIDTH];
end
end
end
always @(posedge clk) begin
if (we1 == 0) begin
for (i = 0; i < `BUF_LOC_SIZE; i = i + 1) begin
q1[i*`DATA_WIDTH+:`DATA_WIDTH] <= ram[addr1][i*`DATA_WIDTH+:`DATA_WIDTH];
end
end else begin
for (i = 0; i < `BUF_LOC_SIZE; i = i + 1) begin
if (we1[i]) ram[addr1][i*`DATA_WIDTH+:`DATA_WIDTH] <= d1[i*`DATA_WIDTH+:`DATA_WIDTH];
end
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.506854 |
module wordwise_bram_2 (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input addr0;
input addr1;
input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0;
input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1;
input [8*`BUF_LOC_SIZE-1:0] we0;
input [8*`BUF_LOC_SIZE-1:0] we1;
output reg [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q0;
output reg [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q1;
input clk;
`ifdef SIMULATION_MEMORY
reg [(8*`BUF_LOC_SIZE*`DATA_WIDTH)-1:0] ram[1:0]; //ping pong buffer
reg [5:0] i;
always @(posedge clk) begin
if (we0 == 0) begin //read
for (i = 0; i < `NUM_WORDS; i = i + 1) begin
q0[i*`DATA_WIDTH+:`DATA_WIDTH] <= ram[addr0][i*`DATA_WIDTH+:`DATA_WIDTH];
end
end else begin //write
for (i = 0; i < `NUM_WORDS; i = i + 1) begin
if (we0[i]) ram[addr0][i*`DATA_WIDTH+:`DATA_WIDTH] <= d0[i*`DATA_WIDTH+:`DATA_WIDTH];
end
end
end
always @(posedge clk) begin
if (we1 == 0) begin
for (i = 0; i < `NUM_WORDS; i = i + 1) begin
q1[i*`DATA_WIDTH+:`DATA_WIDTH] <= ram[addr1][i*`DATA_WIDTH+:`DATA_WIDTH];
end
end else begin
for (i = 0; i < `NUM_WORDS; i = i + 1) begin
if (we1[i]) ram[addr1][i*`DATA_WIDTH+:`DATA_WIDTH] <= d1[i*`DATA_WIDTH+:`DATA_WIDTH];
end
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.506854 |
module
//============================================================================
module fixed_point_addsub(
clk,
rst,
a,
b,
operation, // 0 add, 1 sub
result,
flags
);
// Clock and reset
input clk ; // Clock signal
input rst ; // Reset (active high, resets pipeline registers)
// Input ports
input [`DATAWIDTH-1:0] a ; // Input A, a 32-bit floating point number
input [`DATAWIDTH-1:0] b ; // Input B, a 32-bit floating point number
input operation ; // Operation select signal
// Output ports
output reg [`DATAWIDTH-1:0] result ; // Result of the operation
output [4:0] flags ; // Flags indicating exceptions according to IEEE754
reg [`DATAWIDTH:0] result_t ;
wire [`DATAWIDTH-1:0] b_t ;
assign b_t = ~b + 1;
always@(*) begin
if (operation == 1'b0) begin
result_t = a + b;
end
else begin
result_t = a + b_t;
end
end
always @ (*) begin
if (result_t[16] == 1'b1 && operation == 1'b0) begin
result = 16'h7000;
end
else if (result_t[16] == 1'b1 && operation == 1'b1) begin
result = 16'h8000;
end
else begin
result = result_t[15:0];
end
end
// Pipeline Registers
//reg [79:0] pipe_1; // Pipeline register PreAlign->Align1
endmodule
| 7.574158 |
module
//============================================================================
module comparator(
a,
b,
aeb,
aneb,
alb,
aleb,
agb,
ageb,
unordered
);
input [15:0] a;
input [15:0] b;
output aeb;
output aneb;
output alb;
output aleb;
output agb;
output ageb;
output unordered;
reg lt;
reg eq;
reg gt;
wire [15:0] a_t;
wire [15:0] b_t;
assign a_t = (~a[15:0])+1;
assign b_t = (~b[15:0])+1;
always @(*) begin
if (a[15] == 1'b0 && b[15] == 1'b1) begin
if (a != b) begin
eq = 1'b0;
lt = 1'b0;
gt = 1'b1;
end
else begin
eq = 1'b1;
lt = 1'b0;
gt = 1'b0;
end
end
else if (a[15] == 1'b1 && b[15] == 1'b0) begin
if (a != b) begin
lt = 1'b1;
gt = 1'b0;
eq = 1'b0;
end
else begin
lt = 1'b0;
gt = 1'b0;
eq = 1'b1;
end
end
else if (a[15] == 1'b0 && b[15] == 1'b0) begin
if (a > b) begin
lt = 1'b0;
gt = 1'b1;
eq = 1'b0;
end
else if (a < b) begin
lt = 1'b1;
gt = 1'b0;
eq = 1'b0;
end
else begin
lt = 1'b0;
gt = 1'b0;
eq = 1'b1;
end
end
else if (a[15] == 1'b1 && b[15] == 1'b1) begin
if (a_t > b_t) begin
lt = 1'b1;
gt = 1'b0;
eq = 1'b0;
end
else if (a_t < b_t) begin
lt = 1'b0;
gt = 1'b1;
eq = 1'b0;
end
else begin
lt = 1'b0;
gt = 1'b0;
eq = 1'b1;
end
end
end
//Result flags
assign aeb = eq;
assign aneb = ~eq;
assign alb = lt;
assign aleb = lt | eq;
assign agb = gt;
assign ageb = gt | eq;
endmodule
| 7.574158 |
module align_t (
input [15:0] input_a,
output [15:0] a_m,
output [5:0] a_e,
output a_s
);
wire [15:0] a;
assign a = input_a;
assign a_m[15:5] = {1'b1, a[9 : 0]};
assign a_m[4:0] = 8'b0;
assign a_e = a[14 : 10] - 15;
assign a_s = a[15];
endmodule
| 6.666471 |
module sub_t (
input [5:0] a_e,
output [5:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 7.30096 |
module am_shift_t (
input [5:0] a_e,
input [5:0] sub_a_e,
input [15:0] a_m,
output reg [27:0] a_m_shift
);
always @(a_e or sub_a_e or a_m) begin
if (a_e <= 15 && a_e >= 0) begin
a_m_shift = {a_m, 12'b0} >> sub_a_e;
end else begin
a_m_shift = 24'h0;
end
end
endmodule
| 7.742958 |
module two_comp_t (
input [27:0] a_m_shift,
input a_s,
output [27:0] z
);
assign z = a_s ? -a_m_shift : a_m_shift; // 2's complement
endmodule
| 7.926771 |
module int_to_float_fp16 (
input_a,
output_z
);
input [15:0] input_a;
output [15:0] output_z;
wire [15:0] value;
wire z_s;
wire [4:0] tmp_cnt;
wire [4:0] sub_a_e;
wire [4:0] sub_z_e;
wire [15:0] a_m_shift;
wire [10:0] z_m_final;
wire [4:0] z_e_final;
//wire [31:0] z;
align dut_align (
input_a,
value,
z_s
);
lzc dut_lzc (
value,
tmp_cnt
);
sub dut_sub (
tmp_cnt,
sub_a_e
);
sub2 dut_sub2 (
sub_a_e,
sub_z_e
);
am_shift dut_am_shift (
value,
sub_a_e,
a_m_shift
);
exception dut_exception (
a_m_shift,
sub_z_e,
z_m_final,
z_e_final
);
final_out dut_final_out (
input_a,
z_m_final,
z_e_final,
z_s,
output_z
);
endmodule
| 6.791028 |
module align (
input [15:0] a,
output [15:0] value,
output z_s
);
assign value = a[15] ? -a : a;
assign z_s = a[15];
endmodule
| 7.456157 |
module align2 (
input [31:0] value,
output [31:0] z_m,
//output [7:0] z_r,
//output [7:0] z_e);
//z_e <= 8'd31;
z_m <= value[31:0];
//z_r <= value[7:0];
endmodule
| 7.185384 |
module lzc (
input [15:0] z_m,
output reg [4:0] tmp_cnt_final
);
wire [15:0] Sj_int;
//wire [15:0] val32;
wire [ 7:0] val8;
wire [ 3:0] val4;
wire [ 4:0] tmp_cnt;
assign Sj_int = z_m;
assign tmp_cnt[4] = 1'b0;
assign tmp_cnt[3] = (Sj_int[15:8] == 8'b0);
assign val8 = tmp_cnt[3] ? Sj_int[7:0] : Sj_int[15:8];
assign tmp_cnt[2] = (val8[7:4] == 4'b0);
assign val4 = tmp_cnt[2] ? val8[3:0] : val8[7:4];
assign tmp_cnt[1] = (val4[3:2] == 2'b0);
assign tmp_cnt[0] = tmp_cnt[1] ? ~val4[1] : ~val4[3];
always @(Sj_int or tmp_cnt) begin
if (Sj_int[15:0] == 16'b0) tmp_cnt_final = 5'd16;
else begin
tmp_cnt_final = tmp_cnt;
end
end
endmodule
| 7.161278 |
module sub2 (
input [4:0] a_e,
output [4:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 6.873213 |
module am_shift (
input [15:0] a_m,
input [ 4:0] tmp_cnt,
output [15:0] a_m_shift
);
assign a_m_shift = a_m << tmp_cnt;
endmodule
| 7.120022 |
module exception (
input [15:0] a_m_shift,
input [4:0] z_e,
output reg [10:0] z_m_final,
output reg [4:0] z_e_final
);
wire guard;
wire round_bit;
wire sticky;
wire [10:0] z_m;
assign guard = a_m_shift[4];
assign round_bit = a_m_shift[3];
assign sticky = a_m_shift[2:0] != 0;
assign z_m = a_m_shift[15:5];
always @(guard or round_bit or sticky or z_m or z_e) begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m_final = z_m + 1;
if (z_m == 11'b11111111111) begin
z_e_final = z_e + 1;
end else z_e_final = z_e;
end else begin
z_m_final = z_m;
z_e_final = z_e;
end
end
endmodule
| 7.768978 |
module final_out (
input [15:0] a,
input [10:0] z_m,
input [4:0] z_e,
input z_s,
output reg [15:0] output_z
);
always @(a or z_m or z_e or z_s) begin
if (a == 16'b0) begin
output_z = 16'b0;
end else begin
output_z[9:0] = z_m[9:0];
output_z[14:10] = z_e + 8'd3;
output_z[15] = z_s;
end
end
endmodule
| 6.677848 |
module adder_fp (
input clk,
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a + b;
endmodule
| 7.220012 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
assign bf16 = 1'b1; //hardcoding to 1, to avoid ODIN issue. a `ifdef here wasn't working. apparently, nested `ifdefs don't work
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
wire [ `MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {temp_0, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end
Lvl2[`MANTISSA:`MANTISSA-7] <= 0;
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end
Lvl3[`MANTISSA] <= 0;
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end
Lvl3[`MANTISSA:`MANTISSA-1] <= 0;
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end
Lvl3[`MANTISSA:`MANTISSA-2] <= 0;
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`DWIDTH:0];
// Rotate by 4
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`DWIDTH:0];
// Rotate by 1
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.