code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module asyn_128_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate... | 6.625995 |
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 a... | 7.068635 |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 a... | 6.909672 |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 a... | 6.909672 |
module asyn_256_64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw
);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output [7:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys t... | 6.699918 |
module asyn_32_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifnd... | 6.538429 |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [5:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys trans... | 7.598485 |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ... | 7.598485 |
module asyn_bridge_top #(
parameter ADDR_WD = 32,
parameter DATA_WD = 32,
parameter STRB_WD = 4,
parameter PROT_WD = 3
) (
input a_pclk,
input a_prst_n,
input a_psel,
input a_penable,
input a_pwrite,
input [ADDR_WD-1 : 0] a_pad... | 8.468535 |
module asyn_comp #(
parameter ADDR_WIDTH = 4
) (
input wire rst_n,
output wire asyn_full,
input wire [ADDR_WIDTH-1 : 0] w_ptr,
output wire asyn_empty,
input wire [ADDR_WIDTH-1 : 0] r_ptr
);
wire dirset;
wire dirclr;
assign dirset = (w_ptr[ADDR_WI... | 8.482329 |
module asyn_dff (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 6.700381 |
module asyn_dff_err_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 7.451812 |
module asyn_dff_err_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff_err_setup dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk... | 7.451812 |
module asyn_dff_good_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 6.5815 |
module asyn_dff_good_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
... | 6.5815 |
module asyn_dff_ok_setup (
clk,
rst,
d,
q
);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 7.351348 |
module asyn_dff_ok_setup_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
// Asynchronous DFF
asyn_dff_ok_setup dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
... | 7.351348 |
module asyn_dff_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_asyn_q;
//
// Asynchronous DFF
//
asyn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_asyn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
... | 7.014844 |
module asyn_dual_8x16ram (
d_out,
d_in,
clear,
wr_clk,
rd_clk,
we,
re,
wr_addr,
rd_addr
);
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
output reg [DATA_WIDTH-1:0] d_out;
input [DATA_WIDTH-1:0] d_in;
input [DATA_ADDR-1:0] wr_addr, rd_addr;
input clear, wr_cl... | 7.537807 |
module asyn_dual_8x16ram_tb ();
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
reg [DATA_WIDTH-1:0] d_in;
reg [DATA_ADDR-1:0] wr_addr, rd_addr;
reg clear, wr_clk, rd_clk, we, re;
wire [DATA_WIDTH-1:0] d_out;
asyn_dual_8x16ram DUT (
d_out,
d_in,
clear,
wr_clk,
rd_... | 7.537807 |
module asyn_fifo_tb ();
parameter addr_size = 3, word_width = 8;
reg r_clk;
reg w_clk;
// read and write command
reg rd;
reg wr;
reg reset_n;
reg [word_width-1:0] data_in;
wire [word_width-1:0] data_out;
wire full;
wire empty;
asyn_fifo_top #(
.addr_size (addr_size),
.word_width(wo... | 8.204821 |
module asyn_fifo_top #(
parameter addr_size = 3,
word_width = 8
) (
input r_clk,
input w_clk,
// read and write command
input rd,
input wr,
input reset_n,
input [word_width-1:0] data_in,
output [word_width-1:0] data_out,
output full,
output empty
);
//declaration neede... | 8.621526 |
module Asyn_fifo_v1 #(
parameter DATA_SIZE = 8,
parameter ARRAY_SIZE = 4
) (
output [DATA_SIZE-1:0] rdata,
output wfull,
output rempty,
input [DATA_SIZE-1:0] wdata,
input winc,
wclk,
wrst_n,
input rinc,
rclk,
rrst_n
);
wire [ARRAY_SIZE-1:0] waddr, raddr;
wire [ARRAY... | 7.45862 |
module asyn_fifo_v2 #(
parameter DATA_WIDTH = 16,
ADDR_WIDTH = 4
) (
input wire reset_l,
input wire wr_clk, //дʱ
input wire wr_en, //дʹ
output wire full, //asyn_full == 0 ʾ 1ʾ
input wire [15:0] write_data, //д
input wire rd_clk,... | 8.554777 |
module async_fifo_tb;
reg rst;
reg wr_clk;
reg wr_en;
reg [15:0] din;
reg rd_clk;
reg rd_en;
wire valid;
wire [15:0] dout;
wire empty;
wire full;
reg [15:0] test_cnt;
reg err;
async_fifo #(
.WIDTH(16),
.DEPTH(5)
) async_fifo_u (
.rst(rst),
.wr_clk(wr_clk),
... | 6.523155 |
module ASYN_RESET (
input clk,
input rst_n,
input in,
output reg out
);
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0) out <= 1'b0;
else out <= in;
endmodule
| 7.287386 |
module ASYN_RESET_SYN_RELEASE_T;
reg clk;
reg rst_n;
wire rst_n_syn;
always #5 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b1;
#2 rst_n = 1'b0;
#15 rst_n = 1'b1;
#25 rst_n = 1'b0;
#25 $stop;
end
ASYN_RESET_SYN_RELEASE ASYN_RESET_SYN_RELEASE_T (
.clk(clk),
.... | 7.563577 |
module ASYN_RESET_SYN_RELEASE (
input clk,
input rst_n,
output reg rst_n_syn
);
reg rst_n_d1;
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0) {rst_n_syn, rst_n_d1} <= 2'b00;
else {rst_n_syn, rst_n_d1} <= {rst_n_d1, 1'b1};
endmodule
| 7.563577 |
module asyn_single_8x16ram (
data,
addr_in,
we_in,
en_in
);
parameter DATA_WIDTH = 16, DATA_DEPTH = 8, DATA_ADDR = 3;
input we_in, en_in;
input [DATA_ADDR-1:0] addr_in;
inout [DATA_WIDTH-1:0] data;
reg [DATA_WIDTH-1:0] ram[0:DATA_DEPTH-1];
always @(data, we_in, en_in, addr_in) begin
... | 6.707116 |
module asyn_single_8x16ram_tb();
wire [15:0] data;
reg [2:0] addr_in;
reg we_in,en_in;
reg [15:0] tempd;
integer l;
asyn_single_8x16ram DUT(data,addr_in,we_in,en_in);
assign data=(we_in && !en_in) ? tempd : 8'hzz;
task initialize();
begin
we_in=1'b0; en_in=1'b0; tempd=8'h00;
... | 6.707116 |
module asyn_spram_4x1 (
clk,
addr_0,
addr_1,
d_in,
wr_en,
d_out
);
input wire clk;
input wire addr_0;
input wire addr_1;
input wire d_in;
input wire wr_en;
output wire d_out;
wire [1:0] addr;
reg [3:0] mem;
assign addr = {addr_1, addr_0};
assign d_out = (addr == 2'd0)? me... | 7.132512 |
module asy_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 ac... | 6.563891 |
module asy_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef A... | 6.77794 |
module Asy_Rst_Syn (
input clk_50m,
input rst_n,
output asy_rst_n
);
//----------------------------------------------
reg [1:0] rst_shift;
always @(posedge clk_50m or negedge rst_n) begin
if (!rst_n) rst_shift[1:0] <= 2'b00;
else rst_shift[1:0] <= {rst_shift[0], 1'b1};
end
assign as... | 8.242034 |
module as_reg16b (
input [ 8:0] address,
output [15:0] result
);
reg [15:0] int_reg[511:0];
assign result = int_reg[address];
initial $readmemh("microcode.txt", int_reg);
endmodule
| 6.874577 |
module ata (
input CLK,
input AS,
input RW,
input [23:0] A,
input WAIT,
output [1:0] IDECS,
output IOR,
output IOW,
output DTACK,
output ACCESS
);
/* Timing Diagram
S0 S1 S2 S3 S4 S5 W W S6 S7
__ ... | 6.974379 |
module ATAN_ROM - ROM pre-loaded with the arctangent( 2^-i )
Summary
This module implements the arc-tangent lookup-table (a ROM) required
for the sequential CORDIC module. The initialization datafile is located
in folder ../simdata is created by the Matlab program ../matlab/genatanlut.m
Two data files can be ... | 8.408436 |
module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
data_a,
byteena_a,
wren_b,
data_b,
byteena_b,
q_b,
q_a
);
parameter width_a = 1'd0;
parameter widthad_a = 1'd0;
parameter numwords_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_b = 1'd0;
parameter l... | 8.296277 |
module tb;
reg t_a;
reg t_b;
wire t_w, t_x, t_y, t_z;
//instatiate
and1 a1 (
.a(t_a),
.b(t_b),
.w(t_w),
.x(t_x),
.y(t_y),
.z(t_z)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb);
end
initial begin
$monitor(t_a, t_b, t_w, t_x, t_y, t_z); //displ... | 7.02078 |
module atkState (
input clk
, input game_clk
, input [4:0] direction
, input state
, input [2:0] monster
, output reset
, output [9:0] xPlayer
, output [9:0] yPlayer
, output [6:0] hpPlayer
, output [6:0] hpMonster
, output changeState
);
reg [9:0] xCurrent;
reg [9:0] yCu... | 6.548777 |
module atmega_eep #(
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_DATA_LEN = 8,
parameter EEARH_ADDR = 'h20,
parameter EEARL_ADDR = 'h21,
parameter EEDR_ADDR = 'h22,
parameter EECR_ADDR = 'h23,
parameter EEP_SIZE = 512
) (
input rst_i,
input clk_i,
input [BUS_ADDR_DATA_LEN-... | 6.706772 |
modules. */
/************************************************************/
`timescale 1ns / 1ps
module atmega_pio # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_DATA_LEN = 8,
parameter PORT_WIDTH = 8,
parameter USE_CLEAR_SET = "FALSE",
parameter PORT_OUT_ADDR = 'h00,
parameter DDR_ADDR = 'h03,
paramete... | 8.338405 |
module rtc #(
parameter PERIOD_STATIC = 0,
parameter CNT_SIZE = 10
) (
input rst_i,
input clk_i,
input clk_cnt_i,
input [CNT_SIZE - 1:0] top_i,
output int_o,
input int_ack_i
);
reg int_rst_int_p;
reg int_rst_int_n;
reg [CNT_SIZE-1:0] CNT;
always @(posedge clk_i or posedge rst_... | 7.350277 |
module atmega_eep # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_IO_LEN = 16,
parameter EEARH_ADDR = 0,
parameter EEARL_ADDR = 1,
parameter EEDR_ADDR = 2,
parameter EECR_ADDR = 3,
parameter EEP_SIZE = 512
)(
input rst,
input clk,
input [BUS_ADDR_IO_LEN-1:0]addr,
input wr,
input rd,
input [7:0]bus_in... | 6.549021 |
modules. */
/************************************************************/
`timescale 1ns / 1ps
module atmega_pio # (
parameter PLATFORM = "XILINX",
parameter BUS_ADDR_IO_LEN = 16,
parameter PORT_ADDR = 0,
parameter DDR_ADDR = 1,
parameter PIN_ADDR = 2,
parameter PINMASK = 8'hFF,
parameter PULLUP_MASK = 8'h0,... | 8.338405 |
module spi_sim(
);
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0]addr = 0;
reg [7:0]bus_in = 0;
wire [7:0]bus_out;
reg wr;
reg rd;
reg ss;
wire dat;
wire int;
reg int_rst;
initial begin
addr <= 0;
bus_in <= 8'h00;
ss <= 1'b1;
rd <= 1'b0;
wr <= 1'b0;
int_rst <= 1'b0;
wait(clk);
wait(~clk);
rs... | 6.780304 |
module atmega_tim_8bit_sim ();
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0] io_addr = 0;
reg [7:0] io_bus_in = 0;
reg io_wr;
reg io_rd;
reg [7:0] data_addr = 0;
reg [7:0] data_bus_in = 0;
reg data_wr;
reg data_rd;
wire tov_int;
reg tov_int_rst;
wire ocra_int;
reg ocra_in... | 6.911264 |
module atmega_tim_8bit_sim ();
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0] io_addr = 0;
reg [7:0] io_bus_in = 0;
reg io_wr;
reg io_rd;
reg [7:0] data_addr = 0;
reg [7:0] data_bus_in = 0;
wire [7:0] data_bus_out;
reg data_wr;
reg data_rd;
wire tov_int;
reg tov_int_rst;
w... | 6.911264 |
module PasswordAndIdChecker (
Password,
ID,
IndexOutput,
PassAuthorized
);
input [7:0] Password;
input wire [7:0] ID;
output reg PassAuthorized;
output reg [3:0] IndexOutput;
reg [7:0] authorized_passwords_ROM[0:9];
reg [7:0] authorized_id_ROM[0:9];
parameter OFF = 1'b0;
parameter ON = ... | 6.822896 |
module PasswordAndIdCheckerTESTBENCH ();
wire PassAuthorized;
wire [3:0] IndexOutput;
reg [7:0] ID;
reg [7:0] Password;
PasswordAndIdChecker somerandomname (
Password,
ID,
IndexOutput,
PassAuthorized
);
initial begin
// no currect pass no currect id
ID = 8'b1111000... | 6.822896 |
module AtoD_analog (
cosSAR,
sinSAR,
ana_cos,
ana_sin,
smpl,
gt_cos,
gt_sin
);
input [11:0] cosSAR, sinSAR;
// from A2D digital, acts as DAC input
input [11:0] ana_cos, ana_sin;
// 12-bit representation of analog input
input smpl;
// sample input from A2D digital
output gt_co... | 7.916269 |
module atomicity (
clk, //INPUT
pc, //INPUT
irq,
//pc_en,
reset //OUTPUT
);
input clk;
input [15:0] pc;
input irq;
//input pc_en;
output reset;
// FSM States //////////////////////////////////////////////////////////
parameter notRC = 3'b000;
parameter fstRC = 3'b001;
pa... | 7.171265 |
module delreg_varbits_vardel #(
parameter data_width = 64,
clock_cycles = 16
) (
input clk,
input en,
input [data_width-1 : 0] data_in,
output reg [data_width-1 : 0] data_out = {data_width * 1'b0}
);
reg [clock_cycles-1:0] shift_reg[data_width-1:0];
integer srl_index;
initial
for (s... | 6.902147 |
module atri_event_fifo (
input clk_i,
inout [`EVIF_SIZE-1:0] interface_io
);
wire fifo_clk_o = clk_i;
wire irs_clk_i;
wire fifo_full_o;
wire fifo_empty_o;
wire fifo_wr_i;
wire fifo_rd_i;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [1:0] type_i;
wire [1:0] type_o;
wire prog_empty_o = 0;
w... | 6.732884 |
module atri_i2c_rom (
input clk,
output [17:0] instruction,
input [9:0] address,
output reset,
input jump_wr_stb,
input [7:0] ram_data_in,
output [7:0] ram_data_out,
input [7:0] ram_address,
input ram_wr_stb
);
wire WEA = ram_wr_stb | jump_wr_stb;
wire [10:0] ADDRA = (jump_wr_st... | 7.436585 |
module atri_readout_rom (
input clk,
output [17:0] instruction,
input [9:0] address
);
wire [31:0] doa;
wire [ 3:0] dopa;
RAMB16BWER #(
.DATA_WIDTH_A(18),
.DATA_WIDTH_B(0),
`include "atrireadout_rom.vh"
) bram (
.CLKA (clk),
.WEA (1'b0),
.ENA (1'b1),
.AD... | 7.030736 |
module atri_samplemon_rom (
input clk,
output [17:0] instruction,
input [9:0] address
);
wire [31:0] doa;
wire [ 3:0] dopa;
RAMB16BWER #(
.DATA_WIDTH_A(18),
.DATA_WIDTH_B(0),
`include "atrisamplemon_rom.vh"
) bram (
.CLKA (clk),
.WEA (1'b0),
.ENA (1'b1),
... | 7.253228 |
module atri_sample_monitor (
input clk_i,
input rst_i,
input en_i,
input [3:0] sample_mon_i,
input sync_i,
input sst_i,
output [7:0] irs1_mon_o,
output [7:0] irs2_mon_o,
output [7:0] irs3_mon_o,
output [7:0] irs4_mon_o,
output [52:0] debug_o
);
// screw this, we just use a... | 6.558939 |
module atr_controller (
input clk_i,
input rst_i,
input [5:0] adr_i,
input [3:0] sel_i,
input [31:0] dat_i,
output reg [31:0] dat_o,
input we_i,
input stb_i,
input cyc_i,
output reg ack_o,
input run_rx,
input run_tx,
output [31:0] ctrl_lines
);
reg [ 3:0] state;
... | 8.146591 |
module atr_controller16 (
input clk_i,
input rst_i,
input [5:0] adr_i,
input [1:0] sel_i,
input [15:0] dat_i,
output reg [15:0] dat_o,
input we_i,
input stb_i,
input cyc_i,
output reg ack_o,
input run_rx,
input run_tx,
output [31:0] ctrl_lines
);
reg [3:0] state;
... | 8.146591 |
module attack_ind (
clk,
gameClk, // auto driven by gameclk
x,
y,
rgb,
damage
);
parameter BUS_WIDTH = 12;
parameter TOP = 330;
parameter LEFT = 240;
parameter RIGHT = 400;
parameter THICCNESS = 3;
parameter HEIGHT = 30;
input wire clk;
input wire gameClk; // auto driven by ga... | 6.727504 |
module attack_shift_amount (
input clock,
input reset,
input [3:0] attack_value,
output [3:0] shift_amount,
output done
);
wire [31:0] count_up_to;
attack_rom ar0 (
clock,
attack_value,
count_up_to
);
wire enable;
rate_divider rd0 (
clock,
reset,
count... | 7.295944 |
module shift_amount_reducer (
clock,
reset,
enable,
shift_amount,
shift_done
);
input clock;
input reset;
input enable;
output reg [3:0] shift_amount;
output reg shift_done;
always @(posedge clock) begin
if (reset) begin
shift_done <= 0;
shift_amount <= 4'd15;
end ... | 6.646294 |
module atta_system #(
parameter firmware_file = "../../firmware/MMX.hex",
parameter firmware_ram_depth = 65536 // 64KB
) (
input clk_i,
input rst_i,
// picorv signals
output trap_o,
output trace_valid_o,
output [35:0] trace_data_o,
output mem_ins... | 7.562774 |
module atta_tb #(
parameter VERBOSE = 0
);
reg clk = 1;
reg rst_n = 0;
wire trap;
always #5 clk = ~clk;
wire rst = ~rst_n;
initial begin
repeat (100) @(posedge clk);
rst_n <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, ... | 7.154119 |
module atta_top #(
parameter firmware_file = "../../firmware/MMX.hex"
) (
input sysclk_i,
output [4:0] gpio_led_o
);
wire clk_100;
wire locked;
// Should be more robust than this, but it will do for now
wire rst = ~locked;
sys_clk #(
.DIFF_CLKIN ("FALSE"),
.CLKIN_PERIOD(10.00... | 6.523119 |
module divideby8 (
input [`DATA_WIDTH-1:0] data,
output reg [`DATA_WIDTH-1:0] out
);
reg [`DATA_WIDTH-1:0] mask;
always @(*) begin
if (data[`DATA_WIDTH-1] == 1) mask = 16'b1110000000000000;
else mask = 0;
out = mask | (data >> 3);
end
endmodule
| 7.698216 |
module vecmat_add_32 #(
parameter arraysize = 512,
parameter vectdepth = 32
) (
input clk,
reset,
input [arraysize-1:0] mulout,
output reg [15:0] data_out
);
wire [15:0] tmp0, tmp1 ,tmp2 ,tmp3 ,tmp4 ,tmp5 ,tmp6 ,tmp7 ,tmp8 ,tmp9 ,tmp10 ,tmp11 ,tmp12 ,tmp13 ,tmp14 ,tmp15 ,tmp16 ,tmp17 ,tmp18 ,... | 6.599206 |
module signedmul (
input clk,
input [15:0] a,
input [15:0] b,
output [15:0] c
);
wire [31:0] result;
wire [15:0] a_new;
wire [15:0] b_new;
reg [15:0] a_ff;
reg [15:0] b_ff;
reg [31:0] result_ff;
reg a_sign, b_sign, a_sign_ff, b_sign_ff;
assign c = (b_sign_ff == a_sign_ff) ? result_... | 6.6402 |
module qadd2 (
input [15:0] a,
input [15:0] b,
output [15:0] c
);
assign c = a + b;
endmodule
| 7.287735 |
module dpram (
input clk,
input [4:0] address_a,
input [4:0] address_b,
input wren_a,
input wren_b,
input [(`VECTOR_BITS-1):0] data_a,
input [(`VECTOR_BITS-1):0] data_b,
output reg [(`VECTOR_BITS-1):0] out_a,
output reg [(`VECTOR_BITS-1):0] out_b
);
`ifdef SIMULATION_MEMORY
reg ... | 7.613656 |
module dpram_t (
input clk,
input [5:0] address_a,
input [5:0] address_b,
input wren_a,
input wren_b,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_a,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_b,
output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_a,
output reg [((`NUM_WORDS*`DATA_WIDTH)... | 7.034874 |
module dpram_small (
input clk,
input [8:0] address_a,
input [8:0] address_b,
input wren_a,
input wren_b,
input [`DATA_WIDTH-1:0] data_a,
input [`DATA_WIDTH-1:0] data_b,
output reg [`DATA_WIDTH-1:0] out_a,
output reg [`DATA_WIDTH-1:0] out_b
);
`ifdef SIMULATION_MEMORY
reg [`DATA... | 7.64722 |
module wordwise_bram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`BUF_AWIDTH-1:0] addr0;
input [`BUF_AWIDTH-1:0] addr1;
input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0;
input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1;
input [`BUF_LOC_SIZE-1:0] we0;
input [`BUF_LOC_SIZE-1:0... | 6.506854 |
module wordwise_bram_2 (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input addr0;
input addr1;
input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0;
input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1;
input [8*`BUF_LOC_SIZE-1:0] we0;
input [8*`BUF_LOC_SIZE-1:0] we1;
output reg [8*`BU... | 6.506854 |
module
//============================================================================
module fixed_point_addsub(
clk,
rst,
a,
b,
operation, // 0 add, 1 sub
result,
flags
);
// Clock and reset
input clk ; // Clock signal
input rst ; // Reset (active high, resets pipeline registers... | 7.574158 |
module
//============================================================================
module comparator(
a,
b,
aeb,
aneb,
alb,
aleb,
agb,
ageb,
unordered
);
input [15:0] a;
input [15:0] b;
output aeb;
output aneb;
output alb;
output aleb;
output agb;
output ageb;
output unordered;
reg lt;
reg eq;
reg gt;
wire ... | 7.574158 |
module align_t (
input [15:0] input_a,
output [15:0] a_m,
output [5:0] a_e,
output a_s
);
wire [15:0] a;
assign a = input_a;
assign a_m[15:5] = {1'b1, a[9 : 0]};
assign a_m[4:0] = 8'b0;
assign a_e = a[14 : 10] - 15;
assign a_s = a[15];
endmodule
| 6.666471 |
module sub_t (
input [5:0] a_e,
output [5:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 7.30096 |
module am_shift_t (
input [5:0] a_e,
input [5:0] sub_a_e,
input [15:0] a_m,
output reg [27:0] a_m_shift
);
always @(a_e or sub_a_e or a_m) begin
if (a_e <= 15 && a_e >= 0) begin
a_m_shift = {a_m, 12'b0} >> sub_a_e;
end else begin
a_m_shift = 24'h0;
end
end
endmodule
| 7.742958 |
module two_comp_t (
input [27:0] a_m_shift,
input a_s,
output [27:0] z
);
assign z = a_s ? -a_m_shift : a_m_shift; // 2's complement
endmodule
| 7.926771 |
module int_to_float_fp16 (
input_a,
output_z
);
input [15:0] input_a;
output [15:0] output_z;
wire [15:0] value;
wire z_s;
wire [4:0] tmp_cnt;
wire [4:0] sub_a_e;
wire [4:0] sub_z_e;
wire [15:0] a_m_shift;
wire [10:0] z_m_final;
wire [4:0] z_e_final;
//wire [31:0] z;
align dut_align... | 6.791028 |
module align (
input [15:0] a,
output [15:0] value,
output z_s
);
assign value = a[15] ? -a : a;
assign z_s = a[15];
endmodule
| 7.456157 |
module align2 (
input [31:0] value,
output [31:0] z_m,
//output [7:0] z_r,
//output [7:0] z_e);
//z_e <= 8'd31;
z_m <= value[31:0];
//z_r <= value[7:0];
endmodule
| 7.185384 |
module lzc (
input [15:0] z_m,
output reg [4:0] tmp_cnt_final
);
wire [15:0] Sj_int;
//wire [15:0] val32;
wire [ 7:0] val8;
wire [ 3:0] val4;
wire [ 4:0] tmp_cnt;
assign Sj_int = z_m;
assign tmp_cnt[4] = 1'b0;
assign tmp_cnt[3] = (Sj_int[15:8] == 8'b0);
assign val8 = tmp_cnt[3] ? S... | 7.161278 |
module sub2 (
input [4:0] a_e,
output [4:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 6.873213 |
module am_shift (
input [15:0] a_m,
input [ 4:0] tmp_cnt,
output [15:0] a_m_shift
);
assign a_m_shift = a_m << tmp_cnt;
endmodule
| 7.120022 |
module exception (
input [15:0] a_m_shift,
input [4:0] z_e,
output reg [10:0] z_m_final,
output reg [4:0] z_e_final
);
wire guard;
wire round_bit;
wire sticky;
wire [10:0] z_m;
assign guard = a_m_shift[4];
assign round_bit = a_m_shift[3];
assign sticky = a_m_shift[2:0] != 0;
assign z_... | 7.768978 |
module final_out (
input [15:0] a,
input [10:0] z_m,
input [4:0] z_e,
input z_s,
output reg [15:0] output_z
);
always @(a or z_m or z_e or z_s) begin
if (a == 16'b0) begin
output_z = 16'b0;
end else begin
output_z[9:0] = z_m[9:0];
output_z[14:10] = z_e + 8'd3;
outp... | 6.677848 |
module adder_fp (
input clk,
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a + b;
endmodule
| 7.220012 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
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