code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module Audio_Final (
// Inputs
CLOCK_50,
KEY,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
I2C_SDAT,
// Outputs
AUD_XCK,
AUD_DACDAT,
I2C_SCLK,
SW
);
/*****************************************************************************
* ... | 7.310034 |
module Audio_Handle (
input clk_in,
input RST,
input [11:0] Audio_CH1,
input [11:0] Audio_CH2,
input [11:0] Move_Fre_SIG,
output [11:0] Module_SIG,
output [31:0] Fre_word
);
/***************************************************************************/
wire [11:0] AM_wave;
AM_Modulat... | 6.835094 |
module audio_I2S (
input [31:0] data_in,
input empty,
input BCLK,
input LRCLK,
output get_data,
output reg data_out
);
reg [4:0] state;
reg [4:0] data_count;
reg shift = 0;
always @(posedge BCLK) begin
if(!empty) // only run code if fifo has data available
begin
case (stat... | 7.138664 |
module audio_ice40_fc_eu (
// Global inputs
input clk,
input resetn,
// control
input [5:0] i_bias_addr,
input i_init_bias,
input i_shift, // shift cascade reg
// Data path
input i_run, //
input [15:0] i_din, // data input
input i_d... | 6.799895 |
module iir_1st_order #(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 15,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
) (
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2,
B1,
B2,
input signed [DATA_WIDTH - 1 : 0] ... | 7.067018 |
module iir_2nd_order #(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 14,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
) (
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2,
A3,
B1,
B2,
B3,
input signed [DATA... | 7.908545 |
module audio_input (
input i_clk,
input i_rst_n,
input i_analog_l,
input i_analog_r,
output o_cmpdac_l,
output o_cmpdac_r,
output [9:0] o_adcdt_l,
output [9:0] o_adcdt_r
);
deltaSigmaADC ADC_L (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
... | 6.695797 |
module audio_interp_sigma_delta #(
parameter W_IN = 16,
parameter W_OUT = 4,
parameter LOG_OVERSAMPLE = 5
) (
input wire clk,
input wire rst_n,
input wire clk_en,
input wire [ W_IN-1:0] sample_in,
output wire sample_in_rdy,
output reg [W_OUT-1:0] sample_out
);
reg [... | 6.867768 |
module audio_io (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
iAUD_ADCDAT,
oAUD_ADCLRCK,
iCLK_18_4,
iRST_N,
pulses,
linein
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Du... | 7.475181 |
module audio_key (
input rst, //reset input
input clk, //clock input
input key, //press the button to record,release button play
output reg record, //record ctrl for other module
output reg play, //play ctrl for other module
outpu... | 7.197223 |
module audio_loopback (
input wire sys_clk, //ϵͳʱӣƵ50MHz
input wire sys_rst_n, //ϵͳλ͵ƽЧ
input wire audio_bclk, //WM8978λʱ
input wire audio_lrc, //WM8978/Ҷʱ
input wire audio_adcdat, //WM8978ADC
output wire scl, //wm8978Ĵʱźscl
output wire audio_mclk, //WM8978ʱ,Ƶ12MHz
... | 6.950306 |
module dac (
DACout,
DACin,
Clk,
Reset
);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder;... | 6.686484 |
module mixer (
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1_cha,
input wire [7:0] ay1_chb,
input wire [7:0] ay1_chc,
input wire [7:0] ay2_cha,
input wire [7:0] ay2_chb,
input wire [7:0] ay2_chc,
input wire [7:0]... | 6.918526 |
module audio_module (
CLOCK_50, /*KEY,*/
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
I2C_SCLK,
I2C_SDAT,
TD_CLK27,
TD_RESET_N
);
//////////// CLOCK //////////
input CLOCK_50;
//////////// KEY //////////
//input [3:0] KEY;
///////... | 6.712464 |
module audio_nios (
key_external_connection_export,
seg7_conduit_end_export,
pio_0_external_connection_export,
sw_external_connection_export,
i2c_scl_external_connection_export,
i2c_sda_external_connection_export,
audio_conduit_end_XCK,
audio_conduit_end_ADCDAT,
audio_conduit_end_ADC... | 6.832836 |
module audio_nios_DDR3_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "fa... | 7.526719 |
module audio_nios_DDR3_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wi... | 7.526719 |
module audio_nios_DDR3_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter R... | 7.526719 |
module audio_nios_DDR3_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have t... | 7.526719 |
module audio_nios_DDR3_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have the... | 7.526719 |
module audio_nios_DDR3_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
... | 7.526719 |
module audio_nios_DDR3_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0]... | 7.526719 |
module audio_nios_DDR3_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n... | 7.526719 |
module audio_nios_DDR3_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Sin... | 7.526719 |
module audio_nios_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 7.252384 |
module audio_nios_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;... | 7.252384 |
module audio_nios_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [3... | 7.252384 |
module audio_nios_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
inp... | 7.252384 |
module audio_nios_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input wr... | 6.978191 |
module audio_nios_mem_if_ddr3_emif_0_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to ... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to ""... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LA... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_... | 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastabi... | 7.34268 |
module audio_nios_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2.hex";
output [31:0] readdata;
input [16:0] address;
input [3... | 6.945362 |
module audio_nios_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2_1.hex";
output [31:0] readdata;
input [15:0] address;
inpu... | 6.945362 |
module audio_nios_onchip_memory2_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2_2.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] byteena... | 6.945362 |
module audio_nios_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output ... | 6.56724 |
module audio_nios_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1471402818 : 0;
endmodule
... | 6.583657 |
module audio_output (
input clk,
input reset,
input [31:0] data,
// clock_divider = (audio_clk / sampling_rate) - 1
// ex: (18MHz / 48000Hz) - 1 = 374
input [31:0] clock_divider,
input valid_toggle,
output full,
input ext_audio_clk,
input ... | 7.406687 |
module audio_out_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs... | 8.159243 |
module AUDIO_PLL_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency(... | 6.506107 |
module audio_post (
input clk, //
input i_init, //
input i_we, //
input [15:0] i_dout, //
output reg [15:0] o_diff, // diff between 1st and 2nd max value
output reg [ 2:0] o_max_idx, // index of maxium value, 111 is invalid
... | 8.050278 |
module audio_processing (
input clk,
input [7:0] cnt256_n,
input signed [15:0] ch1_in,
input signed [15:0] ch2_in,
output reg signed [15:0] ch1_out,
output reg signed [15:0] ch2_out
);
parameter ST_IDLE = 0;
parameter ST_CLIP_L = 1;
parameter ST_CLIP_R = 2;
reg [3:0] state;
reg signe... | 7.423247 |
module audio_processing_unit #(
parameter CLOCK_FREQ = 0,
parameter NOTE_TABLE_FILE = "",
parameter VIBRATO_TABLE_FILE = "",
parameter NOISE_TABLE_FILE = ""
) (
input wire i_clk,
input wire i_rst,
input wire [3:0] i_mixer,
output wire [8:0] o_sample,
output wire [3:0] ... | 7.423247 |
module audio_proc_top (
//////////////////////// Clock Input ////////////////////////
input CLOCK_27, // 27 MHz
input CLOCK_50, // 50 MHz
//////////////////////// Push Button ////////////////////////
input [ 3:0] KEY, // Pushbutton[3:0]
///////... | 6.799341 |
module Audio_PWM (
input clk_fm_demo_sampling,
input clk,
input RSTn,
input demod_en,
//input wire [9:0] demodulated_signal_downsample,
input wire [13:0] demodulated_signal_downsample,
output wire audio_pwm
);
//pwm generation simulate the DAC using 10bit range
reg [15:0] cnt = 0;... | 6.70848 |
module audio_rcv (
input wire audio_bclk, //WM8978λʱ
input wire sys_rst_n, //ϵͳλЧ
input wire audio_lrc, //WM8978/Ҷʱ
input wire audio_adcdat, //WM8978ADC
output reg [23:0] adc_data, //һνյ
output reg rcv_done //һݽ
);
//********************************************************... | 6.985246 |
module audio_rcv_ctrl (
input wire eth_rx_clk, //mii时钟,接收
input wire sys_rst_n, //复位信号，低电平有效
input wire audio_bclk, //音频位时钟
input wire audio_send_done, //wm8978音频接收使能信号
input wire rec_end, //单包数据接收完成信号
input wire rec_en, ... | 8.018809 |
module is to receive the audio input from WM8978 chip
*/
/*
this module is drived by the clk signal from WM 8978, since WM8978 chip is working in
a master mode this time. it will generate the bclk signal.
this module will be reset if reset button is pressed or the synchronization signal
aud_lrc has a rising or fallin... | 6.668641 |
module audio_record_play_ctrl (
input rst, //reset input
input clk, //clock input
input key, //press the button to record,release button play
input bclk, //audio bit clock
input daclrc, //DAC sample rate left ... | 6.914727 |
module Audio_Reset (
input clk, // BIT_CLK
input rst, // global reset
output AUDIO_RESET_Z, // AUDIO_RESET_Z FPGA pin
output audio_ready // ready signal to begin work on audio codec
);
parameter START = 2'd0; // start state, sets Audio_RESET_Z high ~.5 s
parameter RESET = 2'd1; // reset sta... | 7.545245 |
module audio_rx (
input rst,
input clk,
input sck_bclk, //audio bit clock
input ws_lrc, //ADC sample rate left right clock
input sdata, //ADC audio data
output reg [31:0] left_data, //left channel audio data ,ws_lrc = 1
... | 7.456006 |
module audio_send (
input wire audio_bclk, //WM8978λʱ
input wire sys_rst_n, //ϵͳλЧ
input wire audio_lrc, //WM8978/Ҷʱ
input wire [23:0] dac_data, //WM8978͵
output reg audio_dacdat, //DACDATݸWM8978
output reg send_done //һݷ
);
//*****************************... | 6.923222 |
module audio_send_ctrl (
input wire audio_bclk, //音频位时钟
input wire sys_rst_n, //复位信号
input wire rcv_done, //一次音频数据接受完成
input wire [23:0] adc_data, //一次接受的音频数据
input wire eth_tx_clk, //mii时钟,发送
input wire read_data_req, //读数据请求信号
in... | 8.164704 |
module Audio_Setup (
input clk, // BIT_CLK
input rst, // global reset
input shft_ready, // ready signal from shifter to codec
output [75:0] shft_data, // audio data to be sent to codec
output shft_load, // load signal to shifter to codec
output done // signal indicating audio codec has bee... | 7.011537 |
module audio_shifter (
input wire clk, //32MHz
input wire nreset,
input wire mix,
input wire [15-1:0] rdata,
input wire [15-1:0] ldata,
input wire exchan,
output wire aud_bclk,
output wire aud_daclrck,
output wire ... | 7.53662 |
module audio_spdif (
// Inputs
input clk_i
, input rst_i
, input audio_clk_i
, input inport_tvalid_i
, input [31:0] inport_tdata_i
, input [ 3:0] inport_tstrb_i
, input [ 3:0] inport_tdest_i
, input inport_tlast_i
// Outputs
, output inpo... | 7.572857 |
module audio_speak (
input sys_clk,
input sys_rst,
//WM978 interface
input aud_bclk, //bit clk
input aud_lrc, //synchronize signal
input aud_adcdat, //audio_input
output aud_mclk, //main clk signal for WM8978,generated by pll ip core
output aud_dacdat, //audio output
... | 6.861695 |
module AUDIO_SPI_CTL_RD (
input iRESET_n,
input iCLK_50,
output oDIN,
output oCS_n,
output oSCLK,
input iDOUT,
output [7:0] oDATA8,
//TEST
output reg CLK_1M,
output reg [ 7:0] ST,
output reg [ 7:0] COUNTER,
output reg [15:0] W_REG... | 6.862032 |
module AUDIO_SRCE (
input [15:0] EXT_DATA16,
output reg [15:0] DATA16_MIC,
input RESET_N,
input MCLK,
//output [15:0] DATA16_SIN ,
input SW_OBMIC_SIN,
input SAMPLE_TR,
output reg [7:0] ROM_ADDR,
output reg ROM_CK,
ou... | 7.494379 |
modulename>audio_synthesis</modulename>
/// <filedescription>Ƶϳɡ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// </version>
`timescale 10ns / 1ps
module audio_synthesis_t #
(
parameter resolution_input = 8,
parameter resolution_output = 16
)
(
output [resolution_output - 1 : 0] AUDIO_... | 6.915106 |
module audio_top (
input wire clk,
input wire rst_n,
// config
input wire mix,
// audio shifter
input wire [15-1:0] rdata,
input wire [15-1:0] ldata,
input wire exchan,
output wire aud_bclk,
output wire aud_daclrck,
... | 8.717327 |
module audio_tx (
input rst,
input clk,
input sck_bclk, //audio bit clock
input ws_lrc, //DAC sample rate left right clock
output reg sdata, //DAC audio data output
input [31:0] left_data, //left channel audio data,... | 7.491715 |
module wave_generator (
input wire clk,
input wire [15:0] freq,
output reg signed [9:0] wave_out
);
reg [5:0] i;
reg signed [7:0] amplitude[0:63];
reg [15:0] counter = 0;
initial begin
amplitude[0] = 0;
amplitude[1] = 7;
amplitude[2] = 13;
amplitude[3] = 19;
amplitude[4] = ... | 7.283079 |
module audio_wave #(
parameter BITS = 6
) (
input reset,
input clock,
input [1:0] form,
input [4:0] freq_id,
input new_f,
output reg [BITS-1:0] level
);
//parameters for types of waves
parameter SIN = 2'd0;
parameter TRI = 2'd1;
parameter SQ = 2'd2;
reg [9:0] index; //current sc... | 8.36702 |
module aud_buf
//
module aud_buf (aud_buffer_Data, aud_buffer_Q, aud_buffer_AlmostFull,
aud_buffer_Clock, aud_buffer_Empty, aud_buffer_Full, aud_buffer_RdEn,
aud_buffer_Reset, aud_buffer_WrEn) /* synthesis sbp_module=true */ ;
input [15:0]aud_buffer_Data;
output [15:0]aud_buffer_Q;
... | 6.863983 |
module instr_rom (
input logic clk,
rst_n,
input logic [13:0] i_addr,
output logic [31:0] o_data
);
localparam INSTR_CNT = 12'd25;
wire [0:INSTR_CNT-1][31:0] instr_rom_cell = {
32'h00002517, //0x00000000
32'h71c50513, //0x00000004
32'h004005ef, //0x00000008
32'h40b50533, //0x000... | 7.005566 |
module aukv_alu (
i_clk,
i_rstn,
i_operation,
i_rs1,
i_rs2,
o_rd,
i_cmp_a,
i_cmp_b,
i_cmp_sign,
o_lt,
o_ge,
o_eq,
o_ne
);
input i_clk;
input i_rstn;
input [3:0] i_operation;
input [31:0] i_rs1;
input [31:0] i_rs2;
output [31:0] o_rd;
input [31:0] i_cm... | 8.249171 |
module aukv_csr_regfile (
i_clk,
i_rstn,
i_exception_id,
i_exception,
i_pc,
i_instr,
i_wr_addr,
i_rd_addr,
i_data,
i_we,
i_rd,
i_op,
o_mtvec,
o_data
);
input i_clk;
input i_rstn;
input [7:0] i_exception_id;
input i_exception;
input [1:0] i_op;
i... | 6.746751 |
module aukv_fetch (
i_clk,
i_rstn,
i_instr_data,
i_instr_data_valid,
o_instr_addr,
o_instr_addr_valid,
i_stall,
i_branch_addr,
i_evec_addr,
i_branch_en,
i_exception,
o_pc,
o_instr,
o_instr_valid
);
input i_clk;
input i_rstn;
input [31:0] i_instr_data;
in... | 6.994719 |
module aukv_gpr_regfile (
i_clk,
i_rstn,
i_rs1_addr,
i_rs2_addr,
i_rd_addr,
i_we,
i_rd_data,
o_rs1data,
o_rs2data
);
input i_clk;
input i_rstn;
input [4:0] i_rs1_addr;
input [4:0] i_rs2_addr;
input [4:0] i_rd_addr;
input [31:0] i_rd_data;
input i_we;
output [31:0] o... | 7.974113 |
module aurora8_RESET_LOGIC (
//***********************************Port Declarations*******************************
// User I/O
input RESET,
USER_CLK,
INIT_CLK_P,
INIT_CLK_N //, GT_RESET_IN;
, input TX_LOCK_IN,
PLL_NOT_LOCKED,
output SYSTEM_RESET,
INIT_CLK_O,
output reg GT_RE... | 7.65897 |
module aurora_64b66b_1_DESCRAMBLER_64B66B #
(
parameter RX_DATA_WIDTH = 32
)
(
// User Interface
SCRAMBLED_DATA_IN,
UNSCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations**********... | 7.200193 |
module aurora_64b66b_1_SCRAMBLER_64B66B #
(
parameter TX_DATA_WIDTH = 32
)
(
// User Interface
UNSCRAMBLED_DATA_IN,
SCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations**************... | 7.200193 |
module aurora_64b66b_1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter BC = DATA_WIDTH>>3, //Byte count
parameter USE_4_NFC = 0, // 0 => PDU, 1 =>... | 7.200193 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to r... | 7.591032 |
module aurora_64b66b_1_common_logic_cbcc #
(
parameter BACKWARD_COMP_MODE1 = 1'b0 //disable check for interCB gap
)
(
input start_cb_writes_in,
input do_rd_en_in,
input bit_err_chan_bond_in,
input final_gater_for_fifo_din_in,
input any_vld_btf_in,
input start_cb_writes_lane1_in,
... | 7.200193 |
module monitors the GTX to detect hard
// errors. All errors are reported to the Global Logic Interface.
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_ERR_DETECT
(
// L... | 7.591032 |
module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_GLOBAL_LOGIC #
(
... | 8.183782 |
module aurora_64b66b_1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter BC = DATA_WIDTH >> 3, //Byte count
parameter RE... | 7.200193 |
module aurora_64b66b_1_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
LINK_RESET_IN,
POWER_DOWN,
FSM_RESETDONE,
SYSTEM_RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
... | 7.200193 |
module takes regular data in Aurora format
// and transforms it to LocalLink formatted data
//
//
//
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_RX_STREAM_DATAPATH
(
//Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
... | 6.652678 |
module aurora_64b66b_1_SUPPORT_RESET_LOGIC
(
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET... | 7.200193 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module auror... | 6.878357 |
module pipelines the data path in compliance
// with Local Link protocol. Provides data to Aurora Lane
// in the required format
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
modu... | 7.885372 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 16 from gtx to 32 into the aurora.
/////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_1_WIDT... | 6.595174 |
module aurora_64b66b_m_0_EXAMPLE_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC and 3 => USER K
parameter BC = DATA_WIDTH >> 3, //Byte c... | 7.200193 |
module aurora_64b66b_support_reset_logic
(
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET; ... | 7.200193 |
module aurora_64b66b_v7_3_DESCRAMBLER_64B66B #
(
parameter RX_DATA_WIDTH = 32
)
(
// User Interface
SCRAMBLED_DATA_IN,
UNSCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
ENABLE,
SYSTEM_RESET
);
//***********************************Port Declarations*****************... | 7.200193 |
module aurora_64b66b_v7_3_SCRAMBLER_64B66B #
(
parameter TX_DATA_WIDTH = 32
)
(
// User Interface
UNSCRAMBLED_DATA_IN,
SCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*************************... | 7.200193 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 64 bit clock from Aurora to 32/16 bit GTX. Width conversion is
// also required since the width of the Aurora interface is 8 bytes
// but t... | 6.595174 |
module aurora_64b66b_v7_3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TRE... | 7.200193 |
module aurora_64b66b_v7_3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire we,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `... | 7.200193 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module aurora_64b66b_v7_3_clock_enable_generator
(
// User IO
RESET,
USER_CLK,
ENABLE_32,
ENABLE_64
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
output ... | 7.200193 |
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