code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Audio_Final (
// Inputs
CLOCK_50,
KEY,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
I2C_SDAT,
// Outputs
AUD_XCK,
AUD_DACDAT,
I2C_SCLK,
SW
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input [0:0] KEY;
input [3:0] SW;
input AUD_ADCDAT;
// Bidirectionals
inout AUD_BCLK;
inout AUD_ADCLRCK;
inout AUD_DACLRCK;
inout I2C_SDAT;
// Outputs
output AUD_XCK;
output AUD_DACDAT;
output I2C_SCLK;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire audio_in_available;
wire [31:0] left_channel_audio_in;
wire [31:0] right_channel_audio_in;
wire read_audio_in;
wire audio_out_allowed;
wire [31:0] left_channel_audio_out;
wire [31:0] right_channel_audio_out;
wire write_audio_out;
// Internal Registers
reg [18:0] delay_cnt;
wire [18:0]delay;
reg snd;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge CLOCK_50)
if (delay_cnt == delay) begin
delay_cnt <= 0;
snd <= !snd;
end else delay_cnt <= delay_cnt + 1;
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign delay = {SW[3:0], 15'd3000};
wire [31:0] sound = (SW == 0) ? 0 : snd ? 32'd10000000 : -32'd10000000;
assign read_audio_in = audio_in_available & audio_out_allowed;
assign left_channel_audio_out = left_channel_audio_in + sound;
assign right_channel_audio_out = right_channel_audio_in + sound;
assign write_audio_out = audio_in_available & audio_out_allowed;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Audio_Controller Audio_Controller (
// Inputs
.CLOCK_50(CLOCK_50),
.reset (~KEY[0]),
.clear_audio_in_memory(),
.read_audio_in (read_audio_in),
.clear_audio_out_memory (),
.left_channel_audio_out (left_channel_audio_out),
.right_channel_audio_out (right_channel_audio_out),
.write_audio_out (write_audio_out),
.AUD_ADCDAT(AUD_ADCDAT),
// Bidirectionals
.AUD_BCLK (AUD_BCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.AUD_DACLRCK(AUD_DACLRCK),
// Outputs
.audio_in_available (audio_in_available),
.left_channel_audio_in (left_channel_audio_in),
.right_channel_audio_in (right_channel_audio_in),
.audio_out_allowed(audio_out_allowed),
.AUD_XCK (AUD_XCK),
.AUD_DACDAT(AUD_DACDAT),
);
avconf #(
.USE_MIC_INPUT(1)
) avc (
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT),
.CLOCK_50(CLOCK_50),
.reset (~KEY[0])
);
endmodule
| 7.310034 |
module Audio_Handle (
input clk_in,
input RST,
input [11:0] Audio_CH1,
input [11:0] Audio_CH2,
input [11:0] Move_Fre_SIG,
output [11:0] Module_SIG,
output [31:0] Fre_word
);
/***************************************************************************/
wire [11:0] AM_wave;
AM_Modulate #(
.INPUT_WIDTH (12),
.PHASE_WIDTH (32),
.OUTPUT_WIDTH(12)
) AM_Modulate_u (
.clk_in (clk_in),
.RST (RST),
.wave_in (Audio_CH2),
.modulate_deep(16'd32768), //(2^16-1)*percent
.center_fre (32'd858993), //(fre*4294967296)/clk_in/1000000 //10K
.AM_wave (AM_wave)
);
/***************************************************************************/
reg signed [11:0] Audio_SIG_r = 0;
always @(posedge clk_in) begin
if (RST) begin
Audio_SIG_r <= 12'd0;
end else begin
Audio_SIG_r <= $signed(Audio_CH1) + $signed(AM_wave);
end
end
assign Module_SIG = Audio_SIG_r;
reg signed [31:0] Carry_fre = 0;
always @(posedge clk_in) begin
if (RST) begin
Carry_fre <= 32'd0;
end else begin
Carry_fre <= $signed(Move_Fre_SIG) * $signed(20'd10486); //5M
end
end
reg [31:0] Fre_word_r = 0;
always @(posedge clk_in) begin
if (RST) begin
Fre_word_r <= 32'd0;
end else begin
Fre_word_r <= 32'd416611827 + $signed(Carry_fre);
end
end
assign Fre_word = Fre_word_r;
endmodule
| 6.835094 |
module audio_I2S (
input [31:0] data_in,
input empty,
input BCLK,
input LRCLK,
output get_data,
output reg data_out
);
reg [4:0] state;
reg [4:0] data_count;
reg shift = 0;
always @(posedge BCLK) begin
if(!empty) // only run code if fifo has data available
begin
case (state)
0: begin
if (LRCLK) state <= 1; // loop until LRCLK is high
end
1: begin
if (!LRCLK) begin // loop until LRCLK is low
shift <= 1;
data_count <= 5'd31;
state <= 2;
end
end
2: begin
if (data_count == 16) begin
shift <= 0;
if (LRCLK) begin
data_count <= 15;
shift <= 1;
state <= 3;
end
end else begin
data_count <= data_count - 5'd1;
end
end
3: begin
if (data_count == 0) begin
shift <= 0;
state <= 0;
end else data_count <= data_count - 5'd1;
end
default: state <= 0;
endcase
end
end
// clock data out on negedge of BCLK so it can be read on postive edge by TLV320
// request data just before falling edge of LRCLK
reg [5:0] get_count;
always @(negedge BCLK) begin
if (shift) data_out <= data_in[data_count];
else data_out <= 0;
if (!LRCLK) get_count <= 0;
else get_count <= get_count + 6'd1;
end
assign get_data = (get_count == 6'd30); // & !empty); // only request data if fifo is not empty
endmodule
| 7.138664 |
module audio_ice40_fc_eu (
// Global inputs
input clk,
input resetn,
// control
input [5:0] i_bias_addr,
input i_init_bias,
input i_shift, // shift cascade reg
// Data path
input i_run, //
input [15:0] i_din, // data input
input i_din_val, // data input valid
input [15:0] i_weight, // weight input
// cascade read out
input [15:0] i_cascade_in,
output reg [15:0] o_cascade_out // partial sum out
);
parameter ECP5_DEBUG = 0;
parameter BYTE_MODE = "DISABLE";
reg [15:0] din_latch;
reg [15:0] weight_latch;
reg [ 2:0] valid_d;
reg [ 1:0] run_d;
wire [39:0] w_bias_ext;
wire [15:0] r_bias;
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) run_d <= 2'b0;
else run_d <= {run_d[0], i_run};
end
always @(posedge clk) begin
if (i_run) begin
din_latch <= i_din_val ? i_din : 16'b0;
weight_latch <= i_weight;
valid_d <= {valid_d[1:0], i_din_val};
end else begin
din_latch <= 16'b0;
weight_latch <= 16'b0;
valid_d <= 3'b0;
end
end
reg [39:0] accu;
wire [31:0] mult;
generate
if (ECP5_DEBUG == 1) begin : g_on_ecp5_debug
mul u_mul16 (
.Clock (clk),
.ClkEn (1'b1),
.Aclr (~resetn),
.DataA (din_latch),
.DataB (weight_latch),
.Result(mult)
);
end else begin
ice40_mul16_reg u_mul16 (
.Clock (clk),
.ClkEn (1'b1),
.Aclr (~resetn),
.DataA (din_latch),
.DataB (weight_latch),
.Result(mult)
);
end
endgenerate
always @(posedge clk) begin
if (i_init_bias) accu <= w_bias_ext;
else if (valid_d[1]) accu <= accu + {{8{mult[31]}}, mult};
end
wire overflow;
assign overflow = (BYTE_MODE == "DISABLE") ? ((|accu[39:30]) != 1'b0) && ((&accu[39:30]) != 1'b1) :
((|accu[39:26]) != 1'b0) ; // unsigned
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) o_cascade_out <= 16'b0;
else if (run_d == 2'b10)
// Apply relu
// input 0.15, weight 5.10 --> accu 6.25, output 5.10(signed 16bit) / 1.7(unsigned)
o_cascade_out <= accu[39] ? 16'b0 : overflow ? {accu[39], {15{~accu[39]}}} :
(BYTE_MODE == "DISABLE") ? accu[30:15] : {8'b0, accu[25:18]};
else if (i_shift) o_cascade_out <= i_cascade_in;
end
assign r_bias = 16'b0; // preliminary 0 bias assumed
assign w_bias_ext = {{14{r_bias[15]}}, r_bias, 10'b0};
endmodule
| 6.799895 |
module iir_1st_order #(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 15,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
) (
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2,
B1,
B2,
input signed [DATA_WIDTH - 1 : 0] in,
output [DATA_WIDTH - 1:0] out
);
reg signed [DATA_WIDTH-1:0] x0, x1, y0;
reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32;
reg [COUNT_BITS - 1:0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass
// assuming 106528Hz sample rate.
//
// The Matlab output is:
// B = [0.093863 0.093863]
// A = [1.00000 -0.81227]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
//
// B = [3076 3076]
// A = [32768 -26616]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076
// B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768
//
// Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0
assign out = y0;
always @(*) begin
out32 <= (B1 * x0 + B2 * x1) - A2 * y0; //Previous output is y0 not y1
end
always @(posedge clk) begin
if (reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
y0 <= 0;
end else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y0 <= {out32[DATA_WIDTH+COEFF_WIDTH-1], out32[COEFF_SCALE+DATA_WIDTH-2 : COEFF_SCALE]};
x1 <= x0;
x0 <= in;
end
end
end
endmodule
| 7.067018 |
module iir_2nd_order #(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 14,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
) (
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2,
A3,
B1,
B2,
B3,
input signed [DATA_WIDTH - 1 : 0] in,
output [DATA_WIDTH - 1 : 0] out
);
reg signed [DATA_WIDTH-1 : 0] x0, x1, x2;
reg signed [DATA_WIDTH-1 : 0] y0, y1;
reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32;
reg [COUNT_BITS : 0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass
// assuming 48000Hz sample rate.
//
// Output is:
// B = [ 0.072231 0.144462 0.072231]
// A = [1.00000 -1.10923 0.39815]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
// Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits.
//
// B = [1183 2367 1183]
// A = [16384 -18174 6523]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183
// B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384
//
// Sample frequency is "clk rate/div"
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation:
// out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1);
assign out = y0;
always @(*) begin
out32 <= (B1 * x0 + B2 * x1 + B3 * x2) - (A2 * y0 + A3 * y1); //Previous output is y0 not y1
end
always @(posedge clk) begin
if (reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
x2 <= 0;
y0 <= 0;
y1 <= 0;
end else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y1 <= y0;
y0 <= {out32[DATA_WIDTH+COEFF_WIDTH-1], out32[(DATA_WIDTH+COEFF_SCALE-2) : COEFF_SCALE]};
x2 <= x1;
x1 <= x0;
x0 <= in;
end
end
end
endmodule
| 7.908545 |
module audio_input (
input i_clk,
input i_rst_n,
input i_analog_l,
input i_analog_r,
output o_cmpdac_l,
output o_cmpdac_r,
output [9:0] o_adcdt_l,
output [9:0] o_adcdt_r
);
deltaSigmaADC ADC_L (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_cmpans(i_analog_l),
.o_cmpdac(o_cmpdac_l),
.o_adc_dt(o_adcdt_l[9:0]),
.o_adc_dt_en()
);
deltaSigmaADC ADC_R (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_cmpans(i_analog_r),
.o_cmpdac(o_cmpdac_r),
.o_adc_dt(o_adcdt_r[9:0]),
.o_adc_dt_en()
);
endmodule
| 6.695797 |
module audio_interp_sigma_delta #(
parameter W_IN = 16,
parameter W_OUT = 4,
parameter LOG_OVERSAMPLE = 5
) (
input wire clk,
input wire rst_n,
input wire clk_en,
input wire [ W_IN-1:0] sample_in,
output wire sample_in_rdy,
output reg [W_OUT-1:0] sample_out
);
reg [LOG_OVERSAMPLE-1:0] oversample_ctr;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
oversample_ctr <= {LOG_OVERSAMPLE{1'b0}};
end else if (clk_en) begin
oversample_ctr <= oversample_ctr + 1'b1;
end
end
assign sample_in_rdy = clk_en && &oversample_ctr;
wire [W_IN+W_OUT-1:0] sample_in_scaled = (sample_in << W_OUT) - sample_in;
reg [W_IN+W_OUT-1:0] sample_in_prev_scaled;
reg [W_IN+W_OUT+LOG_OVERSAMPLE-1:0] interp_sample;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sample_in_prev_scaled <= {W_IN + W_OUT{1'b0}};
interp_sample <= {W_IN + W_OUT + LOG_OVERSAMPLE{1'b0}};
end else if (clk_en) begin
interp_sample <= interp_sample + sample_in_scaled - sample_in_prev_scaled;
if (sample_in_rdy) sample_in_prev_scaled <= sample_in_scaled;
end
end
reg [W_IN+LOG_OVERSAMPLE-1:0] accum;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
accum <= {W_IN + LOG_OVERSAMPLE{1'b0}};
sample_out <= {W_OUT{1'b0}};
end else if (clk_en) begin
{sample_out, accum} <= {{W_OUT{1'b0}}, accum} + interp_sample;
end
end
endmodule
| 6.867768 |
module audio_io (
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
iAUD_ADCDAT,
oAUD_ADCLRCK,
iCLK_18_4,
iRST_N,
pulses,
linein
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
input iAUD_ADCDAT;
output oAUD_ADCLRCK;
// Control Signals
input iCLK_18_4;
input iRST_N;
input [15:0] pulses;
output [15:0] linein;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [3:0] SEL_Cont;
reg LRCK_1X;
//////////// AUD_BCK Generator //////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end else begin
if (BCK_DIV >= REF_CLK / (SAMPLE_RATE * DATA_WIDTH * CHANNEL_NUM * 2) - 1) begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end else BCK_DIV <= BCK_DIV + 1'd1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always @(posedge iCLK_18_4 or negedge iRST_N) begin
if (!iRST_N) begin
LRCK_1X_DIV <= 0;
LRCK_1X <= 0;
end else begin
// LRCK 1X
if (LRCK_1X_DIV >= REF_CLK / (SAMPLE_RATE * 2) - 1) begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end else LRCK_1X_DIV <= LRCK_1X_DIV + 1'd1;
end
end
assign oAUD_LRCK = LRCK_1X;
assign oAUD_ADCLRCK = oAUD_LRCK;
//////////////////////////////////////////////////
////////// 16 Bits PISO MSB First //////////////
always @(negedge oAUD_BCK or negedge iRST_N) begin
if (!iRST_N) SEL_Cont <= 0;
else SEL_Cont <= SEL_Cont + 1'd1;
end
reg [15:0] pulsebuf;
always @(negedge LRCK_1X) begin
pulsebuf <= pulses;
end
assign oAUD_DATA = pulsebuf[~SEL_Cont];
assign linein = inputsample;
reg [15:0] inputsample;
reg [15:0] inputbuf;
always @(negedge oAUD_BCK) begin
inputbuf[~SEL_Cont] <= iAUD_ADCDAT;
end
always @(negedge LRCK_1X) begin
inputsample <= inputbuf;
end
endmodule
| 7.475181 |
module audio_key (
input rst, //reset input
input clk, //clock input
input key, //press the button to record,release button play
output reg record, //record ctrl for other module
output reg play, //play ctrl for other module
output reg write_req, //start write request
input write_req_ack, //start write request response
output reg read_req, //start read request
input read_req_ack //start read request response
);
//state machine code
localparam S_IDLE = 0;
localparam S_RECORD = 1;
localparam S_PLAY = 2;
wire button_negedge; //press button ,one clock cycle
wire button_posedge; //button release,one clock cycle
reg [ 1:0] state;
reg [31:0] record_cnt; //recording counter, recording the recording time
reg [31:0] play_cnt; //play counter, record play time
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
state <= S_IDLE;
record <= 1'b0;
play <= 1'b0;
record_cnt <= 32'd0;
play_cnt <= 32'd0;
write_req <= 1'b0;
read_req <= 1'b0;
end else
case (state)
S_IDLE: begin
//press the button to start recording and write requests simultaneously
if (button_negedge == 1'b1) begin
record <= 1'b1;
write_req <= 1'b1;
state <= S_RECORD;
end
end
S_RECORD: begin
if (write_req_ack) write_req <= 1'b0;
//the button is released, the playback begins, and a read request is issued simultaneously
if (button_posedge == 1'b1) begin
record <= 1'b0;
play <= 1'b1;
state <= S_PLAY;
read_req <= 1'b1;
end
//recording counter
record_cnt <= record_cnt + 32'd1;
play_cnt <= 32'd0;
end
S_PLAY: begin
if (read_req_ack == 1'b1) read_req <= 1'b0;
if (button_negedge == 1'b1) begin
record <= 1'b1;
write_req <= 1'b1;
state <= S_RECORD;
record_cnt <= 32'd0;
play <= 1'b0;
end //Play time equals recording time
else if (play_cnt == record_cnt) begin
record_cnt <= 32'd0;
state <= S_IDLE;
play <= 1'b0;
end else play_cnt <= play_cnt + 32'd1;
end
default: state <= S_IDLE;
endcase
end
ax_debounce ax_debounce_m0 (
.clk (clk),
.rst (rst),
.button_in (key),
.button_posedge(button_posedge),
.button_negedge(button_negedge),
.button_out ()
);
endmodule
| 7.197223 |
module audio_loopback (
input wire sys_clk, //ϵͳʱӣƵ50MHz
input wire sys_rst_n, //ϵͳλ͵ƽЧ
input wire audio_bclk, //WM8978λʱ
input wire audio_lrc, //WM8978/Ҷʱ
input wire audio_adcdat, //WM8978ADC
output wire scl, //wm8978Ĵʱźscl
output wire audio_mclk, //WM8978ʱ,Ƶ12MHz
output wire audio_dacdat, //DACݸWM8978
inout wire sda, //wm8978Ĵźsda
output wire [23:0] adc_data, //һνյ
output wire rcv_done, //һݽ
input wire [23:0] dac_data, //WM8978͵
output wire send_done //һݷ
);
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------------- clk_gen_inst ----------------------
clk_gen clk_gen_inst (
.areset(~sys_rst_n), //첽λȡ
.inclk0(sys_clk), //ʱӣ50MHz
.c0 (audio_mclk), //ʱӣ12MHz
.locked() //ȶʱӱ־ź
);
//------------------- audio_rcv_inst -------------------
audio_rcv audio_rcv_inst (
.audio_bclk (audio_bclk), //WM8978λʱ
.sys_rst_n (sys_rst_n), //ϵͳλЧ
.audio_lrc (audio_lrc), //WM8978/Ҷʱ
.audio_adcdat(audio_adcdat), //WM8978ADC
.adc_data(adc_data), //һνյ
.rcv_done(rcv_done) //һݽ
);
//------------------ audio_send_inst ------------------
audio_send audio_send_inst (
.audio_bclk(audio_bclk), //WM8978λʱ
.sys_rst_n (sys_rst_n), //ϵͳλЧ
.audio_lrc (audio_lrc), //WM8978/Ҷʱ
.dac_data (dac_data), //WM8978͵
.audio_dacdat(audio_dacdat), //DACݸWM8978
.send_done (send_done) //һݷ
);
//----------------- wm8978_cfg_inst --------------------
wm8978_cfg wm8978_cfg_inst (
.sys_clk (sys_clk), //ϵͳʱӣƵ50MHz
.sys_rst_n(sys_rst_n), //ϵͳλ͵ƽЧ
.i2c_scl(scl), //wm8978Ĵʱźscl
.i2c_sda(sda) //wm8978Ĵźsda
);
endmodule
| 6.950306 |
module dac (
DACout,
DACin,
Clk,
Reset
);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI + 1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI + 1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk) begin
if (Reset) begin
SigmaLatch <= #1 1'b1 << (`MSBI + 1);
DACout <= #1 1'b0;
end else begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
| 6.686484 |
module mixer (
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1_cha,
input wire [7:0] ay1_chb,
input wire [7:0] ay1_chc,
input wire [7:0] ay2_cha,
input wire [7:0] ay2_chb,
input wire [7:0] ay2_chc,
input wire [7:0] specdrum,
output wire audio
);
parameter
SRC_BEEPER = 3'd0,
SRC_AY1_CHA = 3'd1,
SRC_AY1_CHB = 3'd2,
SRC_AY1_CHC = 3'd3,
SRC_AY2_CHA = 3'd4,
SRC_AY2_CHB = 3'd5,
SRC_AY2_CHC = 3'd6,
SRC_SPECD = 3'd7;
wire [7:0] beeper = ({ear,spk,mic}==4'h0)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 :
({ear,spk,mic}==3'b011)? 8'd192 :
({ear,spk,mic}==3'b100)? 8'd22 :
({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
reg [7:0] mezcla;
reg [2:0] sndsource = 3'd0;
always @(posedge clkdac) begin
case (sndsource)
SRC_BEEPER: mezcla <= beeper;
SRC_AY1_CHA: mezcla <= ay1_cha;
SRC_AY1_CHB: mezcla <= ay1_chb;
SRC_AY1_CHC: mezcla <= ay1_chc;
SRC_AY2_CHA: mezcla <= ay2_cha;
SRC_AY2_CHB: mezcla <= ay2_chb;
SRC_AY2_CHC: mezcla <= ay2_chc;
SRC_SPECD: mezcla <= specdrum;
endcase
sndsource <= sndsource + 3'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
end
dac audio_dac (
.DACout(audio),
.DACin(mezcla),
.Clk(clkdac),
.Reset(reset)
);
endmodule
| 6.918526 |
module audio_module (
CLOCK_50, /*KEY,*/
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
I2C_SCLK,
I2C_SDAT,
TD_CLK27,
TD_RESET_N
);
//////////// CLOCK //////////
input CLOCK_50;
//////////// KEY //////////
//input [3:0] KEY;
//////////// Audio //////////
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
//////////// I2C for Audio and Tv-Decode //////////
output I2C_SCLK;
inout I2C_SDAT;
//////////// TV Decoder 1 //////////
input TD_CLK27;
output TD_RESET_N;
wire I2C_END;
wire AUD_CTRL_CLK;
reg [31:0] VGA_CLKo;
wire demo_clock;
wire [7:0] song_code1;
//=============================================================================
// Structural coding
//=============================================================================
// TV DECODER ENABLE
assign TD_RESET_N = 1'b1;
// I2C
I2C_AV_Config u7 (
.iCLK(CLOCK_50),
.iRST_N(1'b1),
.o_I2C_END(I2C_END),
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT)
);
// AUDIO SOUND
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
// AUDIO PLL
VGA_Audio_PLL u1 (
.areset(~I2C_END),
.inclk0(TD_CLK27),
.c1(AUD_CTRL_CLK)
);
////////////Sound Select/////////////
wire [15:0] sound1;
wire [15:0] sound2;
wire [15:0] sound3;
wire [15:0] sound4;
wire sound_off1;
wire sound_off2;
wire sound_off3;
wire sound_off4;
assign demo_clock = VGA_CLKo[18];
always @(posedge CLOCK_50) begin
VGA_CLKo <= VGA_CLKo + 1;
end
song_amazing_grace dd1 (
.clock(demo_clock),
.key_code(song_code1)
); //,.k_tr( KEY[1] & KEY[0] )
wire [7:0] sound_code1 = song_code1; //SW[9]=0 is DEMO SOUND,otherwise key
wire [7:0] sound_code2 = 0;
wire [7:0] sound_code3 = 0;
wire [7:0] sound_code4 = 0;
staff st1 (
// Key code-in //
.scan_code1(sound_code1),
.scan_code2(sound_code2),
.scan_code3(sound_code3), // OFF
.scan_code4(sound_code4), // OFF
//Sound Output to Audio Generater//
.sound1(sound1),
.sound2(sound2),
.sound3(sound3), // OFF
.sound4(sound4), // OFF
.sound_off1(sound_off1),
.sound_off2(sound_off2),
.sound_off3(sound_off3), //OFF
.sound_off4(sound_off4) //OFF
);
// 2CH Audio Sound output -- Audio Generater //
adio_codec ad1 (
// AUDIO CODEC //
.oAUD_BCK (AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
.iCLK_18_4(AUD_CTRL_CLK),
// KEY //
.iRST_N (1'b1),
.iSrc_Select(2'b00),
// Sound Control //
.key1_on(1'b1), //CH1 ON / OFF
.key2_on(1'b0), //CH2 ON / OFF
.key3_on(1'b0), // OFF
.key4_on(1'b0), // OFF
.sound1 (sound1), // CH1 Freq
.sound2 (sound2), // CH2 Freq
.sound3 (sound3), // OFF,CH3 Freq
.sound4 (sound4), // OFF,CH4 Freq
.instru (1'b0) // INSTUMENT SELECTION - 1 is OFF?, 0 is BRASS
);
endmodule
| 6.712464 |
module audio_nios (
key_external_connection_export,
seg7_conduit_end_export,
pio_0_external_connection_export,
sw_external_connection_export,
i2c_scl_external_connection_export,
i2c_sda_external_connection_export,
audio_conduit_end_XCK,
audio_conduit_end_ADCDAT,
audio_conduit_end_ADCLRC,
audio_conduit_end_DACDAT,
audio_conduit_end_DACLRC,
audio_conduit_end_BCLK,
clk_clk,
reset_reset_n,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n,
altpll_audio_locked_export,
pll_sdam_clk,
pll_locked_export
);
input [3:0] key_external_connection_export;
output [47:0] seg7_conduit_end_export;
output [9:0] pio_0_external_connection_export;
input [9:0] sw_external_connection_export;
output i2c_scl_external_connection_export;
inout i2c_sda_external_connection_export;
output audio_conduit_end_XCK;
input audio_conduit_end_ADCDAT;
input audio_conduit_end_ADCLRC;
output audio_conduit_end_DACDAT;
input audio_conduit_end_DACLRC;
input audio_conduit_end_BCLK;
input clk_clk;
input reset_reset_n;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [15:0] sdram_wire_dq;
output [1:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
output altpll_audio_locked_export;
output pll_sdam_clk;
output pll_locked_export;
endmodule
| 6.832836 |
module audio_nios_DDR3_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin(phy_clk_dqs),
.delayctrlin(dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin(phy_clk_hr),
.delayctrlin(),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin (leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin(leveled_hr_clocks[0]),
`else
.clkin(leveled_hr_clocks),
`endif
.clkout(hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true") begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0 (
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obuf_ba_0.bus_hold = "false", obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign wire_obuf_ba_oe = {(~wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0 (
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obufa_0.bus_hold = "false", obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign wire_obufa_oe = {(~wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0 (
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign wire_pseudo_diffa_oein = {(~oe_w[0])};
assign dataout = wire_obufa_o, dataout_b = wire_obuf_ba_o, oe_w = 1'b1;
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_reset_n;
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored[0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
generate
genvar entry;
for (entry = 0; entry < WRITE_MEM_DEPTH; entry = entry + 1) begin : mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
always @(posedge wr_clk or negedge wr_reset_n) begin
if (~wr_reset_n) begin
data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
end else begin
if (wr_en) begin
if (entry == wr_addr) begin
data_stored[entry] <= wr_data;
end
end
end
end
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux (
.sel(rd_addr),
.data(all_data),
.result(mux_data_out)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX"; defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk or negedge rd_reset_n) begin
if (~rd_reset_n) begin
rd_data <= {READ_DATA_WIDTH{1'b0}};
end else begin
rd_data <= mux_data_out;
end
end
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam REG_STAGES = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH * RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] extend_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r[REG_STAGES-1:0] /* synthesis dont_merge */;
generate
genvar stage;
for (stage = 0; stage < REG_STAGES; stage = stage + 1) begin : stage_gen
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
if (REG_POST_RESET_HIGH == "true") datain_r[stage] <= {FULL_DATA_WIDTH{1'b1}};
else datain_r[stage] <= {FULL_DATA_WIDTH{1'b0}};
else datain_r[stage] <= (stage == 0) ? datain : datain_r[stage-1];
end
end
endgenerate
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t0 = datain_r[0][(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[0][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_rr_t1 = datain_r[1][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (extend_by == 2'b01) ? {datain_t1 | datain_t0,
datain_t0 | datain_r_t1} : (
(extend_by == 2'b10) ? {datain_t1 | datain_t0 | datain_r_t1,
datain_t0 | datain_r_t1 | datain_r_t0} : (
(extend_by == 2'b11) ? {datain_t1 | datain_t0 | datain_r_t1 | datain_r_t0,
datain_t0 | datain_r_t1 | datain_r_t0 | datain_rr_t1} : (
{datain_t1, datain_t0} )));
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH * RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true") datain_r <= {FULL_DATA_WIDTH{1'b1}};
else datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [FULL_DATA_WIDTH-1:0] dataout_pre;
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam iss_probe_inst.enable_metastability = "NO", iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH, iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0, iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select (
.data(latency_counter),
.eq(selector)
// synopsys translate_off
, .aclr(),
.clken(),
.clock(),
.enable()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM; defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n) begin
if (~reset_n) selector_reg <= {LATENCY_NUM{1'b0}};
else selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n) begin
if (~reset_n) begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end else begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
audio_nios_DDR3_p0_reset_sync ureset_afi_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
audio_nios_DDR3_p0_reset_sync ureset_ctl_reset_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
audio_nios_DDR3_p0_reset_sync ureset_addr_cmd_clk (
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync(reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
audio_nios_DDR3_p0_reset_sync ureset_resync_clk (
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
audio_nios_DDR3_p0_reset_sync ureset_seq_clk (
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
audio_nios_DDR3_p0_reset_sync ureset_scc_clk (
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
audio_nios_DDR3_p0_reset_sync ureset_avl_clk (
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i = 0; i < MEM_READ_DQS_WIDTH; i = i + 1) begin : read_capture_reset
audio_nios_DDR3_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT (1)
) ureset_read_capture_clk (
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync(reset_n_read_capture[i])
);
end
endgenerate
endmodule
| 7.526719 |
module audio_nios_DDR3_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*)
reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i = 0; i < RESET_SYNC_STAGES + NUM_RESET_OUTPUT - 1; i = i + 1) begin : reset_stage
always @(posedge clk or negedge reset_n) begin
if (~reset_n) reset_reg[i] <= 1'b0;
else begin
if (i == 0) reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES) reset_reg[i] <= reset_reg[i-1];
else reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
| 7.526719 |
module audio_nios_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.252384 |
module audio_nios_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
audio_nios_jtag_uart_sim_scfifo_w the_audio_nios_jtag_uart_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.252384 |
module audio_nios_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.252384 |
module audio_nios_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
audio_nios_jtag_uart_sim_scfifo_r the_audio_nios_jtag_uart_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.252384 |
module audio_nios_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 3:0] d1_data_in;
reg [ 3:0] d2_data_in;
wire [ 3:0] data_in;
reg [ 3:0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3:0] edge_detect;
wire irq;
reg [ 3:0] irq_mask;
wire [ 3:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[0] <= 0;
else if (edge_detect[0]) edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[1] <= 0;
else if (edge_detect[1]) edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[2] <= 0;
else if (edge_detect[2]) edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[3] <= 0;
else if (edge_detect[3]) edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
| 6.978191 |
module audio_nios_mem_if_ddr3_emif_0_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin(phy_clk_dqs),
.delayctrlin(dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin(phy_clk_hr),
.delayctrlin(),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin (leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin(leveled_hr_clocks[0]),
`else
.clkin(leveled_hr_clocks),
`endif
.clkout(hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true") begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0 (
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obuf_ba_0.bus_hold = "false", obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign wire_obuf_ba_oe = {(~wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0 (
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obufa_0.bus_hold = "false", obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign wire_obufa_oe = {(~wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0 (
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign wire_pseudo_diffa_oein = {(~oe_w[0])};
assign dataout = wire_obufa_o, dataout_b = wire_obuf_ba_o, oe_w = 1'b1;
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_reset_n;
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored[0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
generate
genvar entry;
for (entry = 0; entry < WRITE_MEM_DEPTH; entry = entry + 1) begin : mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
always @(posedge wr_clk or negedge wr_reset_n) begin
if (~wr_reset_n) begin
data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
end else begin
if (wr_en) begin
if (entry == wr_addr) begin
data_stored[entry] <= wr_data;
end
end
end
end
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux (
.sel(rd_addr),
.data(all_data),
.result(mux_data_out)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX"; defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk or negedge rd_reset_n) begin
if (~rd_reset_n) begin
rd_data <= {READ_DATA_WIDTH{1'b0}};
end else begin
rd_data <= mux_data_out;
end
end
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam REG_STAGES = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH * RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] extend_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r[REG_STAGES-1:0] /* synthesis dont_merge */;
generate
genvar stage;
for (stage = 0; stage < REG_STAGES; stage = stage + 1) begin : stage_gen
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
if (REG_POST_RESET_HIGH == "true") datain_r[stage] <= {FULL_DATA_WIDTH{1'b1}};
else datain_r[stage] <= {FULL_DATA_WIDTH{1'b0}};
else datain_r[stage] <= (stage == 0) ? datain : datain_r[stage-1];
end
end
endgenerate
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t0 = datain_r[0][(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[0][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_rr_t1 = datain_r[1][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (extend_by == 2'b01) ? {datain_t1 | datain_t0,
datain_t0 | datain_r_t1} : (
(extend_by == 2'b10) ? {datain_t1 | datain_t0 | datain_r_t1,
datain_t0 | datain_r_t1 | datain_r_t0} : (
(extend_by == 2'b11) ? {datain_t1 | datain_t0 | datain_r_t1 | datain_r_t0,
datain_t0 | datain_r_t1 | datain_r_t0 | datain_rr_t1} : (
{datain_t1, datain_t0} )));
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH * RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true") datain_r <= {FULL_DATA_WIDTH{1'b1}};
else datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [FULL_DATA_WIDTH-1:0] dataout_pre;
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam iss_probe_inst.enable_metastability = "NO", iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH, iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0, iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select (
.data(latency_counter),
.eq(selector)
// synopsys translate_off
, .aclr(),
.clken(),
.clock(),
.enable()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM; defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n) begin
if (~reset_n) selector_reg <= {LATENCY_NUM{1'b0}};
else selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n) begin
if (~reset_n) begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end else begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_afi_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_ctl_reset_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_addr_cmd_clk (
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync(reset_n_addr_cmd_clk)
);
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_resync_clk (
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_seq_clk (
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_scc_clk (
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_avl_clk (
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i = 0; i < MEM_READ_DQS_WIDTH; i = i + 1) begin : read_capture_reset
audio_nios_mem_if_ddr3_emif_0_p0_reset_sync ureset_read_capture_clk (
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync(reset_n_read_capture[i])
);
end
endgenerate
endmodule
| 7.34268 |
module audio_nios_mem_if_ddr3_emif_0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*)
reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i = 0; i < RESET_SYNC_STAGES + NUM_RESET_OUTPUT - 1; i = i + 1) begin : reset_stage
always @(posedge clk or negedge reset_n) begin
if (~reset_n) reset_reg[i] <= 1'b0;
else begin
if (i == 0) reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES) reset_reg[i] <= reset_reg[i-1];
else reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
| 7.34268 |
module audio_nios_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2.hex";
output [31:0] readdata;
input [16:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 80000,
the_altsyncram.numwords_a = 80000, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 17;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.945362 |
module audio_nios_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2_1.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 51200,
the_altsyncram.numwords_a = 51200, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.945362 |
module audio_nios_onchip_memory2_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "audio_nios_onchip_memory2_2.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [31:0] writedata;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clken),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 51200,
the_altsyncram.numwords_a = 51200, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.945362 |
module audio_nios_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(3),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("7500 ps"),
.duty_cycle1(50),
.output_clock_frequency2("10.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_2, outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.56724 |
module audio_nios_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1471402818 : 0;
endmodule
| 6.583657 |
module audio_output (
input clk,
input reset,
input [31:0] data,
// clock_divider = (audio_clk / sampling_rate) - 1
// ex: (18MHz / 48000Hz) - 1 = 374
input [31:0] clock_divider,
input valid_toggle,
output full,
input ext_audio_clk,
input ext_audio_reset,
output ext_audio_r,
output ext_audio_l
);
parameter FIFO_DEPTH_IN_BITS = 4;
// data write
wire we_cw;
reg toggle;
reg toggle_prev;
reg [31:0] data_in;
assign we_cw = ((toggle_prev != toggle) && (full == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (reset == 1'b1) begin
toggle <= 1'b0;
data_in <= 1'd0;
toggle_prev <= 1'b0;
end else begin
toggle <= valid_toggle;
data_in <= data;
toggle_prev <= toggle;
end
end
// data read
wire req_ca;
wire empty_ca;
wire valid_ca;
reg [15+1:0] sample_sum_r_ca;
reg [15+1:0] sample_sum_l_ca;
wire [ 31:0] data_out_ca;
reg [ 31:0] data_out_reg_ca;
reg [ 15:0] read_freq_counter;
assign req_ca = (read_freq_counter == 1'd0) ? 1'b1 : 1'b0;
assign ext_audio_r = sample_sum_r_ca[15+1];
assign ext_audio_l = sample_sum_l_ca[15+1];
always @(posedge ext_audio_clk) begin
if (ext_audio_reset == 1'b1) begin
sample_sum_r_ca <= 1'd0;
sample_sum_l_ca <= 1'd0;
data_out_reg_ca <= 1'd0;
read_freq_counter <= 1'd0;
end else begin
// read data delays 1 cycle
if (valid_ca) begin
data_out_reg_ca <= data_out_ca;
end
// delta sigma
sample_sum_r_ca <= sample_sum_r_ca[15:0] + data_out_reg_ca[31:16];
sample_sum_l_ca <= sample_sum_l_ca[15:0] + data_out_reg_ca[15:0];
// read data once per READ_FREQ+1 cycles
if (read_freq_counter == 1'd0) begin
read_freq_counter <= clock_divider;
end else begin
read_freq_counter <= read_freq_counter - 1'd1;
end
end
end
cdc_fifo #(
.DATA_WIDTH(32),
.ADDR_WIDTH(FIFO_DEPTH_IN_BITS),
.MAX_ITEMS ((1 << FIFO_DEPTH_IN_BITS) - 3)
) cdc_fifo_0 (
.clk_cr(ext_audio_clk),
.reset_cr(ext_audio_reset),
.data_cr(data_out_ca),
.req_cr(req_ca),
.empty_cr(empty_ca),
.valid_cr(valid_ca),
.clk_cw(clk),
.reset_cw(reset),
.data_cw(data_in),
.we_cw(we_cw),
.full_cw(),
.almost_full_cw(full)
);
endmodule
| 7.406687 |
module audio_out_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr,
// Register interfaces
output reg csr_en_o,
output reg csr_fmt_signed_o,
output reg csr_fmt_16_o,
output reg csr_fmt_mono_o,
output reg csr_ie_o,
input wire csr_empty_i,
input wire csr_full_i,
input wire csr_half_full_i,
output reg [7:0] div_frac_o,
output reg [9:0] div_int_o,
output reg [31:0] fifo_o,
output reg fifo_wen
);
// APB adapter
wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'hc;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;
localparam ADDR_CSR = 0;
localparam ADDR_DIV = 4;
localparam ADDR_FIFO = 8;
wire __csr_wen = wen && addr == ADDR_CSR;
wire __csr_ren = ren && addr == ADDR_CSR;
wire __div_wen = wen && addr == ADDR_DIV;
wire __div_ren = ren && addr == ADDR_DIV;
wire __fifo_wen = wen && addr == ADDR_FIFO;
wire __fifo_ren = ren && addr == ADDR_FIFO;
wire csr_en_wdata = wdata[0];
wire csr_en_rdata;
wire csr_fmt_signed_wdata = wdata[1];
wire csr_fmt_signed_rdata;
wire csr_fmt_16_wdata = wdata[2];
wire csr_fmt_16_rdata;
wire csr_fmt_mono_wdata = wdata[3];
wire csr_fmt_mono_rdata;
wire csr_ie_wdata = wdata[8];
wire csr_ie_rdata;
wire csr_empty_wdata = wdata[29];
wire csr_empty_rdata;
wire csr_full_wdata = wdata[30];
wire csr_full_rdata;
wire csr_half_full_wdata = wdata[31];
wire csr_half_full_rdata;
wire [31:0] __csr_rdata = {
csr_half_full_rdata,
csr_full_rdata,
csr_empty_rdata,
20'h0,
csr_ie_rdata,
4'h0,
csr_fmt_mono_rdata,
csr_fmt_16_rdata,
csr_fmt_signed_rdata,
csr_en_rdata
};
assign csr_en_rdata = csr_en_o;
assign csr_fmt_signed_rdata = csr_fmt_signed_o;
assign csr_fmt_16_rdata = csr_fmt_16_o;
assign csr_fmt_mono_rdata = csr_fmt_mono_o;
assign csr_ie_rdata = csr_ie_o;
assign csr_empty_rdata = csr_empty_i;
assign csr_full_rdata = csr_full_i;
assign csr_half_full_rdata = csr_half_full_i;
wire [ 7:0] div_frac_wdata = wdata[7:0];
wire [ 7:0] div_frac_rdata;
wire [ 9:0] div_int_wdata = wdata[17:8];
wire [ 9:0] div_int_rdata;
wire [31:0] __div_rdata = {14'h0, div_int_rdata, div_frac_rdata};
assign div_frac_rdata = div_frac_o;
assign div_int_rdata = div_int_o;
wire [31:0] fifo_wdata = wdata[31:0];
wire [31:0] fifo_rdata;
wire [31:0] __fifo_rdata = {fifo_rdata};
assign fifo_rdata = 32'h0;
always @(*) begin
case (addr)
ADDR_CSR: rdata = __csr_rdata;
ADDR_DIV: rdata = __div_rdata;
ADDR_FIFO: rdata = __fifo_rdata;
default: rdata = 32'h0;
endcase
fifo_wen = __fifo_wen;
fifo_o = fifo_wdata;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
csr_en_o <= 1'h0;
csr_fmt_signed_o <= 1'h0;
csr_fmt_16_o <= 1'h0;
csr_fmt_mono_o <= 1'h0;
csr_ie_o <= 1'h0;
div_frac_o <= 8'h0;
div_int_o <= 10'h0;
end else begin
if (__csr_wen) csr_en_o <= csr_en_wdata;
if (__csr_wen) csr_fmt_signed_o <= csr_fmt_signed_wdata;
if (__csr_wen) csr_fmt_16_o <= csr_fmt_16_wdata;
if (__csr_wen) csr_fmt_mono_o <= csr_fmt_mono_wdata;
if (__csr_wen) csr_ie_o <= csr_ie_wdata;
if (__div_wen) div_frac_o <= div_frac_wdata;
if (__div_wen) div_int_o <= div_int_wdata;
end
end
endmodule
| 8.159243 |
module AUDIO_PLL_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("1.531995 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.506107 |
module audio_post (
input clk, //
input i_init, //
input i_we, //
input [15:0] i_dout, //
output reg [15:0] o_diff, // diff between 1st and 2nd max value
output reg [ 2:0] o_max_idx, // index of maxium value, 111 is invalid
output reg o_validp, // one cycle pulse for further processing
input resetn
);
reg [ 2:0] r_max_idx;
reg [15:0] r_1st_max_value;
reg [15:0] r_2nd_max_value;
reg [ 2:0] idx_cnt;
reg [ 2:0] r_we_d;
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) r_we_d <= 2'b0;
else r_we_d <= {r_we_d[1:0], i_we};
end
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) idx_cnt <= 3'b0;
else if (i_init) idx_cnt <= 3'b0;
else if (i_we) idx_cnt <= idx_cnt + 3'd1;
end
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
r_1st_max_value <= 16'b0; // consider positive value only for max
r_2nd_max_value <= 16'b0;
r_max_idx <= 3'b111; // invalid idx
end else if (i_init == 1'b1) begin
r_1st_max_value <= 16'b0; // consider positive value only for max
r_2nd_max_value <= 16'b0;
r_max_idx <= 3'b111; // invalid idx
end else if (i_we && (!i_dout[15]) && (r_1st_max_value < i_dout)) begin
r_1st_max_value <= i_dout;
r_2nd_max_value <= r_1st_max_value;
r_max_idx <= idx_cnt;
end else if (i_we && (!i_dout[15]) && (r_2nd_max_value < i_dout)) begin
r_2nd_max_value <= i_dout;
end
end
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
o_diff <= 16'b0;
o_max_idx <= 3'b111;
end else if (r_we_d[2:1] == 2'b10) begin // falling edge
o_diff <= (r_1st_max_value - r_2nd_max_value);
o_max_idx <= r_max_idx;
end
end
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) o_validp <= 1'b0;
else o_validp <= (r_we_d[2:1] == 2'b10);
end
endmodule
| 8.050278 |
module audio_processing (
input clk,
input [7:0] cnt256_n,
input signed [15:0] ch1_in,
input signed [15:0] ch2_in,
output reg signed [15:0] ch1_out,
output reg signed [15:0] ch2_out
);
parameter ST_IDLE = 0;
parameter ST_CLIP_L = 1;
parameter ST_CLIP_R = 2;
reg [3:0] state;
reg signed [15:0] ch1_buf;
reg signed [15:0] ch2_buf;
always @(posedge clk) begin
if (cnt256_n == 8'd0) begin
state <= ST_CLIP_L;
end
end
always @(posedge clk) begin
if (cnt256_n == 8'd1) begin
ch1_out <= ch1_buf;
ch2_out <= ch2_buf;
end
end
always @(posedge clk) begin
case (state)
ST_IDLE: begin
//No Action
end
ST_CLIP_L: begin
if (ch1_in > $signed(16'h1FFF)) begin
ch1_buf <= 16'h1FFF;
end else if (ch1_in < $signed(16'hE000)) begin
ch1_buf <= 16'hE000;
end else begin
ch1_buf <= ch1_in;
end
state <= ST_CLIP_R;
end
ST_CLIP_R: begin
if (ch2_in > $signed(16'h1FFF)) begin
ch2_buf <= 16'h1FFF;
end else if (ch2_in < $signed(16'hE000)) begin
ch2_buf <= 16'hE000;
end else begin
ch2_buf <= ch2_in;
end
state <= ST_IDLE;
end
endcase
end
endmodule
| 7.423247 |
module audio_processing_unit #(
parameter CLOCK_FREQ = 0,
parameter NOTE_TABLE_FILE = "",
parameter VIBRATO_TABLE_FILE = "",
parameter NOISE_TABLE_FILE = ""
) (
input wire i_clk,
input wire i_rst,
input wire [3:0] i_mixer,
output wire [8:0] o_sample,
output wire [3:0] o_frame_pulse
);
wire w_tick_stb;
wire w_beat_stb;
timing_strobe_generator #(
.CLOCK_FREQ(CLOCK_FREQ)
) pulse_generator (
.i_clk(i_clk),
.i_rst(i_rst),
.o_tick_stb(w_tick_stb),
.o_beat_stb(w_beat_stb)
);
wire [8:0] w_compare_pulse_1;
wire w_frame_pulse_1;
channel_1_pulse #(
.NOTE_TABLE_FILE(NOTE_TABLE_FILE),
.VIBRATO_TABLE_FILE(VIBRATO_TABLE_FILE)
) pulse_1 (
.i_clk(i_clk),
.i_rst(i_rst),
.i_tick_stb(w_tick_stb),
.i_note_stb(w_beat_stb),
.o_output(w_compare_pulse_1),
.o_frame_pulse(w_frame_pulse_1)
);
wire [8:0] w_compare_pulse_2;
wire w_frame_pulse_2;
channel_2_pulse #(
.NOTE_TABLE_FILE(NOTE_TABLE_FILE)
) pulse_2 (
.i_clk(i_clk),
.i_rst(i_rst),
.i_tick_stb(w_tick_stb),
.i_note_stb(w_beat_stb),
.o_output(w_compare_pulse_2),
.o_frame_pulse(w_frame_pulse_2)
);
wire [8:0] w_triangle_3_output;
wire w_frame_pulse_3;
channel_3_triangle #(
.NOTE_TABLE_FILE(NOTE_TABLE_FILE)
) triangle_3 (
.i_clk(i_clk),
.i_rst(i_rst),
.i_tick_stb(w_tick_stb),
.i_note_stb(w_beat_stb),
.o_output(w_triangle_3_output),
.o_frame_pulse(w_frame_pulse_3)
);
wire [8:0] w_noise_output;
wire w_frame_pulse_4;
channel_4_noise #(
.NOISE_TABLE_FILE(NOISE_TABLE_FILE)
) noise (
.i_clk(i_clk),
.i_rst(i_rst),
.i_tick_stb(w_tick_stb),
.i_note_stb(w_beat_stb),
.o_output(w_noise_output),
.o_frame_pulse(w_frame_pulse_4)
);
// Mixer
assign o_sample =
(i_mixer[0]? w_compare_pulse_1 : 9'd0) +
(i_mixer[1]? w_compare_pulse_2 : 9'd0) +
(i_mixer[2]? w_triangle_3_output : 9'd0) +
(i_mixer[3]? w_noise_output : 9'd0);
assign o_frame_pulse = {w_frame_pulse_4, w_frame_pulse_3, w_frame_pulse_2, w_frame_pulse_1};
endmodule
| 7.423247 |
module audio_proc_top (
//////////////////////// Clock Input ////////////////////////
input CLOCK_27, // 27 MHz
input CLOCK_50, // 50 MHz
//////////////////////// Push Button ////////////////////////
input [ 3:0] KEY, // Pushbutton[3:0]
//////////////////////////// LED ////////////////////////////
output [ 8:0] LEDG, // LED Green[8:0]
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
input AUD_ADCDAT, // Audio CODEC ADC Data
inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
output AUD_DACDAT, // Audio CODEC DAC Data
inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
output AUD_XCK, // Audio CODEC Chip Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT, // I2C Data
output I2C_SCLK, // I2C Clock
//////////////////// NIOS INTERFACE ////////////////////////////
input wire NIOS_CLK,
input wire [ 9:0] fftaddr,
input wire fftstart,
output wire fftdone,
output wire [15:0] fftpower,
output wire [ 5:0] fftexp
);
/// audio stuff /////////////////////////////////////////////////
// output to audio DAC
wire signed [15:0] audio_outL, audio_outR;
// input from audio ADC
wire signed [15:0] audio_inL, audio_inR;
wire AUD_CTRL_CLK;
wire DLY_RST;
wire audio_ram_wr_clk;
assign AUD_ADCLRCK = audio_ram_wr_clk;
assign AUD_XCK = AUD_CTRL_CLK;
assign AUD_DACLRCK = audio_ram_wr_clk;
Reset_Delay inst0 (
.iCLK (CLOCK_50),
.oRESET(DLY_RST)
);
Audio_PLL p1 (
.areset(~DLY_RST),
.inclk0(CLOCK_27),
.c0(AUD_CTRL_CLK)
);
I2C_AV_Config I2C_inst (
// Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
//.o_I2C_END(I2C_END),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT)
);
AUDIO_DAC_ADC dac_inst (
// Audio Side
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(audio_ram_wr_clk),
.oAUD_inL(audio_inL), // audio data from ADC
.oAUD_inR(audio_inR), // audio data from ADC
.iAUD_ADCDAT(AUD_ADCDAT),
.iAUD_extL(audio_outL), // audio data to DAC
.iAUD_extR(audio_outR), // audio data to DAC
// Control Signals
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY_RST)
);
// FFT controller stuff
parameter LEN = 1024;
parameter LBITS = 10;
parameter EBITS = 6;
parameter BITS = 16;
wire lc;
wire [LBITS-1:0] sampleAddr;
wire [BITS-1:0] sample;
FFTController fftc_inst (
.iReset(~KEY[0]),
.iStart(lc),
.iStateClk(NIOS_CLK),
.oSampAddr(sampleAddr),
.iSamp(sample),
.iReadAddr(fftaddr),
.iReadClock(NIOS_CLK),
.oPower(fftpower),
.oExp(fftexp),
.oDone(fftdone)
);
AudioRam_controller audRAMc_inst (
.iReset(~KEY[0]),
.iStartLoad(fftstart),
.iWriteClock(audio_ram_wr_clk),
.iSample(audio_inL),
.iReadClock(NIOS_CLK),
.iReadAddr(sampleAddr),
.iWindow(KEY[1]),
.oValue(sample),
.oLoadComplete(lc)
);
assign LEDG[8] = fftstart;
endmodule
| 6.799341 |
module Audio_PWM (
input clk_fm_demo_sampling,
input clk,
input RSTn,
input demod_en,
//input wire [9:0] demodulated_signal_downsample,
input wire [13:0] demodulated_signal_downsample,
output wire audio_pwm
);
//pwm generation simulate the DAC using 10bit range
reg [15:0] cnt = 0;
reg audio_pwm_reg;
reg N_1 = 1'b0;
reg N = 1'b0;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) cnt <= 10'b0;
else begin
N_1 <= N;
N <= clk_fm_demo_sampling;
if (N > N_1) cnt <= 10'b0;
else cnt <= cnt + 1'b1;
end
end
always @(posedge clk or negedge RSTn) begin
if (~RSTn) audio_pwm_reg <= 1'b0;
else if (cnt >= (demodulated_signal_downsample)) audio_pwm_reg <= 1'b1;
else audio_pwm_reg <= 1'b0;
end
assign audio_pwm = (~demod_en) ? audio_pwm_reg : 1'b0;
endmodule
| 6.70848 |
module audio_rcv (
input wire audio_bclk, //WM8978λʱ
input wire sys_rst_n, //ϵͳλЧ
input wire audio_lrc, //WM8978/Ҷʱ
input wire audio_adcdat, //WM8978ADC
output reg [23:0] adc_data, //һνյ
output reg rcv_done //һݽ
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg audio_lrc_d1; //ʱӴһź
reg [ 4:0] adcdat_cnt; //WM8978ADCλ
reg [23:0] data_reg; //adc_dataݼĴ
//wire define
wire lrc_edge; //ʱźر־ź
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//ʹźر־ź
assign lrc_edge = audio_lrc ^ audio_lrc_d1;
//audio_lrcźŴһԷźر־ź
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) audio_lrc_d1 <= 1'b0;
else audio_lrc_d1 <= audio_lrc;
//adcdat_cnt:źر־źΪߵƽʱ
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) adcdat_cnt <= 5'b0;
else if (lrc_edge == 1'b1) adcdat_cnt <= 5'b0;
else if (adcdat_cnt < 5'd26) adcdat_cnt <= adcdat_cnt + 1'b1;
else adcdat_cnt <= adcdat_cnt;
//WM8978ADCݼĴdata_regУһμĴ24λ
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) data_reg <= 24'b0;
else if (adcdat_cnt <= 5'd23) data_reg[23-adcdat_cnt] <= audio_adcdat;
else data_reg <= data_reg;
//һλݴ֮Ĵֵadc_data
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) adc_data <= 24'b0;
else if (adcdat_cnt == 5'd24) adc_data <= data_reg;
else adc_data <= adc_data;
//һλݴ֮һʱӵɱ־ź
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) rcv_done <= 1'b0;
else if (adcdat_cnt == 5'd24) rcv_done <= 1'b1;
else rcv_done <= 1'b0;
endmodule
| 6.985246 |
module audio_rcv_ctrl (
input wire eth_rx_clk, //mii时钟,接收
input wire sys_rst_n, //复位信号，低电平有效
input wire audio_bclk, //音频位时钟
input wire audio_send_done, //wm8978音频接收使能信号
input wire rec_end, //单包数据接收完成信号
input wire rec_en, //接收数据使能信号
input wire [31:0] rec_data, //接收数据
output wire [23:0] audio_dac_data //往wm8978发送的音频播放数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [23:0] wr_data; //写fifo数据
wire rd_en; //读fifo使能
//reg define
reg rcv_flag; //数据包接收完成标志信号
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//接收数据的前24位即为音频传输数据
assign wr_data = rec_data[23:0];
//数据包接收完成之后，将音频接收使能信号作为读fifo使能
assign rd_en = audio_send_done & rcv_flag;
//当数据包接收完成之后拉高接收标志信号
always @(posedge eth_rx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) rcv_flag <= 1'b0;
else if (rec_end == 1'b1) rcv_flag <= 1'b1;
//------------ dcfifo_512x24_inst -------------
//例化的FIFO为：512深度24bit位宽的异步fifo
dcfifo_512x24 dcfifo_512x24_inst2 (
.aclr (~sys_rst_n), //异步复位信号
.data (wr_data), //写入FIFO数据
.rdclk (audio_bclk), //读FIFO时钟
.rdreq (rd_en), //读FIFO使能
.wrclk (eth_rx_clk), //写FIFO时钟
.wrreq (rec_en), //写FIFO使能
.q (audio_dac_data), //读FIFO数据
.rdusedw(), //FIFO中存储个数(读时钟采样)
.wrusedw() //FIFO中存储个数(写时钟采样)
);
endmodule
| 8.018809 |
module is to receive the audio input from WM8978 chip
*/
/*
this module is drived by the clk signal from WM 8978, since WM8978 chip is working in
a master mode this time. it will generate the bclk signal.
this module will be reset if reset button is pressed or the synchronization signal
aud_lrc has a rising or falling edge
else it will start counting how many bits being received and start receiving data.
a frame usually has 32bits of data. so, after 32 aud_bclk period(rx_cnt=32), the data in
the temporary register will output the data in this frame. within the frame, the
data in each bit of the temporary register will be updated one by one.
a signal called rx_done will be output high for a period when datas in a frame are all read.
this is to indicate the chip that this frame is successfully received.
*/
module audio_receive #(parameter WL= 6'd32)(
input aud_bclk, //WM8978 synchronize clk
input sys_rst,
input aud_lrc, //synchronization signal
input aud_adcdat,//audio input signal
//user interface
output reg rx_done, //receive done
output reg [31:0] adc_data //data received
);
//parameter deine
//reg defin
reg aud_lrc_d0; //aud_lrc delay for a period
reg [5:0] rx_cnt; //receive count
reg [31:0] adc_data_t; //pre_output data
//wire define
wire lrc_edge; //edge signal
//************************************************************************
// main code
//************************************************************************
//detect edge of the aud_lrc signal
assign lrc_edge = aud_lrc ^ aud_lrc_d0;
//delay the aud_lrc_d0 for a aud_bclk period, to detect the rising edge of the
//synchronization signal aud_lrc
always @(posedge aud_bclk or negedge sys_rst) begin
if(!sys_rst)
aud_lrc_d0 <= 1'b0;
else
aud_lrc_d0 <= aud_lrc;
end
//count the sampled audio data
always @(posedge aud_bclk or negedge sys_rst) begin
if(!sys_rst)
rx_cnt <= 6'd0;
else if (lrc_edge == 1'b1) //reset the counter if need to synchronize
rx_cnt <= 6'd0;
else if (rx_cnt < 6'd35) //else count how many data sampled
rx_cnt <= rx_cnt + 1'b1;
end
//store the sampled data in a temporary register. this is because that IIC protocol
//has only one receive signal and it can only transmit one bit at a clk period
always @(posedge aud_bclk or negedge sys_rst) begin
if(!sys_rst) begin
adc_data_t <= 32'b0;
end
else if (rx_cnt < WL) //if not reach a word length
adc_data_t[WL - 1'd1 - rx_cnt] <= aud_adcdat; //assign the receive signal to the corresponding bit of the register
end
//output the stored signal to a register if a frame is completed
always @(posedge aud_bclk or negedge sys_rst) begin
if(!sys_rst) begin
rx_done <= 1'b0;
adc_data <= 32'b0;
end
else if (rx_cnt == 6'd32) begin //if 32 bits are received
rx_done <= 1'b1; //indicate that receiving done
adc_data <= adc_data_t; //output the received data as a cmplete vector
end
else
rx_done <= 1'b0; //else not finishing receiving
end
endmodule
| 6.668641 |
module audio_record_play_ctrl (
input rst, //reset input
input clk, //clock input
input key, //press the button to record,release button play
input bclk, //audio bit clock
input daclrc, //DAC sample rate left right clock
output dacdat, //DAC audio data output
input adclrc, //ADC sample rate left right clock
input adcdat, //ADC audio data input
output write_req,
input write_req_ack,
output write_en,
output [63:0] write_data,
output read_req,
input read_req_ack,
output read_en,
input [63:0] read_data
);
wire record;
wire play;
wire read_data_en;
wire [31:0] tx_left_data;
wire [31:0] tx_right_data;
wire [31:0] rx_left_data;
wire [31:0] rx_right_data;
wire data_valid;
assign read_en = read_data_en & play;
assign tx_left_data = read_data[63:32];
assign tx_right_data = read_data[31:0];
assign write_data = {rx_left_data, rx_right_data};
assign write_en = data_valid & record;
//button control module
audio_key audio_key_m0 (
.rst (rst),
.clk (clk),
.key (key),
.record (record),
.play (play),
.write_req (write_req),
.write_req_ack(write_req_ack),
.read_req (read_req),
.read_req_ack (read_req_ack)
);
//audio transmission
audio_tx audio_tx_m0 (
.rst (rst),
.clk (clk),
.sck_bclk (bclk),
.ws_lrc (adclrc),
.sdata (dacdat),
.left_data (tx_left_data),
.right_data (tx_right_data),
.read_data_en(read_data_en)
);
//audio receiver
audio_rx audio_rx_m0 (
.rst (rst),
.clk (clk),
.sck_bclk (bclk),
.ws_lrc (adclrc),
.sdata (adcdat),
.left_data (rx_left_data),
.right_data(rx_right_data),
.data_valid(data_valid)
);
endmodule
| 6.914727 |
module Audio_Reset (
input clk, // BIT_CLK
input rst, // global reset
output AUDIO_RESET_Z, // AUDIO_RESET_Z FPGA pin
output audio_ready // ready signal to begin work on audio codec
);
parameter START = 2'd0; // start state, sets Audio_RESET_Z high ~.5 s
parameter RESET = 2'd1; // reset state, sets Audio_RESET_Z low ~.5 s
parameter HOLD = 2'd2; // finisehd state, leaves AudioRESET_Z high
// state and wait counters
reg [1:0] state, next_state;
reg [23:0] wait_count;
assign AUDIO_RESET_Z = (state != RESET); // set reset low in reset state, high otherwise
assign audio_ready = (state == HOLD); // assert ready once reset sequence finished
// sequential logic update
always @(posedge clk) begin
if (rst) begin
state <= START;
wait_count <= 1;
end else begin
state <= next_state;
wait_count <= wait_count + 1;
end
end
// next_state logic
always @(*) begin
case (state)
START:
if (wait_count == 0) next_state = RESET;
else next_state = START;
RESET:
if (wait_count == 0) next_state = HOLD;
else next_state = RESET;
HOLD: next_state = HOLD;
endcase
end
endmodule
| 7.545245 |
module audio_rx (
input rst,
input clk,
input sck_bclk, //audio bit clock
input ws_lrc, //ADC sample rate left right clock
input sdata, //ADC audio data
output reg [31:0] left_data, //left channel audio data ,ws_lrc = 1
output reg [31:0] right_data, //right channel audio data,ws_lrc = 0
output reg data_valid //audio data valid
);
reg sck_bclk_d0; //delay sck_bclk
reg sck_bclk_d1; //delay sck_bclk
reg ws_lrc_d0; //delay ws_lrc
reg ws_lrc_d1; //delay ws_lrc
reg [31:0] left_data_shift; //left channel audio data shift register
reg [31:0] right_data_shift; //right channel audio data shift register
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
sck_bclk_d0 <= 1'b0;
sck_bclk_d1 <= 1'b0;
ws_lrc_d0 <= 1'b0;
ws_lrc_d1 <= 1'b0;
end else begin
sck_bclk_d0 <= sck_bclk;
sck_bclk_d1 <= sck_bclk_d0;
ws_lrc_d0 <= ws_lrc;
ws_lrc_d1 <= ws_lrc_d0;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) left_data_shift <= 32'd0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge
left_data_shift <= 32'd0;
else if(ws_lrc_d1 == 1'b1 && sck_bclk_d1 == 1'b0 && sck_bclk_d0 == 1'b1)//ws_lrc = 1 ,sck_bclk posedge
left_data_shift <= {left_data_shift[30:0], sdata};
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) right_data_shift <= 32'd0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge
right_data_shift <= 32'd0;
else if(ws_lrc_d1 == 1'b0 && sck_bclk_d1 == 1'b0 && sck_bclk_d0 == 1'b1)//ws_lrc = 0 ,sck_bclk posedge
right_data_shift <= {right_data_shift[30:0], sdata};
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
left_data <= 32'd0;
right_data <= 32'd0;
end
else if(ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1)//ws_lrc posedge
begin
left_data <= left_data_shift;
right_data <= right_data_shift;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) data_valid <= 1'b0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge
data_valid <= 1'b1;
else data_valid <= 1'b0;
end
endmodule
| 7.456006 |
module audio_send (
input wire audio_bclk, //WM8978λʱ
input wire sys_rst_n, //ϵͳλЧ
input wire audio_lrc, //WM8978/Ҷʱ
input wire [23:0] dac_data, //WM8978͵
output reg audio_dacdat, //DACDATݸWM8978
output reg send_done //һݷ
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg audio_lrc_d1; //ʱӴһź
reg [ 4:0] dacdat_cnt; //DACDATݷλ
reg [23:0] data_reg; //dac_dataݼĴ
//wire define
wire lrc_edge; //ʱźر־ź
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//ʹźر־ź
assign lrc_edge = audio_lrc ^ audio_lrc_d1;
//audio_lcrźŴһԷźر־ź
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) audio_lrc_d1 <= 1'b0;
else audio_lrc_d1 <= audio_lrc;
//dacdat_cnt:źر־źΪߵƽʱ
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) dacdat_cnt <= 5'b0;
else if (lrc_edge == 1'b1) dacdat_cnt <= 5'b0;
else if (dacdat_cnt < 5'd26) dacdat_cnt <= dacdat_cnt + 1'b1;
else dacdat_cnt <= dacdat_cnt;
//Ҫ͵dac_dataݼĴdata_reg
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) data_reg <= 24'b0;
else if (lrc_edge == 1'b1) data_reg <= dac_data;
else data_reg <= data_reg;
//½صʱdata_regһλһλaudio_dacdat
always @(negedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) audio_dacdat <= 1'b0;
else if (dacdat_cnt <= 5'd23) audio_dacdat <= data_reg[23-dacdat_cnt];
else audio_dacdat <= audio_dacdat;
//һλݴ֮һʱӵķɱ־ź
always @(posedge audio_bclk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) send_done <= 1'b0;
else if (dacdat_cnt == 5'd24) send_done <= 1'b1;
else send_done <= 1'b0;
endmodule
| 6.923222 |
module audio_send_ctrl (
input wire audio_bclk, //音频位时钟
input wire sys_rst_n, //复位信号
input wire rcv_done, //一次音频数据接受完成
input wire [23:0] adc_data, //一次接受的音频数据
input wire eth_tx_clk, //mii时钟,发送
input wire read_data_req, //读数据请求信号
input wire send_end, //单包数据发送完成信号
output reg send_en, //开始发送信号
output wire [15:0] send_data_num, //数据包发送有效数据字节数
output wire [31:0] send_data //发送数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter DATA_CNT_NUM = 9'd256; //FIFO中存储个数为此值时开始发送
//wire define
wire [ 8:0] data_cnt; //FIFO中存储个数
wire [23:0] rd_data; //fifo读出数据
//reg define
reg eth_send_flag; //发送状态标志信号
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//单包数据发送有效字节数：一个发送数据为32bit（4字节）
assign send_data_num = {DATA_CNT_NUM, 2'b0};
//音频数据为24位，以太网发送数据为32位，往高八位补零即可
assign send_data = {8'd0, rd_data};
//发送状态标志信号：fifo内数据大于等于256时拉高，单包数据发送完成后拉低
always @(posedge eth_tx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) eth_send_flag <= 1'b0;
else if (data_cnt >= DATA_CNT_NUM) eth_send_flag <= 1'b1;
else if (send_end == 1'b1) eth_send_flag <= 1'b0;
//当FIFO内数据大于单包发送字节数时且不在发送状态时，拉高开始发送信号
always @(posedge eth_tx_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) send_en <= 1'b0;
else if (data_cnt >= DATA_CNT_NUM && eth_send_flag == 1'b0)
send_en <= 1'b1; //拉高一个时钟发送信号
else send_en <= 1'b0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------ dcfifo_512x24_inst -------------
//例化的FIFO为：512深度24bit位宽的异步fifo
dcfifo_512x24 dcfifo_512x24_inst1 (
.aclr (~sys_rst_n), //异步复位信号
.data (adc_data), //写入FIFO数据
.rdclk (eth_tx_clk), //读FIFO时钟
.rdreq (read_data_req), //读FIFO使能
.wrclk (audio_bclk), //写FIFO时钟
.wrreq (rcv_done), //写FIFO使能
.q (rd_data), //读FIFO数据
.rdusedw(data_cnt), //FIFO中存储个数(读时钟采样)
.wrusedw() //FIFO中存储个数(写时钟采样)
);
endmodule
| 8.164704 |
module Audio_Setup (
input clk, // BIT_CLK
input rst, // global reset
input shft_ready, // ready signal from shifter to codec
output [75:0] shft_data, // audio data to be sent to codec
output shft_load, // load signal to shifter to codec
output done // signal indicating audio codec has been configured
);
// number of commands to be sent to audio codec
parameter NUM_CMDS = 4;
reg [3:0] cmd_cnt; // number of cmds sent so far
// send load command to shifter when it's ready and there are more config needed
assign shft_load = (shft_ready && cmd_cnt != NUM_CMDS) ? 1'd1 : 1'd0;
// set audio codec cmd data
assign shft_data = (cmd_cnt == 0) ? 76'hE000_02000_08080_00000 : // Unmute Master volume
(cmd_cnt == 1) ? 76'hE000_0A000_80000_00000 : // Mute PC_BEEP
(cmd_cnt == 2) ? 76'hE000_04000_00000_00000 : // Unmute Aux Out Volume
(cmd_cnt == 3) ? 76'hE000_18000_00000_00000 : // Unmute PCM Volume
76'h0000_00000_00000_00000; // NULL cmd
// indicate done once all config cmds have been sent
assign done = (cmd_cnt == NUM_CMDS);
// update cmd_cnt each time a config cmd is sent
always @(posedge clk) begin
if (rst) cmd_cnt <= 0;
else if (shft_ready && cmd_cnt < NUM_CMDS) cmd_cnt <= cmd_cnt + 1;
end
endmodule
| 7.011537 |
module audio_shifter (
input wire clk, //32MHz
input wire nreset,
input wire mix,
input wire [15-1:0] rdata,
input wire [15-1:0] ldata,
input wire exchan,
output wire aud_bclk,
output wire aud_daclrck,
output wire aud_dacdat,
output wire aud_xck
);
//// L-R mixer ////
wire [16-1:0] rdata_mix;
wire [16-1:0] ldata_mix;
assign rdata_mix = {rdata[14], rdata} + {{2{ldata[14]}}, ldata[14:1]};
assign ldata_mix = {ldata[14], ldata} + {{2{rdata[14]}}, rdata[14:1]};
// data mux
reg [16-1:0] rdata_mux;
reg [16-1:0] ldata_mux;
always @(posedge clk) begin
rdata_mux <= #1 (mix) ? rdata_mix : {rdata, rdata[13]};
ldata_mux <= #1 (mix) ? ldata_mix : {ldata, ldata[13]};
end
//// audio output shifter ////
reg [ 9-1:0] shiftcnt;
reg [16-1:0] shift;
always @(posedge clk, negedge nreset) begin
if (~nreset) shiftcnt <= 9'd0;
else shiftcnt <= shiftcnt - 9'd1;
end
always @(posedge clk) begin
if (~|shiftcnt[2:0]) begin
if (~|shiftcnt[6:3]) shift <= #1 (exchan ^ shiftcnt[7]) ? ldata_mux : rdata_mux;
else shift <= #1{shift[14:0], 1'b0};
end
end
//// output ////
assign aud_daclrck = shiftcnt[7];
assign aud_bclk = ~shiftcnt[2];
assign aud_xck = shiftcnt[0];
assign aud_dacdat = shift[15];
endmodule
| 7.53662 |
module audio_spdif (
// Inputs
input clk_i
, input rst_i
, input audio_clk_i
, input inport_tvalid_i
, input [31:0] inport_tdata_i
, input [ 3:0] inport_tstrb_i
, input [ 3:0] inport_tdest_i
, input inport_tlast_i
// Outputs
, output inport_tready_o
, output spdif_o
);
wire bit_clock_w = audio_clk_i;
//-----------------------------------------------------------------
// Core SPDIF
//-----------------------------------------------------------------
spdif_core u_core (
.clk_i(clk_i),
.rst_i(rst_i),
.bit_out_en_i(bit_clock_w),
.spdif_o(spdif_o),
.sample_i(inport_tdata_i),
.sample_req_o(inport_tready_o)
);
endmodule
| 7.572857 |
module audio_speak (
input sys_clk,
input sys_rst,
//WM978 interface
input aud_bclk, //bit clk
input aud_lrc, //synchronize signal
input aud_adcdat, //audio_input
output aud_mclk, //main clk signal for WM8978,generated by pll ip core
output aud_dacdat, //audio output
//control interface
output aud_scl, //WM8978 audio IIC clock signal
inout aud_sda //WM8978 audio IIC data signal
);
//parameter define
//reg define
//wire define
wire [31:0] adc_data; //audio data sampled by FPGA
//***********************************************************************
// main code
//***********************************************************************
//the pll module is just to generate a 12MHz signal and to be the main clock signal of the chip
pll_clk u_pll_clk (
.areset(~sys_rst),
.inclk0(sys_clk),
.c0 (aud_mclk) //the output to be the clock of the chip
);
//WM8978 control
wm8978_ctrl u_wm8978_ctrl (
.clk (sys_clk),
.rst_n(sys_rst),
.aud_bclk (aud_bclk), //clk signal coming from the chip, control the data transmission
.aud_lrc (aud_lrc), //synchronization signal
.aud_adcdat(aud_adcdat), //data transmission
.aud_dacdat(aud_dacdat),
.aud_scl(aud_scl), //scl signal of IIC
.aud_sda(aud_sda), //SDA signal of IIC
.adc_data(adc_data),
.dac_data(adc_data),
.rx_done (),
.tx_done ()
);
endmodule
| 6.861695 |
module AUDIO_SPI_CTL_RD (
input iRESET_n,
input iCLK_50,
output oDIN,
output oCS_n,
output oSCLK,
input iDOUT,
output [7:0] oDATA8,
//TEST
output reg CLK_1M,
output reg [ 7:0] ST,
output reg [ 7:0] COUNTER,
output reg [15:0] W_REG_DATA,
output reg [15:0] W_REG_DATA_T,
output reg [15:0] W_REG_DATA_R,
output reg [15:0] READ_DATA,
output reg [ 7:0] WORD_CNT,
output reg W_R,
output reg [ 1:0] OK2
);
//== ASSIGN TO OUTPUT ===
assign RESET_n = iRESET_n;
assign oCS_n = CS;
assign oDIN = DIN;
assign oSCLK = SCLK;
assign CLK_50 = iCLK_50;
assign DOUT = iDOUT;
//======== REG ===========
wire RESET_n;
reg CS;
reg DIN;
reg SCLK;
wire DOUT;
wire CLK_50;
//==SET REGISTER NUM====
parameter W_WORD_NUM = 128;
//== 1M CLOCK GEN ==
//reg CLK_1M ;
reg [15:0] CLK_DELAY;
always @(posedge CLK_50) begin
if ( CLK_DELAY > 62 ) // 25= 1M clock / 62 =400k
begin
CLK_DELAY <= 0;
CLK_1M <= ~CLK_1M;
end else CLK_DELAY <= CLK_DELAY + 1;
end
//===RESET-DELAY ===
reg [31:0] RESET_DELAY;
always @(negedge RESET_n or posedge CLK_1M) begin
if (!RESET_n) RESET_DELAY <= 0;
else begin
if (RESET_DELAY < 1000000) RESET_DELAY <= RESET_DELAY + 1;
else RESET_DELAY <= RESET_DELAY;
end
end
wire ST_RESET;
assign ST_RESET = (RESET_DELAY == 100000 / 2) ? 0 : 1;
//==== SPI ST === //
always @(negedge RESET_n or posedge CLK_1M) begin
if (!RESET_n) begin
ST <= 0;
CS <= 1;
SCLK <= 1;
OK2 <= 0;
ROM_CK <= 0;
WORD_CNT <= 0;
end else
case (ST)
0: begin
ST <= 1;
CS <= 1;
SCLK <= 1;
WORD_CNT <= 0;
end
//--- WRITE REGISTER ---
1: begin
ST <= 30;
CS <= 1;
SCLK <= 0;
COUNTER <= 0;
ROM_CK <= 1;
end
2: begin
ST <= 3;
CS <= 0; //<----CS 0
SCLK <= 1;
{DIN, W_REG_DATA[15:1]} <= W_REG_DATA[15:0];
end
3: begin
ST <= 4;
SCLK <= 1;
end
4: begin
ST <= 5;
SCLK <= 0;
READ_DATA[15:0] <= {READ_DATA[14:0], DOUT};
COUNTER <= COUNTER + 1;
end
5: begin
if (COUNTER != 16) ST <= 2;
else begin
if (W_R == 0) begin
READ_DATA <= 0;
W_R <= 1;
W_REG_DATA <= {W_REG_DATA_R[15:8], 8'hff};
CS <= 1;
ST <= 2;
SCLK <= 0;
COUNTER <= 0;
end //read
else begin
WORD_CNT <= WORD_CNT + 1;
ST <= 6;
CS <= 1; //<----CS 1
end
end
end
6: begin
if ((WORD_CNT == 34) && (READ_DATA[7:0] == 8'h01)) OK2 <= OK2 | 2'b01;
else if ((WORD_CNT == 35) && (READ_DATA[7:0] == 8'h00)) OK2 <= OK2 | 2'b10;
if (WORD_CNT != W_WORD_NUM) ST <= 1;
else ST <= 7;
end
7: begin
ST <= ST;
end
//-----END-ST-------------------
//-----WRITE REGISTER TABLE-----
29: begin
W_REG_DATA <= {W_REG_DATA_T[14:8], 1'b0, W_REG_DATA_T[7:0]};
W_REG_DATA_R <= {W_REG_DATA_T[14:8], 1'b1, W_REG_DATA_T[7:0]};
W_R <= 0;
ST <= 2;
end
30: begin
ROM_CK <= 0;
if ((WORD_CNT >= 0) && (WORD_CNT <= 127)) W_REG_DATA_T[15:0] <= REG_DATA[15:0];
ST <= 29;
end
endcase
end
//--------ROM/RAM Table for Audio Codec Register ----
wire [15:0] REG_DATA;
reg ROM_CK;
SPI_RAM R (
.address(WORD_CNT),
.clock(ROM_CK),
.data(),
.wren(0),
.q(REG_DATA)
);
endmodule
| 6.862032 |
module AUDIO_SRCE (
input [15:0] EXT_DATA16,
output reg [15:0] DATA16_MIC,
input RESET_N,
input MCLK,
//output [15:0] DATA16_SIN ,
input SW_OBMIC_SIN,
input SAMPLE_TR,
output reg [7:0] ROM_ADDR,
output reg ROM_CK,
output reg L2,
//--test
output reg [7:0] ST,
output reg [7:0] CNT
);
always @(negedge RESET_N or posedge MCLK) begin
if (!RESET_N) begin
ST <= 0;
CNT <= 0;
ROM_ADDR <= 0;
ROM_CK <= 0;
end else begin
case (ST)
0: begin
ST <= 1;
end
1: begin
ST <= 2;
end
2: begin
ST <= 3;
end
3: begin
ST <= 4;
if (ROM_ADDR > 192) ROM_ADDR <= 0;
else ROM_ADDR <= ROM_ADDR + 1;
end
4: begin
ROM_CK <= 1;
if (SAMPLE_TR) begin
ST <= 5;
//DATA16_MIC[15:0] <= SW_OBMIC_SIN ? DATA16_SIN[15:0] : EXT_DATA16[15:0] ;
DATA16_MIC[15:0] <= SW_OBMIC_SIN ? 16'h0 : EXT_DATA16[15:0];
end
end
5: begin
ST <= 6;
ROM_CK <= 0;
end
6: begin
ST <= 0;
CNT <= 0;
end
endcase
end
end
/*
//SIN TABLE
SIN s(
.address (ROM_ADDR),
.clock (ROM_CK) ,
.data (0) ,
.wren(0),
.q (DATA16_SIN ) );
*/
endmodule
| 7.494379 |
modulename>audio_synthesis</modulename>
/// <filedescription>Ƶϳɡ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// </version>
`timescale 10ns / 1ps
module audio_synthesis_t #
(
parameter resolution_input = 8,
parameter resolution_output = 16
)
(
output [resolution_output - 1 : 0] AUDIO_OUT,
input [resolution_input - 1 : 0] MAIN_AUDIO_IN,
input MAIN_AUDIO_EN,
input [4:0] MAIN_AUDIO_VOLUMN,
input [resolution_input - 1 : 0] AUX_AUDIO_IN,
input AUX_AUDIO_EN,
input [4:0] AUX_AUDIO_VOLUMN,
input EN
);
reg [resolution_output - 1 : 0] // λ벢Ƶ
main_audio_align,
aux_audio_align;
always @* begin
if (MAIN_AUDIO_EN) begin
main_audio_align = MAIN_AUDIO_IN << (resolution_output - resolution_input);
main_audio_align = main_audio_align >> MAIN_AUDIO_VOLUMN;
end
else
main_audio_align = 0;
if (AUX_AUDIO_EN) begin
aux_audio_align = AUX_AUDIO_IN << (resolution_output - resolution_input);
aux_audio_align = aux_audio_align >> AUX_AUDIO_VOLUMN;
end
else
aux_audio_align = 0;
end
assign AUDIO_OUT = EN ? (main_audio_align + aux_audio_align) : 0;
endmodule
| 6.915106 |
module audio_top (
input wire clk,
input wire rst_n,
// config
input wire mix,
// audio shifter
input wire [15-1:0] rdata,
input wire [15-1:0] ldata,
input wire exchan,
output wire aud_bclk,
output wire aud_daclrck,
output wire aud_dacdat,
output wire aud_xck,
// I2C audio config
output wire i2c_sclk,
inout i2c_sdat
);
////////////////////////////////////////
// modules //
////////////////////////////////////////
// don't include these two modules for sim, as they have some probems in simulation
`ifndef SOC_SIM
// audio shifter
audio_shifter audio_shifter (
.clk (clk),
.nreset (rst_n),
.mix (mix),
.rdata (rdata),
.ldata (ldata),
.exchan (exchan),
.aud_bclk (aud_bclk),
.aud_daclrck(aud_daclrck),
.aud_dacdat (aud_dacdat),
.aud_xck (aud_xck)
);
// I2C audio config
I2C_AV_Config audio_config (
// host side
.iCLK (clk),
.iRST_N (rst_n),
// i2c side
.oI2C_SCLK(i2c_sclk),
.oI2C_SDAT(i2c_sdat)
);
`endif // SOC_SIM
endmodule
| 8.717327 |
module audio_tx (
input rst,
input clk,
input sck_bclk, //audio bit clock
input ws_lrc, //DAC sample rate left right clock
output reg sdata, //DAC audio data output
input [31:0] left_data, //left channel audio data,ws_lrc = 1
input [31:0] right_data, //right channel audio data,ws_lrc = 0
output reg read_data_en //read data enable
);
reg sck_bclk_d0; //delay sck_bclk
reg sck_bclk_d1; //delay sck_bclk
reg ws_lrc_d0; //delay ws_lrc
reg ws_lrc_d1; //delay ws_lrc
reg [31:0] left_data_shift; //left channel audio data shift register
reg [31:0] right_data_shift; //right channel audio data shift register
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
sck_bclk_d0 <= 1'b0;
sck_bclk_d1 <= 1'b0;
ws_lrc_d0 <= 1'b0;
ws_lrc_d1 <= 1'b0;
end else begin
//delay
sck_bclk_d0 <= sck_bclk;
sck_bclk_d1 <= sck_bclk_d0;
ws_lrc_d0 <= ws_lrc;
ws_lrc_d1 <= ws_lrc_d0;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) left_data_shift <= 32'd0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge
left_data_shift <= left_data;
else if(ws_lrc_d1 == 1'b1 && sck_bclk_d1 == 1'b1 && sck_bclk_d0 == 1'b0)//ws_lrc = 1 ,sck_bclk negedge
left_data_shift <= {left_data_shift[30:0], 1'b0};
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) right_data_shift <= 32'd0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge
right_data_shift <= right_data;
else if(ws_lrc_d1 == 1'b0 && sck_bclk_d1 == 1'b1 && sck_bclk_d0 == 1'b0)//ws_lrc = 0 ,sck_bclk negedge
right_data_shift <= {right_data_shift[30:0], 1'b0};
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) sdata <= 1'd0;
else if (ws_lrc_d1 == 1'b1) sdata <= left_data_shift[31];
else if (ws_lrc_d1 == 1'b0) sdata <= right_data_shift[31];
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) read_data_en <= 1'b0;
else if (ws_lrc_d1 == 1'b0 && ws_lrc_d0 == 1'b1) //ws_lrc posedge read the next audio data
read_data_en <= 1'b1;
else read_data_en <= 1'b0;
end
endmodule
| 7.491715 |
module wave_generator (
input wire clk,
input wire [15:0] freq,
output reg signed [9:0] wave_out
);
reg [5:0] i;
reg signed [7:0] amplitude[0:63];
reg [15:0] counter = 0;
initial begin
amplitude[0] = 0;
amplitude[1] = 7;
amplitude[2] = 13;
amplitude[3] = 19;
amplitude[4] = 25;
amplitude[5] = 30;
amplitude[6] = 35;
amplitude[7] = 40;
amplitude[8] = 45;
amplitude[9] = 49;
amplitude[10] = 52;
amplitude[11] = 55;
amplitude[12] = 58;
amplitude[13] = 60;
amplitude[14] = 62;
amplitude[15] = 63;
amplitude[16] = 63;
amplitude[17] = 63;
amplitude[18] = 62;
amplitude[19] = 60;
amplitude[20] = 58;
amplitude[21] = 55;
amplitude[22] = 52;
amplitude[23] = 49;
amplitude[24] = 45;
amplitude[25] = 40;
amplitude[26] = 35;
amplitude[27] = 30;
amplitude[28] = 25;
amplitude[29] = 19;
amplitude[30] = 13;
amplitude[31] = 7;
amplitude[32] = 0;
amplitude[33] = -7;
amplitude[34] = -13;
amplitude[35] = -19;
amplitude[36] = -25;
amplitude[37] = -30;
amplitude[38] = -35;
amplitude[39] = -40;
amplitude[40] = -45;
amplitude[41] = -49;
amplitude[42] = -52;
amplitude[43] = -55;
amplitude[44] = -58;
amplitude[45] = -60;
amplitude[46] = -62;
amplitude[47] = -63;
amplitude[48] = -63;
amplitude[49] = -63;
amplitude[50] = -62;
amplitude[51] = -60;
amplitude[52] = -58;
amplitude[53] = -55;
amplitude[54] = -52;
amplitude[55] = -49;
amplitude[56] = -45;
amplitude[57] = -40;
amplitude[58] = -35;
amplitude[59] = -30;
amplitude[60] = -25;
amplitude[61] = -19;
amplitude[62] = -13;
amplitude[63] = -7;
end
always @(posedge clk) begin
if (freq == 0) wave_out <= 0;
else if (counter == freq) begin
counter <= 0;
wave_out <= $signed(amplitude[i]);
i <= i + 1;
if (i == 63) i <= 0;
else i <= i + 1;
end else counter <= counter + 1;
end
endmodule
| 7.283079 |
module audio_wave #(
parameter BITS = 6
) (
input reset,
input clock,
input [1:0] form,
input [4:0] freq_id,
input new_f,
output reg [BITS-1:0] level
);
//parameters for types of waves
parameter SIN = 2'd0;
parameter TRI = 2'd1;
parameter SQ = 2'd2;
reg [9:0] index; //current scaled horizontal index (512 is halfway through a period)
reg [9:0] next_index; //place to put calculated index in anticipation of next cycle
reg [BITS-1:0] count; //counter that loops between 0 and 63 by default
reg [15:0] count_index; //frequency-adjusted index.
wire [15:0] period; //period and freq outputs
wire [15:0] freq;
reg [4:0] freq_id_rom; //buffered input
wire [BITS-1:0] value; //output from rom
//for sine values
audio_rom #(
.BITS(6)
) audio_rom (
.index(index),
.freq_id(freq_id_rom),
.level(value),
.freq(freq),
.period(period)
);
//on the positive clock edge
always @(posedge clock) begin
//given a new frequency, update the frequency id seen by the ROM
if (new_f) begin
freq_id_rom <= freq_id;
end
//increment count
count <= count + 1;
if (count == 0) begin //if the next cycle is beginning
index <= next_index;
//count_index loops between 0 and period
if (count_index >= (period << (BITS - 6))) begin
count_index <= 0;
end else begin //increment
count_index <= count_index + 1;
end
//calculate next index!
//there's a lot of time to do this calculation.
next_index <= {16'b0, count_index} * freq >> (BITS + 8);
//sine wave
if (form == SIN) begin
level <= value;
end /*else if (form == TRI) begin //triangle wave; phased out because it sounds awful with LPF
if (index < 256) level <= ((index) >> (BITS-2)) + 25;
else if (index < 512) level <= ((512-index) >> (BITS-2)) + 25;
else if (index < 768) level <= 25 - ((index - 512) >> (BITS-2));
else level <= 25 - ((1024 - index) >> (BITS-2));
end*/
else if (form == SQ) begin //square wave
if (index < 256) level <= 30;
else if (index < 512) level <= 0;
else if (index < 768) level <= 30;
else level <= 0;
end else begin //no sound catch-all
level <= 0;
end
end
end
endmodule
| 8.36702 |
module aud_buf
//
module aud_buf (aud_buffer_Data, aud_buffer_Q, aud_buffer_AlmostFull,
aud_buffer_Clock, aud_buffer_Empty, aud_buffer_Full, aud_buffer_RdEn,
aud_buffer_Reset, aud_buffer_WrEn) /* synthesis sbp_module=true */ ;
input [15:0]aud_buffer_Data;
output [15:0]aud_buffer_Q;
output aud_buffer_AlmostFull;
input aud_buffer_Clock;
output aud_buffer_Empty;
output aud_buffer_Full;
input aud_buffer_RdEn;
input aud_buffer_Reset;
input aud_buffer_WrEn;
aud_buffer aud_buffer_inst (.Data({aud_buffer_Data}), .Q({aud_buffer_Q}),
.AlmostFull(aud_buffer_AlmostFull), .Clock(aud_buffer_Clock),
.Empty(aud_buffer_Empty), .Full(aud_buffer_Full), .RdEn(aud_buffer_RdEn),
.Reset(aud_buffer_Reset), .WrEn(aud_buffer_WrEn));
endmodule
| 6.863983 |
module instr_rom (
input logic clk,
rst_n,
input logic [13:0] i_addr,
output logic [31:0] o_data
);
localparam INSTR_CNT = 12'd25;
wire [0:INSTR_CNT-1][31:0] instr_rom_cell = {
32'h00002517, //0x00000000
32'h71c50513, //0x00000004
32'h004005ef, //0x00000008
32'h40b50533, //0x0000000c
32'h00002eb7, //0x00000010
32'h710e8e93, //0x00000014
32'h00200193, //0x00000018
32'h03d51463, //0x0000001c
32'hffffe517, //0x00000020
32'h8fc50513, //0x00000024
32'h004005ef, //0x00000028
32'h40b50533, //0x0000002c
32'hffffeeb7, //0x00000030
32'h8f0e8e93, //0x00000034
32'h00300193, //0x00000038
32'h01d51463, //0x0000003c
32'h00301863, //0x00000040
32'h00100793, //0x00000044
32'h00000213, //0x00000048
32'h00320233, //0x0000004c
32'h00100193, //0x00000050
32'h40f181b3, //0x00000054
32'hc0001073, //0x00000058
32'h00000000, //0x0000005c
32'h00000000 //0x00000060
};
logic [11:0] instr_index;
logic [31:0] data;
assign instr_index = i_addr[13:2];
assign data = (instr_index >= INSTR_CNT) ? 0 : instr_rom_cell[instr_index];
always @(posedge clk or negedge rst_n)
if (~rst_n) o_data <= 0;
else o_data <= data;
endmodule
| 7.005566 |
module aukv_alu (
i_clk,
i_rstn,
i_operation,
i_rs1,
i_rs2,
o_rd,
i_cmp_a,
i_cmp_b,
i_cmp_sign,
o_lt,
o_ge,
o_eq,
o_ne
);
input i_clk;
input i_rstn;
input [3:0] i_operation;
input [31:0] i_rs1;
input [31:0] i_rs2;
output [31:0] o_rd;
input [31:0] i_cmp_a;
input [31:0] i_cmp_b;
input i_cmp_sign;
output o_lt;
output o_ge;
output o_eq;
output o_ne;
wire lt_u;
wire ge_u;
wire eq_u;
wire ne_u;
wire lt_s;
wire ge_s;
wire eq_s;
wire ne_s;
assign o_rd = ~i_rstn ? 32'd0 :
i_operation == 4'd0 ? i_rs1 + i_rs2 :
i_operation == 4'd1 ? i_rs1 - i_rs2 :
i_operation == 4'd2 ? i_rs1 | i_rs2 :
i_operation == 4'd3 ? i_rs1 & i_rs2 :
i_operation == 4'd4 ? i_rs1 ^ i_rs2 :
i_operation == 4'd5 ? i_rs1 << i_rs2 :
i_operation == 4'd6 ? i_rs1 >>> i_rs2 :
i_operation == 4'd7 ? i_rs1 >> i_rs2 :
32'd0;
assign lt_u = i_cmp_a < i_cmp_b ? 1'b1 : 1'b0;
assign ge_u = i_cmp_a >= i_cmp_b ? 1'b1 : 1'b0;
assign eq_u = i_cmp_a == i_cmp_b ? 1'b1 : 1'b0;
assign ne_u = i_cmp_a != i_cmp_b ? 1'b1 : 1'b0;
assign lt_s = $signed(i_cmp_a) < $signed(i_cmp_b) ? 1'b1 : 1'b0;
assign ge_s = $signed(i_cmp_a) >= $signed(i_cmp_b) ? 1'b1 : 1'b0;
assign eq_s = $signed(i_cmp_a) == $signed(i_cmp_b) ? 1'b1 : 1'b0;
assign ne_s = $signed(i_cmp_a) != $signed(i_cmp_b) ? 1'b1 : 1'b0;
assign o_lt = i_cmp_sign ? lt_s : lt_u;
assign o_ge = i_cmp_sign ? ge_s : ge_u;
assign o_eq = i_cmp_sign ? eq_s : eq_u;
assign o_ne = i_cmp_sign ? ne_s : ne_u;
endmodule
| 8.249171 |
module aukv_csr_regfile (
i_clk,
i_rstn,
i_exception_id,
i_exception,
i_pc,
i_instr,
i_wr_addr,
i_rd_addr,
i_data,
i_we,
i_rd,
i_op,
o_mtvec,
o_data
);
input i_clk;
input i_rstn;
input [7:0] i_exception_id;
input i_exception;
input [1:0] i_op;
input [31:0] i_pc;
input [31:0] i_instr;
input [11:0] i_wr_addr;
input [11:0] i_rd_addr;
input [31:0] i_data;
input i_we;
input i_rd;
output [31:0] o_mtvec;
output [31:0] o_data;
wire exception_lth;
reg exception_d1;
reg [31:0] instr_d1;
reg [31:0] mie;
reg [31:0] mstatus;
reg [31:0] mtval;
reg [31:0] mtvec;
reg [31:0] mepc;
reg [31:0] mcause;
assign exception_lth = (~exception_d1) & i_exception;
assign mcause_tmp = i_exception_id == 8'h1 ? 32'h2 : 32'h0;
assign mtval_tmp = i_exception_id == 8'h1 ? instr_d1 : 32'h0;
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
instr_d1 <= 'b0;
end else begin
instr_d1 <= i_instr;
end
end
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
exception_d1 <= 1'b0;
mie <= 32'h0;
mstatus <= 32'h0;
mtval <= 32'h0;
mtvec <= 32'h0;
mepc <= 32'h0;
mcause <= 32'h0;
end else begin
exception_d1 <= i_exception;
if (i_we) begin
if (i_wr_addr == 12'h304) begin
if (i_op == 2'h0) begin
mie <= mie;
end else if (i_op == 2'h1) begin
mie <= i_data;
end else if (i_op == 2'h2) begin
mie <= mie | i_data;
end else begin
mie <= mie & (~i_data);
end
end else if (i_wr_addr == 12'h300) begin
if (i_op == 2'h0) begin
mstatus <= mstatus;
end else if (i_op == 2'h1) begin
mstatus <= i_data;
end else if (i_op == 2'h2) begin
mstatus <= mstatus | i_data;
end else begin
mstatus <= mstatus & (~i_data);
end
end else if (i_wr_addr == 12'h305) begin
if (i_op == 2'h0) begin
mtvec <= mtvec;
end else if (i_op == 2'h1) begin
mtvec <= i_data;
end else if (i_op == 2'h2) begin
mtvec <= mtvec | i_data;
end else begin
mtvec <= mtvec & (~i_data);
end
end
end
if (exception_lth) begin
mcause <= mcause_tmp;
mepc <= i_pc;
mtval <= mtval_tmp;
end else begin
if (i_we) begin
if (i_wr_addr == 12'h343) begin
if (i_op == 2'h0) begin
mcause <= mcause;
end else if (i_op == 2'h1) begin
mcause <= i_data;
end else if (i_op == 2'h2) begin
mcause <= mcause | i_data;
end else begin
mcause <= mcause & (~i_data);
end
end else if (i_wr_addr == 12'h343) begin
if (i_op == 2'h0) begin
mtval <= mtval;
end else if (i_op == 2'h1) begin
mtval <= i_data;
end else if (i_op == 2'h2) begin
mtval <= mtval | i_data;
end else begin
mtval <= mtval & (~i_data);
end
end
end
end
end
end
assign o_mtvec = {mtvec[31:2], 2'h0};
assign o_data= i_rd & (i_rd_addr==12'h304) ? mie :
i_rd & (i_rd_addr==12'h305) ? mtvec:
i_rd & (i_rd_addr==12'h300) ? mstatus:
i_rd & (i_rd_addr==12'h341) ? mepc:
i_rd & (i_rd_addr==12'h342) ? mcause:
i_rd & (i_rd_addr==12'h343) ? mtval:
32'h0;
endmodule
| 6.746751 |
module aukv_fetch (
i_clk,
i_rstn,
i_instr_data,
i_instr_data_valid,
o_instr_addr,
o_instr_addr_valid,
i_stall,
i_branch_addr,
i_evec_addr,
i_branch_en,
i_exception,
o_pc,
o_instr,
o_instr_valid
);
input i_clk;
input i_rstn;
input [31:0] i_instr_data;
input i_instr_data_valid;
output o_instr_addr_valid;
output [31:0] o_instr_addr;
input i_stall;
input [31:0] i_branch_addr;
input [31:0] i_evec_addr;
input i_branch_en;
input i_exception;
output [31:0] o_pc;
output [31:0] o_instr;
output o_instr_valid;
reg [31:0] pc;
reg en_buff;
reg branch_lat;
reg [31:0] data_buff;
reg start;
//reg flush;
wire en_stall;
wire branch_buff;
wire en;
wire ins_valid;
wire [31:0] t_pc;
wire branch;
assign branch = i_branch_en | i_exception;
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
start <= 1'b1;
end else begin
start <= 1'b0;
end
end
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
branch_lat <= 1'b0;
end else begin
if (branch_buff) begin
if (branch) begin
branch_lat <= 1'b1;
end
end else begin
if (i_instr_data_valid) begin
branch_lat <= 1'b0;
end
end
end
end
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
en_buff <= 1'b0;
data_buff <= 32'h33;
end else begin
if (~en_buff) begin
if (i_stall & i_instr_data_valid) begin
en_buff <= 1'b1;
data_buff <= i_instr_data;
end
end else begin
if (~i_stall) begin
en_buff <= 1'b0;
end
end
end
end
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
pc <= 32'h00000000;
end else begin
if (i_stall) begin
if (i_exception) begin
pc <= i_evec_addr;
end
end else begin
if (i_branch_en) begin
//flush<=1'b1;
pc <= i_branch_addr + 32'h4;
end else begin
if (en) begin
pc <= pc + 4;
end
end
end
end
end
assign en_stall = en_buff & (~i_stall);
assign branch_buff = branch_lat & i_instr_data_valid;
assign en = i_rstn & (i_instr_data_valid | start | en_buff | branch) & (~i_stall);
assign ins_valid = (i_instr_data_valid & (~branch) & (~branch_buff) & (~i_stall)) & (~start);
assign t_pc = i_exception ? i_evec_addr : i_branch_en ? i_branch_addr : pc;
assign o_instr_addr = t_pc;
assign o_pc = t_pc - 4;
assign o_instr = en_stall ? data_buff : ins_valid ? i_instr_data : 32'h33;
assign o_instr_valid = ins_valid;
assign o_instr_addr_valid = en;
endmodule
| 6.994719 |
module aukv_gpr_regfile (
i_clk,
i_rstn,
i_rs1_addr,
i_rs2_addr,
i_rd_addr,
i_we,
i_rd_data,
o_rs1data,
o_rs2data
);
input i_clk;
input i_rstn;
input [4:0] i_rs1_addr;
input [4:0] i_rs2_addr;
input [4:0] i_rd_addr;
input [31:0] i_rd_data;
input i_we;
output [31:0] o_rs1data;
output [31:0] o_rs2data;
reg [32-1:0] regfile[31:0];
integer i;
always @(posedge i_clk, negedge i_rstn) begin
if (~i_rstn) begin
for (i = 0; i < 32; i = i + 1) begin
regfile[i] <= 32'h0;
end
end else begin
if (i_we) begin
if (i_rd_addr == 5'd0) begin
regfile[i_rd_addr] <= 32'h0;
end else begin
regfile[i_rd_addr] <= i_rd_data;
end
end
end
end
assign o_rs1data = regfile[i_rs1_addr];
assign o_rs2data = regfile[i_rs2_addr];
endmodule
| 7.974113 |
module aurora8_RESET_LOGIC (
//***********************************Port Declarations*******************************
// User I/O
input RESET,
USER_CLK,
INIT_CLK_P,
INIT_CLK_N //, GT_RESET_IN;
, input TX_LOCK_IN,
PLL_NOT_LOCKED,
output SYSTEM_RESET,
INIT_CLK_O,
output reg GT_RESET_OUT
);
`include "function.v"
`define DLY #1
//**************************Internal Register Declarations****************************
reg [0:3] debounce_gt_rst_r;
reg [0:3] reset_debounce_r;
reg reset_debounce_r2;
reg reset_debounce_r3;
reg reset_debounce_r4;
//********************************Wire Declarations**********************************
wire init_clk_i;
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b0000;
else reset_debounce_r <= {RESET, reset_debounce_r[0:2]};
always @(posedge USER_CLK) begin
reset_debounce_r2 <= &reset_debounce_r;
reset_debounce_r3 <= reset_debounce_r2 || !TX_LOCK_IN;
reset_debounce_r4 <= reset_debounce_r3;
end
assign SYSTEM_RESET = reset_debounce_r4 || PLL_NOT_LOCKED;
// Assign an IBUFDS to INIT_CLK
IBUFDS init_clk_ibufg_i (
.I (INIT_CLK_P),
.IB(INIT_CLK_N),
.O (init_clk_i)
);
assign INIT_CLK_O = init_clk_i;
localparam NO = 0, YES = 1, WAIT = 2, N_STATE = 3, N_MIN_GTX_RESET = 10;
reg [log2(N_STATE)-1:0] state;
reg [log2(N_MIN_GTX_RESET)-1:0] ctr;
assign gt_rst_r = &debounce_gt_rst_r;
always @(posedge init_clk_i) begin
debounce_gt_rst_r <= {RESET, debounce_gt_rst_r[0:2]};
case (state)
default: begin
GT_RESET_OUT <= `FALSE;
if (gt_rst_r) begin
ctr <= 1;
GT_RESET_OUT <= `TRUE;
state <= YES;
end
end
YES: begin
GT_RESET_OUT <= `TRUE;
ctr <= ctr + `TRUE;
if (!ctr) state <= WAIT;
end
WAIT: begin
GT_RESET_OUT <= `TRUE;
if (!debounce_gt_rst_r) begin
GT_RESET_OUT <= `FALSE;
state <= NO;
end
end
endcase
end //always
endmodule
| 7.65897 |
module aurora_64b66b_1_DESCRAMBLER_64B66B #
(
parameter RX_DATA_WIDTH = 32
)
(
// User Interface
SCRAMBLED_DATA_IN,
UNSCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
input [0:(RX_DATA_WIDTH-1)] SCRAMBLED_DATA_IN;
input DATA_VALID_IN;
output [(RX_DATA_WIDTH-1):0] UNSCRAMBLED_DATA_OUT;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************Internal Register Declarations********************
reg [57:0] descrambler;
integer i;
reg [57:0] poly;
reg [0:(RX_DATA_WIDTH-1)] tempData;
reg [(RX_DATA_WIDTH-1):0] unscrambled_data_i;
reg xorBit;
//*********************************Main Body of Code***************************
always @(descrambler,SCRAMBLED_DATA_IN)
begin
poly = descrambler;
for (i=0;i<=(RX_DATA_WIDTH-1);i=i+1)
begin
xorBit = SCRAMBLED_DATA_IN[i] ^ poly[38] ^ poly[57];
poly = {poly[56:0],SCRAMBLED_DATA_IN[i]};
tempData[i] = xorBit;
end
end
always @(posedge USER_CLK)
begin
if (SYSTEM_RESET)
begin
unscrambled_data_i <= `DLY 'h0;
descrambler <= `DLY 58'h155_5555_5555_5555;
end
else if (DATA_VALID_IN )
begin
unscrambled_data_i <= `DLY tempData;
descrambler <= `DLY poly;
end
end
//________________ Scrambled Data assignment to output port _______________
assign UNSCRAMBLED_DATA_OUT = unscrambled_data_i;
endmodule
| 7.200193 |
module aurora_64b66b_1_SCRAMBLER_64B66B #
(
parameter TX_DATA_WIDTH = 32
)
(
// User Interface
UNSCRAMBLED_DATA_IN,
SCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
input [0:(TX_DATA_WIDTH-1)] UNSCRAMBLED_DATA_IN;
input DATA_VALID_IN;
output [(TX_DATA_WIDTH-1):0] SCRAMBLED_DATA_OUT;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************Internal Register Declarations********************
integer i;
reg [57:0] poly;
reg [57:0] scrambler = 58'h155_5555_5555_5555;
reg [0:(TX_DATA_WIDTH-1)] tempData = {TX_DATA_WIDTH{1'b0}};
reg xorBit;
reg [(TX_DATA_WIDTH-1):0] SCRAMBLED_DATA_OUT;
//*********************************Main Body of Code***************************
always @(scrambler,UNSCRAMBLED_DATA_IN)
begin
poly = scrambler;
for (i=0;i<=(TX_DATA_WIDTH-1);i=i+1)
begin
xorBit = UNSCRAMBLED_DATA_IN[i] ^ poly[38] ^ poly[57];
poly = {poly[56:0],xorBit};
tempData[i] = xorBit;
end
end
//________________ Scrambled Data assignment to output port _______________
always @(posedge USER_CLK)
begin
if (DATA_VALID_IN)
begin
SCRAMBLED_DATA_OUT <= `DLY tempData;
scrambler <= `DLY poly;
end
end
endmodule
| 7.200193 |
module aurora_64b66b_1_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter BC = DATA_WIDTH>>3, //Byte count
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC and 3 => USER K
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input CHANNEL_UP;
reg [0:(REM_WIDTH-1)] LL_OP_REM;
reg [(STRB_WIDTH-1):0] i;
reg found_rem = 1'b0;
reg new_pkt_r;
wire new_pkt;
wire [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP_i;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign AXI4_S_IP_TX_TKEEP_i = AXI4_S_IP_TX_TKEEP;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
generate
if(USE_4_NFC==0)
begin
always @ (found_rem or AXI4_S_IP_TX_TKEEP_i)
begin
found_rem = 1'b0;
LL_OP_REM = {(STRB_WIDTH-1){1'b0}};
for (i = 0; i < STRB_WIDTH; i = i + 1) begin
if ((AXI4_S_IP_TX_TKEEP_i[i] == 1'b0) && (found_rem == 1'b0)) begin
LL_OP_REM = i;
found_rem = 1'b1;
end
end
end
end
endgenerate
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(!CHANNEL_UP)
new_pkt_r <= `DLY 1'b0;
else
new_pkt_r <= `DLY new_pkt;
end
endmodule
| 7.200193 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] HARD_ERR;
input [0:1] LANE_UP;
//System Interface
input USER_CLK;
output CHANNEL_HARD_ERR;
//*****************************External Register Declarations*************************
reg CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
assign channel_hard_err_c = |HARD_ERR ;
always @(posedge USER_CLK)
begin
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
end
endmodule
| 7.591032 |
module aurora_64b66b_1_common_logic_cbcc #
(
parameter BACKWARD_COMP_MODE1 = 1'b0 //disable check for interCB gap
)
(
input start_cb_writes_in,
input do_rd_en_in,
input bit_err_chan_bond_in,
input final_gater_for_fifo_din_in,
input any_vld_btf_in,
input start_cb_writes_lane1_in,
input do_rd_en_lane1_in,
input bit_err_chan_bond_lane1_in,
input final_gater_for_fifo_din_lane1_in,
input any_vld_btf_lane1_in,
input cbcc_fifo_reset_wr_clk,
input cbcc_fifo_reset_rd_clk,
output reg all_start_cb_writes_out,
output reg master_do_rd_en_out,
output reg cb_bit_err_out,
output reg all_vld_btf_out,
input rxrecclk_to_fabric,
input rxusrclk2_in
);
//********************************* Reg declaration **************************
reg second_cb_write_failed =1'b0;
reg [3:0] first_cb_to_fifo_wr_window;
reg first_cb_write_failed = 1'b0;
//********************************* Main Body of Code**************************
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
begin
all_start_cb_writes_out <= `DLY 1'b0;
end
else
begin
all_start_cb_writes_out <= `DLY start_cb_writes_in & start_cb_writes_lane1_in;
end
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
begin
all_vld_btf_out <= `DLY 1'b0;
end
else
begin
all_vld_btf_out <= `DLY any_vld_btf_in & any_vld_btf_lane1_in;
end
end
always @(posedge rxusrclk2_in)
begin
if(cbcc_fifo_reset_rd_clk)
begin
master_do_rd_en_out <= `DLY 1'b0;
end
else
begin
master_do_rd_en_out <= `DLY do_rd_en_lane1_in;
end
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
second_cb_write_failed <= `DLY 1'b0;
else
second_cb_write_failed <= bit_err_chan_bond_in | bit_err_chan_bond_lane1_in;
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
first_cb_to_fifo_wr_window <= 4'd0;
else if(final_gater_for_fifo_din_in & final_gater_for_fifo_din_lane1_in)
first_cb_to_fifo_wr_window <= 4'd0;
else if(final_gater_for_fifo_din_in | final_gater_for_fifo_din_lane1_in)
first_cb_to_fifo_wr_window <= first_cb_to_fifo_wr_window + 1'b1;
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
first_cb_write_failed <= `DLY 1'b0;
else if(first_cb_to_fifo_wr_window >= 4'd7)
first_cb_write_failed <= `DLY 1'b1;
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
cb_bit_err_out <= `DLY 1'b0;
else
cb_bit_err_out <= (BACKWARD_COMP_MODE1) ? first_cb_write_failed : first_cb_write_failed | second_cb_write_failed ;
end
endmodule
| 7.200193 |
module monitors the GTX to detect hard
// errors. All errors are reported to the Global Logic Interface.
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_ERR_DETECT
(
// Lane Init SM Interface
ENABLE_ERR_DETECT,
HARD_ERR_RESET,
// Global Logic Interface
HARD_ERR,
SOFT_ERR,
//Sym Decoder interface
ILLEGAL_BTF,
// GTX Interface
RX_BUF_ERR,
TX_BUF_ERR,
RX_HEADER_0,
RX_HEADER_1,
RXDATAVALID_IN,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// Lane Init SM Interface
input ENABLE_ERR_DETECT;
output HARD_ERR_RESET;
// Sym decoder Interface
input ILLEGAL_BTF;
// GTX Interface
input RX_BUF_ERR;
input TX_BUF_ERR;
input RX_HEADER_0;
input RX_HEADER_1;
input RXDATAVALID_IN;
// System Interface
input USER_CLK;
// Global Logic Interface
output HARD_ERR;
output SOFT_ERR;
//**************************External Register Declarations****************************
reg HARD_ERR;
reg SOFT_ERR;
//*********************************Main Body of Code**********************************
//____________________________ Error Processing _________________________________
// Detect Soft Errors
always @(posedge USER_CLK)
if(ENABLE_ERR_DETECT)
begin
SOFT_ERR <= `DLY (((RX_HEADER_0 == RX_HEADER_1) | ILLEGAL_BTF) & RXDATAVALID_IN );
end
else
begin
SOFT_ERR <= `DLY 1'b0;
end
// Detect Hard Errors
always @(posedge USER_CLK)
if(ENABLE_ERR_DETECT)
begin
HARD_ERR <= `DLY (RX_BUF_ERR | TX_BUF_ERR);
end
else
begin
HARD_ERR <= `DLY 1'b0;
end
// Assert hard error reset when there is a hard error. This assignment
// just renames the two fanout branches of the hard error signal.
assign HARD_ERR_RESET = HARD_ERR;
endmodule
| 7.591032 |
module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_GLOBAL_LOGIC #
(
parameter INTER_CB_GAP = 5'd9
)
(
// GTX Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
CHAN_BOND_RESET,
// Aurora Lane Interface
LANE_UP,
HARD_ERR,
GEN_NA_IDLES,
GEN_CH_BOND,
RESET_LANES,
GOT_NA_IDLES,
GOT_CCS,
REMOTE_READY,
GOT_CBS,
GOT_IDLES,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP_RX_IF,
CHANNEL_UP_TX_IF,
CHANNEL_HARD_ERR,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTX Interface
input [0:1] CH_BOND_DONE;
output EN_CHAN_SYNC;
output CHAN_BOND_RESET;
// Aurora Lane Interface
input [0:1] LANE_UP;
input [0:1] HARD_ERR;
input [0:1] GOT_NA_IDLES;
input [0:1] GOT_CCS;
input [0:1] REMOTE_READY;
input [0:1] GOT_CBS;
input [0:1] GOT_IDLES;
output GEN_NA_IDLES;
output [0:1] GEN_CH_BOND;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input TXDATAVALID_IN;
output CHANNEL_UP_RX_IF;
output CHANNEL_UP_TX_IF;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire reset_channel_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_64b66b_1_CHANNEL_INIT_SM channel_init_sm_i
(
// GTX Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
.CHAN_BOND_RESET(CHAN_BOND_RESET),
// Aurora Lane Interface
.GEN_NA_IDLES(GEN_NA_IDLES),
.RX_NA_IDLES(GOT_NA_IDLES),
.RX_CC(GOT_CCS),
.REMOTE_READY(REMOTE_READY),
.RX_CB(GOT_CBS),
.RX_IDLES(GOT_IDLES),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.LANE_UP(LANE_UP),
.CHANNEL_UP_TX_IF(CHANNEL_UP_TX_IF),
.CHANNEL_UP_RX_IF(CHANNEL_UP_RX_IF)
);
// Idle and verification sequence generator module.
aurora_64b66b_1_CHANNEL_BOND_GEN #
(
.INTER_CB_GAP (INTER_CB_GAP)
)channel_bond_gen_i
(
// Channel Init SM Interface
.CHANNEL_UP(CHANNEL_UP_TX_IF),
// Aurora Lane Interface
.GEN_CH_BOND(GEN_CH_BOND),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
// Channel Error Management module.
aurora_64b66b_1_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR)
);
endmodule
| 8.183782 |
module aurora_64b66b_1_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter BC = DATA_WIDTH >> 3, //Byte count
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
wire [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP_i;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TKEEP = AXI4_S_OP_TKEEP_i;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP_i = (LL_IP_REM == {REM_WIDTH{1'b0}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 7.200193 |
module aurora_64b66b_1_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
LINK_RESET_IN,
POWER_DOWN,
FSM_RESETDONE,
SYSTEM_RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input POWER_DOWN;
input LINK_RESET_IN;
input FSM_RESETDONE;
output SYSTEM_RESET;
//************************** Register Declarations***********************************
reg SYSTEM_RESET = 1'b1;
//********************************Wire Declarations**********************************
wire fsm_resetdone_sync;
wire power_down_sync;
wire link_reset_sync;
//*********************************Main Body of Code**********************************
aurora_64b66b_1_rst_sync #(
.c_mtbf_stages(5)
) u_rst_done_sync (
.prmry_in (FSM_RESETDONE),
.scndry_aclk(USER_CLK),
.scndry_out (fsm_resetdone_sync)
);
aurora_64b66b_1_rst_sync #(
.c_mtbf_stages(5)
) u_link_rst_sync (
.prmry_in (LINK_RESET_IN),
.scndry_aclk(USER_CLK),
.scndry_out (link_reset_sync)
);
aurora_64b66b_1_rst_sync #(
.c_mtbf_stages(5)
) u_pd_sync (
.prmry_in (POWER_DOWN),
.scndry_aclk(USER_CLK),
.scndry_out (power_down_sync)
);
always @(posedge USER_CLK)
SYSTEM_RESET <= RESET || !fsm_resetdone_sync || power_down_sync || link_reset_sync;
endmodule
| 7.200193 |
module takes regular data in Aurora format
// and transforms it to LocalLink formatted data
//
//
//
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_RX_STREAM_DATAPATH
(
//Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
//Flow control signals
// Global Logic
CHANNEL_UP,
//RX LocalLink Interface
RX_D,
RX_SRC_RDY_N,
//System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:127] RX_PE_DATA;
input [0:1] RX_PE_DATA_V;
// Global Logic
input CHANNEL_UP;
//LocalLink Interface
output [0:127] RX_D;
output RX_SRC_RDY_N;
//System Interface
input USER_CLK;
input RESET;
//****************************External Register Declarations**************************
reg [0:127] RX_D;
reg RX_SRC_RDY_N;
//*********************************Wire Declarations**********************************
wire src_rdy_n_c;
wire rx_pe_data_v_c;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
if(RESET)
RX_D <= `DLY 128'b0;
else if ( CHANNEL_UP & |RX_PE_DATA_V )
RX_D <= `DLY RX_PE_DATA;
assign rx_pe_data_v_c = & RX_PE_DATA_V;
assign src_rdy_n_c = (CHANNEL_UP & rx_pe_data_v_c);
//Register the SRC_RDY_N signal
always @(posedge USER_CLK)
if(RESET)
RX_SRC_RDY_N <= `DLY 1'b1;
else if( src_rdy_n_c )
RX_SRC_RDY_N <= `DLY 1'b0;
else
RX_SRC_RDY_N <= `DLY 1'b1;
endmodule
| 6.652678 |
module aurora_64b66b_1_SUPPORT_RESET_LOGIC
(
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input GT_RESET_IN;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r = 4'h0;
reg SYSTEM_RESET = 1'b1;
reg gt_rst_r = 1'b0;
reg [19:0] dly_gt_rst_r = 20'h00000;
(* ASYNC_REG = "true" *) (* shift_extract = "{no}" *) reg [0:3] debounce_gt_rst_r = 4'h0;
wire gt_rst_sync;
//*********************************Main Body of Code**********************************
//Reset sync from INIT_CLK to USER_CLK
aurora_64b66b_1_rst_sync_exdes #
(
.c_mtbf_stages (5)
)u_rst_sync_gt
(
.prmry_in (gt_rst_r),
.scndry_aclk (USER_CLK),
.scndry_out (gt_rst_sync)
);
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK )
if(gt_rst_sync)
reset_debounce_r <= 4'b1111;
else
reset_debounce_r <= {RESET,reset_debounce_r[0:2]};
always @ (posedge USER_CLK)
SYSTEM_RESET <= &reset_debounce_r;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge INIT_CLK)
debounce_gt_rst_r <= {GT_RESET_IN,debounce_gt_rst_r[0:2]};
always @(posedge INIT_CLK)
gt_rst_r <= `DLY &debounce_gt_rst_r;
// Delay RESET assertion to GT.This will ensure all logic is reset first before GT is reset
always @ (posedge INIT_CLK)
begin
dly_gt_rst_r <= `DLY {dly_gt_rst_r[18:0],gt_rst_r};
end
assign GT_RESET_OUT = dly_gt_rst_r[18];
endmodule
| 7.200193 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_TX_STREAM
(
// LocalLink Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// Clock Compensation Interface
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
TX_PE_DATA_V,
TX_PE_DATA,
GEN_CC,
// GTX Interface
TXDATAVALID_IN,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink Interface
input [0:127] TX_D;
input TX_SRC_RDY_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output [0:1] TX_PE_DATA_V;
output [0:127] TX_PE_DATA;
output [0:1] GEN_CC;
// GTX Interface
input TXDATAVALID_IN;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL_SM and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
// TX_LL_Datapath module
aurora_64b66b_1_TX_STREAM_DATAPATH tx_stream_datapath_i
(
// LocalLink Interface
.TX_D(TX_D),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.TX_DST_RDY_N(TX_DST_RDY_N),
// System Interface
.USER_CLK(USER_CLK)
);
// TX_STREAM_Control module
aurora_64b66b_1_TX_STREAM_CONTROL_SM tx_stream_control_sm_i
(
// LocalLink Interface
.TX_DST_RDY_N(TX_DST_RDY_N),
// Clock Compensation Interface
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
// Aurora Lane Interface
.GEN_CC(GEN_CC),
// GTX Interface
.TXDATAVALID_IN(TXDATAVALID_IN),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module pipelines the data path in compliance
// with Local Link protocol. Provides data to Aurora Lane
// in the required format
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_1_TX_STREAM_DATAPATH
(
// LocalLink Interface
TX_D,
TX_SRC_RDY_N,
// Aurora Lane Interface
TX_PE_DATA_V,
TX_PE_DATA,
// TX_STREAM Control Module Interface
TX_DST_RDY_N,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink Interface
input [0:127] TX_D;
input TX_SRC_RDY_N;
// Aurora Lane Interface
output [0:1] TX_PE_DATA_V;
output [0:127] TX_PE_DATA;
// TX_STREAM Control Module Interface
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
//**************************External Register Declarations****************************
reg [0:127] TX_PE_DATA;
reg [0:1] TX_PE_DATA_V;
//******************************Internal Wire Declarations****************************
wire in_frame_c;
wire ll_valid_c;
wire [0:127] tx_pe_data_c;
wire [0:1] tx_pe_data_v_c;
//*********************************Main Body of Code**********************************
// LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
assign ll_valid_c = !TX_SRC_RDY_N && !TX_DST_RDY_N;
assign in_frame_c = ll_valid_c ;
// Multiplex between UFC Messages & User data
assign tx_pe_data_c = TX_D;
//Assign tx_pe_data_v_c based on Protocol rules
//IN SA=1 Following rules are followed
//1. Lanes higher than SEP can't have data
//2. UFCH is sent only on the last lane
assign tx_pe_data_v_c[0] =
(ll_valid_c) ? 1'b1 :
1'b0 ;
assign tx_pe_data_v_c[1] =
(ll_valid_c) ? 1'b1 :
1'b0 ;
// Implement the data out register.
always @(posedge USER_CLK)
begin
TX_PE_DATA <= `DLY tx_pe_data_c;
TX_PE_DATA_V <= `DLY tx_pe_data_v_c;
end
endmodule
| 7.885372 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 16 from gtx to 32 into the aurora.
/////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_1_WIDTH_CONVERSION #
(
parameter INPUT_WIDTH =2,
parameter OUTPUT_WIDTH=4
)
(
//Output to the Aurora Protocol interface
DATA_OUT,
//Input from the GTX
DATA_IN,
// Sync header from GTX Interface
HEADER_IN,
DATAVALID_IN,
// Sync header to Aurora
HEADER_OUT,
DATAVALID_OUT,
//Clock and reset
USER_CLK,
ENABLE,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
input RESET;
input USER_CLK;
input ENABLE;
input [INPUT_WIDTH*8-1:0] DATA_IN;
output [OUTPUT_WIDTH*8-1:0] DATA_OUT;
output [1:0] HEADER_OUT;
output DATAVALID_OUT;
//*****************************MGT Interface**************************
input [1:0] HEADER_IN;
input DATAVALID_IN;
//*****************************External Register Declarations**************************
reg [OUTPUT_WIDTH*8-1:0] DATA_OUT;
reg [1:0] HEADER_OUT;
//*****************************Internal Register Declarations**************************
reg [INPUT_WIDTH*8-1:0] data_in_r;
reg [INPUT_WIDTH*8-1:0] data_in_r2;
reg [1:0] header_in_r;
reg [1:0] header_in_r2;
reg datavalid_r;
reg datavalid_r2;
reg datavalid_neg_r;
reg datavalid_pos_r;
reg state;
//*****************************Beginning of Code *************************
always @(posedge USER_CLK)
begin
data_in_r <= `DLY DATA_IN;
data_in_r2 <= `DLY data_in_r;
header_in_r <= `DLY HEADER_IN;
header_in_r2 <= `DLY header_in_r;
end
always @(posedge USER_CLK)
begin
datavalid_r <= `DLY DATAVALID_IN;
datavalid_r2 <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
begin
if(RESET)
state <= `DLY 1'b1;
else if (ENABLE && datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b0;
else if (ENABLE && !datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b1;
end
always @(posedge USER_CLK)
if(ENABLE)
begin
datavalid_pos_r <= `DLY datavalid_r;
end
always @(negedge USER_CLK)
begin
datavalid_neg_r <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
if(RESET) DATA_OUT <= `DLY 32'b0;
else if(ENABLE)
begin
if(state)
DATA_OUT <= `DLY {data_in_r2,data_in_r};
else if(!state)
DATA_OUT <= `DLY {data_in_r,DATA_IN};
end
always @(posedge USER_CLK)
if (RESET) HEADER_OUT <= `DLY 2'b0;
else if(ENABLE)
begin
if(!state)
HEADER_OUT <= `DLY header_in_r;
else if(state)
HEADER_OUT <= `DLY header_in_r2;
end
assign DATAVALID_OUT = datavalid_pos_r;
endmodule
| 6.595174 |
module aurora_64b66b_m_0_EXAMPLE_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_4_NFC = 0, // 0 => PDU, 1 => NFC, 2 => UFC and 3 => USER K
parameter BC = DATA_WIDTH >> 3, //Byte count
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY,
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
input USER_CLK;
input RESET;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
wire [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP_i;
wire [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA_INT;
wire [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP_INT;
wire AXI4_S_OP_TVALID_INT;
wire AXI4_S_OP_TLAST_INT;
wire AXI4_S_IP_TREADY_INT;
wire reset_n;
wire [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA_i;
assign reset_n = !RESET;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = AXI4_S_OP_TDATA_i;
generate
if (USE_4_NFC == 0) begin
assign AXI4_S_OP_TKEEP = AXI4_S_OP_TKEEP_i;
end
endgenerate
assign AXI4_S_OP_TDATA_INT = LL_IP_DATA;
assign AXI4_S_OP_TVALID_INT = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST_INT = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP_INT = (LL_IP_REM == {REM_WIDTH{1'b0}})? ({STRB_WIDTH{1'b1}}) :
(~({STRB_WIDTH{1'b1}}>>(LL_IP_REM)));
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY_INT;
aurora_64b66b_m_0_reg_slice_0 axis_reg_i (
.aclk(USER_CLK),
.aresetn(reset_n),
.s_axis_tready(AXI4_S_IP_TREADY_INT),
.m_axis_tready(AXI4_S_IP_TREADY),
.s_axis_tkeep(AXI4_S_OP_TKEEP_INT),
.m_axis_tkeep(AXI4_S_OP_TKEEP_i),
.s_axis_tlast(AXI4_S_OP_TLAST_INT),
.m_axis_tlast(AXI4_S_OP_TLAST),
.s_axis_tvalid(AXI4_S_OP_TVALID_INT),
.s_axis_tdata(AXI4_S_OP_TDATA_INT),
.m_axis_tvalid(AXI4_S_OP_TVALID),
.m_axis_tdata(AXI4_S_OP_TDATA_i)
);
endmodule
| 7.200193 |
module aurora_64b66b_support_reset_logic
(
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
input GT_RESET_IN;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r = 4'h0;
reg SYSTEM_RESET = 1'b1;
reg gt_rst_r = 1'b0;
reg [19:0] dly_gt_rst_r = 20'h00000;
(* ASYNC_REG = "true" *) (* shift_extract = "{no}" *) reg [0:3] debounce_gt_rst_r = 4'h0;
wire gt_rst_sync;
//*********************************Main Body of Code**********************************
//Reset sync from INIT_CLK to USER_CLK
aurora_64b66b_rst_sync_exdes #
(
.c_mtbf_stages (5)
)u_rst_sync_gt
(
.prmry_in (gt_rst_r),
.scndry_aclk (USER_CLK),
.scndry_out (gt_rst_sync)
);
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK )
if(gt_rst_sync)
reset_debounce_r <= 4'b1111;
else
reset_debounce_r <= {RESET,reset_debounce_r[0:2]};
always @ (posedge USER_CLK)
SYSTEM_RESET <= &reset_debounce_r;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge INIT_CLK)
debounce_gt_rst_r <= {GT_RESET_IN,debounce_gt_rst_r[0:2]};
always @(posedge INIT_CLK)
gt_rst_r <= `DLY &debounce_gt_rst_r;
// Delay RESET assertion to GT.This will ensure all logic is reset first before GT is reset
always @ (posedge INIT_CLK)
begin
dly_gt_rst_r <= `DLY {dly_gt_rst_r[18:0],gt_rst_r};
end
assign GT_RESET_OUT = dly_gt_rst_r[18];
endmodule
| 7.200193 |
module aurora_64b66b_v7_3_DESCRAMBLER_64B66B #
(
parameter RX_DATA_WIDTH = 32
)
(
// User Interface
SCRAMBLED_DATA_IN,
UNSCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
ENABLE,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
input [0:(RX_DATA_WIDTH-1)] SCRAMBLED_DATA_IN;
input DATA_VALID_IN;
output [(RX_DATA_WIDTH-1):0] UNSCRAMBLED_DATA_OUT;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
input ENABLE;
//***************************Internal Register Declarations********************
reg [57:0] descrambler;
integer i;
reg [57:0] poly;
reg [0:(RX_DATA_WIDTH-1)] tempData;
reg [(RX_DATA_WIDTH-1):0] unscrambled_data_i;
reg xorBit;
//*********************************Main Body of Code***************************
always @(descrambler,SCRAMBLED_DATA_IN)
begin
poly = descrambler;
for (i=0;i<=(RX_DATA_WIDTH-1);i=i+1)
begin
xorBit = SCRAMBLED_DATA_IN[i] ^ poly[38] ^ poly[57];
poly = {poly[56:0],SCRAMBLED_DATA_IN[i]};
tempData[i] = xorBit;
end
end
always @(posedge USER_CLK)
begin
if (SYSTEM_RESET)
begin
unscrambled_data_i <= `DLY 'h0;
descrambler <= `DLY 58'h155_5555_5555_5555;
end
else if (DATA_VALID_IN && ENABLE)
begin
unscrambled_data_i <= `DLY tempData;
descrambler <= `DLY poly;
end
end
//________________ Scrambled Data assignment to output port _______________
assign UNSCRAMBLED_DATA_OUT = unscrambled_data_i;
endmodule
| 7.200193 |
module aurora_64b66b_v7_3_SCRAMBLER_64B66B #
(
parameter TX_DATA_WIDTH = 32
)
(
// User Interface
UNSCRAMBLED_DATA_IN,
SCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
input [0:(TX_DATA_WIDTH-1)] UNSCRAMBLED_DATA_IN;
input DATA_VALID_IN;
output [(TX_DATA_WIDTH-1):0] SCRAMBLED_DATA_OUT;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************Internal Register Declarations********************
integer i;
reg [57:0] poly;
reg [57:0] scrambler;
reg [0:(TX_DATA_WIDTH-1)] tempData;
reg xorBit;
reg [(TX_DATA_WIDTH-1):0] SCRAMBLED_DATA_OUT;
//*********************************Main Body of Code***************************
always @(scrambler,UNSCRAMBLED_DATA_IN)
begin
poly = scrambler;
for (i=0;i<=(TX_DATA_WIDTH-1);i=i+1)
begin
xorBit = UNSCRAMBLED_DATA_IN[i] ^ poly[38] ^ poly[57];
poly = {poly[56:0],xorBit};
tempData[i] = xorBit;
end
end
always @(posedge USER_CLK)
begin
if (SYSTEM_RESET)
begin
SCRAMBLED_DATA_OUT <= `DLY 'h0;
scrambler <= `DLY 58'h155_5555_5555_5555;
end
else if (DATA_VALID_IN)
begin
SCRAMBLED_DATA_OUT <= `DLY tempData;
scrambler <= `DLY poly;
end
end
endmodule
| 7.200193 |
module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 64 bit clock from Aurora to 32/16 bit GTX. Width conversion is
// also required since the width of the Aurora interface is 8 bytes
// but the Rainier gtx does not have an 8byte interface.
//
/////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_GTX_WIDTH_AND_CLK_CONV_TX #
(
parameter INPUT_WIDTH=8,
parameter OUTPUT_WIDTH=4
)
(
//Output to the GTX interface
DATA_TO_GTX,
//Input from the Aurora
DATA_FROM_AURORA,
// Sync header from Aurora Interface
TX_HEADER_IN,
// Sync header to GTX
TX_HEADER_OUT,
//Clock and reset
CLK_GTX,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
input RESET;
input CLK_GTX;
input [INPUT_WIDTH*8-1:0] DATA_FROM_AURORA;
output [OUTPUT_WIDTH*8-1:0] DATA_TO_GTX;
output [1:0] TX_HEADER_OUT;
//*****************************GTX Interface**************************
input [1:0] TX_HEADER_IN;
//*****************************Internal Register Declarations**************************
reg [OUTPUT_WIDTH*8-1:0] DATA_TO_GTX;
reg [1:0] TX_HEADER_OUT;
//*****************************Internal Register Declarations**************************
reg sel_mux;
//*****************************Wire Declarations**************************
wire [31:0] data_to_aurora_c;
//*****************************Beginning of Code *************************
always @(posedge CLK_GTX)
begin
if(RESET)
sel_mux <= `DLY 1'b1;
else if(sel_mux==1'b1)
sel_mux <= `DLY sel_mux +1;
else
sel_mux <= `DLY 1'b1;
end
//Split data into 32 bit blocks, required for 32 bit GTX interface
assign data_to_aurora_c = (sel_mux)?DATA_FROM_AURORA[63:32]:DATA_FROM_AURORA[31:0];
//Assign output
always @(posedge CLK_GTX)
begin
if(RESET)
DATA_TO_GTX <= `DLY 32'b0;
else
DATA_TO_GTX <= `DLY data_to_aurora_c;
end
always @(posedge CLK_GTX)
begin
if(RESET)
TX_HEADER_OUT <= `DLY 2'b0;
else
TX_HEADER_OUT <= `DLY TX_HEADER_IN;
end
endmodule
| 6.595174 |
module aurora_64b66b_v7_3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == ({STRB_WIDTH{1'b1}})) ? ({REM_WIDTH{1'b0}}) : (AXI4_S_IP_TX_TKEEP[0] + AXI4_S_IP_TX_TKEEP[1] + AXI4_S_IP_TX_TKEEP[2] + AXI4_S_IP_TX_TKEEP[3] + AXI4_S_IP_TX_TKEEP[4] + AXI4_S_IP_TX_TKEEP[5] + AXI4_S_IP_TX_TKEEP[6] + AXI4_S_IP_TX_TKEEP[7] + AXI4_S_IP_TX_TKEEP[8] + AXI4_S_IP_TX_TKEEP[9] + AXI4_S_IP_TX_TKEEP[10] + AXI4_S_IP_TX_TKEEP[11] + AXI4_S_IP_TX_TKEEP[12] + AXI4_S_IP_TX_TKEEP[13] + AXI4_S_IP_TX_TKEEP[14] + AXI4_S_IP_TX_TKEEP[15]);
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(!CHANNEL_UP)
new_pkt_r <= `DLY 1'b0;
else
new_pkt_r <= `DLY new_pkt;
end
endmodule
| 7.200193 |
module aurora_64b66b_v7_3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire we,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else if(we)
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 7.200193 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module aurora_64b66b_v7_3_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] HARD_ERR;
input [0:1] LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//*********************************Wire Declarations**********************************
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
assign channel_hard_err_c = |HARD_ERR ;
always @(posedge USER_CLK)
begin
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
end
assign reset_channel_c = !(&(LANE_UP)) ;
always @(posedge USER_CLK)
begin
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
end
endmodule
| 7.591032 |
module aurora_64b66b_v7_3_clock_enable_generator
(
// User IO
RESET,
USER_CLK,
ENABLE_32,
ENABLE_64
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
output ENABLE_64;
output ENABLE_32;
//**************************External Register Declarations****************************
reg ENABLE_64;
reg ENABLE_32;
//**************************Internal Register Declarations****************************
reg [1:0] count;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK,negedge RESET)
if(!RESET)
count <= `DLY 2'b00;
else
count <= `DLY count +1'b1;
always @ (posedge USER_CLK)
if(!RESET)
ENABLE_32 <= `DLY 1'b0;
else if(count == 2'b00 || count == 2'b10)
ENABLE_32 <= `DLY 1'b1;
else
ENABLE_32 <= `DLY 1'b0;
always @ (posedge USER_CLK)
if(!RESET)
ENABLE_64 <= `DLY 1'b0;
else if(count == 2'b00)
ENABLE_64 <= `DLY 1'b1;
else
ENABLE_64 <= `DLY 1'b0;
endmodule
| 7.200193 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.