code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_v5_2_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_TX_LL
(... | 6.878357 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
... | 6.806955 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, th... | 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the p... | 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_v5_3_hotplug
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output [1:0] LINK_RESET_OUT,
// System Interface
input USER_CLK
);
`define DLY #1
//***************************** Wire D... | 8.673171 |
module aurora_8b10b_v5_3_hotplug
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output [1:0] LINK_RESET_OUT,
// System Interface
input USER_CLK
);
`define DLY #1
//***************************** Wire D... | 8.673171 |
module aurora_8b10b_v5_3_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
// INIT_CLK_P,
// INIT_CLK_N,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations******************... | 8.673171 |
module aurora_8b10b_v8_3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREA... | 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//***********************... | 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`ti... | 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Auro... | 8.183782 |
module aurora_8b10b_v8_3_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input ... | 8.673171 |
module aurora_8b10b_v8_3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
... | 8.673171 |
module aurora_8b10b_v8_3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_I... | 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_TX_LL
(... | 6.878357 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module Aurora_clk_gen_top (
// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED,
output WB_CLK_SLAVE,
output WB_RST,
output WB_CLK_MASTER,
output WB_CLK_DIVIDE,
output WB_RST_... | 7.129938 |
module Aurora_FPGA_clock ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED,
output CLK_IN_BUF
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(... | 6.845304 |
module Aurora_FPGA_clock_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,... | 6.845304 |
module Aurora_FPGA_clock_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time P... | 6.845304 |
module Aurora_FPGA_ctrl (
input user_clk,
input pll_not_locked, //will reset channel
//
input rst, //clear fifo and logic, will reset channel
input rx_fifo_rst,
//
input channel_rdy,
//rd fifo interface
input [31:0] fifo_dat_i,
input fifo_empty_i,
output fifo_rd_o,
//w... | 6.845304 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, th... | 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. The data it generates on each ... | 7.0217 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset... | 7.591032 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_framing_GLOBAL_LOGIC
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora... | 8.183782 |
module aurora_framing_PHASE_ALIGN (
//Aurora Lane Interface
ENA_COMMA_ALIGN,
//MGT Interface
RX_REC_CLK,
ENA_CALIGN_REC
);
`define DLY #1
//***********************************Port Declarations*******************************
//synthesis attribute keep_hierarchy PHASE_ALIGN true;
//Auro... | 7.795455 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_GLOBAL_LOGIC
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Int... | 8.183782 |
module AURORA_IP_TOP (
//Global
input RESET,
// Status
output CHANNEL_UP,
// System Interface
input System_CLK_P,
input System_CLK_N,
// GT Reference Clock Interface
input GT_REF_CLK_P,
input GT_REF_CLK_N,
//TX Interface
input [0:63] txdata_i,
input txdat... | 6.511769 |
module aurora_phy_clk_gen (
input areset,
input refclk_p,
input refclk_n,
output refclk,
output clk156,
output init_clk
);
wire clk156_buf;
wire init_clk_buf;
wire clkfbout;
IBUFDS_GTE2 ibufds_inst (
.O (refclk),
.ODIV2(),
.CEB (1'b0),
.I (refclk_p),
... | 6.505467 |
module AusdioTut (
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
////////... | 7.187105 |
module Auto2 (
clock0,
clock180,
reset,
leds,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock0;
input wire clock180;
input wire reset;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output w... | 7.272661 |
module Auto2FPGA (
clock,
reset,
leds,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock;
input wire reset;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire cm_locked;
wir... | 7.284943 |
module autoanim_sync (
input CLK,
input RASTER8,
input RESETP,
input [7:0] AA_SPEED,
output [2:0] AA_COUNT
);
wire [3:0] D151_Q;
//wire B91_CO;
//wire E117_CO;
//wire E95A_OUT = ~|{E117_CO, 1'b0}; // Used for test mode
//wire E149_OUT = ~^{CLK, 1'b0}; // Used for test mode
// Timer... | 7.003183 |
module AutoBoot (
input wire clk,
input wire rstn,
input wire [15:0] TokenReady_i,
output wire [15:0] TokenValid_o,
input wire TokenXReady_i,
output wire TokenXValid_o,
output wire [3:0] ID_o
);
localparam IDLE = 2'b00;
localparam XADC = 2'b01;
localparam LOGI = 2'b10;
reg [1:... | 8.050907 |
module autoconfig #(
parameter INTERLEAVED = 0,
parameter ENABLE = 0
) (
input clk,
input rst,
output busy,
output [15:0] config_data,
output [ 3:0] config_addr,
output config_start,
input config_done
);
localparam STATE_IDLE = 0;
localparam STATE_BUS... | 7.807376 |
module autoconfig (
input RESET,
input AS20,
input RW20,
input DS20,
input [31:0] A,
input [15:0] D,
output [ 7:4] DOUT,
output ACCESS,
output [1:0] DECODE
);
localparam RAM_CARD = 0;
localparam SPI_CARD = 1;
localparam CONFIGURING_RAM = 2'b00;
localparam CONFIGURING_... | 7.404861 |
module: Autocorr_Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Autocorr_test;
`include "paramList.v"
// Inputs
reg clk;
reg reset;
reg start;
reg [7:0] xMemAddr;
reg [31:... | 7.074428 |
module Autofire #(
parameter FREQ = 37_800_000,
parameter FIRERATE = 10
) (
input clk,
input resetn,
input btn,
input reg out
);
localparam DELAY = FREQ / FIRERATE / 2;
reg [$clog2(DELAY)-1:0] timer;
always @(posedge clk) begin
if (~resetn) begin
timer <= 0;
out <= 0;
... | 7.186073 |
module AutoIncOutput (
input reset_n,
clk,
input OUT1n,
BD3,
input [2:0] BA,
output BUF1BUF2n,
STARTLED1,
output SIREn,
PLAYER2,
output YINCn,
XINCn,
output AYn,
AXn
);
reg [7:0] q;
always @(posedge clk or negedge reset_n) //ic6P
begin
if (~reset_n) ... | 6.641314 |
module AutoIncrement (
input clk,
reset_n,
ce2H,
input [15:0] BA,
input [7:0] BD,
input BITMDn,
input XCOORDn,
XINCn,
AXn,
input YCOORDn,
YINCn,
AYn,
output [14:0] DRBA,
output PIXA
);
assign DRBA = ~BITMDn ? {yCoord, xCoord[7:1]} : BA[14:0];
reg [7:0] xCo... | 6.677897 |
module AutoLock (
input wire clk,
input wire update,
input wire [15:0] errorsig,
input wire signed [15:0] discriminator,
input wire signed [15:0] threshold,
input wire enable,
output reg enable_lock_out = 0,
output reg scanEnable = 0,
input wire [31:0] timeout
);
reg [3:0] state ... | 6.9465 |
module AutoLock_tb;
wire clk;
clock_gen #(20) mclk (clk);
// Inputs
reg update;
reg [15:0] errorsig;
reg [15:0] discriminator;
reg [15:0] threshold;
reg enable;
reg [31:0] pCoeff;
reg [31:0] iCoeff;
reg [15:0] input_offset0;
reg lock_enable;
reg [15:0] scan_increment_0, scan_min_0, scan_max_0... | 6.827295 |
module automated_fsm (
reset_n,
clock,
direction,
stop,
begin_signal,
sync_counter,
out_x,
out_y,
out_color
);
input reset_n, clock, stop, begin_signal, sync_counter;
input [1:0] direction;
output reg [7:0] out_x;
output reg [6:0] out_y;
output reg [2:0] out_color;
reg [... | 7.348733 |
module
*/
module AutomaticGainControl(
clk,
din, din_valid,
dout, dout_valid,
agc_gain
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
localparam DATA_WIDTH = 32; //Width of one integer being summed
param... | 7.373501 |
module automatic_washing_machine (
clk,
reset,
door_close,
start,
filled,
detergent_added,
cycle_timeout,
drained,
spin_timeout,
door_lock,
motor_on,
fill_value_on,
drain_value_on,
done,
soap_wash,
water_wash
);
input clk, reset, door_close, start, fill... | 6.788539 |
module automaton (
clk,
rst_n,
over,
start_sig,
gameready_sig,
over_sig
);
input clk;
input rst_n;
input over;
output start_sig;
output gameready_sig;
output over_sig;
/**************************************************/
parameter ready = 3'b001, game = 3'b010, game_over = 3'b1... | 7.074838 |
module automaton_tb ();
parameter WIDTH = 80;
reg [7:0] count = 0;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del componente
wire [WIDTH-1:0] data;
//-- Instanciar el componente (N=1 aqui, segundos)
automaton #(
.WIDTH(WIDTH)
) myCA (
.clk (clk),
... | 6.615668 |
module topControl (
input CLOCK_50,
input [3:0] KEY,
output [9:0] LEDR,
output VGA_CLK,
output VGA_HS,
output VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
localparam DELAY = 5000000;
reg [ 8:0] xoffsetset;... | 8.29194 |
module autoPNGVGA (
input CLOCK_50,
input [8:0] xoffsetset,
input [7:0] yoffsetset,
input [3:0] KEY,
output VGA_CLK,
output VGA_HS,
output VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
reg [16:0] address;... | 6.72565 |
module for sdram to keep the data in capacitors
for every 64ms all units need to be refreshed. (15us between each refreshing process)
*/
module autorefresh (
//system input signals
input sys_clk,
input sys_rst,
//communication with top level entity (arbit)
... | 7.11804 |
module autoref_config (
input clk,
input rst,
input set_interval,
input [27:0] interval_in,
input set_trfc,
input [27:0] trfc_in,
output reg aref_en,
output reg [27:0] aref_interval,
output reg [27:0] trfc
);
always @(posedge clk) begin
if (rst) begin
aref_en <= 0;
... | 6.508465 |
module implements the autorepeat function with 500ms initial time to start the repeat
function and 300ms repeat interval. Time is counted in units of the period of clken100hz
signal.
------------------------------------------------------------
Revision history:
- Dec 21, 2005 - First release, jca (jc... | 7.842559 |
module auto_add_tb ();
reg clk, rst, start;
wire DONE;
wire [31:0] sum_out;
auto_add dut (
clk,
rst,
start,
DONE,
sum_out
);
initial clk = 0;
always #10 clk = ~clk;
initial begin
rst <= 1;
start <= 0;
#15 rst <= 0;
#5 start <= 1;
#105 start <= 0;
... | 6.508501 |
module Auto_Cal #(
parameter DATA_WIDTH = 8
) (
start,
rst,
clk,
done,
sum_out
);
input start;
input rst;
input clk;
output wire done;
output wire [DATA_WIDTH-1:0] sum_out;
wire NEXT_ZERO, LD_SUM, LD_NEXT, SUM_SEL, NEXT_SEL, A_SEL;
FSM control (
clk,
rst,
start,... | 7.196357 |
module Auto_Cal_tb ();
parameter DATA_WIDTH = 32;
reg start;
reg rst;
reg clk;
wire done;
wire [DATA_WIDTH-1:0] sum_out;
initial begin
start = 0;
rst = 0;
clk = 0;
end
always begin
#10 clk = ~clk;
end
always begin
#100 start = 1;
#400 start = 0;
end
Auto_Cal #(D... | 6.786519 |
module auto_low_freq_counter (
input wire clk,
reset,
input wire start,
si,
output wire [3:0] bcd3,
bcd2,
bcd1,
bcd0,
output wire [1:0] decimal_counter
);
// symbolic state declaration
localparam [2:0] idle = 3'b000, count = 3'b001, frq = 3'b010, b2b = 3'b011, adj ... | 8.320934 |
module auto_low_freq_counter_tb;
// signal declaration
localparam T = 10; // clk period
reg clk, reset;
reg start;
reg si1, si2, si3; // test signals
reg [1:0] sel;
localparam cnt1 = 11_000;
localparam cnt2 = 300_000;
localparam cnt3 = 17_000_000;
wire si;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
w... | 8.320934 |
module auto_low_freq_counter_test (
input wire clk,
reset,
input wire btn,
input wire [2:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire start;
reg si;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
wire [1:0] decimal_counter;
reg [3:0] dp_in;
... | 8.320934 |
module auto_range (
input clk,
input rst,
input ready,
input max_result_valid,
input [ 4:0] vga_in,
input [15:0] auto_upper,
input [15:0] auto_lower,
input [15:0] signal_max_a,
input [15:0] signal_max_b,
input [15:0] signal_max_c,
input [15:0] signal_max_d,
output reg [... | 7.572046 |
module top (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/ir.py:329" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "a... | 6.782499 |
module auto_tb ();
reg clk = 0;
reg [15:0] a_operand;
reg [15:0] b_operand;
wire Exception, Overflow, Underflow;
wire [15:0] result;
reg [15:0] Expected_result;
reg [95:0] testVector[`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;... | 6.595049 |
module Auto_Write_Read #(
parameter WR_RD_DATA = 'd256
) (
input clk, //
input rst_n,
//wfifo signal
input wfifo_wclk,
input wfifo_wr_en,
input [15:0] wfifo_wr_data,
input wfifo_rclk,
input wfifo_... | 6.76176 |
module auxControl (
input [2:0] branch,
input [1:0] jump,
input zero,
input sgn,
input [31:0] pcimm,
input [31:0] aluc,
output reg npc_op,
output reg [31:0] npc_bj
);
always @(*) begin
if (jump[0] == 1'b1) npc_op = 1'b1; // jal or jalr
else if (branch[0] == 1'b1) begin
... | 7.400879 |
module AuxCounter (
clk,
rst_n,
en,
ld,
val,
cnt
);
parameter CntBit = 32;
input clk;
input rst_n;
input en;
input ld;
input [CntBit - 1:0] val;
output reg [CntBit - 1:0] cnt;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) cnt <= 'd0;
else if (ld) cnt <= val;
... | 6.633945 |
module auxdec (
input wire [1:0] alu_op,
input wire [5:0] funct,
output wire [3:0] alu_ctrl,
output wire [1:0] hilo_mux_ctrl,
output wire hilo_we,
output wire jr_mux_ctrl
);
reg [7:0] ctrl;
assign {alu_ctrl, hilo_mux_ctrl, hilo_we, jr_mux_ctrl} = ctrl;
always @(alu_op, funct) begin
... | 6.543732 |
module auxiliary_arc (
input clk,
input rst,
input rst_n,
output [`RV_BIT_NUM_DIVIV_NUM-1:0] aux_mem_keep,
output [`RV_BIT_NUM-1:0] aux_mem_datai,
output [`RV_BIT_NUM-1:0] aux_mem_addr,
input [`RV_BIT_NUM-1:0] aux_mem_datao,
input [`RV_BIT_NUM-1:0] aux_start_addr,
input aux_en,
... | 6.772793 |
module to handle delay of signals by a certain number of cycles
// LOG should be log2(CYCLES) rounded up
module pipeliner #(parameter CYCLES=1, parameter LOG=1, parameter WIDTH = 1)
(input reset,
input clock,
input [WIDTH-1:0] in,
output reg [WIDTH... | 6.570521 |
module binary_to_bcd #(
parameter LOG = 3,
WIDTH = 8,
WAIT = 0,
CALC = 1,
SHIFT = 0,
ADD = 1
) (
input [WIDTH-1:0] bin,
input clock,
output reg [4*LOG-1:0] out = 0
);
reg count = 0;
reg [WIDTH+4*LOG-1:0] calc = 0;
reg state = WAIT;
reg int_state = SHIFT;
integer i = 0;
wi... | 8.011872 |
module pulse (
input clock,
signal,
output reg out
);
reg state = 0;
always @(posedge clock) begin
state <= signal;
if (out) out <= 0;
else out <= signal & ~state;
end
endmodule
| 6.570181 |
module pulse2 (
input clock,
signal,
output reg out
);
reg state = 0;
reg count = 0;
always @(posedge clock) begin
state <= signal;
if (out) begin
if (count == 0) begin
count <= count + 1;
end else begin
out <= 0;
count <= 0;
end
end else out <=... | 6.524618 |
module auxillary_memory (
clk,
rst,
cmd_in,
addr_in,
data_in,
data_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter dw = `DATA_WIDTH;
parameter aw = `ADDR_WIDTH;
parameter sw = `SCAN_WI... | 8.106877 |
modules here...
// DeBounce_v.v
//////////////////////// Button Debounceer ///////////////////////////////////////
//***********************************************************************
// FileName: DeBounce_v.v
// FPGA: MachXO2 7000HE
// IDE: Diamond 2.0.1
//
// HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCL... | 8.990348 |
module SSeg (
input [3:0] bin,
input neg,
input enable,
output reg [6:0] segs
);
always @(*)
if (enable) begin
if (neg) segs = 7'b011_1111;
else begin
case (bin)
0: segs = 7'b100_0000;
1: segs = 7'b111_1001;
2: segs = 7'b010_0100;
3: ... | 7.166491 |
module Disp2cNum (
input signed [7:0] x,
input enable,
output [6:0] H3,
H2,
H1,
H0 /*, output [7:0] xo0_check,xo1_check,xo2_check,xo3_check*/
);
wire neg = (x < 0);
wire [7:0] ux = neg ? -x : x;
wire [7:0] xo0, xo1, xo2, xo3;
wire eno0, eno1, eno2, eno3;
DispDec h0 (
ux,
... | 7.668752 |
module DispDec (
input [7:0] x,
input neg,
enable,
output reg [7:0] xo,
output reg eno,
output [6:0] segs
);
wire [3:0] digit;
wire n = (x == 1'b0 && neg == 1'b1) ? neg : 1'b0;
assign digit = x % 4'd10;
SSeg converter (
digit,
n,
enable,
segs
);
always @(x) b... | 7.957199 |
module DispHex (
input [7:0] value,
output [6:0] display0,
display1
);
SSeg sseg0 (
value[7:4],
0,
1,
display0
);
SSeg sseg1 (
value[3:0],
0,
1,
display1
);
endmodule
| 6.832901 |
module AUX_Run ();
integer i;
integer fd;
reg [7:0] a;
reg [14:0] b;
reg [23:0] addr;
always #1 a = a + 1;
always #1 b = b + 1;
always #1 addr = addr + 1;
wire [31:0] aout;
wire [31:0] bout;
AUX aux (
.AUX_A(a),
.AUX_B(b),
.AOut (aout),
.BOut (bout)
);
AUX_Dumper ... | 7.123427 |
module au_top (
input clk, // 100MHz clock
input rst_n, // reset button (active low)
output [ 7:0] led, // 8 user controllable LEDs
input usb_rx, // USB->Serial input
output usb_tx, // USB->Serial output,
input [ 4:0] io_button,
inpu... | 7.049401 |
module inicial01 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] d
);
wire [3:0] na, nb, w0, w1;
// descrever por portas
not not1[3:0] (na, a);
not not2[3:0] (nb, b);
and and1[3:0] (w1, nb, d);
or or1[3:0] (w0, na, nb);
or or1[3:0] (saida0, w1, na);
endmodule
| 6.692001 |
module inicial02 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] d
);
wire [3:0] nb;
// descrever por portas
not not1[3:0] (nb, b);
and and1[3:0] (s, a, nb, d);
endmodule
| 6.650573 |
module s0 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d
);
wire [3:0] sinicial01, sinicial02;
// descrever por portas
and and1[3:0] (w1, a, sinicial01, c);
or or1[3:0] (saida0, w1, sinicial02);
endmodule
| 6.510634 |
module avalon2rcn (
input av_clk,
input av_rst,
output av_waitrequest,
input [21:0] av_address,
input av_write,
input av_read,
input [3:0] av_byteenable,
input [31:0] av_writedata,
output [31:0] av_readdata,
output av_readdatavalid,
input [68:0] rcn_in,
output [68:0] r... | 7.394587 |
module avaloncontrol (
clk,
rst_n,
rd_n,
wr_n,
cs_n,
rddata,
wrdata,
addr,
code0,
code1,
code2,
code3,
set,
A,
B,
Z_OpenLoop,
Z_Brushless
);
input clk, rst_n, rd_n, wr_n, cs_n;
input [31:0] code0, code1, code2, code3, wrdata;
input [2:0] addr;
... | 7.86358 |
module avaloncontrol_0 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // ... | 7.86358 |
module avaloncontrol_1 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // ... | 7.86358 |
module avaloncontrol_2 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // ... | 7.86358 |
module avaloncontrol_3 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // ... | 7.86358 |
module avaloncontrol_dribbler (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // ... | 7.86358 |
module avalonif_mmc (
clk,
reset,
chipselect,
address,
read,
readdata,
write,
writedata,
irq,
MMC_nCS,
MMC_SCK,
MMC_SDO,
MMC_SDI,
MMC_CD,
MMC_WP
);
//--- AvalonoXM -----------
input clk;
input reset;
input chipselect;
input [3:2] address;
input re... | 7.306123 |
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