code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_v5_2_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_v5_2_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_v5_2_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_v5_2_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
input INIT_CLK;
(* ASYNC_REG = "TRUE" *)
input GT_RESET_IN;
input TX_LOCK_IN;
input PLL_NOT_LOCKED;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] reset_debounce_r;
reg [0:3] debounce_gt_rst_r;
reg reset_debounce_r2;
reg reset_debounce_r3;
reg reset_debounce_r4;
wire SYSTEM_RESET;
//********************************Wire Declarations**********************************
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b1111;
else reset_debounce_r <= {!RESET, reset_debounce_r[0:2]}; //Note: Using active low reset
always @(posedge USER_CLK) begin
reset_debounce_r2 <= &reset_debounce_r;
reset_debounce_r3 <= reset_debounce_r2 || !TX_LOCK_IN;
reset_debounce_r4 <= reset_debounce_r3;
end
assign SYSTEM_RESET = reset_debounce_r4 || PLL_NOT_LOCKED;
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge INIT_CLK) debounce_gt_rst_r <= {GT_RESET_IN, debounce_gt_rst_r[0:2]};
assign gt_rst_r = &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_2_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_v5_2_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_v5_2_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg [0:1] soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r[0] |
soft_err_r[1];
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports Virtex-5
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_CHBOND_COUNT_DEC_4BYTE (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* keep_hierarchy="true" *)
module aurora_8b10b_v5_3_CLOCK_MODULE #
(
parameter MULT = 8.0,
parameter DIVIDE = 2,
parameter CLK_PERIOD = 5.0,
parameter OUT0_DIVIDE = 8.0,
parameter OUT1_DIVIDE = 4,
parameter OUT2_DIVIDE = 8,
parameter OUT3_DIVIDE = 4
)
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
`define DLY #1
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Wire Declarations**********************************
wire clkfb_w;
wire clkout0_o;
wire clkout1_o;
wire clkout2_o;
wire clkout3_o;
wire locked_w;
//*********************************Main Body of Code**********************************
// Instantiate a MMCM module to divide the reference clock.
MMCM_ADV #
(
.CLKFBOUT_MULT_F (MULT),
.DIVCLK_DIVIDE (DIVIDE),
.CLKFBOUT_PHASE (0),
.CLKIN1_PERIOD (CLK_PERIOD),
.CLKIN2_PERIOD (10),
.CLKOUT0_DIVIDE_F (OUT0_DIVIDE),
.CLKOUT0_PHASE (0),
.CLKOUT1_DIVIDE (OUT1_DIVIDE),
.CLKOUT1_PHASE (0),
.CLKOUT2_DIVIDE (OUT2_DIVIDE),
.CLKOUT2_PHASE (0),
.CLKOUT3_DIVIDE (OUT3_DIVIDE),
.CLKOUT3_PHASE (0),
.CLOCK_HOLD ("TRUE")
)
mmcm_adv_i
(
.CLKIN1 (GT_CLK),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.CLKFBIN (clkfb_w),
.CLKOUT0 (clkout0_o),
.CLKOUT0B (),
.CLKOUT1 (clkout1_o),
.CLKOUT1B (),
.CLKOUT2 (clkout2_o),
.CLKOUT2B (),
.CLKOUT3 (clkout3_o),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKFBOUT (clkfb_w),
.CLKFBOUTB (),
.CLKFBSTOPPED (),
.CLKINSTOPPED (),
.DO (),
.DRDY (),
.DADDR (7'd0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'd0),
.DWE (1'b0),
.LOCKED (locked_w),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.PWRDWN (1'b0),
.RST (!GT_CLK_LOCKED)
);
// The PLL_NOT_LOCKED signal is created by inverting the MMCM's locked signal.
assign PLL_NOT_LOCKED = ~locked_w;
// The User Clock is distributed on a global clock net.
BUFG user_clk_net_i
(
.I(clkout0_o),
.O(USER_CLK)
);
BUFG sync_clk_net_i
(
.I(clkout1_o),
.O(SYNC_CLK)
);
endmodule
| 6.806955 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, the error count is incremented until it
// reaches its max value.
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_v5_3_FRAME_CHECK
(
// User Interface
RX_D,
RX_SRC_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP,
ERR_COUNT
);
//***********************************Port Declarations*******************************
// User Interface
input [0:15] RX_D;
input RX_SRC_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
output [0:7] ERR_COUNT;
//***************************Internal Register Declarations***************************
reg [0:8] err_count_r;
// RX Data registers
reg [0:15] data_lfsr_r;
//*********************************Wire Declarations**********************************
wire reset_c;
wire [0:15] data_lfsr_concat_w;
wire data_valid_c;
wire data_err_detected_c;
reg data_err_detected_r;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Capture incoming data ___________________________
//Data is valid when RX_SRC_RDY_N is asserted
assign data_valid_c = !RX_SRC_RDY_N;
//generate expected RX_D using LFSR
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hD5E6; //random seed value
end
else if(data_valid_c)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
end
assign data_lfsr_concat_w = {1{data_lfsr_r}};
//___________________________ Check incoming data for errors __________________________
//An error is detected when LFSR generated RX data from the data_lfsr_concat_w register,
//does not match valid data from the RX_D port
assign data_err_detected_c = (data_valid_c && (RX_D != data_lfsr_concat_w));
//We register the data_err_detected_c signal for use with the error counter logic
always @(posedge USER_CLK)
data_err_detected_r <= `DLY data_err_detected_c;
//Compare the incoming data with calculated expected data.
//Increment the ERROR COUNTER if mismatch occurs.
//Stop the ERROR COUNTER once it reaches its max value (i.e. 255)
always @(posedge USER_CLK)
if(reset_c)
err_count_r <= `DLY 9'd0;
else if(&err_count_r)
err_count_r <= `DLY err_count_r;
else if(data_err_detected_r)
err_count_r <= `DLY err_count_r + 1;
//Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
//max value) to the module output
assign ERR_COUNT = err_count_r[1:8];
endmodule
| 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the pseudo-random
// data and lower bits of LFSR are connected to REM bus
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_8b10b_v5_3_FRAME_GEN
(
// User Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
//*****************************Parameter Declarations****************************
//***********************************Port Declarations*******************************
// User Interface
output [0:15] TX_D;
output TX_SRC_RDY_N;
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
//***************************External Register Declarations***************************
reg TX_SRC_RDY_N;
//***************************Internal Register Declarations***************************
reg [0:15] data_lfsr_r;
wire reset_c;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Transmit Data __________________________________
//Transmit data when TX_DST_RDY_N is asserted.
//Random data is generated using XNOR feedback LFSR
//TX_SRC_RDY_N is asserted on every cycle with data
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hABCD; //random seed value
TX_SRC_RDY_N <= `DLY 1'b1;
end
else if(!TX_DST_RDY_N)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
TX_SRC_RDY_N <= `DLY 1'b0;
end
//Connect TX_D to the DATA LFSR register
assign TX_D = {1{data_lfsr_r}};
endmodule
| 7.0217 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_v5_3_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_v5_3_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_v5_3_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v5_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:1] SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output GEN_A;
output [0:3] GEN_K;
output [0:3] GEN_R;
output [0:3] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_v5_3_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_v5_3_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_v5_3_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_v5_3_hotplug
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output [1:0] LINK_RESET_OUT,
// System Interface
input USER_CLK
);
`define DLY #1
//***************************** Wire Declarations *****************************
reg link_reset_0;
reg link_reset_1;
//***************************** Reg Declarations *****************************
reg [13:0] count_for_reset_r;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 14'd0;
// Reset link if CC is not detected after 5000 clk cycles
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time. link_reset_0 is used to reset the GT & link_reset_1 is used
// to reset the Aurora lanes inorder to reinitialize the lanes
always @(posedge USER_CLK)
begin
if(RX_CC || RX_SP || RX_SPA)
count_for_reset_r <= `DLY 14'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
always @(posedge USER_CLK)
begin
link_reset_0 <=( (count_for_reset_r > 14'd5100) && (count_for_reset_r < 14'd10200) ) ? 1'b1 : 1'b0;
link_reset_1 <=( (count_for_reset_r > 14'd5100) && (count_for_reset_r < 14'd16300) ) ? 1'b1 : 1'b0;
end
// assign link_reset_0 =( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd10200) ) ? 1'b1 : 1'b0;
// assign link_reset_1 =( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd16300) ) ? 1'b1 : 1'b0;
assign LINK_RESET_OUT = {link_reset_1,link_reset_0};
endmodule
| 8.673171 |
module aurora_8b10b_v5_3_hotplug
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output [1:0] LINK_RESET_OUT,
// System Interface
input USER_CLK
);
`define DLY #1
//***************************** Wire Declarations *****************************
reg link_reset_0;
reg link_reset_1;
//***************************** Reg Declarations *****************************
reg [12:0] count_for_reset_r;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 13'd0;
// Reset link if CC is not detected after 3000 clk cycles
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time. link_reset_0 is used to reset the GT & link_reset_1 is used
// to reset the Aurora lanes inorder to reinitialize the lanes
always @(posedge USER_CLK)
begin
if(RX_CC || RX_SP || RX_SPA)
count_for_reset_r <= `DLY 13'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
always @(posedge USER_CLK)
begin
link_reset_0 <= ( (count_for_reset_r > 13'd3100) & (count_for_reset_r < 13'd6200) ) ? 1'b1 : 1'b0;
link_reset_1 <= ( (count_for_reset_r > 13'd3100) & (count_for_reset_r < 13'd8100) ) ? 1'b1 : 1'b0;
end
assign LINK_RESET_OUT = {link_reset_1,link_reset_0};
endmodule
| 8.673171 |
module aurora_8b10b_v5_3_RESET_LOGIC (
// User IO
RESET,
USER_CLK,
// INIT_CLK_P,
// INIT_CLK_N,
INIT_CLK,
GT_RESET_IN,
TX_LOCK_IN,
PLL_NOT_LOCKED,
SYSTEM_RESET,
GT_RESET_OUT
);
`define DLY #1
//***********************************Port Declarations*******************************
// User I/O
input RESET;
input USER_CLK;
// input INIT_CLK_P;
// input INIT_CLK_N;
input INIT_CLK;
input GT_RESET_IN;
input TX_LOCK_IN;
input PLL_NOT_LOCKED;
output SYSTEM_RESET;
output GT_RESET_OUT;
//**************************Internal Register Declarations****************************
reg [0:3] debounce_gt_rst_r;
reg [0:3] reset_debounce_r;
reg reset_debounce_r2;
reg reset_debounce_r3;
reg reset_debounce_r4;
wire SYSTEM_RESET;
//********************************Wire Declarations**********************************
wire init_clk_i;
wire gt_rst_r;
//*********************************Main Body of Code**********************************
//_________________Debounce the Reset and PMA init signal___________________________
// Simple Debouncer for Reset button. The debouncer has an
// asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
// that unknown values are not driven into the reset line
always @(posedge USER_CLK or posedge gt_rst_r)
if (gt_rst_r) reset_debounce_r <= 4'b1111;
else reset_debounce_r <= {!RESET, reset_debounce_r[0:2]}; //Note: Using active low reset
always @(posedge USER_CLK) begin
reset_debounce_r2 <= &reset_debounce_r;
reset_debounce_r3 <= reset_debounce_r2 || !TX_LOCK_IN;
reset_debounce_r4 <= reset_debounce_r3;
end
assign SYSTEM_RESET = reset_debounce_r4 || PLL_NOT_LOCKED;
// Assign an IBUFDS to INIT_CLK
assign init_clk_i = INIT_CLK;
/*
IBUFDS init_clk_ibufg_i
(
.I(INIT_CLK_P),
.IB(INIT_CLK_N),
.O(init_clk_i)
);
*/
// Debounce the GT_RESET_IN signal using the INIT_CLK
always @(posedge init_clk_i) debounce_gt_rst_r <= {GT_RESET_IN, debounce_gt_rst_r[0:2]};
assign gt_rst_r = &debounce_gt_rst_r;
assign GT_RESET_OUT = gt_rst_r;
endmodule
| 8.673171 |
module aurora_8b10b_v8_3_AXI_TO_LL #
(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter REM_WIDTH = 1 // REM bus width
)
(
// AXI4-S input signals
AXI4_S_IP_TX_TVALID,
AXI4_S_IP_TX_TREADY,
AXI4_S_IP_TX_TDATA,
AXI4_S_IP_TX_TKEEP,
AXI4_S_IP_TX_TLAST,
// LocalLink output Interface
LL_OP_DATA,
LL_OP_SOF_N,
LL_OP_EOF_N,
LL_OP_REM,
LL_OP_SRC_RDY_N,
LL_IP_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream Interface
input [0:(DATA_WIDTH-1)] AXI4_S_IP_TX_TDATA;
input [0:(STRB_WIDTH-1)] AXI4_S_IP_TX_TKEEP;
input AXI4_S_IP_TX_TVALID;
input AXI4_S_IP_TX_TLAST;
output AXI4_S_IP_TX_TREADY;
// LocalLink TX Interface
output [0:(DATA_WIDTH-1)] LL_OP_DATA;
output [0:(REM_WIDTH-1)] LL_OP_REM;
output LL_OP_SRC_RDY_N;
output LL_OP_SOF_N;
output LL_OP_EOF_N;
input LL_IP_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
reg new_pkt_r;
wire new_pkt;
//*********************************Main Body of Code**********************************
assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;
assign LL_OP_DATA = AXI4_S_IP_TX_TDATA;
assign LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;
assign LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;
assign LL_OP_REM = (AXI4_S_IP_TX_TKEEP == 2'b10) ? 1'b0 : 1'b1;
assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);
assign LL_OP_SOF_N = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));
always @ (posedge USER_CLK)
begin
if(RESET)
new_pkt_r <= `DLY 1'b0;
else if(CHANNEL_UP)
new_pkt_r <= `DLY new_pkt;
else
new_pkt_r <= `DLY 1'b0;
end
endmodule
| 8.673171 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_CHANNEL_ERR_DETECT
(
// Aurora Lane Interface
SOFT_ERR,
HARD_ERR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERR;
input HARD_ERR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERR;
reg CHANNEL_HARD_ERR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_err_r;
reg hard_err_r;
reg lane_up_r;
//*********************************Wire Declarations**********************************
wire channel_soft_err_c;
wire channel_hard_err_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_err_r <= `DLY SOFT_ERR;
hard_err_r <= `DLY HARD_ERR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERR = 1'b1;
assign channel_soft_err_c = soft_err_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERR <= `DLY channel_soft_err_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERR = 1'b1;
assign channel_hard_err_c = hard_err_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERR <= `DLY channel_hard_err_c;
//FF stage added for timing closure
always @ (posedge USER_CLK)
lane_up_r <= `DLY LANE_UP;
// "reset_channel_c" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !lane_up_r;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
| 7.382845 |
module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces fabric clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aurora_8b10b_v8_3,aurora_8b10b_v8_3,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ1,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=1,c_gt_loc_9=X,c_lane_width=2,c_line_rate=62500,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
module aurora_8b10b_v8_3_CLOCK_MODULE
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Main Body of Code**********************************
// Input buffering
//------------------------------------
BUFG user_clk_buf_i
(
.I(GT_CLK),
.O(USER_CLK)
);
assign SYNC_CLK = USER_CLK;
assign PLL_NOT_LOCKED = !GT_CLK_LOCKED;
endmodule
| 6.806955 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERR,
HARD_ERR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERR,
CHANNEL_HARD_ERR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERR;
input LANE_UP;
input HARD_ERR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERR;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_8b10b_v8_3_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_8b10b_v8_3_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_8b10b_v8_3_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.SOFT_ERR(SOFT_ERR),
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERR(CHANNEL_SOFT_ERR),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_8b10b_v8_3_hotplug #
(
parameter ENABLE_HOTPLUG = 1
)
(
// Sym Dec Interface
input RX_CC,
input RX_SP,
input RX_SPA,
// GT Wrapper Interface
output LINK_RESET_OUT,
// System Interface
input INIT_CLK,
input USER_CLK,
input RESET
);
`define DLY #1
//***************************** Reg Declarations *****************************
reg link_reset_0;
reg link_reset_r;
reg [19:0] count_for_reset_r;
wire rx_cc_comb_i;
wire rx_sp_comb_i;
wire rx_spa_comb_i;
//********************************* Main Body of Code**************************
initial
count_for_reset_r = 20'd0;
// Clock domain crossing from USER_CLK to INIT_CLK
aurora_8b10b_v8_3_cir_fifo rx_cc_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_CC),
.rd_clk (INIT_CLK),
.dout (rx_cc_comb_i)
);
aurora_8b10b_v8_3_cir_fifo rx_sp_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SP),
.rd_clk (INIT_CLK),
.dout (rx_sp_comb_i)
);
aurora_8b10b_v8_3_cir_fifo rx_spa_cir_fifo_i
(
.reset (RESET),
.wr_clk (USER_CLK),
.din (RX_SPA),
.rd_clk (INIT_CLK),
.dout (rx_spa_comb_i)
);
// Reset link if CC is not detected after 5000 clk cycles
// Wait for sufficient number of times to allow the link recovery and CC consumption
// This circuit for auto-recovery of the link during hot-plug scenario
// Incoming control characters are decoded to detmine CC reception
// RX_CC, RX_SP, RX_SPA are used as the reset for the count_for_reset_r, which would reset
// the link after the defined time.
// link_reset_0 is used to reset the GT & Aurora core
always @(posedge INIT_CLK)
begin
if(rx_cc_comb_i || rx_sp_comb_i || rx_spa_comb_i)
count_for_reset_r <= `DLY 20'h0;
else
count_for_reset_r <= `DLY count_for_reset_r + 1'b1;
end
// Wait for sufficient time : 2^20 = 1048576
always @(posedge INIT_CLK)
begin
link_reset_0 <= `DLY ( (count_for_reset_r > 20'd1048560) & (count_for_reset_r < 20'd1048570) ) ? 1'b1 : 1'b0;
end
always @(posedge INIT_CLK)
begin
link_reset_r <= `DLY link_reset_0 ;
end
generate
if(ENABLE_HOTPLUG == 1)
begin
assign LINK_RESET_OUT = link_reset_r;
end
else
begin
assign LINK_RESET_OUT = 1'b0;
end
endgenerate
endmodule
| 8.673171 |
module aurora_8b10b_v8_3_cir_fifo (
input wire reset,
input wire wr_clk,
input wire din,
input wire rd_clk,
output reg dout
);
reg [7:0] mem;
reg [2:0] wr_ptr;
reg [2:0] rd_ptr;
always @ ( posedge wr_clk or posedge reset )
begin
if ( reset )
begin
mem <= `DLY 8'b0;
wr_ptr <= `DLY 3'b0;
end
else
begin
mem[wr_ptr] <= `DLY din;
wr_ptr <= `DLY wr_ptr + 1'b1;
end
end
always @ ( posedge rd_clk or posedge reset )
begin
if ( reset )
begin
rd_ptr <= `DLY 3'b100;
dout <= `DLY 1'b0;
end
else
begin
rd_ptr <= `DLY rd_ptr + 1'b1;
dout <= `DLY mem[rd_ptr];
end
end
endmodule
| 8.673171 |
module aurora_8b10b_v8_3_LL_TO_AXI #(
parameter DATA_WIDTH = 16, // DATA bus width
parameter STRB_WIDTH = 2, // STROBE bus width
parameter USE_UFC_REM = 0, // UFC REM bus width identifier
parameter REM_WIDTH = 1 // REM bus width
) (
// LocalLink input Interface
LL_IP_DATA,
LL_IP_SOF_N,
LL_IP_EOF_N,
LL_IP_REM,
LL_IP_SRC_RDY_N,
LL_OP_DST_RDY_N,
// AXI4-S output signals
AXI4_S_OP_TVALID,
AXI4_S_OP_TDATA,
AXI4_S_OP_TKEEP,
AXI4_S_OP_TLAST,
AXI4_S_IP_TREADY
);
`define DLY #1
//***********************************Port Declarations*******************************
// AXI4-Stream TX Interface
output [0:(DATA_WIDTH-1)] AXI4_S_OP_TDATA;
output [0:(STRB_WIDTH-1)] AXI4_S_OP_TKEEP;
output AXI4_S_OP_TVALID;
output AXI4_S_OP_TLAST;
input AXI4_S_IP_TREADY;
// LocalLink TX Interface
input [0:(DATA_WIDTH-1)] LL_IP_DATA;
input [0:(REM_WIDTH-1)] LL_IP_REM;
input LL_IP_SOF_N;
input LL_IP_EOF_N;
input LL_IP_SRC_RDY_N;
output LL_OP_DST_RDY_N;
//*********************************Main Body of Code**********************************
assign AXI4_S_OP_TDATA = LL_IP_DATA;
assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;
assign AXI4_S_OP_TLAST = !LL_IP_EOF_N;
assign AXI4_S_OP_TKEEP = (LL_IP_REM == 1'b1) ? 2'b11 : 2'b10;
assign LL_OP_DST_RDY_N = !AXI4_S_IP_TREADY;
endmodule
| 8.673171 |
module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// It also handles NFC and UFC messages.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_8b10b_v8_3_TX_LL
(
// LocalLink PDU Interface
TX_D,
TX_REM,
TX_SRC_RDY_N,
TX_SOF_N,
TX_EOF_N,
TX_DST_RDY_N,
// Clock Compensation Interface
WARN_CC,
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_REM;
input TX_SRC_RDY_N;
input TX_SOF_N;
input TX_EOF_N;
output TX_DST_RDY_N;
// Clock Compensation Interface
input WARN_CC;
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//*********************************Wire Declarations**********************************
wire halt_c_i;
wire tx_dst_rdy_n_i;
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
assign TX_DST_RDY_N = tx_dst_rdy_n_i;
// TX_LL_Datapath module
aurora_8b10b_v8_3_TX_LL_DATAPATH tx_ll_datapath_i
(
// LocalLink PDU Interface
.TX_D(TX_D),
.TX_REM(TX_REM),
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_8b10b_v8_3_TX_LL_CONTROL tx_ll_control_i
(
// LocalLink PDU Interface
.TX_SRC_RDY_N(TX_SRC_RDY_N),
.TX_SOF_N(TX_SOF_N),
.TX_EOF_N(TX_EOF_N),
.TX_REM(TX_REM),
.TX_DST_RDY_N(tx_dst_rdy_n_i),
// Clock Compensation Interface
.WARN_CC(WARN_CC),
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
.HALT_C(halt_c_i),
// Aurora Lane Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
| 6.878357 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_CHANNEL_ERROR_DETECT
(
// Aurora Lane Interface
SOFT_ERROR,
HARD_ERROR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] SOFT_ERROR;
input HARD_ERROR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERROR;
reg CHANNEL_HARD_ERROR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg [0:1] soft_error_r;
reg hard_error_r;
//*********************************Wire Declarations**********************************
wire channel_soft_error_c;
wire channel_hard_error_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_error_r <= `DLY SOFT_ERROR;
hard_error_r <= `DLY HARD_ERROR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERROR = 1'b1;
assign channel_soft_error_c = soft_error_r[0] |
soft_error_r[1];
always @(posedge USER_CLK)
CHANNEL_SOFT_ERROR <= `DLY channel_soft_error_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERROR = 1'b1;
assign channel_hard_error_c = hard_error_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERROR <= `DLY channel_hard_error_c;
// "reset_channel_r" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !LANE_UP;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module Aurora_clk_gen_top (
// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED,
output WB_CLK_SLAVE,
output WB_RST,
output WB_CLK_MASTER,
output WB_CLK_DIVIDE,
output WB_RST_DELAY
);
wire locked_in;
wire wb_clk_slave_in;
wire wb_clk_master_in;
wire wb_clk_divide_in;
wire wb_reset;
reg wb_reset_delay;
reg [11:0] wb_reset_cnt;
reg [7:0] dcm_rst_cnt;
wire dcm_rst_in;
Aurora_FPGA_clock u_Aurora_FPGA_clock ( // Clock in ports
.CLK_IN1 (CLK_IN1), // IN
// Clock out ports
.CLK_OUT1 (wb_clk_slave_in), // OUT
.CLK_OUT2 (wb_clk_divide_in), // OUT
// Status and control signals
.RESET (dcm_rst_in), // IN
.LOCKED (locked_in),
.CLK_IN_BUF(wb_clk_master_in)
); // OUT
assign LOCKED = locked_in;
assign WB_CLK_SLAVE = wb_clk_slave_in;
assign WB_CLK_MASTER = wb_clk_master_in;
assign wb_reset = RESET | (~locked_in);
assign WB_RST = wb_reset;
assign WB_CLK_DIVIDE = wb_clk_divide_in;
initial begin
dcm_rst_cnt <= 8'b0;
end
always @(posedge wb_clk_master_in) begin
if (RESET) dcm_rst_cnt <= 8'b0;
else if (dcm_rst_cnt[7] == 1'b0) dcm_rst_cnt <= dcm_rst_cnt + 1'b1;
else dcm_rst_cnt <= dcm_rst_cnt;
end
assign dcm_rst_in = (~dcm_rst_cnt[7]);
initial begin
wb_reset_cnt <= 0;
end
always @(posedge wb_clk_slave_in) begin
if (wb_reset) wb_reset_cnt <= 0;
else if (wb_reset_cnt[11] == 1'b0) wb_reset_cnt <= wb_reset_cnt + 1'b1;
else wb_reset_cnt <= wb_reset_cnt;
end
initial begin
wb_reset_delay <= 1'b1;
end
always @(posedge wb_clk_slave_in) begin
if (wb_reset) wb_reset_delay <= 1'b1;
else wb_reset_delay <= (~wb_reset_cnt[11]);
end
assign WB_RST_DELAY = wb_reset_delay;
endmodule
| 7.129938 |
module Aurora_FPGA_clock ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED,
output CLK_IN_BUF
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
assign CLK_IN_BUF = clkin1;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkdv;
DCM_SP #(
.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (15.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm_sp_inst
// Input clock
(
.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180(),
.CLKFX (),
.CLKFX180(),
.CLKDV (clkdv),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC(1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN(1'b0)
);
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1;
BUFG clkout1_buf (
.O(CLK_OUT1),
.I(clk0)
);
BUFG clkout2_buf (
.O(CLK_OUT2),
.I(clkdv)
);
endmodule
| 6.845304 |
module Aurora_FPGA_clock_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 2;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
Aurora_FPGA_clock clknetwork ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1(clk_int[1]),
.CLK_OUT2(clk_int[2]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen]) begin
if (reset_int) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 6.845304 |
module Aurora_FPGA_clock_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 15.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
COUNTER_RESET = 1;
#(PER1 * 20) COUNTER_RESET = 0;
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Aurora_FPGA_clock_exdes #(
.TCQ(TCQ)
) dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
endmodule
| 6.845304 |
module Aurora_FPGA_ctrl (
input user_clk,
input pll_not_locked, //will reset channel
//
input rst, //clear fifo and logic, will reset channel
input rx_fifo_rst,
//
input channel_rdy,
//rd fifo interface
input [31:0] fifo_dat_i,
input fifo_empty_i,
output fifo_rd_o,
//wr fifo interface
output [31:0] fifo_wr_dat_o,
output fifo_wr_o,
input fifo_full_i, //should be connected to almost_full flag
//Aurora transfer interface
output [31:0] tx_data,
output tx_data_src_rdy,
input tx_data_dst_rdy,
input [31:0] rx_data,
input rx_data_src_rdy
);
wire rst_in;
reg [7:0] rst_fifo_cnt;
wire rst_in_delay;
assign rst_in = rst | pll_not_locked;
always @(posedge user_clk or posedge rst_in) begin
if (rst_in) rst_fifo_cnt <= 8'b0;
else if (rst_fifo_cnt[4] == 1'b0) rst_fifo_cnt <= rst_fifo_cnt + 1'b1;
else rst_fifo_cnt <= rst_fifo_cnt;
end
assign rst_in_delay = (~rst_fifo_cnt[4]);
//--------------------------------------
wire fifo_rd_t;
wire [31:0] fifo_rd_data_t;
wire [17:0] fifo_cnt_t;
wire [17:0] partner_empty_slots;
wire partner_empty_slots_valid;
wire [17:0] empty_slots;
wire fifo_wr_s;
wire [31:0] fifo_wr_dat_s;
wire rst_transmitter;
wire rst_receiver;
prefetch_fifo u_prefetch_fifo (
.clk_i(user_clk),
.reset_i(rst_in_delay), //logic
.reset_i_fifo(rst_in), //fifo
//rd fifo interface
.fifo_dat_i(fifo_dat_i),
.fifo_empty_i(fifo_empty_i),
.fifo_rd_o(fifo_rd_o),
//Aurora transmitter interface
.prefetch_fifo_empty(prefetch_fifo_empty),
.fifo_rd_i(fifo_rd_t),
.fifo_dat_o(fifo_rd_data_t),
.fifo_cnt_o(fifo_cnt_t)
);
assign rst_transmitter = (~channel_rdy) | rst_in_delay;
Aurora_transmitter u_Aurora_transmitter (
.clk_i(user_clk),
.reset_i(rst_transmitter),
//rd fifo interface
.fifo_rd(fifo_rd_t),
.fifo_dat(fifo_rd_data_t),
.fifo_empty(prefetch_fifo_empty),
.fifo_cnt(fifo_cnt_t),
.fifo_dat_valid(1'b0),
//wr fifo interface
.empty_slots(empty_slots), //lower bounds of available slots
//partner info
.partner_empty_slots(partner_empty_slots),
.partner_empty_slots_valid(partner_empty_slots_valid),
//
.tx_data(tx_data),
.tx_data_src_rdy(tx_data_src_rdy),
.tx_data_dst_rdy(tx_data_dst_rdy)
);
assign rst_receiver = (~channel_rdy) | rst_in_delay;
Aurora_receiver u_Aurora_receiver (
.clk_i(user_clk),
.reset_i(rst_receiver),
//
.rx_data(rx_data),
.rx_data_src_rdy(rx_data_src_rdy),
//wr fifo interface
.fifo_data(fifo_wr_dat_s),
.fifo_wr_en(fifo_wr_s),
//ctrl words
.partner_empty_slots(partner_empty_slots),
.partner_empty_slots_valid(partner_empty_slots_valid)
);
hold_fifo u_hold_fifo (
.clk_i(user_clk),
.reset_i(rst_in_delay),
.reset_i_fifo(rx_fifo_rst),
//wr fifo interface
.fifo_wr_dat_o(fifo_wr_dat_o),
.fifo_wr_o(fifo_wr_o),
.fifo_full_i(fifo_full_i),
//Aurora receiver interface
.fifo_wr_i(fifo_wr_s),
.fifo_wr_dat_i(fifo_wr_dat_s),
//Aurora transmitter interface
.empty_slots(empty_slots)
);
endmodule
| 6.845304 |
module is a pattern checker to test the Aurora
// designs in hardware. The frames generated by FRAME_GEN
// pass through the Aurora channel and arrive at the frame checker
// through the RX User interface. Every time an error is found in
// the data recieved, the error count is incremented until it
// reaches its max value.
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_FRAME_CHECK
(
// User Interface
RX_D,
RX_SRC_RDY_N,
// System Interface
USER_CLK,
RESET,
ERROR_COUNT
);
//***********************************Port Declarations*******************************
// User Interface
input [0:31] RX_D;
input RX_SRC_RDY_N;
// System Interface
input USER_CLK;
input RESET;
output [0:7] ERROR_COUNT;
reg [0:7] ERROR_COUNT;
//***************************Internal Register Declarations***************************
reg [0:31] data_r;
reg data_valid_r;
reg error_detected_r;
reg [0:8] error_count_r;
//*********************************Wire Declarations**********************************
wire data_valid_c;
wire error_detected_c;
//*********************************Main Body of Code**********************************
//______________________________ Capture incoming data ___________________________
//Data is valid when RX_SRC_RDY_N is asserted
assign data_valid_c = !RX_SRC_RDY_N;
//Capture valid incoming data, right shifted 1 bit for comparison with the next valid
//incoming data
always @(posedge USER_CLK)
if(data_valid_c)
data_r <= `DLY {RX_D[31],RX_D[0:30]};
//Data in the data register is valid only if it was valid when captured and had no error
always @(posedge USER_CLK)
if(RESET) data_valid_r <= `DLY 1'b0;
else data_valid_r <= `DLY data_valid_c && !error_detected_c;
//___________________________ Check incoming data for errors __________________________
//An error is detected when valid data from the data register, when right shifted, does not match valid data
//from the Aurora RX port
assign error_detected_c = data_valid_c && data_valid_r && (RX_D != data_r);
//We register the error_detected signal for use with the error counter logic
always @(posedge USER_CLK)
if(RESET)
error_detected_r <= `DLY 1'b0;
else
error_detected_r <= `DLY error_detected_c;
//We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
//errors we did not directly observe. This counter must be reset when it reaches its max value
always @(posedge USER_CLK)
begin
if(RESET)
error_count_r <= `DLY 9'd0;
else if(error_detected_r && !error_count_r[0] )
error_count_r <= `DLY error_count_r + 1;
if(!error_count_r[0])
assign ERROR_COUNT = error_count_r[1:8];
else
assign ERROR_COUNT = 8'b11111111;
end
//Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
//max value) to the module output
endmodule
| 6.894155 |
module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. The data it generates on each cycle is
// a word of all zeros, except for one high bit which
// is shifted right each cycle. REM is always set to
// the maximum value.
`timescale 1 ns / 1 ps
`define DLY #1
module aurora_FRAME_GEN
(
// User Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// System Interface
USER_CLK,
RESET
);
//***********************************Port Declarations*******************************
// User Interface
output [0:31] TX_D;
output TX_SRC_RDY_N;
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
//***************************External Register Declarations***************************
reg TX_SRC_RDY_N;
//***************************Internal Register Declarations***************************
reg [0:31] tx_d_r;
//*********************************Main Body of Code**********************************
//______________________________ Transmit Data __________________________________
//Transmit data when TX_DST_RDY_N is asserted. Data is right shifted every cycle.
//TX_SRC_RDY_N is asserted on every cycle with data
always @(posedge USER_CLK)
if(RESET)
begin
tx_d_r <= `DLY 32'd1;
TX_SRC_RDY_N <= `DLY 1'b1;
end
else if(!TX_DST_RDY_N)
begin
tx_d_r <= `DLY {tx_d_r[31],tx_d_r[0:30]};
TX_SRC_RDY_N <= `DLY 1'b0;
end
//Connect TX_D to the internal tx_d_r register
assign TX_D = tx_d_r;
endmodule
| 7.0217 |
module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_framing_CHANNEL_ERROR_DETECT
(
// Aurora Lane Interface
SOFT_ERROR,
HARD_ERROR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERROR;
input HARD_ERROR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERROR;
reg CHANNEL_HARD_ERROR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_error_r;
reg hard_error_r;
//*********************************Wire Declarations**********************************
wire channel_soft_error_c;
wire channel_hard_error_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_error_r <= `DLY SOFT_ERROR;
hard_error_r <= `DLY HARD_ERROR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERROR = 1'b1;
assign channel_soft_error_c = soft_error_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERROR <= `DLY channel_soft_error_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERROR = 1'b1;
assign channel_hard_error_c = hard_error_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERROR <= `DLY channel_hard_error_c;
// "reset_channel_r" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !LANE_UP;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
| 7.591032 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_framing_GLOBAL_LOGIC
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR
);
`define DLY #1
//*******************************Parameter Declarations******************************
parameter EXTEND_WATCHDOGS = 0;
//***********************************Port Declarations*******************************
// MGT Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERROR;
input LANE_UP;
input HARD_ERROR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
defparam aurora_framing_channel_init_sm_i.EXTEND_WATCHDOGS = EXTEND_WATCHDOGS;
aurora_framing_CHANNEL_INIT_SM aurora_framing_channel_init_sm_i
(
// MGT Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_framing_IDLE_AND_VER_GEN aurora_framing_idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_framing_CHANNEL_ERROR_DETECT aurora_framing_channel_error_detect_i
(
// Aurora Lane Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERROR(CHANNEL_SOFT_ERROR),
.CHANNEL_HARD_ERROR(CHANNEL_HARD_ERROR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module aurora_framing_PHASE_ALIGN (
//Aurora Lane Interface
ENA_COMMA_ALIGN,
//MGT Interface
RX_REC_CLK,
ENA_CALIGN_REC
);
`define DLY #1
//***********************************Port Declarations*******************************
//synthesis attribute keep_hierarchy PHASE_ALIGN true;
//Aurora Lane Interface
input [0:0] ENA_COMMA_ALIGN;
//MGT Interface
input [0:0] RX_REC_CLK;
output [0:0] ENA_CALIGN_REC;
//**************************External Register Declarations****************************
//**************************Internal Register Declarations****************************
wire [0:1] phase_align_flops_r;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
// To phase align the signal, we sample it using a flop clocked with the recovered
// clock. We then sample the output of the first flop and pass it to the output.
// This ensures that the signal is not metastable, and prevents transitions from
// occuring except at the clock edge. The comma alignment circuit cannot tolerate
// transitions except at the recovered clock edge.
FD phase_align_flops_0 (
.D(ENA_COMMA_ALIGN[0]),
.C(RX_REC_CLK[0]),
.Q(phase_align_flops_r[0])
);
FD phase_align_flops_1 (
.D(phase_align_flops_r[0]),
.C(RX_REC_CLK[0]),
.Q(phase_align_flops_r[1])
);
assign ENA_CALIGN_REC[0] = phase_align_flops_r[1];
endmodule
| 7.795455 |
module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 1 ps
module aurora_GLOBAL_LOGIC
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR
);
`define DLY #1
//*******************************Parameter Declarations******************************
parameter EXTEND_WATCHDOGS = 0;
//***********************************Port Declarations*******************************
// MGT Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:1] SOFT_ERROR;
input LANE_UP;
input HARD_ERROR;
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output GEN_A;
output [0:3] GEN_K;
output [0:3] GEN_R;
output [0:3] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
defparam aurora_channel_init_sm_i.EXTEND_WATCHDOGS = EXTEND_WATCHDOGS;
aurora_CHANNEL_INIT_SM aurora_channel_init_sm_i
(
// MGT Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_IDLE_AND_VER_GEN aurora_idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_CHANNEL_ERROR_DETECT aurora_channel_error_detect_i
(
// Aurora Lane Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERROR(CHANNEL_SOFT_ERROR),
.CHANNEL_HARD_ERROR(CHANNEL_HARD_ERROR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
| 8.183782 |
module AURORA_IP_TOP (
//Global
input RESET,
// Status
output CHANNEL_UP,
// System Interface
input System_CLK_P,
input System_CLK_N,
// GT Reference Clock Interface
input GT_REF_CLK_P,
input GT_REF_CLK_N,
//TX Interface
input [0:63] txdata_i,
input txdata_sop_n_i,
input txdata_eop_n_i,
input [ 0:2] txdata_mod_i,
input tx_src_rdy_n_i,
output tx_dst_rdy_n_o,
//RX Interface
output [0:63] rxdata_o,
output rxdata_sop_n_o,
output rxdata_eop_n_o,
output [ 0:2] rxdata_mod_o,
output rx_src_rdy_n_o,
//User Clock
output user_clk_o,
// GTX Serial I/O
input RXP,
input RXN,
output TXP,
output TXN
);
//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s)
//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGs
//WIREs
wire INIT_CLK;
wire DRP_CLK;
//*********************
//INSTANTCE MODULE
//*********************
clk_wiz_0 INIT_DRP_CLK_gen (
// Clock out ports
.INIT_CLK (INIT_CLK), // output INIT_CLK
.DRP_CLK (DRP_CLK), // output DRP_CLK
// Status and control signals
.reset (RESET), // input reset
.locked (), // output locked
// Clock in ports
.clk_in1_p(System_CLK_P), // input clk_in1_p
.clk_in1_n(System_CLK_N)
); // input clk_in1_n
aurora_64b66b_m_0_exdes aurora_master_0 (
// User IO
.RESET(RESET),
// Error signals from Aurora
.HARD_ERR (),
.SOFT_ERR (),
// Status Signals
.LANE_UP(),
.CHANNEL_UP(CHANNEL_UP),
.INIT_CLK_IN (INIT_CLK),
.PMA_INIT (1'b0),
.DRP_CLK_IN (DRP_CLK),
// Clock Signals
.GTHQ1_P(GT_REF_CLK_P),
.GTHQ1_N(GT_REF_CLK_N),
//User Interface
.txdata_i (txdata_i),
.txdata_sop_n_i(txdata_sop_n_i),
.txdata_eop_n_i(txdata_eop_n_i),
.txdata_mod_i (txdata_mod_i),
.tx_src_rdy_n_i(tx_src_rdy_n_i),
.tx_dst_rdy_n_o(tx_dst_rdy_n_o),
.rxdata_o (rxdata_o),
.rxdata_sop_n_o(rxdata_sop_n_o),
.rxdata_eop_n_o(rxdata_eop_n_o),
.rxdata_mod_o (rxdata_mod_o),
.rx_src_rdy_n_o(rx_src_rdy_n_o),
.user_clk_o(user_clk_o),
// GT I/O
.RXP(RXP),
.RXN(RXN),
.TXP(TXP),
.TXN(TXN)
);
//*********************
//MAIN CORE
//*********************
//*********************
endmodule
| 6.511769 |
module aurora_phy_clk_gen (
input areset,
input refclk_p,
input refclk_n,
output refclk,
output clk156,
output init_clk
);
wire clk156_buf;
wire init_clk_buf;
wire clkfbout;
IBUFDS_GTE2 ibufds_inst (
.O (refclk),
.ODIV2(),
.CEB (1'b0),
.I (refclk_p),
.IB (refclk_n)
);
BUFG clk156_bufg_inst (
.I(refclk),
.O(clk156)
);
// Divding independent clock by 2 as source for DRP clock
BUFR #(
.BUFR_DIVIDE("2")
) dclk_divide_by_2_buf (
.I (clk156),
.O (init_clk_buf),
.CE (1'b1),
.CLR(1'b0)
);
BUFG dclk_bufg_i (
.I(init_clk_buf),
.O(init_clk)
);
endmodule
| 6.505467 |
module AusdioTut (
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// I2C for Audio and Video-In //////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// VGA //////////
output VGA_BLANK_N,
output [7:0] VGA_B,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
| 7.187105 |
module Auto2 (
clock0,
clock180,
reset,
leds,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock0;
input wire clock180;
input wire reset;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [ 7:0] seq_next;
wire [ 11:0] seq_oreg;
wire [ 7:0] seq_oreg_wen;
wire [ 19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [ 7:0] alu_result;
wire swc_ready;
Seq seq (
.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0, swc_ready}),
.ireg_2(8'h00),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen)
);
Auto2Rom coderom (
.addr (seq_next),
.data_o(coderom_data_o)
);
`ifdef SIM
Auto2RomText coderomtext (
.addr (seq_next),
.data_o(coderomtext_data_o)
);
`endif
Alu alu (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result)
);
Swc swc (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.ready(swc_ready)
);
LedBank ledbank (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.leds(leds)
);
VGA1 vga (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[3]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
| 7.272661 |
module Auto2FPGA (
clock,
reset,
leds,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock;
input wire reset;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire cm_locked;
wire cm_clock0;
wire cm_clock180;
ClockManager cm (
.clock(clock),
.reset(reset),
.locked (cm_locked),
.clock0 (cm_clock0),
.clock180(cm_clock180)
);
Auto2 auto2 (
.clock0(cm_clock0),
.clock180(cm_clock180),
.reset(reset & cm_locked),
.leds(leds),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
| 7.284943 |
module autoanim_sync (
input CLK,
input RASTER8,
input RESETP,
input [7:0] AA_SPEED,
output [2:0] AA_COUNT
);
wire [3:0] D151_Q;
//wire B91_CO;
//wire E117_CO;
//wire E95A_OUT = ~|{E117_CO, 1'b0}; // Used for test mode
//wire E149_OUT = ~^{CLK, 1'b0}; // Used for test mode
// Timer counters
//C43 B91(E149_OUT, ~AA_SPEED[3:0], E95A_OUT, 1'b1, 1'b1, 1'b1, , B91_CO);
//C43 E117(E149_OUT, ~AA_SPEED[7:4], E95A_OUT, 1'b1, B91_CO, 1'b1, , E117_CO);
// Auto-anim tile counter
//C43 D151(E149_OUT, 4'b0000, 1'b1, 1'b1, E117_CO, RESETP, D151_Q);
//assign AA_COUNT = D151_Q[2:0];
reg [7:0] TIMER_CNT;
reg [3:0] AA_CNT_FULL;
always @(posedge CLK) begin
reg RASTER8_d;
RASTER8_d <= RASTER8;
if (~RASTER8_d & RASTER8) begin
if (&TIMER_CNT) TIMER_CNT <= ~AA_SPEED;
else TIMER_CNT <= TIMER_CNT + 1'd1;
if (!RESETP) AA_CNT_FULL <= 0;
else if (&TIMER_CNT) AA_CNT_FULL <= AA_CNT_FULL + 1'd1;
end
end
assign AA_COUNT = AA_CNT_FULL[2:0];
endmodule
| 7.003183 |
module AutoBoot (
input wire clk,
input wire rstn,
input wire [15:0] TokenReady_i,
output wire [15:0] TokenValid_o,
input wire TokenXReady_i,
output wire TokenXValid_o,
output wire [3:0] ID_o
);
localparam IDLE = 2'b00;
localparam XADC = 2'b01;
localparam LOGI = 2'b10;
reg [1:0] StateCr = IDLE;
reg [1:0] StateNxt;
always @(posedge clk or negedge rstn) begin
if (~rstn) StateCr <= IDLE;
else StateCr <= StateNxt;
end
reg [32:0] Slack = 33'b0;
always @(posedge clk or negedge rstn) begin
if (~rstn) Slack <= 33'b0;
else if (StateCr == IDLE) Slack <= Slack + 33'b1;
else Slack <= 33'b0;
end
wire SlackDone;
assign SlackDone = Slack == 33'd60_000_000_000;
wire ReadySel;
reg [3:0] LogicSel = 4'h0;
always @(posedge clk or negedge rstn) begin
if (~rstn) LogicSel <= 4'h0;
else if ((StateCr == LOGI) & ReadySel) LogicSel <= LogicSel + 4'h1;
end
assign ReadySel = TokenReady_i[LogicSel];
always @(*) begin
case (StateCr)
IDLE: if (SlackDone) StateNxt = XADC;
else StateNxt = StateCr;
XADC: if (TokenXReady_i) StateNxt = LOGI;
else StateNxt = StateCr;
LOGI: if (ReadySel) StateNxt = IDLE;
else StateNxt = StateCr;
default: StateNxt = IDLE;
endcase
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : TokenDec
assign TokenValid_o[i] = (StateCr == XADC) & TokenXReady_i & (LogicSel == i);
end
endgenerate
assign TokenXValid_o = (StateCr == IDLE) & SlackDone;
assign ID_o = LogicSel;
endmodule
| 8.050907 |
module autoconfig #(
parameter INTERLEAVED = 0,
parameter ENABLE = 0
) (
input clk,
input rst,
output busy,
output [15:0] config_data,
output [ 3:0] config_addr,
output config_start,
input config_done
);
localparam STATE_IDLE = 0;
localparam STATE_BUSY = 1;
localparam STATE_DONE = 2;
localparam REG_COUNT = 4'd9;
generate
if (ENABLE) begin : AUTO_ENABLE_generate
reg [1:0] config_state;
reg [3:0] progress;
always @(posedge clk) begin
if (rst) begin
config_state <= STATE_IDLE;
end else begin
case (config_state)
STATE_IDLE: begin
config_state <= STATE_BUSY;
end
STATE_BUSY: begin
if (progress == REG_COUNT - 1 && config_done) begin
config_state <= STATE_DONE;
end
end
STATE_DONE: begin
end
endcase
end
end
assign busy = config_state != STATE_DONE;
reg config_start_reg;
assign config_start = config_start_reg;
reg waiting;
always @(posedge clk) begin
config_start_reg <= 1'b0;
if (config_state == STATE_IDLE) begin
waiting <= 0;
progress <= 4'b0;
end else begin
if (progress < 9) begin
if (!waiting) begin
config_start_reg <= 1'b1;
waiting <= 1'b1;
end
if (config_done) begin
waiting <= 1'b0;
progress <= progress + 1;
end
end
end
end
assign config_data = progress == 0 ? 16'h7FFF :
progress == 1 ? 16'hBAFF :
progress == 2 ? 16'h007F :
progress == 3 ? 16'h807F :
progress == 4 ? (INTERLEAVED ? 16'h23FF : 16'h03FF ):
progress == 5 ? 16'h007F :
progress == 6 ? 16'h807F :
progress == 7 ? 16'h00FF :
16'h007F;
assign config_addr = progress == 0 ? 4'h0 :
progress == 1 ? 4'h1 :
progress == 2 ? 4'h2 :
progress == 3 ? 4'h3 :
progress == 4 ? 4'h9 :
progress == 5 ? 4'ha :
progress == 6 ? 4'hb :
progress == 7 ? 4'he :
4'hf;
end else begin : AUTO_DISABLE_generate
assign busy = 0;
assign config_data = 0;
assign config_addr = 0;
assign config_start = 0;
end
endgenerate
endmodule
| 7.807376 |
module autoconfig (
input RESET,
input AS20,
input RW20,
input DS20,
input [31:0] A,
input [15:0] D,
output [ 7:4] DOUT,
output ACCESS,
output [1:0] DECODE
);
localparam RAM_CARD = 0;
localparam SPI_CARD = 1;
localparam CONFIGURING_RAM = 2'b00;
localparam CONFIGURING_SPI = 2'b01;
reg [1:0] config_out = 'd0;
reg [1:0] configured = 'd0;
reg [1:0] shutup = 'd0;
reg [7:4] data_out = 'd0;
// 0xE80000
wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | (&config_out);
wire Z2_WRITE = (Z2_ACCESS | RW20);
wire [5:0] zaddr = {A[6:1]};
always @(posedge AS20 or negedge RESET) begin
if (RESET == 1'b0) begin
config_out <= 'd0;
end else begin
config_out <= configured | shutup;
end
end
always @(negedge DS20 or negedge RESET) begin
if (RESET == 1'b0) begin
configured <= 'd0;
shutup <= 'd0;
data_out[7:4] <= 4'hf;
end else begin
if (Z2_WRITE == 1'b0) begin
case (zaddr)
'h24: begin //configure logic
if (config_out == 2'b00) configured[0] <= 1'b1;
if (config_out == 2'b01) configured[1] <= 1'b1;
end
'h26: begin // shutup logic
if (config_out == 2'b00) shutup[0] <= 1'b1;
if (config_out == 2'b01) shutup[1] <= 1'b1;
end
endcase
end
// autoconfig ROMs
case (zaddr)
6'h00: begin
if (config_out == CONFIGURING_SPI) data_out[7:4] <= 4'hc;
if (config_out == CONFIGURING_RAM) data_out[7:4] <= 4'he;
end
6'h01: begin
if (config_out == CONFIGURING_SPI) data_out[7:4] <= 4'h1;
if (config_out == CONFIGURING_RAM) data_out[7:4] <= 4'h6;
end
6'h02: begin
if (config_out == CONFIGURING_SPI) data_out[7:4] <= 4'h7;
if (config_out == CONFIGURING_RAM) data_out[7:4] <= 4'hf;
end
// common autoconfig params
6'h03: data_out[7:4] <= 4'he;
6'h04: data_out[7:4] <= 4'h7;
6'h08: data_out[7:4] <= 4'he;
6'h09: data_out[7:4] <= 4'hc;
6'h0a: data_out[7:4] <= 4'h2;
6'h0b: data_out[7:4] <= 4'h7;
6'h11: data_out[7:4] <= 4'hd;
6'h12: data_out[7:4] <= 4'he;
6'h13: data_out[7:4] <= 4'hd;
default: data_out[7:4] <= 4'hf;
endcase
end
end
// decode the base addresses
// these are hardcoded to the address they always get assigned to.
assign DECODE[SPI_CARD] = ({A[23:16]} != {8'he9}) | shutup[SPI_CARD];
`ifndef ATARI
assign DECODE[RAM_CARD] = ({A[23:21]} != {3'b001}) | shutup[RAM_CARD];
`else
assign DECODE[RAM_CARD] = ({A[31:21]} != {8'h01, 3'b000}) | shutup[RAM_CARD]; // 2MB TT-RAM
`endif
assign ACCESS = Z2_ACCESS;
assign DOUT = data_out;
endmodule
| 7.404861 |
module: Autocorr_Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Autocorr_test;
`include "paramList.v"
// Inputs
reg clk;
reg reset;
reg start;
reg [7:0] xMemAddr;
reg [31:0] xMemOut;
reg xMemEn;
reg autocorrMuxSel;
reg [11:0] testReadRequested;
reg [11:0] testWriteRequested;
reg [31:0] testMemOut;
reg testMemWrite;
// Outputs
wire done;
wire [31:0] memIn;
//working regs
reg [15:0] autocorrInMem [0:9999];
reg [31:0] autocorrOutMem [0:9999];
integer i,j;
//file read in for inputs and output tests
initial
begin// samples out are samples from ITU G.729 test vectors
$readmemh("tame_autocorr_in.out", autocorrInMem);
$readmemh("tame_autocorr_out.out", autocorrOutMem);
end
// Instantiate the Unit Under Test (UUT)
Autocorr_Top uut (
.clk(clk),
.reset(reset),
.start(start),
.xMemAddr(xMemAddr),
.xMemOut(xMemOut),
.xMemEn(xMemEn),
.autocorrMuxSel(autocorrMuxSel),
.testReadRequested(testReadRequested),
.testWriteRequested(testWriteRequested),
.testMemOut(testMemOut),
.testMemWrite(testMemWrite),
.done(done),
.memIn(memIn)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
start = 0;
xMemAddr = 0;
xMemOut = 0;
xMemEn = 0;
autocorrMuxSel = 1;
testReadRequested = 0;
testWriteRequested = 0;
testMemOut = 0;
testMemWrite = 0;
// Wait 150 ns for global reset to finish
@(posedge clk) #5;
reset = 1;
@(posedge clk) #5;
reset = 0;
@(posedge clk);
@(posedge clk) #5;
for(j=0;j<5;j=j+1)
begin
@(posedge clk);
@(posedge clk) #5;
autocorrMuxSel = 1;
//writing the previous modules to memory
for(i=0;i<240;i=i+1)
begin
@(posedge clk);
@(posedge clk) #5;
xMemAddr = i[7:0];
xMemOut = autocorrInMem[j*240+i];
xMemEn = 1;
@(posedge clk);
@(posedge clk) #5;
end
autocorrMuxSel = 0;
xMemEn = 0;
start = 1;
@(posedge clk);
@(posedge clk) #5;
start = 0;
@(posedge clk);
@(posedge clk) #5;
wait(done);
// @(posedge clk) #5;
// Add stimulus here
autocorrMuxSel = 1;
for (i = 0; i<11;i=i+1)
begin
testReadRequested = {AUTOCORR_R[10:4],i[3:0]};
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
if (memIn != autocorrOutMem[11*j+i])
$display($time, " ERROR: r[%d] = %x, expected = %x", 11*j+i, memIn, autocorrOutMem[11*j+i]);
else if (memIn == autocorrOutMem[11*j+i])
$display($time, " CORRECT: r[%d] = %x", 11*j+i, memIn);
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
end
end// for loop j
end//end initial
initial forever #10 clk = ~clk; //50MHz Clock
endmodule
| 7.074428 |
module Autofire #(
parameter FREQ = 37_800_000,
parameter FIRERATE = 10
) (
input clk,
input resetn,
input btn,
input reg out
);
localparam DELAY = FREQ / FIRERATE / 2;
reg [$clog2(DELAY)-1:0] timer;
always @(posedge clk) begin
if (~resetn) begin
timer <= 0;
out <= 0;
end else begin
if (btn) begin
timer <= timer + 1;
if (timer == 0) out <= ~out;
if (timer == DELAY - 1) timer <= 0;
end else begin
timer <= 0;
out <= 0;
end
end
end
endmodule
| 7.186073 |
module AutoIncOutput (
input reset_n,
clk,
input OUT1n,
BD3,
input [2:0] BA,
output BUF1BUF2n,
STARTLED1,
output SIREn,
PLAYER2,
output YINCn,
XINCn,
output AYn,
AXn
);
reg [7:0] q;
always @(posedge clk or negedge reset_n) //ic6P
begin
if (~reset_n) q <= #1 8'b00000000;
else if (~OUT1n)
case (BA)
3'b000: q[0] <= #1 BD3;
3'b001: q[1] <= #1 BD3;
3'b010: q[2] <= #1 BD3;
3'b011: q[3] <= #1 BD3;
3'b100: q[4] <= #1 BD3;
3'b101: q[5] <= #1 BD3;
3'b110: q[6] <= #1 BD3;
3'b111: q[7] <= #1 BD3;
endcase
end
assign BUF1BUF2n = q[7];
assign STARTLED1 = q[6];
assign SIREn = q[5];
assign PLAYER2 = q[4];
assign YINCn = q[3];
assign XINCn = q[2];
assign AYn = q[1];
assign AXn = q[0];
endmodule
| 6.641314 |
module AutoIncrement (
input clk,
reset_n,
ce2H,
input [15:0] BA,
input [7:0] BD,
input BITMDn,
input XCOORDn,
XINCn,
AXn,
input YCOORDn,
YINCn,
AYn,
output [14:0] DRBA,
output PIXA
);
assign DRBA = ~BITMDn ? {yCoord, xCoord[7:1]} : BA[14:0];
reg [7:0] xCoord, yCoord;
assign PIXA = xCoord[0];
always @(posedge clk or negedge reset_n) begin
if (~reset_n) xCoord <= #1 8'b0000000;
else if (~XCOORDn) xCoord <= #1 BD;
else if (~AXn & ~BITMDn & ce2H) begin
if (XINCn) xCoord <= #1 xCoord - 8'b00000001;
else xCoord <= #1 xCoord + 8'b00000001;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) yCoord <= #1 8'b0000000;
else if (~YCOORDn) yCoord <= #1 BD;
else if (~AYn & ~BITMDn & ce2H) begin
if (YINCn) yCoord <= #1 yCoord - 8'b00000001;
else yCoord <= #1 yCoord + 8'b00000001;
end
end
endmodule
| 6.677897 |
module AutoLock (
input wire clk,
input wire update,
input wire [15:0] errorsig,
input wire signed [15:0] discriminator,
input wire signed [15:0] threshold,
input wire enable,
output reg enable_lock_out = 0,
output reg scanEnable = 0,
input wire [31:0] timeout
);
reg [3:0] state = 4'h0;
localparam s_idle = 4'h0, s_searching = 4'h1, s_wait = 4'h2, s_locked = 4'h3, s_dropout = 4'h4;
wire aboveThreshold = ($signed(discriminator) > $signed(threshold));
reg [29:0] dropout_count = 0;
// control state transitions
always @(posedge clk) begin
if (~enable) begin
state <= s_idle;
enable_lock_out <= 1'b0;
scanEnable <= 1'b0;
end else
case (state)
s_idle: begin
state <= s_searching;
end
s_searching: begin
if (aboveThreshold) begin
state <= s_wait;
enable_lock_out <= 1'b1;
scanEnable <= 1'b0;
end else begin
enable_lock_out <= 1'b0;
scanEnable <= 1'b1;
end
end
s_wait: begin
state <= s_locked;
end
s_locked: begin
if (aboveThreshold) begin
enable_lock_out <= 1'b1;
scanEnable <= 1'b0;
end else begin
state <= s_dropout;
end
dropout_count <= timeout[31:2];
end
s_dropout: begin
if (aboveThreshold) begin
state <= s_locked;
end else begin
if (|dropout_count) begin
dropout_count <= dropout_count - 1;
end else begin
state <= s_searching;
end
end
end
endcase
end
endmodule
| 6.9465 |
module AutoLock_tb;
wire clk;
clock_gen #(20) mclk (clk);
// Inputs
reg update;
reg [15:0] errorsig;
reg [15:0] discriminator;
reg [15:0] threshold;
reg enable;
reg [31:0] pCoeff;
reg [31:0] iCoeff;
reg [15:0] input_offset0;
reg lock_enable;
reg [15:0] scan_increment_0, scan_min_0, scan_max_0;
reg [31:0] timeout;
// Outputs
wire enable_lock_out;
wire scanEnable;
wire [15:0] regOut;
wire regulatorUpdate;
wire [1:0] externalStatus;
wire [15:0] lockScan;
// Instantiate the Unit Under Test (UUT)
wire scan_upd, pi_gate_0;
delayed_on_gate delayed_on_gate_0 (
.clk(clk),
.gate(lock_enable | enable_lock_out),
.delay(0),
.q(pi_gate_0)
);
picore ampl_piCore0 (
.clk(clk),
.update(update),
.errorsig(errorsig),
.pCoeff(pCoeff[31:0]),
.iCoeff(iCoeff[31:0]),
.enable(pi_gate_0),
.sclr(0),
.regOut(regOut),
.regOutUpdate(regulatorUpdate),
.inputOffset(input_offset0[15:0]),
.underflow(externalStatus[0]),
.overflow(externalStatus[1]),
.output_offset(lockScan),
.set_output_offset(scanEnable),
.set_output_clk(scan_upd)
);
AutoLock Autolock0 (
.clk(clk),
.update(update),
.errorsig(errorsig),
.discriminator(discriminator),
.threshold(threshold),
.enable(enable),
.enable_lock_out(enable_lock_out),
.scanEnable(scanEnable),
.timeout(timeout)
);
VarScanGenerator scanGenLock (
.clk(clk),
.increment(scan_increment_0),
.sinit(1'b0),
.scan_min(scan_min_0),
.scan_max(scan_max_0),
.scan_enable(scanEnable),
.q(lockScan),
.output_upd(scan_upd)
);
initial begin
// Initialize Inputs
update = 0;
errorsig = 10;
discriminator = -20;
threshold = 1000;
enable = 0;
pCoeff = 10;
iCoeff = 10;
input_offset0 = 0;
lock_enable = 0;
scan_increment_0 = 1000;
scan_min_0 = 0;
scan_max_0 = 10000;
timeout = 16;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
enable = 1;
#3000;
discriminator = 12000;
#8000;
discriminator = 100;
end
endmodule
| 6.827295 |
module automated_fsm (
reset_n,
clock,
direction,
stop,
begin_signal,
sync_counter,
out_x,
out_y,
out_color
);
input reset_n, clock, stop, begin_signal, sync_counter;
input [1:0] direction;
output reg [7:0] out_x;
output reg [6:0] out_y;
output reg [2:0] out_color;
reg [3:0] current_state, next_state;
localparam DRAW_UP = 4'b0000,
DRAW_DOWN = 4'b0001,
DRAW_RIGHT = 4'b0010,
DRAW_LEFT = 4'b0011,
CHANGE_UP = 4'b0100,
CHANGE_DOWN = 4'b0101,
CHANGE_RIGHT = 4'b0110,
CHANGE_LEFT = 4'b0111,
AUTOMATIC_SEQUENCE_REST = 4'b1000,
UPDATE_COLOR = 4'b1001;
// BEGIN_WAIT = 3'b100;
always @(posedge clock) begin
if (!reset_n) begin
current_state <= DRAW_UP;
end else begin
current_state <= next_state;
end
end
always @(posedge sync_counter) begin : state_table
case (current_state)
DRAW_UP: next_state = DRAW_DOWN;
DRAW_DOWN: next_state = DRAW_LEFT;
DRAW_LEFT: next_state = DRAW_RIGHT;
DRAW_RIGHT: next_state = begin_signal ? AUTOMATIC_SEQUENCE_REST : DRAW_RIGHT;
AUTOMATIC_SEQUENCE_REST: next_state = stop ? AUTOMATIC_SEQUENCE_REST : UPDATE_COLOR;
UPDATE_COLOR: begin
if (direction == 2'b00) next_state = CHANGE_UP;
else if (direction == 2'b01) next_state = CHANGE_DOWN;
else if (direction == 2'b10) next_state = CHANGE_RIGHT;
else if (direction == 2'b11) next_state = CHANGE_LEFT;
end
CHANGE_UP: next_state = DRAW_UP;
CHANGE_DOWN: next_state = DRAW_UP;
CHANGE_RIGHT: next_state = DRAW_UP;
CHANGE_LEFT: next_state = DRAW_UP;
endcase
end
always @(posedge clock) begin
out_color = 3'b111;
case (current_state)
DRAW_UP: begin
out_x <= 8'b01001110;
out_y <= 7'b0110110;
out_color <= 3'b111;
end
DRAW_DOWN: begin
out_x <= 8'b01001110;
out_y <= 7'b0111110;
out_color <= 3'b111;
end
DRAW_LEFT: begin
out_x <= 8'b01001010;
out_y <= 7'b0111010;
out_color <= 3'b111;
end
DRAW_RIGHT: begin
out_x <= 8'b01010010;
out_y <= 7'b0111010;
out_color <= 3'b111;
end
AUTOMATIC_SEQUENCE_REST: begin
out_x <= 8'b01001010;
out_y <= 7'b0111010;
out_color <= 3'b111;
end
UPDATE_COLOR: begin
end
CHANGE_DOWN: begin
out_x <= 8'b01001110;
out_y <= 7'b0111110;
out_color <= 3'b010;
end
CHANGE_UP: begin
out_x <= 8'b01001110;
out_y <= 7'b0110110;
out_color <= 3'b010;
end
CHANGE_LEFT: begin
out_x <= 8'b01001010;
out_y <= 7'b0111010;
out_color <= 3'b010;
end
CHANGE_RIGHT: begin
out_x <= 8'b01010010;
out_y <= 7'b0111010;
out_color <= 3'b010;
end
endcase
end
endmodule
| 7.348733 |
module
*/
module AutomaticGainControl(
clk,
din, din_valid,
dout, dout_valid,
agc_gain
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
localparam DATA_WIDTH = 32; //Width of one integer being summed
parameter AGC_SAMPLES = 2048; //Number of samples to run over for the peak detector
parameter MIN_AMPLITUDE = 32'h20000000;
parameter MAX_AMPLITUDE = 32'h40000000;
`include "../util/clog2.vh";
localparam AGC_BITS = clog2(AGC_SAMPLES);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
input wire clk;
input wire[DATA_WIDTH - 1 : 0] din; //The input data
input wire din_valid; //Set true to process data, false to ignore
output reg[DATA_WIDTH-1 : 0] dout = 0; //Output bus
output reg dout_valid = 0; //Goes high to indicate new data is ready
output reg[DATA_WIDTH-1:0] agc_gain = 32'h00010000; //fixed point 16.16, unity gain
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The core AGC logic
//Gain compensation
(* MULT_STYLE = "PIPE_BLOCK" *)
reg[DATA_WIDTH*2-1:0] agc_mult = 0;
reg[DATA_WIDTH*2-1:0] agc_mult_ff = 0;
reg[DATA_WIDTH*2-1:0] agc_mult_ff2 = 0;
reg din_valid_ff = 0;
reg din_valid_ff2 = 0;
reg din_valid_ff3 = 0;
always @(posedge clk) begin
agc_mult <= $signed(agc_gain) * $signed(din);
agc_mult_ff <= agc_mult;
agc_mult_ff2 <= agc_mult_ff;
din_valid_ff <= din_valid;
din_valid_ff2 <= din_valid_ff;
din_valid_ff3 <= din_valid_ff2;
dout_valid <= din_valid_ff3;
dout <= agc_mult_ff2[47:16]; //fixed point shift
end
//Post-gain control peak detector and feedback logic
reg[31:0] agc_max = 0;
reg[AGC_BITS-1:0] agc_count = 0;
wire[AGC_BITS-1:0] agc_count_next = agc_count + 1'h1;
always @(posedge clk) begin
//Peak detector
if($signed(dout) >= 0) begin
if(dout > agc_max)
agc_max <= dout;
end
else begin
if(-$signed(dout) > agc_max)
agc_max <= -$signed(dout);
end
agc_count <= agc_count_next;
//Count period is done, update the input gain
//TODO: smoother steps when updating (say 1/8192 every few clocks for N clocks)
if(agc_count_next == 0) begin
//If the signal is too weak and AGC isn't already maxed out, increase the gain by 1/128
if( (agc_max < MIN_AMPLITUDE) && (agc_gain < 32'h40000000) )
agc_gain <= agc_gain + agc_gain[31:9];
//If the signal is too strong and AGC isn't already bottomed out, decrease the gain by 1/128
if( (agc_max > MAX_AMPLITUDE) && (agc_gain > 32'h00000100) )
agc_gain <= agc_gain - agc_gain[31:9];
agc_max <= 0;
end
end
endmodule
| 7.373501 |
module automatic_washing_machine (
clk,
reset,
door_close,
start,
filled,
detergent_added,
cycle_timeout,
drained,
spin_timeout,
door_lock,
motor_on,
fill_value_on,
drain_value_on,
done,
soap_wash,
water_wash
);
input clk, reset, door_close, start, filled, detergent_added, cycle_timeout, drained, spin_timeout;
output reg door_lock, motor_on, fill_value_on, drain_value_on, done, soap_wash, water_wash;
//defining the states
parameter check_door = 3'b000;
parameter fill_water = 3'b001;
parameter add_detergent = 3'b010;
parameter cycle = 3'b011;
parameter drain_water = 3'b100;
parameter spin = 3'b101;
reg [2:0] current_state, next_state;
always@(current_state or start or door_close or filled or detergent_added or drained or cycle_timeout or spin_timeout)
begin
case (current_state)
check_door:
if (start == 1 && door_close == 1) begin
next_state = fill_water;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 0;
water_wash = 0;
done = 0;
end else begin
next_state = current_state; // Bug 1 Fixed
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 0; // Bug 2 Fixed
soap_wash = 0;
water_wash = 0;
done = 0;
end
fill_water:
if (filled == 1) begin
if (soap_wash == 0) begin
next_state = add_detergent;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 0;
done = 0;
end else begin
next_state = cycle;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
end else begin
next_state = current_state;
motor_on = 0;
fill_value_on = 1;
drain_value_on = 0;
door_lock = 1;
done = 0;
end
add_detergent:
if (detergent_added == 1) begin
next_state = cycle;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
done = 0;
end else begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 0;
done = 0;
end
cycle:
if (cycle_timeout == 1) begin
next_state = drain_water;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
//soap_wash = 1;
done = 0;
end else begin
next_state = current_state;
motor_on = 1;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
//soap_wash = 1;
done = 0;
end
drain_water:
if (drained == 1) begin
if (water_wash == 0) begin
next_state = fill_water;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
//water_wash = 1;
done = 0;
end else begin
next_state = spin;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
end else begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 1;
door_lock = 1;
soap_wash = 1;
//water_wash = 1;
done = 0;
end
spin:
if (spin_timeout == 1) begin
next_state = door_close;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 1;
end else begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 1;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
default: next_state = check_door;
endcase
end
always @(posedge clk or negedge reset) begin
if (reset) begin
current_state <= 3'b000;
end else begin
current_state <= next_state;
end
end
endmodule
| 6.788539 |
module automaton (
clk,
rst_n,
over,
start_sig,
gameready_sig,
over_sig
);
input clk;
input rst_n;
input over;
output start_sig;
output gameready_sig;
output over_sig;
/**************************************************/
parameter ready = 3'b001, game = 3'b010, game_over = 3'b100;
parameter T5S = 30'd125_000_000;
reg [29:0] count_T5S;
reg start;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
start <= 0;
count_T5S <= 0;
end else begin
if (count_T5S < T5S) begin
count_T5S <= count_T5S + 1'b1;
start <= 0;
end else if (count_T5S == T5S) begin
count_T5S <= 0;
start <= 1;
end else begin
count_T5S <= 0;
start <= 0;
end
end
end
/**************************************************/
reg [2:0] game_current_process;
reg [2:0] game_next_process;
reg start_sig;
reg gameready_sig;
reg over_sig;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) game_current_process <= ready;
else game_current_process <= game_next_process;
end
always @(game_current_process or start or over) begin
case (game_current_process)
ready: begin
ready_out;
if (start) game_next_process = game;
else game_next_process = ready;
end
game: begin
game_out;
if (over) game_next_process = game_over;
else game_next_process = game;
end
game_over: begin
over_out;
game_next_process = game_over;
end
default: begin
ready_out;
game_next_process = ready;
end
endcase
end
task ready_out;
{gameready_sig, start_sig, over_sig} = 3'b100;
endtask
task game_out;
{gameready_sig, start_sig, over_sig} = 3'b010;
endtask
task over_out;
{gameready_sig, start_sig, over_sig} = 3'b001;
endtask
/**************************************************/
endmodule
| 7.074838 |
module automaton_tb ();
parameter WIDTH = 80;
reg [7:0] count = 0;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del componente
wire [WIDTH-1:0] data;
//-- Instanciar el componente (N=1 aqui, segundos)
automaton #(
.WIDTH(WIDTH)
) myCA (
.clk (clk),
.data(data)
);
defparam myCA.N = 1; defparam myCA.RULE = 126; // http://mathworld.wolfram.com/Rule126.html
defparam myCA.SEED = 2 ** (WIDTH / 2);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
integer file;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("automaton_tb.vcd");
$dumpvars(0, automaton_tb);
#1 $display("data: %b (%d)", data, count);
file = $fopen("data.out", "wb");
$fwrite(file, "%b\n", data);
for (count = 1; count <= 59; count = count + 1) begin
#4 $display("data: %b (%d)", data, count);
$fwrite(file, "%b\n", data);
end
$fclose(file);
#1 $display("FIN de la simulacion");
$finish;
end
endmodule
| 6.615668 |
module topControl (
input CLOCK_50,
input [3:0] KEY,
output [9:0] LEDR,
output VGA_CLK,
output VGA_HS,
output VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
localparam DELAY = 5000000;
reg [ 8:0] xoffsetset;
reg [ 7:0] yoffsetset;
reg [23:0] delayCnt;
initial begin
xoffsetset <= 9'b010000000;
yoffsetset <= 8'd56;
delayCnt <= DELAY;
end
// move the sprite from right to left
always @(posedge CLOCK_50) begin
if (delayCnt == 0) begin
if (xoffsetset == 0) xoffsetset <= 9'b010000000;
else xoffsetset <= xoffsetset - 1;
delayCnt <= DELAY;
end else delayCnt <= delayCnt - 1;
end
autoPNGVGA u0 (
.CLOCK_50(CLOCK_50),
.xoffsetset(xoffsetset),
.yoffsetset(yoffsetset),
.KEY(KEY),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_B(VGA_B),
.VGA_G(VGA_G)
);
endmodule
| 8.29194 |
module autoPNGVGA (
input CLOCK_50,
input [8:0] xoffsetset,
input [7:0] yoffsetset,
input [3:0] KEY,
output VGA_CLK,
output VGA_HS,
output VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
reg [16:0] address;
wire [11:0] data;
reg [11:0] colour;
reg [ 8:0] x;
reg [ 7:0] y;
reg [ 8:0] xmax;
reg [ 7:0] ymax;
reg [ 8:0] xoffset;
reg [ 7:0] yoffset;
reg [3:0] todraw, DrawState;
reg next, startdraw, donedraw;
reg [7:0] delayCnt;
wire [7:0] w;
//gradient 8bit
/*
ROM65536x24 (.address(address),.clock(CLOCK_50),.q(data));
*/
// Gradient Picture 4bit
//ROM65536x12 (.address(address),.clock(CLOCK_50),.q(data));
//gradient 3bit
/*
ROM65536x3 (.address(address),.clock(CLOCK_50),.q(data));
*/
ROM256x12TEST(
.address(address), .clock(CLOCK_50), .q(data)
);
localparam BG = 4'b0001, BGwait = 4'b0010,
Draw1 = 4'b0011 , Draw1wait = 4'b0100,
Justwait = 4'b1101;
localparam Background = 4'b0001, Item1 = 4'b0010;
initial begin
address <= 17'd0;
DrawState <= BG;
donedraw <= 0;
next <= 0;
startdraw <= 0;
x = 0;
y = 0;
end
reg setdraw;
always @(posedge CLOCK_50) begin : drawingstate
case (DrawState)
BG: begin
setdraw <= 1;
startdraw <= 0;
todraw <= Background;
if (next == 1) DrawState <= BGwait;
end
BGwait: begin
setdraw <= 0;
startdraw <= 1;
if (donedraw == 2) DrawState <= Draw1;
end
Draw1: begin
setdraw <= 1;
todraw = Item1;
startdraw <= 0;
if (next == 1) DrawState <= Draw1wait;
end
Draw1wait: begin
setdraw <= 0;
startdraw <= 1;
if (donedraw == 1) begin
DrawState <= Justwait;
end
end
Justwait: begin
startdraw <= 0;
DrawState <= BG;
end
endcase
end
// whats going on here kevin??
or (w[2], setdraw, next);
and (w[1], w[2], CLOCK_50);
always @(posedge w[1]) begin : drawsetter
if (setdraw == 0) next <= 0;
else begin
case (todraw)
Background: begin
xoffset <= 0;
yoffset <= 0;
xmax <= 9'd320;
ymax <= 8'd240;
next <= 1;
end
Item1: begin
xoffset = xoffsetset;
yoffset = yoffsetset;
xmax = 9'd15 + xoffset;
ymax = 8'd15 + yoffset;
next = 1;
end
endcase
end
end
or (w[3], startdraw, donedraw);
and (w[0], w[3], CLOCK_50);
always @(posedge w[0]) begin : imagesetter
if (startdraw == 0) donedraw <= 0;
else begin
address <= 0;
donedraw <= 0;
case (x)
xmax: begin
if (y == ymax) begin
donedraw <= donedraw + 1;
address <= 0;
end else begin
x <= xoffset;
y <= y + 1;
address <= address + 1;
end
end
default: begin
if (address == 0) begin
x <= xoffset;
y <= yoffset;
address <= address + 1;
end else begin
address <= address + 1;
x <= x + 1;
y <= y + 0;
end
end
endcase
end
end
always @(*) begin : dataset
case (todraw)
Background: begin
colour <= 12'b100010000100;
end
Item1: begin
colour <= data;
end
endcase
end
vga_adapter VGA0 (
.resetn(KEY[0]),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(KEY[2]),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA0.RESOLUTION = "320x240"; defparam VGA0.MONOCHROME = "FALSE";
defparam VGA0.BITS_PER_COLOUR_CHANNEL = 4; defparam VGA0.BACKGROUND_IMAGE = "black.mif";
endmodule
| 6.72565 |
module for sdram to keep the data in capacitors
for every 64ms all units need to be refreshed. (15us between each refreshing process)
*/
module autorefresh (
//system input signals
input sys_clk,
input sys_rst,
//communication with top level entity (arbit)
input ref_en,
output wire ref_req,
output reg ref_end_flag,
//output to the port and communicate with sdram chip
output reg [3:0] ref_cmd,
output wire [11:0] ref_addr,
//communication bewteen this module and the initiallization module(it shall send autofresh request after initiallization completed
input init_end_flag
);
//===========================================================================
// parameter define
//===========================================================================
//parameter define
localparam DELAY_15US = 10'd750;
localparam CMD_AUTOREFRESH = 4'b0001;
localparam CMD_NOP = 4'b0111;
localparam CMD_PRECHARGE = 4'b0010;
//reg define
reg [3:0] cmd_cnt;
reg [9:0] ref_cnt;
reg flag_ref;
//wire define
//===========================================================================
// main code
//===========================================================================
assign ref_req = (ref_cnt >= DELAY_15US)? 1'b1: 1'b0;
assign ref_addr = 12'b 0100_0000_0000;
//a counter to count how many clk period has passed. for every 15us an autorefresh request will be sent after initiallization
always @(posedge sys_clk or negedge sys_rst)begin
if(!sys_rst)begin
ref_cnt <= 10'd0;
end
else if (ref_cnt >= DELAY_15US)begin
ref_cnt <= 10'd0;
end
else if (init_end_flag == 1'b1)begin
ref_cnt <= ref_cnt + 1;
end
//maybe delete this else structure? or let ref_cnt <= ref_cnt?
else begin
ref_cnt <= 10'd0;
end
//maybe delete this else structure? or let ref_cnt <= ref_cnt?
end
//define a flag signal and indicates that the chip is being refreshed when the signal is 1
//when the ref_end_flag is 1 then the refreshing procedure is stopped then set the signal as 0
//the refreshing precedure needs to be engaged by the ref_en signal
always @(posedge sys_clk or negedge sys_rst)begin
if(!sys_rst) begin
flag_ref <= 1'b0;
end
else if(ref_end_flag == 1'b1)begin //after initiallization
flag_ref <= 1'b0;
end
else if(ref_en == 1'b1) begin
flag_ref <= 1'b1;
end
else begin
flag_ref <= 1'b0;
end
end
//set a counter to count how many clks are passed after working procedure intiallized.
always @(posedge sys_clk or negedge sys_rst)begin
if(!sys_rst)begin
cmd_cnt <= 4'd0;
end
else if(flag_ref == 1'b1) begin
cmd_cnt <= cmd_cnt + 1;
end
else begin
cmd_cnt <= 4'd0;
end
end
//output different instructions in different cmd_cnt periods to implement a complete refreshing procedure
always @(posedge sys_clk or negedge sys_rst)begin
if(!sys_rst)begin
ref_cmd <= 4'b0;
end
else
case (cmd_cnt)
4'd1: ref_cmd <= CMD_PRECHARGE;
4'd2: ref_cmd <= CMD_AUTOREFRESH;
default: ref_cmd <= CMD_NOP;
endcase
end
endmodule
| 7.11804 |
module autoref_config (
input clk,
input rst,
input set_interval,
input [27:0] interval_in,
input set_trfc,
input [27:0] trfc_in,
output reg aref_en,
output reg [27:0] aref_interval,
output reg [27:0] trfc
);
always @(posedge clk) begin
if (rst) begin
aref_en <= 0;
aref_interval <= 0;
trfc <= 0;
end else begin
if (set_interval) begin
aref_en <= |interval_in;
aref_interval <= interval_in;
end //set_interval
if (set_trfc) begin
trfc <= trfc_in;
end
end
end
endmodule
| 6.508465 |
module implements the autorepeat function with 500ms initial time to start the repeat
function and 300ms repeat interval. Time is counted in units of the period of clken100hz
signal.
------------------------------------------------------------
Revision history:
- Dec 21, 2005 - First release, jca (jca@fe.up.pt)
- Jul 27. 2017 - Master clock changed to 100MHz, AJA
------------------------------------------------------------
*/
`timescale 1ns/100ps
module autorepeat
( clock, // master clock (100MHz)
reset, // master reset, assynchronous, active high
clken, // clock enable signal, 100Hz, used as time base
rpten, // enable repeat function
keyin, // connects to the debounced key input
keyout // output signal with autorepeat
);
// *2 pq clock tem agora o dobro da frequncia...
parameter START_TIME = 2*600/10*3, // miliseconds / 10ms (mul by 3 for clkenable = 250Hz )
REPEAT_TIME = 2*200/10*3;
input clock, reset;
input rpten;
input clken;
input keyin;
output keyout;
reg keyout;
// timer for the autorepeat function: counting is enabled by clken100hz
reg [7:0] timer;
// state for the autorepeat FSM
reg [2:0] state;
reg resettimer;
reg keypressed;
// control FSM:
always @(posedge clock or posedge reset)
begin
if ( reset )
begin
state = 0;
keypressed = 0;
resettimer = 0;
keyout = 0;
end
else
begin
keyout = 0;
resettimer = 0;
case ( state )
0: begin // startup state: wait any key and reset timer
resettimer = 1;
if ( keyin ) // key after debounce
state = 1;
else
state = 0;
end
1: begin
keyout = 1;
state = 2;
end
2: begin
keyout = 0;
if ( keyin )
begin
if ( rpten )
begin
if ( keypressed ? (timer==REPEAT_TIME) : (timer==START_TIME) )
begin
keypressed = 1;
state = 0;
end
else
begin
state = 2;
end
end
else
state = 2; // keep here until key is released
end
else
begin
keypressed = 0;
state = 0;
end
end
default: state = 0;
endcase
end
end
// timer for autorepeat function: counts units of 10ms
always @(posedge clock or posedge reset)
begin
if ( reset )
timer = 0;
else
begin
begin
if ( resettimer )
begin
timer = 0;
end
else
begin
if ( clken )
timer = timer + 1'b1;
end
end
end
end
endmodule
| 7.842559 |
module auto_add_tb ();
reg clk, rst, start;
wire DONE;
wire [31:0] sum_out;
auto_add dut (
clk,
rst,
start,
DONE,
sum_out
);
initial clk = 0;
always #10 clk = ~clk;
initial begin
rst <= 1;
start <= 0;
#15 rst <= 0;
#5 start <= 1;
#105 start <= 0;
// @(posedge clk); //һʱ
// #5 if (LD_SUM != 0) //ӳ5ns֤λǷɹ
// $display("%t: Reset failed", $time);
end
endmodule
| 6.508501 |
module Auto_Cal #(
parameter DATA_WIDTH = 8
) (
start,
rst,
clk,
done,
sum_out
);
input start;
input rst;
input clk;
output wire done;
output wire [DATA_WIDTH-1:0] sum_out;
wire NEXT_ZERO, LD_SUM, LD_NEXT, SUM_SEL, NEXT_SEL, A_SEL;
FSM control (
clk,
rst,
start,
NEXT_ZERO,
LD_SUM,
LD_NEXT,
SUM_SEL,
NEXT_SEL,
A_SEL,
done
);
data_path #(DATA_WIDTH) dp (
clk,
rst,
SUM_SEL,
NEXT_SEL,
A_SEL,
LD_SUM,
LD_NEXT,
NEXT_ZERO,
sum_out
);
endmodule
| 7.196357 |
module Auto_Cal_tb ();
parameter DATA_WIDTH = 32;
reg start;
reg rst;
reg clk;
wire done;
wire [DATA_WIDTH-1:0] sum_out;
initial begin
start = 0;
rst = 0;
clk = 0;
end
always begin
#10 clk = ~clk;
end
always begin
#100 start = 1;
#400 start = 0;
end
Auto_Cal #(DATA_WIDTH) tb (
start,
rst,
clk,
done,
sum_out
);
endmodule
| 6.786519 |
module auto_low_freq_counter (
input wire clk,
reset,
input wire start,
si,
output wire [3:0] bcd3,
bcd2,
bcd1,
bcd0,
output wire [1:0] decimal_counter
);
// symbolic state declaration
localparam [2:0] idle = 3'b000, count = 3'b001, frq = 3'b010, b2b = 3'b011, adj = 3'b100;
// signal declaration
reg [2:0] state_reg, state_next;
wire [19:0] prd;
wire [29:0] dvsr, dvnd, quo;
reg prd_start, div_start, b2b_start, adj_start;
wire prd_done_tick, div_done_tick, b2b_done_tick, adj_done_tick;
wire [3:0] bcd_tmp6, bcd_tmp5, bcd_tmp4, bcd_tmp3, bcd_tmp2, bcd_tmp1, bcd_tmp0;
//==========================================
// component instantiation
//==========================================
// instantiate period counter
period_counter prd_count_unit (
.clk(clk),
.reset(reset),
.start(prd_start),
.si(si),
.ready(),
.done_tick(prd_done_tick),
.prd(prd)
);
// instantiate division circuit
div #(
.W(30),
.CBIT(5)
) div_unit (
.clk(clk),
.reset(reset),
.start(div_start),
.dvsr(dvsr),
.dvnd(dvnd),
.quo(quo),
.rmd(),
.ready(),
.done_tick(div_done_tick)
);
// instantiate binary-to-BCD converter
bin2bcd b2b_unit (
.clk(clk),
.reset(reset),
.start(b2b_start),
.bin(quo[24:0]),
.ready(),
.done_tick(b2b_done_tick),
.bcd6(bcd_tmp6),
.bcd5(bcd_tmp5),
.bcd4(bcd_tmp4),
.bcd3(bcd_tmp3),
.bcd2(bcd_tmp2),
.bcd1(bcd_tmp1),
.bcd0(bcd_tmp0)
);
// instance of bcd adjust circuit
bcd_adjust adj_unit (
.clk(clk),
.reset(reset),
.start(adj_start),
.bcd6(bcd_tmp6),
.bcd5(bcd_tmp5),
.bcd4(bcd_tmp4),
.bcd3(bcd_tmp3),
.bcd2(bcd_tmp2),
.bcd1(bcd_tmp1),
.bcd0(bcd_tmp0),
.bcd_out3(bcd3),
.bcd_out2(bcd2),
.bcd_out1(bcd1),
.bcd_out0(bcd0),
.decimal_counter(decimal_counter),
.done_tick(adj_done_tick),
.ready()
);
// signal width extension
assign dvnd = 30'd1_000_000_000;
assign dvsr = {10'b0, prd};
//==========================================
// master FSM
//==========================================
always @(posedge clk, posedge reset)
if (reset) state_reg <= idle;
else state_reg <= state_next;
always @* begin
state_next = state_reg;
prd_start = 1'b0;
div_start = 1'b0;
b2b_start = 1'b0;
adj_start = 1'b0;
case (state_reg)
idle:
if (start) begin
prd_start = 1'b1;
state_next = count;
end
count:
if (prd_done_tick) begin
div_start = 1'b1;
state_next = frq;
end
frq:
if (div_done_tick) begin
b2b_start = 1'b1;
state_next = b2b;
end
b2b:
if (b2b_done_tick) begin
adj_start = 1'b1;
state_next = adj;
end
adj: if (adj_done_tick) state_next = idle;
endcase
end
endmodule
| 8.320934 |
module auto_low_freq_counter_tb;
// signal declaration
localparam T = 10; // clk period
reg clk, reset;
reg start;
reg si1, si2, si3; // test signals
reg [1:0] sel;
localparam cnt1 = 11_000;
localparam cnt2 = 300_000;
localparam cnt3 = 17_000_000;
wire si;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
wire [1:0] decimal_counter;
// instance of uut
auto_low_freq_counter uut (
.clk(clk),
.reset(reset),
.start(start),
.si(si),
.bcd3(bcd3),
.bcd2(bcd2),
.bcd1(bcd1),
.bcd0(bcd0),
.decimal_counter(decimal_counter)
);
// selection of input source
assign si = (sel == 0) ? si1 : (sel == 1) ? si2 : (sel == 2) ? si3 : 1'bx;
// clock
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
// reset
initial begin
reset = 1'b1;
#(T / 2);
reset = 1'b0;
end
// signal one: 0.11 ms period => 9090.91Hz
always begin
si1 = 1'b0;
#(cnt1 * T);
si1 = 1'b1;
#T;
end
// signal two: 3 ms period => 333.333Hz
always begin
si2 = 1'b0;
#(cnt2 * T);
si2 = 1'b1;
#T;
end
// signal three: 170 ms period => 5.88235Hz
always begin
si3 = 1'b0;
#(cnt3 * T);
si3 = 1'b1;
#T;
end
// test vector
initial begin
repeat (5) @(negedge clk); // wait a few clocks
// signal 1
sel = 0;
start = 1;
repeat (5) @(negedge clk); // wait a few clocks
start = 0;
#(cnt1 * T * 3); // wait 2 cycles
repeat (5) @(negedge clk); // wait a few clocks
// signal 2
sel = 1;
start = 1;
repeat (5) @(negedge clk); // wait a few clocks
start = 0;
#(cnt2 * T * 3); // wait 2 cycles
repeat (5) @(negedge clk); // wait a few clocks
// signal 3
sel = 2;
start = 1;
repeat (5) @(negedge clk); // wait a few clocks
start = 0;
#(cnt3 * T * 3); // wait 2 cycles
repeat (5) @(negedge clk); // wait a few clocks
$stop;
end
endmodule
| 8.320934 |
module auto_low_freq_counter_test (
input wire clk,
reset,
input wire btn,
input wire [2:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire start;
reg si;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
wire [1:0] decimal_counter;
reg [3:0] dp_in;
//=============================================
// generate a tick with variable period
//=============================================
localparam N = 27; // number of counter bits to fit 1s
reg [N-1:0] q_next = 0, q_reg = 0;
always @(posedge clk) q_reg <= q_next;
always @* begin
q_next = q_reg + 1;
si = 1'b0;
case (sw)
// 0.11 ms period => 9090.91 Hz
// 1 ms period
3'b000:
if (q_reg == 11_000) begin
si = 1'b1;
q_next = 0;
end
// 0.2 ms period => 5000 Hz
3'b001:
if (q_reg == 20_000) begin
si = 1'b1;
q_next = 0;
end
// 1 ms period => 1000 Hz
3'b010:
if (q_reg == 100_000) begin
si = 1'b1;
q_next = 0;
end
// 3 ms period => 333.3333 Hz
3'b011:
if (q_reg == 300_000) begin
si = 1'b1;
q_next = 0;
end
// 60 ms period => 16.6666 Hz
3'b100:
if (q_reg == 6_000_000) begin
si = 1'b1;
q_next = 0;
end
// 170 ms period => 5.88235 Hz
3'b101:
if (q_reg == 17_000_000) begin
si = 1'b1;
q_next = 0;
end
// 760 ms period => 1.315789 Hz
3'b110:
if (q_reg == 76_000_000) begin
si = 1'b1;
q_next = 0;
end
// 1s period => 1 Hz
3'b111:
if (q_reg == 100_000_000) begin
si = 1'b1;
q_next = 0;
end
endcase
end
//=============================================
// Submodules
//=============================================
// instance of debouncer
debounce db_unit (
.clk(clk),
.reset(reset),
.sw(btn),
.db_level(),
.db_tick(start)
);
// instance of low freq counter
auto_low_freq_counter freq_counter_unit (
.clk(clk),
.reset(reset),
.start(start),
.si(si),
.bcd3(bcd3),
.bcd2(bcd2),
.bcd1(bcd1),
.bcd0(bcd0),
.decimal_counter(decimal_counter)
);
// instance of display unit
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.dp_in(dp_in),
.hex3(bcd3),
.hex2(bcd2),
.hex1(bcd1),
.hex0(bcd0),
.an(an),
.sseg(sseg)
);
// decimal counter to dp in circuit
always @* begin
case (decimal_counter)
0: dp_in = 4'b1111;
1: dp_in = 4'b1101;
2: dp_in = 4'b1011;
default: dp_in = 4'b0111; // case 3
endcase
end
endmodule
| 8.320934 |
module auto_range (
input clk,
input rst,
input ready,
input max_result_valid,
input [ 4:0] vga_in,
input [15:0] auto_upper,
input [15:0] auto_lower,
input [15:0] signal_max_a,
input [15:0] signal_max_b,
input [15:0] signal_max_c,
input [15:0] signal_max_d,
output reg [4:0] auto_att_reg
);
//parameter upper_threshold = 25000; // Full range of amplitude is 32768
//parameter lower_threshold = 15000; // Lower threshold roughly 3 dB less than upper threshold
parameter data_width = 16;
parameter step = 2;
parameter max = 30;
reg [data_width-1:0] signal_max_all;
always @(posedge clk) begin
/* Reset parameters by maxing out attenuation */
if (rst) begin
auto_att_reg <= max;
end
/* Otherwise check for position ready flag and begin processing */
else if (ready && max_result_valid) begin
signal_max_all <= signal_max_a; ///< Initialize signal_max_all as signal_max_a
/* Comparatively loads the maximum signal from rest of the channels */
if (signal_max_b[15:0] > signal_max_all) signal_max_all <= signal_max_b;
if (signal_max_c[15:0] > signal_max_all) signal_max_all <= signal_max_c;
if (signal_max_d[15:0] > signal_max_all) signal_max_all <= signal_max_d;
/* Lower or increase VGA attenuation depending on signal_max_all relative to the corresponding thresholds */
if (signal_max_all > auto_upper) begin
if (vga_in < max) auto_att_reg <= vga_in + step;
end else if (signal_max_all < auto_lower) begin
if (vga_in >= step) auto_att_reg <= vga_in - step;
end
end
end
endmodule
| 7.572046 |
module top (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/ir.py:329" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *) (* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "nmigen/hdl/ir.py:329" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk) reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1: \$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1: \$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.782499 |
module auto_tb ();
reg clk = 0;
reg [15:0] a_operand;
reg [15:0] b_operand;
wire Exception, Overflow, Underflow;
wire [15:0] result;
reg [15:0] Expected_result;
reg [95:0] testVector[`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;
BF16mul DUT (
a_operand,
b_operand,
Exception,
Overflow,
Underflow,
result
);
always #5 clk = ~clk;
initial begin
$readmemh(
"/home/ankita/Documents/v_files/Bfloat16/BF16mul/FP16.srcs/sim_1/new/TestVectorMultiply",
testVector);
mcd = $fopen("Results_Ver2.txt", "w");
end
always @(posedge clk) begin
{a_operand, b_operand, Expected_result} = testVector[test_n];
test_n = test_n + 1'b1;
#2;
if (result == Expected_result) begin
$fdisplay(mcd, "TestPassed Test Number -> %d", test_n);
pass = pass + 1'b1;
end
if (result != Expected_result) begin
$fdisplay(mcd, "Test Failed Expected Result = %h, Obtained result = %h, Test Number -> %d",
Expected_result, result, test_n);
error = error + 1'b1;
end
if (test_n >= `N_TESTS) begin
$fdisplay(mcd, "Completed %d tests, %d passes and %d fails.", test_n, pass, error);
test_stop_enable = 1'b1;
end
end
always @(posedge clk) begin
if (test_stop_enable == 1'b1) begin
$fclose(mcd);
$finish;
end
end
endmodule
| 6.595049 |
module Auto_Write_Read #(
parameter WR_RD_DATA = 'd256
) (
input clk, //
input rst_n,
//wfifo signal
input wfifo_wclk,
input wfifo_wr_en,
input [15:0] wfifo_wr_data,
input wfifo_rclk,
input wfifo_rd_en,
output [15:0] wfifo_rd_data,
output reg wr_trig,
//rfifo signal
input rfifo_wclk,
input rfifo_wr_en,
input [15:0] rfifo_wr_data,
input rfifo_rclk,
input rfifo_rd_en,
output [15:0] rfifo_rd_data,
output rd_trig,
output reg rfifo_rd_ready
);
wire [8:0] wfifo_wrusedw;
//wire [8:0] wfifo_rdusedw;
wire [8:0] rfifo_wrusedw;
//wire [8:0] rfifo_rdusedw;
reg rfifo_wr_valid;
/*
always @(posedge wfifo_wclk or negedge rst_n)begin
if(rst_n == 1'b0)
wr_trig <= 1'b0;
else if(wfifo_wrusedw > WR_RD_DATA - 1'b1)
wr_trig <= 1'b1;
else
wr_trig <= 1'b0;
end
always @(posedge rfifo_wclk or negedge rst_n)begin
if(rst_n == 1'b0)
rd_trig_r <= 1'b0;
else if(rfifo_wrusedw < WR_RD_DATA - 1'b1 && rfifo_wr_valid == 1'b1)
rd_trig_r <= 1'b1;
else
rd_trig_r <= 1'b0;
end
*/
reg rd_trig_r;
reg rd_trig_r1;
always @(posedge rfifo_wclk or negedge rst_n) begin
if (rst_n == 1'b0) begin
wr_trig <= 1'b0;
rd_trig_r <= 1'b0;
end else if (wfifo_wrusedw > WR_RD_DATA - 1'b1) begin
wr_trig <= 1'b1;
rd_trig_r <= 1'b0;
end else if (rfifo_wrusedw < WR_RD_DATA - 1'b1 && rfifo_wr_valid == 1'b1) begin
rd_trig_r <= 1'b1;
wr_trig <= 1'b0;
end else begin
wr_trig <= 0;
rd_trig_r <= 0;
end
end
always @(posedge rfifo_wclk) begin
rd_trig_r1 <= rd_trig_r;
end
assign rd_trig = rd_trig_r & ~rd_trig_r1;
reg rd_trig_flag;
always @(posedge rfifo_wclk or negedge rst_n) begin
if (rst_n == 1'b0) rd_trig_flag <= 1'b0;
else if (rd_trig == 1'b1) rd_trig_flag <= 1'b1;
end
always @(posedge rfifo_wclk or negedge rst_n) begin
if (rst_n == 1'b0) rfifo_wr_valid <= 1'b0;
else if (wr_trig == 1'b1) rfifo_wr_valid <= 1'b1;
else rfifo_wr_valid <= rfifo_wr_valid;
end
reg [1:0] rfifo_wr_en_r;
always @(posedge rfifo_wclk or negedge rst_n) begin
if (!rst_n) rfifo_wr_en_r <= 2'b0;
else rfifo_wr_en_r <= {rfifo_wr_en_r[0], rfifo_wr_en};
end
wire rfifo_wr_en_nedge = ~rfifo_wr_en_r[0] & rfifo_wr_en_r[1];
always @(posedge rfifo_wclk or negedge rst_n) begin
if (rst_n == 1'b0) rfifo_rd_ready <= 1'b0;
else if (rd_trig_flag == 1'b1 && rfifo_wrusedw > WR_RD_DATA - 1) rfifo_rd_ready <= 1'b1;
else rfifo_rd_ready <= rfifo_rd_ready;
end
//-------------------------------------------------------
//wfifo_16x512
dfifo_16x512 wfifo_16x512_inst (
.data (wfifo_wr_data),
.rdclk (wfifo_rclk),
.rdreq (wfifo_rd_en),
.wrclk (wfifo_wclk),
.wrreq (wfifo_wr_en),
.q (wfifo_rd_data),
.rdusedw(),
.wrusedw(wfifo_wrusedw)
);
//-------------------------------------------------------
//rfifo_16x512
dfifo_16x512 rfifo_16x512_inst (
.data (rfifo_wr_data),
.rdclk (rfifo_rclk),
.rdreq (rfifo_rd_en),
.wrclk (rfifo_wclk),
.wrreq (rfifo_wr_en),
.q (rfifo_rd_data),
.rdusedw(),
.wrusedw(rfifo_wrusedw)
);
endmodule
| 6.76176 |
module auxControl (
input [2:0] branch,
input [1:0] jump,
input zero,
input sgn,
input [31:0] pcimm,
input [31:0] aluc,
output reg npc_op,
output reg [31:0] npc_bj
);
always @(*) begin
if (jump[0] == 1'b1) npc_op = 1'b1; // jal or jalr
else if (branch[0] == 1'b1) begin
case (branch[2:1])
2'b00: npc_op = zero ? 1'b1 : 1'b0; // beq
2'b01: npc_op = zero ? 1'b0 : 1'b1; // bne
2'b10: npc_op = sgn ? 1'b1 : 1'b0; // blt
2'b11: npc_op = sgn ? 1'b0 : 1'b1; // bge
endcase
end else npc_op = 1'b0;
end
always @(*) begin
if (jump == 2'b01) npc_bj = {aluc[31:1], 1'b0}; // jalr
else if (jump == 2'b11) npc_bj = pcimm; // jal
else npc_bj = pcimm; // otherwise
end
endmodule
| 7.400879 |
module AuxCounter (
clk,
rst_n,
en,
ld,
val,
cnt
);
parameter CntBit = 32;
input clk;
input rst_n;
input en;
input ld;
input [CntBit - 1:0] val;
output reg [CntBit - 1:0] cnt;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) cnt <= 'd0;
else if (ld) cnt <= val;
else if (en) cnt <= cnt + 'd1;
end
endmodule
| 6.633945 |
module auxdec (
input wire [1:0] alu_op,
input wire [5:0] funct,
output wire [3:0] alu_ctrl,
output wire [1:0] hilo_mux_ctrl,
output wire hilo_we,
output wire jr_mux_ctrl
);
reg [7:0] ctrl;
assign {alu_ctrl, hilo_mux_ctrl, hilo_we, jr_mux_ctrl} = ctrl;
always @(alu_op, funct) begin
case (alu_op)
2'b00: ctrl = 8'b0010_00_0_0; // ADD
2'b01: ctrl = 8'b0110_00_0_0; // SUB
default:
case (funct)
6'b10_0100: ctrl = 8'b0000_00_0_0; // AND
6'b10_0101: ctrl = 8'b0001_00_0_0; // OR
6'b10_0000: ctrl = 8'b0010_00_0_0; // ADD
6'b10_0010: ctrl = 8'b0110_00_0_0; // SUB
6'b10_1010: ctrl = 8'b0111_00_0_0; // SLT
6'b01_1001: ctrl = 8'b1000_00_1_0; // MULTU
6'b01_0000: ctrl = 8'b0000_11_0_0; // MFHI
6'b01_0010: ctrl = 8'b0000_01_0_0; // MFLO
6'b00_0000: ctrl = 8'b1001_00_0_0; // SLL
6'b00_0010: ctrl = 8'b1010_00_0_0; // SRL
6'b00_1000: ctrl = 8'b0000_00_0_1; // JR
default: ctrl = 8'bxxxx_xx_x_x;
endcase
endcase
end
endmodule
| 6.543732 |
module auxiliary_arc (
input clk,
input rst,
input rst_n,
output [`RV_BIT_NUM_DIVIV_NUM-1:0] aux_mem_keep,
output [`RV_BIT_NUM-1:0] aux_mem_datai,
output [`RV_BIT_NUM-1:0] aux_mem_addr,
input [`RV_BIT_NUM-1:0] aux_mem_datao,
input [`RV_BIT_NUM-1:0] aux_start_addr,
input aux_en,
output reg aux_done
);
always @(posedge clk) begin
if (rst_n == 0) begin
aux_done <= 0;
end else begin
if (aux_en == 1) begin
aux_done <= 1;
end else begin
aux_done <= 0;
end
end
end
endmodule
| 6.772793 |
module to handle delay of signals by a certain number of cycles
// LOG should be log2(CYCLES) rounded up
module pipeliner #(parameter CYCLES=1, parameter LOG=1, parameter WIDTH = 1)
(input reset,
input clock,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out);
reg [WIDTH-1:0] buffer [CYCLES-1:0];
reg [LOG-1:0] i; //pointer to next output
always @(posedge clock) begin
if (reset) begin //reset
//clear buffer
for (i = 0; i < CYCLES; i = i+1) begin
buffer[i] <= 0;
end
//reset pointer
i <= 0;
//reset output
out <= 0;
end
//otherwise (normal operation)
else begin
//shift output out
out <= buffer[i];
//increment counter
if (i == CYCLES-1) begin
i <= 0;
end
else begin
i <= i + 1;
end
//shift input in
buffer[i] <= in;
end
end
endmodule
| 6.570521 |
module binary_to_bcd #(
parameter LOG = 3,
WIDTH = 8,
WAIT = 0,
CALC = 1,
SHIFT = 0,
ADD = 1
) (
input [WIDTH-1:0] bin,
input clock,
output reg [4*LOG-1:0] out = 0
);
reg count = 0;
reg [WIDTH+4*LOG-1:0] calc = 0;
reg state = WAIT;
reg int_state = SHIFT;
integer i = 0;
wire new_num;
wire new_pulse;
reg [WIDTH-1:0] last_num = 0;
assign new_num = |(last_num ^ bin);
pulse2 new_p (
.clock(clock),
.signal(new_num),
.out(new_pulse)
);
always @(posedge clock) begin
case (state)
WAIT: begin
count <= 0;
if (new_pulse) begin
calc <= bin;
state <= CALC;
last_num <= bin;
end
end
CALC: begin
if (new_pulse) begin
calc <= bin;
last_num <= bin;
count <= 0;
end else if (count < WIDTH) begin
if (int_state == SHIFT) begin
calc <= calc << 1;
int_state <= ADD;
end else if (int_state == ADD) begin
for (i = 0; i < LOG; i = i + 1) begin
if (calc[WIDTH+i*4+:4] > 4) begin
calc[WIDTH+i*4+:4] <= calc[WIDTH+i*4+:4] + 3;
end
end
count <= count + 1;
int_state <= SHIFT;
end
end else begin
out <= calc[WIDTH+:4*LOG];
state <= WAIT;
end
end
endcase
end
endmodule
| 8.011872 |
module pulse (
input clock,
signal,
output reg out
);
reg state = 0;
always @(posedge clock) begin
state <= signal;
if (out) out <= 0;
else out <= signal & ~state;
end
endmodule
| 6.570181 |
module pulse2 (
input clock,
signal,
output reg out
);
reg state = 0;
reg count = 0;
always @(posedge clock) begin
state <= signal;
if (out) begin
if (count == 0) begin
count <= count + 1;
end else begin
out <= 0;
count <= 0;
end
end else out <= signal & ~state;
end
endmodule
| 6.524618 |
module auxillary_memory (
clk,
rst,
cmd_in,
addr_in,
data_in,
data_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter dw = `DATA_WIDTH;
parameter aw = `ADDR_WIDTH;
parameter sw = `SCAN_WIDTH;
parameter tasw = `ADDR_WIDTH;
parameter tcsw = `MARCH_SEQ_FRMT_SIZE;
parameter tdsw = `DATA_WIDTH;
//-----------------------------------------------
// Input/Output Signals
//-----------------------------------------------
input clk;
input rst;
input [tcsw-1:0] cmd_in;
input [tasw-1:0] addr_in;
input [tdsw-1:0] data_in;
output [tdsw-1:0] data_out;
//-----------------------------------------------
// Internal Signals
//-----------------------------------------------
//***********************************************
// Module definition
//***********************************************
blk_mem_8x256 mem_8x256 (
.clka (clk),
.rsta (rst),
.wea (cmd_in[0]),
.addra(addr_in),
.dina (data_in),
.douta(data_out)
);
endmodule
| 8.106877 |
modules here...
// DeBounce_v.v
//////////////////////// Button Debounceer ///////////////////////////////////////
//***********************************************************************
// FileName: DeBounce_v.v
// FPGA: MachXO2 7000HE
// IDE: Diamond 2.0.1
//
// HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
// WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
// BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
// DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
// PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
// BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
// ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
// DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
// INFRINGEMENT.
//
// Version History
// Version 1.0 04/11/2013 Tony Storey
// Initial Public Release
// Small Footprint Button Debouncer
/*module DeBounce
(
input clk, n_reset, button_in, // inputs
output reg DB_out // output
);
//// ---------------- internal constants --------------
parameter N = 11 ; // (2^ (21-1) )/ 38 MHz = 32 ms debounce time
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg; // timing regs
reg [N-1 : 0] q_next;
reg DFF1, DFF2; // input flip-flops
wire q_add; // control flags
wire q_reset;
//// ------------------------------------------------------
////contenious assignment for counter control
assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level chage to reset counter
assign q_add = ~(q_reg[N-1]); // add to counter when q_reg msb is equal to 0
//// combo counter to manage q_next
always @ ( q_reset, q_add, q_reg)
begin
case( {q_reset , q_add})
2'b00 :
q_next <= q_reg;
2'b01 :
q_next <= q_reg + 1;
default :
q_next <= { N {1'b0} };
endcase
end
//// Flip flop inputs and q_reg update
always @ ( posedge clk )
begin
if(n_reset == 1'b0)
begin
DFF1 <= 1'b0;
DFF2 <= 1'b0;
q_reg <= { N {1'b0} };
end
else
begin
DFF1 <= button_in;
DFF2 <= DFF1;
q_reg <= q_next;
end
end
//// counter control
always @ ( posedge clk )
begin
if(q_reg[N-1] == 1'b1)
DB_out <= DFF2;
else
DB_out <= DB_out;
end
endmodule
| 8.990348 |
module SSeg (
input [3:0] bin,
input neg,
input enable,
output reg [6:0] segs
);
always @(*)
if (enable) begin
if (neg) segs = 7'b011_1111;
else begin
case (bin)
0: segs = 7'b100_0000;
1: segs = 7'b111_1001;
2: segs = 7'b010_0100;
3: segs = 7'b011_0000;
4: segs = 7'b001_1001;
5: segs = 7'b001_0010;
6: segs = 7'b000_0010;
7: segs = 7'b111_1000;
8: segs = 7'b000_0000;
9: segs = 7'b001_1000;
10: segs = 7'b000_1000;
11: segs = 7'b000_0011;
12: segs = 7'b100_0110;
13: segs = 7'b010_0001;
14: segs = 7'b000_0110;
15: segs = 7'b000_1110;
endcase
end
end else segs = 7'b111_1111;
endmodule
| 7.166491 |
module Disp2cNum (
input signed [7:0] x,
input enable,
output [6:0] H3,
H2,
H1,
H0 /*, output [7:0] xo0_check,xo1_check,xo2_check,xo3_check*/
);
wire neg = (x < 0);
wire [7:0] ux = neg ? -x : x;
wire [7:0] xo0, xo1, xo2, xo3;
wire eno0, eno1, eno2, eno3;
DispDec h0 (
ux,
neg,
enable,
xo0,
eno0,
H0
);
DispDec h1 (
xo0,
neg,
eno0,
xo1,
eno1,
H1
);
DispDec h2 (
xo1,
neg,
eno1,
xo2,
eno2,
H2
);
DispDec h3 (
xo2,
neg,
eno2,
xo3,
eno3,
H3
);
//assign xo0_check = xo0;
//assign xo1_check = xo1;
//assign xo2_check = xo2;
//assign xo3_check = xo3;
endmodule
| 7.668752 |
module DispDec (
input [7:0] x,
input neg,
enable,
output reg [7:0] xo,
output reg eno,
output [6:0] segs
);
wire [3:0] digit;
wire n = (x == 1'b0 && neg == 1'b1) ? neg : 1'b0;
assign digit = x % 4'd10;
SSeg converter (
digit,
n,
enable,
segs
);
always @(x) begin
xo = x / 8'd10;
end
always @(x or neg or enable or segs) begin
if (x / 10 == 0 && neg == 0) eno = 0;
else eno = enable;
if (segs == 7'b011_1111) eno = 0;
//else eno = enable;
end
endmodule
| 7.957199 |
module DispHex (
input [7:0] value,
output [6:0] display0,
display1
);
SSeg sseg0 (
value[7:4],
0,
1,
display0
);
SSeg sseg1 (
value[3:0],
0,
1,
display1
);
endmodule
| 6.832901 |
module AUX_Run ();
integer i;
integer fd;
reg [7:0] a;
reg [14:0] b;
reg [23:0] addr;
always #1 a = a + 1;
always #1 b = b + 1;
always #1 addr = addr + 1;
wire [31:0] aout;
wire [31:0] bout;
AUX aux (
.AUX_A(a),
.AUX_B(b),
.AOut (aout),
.BOut (bout)
);
AUX_Dumper dump_a (
.addr(addr),
.val (aout)
);
AUX_Dumper dump_b (
.addr(addr),
.val (bout)
);
initial begin
$dumpfile("aux_test.vcd");
$dumpvars(0, a);
$dumpvars(1, b);
$dumpvars(2, aout);
$dumpvars(3, bout);
a <= 0;
b <= 0;
addr <= 0;
repeat (32769) @(b);
// Save to file
fd = $fopen("auxa_dump.bin", "wb");
for (i = 0; i < 16777216; i = i + 1) begin
$fwrite(fd, "%u", dump_a.mem[i]);
end
$fclose(fd);
fd = $fopen("auxb_dump.bin", "wb");
for (i = 0; i < 16777216; i = i + 1) begin
$fwrite(fd, "%u", dump_b.mem[i]);
end
$fclose(fd);
$finish;
end
endmodule
| 7.123427 |
module au_top (
input clk, // 100MHz clock
input rst_n, // reset button (active low)
output [ 7:0] led, // 8 user controllable LEDs
input usb_rx, // USB->Serial input
output usb_tx, // USB->Serial output,
input [ 4:0] io_button,
input [23:0] io_dip,
output [23:0] io_led,
output [ 7:0] io_seg,
output [ 3:0] io_sel
);
assign led = 8'h00; // turn LEDs off
assign usb_tx = usb_rx; // echo the serial data
arbiter my_arbiter (
.a(io_dip[23:0]),
.q(io_led[23:0])
);
endmodule
| 7.049401 |
module inicial01 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] d
);
wire [3:0] na, nb, w0, w1;
// descrever por portas
not not1[3:0] (na, a);
not not2[3:0] (nb, b);
and and1[3:0] (w1, nb, d);
or or1[3:0] (w0, na, nb);
or or1[3:0] (saida0, w1, na);
endmodule
| 6.692001 |
module inicial02 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] d
);
wire [3:0] nb;
// descrever por portas
not not1[3:0] (nb, b);
and and1[3:0] (s, a, nb, d);
endmodule
| 6.650573 |
module s0 (
output [3:0] saida0,
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d
);
wire [3:0] sinicial01, sinicial02;
// descrever por portas
and and1[3:0] (w1, a, sinicial01, c);
or or1[3:0] (saida0, w1, sinicial02);
endmodule
| 6.510634 |
module avalon2rcn (
input av_clk,
input av_rst,
output av_waitrequest,
input [21:0] av_address,
input av_write,
input av_read,
input [3:0] av_byteenable,
input [31:0] av_writedata,
output [31:0] av_readdata,
output av_readdatavalid,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter MASTER_ID = 6'h3F;
reg [68:0] rin;
reg [68:0] rout;
reg [ 2:0] next_rd_id;
reg [ 2:0] wait_rd_id;
reg [ 2:0] next_wr_id;
reg [ 2:0] wait_wr_id;
assign rcn_out = rout;
wire [5:0] my_id = MASTER_ID;
wire my_resp = rin[68] && !rin[67] && (rin[65:60] == my_id) &&
((rin[66]) ? (rin[33:32] == wait_wr_id[1:0]) : (rin[33:32] == wait_rd_id[1:0]));
wire bus_stall = (rin[68] && !my_resp) || ((av_read) ? (next_rd_id == wait_rd_id) : (next_wr_id == wait_wr_id));
assign av_waitrequest = bus_stall;
wire req_valid;
wire [68:0] req;
always @(posedge av_clk or posedge av_rst)
if (av_rst) begin
rin <= 69'd0;
rout <= 69'd0;
next_rd_id <= 3'b000;
wait_rd_id <= 3'b100;
next_wr_id <= 3'b000;
wait_wr_id <= 3'b100;
end else begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
next_rd_id <= (req_valid && av_read) ? next_rd_id + 3'd1 : next_rd_id;
wait_rd_id <= (my_resp && !rin[66]) ? wait_rd_id + 3'd1 : wait_rd_id;
next_wr_id <= (req_valid && av_write) ? next_wr_id + 3'd1 : next_wr_id;
wait_wr_id <= (my_resp && rin[66]) ? wait_wr_id + 3'd1 : wait_wr_id;
end
assign req_valid = (av_write || av_read) && !bus_stall;
wire [1:0] seq = (av_read) ? next_rd_id[1:0] : next_wr_id[1:0];
assign req = {1'b1, 1'b1, av_write, my_id, av_byteenable, av_address[21:0], seq, av_writedata};
assign av_readdatavalid = my_resp && !rin[66];
assign av_readdata = rin[31:0];
endmodule
| 7.394587 |
module avaloncontrol (
clk,
rst_n,
rd_n,
wr_n,
cs_n,
rddata,
wrdata,
addr,
code0,
code1,
code2,
code3,
set,
A,
B,
Z_OpenLoop,
Z_Brushless
);
input clk, rst_n, rd_n, wr_n, cs_n;
input [31:0] code0, code1, code2, code3, wrdata;
input [2:0] addr;
output [31:0] A, B, rddata, set;
output Z_OpenLoop, Z_Brushless;
reg [31:0] A, B, rddata, set;
reg Z_OpenLoop, Z_Brushless;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
A <= 32'd170;
B <= 32'd100;
rddata <= 32'd0;
set <= 32'd0;
Z_OpenLoop <= 1'b0;
Z_Brushless <= 1'b1;
end else begin
if (!wr_n && !cs_n) begin
if (addr == 3'b000) begin
A <= wrdata;
end else if (addr == 3'b001) begin
B <= wrdata;
end else if (addr == 3'b010) begin
set <= wrdata;
end else if (addr == 3'b011) begin
Z_OpenLoop <= wrdata[0];
end else if (addr == 3'b100) begin
Z_Brushless <= wrdata[0];
end else begin
A <= A;
B <= B;
set <= set;
Z_OpenLoop <= Z_OpenLoop;
Z_Brushless <= Z_Brushless;
end
end else if (!rd_n && !cs_n) begin
if (addr == 3'b000) begin
rddata <= code0;
end else if (addr == 3'b001) begin
rddata <= code1;
end else if (addr == 3'b010) begin
rddata <= code2;
end else if (addr == 3'b011) begin
rddata <= code3;
end else begin
rddata <= rddata;
end
end else begin
A <= A;
B <= B;
set <= set;
end
end
end
endmodule
| 7.86358 |
module avaloncontrol_0 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // .writedata
input wire rd_n, // .read_n
input wire wr_n, // .write_n
input wire [ 2:0] addr, // .address
output wire [31:0] set, // conduit_end.export
input wire [31:0] code0, // .export
input wire [31:0] code1, // .export
input wire [31:0] code2, // .export
input wire [31:0] code3, // .export
output wire [31:0] A, // .export
output wire [31:0] B, // .export
output wire IsOpenLoop // .export
);
avaloncontrol avaloncontrol_0 (
.clk (clk), // clock_reset.clk
.rst_n (rst_n), // .reset_n
.cs_n (cs_n), // avalon_slave_0.chipselect_n
.rddata (rddata), // .readdata
.wrdata (wrdata), // .writedata
.rd_n (rd_n), // .read_n
.wr_n (wr_n), // .write_n
.addr (addr), // .address
.set (set), // conduit_end.export
.code0 (code0), // .export
.code1 (code1), // .export
.code2 (code2), // .export
.code3 (code3), // .export
.A (A), // .export
.B (B), // .export
.IsOpenLoop(IsOpenLoop) // .export
);
endmodule
| 7.86358 |
module avaloncontrol_1 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // .writedata
input wire rd_n, // .read_n
input wire wr_n, // .write_n
input wire [ 2:0] addr, // .address
output wire [31:0] set, // conduit_end.export
input wire [31:0] code0, // .export
input wire [31:0] code1, // .export
input wire [31:0] code2, // .export
input wire [31:0] code3, // .export
output wire [31:0] A, // .export
output wire [31:0] B, // .export
output wire IsOpenLoop // .export
);
avaloncontrol avaloncontrol_1 (
.clk (clk), // clock_reset.clk
.rst_n (rst_n), // .reset_n
.cs_n (cs_n), // avalon_slave_0.chipselect_n
.rddata (rddata), // .readdata
.wrdata (wrdata), // .writedata
.rd_n (rd_n), // .read_n
.wr_n (wr_n), // .write_n
.addr (addr), // .address
.set (set), // conduit_end.export
.code0 (code0), // .export
.code1 (code1), // .export
.code2 (code2), // .export
.code3 (code3), // .export
.A (A), // .export
.B (B), // .export
.IsOpenLoop(IsOpenLoop) // .export
);
endmodule
| 7.86358 |
module avaloncontrol_2 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // .writedata
input wire rd_n, // .read_n
input wire wr_n, // .write_n
input wire [ 2:0] addr, // .address
output wire [31:0] set, // conduit_end.export
input wire [31:0] code0, // .export
input wire [31:0] code1, // .export
input wire [31:0] code2, // .export
input wire [31:0] code3, // .export
output wire [31:0] A, // .export
output wire [31:0] B, // .export
output wire IsOpenLoop // .export
);
avaloncontrol avaloncontrol_2 (
.clk (clk), // clock_reset.clk
.rst_n (rst_n), // .reset_n
.cs_n (cs_n), // avalon_slave_0.chipselect_n
.rddata (rddata), // .readdata
.wrdata (wrdata), // .writedata
.rd_n (rd_n), // .read_n
.wr_n (wr_n), // .write_n
.addr (addr), // .address
.set (set), // conduit_end.export
.code0 (code0), // .export
.code1 (code1), // .export
.code2 (code2), // .export
.code3 (code3), // .export
.A (A), // .export
.B (B), // .export
.IsOpenLoop(IsOpenLoop) // .export
);
endmodule
| 7.86358 |
module avaloncontrol_3 (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // .writedata
input wire rd_n, // .read_n
input wire wr_n, // .write_n
input wire [ 2:0] addr, // .address
output wire [31:0] set, // conduit_end.export
input wire [31:0] code0, // .export
input wire [31:0] code1, // .export
input wire [31:0] code2, // .export
input wire [31:0] code3, // .export
output wire [31:0] A, // .export
output wire [31:0] B, // .export
output wire IsOpenLoop // .export
);
avaloncontrol avaloncontrol_3 (
.clk (clk), // clock_reset.clk
.rst_n (rst_n), // .reset_n
.cs_n (cs_n), // avalon_slave_0.chipselect_n
.rddata (rddata), // .readdata
.wrdata (wrdata), // .writedata
.rd_n (rd_n), // .read_n
.wr_n (wr_n), // .write_n
.addr (addr), // .address
.set (set), // conduit_end.export
.code0 (code0), // .export
.code1 (code1), // .export
.code2 (code2), // .export
.code3 (code3), // .export
.A (A), // .export
.B (B), // .export
.IsOpenLoop(IsOpenLoop) // .export
);
endmodule
| 7.86358 |
module avaloncontrol_dribbler (
input wire clk, // clock_reset.clk
input wire rst_n, // .reset_n
input wire cs_n, // avalon_slave_0.chipselect_n
output wire [31:0] rddata, // .readdata
input wire [31:0] wrdata, // .writedata
input wire rd_n, // .read_n
input wire wr_n, // .write_n
input wire [ 2:0] addr, // .address
output wire [31:0] set, // conduit_end.export
input wire [31:0] code0, // .export
input wire [31:0] code1, // .export
input wire [31:0] code2, // .export
input wire [31:0] code3, // .export
output wire [31:0] A, // .export
output wire [31:0] B, // .export
output wire IsOpenLoop // .export
);
avaloncontrol avaloncontrol_dribbler (
.clk (clk), // clock_reset.clk
.rst_n (rst_n), // .reset_n
.cs_n (cs_n), // avalon_slave_0.chipselect_n
.rddata (rddata), // .readdata
.wrdata (wrdata), // .writedata
.rd_n (rd_n), // .read_n
.wr_n (wr_n), // .write_n
.addr (addr), // .address
.set (set), // conduit_end.export
.code0 (code0), // .export
.code1 (code1), // .export
.code2 (code2), // .export
.code3 (code3), // .export
.A (A), // .export
.B (B), // .export
.IsOpenLoop(IsOpenLoop) // .export
);
endmodule
| 7.86358 |
module avalonif_mmc (
clk,
reset,
chipselect,
address,
read,
readdata,
write,
writedata,
irq,
MMC_nCS,
MMC_SCK,
MMC_SDO,
MMC_SDI,
MMC_CD,
MMC_WP
);
//--- AvalonoXM -----------
input clk;
input reset;
input chipselect;
input [3:2] address;
input read;
output [31:0] readdata;
input write;
input [31:0] writedata;
output irq;
//--- MMC SPIM -----------
// es̐MxLVCMOSɐݒ肷邱
output MMC_nCS;
output MMC_SCK;
output MMC_SDO;
// MMC_SDI : in std_logic := '1';
// MMC_CD : in std_logic := '1'; -- J[h}o
// MMC_WP : in std_logic := '1' -- CgveNgo
input MMC_SDI;
input MMC_CD; // J[h}o
input MMC_WP; // CgveNgo
parameter IDLE = 4'b1000;
parameter SDO = 4'b0100;
parameter SDI = 4'b0010;
parameter DONE = 4'b0001;
reg [ 3:0] state;
reg [ 7:0] bitcount;
wire [31:0] read_0_sig;
wire [31:0] read_1_sig;
wire [31:0] read_2_sig;
reg [ 7:0] divref_reg;
reg [ 7:0] divcount;
reg [ 7:0] rxddata;
reg [ 7:0] txddata;
reg irqena_reg;
reg exit_reg;
reg mmc_wp_reg;
reg mmc_cd_reg;
reg ncs_reg;
reg sck_reg;
reg sdo_reg;
reg [31:0] frc_reg;
reg frczero_reg;
assign irq = (irqena_reg == 1'b1) ? (exit_reg) : (1'b0);
assign readdata = (address == 2'b10) ? (read_2_sig)
: ((address == 2'b01) ? (read_1_sig) : (read_0_sig));
assign read_0_sig[31:16] = 16'h0000;
assign read_0_sig[15] = irqena_reg;
assign read_0_sig[14] = 1'b0;
assign read_0_sig[13] = 1'b0;
assign read_0_sig[12] = frczero_reg;
assign read_0_sig[11] = mmc_wp_reg;
assign read_0_sig[10] = mmc_cd_reg;
assign read_0_sig[9] = exit_reg;
assign read_0_sig[8] = ncs_reg;
assign read_0_sig[7:0] = rxddata;
assign read_1_sig[31:8] = 24'h00_0000;
assign read_1_sig[7:0] = divref_reg;
assign read_2_sig = frc_reg;
assign MMC_nCS = ncs_reg;
assign MMC_SCK = sck_reg;
assign MMC_SDO = sdo_reg;
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
state <= IDLE;
divref_reg <= 8'hFF;
irqena_reg <= 1'b0;
ncs_reg <= 1'b1;
sck_reg <= 1'b1;
sdo_reg <= 1'b1;
exit_reg <= 1'b1;
frc_reg <= 32'h0000_0000;
frczero_reg <= 1'b1;
end else begin
mmc_cd_reg <= MMC_CD;
mmc_wp_reg <= MMC_WP;
case (state)
IDLE: begin
if (chipselect == 1'b1 && write == 1'b1 && address[3] == 1'b0) begin
case (address[2])
1'b0: begin
if (writedata[9] == 1'b0) begin
state <= SDO;
bitcount <= 0;
divcount <= divref_reg;
exit_reg <= 1'b0;
end
irqena_reg <= writedata[15];
ncs_reg <= writedata[8];
txddata <= writedata[7:0];
end
1'b1: begin
divref_reg <= writedata[7:0];
end
endcase
end
end
SDO: begin
if (divcount == 0) begin
state <= SDI;
divcount <= divref_reg;
sck_reg <= ~sck_reg;
sdo_reg <= txddata[7];
txddata <= {txddata[6:0], 1'b0};
end else begin
divcount <= divcount - 1'b1;
end
end
SDI: begin
if (divcount == 0) begin
if (bitcount == 7) begin
state <= DONE;
end else begin
state <= SDO;
end
bitcount <= bitcount + 1;
divcount <= divref_reg;
sck_reg <= ~sck_reg;
rxddata <= {rxddata[6:0], MMC_SDI};
end else begin
divcount <= divcount - 1'b1;
end
end
DONE: begin
if (divcount == 0) begin
state <= IDLE;
sck_reg <= 1'b1;
sdo_reg <= 1'b1;
exit_reg <= 1'b1;
end else begin
divcount <= divcount - 1'b1;
end
end
endcase
if (chipselect == 1'b1 && write == 1'b1 && address == 2'b10) begin
frc_reg <= writedata;
end else if (frc_reg != 0) begin
frc_reg <= frc_reg - 1'b1;
end
if (frc_reg == 0) begin
frczero_reg <= 1'b1;
end else begin
frczero_reg <= 1'b0;
end
end
end // always @ (posedge clk or posedge reset)
endmodule
| 7.306123 |
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