code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AsyncReceiver (
input io_enable,
input io_mem_valid,
output io_mem_ready,
input [3:0] io_mem_addr,
output [31:0] io_mem_rdata,
input io_baudClockX64,
input io_rx,
input clk,
input reset
);
reg _zz_5;
reg _zz_6;
wire [7:0] _zz_7;
wire _zz_8;
wire _zz_9;
wire _zz_10;... | 7.722265 |
module AsyncResetReg (
d,
q,
en,
clk,
rst
);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset... | 6.68936 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetR... | 6.68936 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 59:89]
reg sync_1; // @[Sy... | 6.605499 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 59:89]
reg sync_1; // @[... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[Shi... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[S... | 6.605499 |
module asyncrst_dff (
input clk, // System clock
input en, // System enable
input rst, // System reset
input d, // input
output reg q
); // output
always @(posedge clk or negedge rst) begin
if (~rst) q <= 1'b0;
else if (en) q <= d;
end
endmodule
| 6.765811 |
module AsyncTransmitter (
input wire clk, // write clock
input wire [ 7:0] command, // command input
input wire [63:0] data, // data input
input wire ready,
output reg TxD = 0, // communication line
output wire ndone,
output wire [ 3:0] debug
);
... | 7.099019 |
module AsyncTransmitter_tb;
// Inputs
wire clk;
clock_gen #(10) mclk (clk);
reg [7:0] command;
reg [63:0] data;
reg ready;
reg rd_en;
// Outputs
wire data_line;
wire ndone;
wire [7:0] rec_command;
wire [63:0] rec_data;
wire valid;
wire [63:0] raw_data;
wire raw_data_write;
// Instan... | 7.099019 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX... | 6.83375 |
module AsyncUartReceiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are... | 7.244029 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) lo... | 7.463142 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_i... | 6.70336 |
module async_4phase_handshake_master (
input wire ack,
output wire busy,
output wire req,
input wire reset,
input wire strobe
);
assign busy = ack | req;
/*
* The implementation is a very simple SR latch.
*
* S (strobe) R (ack) Q (req)
* ------------------------------... | 6.624121 |
module async_4phase_handshake_master_tb;
// Inputs
reg ack;
reg reset;
reg strobe;
// Outputs
wire req;
wire busy;
task assert_one;
begin
if (req != 1'b1) begin
$display("ASSERTION FAILED: req expected == 1'b1, actual == 1'b%H", req);
$stop;
end
end
endtask
... | 6.624121 |
module async_4phase_handshake_slave (
output wire ack,
input wire clear,
output wire flag,
input wire req,
input wire reset
);
/*
* A Muller C-element is used to remember if both req and clear have been
* asserted. This allows us to deassert clear and ignore req until it has also
* been dea... | 6.624121 |
module async_4phase_handshake_slave_tb;
// Inputs
reg clear = 1'b0;
reg req = 1'b0;
reg reset = 1'b1;
// Outputs
wire ack;
wire flag;
task assertion;
input [255:0] variable_name;
input actual;
input expected;
begin
if (actual != expected) begin
$display("ASSERTION FAI... | 6.624121 |
module async_audio_axi4lite
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
)
//-----------------------------------------------------------------
// Ports
//--------------------------------------------------------------... | 7.136113 |
module ASYNC_CMP #(
parameter ASIZE = 4
) (
input wrst_n, //write reset
input [ASIZE-1:0] wptr, //write address
input [ASIZE-1:0] rptr, //read address
output aempty_n, //almost empty
output afull_n //almost full
);
reg direction;
wire... | 7.651156 |
module async_controller (
input clk,
WE,
EN,
input [ 2:0] addr,
input [ 3:0] data_write,
inout [15:0] MemDB,
output RamAdv,
RamClk,
RamCS,
MemOE,
MemWR,
RamLB,
RamUB,
output [ 3:0] an,
output [ 7:0] seg,
// output [1... | 7.420594 |
module async_fsm (
input clk,
WR,
CS,
output RamAdv,
RamClk,
RamCS,
MemOE,
MemWR,
RamLB,
RamUB
);
localparam
READY = 2'b00,
READ = 2'b01,
WRITE = 2'b10,
INACTIVE = 7'b1111111,
CYCLES_TO_WAIT = 3'd6;
reg [1:0] current, next;
reg [2:0] cycle... | 7.61829 |
module async_dpram_40W_32D (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [39:0] data;
input [4:0] rdaddress;
input rdclock;
input [4:0] wraddress;
input wrclock;
input wren;
output [39:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 ... | 6.54746 |
module async_d_ff (
clk,
D,
reset,
Q
);
input clk, D, reset;
output reg Q;
always @(posedge clk, negedge reset)
if (!reset) Q = 0;
else Q = D;
endmodule
| 6.607682 |
module async_fifo #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writ... | 8.811691 |
module async_fifo_114 (
input wclk,
input wrst,
input [9:0] din,
input wput,
output reg full,
input rclk,
input rrst,
output reg [9:0] dout,
input rget,
output reg empty
);
localparam SIZE = 4'ha;
localparam DEPTH = 5'h10;
localparam ADDR_SIZE = 3'h4;
reg [3:0] M_wadd... | 6.86723 |
module async_fifo_256x72_to_36 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
almost_full,
dout,
empty,
full,
rd_data_count
);
input [71 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output almost_full;
output [35 : 0] dout;
output ... | 7.438764 |
module async_fifo_256x72_to_36 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull
);
input aclr;
input [71:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
`i... | 7.438764 |
module async_fifo_512x36_progfull_500 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
prog_full,
rd_data_count,
wr_data_count
);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
outpu... | 7.57829 |
module async_fifo_512x36_to_72_progfull_500 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
prog_full,
rd_data_count,
wr_data_count
);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [71 : 0] dout;
... | 7.57829 |
module async_fifo_512x36_to_72_progfull_500 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [71:0] q;
output rdempty;
output wrfull;
output [8:0... | 7.57829 |
module async_fifo_64by16 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
valid
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output valid;
// synthesis... | 7.273335 |
module async_fifo_86 (
input wclk,
input wrst,
input [23:0] din,
input wput,
output reg full,
input rclk,
input rrst,
output reg [23:0] dout,
input rget,
output reg empty
);
localparam SIZE = 5'h18;
localparam DEPTH = 7'h40;
localparam ADDR_SIZE = 3'h6;
reg [5:0] M_wa... | 6.8431 |
module vfifo_dual_port_ram_dc_dw (
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(D... | 7.980715 |
module dff_sr (
aclr,
aset,
clock,
data,
q
);
input aclr;
input aset;
input clock;
input data;
output reg q;
always @(posedge clock or posedge aclr or posedge aset)
if (aclr) q <= 1'b0;
else if (aset) q <= 1'b1;
else q <= data;
endmodule
| 6.823625 |
module versatile_fifo_async_cmp (
wptr,
rptr,
fifo_empty,
fifo_full,
wclk,
rclk,
rst
);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH - 1;
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
parameter going_empty = 1'b0;
parameter g... | 7.199743 |
module async_fifo_dw_simplex_top (
// a side
a_d,
a_wr,
a_fifo_full,
a_q,
a_rd,
a_fifo_empty,
a_clk,
a_rst,
// b side
b_d,
b_wr,
b_fifo_full,
b_q,
b_rd,
b_fifo_empty,
b_clk,
b_rst
);
parameter data_width = 18;
parameter addr_width = 4;
// a... | 8.957407 |
module async_fifo_dw_simplex_top (
// a side
a_d,
a_wr,
a_fifo_full,
a_q,
a_rd,
a_fifo_empty,
a_clk,
a_rst,
// b side
b_d,
b_wr,
b_fifo_full,
b_q,
b_rd,
b_fifo_empty,
b_clk,
b_rst
);
parameter data_width = 18;
parameter addr_width = 4;
// a... | 8.957407 |
module async_fifomem #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4,
parameter WRITE_BLOCK_SIZE = DATA_WIDTH //number of bits for individual write enable
) (
input wire wclk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wdata_i,
inp... | 7.170627 |
module async_fifo_fwft #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2 ** clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH + 1)
) (
input... | 8.448902 |
module async_fifo_generator_v2_2_33x16 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
valid
);
input [32 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [32 : 0] dout;
output empty;
output full;
output valid;
... | 8.434118 |
module async_fifo_in #(
parameter DATA_WIDTH = 16, //data width
parameter ADDR_WIDTH = 3, //adress width
parameter ALMOST_FULL_BUFFER = 2 //number of free entries until almost_full
) (
input wire aresetn_i,
input wire scan_mode_i,
output wire [ ADDR_WIDTH:0] wr_ptr_o, //... | 6.513425 |
module async_fifo_in_288b_out_72b (
//-----------------------------------
//wr intfc
input [287:0] din,
input wr_en,
output almost_full,
output full,
input wr_clk,
//-----------------------------------
//rd intfc
input rd_en,
output almost_empty,
output empty,
ou... | 6.513425 |
module async_fifo_in_72b_out_144b (
//-----------------------------
//wr intfc
//din is one clk cycle later than wr_en due to set-up time violation fix
input [71:0] din,
input wr_en,
output full,
input wr_clk,
input wr_reset,
input wr_clear_residue,
//-------------------------... | 6.513425 |
module async_fifo_in_72b_out_288b (
//-----------------------------
//wr intfc
//din is one clk cycle later than wr_en due to set-up time violation fix
input [71:0] din,
input wr_en,
output full,
input wr_clk,
input wr_reset,
input wr_clear_residue,
//-------------------------... | 6.513425 |
module async_fifo_mq (
d,
fifo_full,
write,
write_enable,
clk1,
rst1,
q,
fifo_empty,
read,
read_enable,
clk2,
rst2
);
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
input [data_width-1:0] d;
output [... | 7.477422 |
module async_fifo_mq_md (
d,
fifo_full,
write,
write_enable,
clk1,
rst1,
q,
fifo_empty,
read,
read_enable,
clk2,
rst2
);
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
input [data_width*nr_of_queues-1:... | 7.477422 |
module async_fifo_out #(
parameter DATA_WIDTH = 16, //data width
parameter ADDR_WIDTH = 3, //adress width
parameter ALMOST_EMPTY_BUFFER = 2 //number of written entries until almost_empty
) (
input wire aresetn_i,
input wire scan_mode_i,
input wire rclk_... | 8.324355 |
module async_fifo_riffa #(
parameter C_WIDTH = 8, // Data bus width
parameter C_DEPTH = 64, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2 ** `CLOG2(C_DEPTH),
parameter C_DEPTH_BITS = `CLOG2(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = `CLOG2(C_REAL_DEPTH + 1)
) (
input ... | 8.379812 |
module async_cmp #(
parameter C_DEPTH_BITS = 4,
// Local parameters
parameter N = C_DEPTH_BITS - 1
) (
input WR_RST,
input WR_CLK,
input RD_RST,
input RD_CLK,
input RD_VALID,
input WR_VALID,
output EMPTY,
output FULL,
input [C_DEPTH_BITS-1:0] WR_PTR,
input [C_DEPTH_BI... | 7.9477 |
module rd_ptr_empty #(
parameter C_DEPTH_BITS = 4
) (
input RD_CLK,
input RD_RST,
input RD_EN,
output RD_EMPTY,
output [C_DEPTH_BITS-1:0] RD_PTR,
output [C_DEPTH_BITS-1:0] RD_PTR_P1,
input CMP_EMPTY
);
reg rEmpty = 1;
reg rEmpty2 = 1;
reg [... | 7.458099 |
module wr_ptr_full #(
parameter C_DEPTH_BITS = 4
) (
input WR_CLK,
input WR_RST,
input WR_EN,
output WR_FULL,
output [C_DEPTH_BITS-1:0] WR_PTR,
output [C_DEPTH_BITS-1:0] WR_PTR_P1,
input CMP_FULL
);
reg rFull = 0;
reg rFull2 = 0;
reg [C_DEP... | 7.340892 |
module sync_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
parameter C_PROVIDE_COUNT = 0, // Include code for counts
// Local parameters
parameter C_REAL_DEPTH = 2 ** `CLOG2(C_DEPTH),
parameter C_DEPTH_BITS = `CLOG2S(C_REAL_DEPTH),
paramet... | 7.717079 |
module ram_1clk_1w_1r #(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
) (
input CLK,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRB,
input [ C_RAM_WIDTH-1:0] DINA,
ou... | 7.362944 |
module ram_2clk_1w_1r #(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
) (
input CLKA,
input CLKB,
input WEA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRB,
i... | 7.640135 |
module async_fifo_rptr_empty_ctrl #(
parameter ADDR_WIDTH = 4,
parameter ALMOST_EMPTY_BUFFER = 2
) (
input wire rclk_i,
input wire rresetn_i,
input wire rd_en_i,
input wire [ADDR_WIDTH:0] rsync_wr_ptr_i, //gray coded
output wire ... | 6.943524 |
module async_fifo_tb #(
parameter WIDTH = 8,
DEPTH = 130
) ();
/************* 用取对数的方法计算地址指针的位宽 ************************/
function integer log2b(input integer data); //函数返回类型integer
begin
for (log2b = 0; data > 0; log2b = log2b + 1) data = data >> 1;
log2b = log2b - 1;
end
endfunctio... | 6.523155 |
module async_fifo_v1 #(
parameter BUS_WIDTH = 8,
FIFO_DEPTH = 16
) (
input RST,
input CLK_WR,
input CLK_RD,
input [BUS_WIDTH-1:0] DATA_IN,
input WR_EN,
input RD_EN,
input H_FLUSH,
output reg [BUS_WIDTH-1:0] DATA_OUT,
output FULL,
output EMPTY,
output H_FULL
);
pa... | 7.408872 |
module ASYNC_FIFO_WPTR_FULL #(
parameter ADDRSIZE = 4
) (
output reg wfull,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE : 0] wptr,
input [ADDRSIZE : 0] wq2_rptr,
input winc,
wclk,
wrst_n
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
... | 7.009131 |
module async_mem ( /*AUTOARG*/
// Outputs
ack,
dout,
// Inputs
req,
addr,
din,
we
);
parameter ACCESS_TIME = 10;
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
localparam CLOCK_PULSE_W... | 8.00349 |
module async_mem2 (
input wire clkA,
input wire clkB,
input wire [asz-1:0] addrA,
input wire [asz-1:0] addrB,
input wire wr_csA,
input wire wr_csB,
input wire [ 7:0] wr_dataA,
input wire [ 7:0] wr_dataB,
output wire [ 7:0] rd_d... | 8.608668 |
module async_memory (
input clock,
input reset,
input [31:0] addr_in,
output [31:0] data_out,
input [31:0] data_in,
input [ 1:0] size_in, //0=byte, 1=2-byte, 2=unaligned, 3=word
input we_in,
input re_in
);
parameter MEM_ADDR = 16'h1000;
parameter DO_INIT = 0;
... | 8.247777 |
module async_ram256x8 (
input wire [7:0] a, // líneas de dirección
inout tri [7:0] d, // líneas de datos (entrada/salida)
input wire we, // escritura (write enable)
input wire oe // lectura (output enable)
);
/* Las señales tipo "tri" son idénticas a "wire". Se suele emplear "tri"
... | 7.877666 |
module based on the number
of rd/wr ports.
NOTE:
This module does not have reset. Tables can be too big, the state machine to
clear datas should be handled outside (if necessary).
****************************************************************************/
`include "logfunc.h"
module async_ram_1port
#... | 7.152734 |
module based on the number
of rd/wr ports.
NOTE:
This module does not have reset. Tables can be too big, the state machine to
clear datas should be handled outside (if necessary).
****************************************************************************/
`include "logfunc.h"
module async_ram_2port
... | 7.152734 |
module async_receiver (
input clk,
input rst,
input RxD,
output RxD_start,
output reg RxD_data_ready,
output reg [7:0]RxD_data // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
);
wire OversamplingTick;
`ifdef IMPLEMENT
parameter ClkFrequency = 50000000; ... | 7.236243 |
module async_reset (
clock,
reset,
d,
q
);
(* src = "tests/async_reset.v:2.9-2.14" *)
input clock;
wire clock;
(* src = "tests/async_reset.v:4.9-4.10" *)
input d;
wire d;
(* src = "tests/async_reset.v:5.10-5.11" *)
output q;
wire q;
(* src = "tests/async_reset.v:7.7-7.12" *)
reg q... | 6.817445 |
module async_reset (
input rstn_async,
input clk,
output reg rstn
);
reg q1;
always @(posedge clk or negedge rstn_async) begin
if (!rstn_async) begin
q1 <= 1'b0;
end else begin
q1 <= 1'b1;
end
end
always @(posedge clk or negedge rstn_async) begin
if (!rstn_async) begin... | 6.817445 |
module async_reset_n (
clock,
reset_n,
d,
q
);
(* src = "tests/async_reset_n.v:2.9-2.14" *)
input clock;
wire clock;
(* src = "tests/async_reset_n.v:4.9-4.10" *)
input d;
wire d;
(* src = "tests/async_reset_n.v:5.10-5.11" *)
output q;
wire q;
(* src = "tests/async_reset_n.v:7.7-7.12"... | 6.824245 |
module async_reset_n (
input clock,
input reset_n,
input d,
output q
);
reg q_reg;
always @(posedge clock, negedge reset_n) begin
if (~reset_n) begin
q_reg <= 1'b0;
end else begin
q_reg <= d;
end
end
assign q = q_reg;
endmodule
| 6.824245 |
module
* Copyright Robert Schmidt <rschmidt@uni-bremen.de>, 2020
*
* This documentation describes Open Hardware and is licensed under the
* CERN-OHL-W v2.
*
* You may redistribute and modify this documentation under the terms
* of the CERN-OHL-W v2. (https://cern.ch/cern-ohl). This documentation
* is distribute... | 8.161218 |
module async_rstn_glitch_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RSTN
);
wire w_or_1;
//wire w_buf_1;
//buf(w_buf_1, i_RSTN);
or (w_or_1, i_RSTN, i_RSTN);
async_rstn_synchronizer async_rstn_synchronizer (
.i_CLK (i_CLK),
.i_RSTN(w_or_1),
.o_RSTN(o_RSTN)
);
endm... | 6.953109 |
module async_rstn_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RSTN
);
reg r_ff;
always @(posedge i_CLK, negedge i_RSTN) begin
if (!i_RSTN) {o_RSTN, r_ff} <= 2'b0;
else {o_RSTN, r_ff} <= {r_ff, 1'b1};
end
endmodule
| 7.291522 |
module async_rst_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RST
);
reg r_ff;
always @(posedge i_CLK, negedge i_RSTN) begin
if (!i_RSTN) {o_RST, r_ff} <= 2'b11;
else {o_RST, r_ff} <= {r_ff, 1'b0};
end
endmodule
| 6.653778 |
module async_rx (
input clk,
input rst,
input [11:0] data,
output r_en,
input empty,
output reg [11:0] duty_cycle
);
localparam IDLE = 3'b001, READ = 3'b010, LATCH = 3'b100;
reg [2:0] state;
reg [2:0] next_state;
always @(*) begin
case (state)
IDLE:
if (!empty) next_sta... | 8.183881 |
module async_send (
input clk,
input TxD_start,
input [7:0] TxD_data,
output reg TxD,
output TxD_busy
);
parameter Clk_Freq = 50000000; //50M
parameter Baud = 115200; //波特率
parameter BaudGeneAccWidth = 16;
reg [BaudGeneAccWidth:0] BaudGeneAcc;
... | 7.411494 |
module async_seq_writer #(
parameter word_count_top = 2'd3,
parameter read_count_top = 3'd7,
parameter address_step = 30'd4,
parameter address_bottom = 30'h0000_0000,
parameter address_top = 30'h0200_0000 - address_step
) (
input ddr2_clk,
input wr_clk,
input RST,
output reg ... | 8.14394 |
module async_sram_phy #(
parameter W_ADDR = 18,
parameter W_DATA = 16,
// If 1, register input paths, increasing read latency from 1 to 2 cycles:
parameter DQ_SYNC_IN = 0
) (
// These should be the same clock/reset used by the controller
input wire clk,
input wire rst_n,
// From... | 8.359444 |
module fifo_async_tb;
reg wclk, wrst_n;
reg rclk, rrst_n;
reg wq, rq;
reg [7:0] write_data; // data input to be pushed to buffer
wire [7:0] read_data; // port to output the data using pop.
wire rempty, wfull; // buffer empty and full indication
integer idx = 0;
`define TEST_CASE(VAR, VALUE) \
... | 7.518899 |
module async_to_sync_reset_shift (
input clk,
input Pinput,
output Poutput
);
parameter LENGTH = 8;
parameter INPUT_POLARITY = 1'b1;
parameter OUTPUT_POLARITY = 1'b1;
reg [LENGTH-1:0] shift = 0;
always @(Pinput or(clk)) begin
if (Pinput == INPUT_POLARITY) begin
shift <= {LENGTH{OUTPUT... | 8.342032 |
module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequenc... | 6.83375 |
module: async_transmitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module async_transmitter_tb;
// Inputs
reg clk;
reg TxD_start;
reg [7:0] TxD_data;
// Outputs
wire TxD;
wi... | 8.14618 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
////////////////////////////////////////////////////////
module async_transmitter(
input clk,
input... | 6.83375 |
module BaudTickGen (
input clk,
rst,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >>... | 7.463142 |
module async_up_counter (
input clk_i, // Clock
input rst_i, // Reset
output [3:0] count_o // Count Value
);
wire [3:0] q_n;
// DFF 0
dff dff_1 (
.clk_i(clk_i), // Input Clock
.rst_i(rst_i),
.d_i (q_n[0]),
.q_o (count_o[0]),
.q_n_o(q_n[0])
)... | 7.183579 |
module dff (
input clk_i,
input rst_i,
input d_i,
output reg q_o,
output q_n_o
);
assign q_n_o = ~q_o;
always @(posedge clk_i) begin
if (rst_i) begin
q_o <= 1'b0;
end else begin
q_o <= d_i;
end
end
endmodule
| 7.174483 |
module async_wb (
wbm_rst_n,
wbm_clk_i,
wbm_cyc_i,
wbm_stb_i,
wbm_adr_i,
wbm_we_i,
wbm_dat_i,
wbm_sel_i,
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbs_rst_n,
wbs_clk_i,
wbs_cyc_o,
wbs_stb_o,
wbs_adr_o,
wbs_we_o,
wbs_dat_o,
wbs_sel_o,
wbs_dat_i,
... | 7.368908 |
module asynrecounter10 (
input wire clk,
input wire reset, //asynchronous active-high reset
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset) q <= 4'b0000;
else if (q == 4'b1001) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 6.946006 |
module asynrecounter10_tb;
`define asynrecounter10_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
asy... | 6.946006 |
module asynrecounter15 (
input clk,
input reset, //asynchronous active-high reset
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 6.946006 |
module asynrecounter15_tb;
`define asynrecounter15_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
asy... | 6.946006 |
module asynrefsm1 (
input wire clk,
input wire reset, //asynchronous active-high reset
input wire in,
output reg out
);
reg state;
parameter A = 1'b0, B = 1'b1;
always @(posedge clk or posedge reset)
if (reset) begin
state <= B;
out <= 1'b1;
end else if (state == A) beg... | 7.460022 |
module asynrefsm1_tb;
`define asynrefsm1_TEST(ID, CLK, RESET, IN, OUT)\
clk=CLK;\
reset=RESET;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg ... | 7.387525 |
module asynrefsm2 (
input wire clk,
input wire reset, //asynchronous active-high reset
input wire j,
input wire k,
output reg out
);
reg state;
parameter ON = 1'b1, OFF = 1'b0;
always @(posedge clk or posedge reset)
if (reset) begin
state <= OFF;
out <= 1'b0;
end e... | 7.606491 |
module asynrefsm2_tb;
`define asynrefsm2_TEST(ID, CLK, RESET, J, K, OUT)\
clk=CLK;\
reset=RESET;\
j=J;\
k=K;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg r... | 6.992946 |
module asynrevem (
input wire clk,
input wire rst, //asynchronous active-high reset
input wire [1:0]in,
output reg [1:0]out
);
reg [2:0] cur_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always @(posedge clk or posedge rst)
if (rst) cur_state... | 8.505785 |
module asynrevem_tb;
`define asynrevem_TEST(ID, CLK, RST, IN, OUT)\
clk=CLK;\
rst=RST;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg rst;
reg [1:0] in;
... | 6.799103 |
module asyn_1024_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output rdempty;
output [10:0] rdusedw;
output [10:0] wrusedw;
... | 7.109215 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.