code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AsyncReceiver (
input io_enable,
input io_mem_valid,
output io_mem_ready,
input [3:0] io_mem_addr,
output [31:0] io_mem_rdata,
input io_baudClockX64,
input io_rx,
input clk,
input reset
);
reg _zz_5;
reg _zz_6;
wire [7:0] _zz_7;
wire _zz_8;
wire _zz_9;
wire _zz_10;
wire _zz_11;
wire [31:0] _zz_12;
wire [0:0] _zz_13;
reg [1:0] state;
reg [5:0] bitTimer;
reg [2:0] bitCount;
reg [7:0] shifter;
reg baudClockX64Sync1;
reg baudClockX64Sync2;
reg rxSync1;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg [7:0] rdata;
reg ready;
wire busCycle;
reg _zz_4;
assign _zz_10 = (busCycle && (!_zz_4));
assign _zz_11 = (bitTimer == (6'b000000));
assign _zz_12 = {24'd0, rdata};
assign _zz_13 = (!_zz_9);
Fifo fifo_1 (
.io_dataIn(shifter),
.io_dataOut(_zz_7),
.io_read(_zz_5),
.io_write(_zz_6),
.io_full(_zz_8),
.io_empty(_zz_9),
.clk(clk),
.reset(reset)
);
always @(*) begin
_zz_5 = 1'b0;
if (_zz_10) begin
case (io_mem_addr)
4'b0000: begin
_zz_5 = 1'b1;
end
4'b0100: begin
end
default: begin
end
endcase
end
end
always @(*) begin
_zz_6 = 1'b0;
case (state)
2'b00: begin
end
2'b01: begin
end
2'b10: begin
end
default: begin
if (_zz_11) begin
if ((rxSync1 == 1'b1)) begin
if ((!_zz_8)) begin
_zz_6 = 1'b1;
end
end
end
end
endcase
end
assign busCycle = (io_mem_valid && io_enable);
assign io_mem_rdata = (busCycle ? _zz_12 : (32'b00000000000000000000000000000000));
assign io_mem_ready = (busCycle ? ready : 1'b0);
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= (2'b00);
bitTimer <= (6'b000000);
bitCount <= (3'b000);
shifter <= (8'b00000000);
baudClockX64Sync1 <= 1'b0;
baudClockX64Sync2 <= 1'b0;
rxSync1 <= 1'b0;
rdata <= (8'b00000000);
ready <= 1'b0;
end else begin
baudClockX64Sync1 <= io_baudClockX64;
baudClockX64Sync2 <= baudClockX64Sync1;
rxSync1 <= io_rx;
if ((baudClockX64Sync2 && (!_zz_1))) begin
bitTimer <= (bitTimer - (6'b000001));
end
case (state)
2'b00: begin
state <= (2'b00);
if (((!rxSync1) && _zz_2)) begin
state <= (2'b01);
bitTimer <= (6'b011111);
end
end
2'b01: begin
state <= (2'b01);
if ((bitTimer == (6'b000000))) begin
if ((rxSync1 == 1'b0)) begin
bitTimer <= (6'b111111);
state <= (2'b10);
end else begin
state <= (2'b00);
end
end
end
2'b10: begin
state <= (2'b10);
if ((baudClockX64Sync2 && (!_zz_3))) begin
if ((bitTimer == (6'b000000))) begin
shifter[bitCount] <= rxSync1;
bitCount <= (bitCount + (3'b001));
if ((bitCount == (3'b111))) begin
state <= (2'b11);
end
end
end
end
default: begin
state <= (2'b11);
if (_zz_11) begin
state <= (2'b00);
end
end
endcase
ready <= busCycle;
if (_zz_10) begin
case (io_mem_addr)
4'b0000: begin
rdata <= _zz_7;
end
4'b0100: begin
rdata <= {7'd0, _zz_13};
end
default: begin
end
endcase
end
end
end
always @(posedge clk) begin
_zz_1 <= baudClockX64Sync2;
_zz_4 <= busCycle;
end
always @(posedge clk) begin
_zz_2 <= rxSync1;
end
always @(posedge clk) begin
_zz_3 <= baudClockX64Sync2;
end
endmodule
| 7.722265 |
module AsyncResetReg (
d,
q,
en,
clk,
rst
);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset
// is not actually asserted cleanly at time 0,
// and we want to make sure to properly model
// that, yet Chisel codebase is absolutely intolerant
// of Xs.
`ifndef SYNTHESIS
initial begin : B0
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
q = _RAND[0];
`endif // RANDOMIZE
if (rst) begin
q = RESET_VALUE[0];
end
end
`endif
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= RESET_VALUE[0];
end else if (en) begin
q <= d;
end
end
endmodule
| 6.68936 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin
reg_ <= 1'h0;
end else begin
reg_ <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin
reg_ <= 2'h0;
end else if (io_en) begin
reg_ <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 2'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge reset) begin
if (reset) begin
reg_ <= 2'h0;
end else begin
reg_ <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
reg_ = 2'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.68936 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 59:89]
reg sync_1; // @[SynchronizerReg.scala 59:89]
reg sync_2; // @[SynchronizerReg.scala 59:89]
assign io_q = sync_0; // @[SynchronizerReg.scala 67:10]
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_0 <= 1'h0;
end else begin
sync_0 <= sync_1;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_1 <= 1'h0;
end else begin
sync_1 <= sync_2;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_2 <= 1'h0;
end else begin
sync_2 <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
sync_0 = 1'h0;
end
if (reset) begin
sync_1 = 1'h0;
end
if (reset) begin
sync_2 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.605499 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 59:89]
reg sync_1; // @[SynchronizerReg.scala 59:89]
reg sync_2; // @[SynchronizerReg.scala 59:89]
assign io_q = sync_0; // @[SynchronizerReg.scala 67:10]
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_0 <= 1'h0;
end else begin
sync_0 <= sync_1;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_1 <= 1'h0;
end else begin
sync_1 <= sync_2;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_2 <= 1'h0;
end else begin
sync_2 <= io_d;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
sync_0 = 1'h0;
end
if (reset) begin
sync_1 = 1'h0;
end
if (reset) begin
sync_2 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:24 ShiftReg.scala 48:24]
assign output_chain_clock = clock;
assign output_chain_reset = reset;
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 82:39]
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 output_chain ( // @[ShiftReg.scala 45:23]
.clock(output_chain_clock),
.reset(output_chain_reset),
.io_d (output_chain_io_d),
.io_q (output_chain_io_q)
);
assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:24 ShiftReg.scala 48:24]
assign output_chain_clock = clock;
assign output_chain_reset = reset;
assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 82:39]
endmodule
| 6.605499 |
module asyncrst_dff (
input clk, // System clock
input en, // System enable
input rst, // System reset
input d, // input
output reg q
); // output
always @(posedge clk or negedge rst) begin
if (~rst) q <= 1'b0;
else if (en) q <= d;
end
endmodule
| 6.765811 |
module AsyncTransmitter (
input wire clk, // write clock
input wire [ 7:0] command, // command input
input wire [63:0] data, // data input
input wire ready,
output reg TxD = 0, // communication line
output wire ndone,
output wire [ 3:0] debug
);
reg wr_en = 1'b0, rd_en = 1'b0;
wire empty, full, valid;
wire [71:0] dout;
reg [71:0] data_to_send = 72'h0;
reg [7:0] bits_to_send = 8'h0;
reg csb = 1'b0;
wire done;
assign ndone = ~done;
assign debug = {TxD, read_state};
TransmitterReceiverFifo fifo (
.wr_clk(clk),
.rd_clk(clk),
.din({command, data}),
.dout(dout),
.wr_en(wr_en),
.rd_en(rd_en),
.full(full),
.empty(empty),
.valid(valid)
);
/// writing to fifo
reg write_state = 1'b0;
always @(posedge clk) begin
case (write_state)
1'b0: begin
if (ready) begin
wr_en <= 1'b1;
write_state <= 1'b1;
end
end
1'b1: begin
wr_en <= 1'b0;
if (~ready) write_state <= 1'b0;
end
endcase
end
reg done_sending = 0;
set_reset #(1'b1) done_ff (
.clock(clk),
.set(done_sending & empty),
.reset(ready),
.q(done)
);
reg [7:0] delay = 0;
parameter clock_cycles = 9;
// reading from fifo
reg [2:0] read_state = 3'h0;
always @(posedge clk) begin
if (|delay) begin
delay <= delay - 8'b1;
end else begin
done_sending <= 1'b0;
case (read_state)
3'h0: begin
if (valid) begin
read_state <= 3'h1;
end
TxD <= 1'b0;
end
3'h1: begin
rd_en <= 1'b1;
data_to_send <= dout;
read_state <= 3'h2;
TxD <= 1'b0;
end
3'h2: begin
bits_to_send <= 8'd72;
read_state <= 3'h3;
rd_en <= 1'b0;
TxD <= 1'b1;
delay <= clock_cycles;
end
3'h3: begin
TxD <= data_to_send[71];
delay <= clock_cycles;
if (bits_to_send > 1) begin
data_to_send <= {data_to_send[70:0], 1'b0};
bits_to_send <= bits_to_send - 1'b1;
end else begin
read_state <= 3'h4;
end
end
3'h4: begin
done_sending <= 1'b1;
read_state <= 3'h5;
TxD <= 1'b1;
delay <= clock_cycles;
end
3'h5: begin
TxD <= 1'b0;
delay <= 8'd19;
read_state <= 3'h0;
end
default: begin
read_state <= 3'h0;
TxD <= 1'b0;
end
endcase
end
end
endmodule
| 7.099019 |
module AsyncTransmitter_tb;
// Inputs
wire clk;
clock_gen #(10) mclk (clk);
reg [7:0] command;
reg [63:0] data;
reg ready;
reg rd_en;
// Outputs
wire data_line;
wire ndone;
wire [7:0] rec_command;
wire [63:0] rec_data;
wire valid;
wire [63:0] raw_data;
wire raw_data_write;
// Instantiate the Unit Under Test (UUT)
AsyncTransmitter uut (
.clk(clk),
.command(command),
.data(data),
.ready(ready),
.TxD(data_line),
.ndone(ndone)
);
AsyncReceiver uut2 (
.clk(clk),
.command(rec_command),
.data(rec_data),
.rd_en(rd_en),
.RxD(data_line),
.valid(valid),
.raw_data(raw_data),
.raw_data_write(raw_data_write)
);
initial begin
// Initialize Inputs
command = 0;
data = 0;
ready = 0;
rd_en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
command = 8'h42;
data = 64'h123456789abcdeff;
ready = 1;
#20 ready = 0;
#20 ready = 1;
#20 ready = 0;
end
endmodule
| 7.099019 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
module AsyncUartTransmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 100000000; // 25MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
| 6.83375 |
module AsyncUartReceiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 100000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 8; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
`ifdef SIMULATION
assign RxD_idle = 0;
`else
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
`endif
endmodule
| 7.244029 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
.clock(io_out_source_valid_0_clock),
.reset(io_out_source_valid_0_reset),
.io_d (io_out_source_valid_0_io_d),
.io_q (io_out_source_valid_0_io_q)
);
assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:24 ShiftReg.scala 48:24]
assign io_out_source_valid_0_clock = clock;
assign io_out_source_valid_0_reset = reset;
assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
endmodule
| 6.70336 |
module async_4phase_handshake_master (
input wire ack,
output wire busy,
output wire req,
input wire reset,
input wire strobe
);
assign busy = ack | req;
/*
* The implementation is a very simple SR latch.
*
* S (strobe) R (ack) Q (req)
* -----------------------------------
* 0 0 No Change
* 0 1 0
* 1 0 1
* 1 1 Scary Badness
*
* Note: The scary badness should not happen due to proper combinational logic.
*/
wire s = ~r & strobe; // block the strobe signal if we are in reset or if ack is asserted
wire r = reset | ack; // IMPORTANT: the reset puts the SR latch into a known state
wire q_n = ~(q | s);
wire q = ~(q_n | r);
assign req = q;
endmodule
| 6.624121 |
module async_4phase_handshake_master_tb;
// Inputs
reg ack;
reg reset;
reg strobe;
// Outputs
wire req;
wire busy;
task assert_one;
begin
if (req != 1'b1) begin
$display("ASSERTION FAILED: req expected == 1'b1, actual == 1'b%H", req);
$stop;
end
end
endtask
task assert_zero;
begin
if (req != 1'b0) begin
$display("ASSERTION FAILED: req expected == 1'b0, actual == 1'b%H", req);
$stop;
end
end
endtask
// Stimulus and assertions
initial begin
ack = 1'b0;
reset = 1'b1;
strobe = 1'b0;
#100; // wait for Xilinx GSR
reset = 1'b0;
// test 1: proper state transition
strobe = 1'b0;
#1;
assert_zero;
strobe = 1'b1;
#1;
assert_one;
strobe = 1'b0;
#1;
assert_one;
ack = 1'b1;
#1;
assert_zero;
ack = 1'b0;
#1;
assert_zero;
// test 2: illegal transition: ack takes priority
strobe = 1'b1;
#2;
assert_one;
ack = 1'b1;
#1;
assert_zero;
strobe = 1'b0;
ack = 1'b0;
#1;
assert_zero;
$stop;
end
// Unit-under-test
async_4phase_handshake_master UUT (
.ack(ack),
.busy(busy),
.req(req),
.reset(reset),
.strobe(strobe)
);
endmodule
| 6.624121 |
module async_4phase_handshake_slave (
output wire ack,
input wire clear,
output wire flag,
input wire req,
input wire reset
);
/*
* A Muller C-element is used to remember if both req and clear have been
* asserted. This allows us to deassert clear and ignore req until it has also
* been deasserted.
*/
wire x;
async_muller_c_element async_muller_c_element_inst (
.in ({req, clear}), // input [1:0]
.out(x) // output
);
/*
* The implementation uses two SR latches.
*
* S R Q
* -------------------
* 0 0 No Change
* 0 1 0
* 1 0 1
* 1 1 Scary Badness
*
* Note: The scary badness should not happen due to proper combinational logic.
*/
wire q1_n = ~(q1 | s1);
wire q1 = ~(q1_n | r1);
wire q2_n = ~(q2 | s2);
wire q2 = ~(q2_n | r2);
// flag is the output of SR latch #1
assign flag = q1;
wire s1 = req & ~r1; // block the req signal if we are in reset or if clear is asserted
wire r1 = reset | x; // IMPORTANT: the reset puts the SR latch into a known state
// ack is the output of SR latch #2
assign ack = q2;
wire s2 = clear & ~r2; // block the clear signal if we are in reset or if req is deasserted
wire r2 = reset | ~req; // IMPORTANT: the reset puts the SR latch into a known state
endmodule
| 6.624121 |
module async_4phase_handshake_slave_tb;
// Inputs
reg clear = 1'b0;
reg req = 1'b0;
reg reset = 1'b1;
// Outputs
wire ack;
wire flag;
task assertion;
input [255:0] variable_name;
input actual;
input expected;
begin
if (actual != expected) begin
$display("ASSERTION FAILED: actual == 1'b%H, expected == 1'b%H: %s", actual, expected,
variable_name);
$stop;
end
end
endtask
// Stimulus and assertions
initial begin
#100; // wait for Xilinx GSR
reset = 1'b0;
// test 1: proper state transition
req = 1'b0;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b0);
req = 1'b1;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b1);
clear = 1'b1;
#1;
assertion("ack", ack, 1'b1);
assertion("flag", flag, 1'b0);
clear = 1'b0;
#1;
assertion("ack", ack, 1'b1);
assertion("flag", flag, 1'b0);
req = 1'b0;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b0);
// test 2: keep clear asserted longer than we should
req = 1'b0;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b0);
req = 1'b1;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b1);
clear = 1'b1;
#1;
assertion("ack", ack, 1'b1);
assertion("flag", flag, 1'b0);
req = 1'b0;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b0);
clear = 1'b0;
#1;
assertion("ack", ack, 1'b0);
assertion("flag", flag, 1'b0);
$stop;
end
// Unit-under-test
async_4phase_handshake_slave UUT (
.ack (ack), // output
.clear(clear), // input
.flag (flag), // output
.req (req), // input
.reset(reset) // input
);
endmodule
| 6.624121 |
module async_audio_axi4lite
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input cfg_awvalid_i
, input [31:0] cfg_awaddr_i
, input cfg_wvalid_i
, input [31:0] cfg_wdata_i
, input [ 3:0] cfg_wstrb_i
, input cfg_bready_i
, input cfg_arvalid_i
, input [31:0] cfg_araddr_i
, input cfg_rready_i
// Outputs
, output cfg_awready_o
, output cfg_wready_o
, output cfg_bvalid_o
, output [ 1:0] cfg_bresp_o
, output cfg_arready_o
, output cfg_rvalid_o
, output [31:0] cfg_rdata_o
, output [ 1:0] cfg_rresp_o
, output signed [15:0] channel_a
, output signed [15:0] channel_b
);
//-----------------------------------------------------------------
// Retime write data
//-----------------------------------------------------------------
reg [31:0] wr_data_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i) wr_data_q <= 32'b0;
else wr_data_q <= cfg_wdata_i;
//-----------------------------------------------------------------
// Request Logic
//-----------------------------------------------------------------
wire read_en_w = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = cfg_awvalid_i & cfg_awready_o;
//-----------------------------------------------------------------
// Accept Logic
//-----------------------------------------------------------------
assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i;
assign cfg_wready_o = cfg_awready_o;
//-----------------------------------------------------------------
// BVALID
//-----------------------------------------------------------------
reg bvalid_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i) bvalid_q <= 1'b0;
else if (write_en_w) bvalid_q <= 1'b1;
else if (cfg_bready_i) bvalid_q <= 1'b0;
assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o = 2'b0;
reg signed [15:0] channel_a;
reg signed [15:0] channel_b;
always @(posedge clk_i or posedge rst_i)
if (rst_i) bvalid_q <= 1'b0;
else if (write_en_w) begin
bvalid_q <= 1'b1;
if (cfg_awaddr_i[2] == 0) channel_a <= cfg_wdata_i[15:0];
else channel_b <= cfg_wdata_i[15:0];
end else if (cfg_bready_i) bvalid_q <= 1'b0;
endmodule
| 7.136113 |
module ASYNC_CMP #(
parameter ASIZE = 4
) (
input wrst_n, //write reset
input [ASIZE-1:0] wptr, //write address
input [ASIZE-1:0] rptr, //read address
output aempty_n, //almost empty
output afull_n //almost full
);
reg direction;
wire dirset_n = ~((wptr[ASIZE-1] ^ rptr[ASIZE-2]) & ~(wptr[ASIZE-2] ^ rptr[ASIZE-1]));
wire dirclr_n = ~(~((wptr[ASIZE-1] ^ rptr[ASIZE-2]) & (wptr[ASIZE-2] ^ rptr[ASIZE-1])) | ~wrst_n);
always @(negedge dirset_n or negedge dirclr_n)
if (dirclr_n == 1'b0) direction <= 1'b0; //going empty
else direction <= 1'b1; //going full
assign aempty_n = ~((wptr == rptr) & (direction == 1'b0));
assign afull_n = ~((wptr == rptr) & (direction == 1'b1));
endmodule
| 7.651156 |
module async_controller (
input clk,
WE,
EN,
input [ 2:0] addr,
input [ 3:0] data_write,
inout [15:0] MemDB,
output RamAdv,
RamClk,
RamCS,
MemOE,
MemWR,
RamLB,
RamUB,
output [ 3:0] an,
output [ 7:0] seg,
// output [15:0] data_read,
output [22:0] MemAdr
);
wire systemClock;
assign systemClock = clk;
assign MemAdr = {{20{1'b0}}, addr};
reg WR, CS;
reg [15:0] data_read;
assign MemDB = (WR) ? {data_write, data_write, data_write, data_write} : 16'bZ;
always @(posedge systemClock) begin
data_read = MemDB;
WR <= WE;
CS <= EN;
end
async_fsm async (
systemClock,
WR,
CS,
RamAdv,
RamClk,
RamCS,
MemOE,
MemWR,
RamLB,
RamUB
);
disp_hex_mux hex_display (
systemClock,
1'b0,
data_read[15:12],
data_read[11:8],
data_read[7:4],
data_read[3:0],
4'hf,
an,
seg
);
endmodule
| 7.420594 |
module async_fsm (
input clk,
WR,
CS,
output RamAdv,
RamClk,
RamCS,
MemOE,
MemWR,
RamLB,
RamUB
);
localparam
READY = 2'b00,
READ = 2'b01,
WRITE = 2'b10,
INACTIVE = 7'b1111111,
CYCLES_TO_WAIT = 3'd6;
reg [1:0] current, next;
reg [2:0] cycle_count;
reg [6:0] controls;
assign {RamAdv, RamClk, RamCS, MemOE, MemWR, RamLB, RamUB} = controls;
initial begin
current <= READY;
next <= READY;
cycle_count <= 3'd0;
controls <= INACTIVE;
end
always @(posedge clk) begin
current <= next;
cycle_count <= (READY == current) ? 3'd0 : cycle_count + 1'b1;
end
always @(*) begin
case (current)
READY: begin
next <= (CS) ? ((WR) ? WRITE : READ) : READY;
controls <= INACTIVE;
end
READ: begin
next <= (CYCLES_TO_WAIT == cycle_count) ? READY : READ;
controls <= 7'b0000100;
end
WRITE: begin
next <= (CYCLES_TO_WAIT == cycle_count) ? READY : WRITE;
controls <= 7'b0001000;
end
default: begin
next <= READY;
controls <= INACTIVE;
end
endcase
end
endmodule
| 7.61829 |
module async_dpram_40W_32D (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [39:0] data;
input [4:0] rdaddress;
input rdclock;
input [4:0] wraddress;
input wrclock;
input wren;
output [39:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [39:0] sub_wire0;
wire [39:0] q = sub_wire0[39:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({40{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 40,
altsyncram_component.width_b = 40,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.54746 |
module async_d_ff (
clk,
D,
reset,
Q
);
input clk, D, reset;
output reg Q;
always @(posedge clk, negedge reset)
if (!reset) Q = 0;
else Q = D;
endmodule
| 6.607682 |
module async_fifo #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in
);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem[FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
assign Data_out = Mem[pNextWordToRead];
// always @ (posedge RClk)
// if (!PresetEmpty)
// Data_out <= Mem[pNextWordToRead];
// if (ReadEn_in & !Empty_out)
//'Data_in' logic:
always @(posedge WClk) if (WriteEn_in & !Full_out) Mem[pNextWordToWrite] <= Data_in;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
GrayCounter #(
.COUNTER_WIDTH(ADDRESS_WIDTH)
) GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
GrayCounter #(
.COUNTER_WIDTH(ADDRESS_WIDTH)
) GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @(Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in) Status = 0; //Going 'Empty'.
else if (Set_Status) Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @(posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull) Full_out <= 1;
else Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @(posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty) Empty_out <= 1;
else Empty_out <= 0;
endmodule
| 8.811691 |
module async_fifo_114 (
input wclk,
input wrst,
input [9:0] din,
input wput,
output reg full,
input rclk,
input rrst,
output reg [9:0] dout,
input rget,
output reg empty
);
localparam SIZE = 4'ha;
localparam DEPTH = 5'h10;
localparam ADDR_SIZE = 3'h4;
reg [3:0] M_waddr_d, M_waddr_q = 1'h0;
reg [7:0] M_wsync_d, M_wsync_q = 1'h0;
reg [3:0] M_raddr_d, M_raddr_q = 1'h0;
reg [7:0] M_rsync_d, M_rsync_q = 1'h0;
wire [10-1:0] M_ram_read_data;
reg [ 1-1:0] M_ram_wclk;
reg [ 4-1:0] M_ram_waddr;
reg [10-1:0] M_ram_write_data;
reg [ 1-1:0] M_ram_write_en;
reg [ 1-1:0] M_ram_rclk;
reg [ 4-1:0] M_ram_raddr;
simple_dual_ram_125 #(
.SIZE (4'ha),
.DEPTH(5'h10)
) ram (
.wclk(M_ram_wclk),
.waddr(M_ram_waddr),
.write_data(M_ram_write_data),
.write_en(M_ram_write_en),
.rclk(M_ram_rclk),
.raddr(M_ram_raddr),
.read_data(M_ram_read_data)
);
reg [3:0] waddr_gray;
reg [3:0] wnext_gray;
reg [3:0] raddr_gray;
reg wrdy;
reg rrdy;
always @* begin
M_rsync_d = M_rsync_q;
M_wsync_d = M_wsync_q;
M_raddr_d = M_raddr_q;
M_waddr_d = M_waddr_q;
M_ram_wclk = wclk;
M_ram_rclk = rclk;
M_ram_write_en = 1'h0;
waddr_gray = (M_waddr_q >> 1'h1) ^ M_waddr_q;
wnext_gray = ((M_waddr_q + 1'h1) >> 1'h1) ^ (M_waddr_q + 1'h1);
raddr_gray = (M_raddr_q >> 1'h1) ^ M_raddr_q;
M_rsync_d = {M_rsync_q[0+3-:4], waddr_gray};
M_wsync_d = {M_wsync_q[0+3-:4], raddr_gray};
wrdy = wnext_gray != M_wsync_q[4+3-:4];
rrdy = raddr_gray != M_rsync_q[4+3-:4];
full = !wrdy;
empty = !rrdy;
M_ram_waddr = M_waddr_q;
M_ram_raddr = M_raddr_q;
M_ram_write_data = din;
if (wput && wrdy) begin
M_waddr_d = M_waddr_q + 1'h1;
M_ram_write_en = 1'h1;
end
if (rget && rrdy) begin
M_raddr_d = M_raddr_q + 1'h1;
M_ram_raddr = M_raddr_q + 1'h1;
end
dout = M_ram_read_data;
end
always @(posedge rclk) begin
if (rrst == 1'b1) begin
M_raddr_q <= 1'h0;
M_rsync_q <= 1'h0;
end else begin
M_raddr_q <= M_raddr_d;
M_rsync_q <= M_rsync_d;
end
end
always @(posedge wclk) begin
if (wrst == 1'b1) begin
M_waddr_q <= 1'h0;
M_wsync_q <= 1'h0;
end else begin
M_waddr_q <= M_waddr_d;
M_wsync_q <= M_wsync_d;
end
end
endmodule
| 6.86723 |
module async_fifo_256x72_to_36 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
almost_full,
dout,
empty,
full,
rd_data_count
);
input [71 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output almost_full;
output [35 : 0] dout;
output empty;
output full;
output [6 : 0] rd_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(72),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(253),
.C_PROG_FULL_THRESH_NEGATE_VAL(252),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(7),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(7),
.C_WR_DEPTH(256),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(8),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.ALMOST_FULL(almost_full),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.RD_DATA_COUNT(rd_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 7.438764 |
module async_fifo_256x72_to_36 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull
);
input aclr;
input [71:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.438764 |
module async_fifo_512x36_progfull_500 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
prog_full,
rd_data_count,
wr_data_count
);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
output prog_full;
output [8 : 0] rd_data_count;
output [8 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(500),
.C_PROG_FULL_THRESH_NEGATE_VAL(499),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.PROG_FULL(prog_full),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 7.57829 |
module async_fifo_512x36_to_72_progfull_500 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
prog_full,
rd_data_count,
wr_data_count
);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [71 : 0] dout;
output empty;
output full;
output prog_full;
output [8 : 0] rd_data_count;
output [8 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(72),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(500),
.C_PROG_FULL_THRESH_NEGATE_VAL(499),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(256),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(8),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.PROG_FULL(prog_full),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 7.57829 |
module async_fifo_512x36_to_72_progfull_500 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [71:0] q;
output rdempty;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.57829 |
module async_fifo_64by16 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
valid
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1021),
.C_PROG_FULL_THRESH_NEGATE_VAL(1020),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.VALID(valid),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 7.273335 |
module async_fifo_86 (
input wclk,
input wrst,
input [23:0] din,
input wput,
output reg full,
input rclk,
input rrst,
output reg [23:0] dout,
input rget,
output reg empty
);
localparam SIZE = 5'h18;
localparam DEPTH = 7'h40;
localparam ADDR_SIZE = 3'h6;
reg [5:0] M_waddr_d, M_waddr_q = 1'h0;
reg [11:0] M_wsync_d, M_wsync_q = 1'h0;
reg [5:0] M_raddr_d, M_raddr_q = 1'h0;
reg [11:0] M_rsync_d, M_rsync_q = 1'h0;
wire [24-1:0] M_ram_read_data;
reg [ 1-1:0] M_ram_wclk;
reg [ 6-1:0] M_ram_waddr;
reg [24-1:0] M_ram_write_data;
reg [ 1-1:0] M_ram_write_en;
reg [ 1-1:0] M_ram_rclk;
reg [ 6-1:0] M_ram_raddr;
simple_dual_ram_100 #(
.SIZE (5'h18),
.DEPTH(7'h40)
) ram (
.wclk(M_ram_wclk),
.waddr(M_ram_waddr),
.write_data(M_ram_write_data),
.write_en(M_ram_write_en),
.rclk(M_ram_rclk),
.raddr(M_ram_raddr),
.read_data(M_ram_read_data)
);
reg [5:0] waddr_gray;
reg [5:0] wnext_gray;
reg [5:0] raddr_gray;
reg wrdy;
reg rrdy;
always @* begin
M_rsync_d = M_rsync_q;
M_wsync_d = M_wsync_q;
M_raddr_d = M_raddr_q;
M_waddr_d = M_waddr_q;
M_ram_wclk = wclk;
M_ram_rclk = rclk;
M_ram_write_en = 1'h0;
waddr_gray = (M_waddr_q >> 1'h1) ^ M_waddr_q;
wnext_gray = ((M_waddr_q + 1'h1) >> 1'h1) ^ (M_waddr_q + 1'h1);
raddr_gray = (M_raddr_q >> 1'h1) ^ M_raddr_q;
M_rsync_d = {M_rsync_q[0+5-:6], waddr_gray};
M_wsync_d = {M_wsync_q[0+5-:6], raddr_gray};
wrdy = wnext_gray != M_wsync_q[6+5-:6];
rrdy = raddr_gray != M_rsync_q[6+5-:6];
full = !wrdy;
empty = !rrdy;
M_ram_waddr = M_waddr_q;
M_ram_raddr = M_raddr_q;
M_ram_write_data = din;
if (wput && wrdy) begin
M_waddr_d = M_waddr_q + 1'h1;
M_ram_write_en = 1'h1;
end
if (rget && rrdy) begin
M_raddr_d = M_raddr_q + 1'h1;
M_ram_raddr = M_raddr_q + 1'h1;
end
dout = M_ram_read_data;
end
always @(posedge rclk) begin
if (rrst == 1'b1) begin
M_raddr_q <= 1'h0;
M_rsync_q <= 1'h0;
end else begin
M_raddr_q <= M_raddr_d;
M_rsync_q <= M_rsync_d;
end
end
always @(posedge wclk) begin
if (wrst == 1'b1) begin
M_waddr_q <= 1'h0;
M_wsync_q <= 1'h0;
end else begin
M_waddr_q <= M_waddr_d;
M_wsync_q <= M_wsync_d;
end
end
endmodule
| 6.8431 |
module vfifo_dual_port_ram_dc_dw (
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk_a, clk_b;
reg [(DATA_WIDTH-1):0] q_b;
reg [ DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @(posedge clk_a) begin
q_a <= ram[adr_a];
if (we_a) ram[adr_a] <= d_a;
end
always @(posedge clk_b) begin
q_b <= ram[adr_b];
if (we_b) ram[adr_b] <= d_b;
end
endmodule
| 7.980715 |
module dff_sr (
aclr,
aset,
clock,
data,
q
);
input aclr;
input aset;
input clock;
input data;
output reg q;
always @(posedge clock or posedge aclr or posedge aset)
if (aclr) q <= 1'b0;
else if (aset) q <= 1'b1;
else q <= data;
endmodule
| 6.823625 |
module versatile_fifo_async_cmp (
wptr,
rptr,
fifo_empty,
fifo_full,
wclk,
rclk,
rst
);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH - 1;
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
reg direction;
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @(wptr[N:N-1] or rptr[N:N-1])
case ({
wptr[N:N-1], rptr[N:N-1]
})
{Q1, Q2} : direction_set <= 1'b1;
{Q2, Q3} : direction_set <= 1'b1;
{Q3, Q4} : direction_set <= 1'b1;
{Q4, Q1} : direction_set <= 1'b1;
default: direction_set <= 1'b0;
endcase
// direction_clear
always @(wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst) direction_clr <= 1'b1;
else
case ({
wptr[N:N-1], rptr[N:N-1]
})
{Q2, Q1} : direction_clr <= 1'b1;
{Q3, Q2} : direction_clr <= 1'b1;
{Q4, Q3} : direction_clr <= 1'b1;
{Q1, Q4} : direction_clr <= 1'b1;
default: direction_clr <= 1'b0;
endcase
always @(posedge direction_set or posedge direction_clr)
if (direction_clr) direction <= going_empty;
else direction <= going_full;
assign async_empty = (wptr == rptr) && (direction == going_empty);
assign async_full = (wptr == rptr) && (direction == going_full);
dff_sr dff_sr_empty0 (
.aclr(rst),
.aset(async_full),
.clock(wclk),
.data(async_full),
.q(fifo_full2)
);
dff_sr dff_sr_empty1 (
.aclr(rst),
.aset(async_full),
.clock(wclk),
.data(fifo_full2),
.q(fifo_full)
);
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @(posedge rclk or posedge async_empty)
if (async_empty) {fifo_empty, fifo_empty2} <= 2'b11;
else {fifo_empty, fifo_empty2} <= {fifo_empty2, async_empty};
endmodule
| 7.199743 |
module async_fifo_dw_simplex_top (
// a side
a_d,
a_wr,
a_fifo_full,
a_q,
a_rd,
a_fifo_empty,
a_clk,
a_rst,
// b side
b_d,
b_wr,
b_fifo_full,
b_q,
b_rd,
b_fifo_empty,
b_clk,
b_rst
);
parameter data_width = 18;
parameter addr_width = 4;
// a side
input [data_width-1:0] a_d;
input a_wr;
output a_fifo_full;
output [data_width-1:0] a_q;
input a_rd;
output a_fifo_empty;
input a_clk;
input a_rst;
// b side
input [data_width-1:0] b_d;
input b_wr;
output b_fifo_full;
output [data_width-1:0] b_q;
input b_rd;
output b_fifo_empty;
input b_clk;
input b_rst;
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
adr_gen #(
.length(addr_width)
) fifo_a_wr_adr (
.cke(a_wr),
.q(a_wadr),
.q_bin(a_wadr_bin),
.rst(a_rst),
.clk(a_clk)
);
adr_gen #(
.length(addr_width)
) fifo_a_rd_adr (
.cke(a_rd),
.q(a_radr),
.q_bin(a_radr_bin),
.rst(a_rst),
.clk(a_clk)
);
adr_gen #(
.length(addr_width)
) fifo_b_wr_adr (
.cke(b_wr),
.q(b_wadr),
.q_bin(b_wadr_bin),
.rst(b_rst),
.clk(b_clk)
);
adr_gen #(
.length(addr_width)
) fifo_b_rd_adr (
.cke(b_rd),
.q(b_radr),
.q_bin(b_radr_bin),
.rst(b_rst),
.clk(b_clk)
);
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0, a_wadr_bin} : {1'b1, a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1, b_wadr_bin} : {1'b0, b_radr_bin};
vfifo_dual_port_ram_dc_dw #(
.DATA_WIDTH(data_width),
.ADDR_WIDTH(addr_width + 1)
) dpram (
.d_a (a_d),
.q_a (a_q),
.adr_a(a_dpram_adr),
.we_a (a_wr),
.clk_a(a_clk),
.d_b (b_d),
.q_b (b_q),
.adr_b(b_dpram_adr),
.we_b (b_wr),
.clk_b(b_clk)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(addr_width)
) cmp1 (
.wptr(a_wadr),
.rptr(b_radr),
.fifo_empty(b_fifo_empty),
.fifo_full(a_fifo_full),
.wclk(a_clk),
.rclk(b_clk),
.rst(a_rst)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(addr_width)
) cmp2 (
.wptr(b_wadr),
.rptr(a_radr),
.fifo_empty(a_fifo_empty),
.fifo_full(b_fifo_full),
.wclk(b_clk),
.rclk(a_clk),
.rst(b_rst)
);
endmodule
| 8.957407 |
module async_fifo_dw_simplex_top (
// a side
a_d,
a_wr,
a_fifo_full,
a_q,
a_rd,
a_fifo_empty,
a_clk,
a_rst,
// b side
b_d,
b_wr,
b_fifo_full,
b_q,
b_rd,
b_fifo_empty,
b_clk,
b_rst
);
parameter data_width = 18;
parameter addr_width = 4;
// a side
input [data_width-1:0] a_d;
input a_wr;
output a_fifo_full;
output [data_width-1:0] a_q;
input a_rd;
output a_fifo_empty;
input a_clk;
input a_rst;
// b side
input [data_width-1:0] b_d;
input b_wr;
output b_fifo_full;
output [data_width-1:0] b_q;
input b_rd;
output b_fifo_empty;
input b_clk;
input b_rst;
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
adr_gen #(
.length(addr_width)
) fifo_a_wr_adr (
.cke(a_wr),
.q(a_wadr),
.q_bin(a_wadr_bin),
.rst(a_rst),
.clk(a_clk)
);
adr_gen #(
.length(addr_width)
) fifo_a_rd_adr (
.cke(a_rd),
.q(a_radr),
.q_bin(a_radr_bin),
.rst(a_rst),
.clk(a_clk)
);
adr_gen #(
.length(addr_width)
) fifo_b_wr_adr (
.cke(b_wr),
.q(b_wadr),
.q_bin(b_wadr_bin),
.rst(b_rst),
.clk(b_clk)
);
adr_gen #(
.length(addr_width)
) fifo_b_rd_adr (
.cke(b_rd),
.q(b_radr),
.q_bin(b_radr_bin),
.rst(b_rst),
.clk(b_clk)
);
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0, a_wadr_bin} : {1'b1, a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1, b_wadr_bin} : {1'b0, b_radr_bin};
vfifo_dual_port_ram_dc_dw #(
.DATA_WIDTH(data_width),
.ADDR_WIDTH(addr_width + 1)
) dpram (
.d_a (a_d),
.q_a (a_q),
.adr_a(a_dpram_adr),
.we_a (a_wr),
.clk_a(a_clk),
.d_b (b_d),
.q_b (b_q),
.adr_b(b_dpram_adr),
.we_b (b_wr),
.clk_b(b_clk)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(addr_width)
) cmp1 (
.wptr(a_wadr),
.rptr(b_radr),
.fifo_empty(b_fifo_empty),
.fifo_full(a_fifo_full),
.wclk(a_clk),
.rclk(b_clk),
.rst(a_rst)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(addr_width)
) cmp2 (
.wptr(b_wadr),
.rptr(a_radr),
.fifo_empty(a_fifo_empty),
.fifo_full(b_fifo_full),
.wclk(b_clk),
.rclk(a_clk),
.rst(b_rst)
);
endmodule
| 8.957407 |
module async_fifomem #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4,
parameter WRITE_BLOCK_SIZE = DATA_WIDTH //number of bits for individual write enable
) (
input wire wclk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wdata_i,
input wire [ADDR_WIDTH-1:0] waddr_i,
input wire [ADDR_WIDTH-1:0] raddr_i,
output wire [DATA_WIDTH-1:0] rdata_o
);
reg [DATA_WIDTH-1:0] reg_array[0:(1<<ADDR_WIDTH)-1];
assign rdata_o = reg_array[raddr_i];
always @(posedge wclk_i) begin
if (wr_en_i == 1'b1) begin
reg_array[waddr_i] <= wdata_i;
end
end
endmodule
| 7.170627 |
module async_fifo_fwft #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2 ** clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH + 1)
) (
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "functions.vh"
reg [C_WIDTH-1:0] rData = 0;
reg [C_WIDTH-1:0] rCache = 0;
reg [ 1:0] rCount = 0;
reg rFifoDataValid = 0;
reg rDataValid = 0;
reg rCacheValid = 0;
wire [C_WIDTH-1:0] wData;
wire wEmpty;
wire wRen = RD_EN || (rCount < 2'd2);
assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;
// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will
// determine the memory option).
async_fifo #(
.C_WIDTH(C_WIDTH),
.C_DEPTH(C_DEPTH)
) fifo (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.WR_FULL(WR_FULL),
.RD_EN(wRen),
.RD_DATA(wData),
.RD_EMPTY(wEmpty)
);
always @(posedge RD_CLK) begin
if (RD_RST) begin
rCount <= #1 0;
rDataValid <= #1 0;
rCacheValid <= #1 0;
rFifoDataValid <= #1 0;
end else begin
// Keep track of the count
rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);
// Signals when wData from FIFO is valid
rFifoDataValid <= #1 (wRen & !wEmpty);
// Keep rData up to date
if (rFifoDataValid) begin
if (RD_EN | !rDataValid) begin
rData <= #1 wData;
rDataValid <= #1 1'd1;
rCacheValid <= #1 1'd0;
end else begin
rCacheValid <= #1 1'd1;
end
rCache <= #1 wData;
end else begin
if (RD_EN | !rDataValid) begin
rData <= #1 rCache;
rDataValid <= #1 rCacheValid;
rCacheValid <= #1 1'd0;
end
end
end
end
endmodule
| 8.448902 |
module async_fifo_generator_v2_2_33x16 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
valid
);
input [32 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [32 : 0] dout;
output empty;
output full;
output valid;
// synopsys translate_off
FIFO_GENERATOR_V2_2 #(0, // c_common_clock
0, // c_count_type
2, // c_data_count_width
"BlankString", // c_default_value
33, // c_din_width
"0", // c_dout_rst_val
33, // c_dout_width
0, // c_enable_rlocs
"virtex2p", // c_family
0, // c_has_almost_empty
0, // c_has_almost_full
0, // c_has_backup
0, // c_has_data_count
0, // c_has_meminit_file
0, // c_has_overflow
0, // c_has_rd_data_count
0, // c_has_rd_rst
1, // c_has_rst
0, // c_has_underflow
1, // c_has_valid
0, // c_has_wr_ack
0, // c_has_wr_data_count
0, // c_has_wr_rst
2, // c_implementation_type
0, // c_init_wr_pntr_val
2, // c_memory_type
"BlankString", // c_mif_file_name
0, // c_optimization_mode
0, // c_overflow_low
1, // c_preload_latency
0, // c_preload_regs
512, // c_prim_fifo_type
4, // c_prog_empty_thresh_assert_val
4, // c_prog_empty_thresh_negate_val
0, // c_prog_empty_type
12, // c_prog_full_thresh_assert_val
12, // c_prog_full_thresh_negate_val
0, // c_prog_full_type
2, // c_rd_data_count_width
16, // c_rd_depth
4, // c_rd_pntr_width
0, // c_underflow_low
0, // c_use_fifo16_flags
0, // c_valid_low
0, // c_wr_ack_low
2, // c_wr_data_count_width
16, // c_wr_depth
4, // c_wr_pntr_width
1) // c_wr_response_latency
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.VALID(valid),
.CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT()
);
// synopsys translate_on
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of async_fifo_generator_v2_2_33x16 is "true"
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of async_fifo_generator_v2_2_33x16 is "black_box"
endmodule
| 8.434118 |
module async_fifo_in #(
parameter DATA_WIDTH = 16, //data width
parameter ADDR_WIDTH = 3, //adress width
parameter ALMOST_FULL_BUFFER = 2 //number of free entries until almost_full
) (
input wire aresetn_i,
input wire scan_mode_i,
output wire [ ADDR_WIDTH:0] wr_ptr_o, //to async_fifo_out
output wire [DATA_WIDTH-1:0] rdata_o, //to async_fifo_out
input wire wclk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wdata_i,
input wire [ ADDR_WIDTH:0] rd_ptr_i, //from async_fifo_out
output wire walmost_full_o,
output wire wfull_o
);
wire wresetn;
wire [ADDR_WIDTH:0] wsync_rd_ptr;
util_reset_sync i_reset_sync_r2w (
.clk_i (wclk_i),
.reset_q_i (aresetn_i),
.scan_mode_i (scan_mode_i),
.sync_reset_q_o(wresetn)
);
util_sync #(
.WIDTH(ADDR_WIDTH + 1)
) i_sync_r2w (
.clk_i (wclk_i),
.reset_n_i(wresetn),
.data_i (rd_ptr_i),
.data_o (wsync_rd_ptr)
);
async_fifo_wptr_full_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH),
.ALMOST_FULL_BUFFER(ALMOST_FULL_BUFFER)
) i_wptr_full_ctrl (
.wclk_i (wclk_i),
.wresetn_i (wresetn),
.wr_en_i (wr_en_i),
.wsync_rd_ptr_i(wsync_rd_ptr),
.walmost_full_o(walmost_full_o),
.wfull_o (wfull_o),
.wr_ptr_o (wr_ptr_o)
);
// calculate adresses out of grey code pointer
wire raddr_msb = rd_ptr_i[ADDR_WIDTH] ^ rd_ptr_i[ADDR_WIDTH-1];
wire waddr_msb = wr_ptr_o[ADDR_WIDTH] ^ wr_ptr_o[ADDR_WIDTH-1];
wire [ADDR_WIDTH-1:0] raddr;
wire [ADDR_WIDTH-1:0] waddr;
generate
if (ADDR_WIDTH >= 2) begin : GEN_2PLUS
assign raddr = {raddr_msb, rd_ptr_i[ADDR_WIDTH-2:0]};
assign waddr = {waddr_msb, wr_ptr_o[ADDR_WIDTH-2:0]};
end else begin : GEN_1
assign raddr = raddr_msb;
assign waddr = waddr_msb;
end
endgenerate
async_fifomem #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) i_async_fifomem (
.wclk_i (wclk_i),
.waddr_i(waddr),
.raddr_i(raddr),
.wr_en_i(wr_en_i && ~wfull_o),
.wdata_i(wdata_i),
.rdata_o(rdata_o)
);
endmodule
| 6.513425 |
module async_fifo_in_288b_out_72b (
//-----------------------------------
//wr intfc
input [287:0] din,
input wr_en,
output almost_full,
output full,
input wr_clk,
//-----------------------------------
//rd intfc
input rd_en,
output almost_empty,
output empty,
output [71:0] dout,
input rd_clk,
//-----------------------------------
// async reset
input rst
);
async_fifo_in_144b_out_36b high_half (
//-----------------------------------
//wr intfc
//input:
.din ({din[287:252], din[215:180], din[143:108], din[71:36]}),
.wr_en(wr_en),
//output:
.almost_full(almost_full_hi),
.full (full_hi),
//clk:
.wr_clk(wr_clk),
//-----------------------------------
//rd intfc
//input:
.rd_en(rd_en),
//output:
.almost_empty(almost_empty_hi),
.empty (empty_hi),
.dout (dout[71:36]),
//clk:
.rd_clk(rd_clk),
//-----------------------------------
// async rst
.rst(rst)
);
async_fifo_in_144b_out_36b low_half (
//-----------------------------------
//wr intfc
//input:
.din ({din[251:216], din[179:144], din[107:72], din[35:0]}),
.wr_en(wr_en),
//output:
.almost_full(almost_full_lo),
.full (full_lo),
//clk:
.wr_clk(wr_clk),
//-----------------------------------
//rd intfc
//input:
.rd_en(rd_en),
//output:
.almost_empty(almost_empty_lo),
.empty (empty_lo),
.dout (dout[35:0]),
//clk:
.rd_clk(rd_clk),
//-----------------------------------
// async rst
.rst(rst)
);
assign almost_full = almost_full_hi | almost_full_lo;
assign full = full_hi | full_lo;
assign almost_empty = almost_empty_hi | almost_empty_lo;
assign empty = empty_hi | empty_lo;
endmodule
| 6.513425 |
module async_fifo_in_72b_out_144b (
//-----------------------------
//wr intfc
//din is one clk cycle later than wr_en due to set-up time violation fix
input [71:0] din,
input wr_en,
output full,
input wr_clk,
input wr_reset,
input wr_clear_residue,
//-----------------------------
//rd intfc
input rd_en,
output [143:0] dout,
output empty,
input rd_clk,
//--------------------------
// async reset
input arst
);
reg [71:0] din_1, din_1_nxt;
reg din_1_vld;
reg din_1_vld_a1, din_1_vld_a1_nxt;
reg fifo_wr_en_nxt, fifo_wr_en;
wire fifo_full;
assign full = din_1_vld_a1 & fifo_full;
async_fifo_144b async_fifo_144b_u (
//-----------------------------
//wr intfc
//input:
.din ({din_1, din}),
.wr_en(fifo_wr_en),
//output:
.prog_full(),
.full (fifo_full),
//wr clk
.wr_clk(wr_clk),
//-----------------------------
//rd intfc
//input:
.rd_en(rd_en),
//output:
.dout (dout),
.prog_empty(),
.empty (empty),
//rd clk
.rd_clk(rd_clk),
//--------------------------
// async reset
.rst(arst)
);
//-------------------------------------------------
// Logic in wr_clk domain
always @(*) begin
//---------------------------------
// pkt rd: from 64-bit dram to 72-bit bram
fifo_wr_en_nxt = 1'b0;
din_1_vld_a1_nxt = din_1_vld_a1;
din_1_nxt = din_1;
if (wr_en) begin
if (~din_1_vld_a1) begin
//will load din_1 one cycle later
din_1_vld_a1_nxt = 1'b1;
end else begin
//will write to fifo_144b_u.din one cycle later
fifo_wr_en_nxt = 1'b1;
din_1_vld_a1_nxt = 1'b0;
end
end // if ( wr_en )
if ((~din_1_vld) & (din_1_vld_a1)) din_1_nxt = din;
if (wr_clear_residue) begin
din_1_vld_a1_nxt = 1'b0;
end
end // always @ (*)
always @(posedge wr_clk) begin
if (wr_reset) begin
din_1 <= 72'h0;
din_1_vld_a1 <= 1'b0;
din_1_vld <= 1'b0;
fifo_wr_en <= 1'b0;
end else begin
din_1 <= din_1_nxt;
din_1_vld_a1 <= din_1_vld_a1_nxt;
din_1_vld <= din_1_vld_a1;
fifo_wr_en <= fifo_wr_en_nxt;
end
end // always @ (posedge wr_clk)
endmodule
| 6.513425 |
module async_fifo_in_72b_out_288b (
//-----------------------------
//wr intfc
//din is one clk cycle later than wr_en due to set-up time violation fix
input [71:0] din,
input wr_en,
output full,
input wr_clk,
input wr_reset,
input wr_clear_residue,
//-----------------------------
//rd intfc
input rd_en,
output [287:0] dout,
output empty,
input rd_clk,
//--------------------------
// async reset
input arst
);
reg [215:0] din_1, din_1_nxt;
reg din_1_latch_a1, din_1_latch_a1_nxt;
reg [1:0] din_1_cnt_a1, din_1_cnt_a1_nxt;
reg fifo_wr_en_nxt, fifo_wr_en;
wire fifo_prog_full_1, fifo_prog_full_0;
wire fifo_prog_full = fifo_prog_full_1 | fifo_prog_full_0;
assign full = (din_1_cnt_a1 == 3) & fifo_prog_full;
wire empty_1, empty_0;
assign empty = empty_1 | empty_0;
async_fifo_144b async_fifo_144b_u0 (
//-----------------------------
//wr intfc
//input:
.din ({din_1[71:0], din}),
.wr_en(fifo_wr_en),
//output:
.prog_full(fifo_prog_full_0),
.full (),
//wr clk
.wr_clk(wr_clk),
//-----------------------------
//rd intfc
//input:
.rd_en(rd_en),
//output:
.dout (dout[143:0]),
.prog_empty(),
.empty (empty_0),
//rd clk
.rd_clk(rd_clk),
//--------------------------
// async reset
.rst(arst)
);
async_fifo_144b async_fifo_144b_u1 (
//-----------------------------
//wr intfc
//input:
.din (din_1[215:72]),
.wr_en(fifo_wr_en),
//output:
.prog_full(fifo_prog_full_1),
.full (),
//wr clk
.wr_clk(wr_clk),
//-----------------------------
//rd intfc
//input:
.rd_en(rd_en),
//output:
.dout (dout[287:144]),
.prog_empty(),
.empty (empty_1),
//rd clk
.rd_clk(rd_clk),
//--------------------------
// async reset
.rst(arst)
);
//-------------------------------------------------
// Logic in wr_clk domain
always @(*) begin
fifo_wr_en_nxt = 1'b0;
din_1_latch_a1_nxt = 1'b0;
din_1_cnt_a1_nxt = din_1_cnt_a1;
din_1_nxt = din_1;
if (wr_en) begin
if (din_1_cnt_a1 < 3) begin
//will load din_1 one cycle later
din_1_latch_a1_nxt = 1'b1;
din_1_cnt_a1_nxt = din_1_cnt_a1 + 1;
end else begin
//will write to fifo_144b_u.din one cycle later
fifo_wr_en_nxt = 1'b1;
din_1_cnt_a1_nxt = 2'b0;
end
end // if ( wr_en )
if (din_1_latch_a1) din_1_nxt = {din_1[215:0], din};
if (wr_clear_residue) begin
din_1_cnt_a1_nxt = 2'b0;
end
end // always @ (*)
always @(posedge wr_clk) begin
if (wr_reset) begin
din_1 <= 216'h0;
din_1_latch_a1 <= 1'b0;
din_1_cnt_a1 <= 2'b0;
fifo_wr_en <= 1'b0;
end else begin
din_1 <= din_1_nxt;
din_1_latch_a1 <= din_1_latch_a1_nxt;
din_1_cnt_a1 <= din_1_cnt_a1_nxt;
fifo_wr_en <= fifo_wr_en_nxt;
end
end // always @ (posedge wr_clk)
endmodule
| 6.513425 |
module async_fifo_mq (
d,
fifo_full,
write,
write_enable,
clk1,
rst1,
q,
fifo_empty,
read,
read_enable,
clk2,
rst2
);
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
input [data_width-1:0] d;
output [0:nr_of_queues-1] fifo_full;
input write;
input [0:nr_of_queues-1] write_enable;
input clk1;
input rst1;
output [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
input read;
input [0:nr_of_queues-1] read_enable;
input clk2;
input rst2;
wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_gray[0:nr_of_queues-1];
reg [a_lo_size-1:0] wadr;
reg [a_lo_size-1:0] radr;
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
genvar i;
integer j, k, l;
function [a_lo_size-1:0] onehot2bin;
input [0:nr_of_queues-1] a;
integer i;
begin
onehot2bin = {a_lo_size{1'b0}};
for (i = 1; i < nr_of_queues; i = i + 1) begin
if (a[i]) onehot2bin = i;
end
end
endfunction
generate
for (i = 0; i < nr_of_queues; i = i + 1) begin : fifo_adr
gray_counter wadrcnt (
.cke(write & write_enable[i]),
.q(fifo_wadr_gray[i]),
.q_bin(fifo_wadr_bin[i]),
.rst(rst1),
.clk(clk1)
);
gray_counter radrcnt (
.cke(read & read_enable[i]),
.q(fifo_radr_gray[i]),
.q_bin(fifo_radr_bin[i]),
.rst(rst2),
.clk(clk2)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(a_lo_size)
) egresscmp (
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.wclk(clk1),
.rclk(clk2),
.rst(rst1)
);
end
endgenerate
// and-or mux write address
always @* begin
wadr = {a_lo_size{1'b0}};
for (j = 0; j < nr_of_queues; j = j + 1) begin
wadr = (fifo_wadr_bin[j] & {a_lo_size{write_enable[j]}}) | wadr;
end
end
// and-or mux read address
always @* begin
radr = {a_lo_size{1'b0}};
for (k = 0; k < nr_of_queues; k = k + 1) begin
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable[k]}}) | radr;
end
end
vfifo_dual_port_ram_dc_sw #(
.DATA_WIDTH(data_width),
.ADDR_WIDTH(a_hi_size + a_lo_size)
) dpram (
.d_a (d),
.adr_a({onehot2bin(write_enable), wadr}),
.we_a (write),
.clk_a(clk1),
.q_b (q),
.adr_b({onehot2bin(read_enable), radr}),
.clk_b(clk2)
);
endmodule
| 7.477422 |
module async_fifo_mq_md (
d,
fifo_full,
write,
write_enable,
clk1,
rst1,
q,
fifo_empty,
read,
read_enable,
clk2,
rst2
);
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
input [data_width*nr_of_queues-1:0] d;
output [0:nr_of_queues-1] fifo_full;
input write;
input [0:nr_of_queues-1] write_enable;
input clk1;
input rst1;
output [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
input read;
input [0:nr_of_queues-1] read_enable;
input clk2;
input rst2;
wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_gray[0:nr_of_queues-1];
reg [a_lo_size-1:0] wadr;
reg [a_lo_size-1:0] radr;
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
genvar i;
integer j, k, l;
function [a_lo_size-1:0] onehot2bin;
input [0:nr_of_queues-1] a;
integer i;
begin
onehot2bin = {a_lo_size{1'b0}};
for (i = 1; i < nr_of_queues; i = i + 1) begin
if (a[i]) onehot2bin = i;
end
end
endfunction
generate
for (i = 0; i < nr_of_queues; i = i + 1) begin : fifo_adr
gray_counter wadrcnt (
.cke(write & write_enable[i]),
.q(fifo_wadr_gray[i]),
.q_bin(fifo_wadr_bin[i]),
.rst(rst1),
.clk(clk1)
);
gray_counter radrcnt (
.cke(read & read_enable[i]),
.q(fifo_radr_gray[i]),
.q_bin(fifo_radr_bin[i]),
.rst(rst2),
.clk(clk2)
);
versatile_fifo_async_cmp #(
.ADDR_WIDTH(a_lo_size)
) egresscmp (
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.wclk(clk1),
.rclk(clk2),
.rst(rst1)
);
end
endgenerate
// and-or mux write address
always @* begin
wadr = {a_lo_size{1'b0}};
for (j = 0; j < nr_of_queues; j = j + 1) begin
wadr = (fifo_wadr_bin[j] & {a_lo_size{write_enable[j]}}) | wadr;
end
end
// and-or mux read address
always @* begin
radr = {a_lo_size{1'b0}};
for (k = 0; k < nr_of_queues; k = k + 1) begin
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable[k]}}) | radr;
end
end
// and-or mux write data
generate
for (i = 0; i < nr_of_queues; i = i + 1) begin : vector2array
assign wdataa[i] = d[(nr_of_queues-i)*data_width-1:(nr_of_queues-1-i)*data_width];
end
endgenerate
always @* begin
wdata = {data_width{1'b0}};
for (l = 0; l < nr_of_queues; l = l + 1) begin
wdata = (wdataa[l] & {data_width{write_enable[l]}}) | wdata;
end
end
vfifo_dual_port_ram_dc_sw #(
.DATA_WIDTH(data_width),
.ADDR_WIDTH(a_hi_size + a_lo_size)
) dpram (
.d_a (wdata),
.adr_a({onehot2bin(write_enable), wadr}),
.we_a (write),
.clk_a(clk1),
.q_b (q),
.adr_b({onehot2bin(read_enable), radr}),
.clk_b(clk2)
);
endmodule
| 7.477422 |
module async_fifo_out #(
parameter DATA_WIDTH = 16, //data width
parameter ADDR_WIDTH = 3, //adress width
parameter ALMOST_EMPTY_BUFFER = 2 //number of written entries until almost_empty
) (
input wire aresetn_i,
input wire scan_mode_i,
input wire rclk_i,
input wire rd_en_i,
output wire [DATA_WIDTH-1:0] rdata_o,
output wire [ ADDR_WIDTH:0] rd_ptr_o, //to async_fifo_in
output wire ralmost_empty_o,
output wire rempty_o,
input wire [ ADDR_WIDTH:0] wr_ptr_i, //from async_fifo_in
input wire [DATA_WIDTH-1:0] rdata_i //from async_fifo_in
);
wire rresetn;
wire [ADDR_WIDTH:0] rsync_wr_ptr;
assign rdata_o = rdata_i;
util_reset_sync i_reset_sync_w2r (
.clk_i (rclk_i),
.reset_q_i (aresetn_i),
.scan_mode_i (scan_mode_i),
.sync_reset_q_o(rresetn)
);
util_sync #(
.WIDTH(ADDR_WIDTH + 1)
) i_sync_w2r (
.clk_i (rclk_i),
.reset_n_i(rresetn),
.data_i (wr_ptr_i),
.data_o (rsync_wr_ptr)
);
async_fifo_rptr_empty_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH),
.ALMOST_EMPTY_BUFFER(ALMOST_EMPTY_BUFFER)
) i_rptr_empty_ctrl (
.rclk_i (rclk_i),
.rresetn_i (rresetn),
.rd_en_i (rd_en_i),
.rsync_wr_ptr_i (rsync_wr_ptr),
.ralmost_empty_o(ralmost_empty_o),
.rempty_o (rempty_o),
.rd_ptr_o (rd_ptr_o)
);
endmodule
| 8.324355 |
module async_fifo_riffa #(
parameter C_WIDTH = 8, // Data bus width
parameter C_DEPTH = 64, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2 ** `CLOG2(C_DEPTH),
parameter C_DEPTH_BITS = `CLOG2(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = `CLOG2(C_REAL_DEPTH + 1)
) (
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
wire wCmpEmpty;
wire wCmpFull;
wire [C_DEPTH_BITS-1:0] wWrPtr;
wire [C_DEPTH_BITS-1:0] wRdPtr;
wire [C_DEPTH_BITS-1:0] wWrPtrP1;
wire [C_DEPTH_BITS-1:0] wRdPtrP1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_2clk_1w_1r #(
.C_RAM_WIDTH(C_WIDTH),
.C_RAM_DEPTH(C_REAL_DEPTH)
) mem (
.CLKA (WR_CLK),
.ADDRA(wWrPtr),
.WEA (WR_EN & !WR_FULL),
.DINA (WR_DATA),
.CLKB (RD_CLK),
.ADDRB(wRdPtr),
.DOUTB(RD_DATA)
);
// Compare the pointers.
async_cmp #(
.C_DEPTH_BITS(C_DEPTH_BITS)
) asyncCompare (
.WR_RST(WR_RST),
.WR_CLK(WR_CLK),
.RD_RST(RD_RST),
.RD_CLK(RD_CLK),
.RD_VALID(RD_EN & !RD_EMPTY),
.WR_VALID(WR_EN & !WR_FULL),
.EMPTY(wCmpEmpty),
.FULL(wCmpFull),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1)
);
// Calculate empty
rd_ptr_empty #(
.C_DEPTH_BITS(C_DEPTH_BITS)
) rdPtrEmpty (
.RD_EMPTY(RD_EMPTY),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1),
.CMP_EMPTY(wCmpEmpty),
.RD_EN(RD_EN),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST)
);
// Calculate full
wr_ptr_full #(
.C_DEPTH_BITS(C_DEPTH_BITS)
) wrPtrFull (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.WR_EN(WR_EN),
.WR_FULL(WR_FULL),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.CMP_FULL(wCmpFull)
);
endmodule
| 8.379812 |
module async_cmp #(
parameter C_DEPTH_BITS = 4,
// Local parameters
parameter N = C_DEPTH_BITS - 1
) (
input WR_RST,
input WR_CLK,
input RD_RST,
input RD_CLK,
input RD_VALID,
input WR_VALID,
output EMPTY,
output FULL,
input [C_DEPTH_BITS-1:0] WR_PTR,
input [C_DEPTH_BITS-1:0] RD_PTR,
input [C_DEPTH_BITS-1:0] WR_PTR_P1,
input [C_DEPTH_BITS-1:0] RD_PTR_P1
);
reg rDir = 0;
wire wDirSet = ((WR_PTR[N] ^ RD_PTR[N-1]) & ~(WR_PTR[N-1] ^ RD_PTR[N]));
wire wDirClr = ((~(WR_PTR[N] ^ RD_PTR[N-1]) & (WR_PTR[N-1] ^ RD_PTR[N])) | WR_RST);
reg rRdValid = 0;
reg rEmpty = 1;
reg rFull = 0;
wire wATBEmpty = ((WR_PTR == RD_PTR_P1) && (RD_VALID | rRdValid));
wire wATBFull = ((WR_PTR_P1 == RD_PTR) && WR_VALID);
wire wEmpty = ((WR_PTR == RD_PTR) && !rDir);
wire wFull = ((WR_PTR == RD_PTR) && rDir);
assign EMPTY = wATBEmpty || rEmpty;
assign FULL = wATBFull || rFull;
always @(posedge wDirSet or posedge wDirClr)
if (wDirClr) rDir <= 1'b0;
else rDir <= 1'b1;
always @(posedge RD_CLK) begin
rEmpty <= (RD_RST ? 1'd1 : wEmpty);
rRdValid <= (RD_RST ? 1'd0 : RD_VALID);
end
always @(posedge WR_CLK) begin
rFull <= (WR_RST ? 1'd0 : wFull);
end
endmodule
| 7.9477 |
module rd_ptr_empty #(
parameter C_DEPTH_BITS = 4
) (
input RD_CLK,
input RD_RST,
input RD_EN,
output RD_EMPTY,
output [C_DEPTH_BITS-1:0] RD_PTR,
output [C_DEPTH_BITS-1:0] RD_PTR_P1,
input CMP_EMPTY
);
reg rEmpty = 1;
reg rEmpty2 = 1;
reg [C_DEPTH_BITS-1:0] rRdPtr = 0;
reg [C_DEPTH_BITS-1:0] rRdPtrP1 = 0;
reg [C_DEPTH_BITS-1:0] rBin = 0;
reg [C_DEPTH_BITS-1:0] rBinP1 = 1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign RD_EMPTY = rEmpty;
assign RD_PTR = rRdPtr;
assign RD_PTR_P1 = rRdPtrP1;
// Gray coded pointer
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rRdPtr <= #1 0;
rRdPtrP1 <= #1 0;
end else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rRdPtr <= #1 wGrayNext;
rRdPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not empty
assign wBinNext = (!rEmpty ? rBin + RD_EN : rBin);
assign wBinNextP1 = (!rEmpty ? rBinP1 + RD_EN : rBinP1);
assign wGrayNext = ((wBinNext >> 1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1 >> 1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge RD_CLK) begin
if (CMP_EMPTY) {rEmpty, rEmpty2} <= #1 2'b11;
else {rEmpty, rEmpty2} <= #1{rEmpty2, CMP_EMPTY};
end
endmodule
| 7.458099 |
module wr_ptr_full #(
parameter C_DEPTH_BITS = 4
) (
input WR_CLK,
input WR_RST,
input WR_EN,
output WR_FULL,
output [C_DEPTH_BITS-1:0] WR_PTR,
output [C_DEPTH_BITS-1:0] WR_PTR_P1,
input CMP_FULL
);
reg rFull = 0;
reg rFull2 = 0;
reg [C_DEPTH_BITS-1:0] rPtr = 0;
reg [C_DEPTH_BITS-1:0] rPtrP1 = 0;
reg [C_DEPTH_BITS-1:0] rBin = 0;
reg [C_DEPTH_BITS-1:0] rBinP1 = 1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign WR_FULL = rFull;
assign WR_PTR = rPtr;
assign WR_PTR_P1 = rPtrP1;
// Gray coded pointer
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rPtr <= #1 0;
rPtrP1 <= #1 0;
end else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rPtr <= #1 wGrayNext;
rPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not full
assign wBinNext = (!rFull ? rBin + WR_EN : rBin);
assign wBinNextP1 = (!rFull ? rBinP1 + WR_EN : rBinP1);
assign wGrayNext = ((wBinNext >> 1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1 >> 1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge WR_CLK) begin
if (WR_RST) {rFull, rFull2} <= #1 2'b00;
else if (CMP_FULL) {rFull, rFull2} <= #1 2'b11;
else {rFull, rFull2} <= #1{rFull2, CMP_FULL};
end
endmodule
| 7.340892 |
module sync_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
parameter C_PROVIDE_COUNT = 0, // Include code for counts
// Local parameters
parameter C_REAL_DEPTH = 2 ** `CLOG2(C_DEPTH),
parameter C_DEPTH_BITS = `CLOG2S(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = `CLOG2S(C_REAL_DEPTH + 1)
) (
input CLK, // Clock
input RST, // Sync reset, active high
input [ C_WIDTH-1:0] WR_DATA, // Write data input
input WR_EN, // Write enable, high active
output [ C_WIDTH-1:0] RD_DATA, // Read data output
input RD_EN, // Read enable, high active
output FULL, // Full condition
output EMPTY, // Empty condition
output [C_DEPTH_P1_BITS-1:0] COUNT // Data count
);
reg [C_DEPTH_BITS:0] rWrPtr = 0, _rWrPtr = 0;
reg [C_DEPTH_BITS:0] rWrPtrPlus1 = 1, _rWrPtrPlus1 = 1;
reg [C_DEPTH_BITS:0] rRdPtr = 0, _rRdPtr = 0;
reg [C_DEPTH_BITS:0] rRdPtrPlus1 = 1, _rRdPtrPlus1 = 1;
reg rFull = 0, _rFull = 0;
reg rEmpty = 1, _rEmpty = 1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_1clk_1w_1r #(
.C_RAM_WIDTH(C_WIDTH),
.C_RAM_DEPTH(C_REAL_DEPTH)
) mem (
.CLK (CLK),
.ADDRA(rWrPtr[C_DEPTH_BITS-1:0]),
.WEA (WR_EN & !rFull),
.DINA (WR_DATA),
.ADDRB(rRdPtr[C_DEPTH_BITS-1:0]),
.DOUTB(RD_DATA)
);
// Write pointer logic.
always @(posedge CLK) begin
if (RST) begin
rWrPtr <= #1 0;
rWrPtrPlus1 <= #1 1;
end else begin
rWrPtr <= #1 _rWrPtr;
rWrPtrPlus1 <= #1 _rWrPtrPlus1;
end
end
always @(*) begin
if (WR_EN & !rFull) begin
_rWrPtr = rWrPtrPlus1;
_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
end else begin
_rWrPtr = rWrPtr;
_rWrPtrPlus1 = rWrPtrPlus1;
end
end
// Read pointer logic.
always @(posedge CLK) begin
if (RST) begin
rRdPtr <= #1 0;
rRdPtrPlus1 <= #1 1;
end else begin
rRdPtr <= #1 _rRdPtr;
rRdPtrPlus1 <= #1 _rRdPtrPlus1;
end
end
always @(*) begin
if (RD_EN & !rEmpty) begin
_rRdPtr = rRdPtrPlus1;
_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
end else begin
_rRdPtr = rRdPtr;
_rRdPtrPlus1 = rRdPtrPlus1;
end
end
// Calculate empty
assign EMPTY = rEmpty;
always @(posedge CLK) begin
rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
end
always @(*) begin
_rEmpty = (rWrPtr == rRdPtr) || (RD_EN && !rEmpty && (rWrPtr == rRdPtrPlus1));
end
// Calculate full
assign FULL = rFull;
always @(posedge CLK) begin
rFull <= #1 (RST ? 1'd0 : _rFull);
end
always @(*) begin
_rFull = ((rWrPtr[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtr[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS])) ||
(WR_EN && (rWrPtrPlus1[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtrPlus1[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS]));
end
generate
if (C_PROVIDE_COUNT) begin : provide_count
reg [C_DEPTH_BITS:0] rCount = 0, _rCount = 0;
assign COUNT = (rFull ? C_REAL_DEPTH[C_DEPTH_P1_BITS-1:0] : rCount);
// Calculate read count
always @(posedge CLK) begin
if (RST) rCount <= #1 0;
else rCount <= #1 _rCount;
end
always @(*) begin
_rCount = (rWrPtr - rRdPtr);
end
end else begin : provide_no_count
assign COUNT = 0;
end
endgenerate
endmodule
| 7.717079 |
module ram_1clk_1w_1r #(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
) (
input CLK,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRB,
input [ C_RAM_WIDTH-1:0] DINA,
output [ C_RAM_WIDTH-1:0] DOUTB
);
localparam C_RAM_ADDR_BITS = `CLOG2S(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA) rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
| 7.362944 |
module ram_2clk_1w_1r #(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
) (
input CLKA,
input CLKB,
input WEA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRA,
input [`CLOG2S(C_RAM_DEPTH)-1:0] ADDRB,
input [ C_RAM_WIDTH-1:0] DINA,
output [ C_RAM_WIDTH-1:0] DOUTB
);
//Local parameters
localparam C_RAM_ADDR_BITS = `CLOG2S(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA) rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
| 7.640135 |
module async_fifo_rptr_empty_ctrl #(
parameter ADDR_WIDTH = 4,
parameter ALMOST_EMPTY_BUFFER = 2
) (
input wire rclk_i,
input wire rresetn_i,
input wire rd_en_i,
input wire [ADDR_WIDTH:0] rsync_wr_ptr_i, //gray coded
output wire ralmost_empty_o,
output wire rempty_o,
output reg [ADDR_WIDTH:0] rd_ptr_o //gray coded
);
// increment buffer to threshold so we can use < instead of <=
localparam ALMOST_EMPTY_THRESHOLD = ALMOST_EMPTY_BUFFER[ADDR_WIDTH:0] + {{(ADDR_WIDTH){1'b0}}, 1'b1};
reg [ADDR_WIDTH:0] rd_ptr_bin;
reg [ADDR_WIDTH:0] next_rd_ptr; //gray coded
reg [ADDR_WIDTH:0] next_rd_ptr_bin;
reg [ADDR_WIDTH:0] rsync_wr_ptr_bin;
wire do_read;
wire [ADDR_WIDTH:0] wr_rd_diff = rsync_wr_ptr_bin - rd_ptr_bin;
integer i;
// calculate and assign next grey pointer
always @(posedge rclk_i or negedge rresetn_i) begin
if (rresetn_i == 1'b0) begin
rd_ptr_o <= 0;
end else begin
rd_ptr_o <= next_rd_ptr;
end
end
// read
assign do_read = rd_en_i & (~rempty_o);
always @(rd_ptr_o or do_read or rsync_wr_ptr_i) begin
//gray to binary code conversion
for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
rd_ptr_bin[i] = ^(rd_ptr_o >> i);
rsync_wr_ptr_bin[i] = ^(rsync_wr_ptr_i >> i);
end
//increment binary rd pointer
next_rd_ptr_bin = rd_ptr_bin + {{(ADDR_WIDTH) {1'b0}}, do_read};
//binary to gray code conversion
next_rd_ptr = (next_rd_ptr_bin >> 1) ^ next_rd_ptr_bin;
end
// empty control signal
assign rempty_o = (rd_ptr_o == rsync_wr_ptr_i) ? 1'b1 : 1'b0;
// almost_empty control signal
assign ralmost_empty_o = wr_rd_diff < ALMOST_EMPTY_THRESHOLD;
endmodule
| 6.943524 |
module async_fifo_tb #(
parameter WIDTH = 8,
DEPTH = 130
) ();
/************* 用取对数的方法计算地址指针的位宽 ************************/
function integer log2b(input integer data); //函数返回类型integer
begin
for (log2b = 0; data > 0; log2b = log2b + 1) data = data >> 1;
log2b = log2b - 1;
end
endfunction
/************************************************************************/
localparam ADDR_W = log2b(DEPTH), DATA_W = WIDTH;
reg rst_n; //异步复位 高电平有效
//写侧信号
reg wrclk; //写时钟
reg wrreq; //写请求
reg [DATA_W-1:0] wrdin; //写数据输入
wire wrfull; //写满标志
wire wrempty; //写空标志
wire [ADDR_W-1:0] wrusedw; //写侧可读数据量
//读侧信号
reg rdclk; //读时钟
reg rdreq; //读请求
wire [DATA_W-1:0] rddout; //读数据输出
wire rdfull; //读满标志
wire rdempty; //读空标志
wire [ADDR_W-1:0] rdusedw; //读侧可读数据量
//时钟周期定义
parameter WRCYCLE = 20, RDCYCLE = 12;
//复位周期定义
parameter RST_TIME = 30;
integer i = 0, j = 0;
//仿真模块例化
async_fifo #(
.FIFO_WIDTH(WIDTH),
.FIFO_DEPTH(DEPTH)
) u_async_fifo (
.rst_n (rst_n), //异步复位 高电平有效
//写侧信号
.wrclk (wrclk), //写时钟
.wrreq (wrreq), //写请求
.wrdin (wrdin), //写数据输入
.wrfull (wrfull), //写满标志
.wrempty(wrempty), //写空标志
.wrusedw(wrusedw), //写时钟域下的可读数据量
//读侧信号
.rdclk (rdclk), //读时钟
.rdreq (rdreq), //读请求
.rddout (rddout), //读数据输出
.rdfull (rdfull), //读满标志
.rdempty(rdempty), //读空标志
.rdusedw(rdusedw) //读时钟域下的可读数据量
);
//产生写时钟
initial begin
fork
wrclk = 1;
#2;
wrclk = 0;
join
forever #(WRCYCLE / 2) wrclk = ~wrclk;
end
//产生读时钟
initial begin
fork
rdclk = 1;
#2;
rdclk = 0;
join
forever #(RDCYCLE / 2) rdclk = ~rdclk;
end
//复位
initial begin
rst_n = 1;
#2;
rst_n = 0;
#RST_TIME;
rst_n = 1;
end
//写侧输入
initial begin
#1;
wrreq = 0; //写请求
wrdin = 0; //写数据输入
#(10 * WRCYCLE);
repeat (5) begin
for (i = 0; i < 500; i = i + 1) begin
wrreq = wrfull ? 1'b0 : {$random}; //写请求
wrdin = {$random}; //写数据输入
#(1 * WRCYCLE);
end
wrreq = 0; //写请求
wrdin = 0; //写数据输入
#(100 * WRCYCLE);
end
#(100 * WRCYCLE);
$stop;
end
//读侧输入
initial begin
#1;
rdreq = 0; //读请求
#(30 * RDCYCLE);
repeat (8) begin
for (j = 0; j < 200; j = j + 1) begin
rdreq = rdempty ? 1'b0 : {$random};
#(1 * RDCYCLE);
end
rdreq = 0;
#(300 * RDCYCLE);
end
end
endmodule
| 6.523155 |
module async_fifo_v1 #(
parameter BUS_WIDTH = 8,
FIFO_DEPTH = 16
) (
input RST,
input CLK_WR,
input CLK_RD,
input [BUS_WIDTH-1:0] DATA_IN,
input WR_EN,
input RD_EN,
input H_FLUSH,
output reg [BUS_WIDTH-1:0] DATA_OUT,
output FULL,
output EMPTY,
output H_FULL
);
parameter PTR_WIDTH = $clog2(FIFO_DEPTH);
integer i = 0;
reg [PTR_WIDTH:0] wr_ptr, rd_ptr;
reg [PTR_WIDTH:0] fifo_count_p;
reg [PTR_WIDTH:0] fifo_count_n;
reg [BUS_WIDTH-1:0] MEM[FIFO_DEPTH-1:0];
// FIFO Counter
always @(*) begin
if (!FULL && WR_EN && fifo_count_p != 'd16) begin
fifo_count_n = fifo_count_p + 1;
end
if (!EMPTY && RD_EN && fifo_count_p != 'd0) begin
fifo_count_n = fifo_count_p - 1;
end
if (H_FLUSH && !EMPTY) begin
fifo_count_n = (fifo_count_p / 2);
end
end
// FIFO Write Module
always @(posedge CLK_WR or posedge RST) begin
wr_ptr <= wr_ptr;
fifo_count_p <= fifo_count_p;
for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
MEM[i] <= MEM[i];
end
if (RST) begin
wr_ptr <= 0;
fifo_count_p <= 0;
end else begin
fifo_count_p <= fifo_count_n;
if (!FULL && WR_EN) begin
wr_ptr <= wr_ptr + 1'b1;
MEM[wr_ptr[PTR_WIDTH-1:0]] <= DATA_IN;
end
end
end
// FIFO Read Module
always @(posedge CLK_RD or posedge RST) begin
rd_ptr <= rd_ptr;
DATA_OUT <= DATA_OUT;
if (RST) begin
rd_ptr <= 0;
end else begin
if (!EMPTY && H_FLUSH) begin
rd_ptr <= rd_ptr + (fifo_count_p - (fifo_count_p / 2));
//if( RD_EN )
//begin
// rd_ptr <= rd_ptr + 1'b1;
// DATA_OUT <= MEM[rd_ptr[PTR_WIDTH-1:0]];
//end
end else if (!EMPTY && RD_EN) begin
rd_ptr <= rd_ptr + 1'b1;
DATA_OUT <= MEM[rd_ptr[PTR_WIDTH-1:0]];
end
end
end
assign FULL = ( rd_ptr[PTR_WIDTH-1:0] == wr_ptr[PTR_WIDTH-1:0] && rd_ptr[PTR_WIDTH] != wr_ptr[PTR_WIDTH] ) ? 1'b1 : 1'b0;
assign EMPTY = ( rd_ptr[PTR_WIDTH-1:0] == wr_ptr[PTR_WIDTH-1:0] && rd_ptr[PTR_WIDTH] == wr_ptr[PTR_WIDTH] ) ? 1'b1 : 1'b0;
assign H_FULL = (fifo_count_p > ((FIFO_DEPTH / 2) - 1)) ? 1'b1 : 1'b0;
initial begin
//$monitor( $time, " Module : RD_PTR : ( %0b, %0d ), WR_PTR : ( %0b, %0d ), fifo_count_p : %0d ", rd_ptr[PTR_WIDTH], rd_ptr[PTR_WIDTH-1:0], wr_ptr[PTR_WIDTH], wr_ptr[PTR_WIDTH-1:0], fifo_count_p );
end
endmodule
| 7.408872 |
module ASYNC_FIFO_WPTR_FULL #(
parameter ADDRSIZE = 4
) (
output reg wfull,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE : 0] wptr,
input [ADDRSIZE : 0] wq2_rptr,
input winc,
wclk,
wrst_n
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) wfull <= 1'b0;
else wfull <= wfull_val;
endmodule
| 7.009131 |
module async_mem ( /*AUTOARG*/
// Outputs
ack,
dout,
// Inputs
req,
addr,
din,
we
);
parameter ACCESS_TIME = 10;
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
localparam CLOCK_PULSE_WIDTH = 5;
input req;
output ack;
input [ADDR_WIDTH-1:0] addr; // To U_SSRAM of bytewrite_ram_32bits.v
input [NB_COL*COL_WIDTH-1:0] din; // To U_SSRAM of bytewrite_ram_32bits.v
input [NB_COL-1:0] we; // To U_SSRAM of bytewrite_ram_32bits.v
output [NB_COL*COL_WIDTH-1:0] dout; // From U_SSRAM of bytewrite_ram_32bits.v
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
// local clock
wire ack_clk;
wire ack;
assign #1 clk = req ^ ack;
delay #(
.DELAY(CLOCK_PULSE_WIDTH)
) U_DELAY_CLOCK_PULSE (
.i(req),
.d(ack_clk)
);
delay #(
.DELAY(ACCESS_TIME)
) U_DELAY_ACCESS_TIME (
.i(req),
.d(ack)
);
/* bytewrite_ram_32bits AUTO_TEMPLATE(
); */
bytewrite_ram_32bits #(
.SIZE(SIZE),
.ADDR_WIDTH(ADDR_WIDTH),
.filename(filename)
) U_SSRAM (
.clk (clk),
/*AUTOINST*/
// Outputs
.dout(dout[NB_COL*COL_WIDTH-1:0]),
// Inputs
.we (we[NB_COL-1:0]),
.addr(addr[ADDR_WIDTH-1:0]),
.din (din[NB_COL*COL_WIDTH-1:0])
);
endmodule
| 8.00349 |
module async_mem2 (
input wire clkA,
input wire clkB,
input wire [asz-1:0] addrA,
input wire [asz-1:0] addrB,
input wire wr_csA,
input wire wr_csB,
input wire [ 7:0] wr_dataA,
input wire [ 7:0] wr_dataB,
output wire [ 7:0] rd_dataA,
output wire [ 7:0] rd_dataB
);
parameter asz = 15;
parameter depth = 32768;
reg [7:0] mem[0:depth-1];
always @(posedge clkA) begin
if (wr_csA) mem[addrA] <= wr_dataA;
end
always @(posedge clkB) begin
if (wr_csB) mem[addrB] <= wr_dataB;
end
assign rd_dataA = mem[addrA];
assign rd_dataB = mem[addrB];
endmodule
| 8.608668 |
module async_memory (
input clock,
input reset,
input [31:0] addr_in,
output [31:0] data_out,
input [31:0] data_in,
input [ 1:0] size_in, //0=byte, 1=2-byte, 2=unaligned, 3=word
input we_in,
input re_in
);
parameter MEM_ADDR = 16'h1000;
parameter DO_INIT = 0;
parameter INIT_PROGRAM0 = "c:/altera/11.1sp1/141/hello_world.data_ram0.memh";
parameter INIT_PROGRAM1 = "c:/altera/11.1sp1/141/hello_world.data_ram1.memh";
parameter INIT_PROGRAM2 = "c:/altera/11.1sp1/141/hello_world.data_ram2.memh";
parameter INIT_PROGRAM3 = "c:/altera/11.1sp1/141/hello_world.data_ram3.memh";
reg [256*8:1] file_init0, file_init1, file_init2, file_init3;
localparam NUM_WORDS = 1024;
localparam NUM_WORDS_LOG = 10;
integer i;
//memory for 4KB of data
reg [7:0] mem3[0:NUM_WORDS-1]; //31:24
reg [7:0] mem2[0:NUM_WORDS-1]; //23:16
reg [7:0] mem1[0:NUM_WORDS-1]; //15:8
reg [7:0] mem0[0:NUM_WORDS-1]; //7:0
reg [31:0] rd;
assign data_out = rd;
initial begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
mem0[i] = 8'hAD;
mem1[i] = 8'hAD;
mem2[i] = 8'hAD;
mem3[i] = 8'hAD;
end
if (DO_INIT == 1) begin
$readmemh(INIT_PROGRAM0, mem0);
$readmemh(INIT_PROGRAM1, mem1);
$readmemh(INIT_PROGRAM2, mem2);
$readmemh(INIT_PROGRAM3, mem3);
end
end
//read data all the time
/*
always @(*) begin
rd[31:24] <= mem3[addr_i[2+NUM_WORDS_LOG-1:2]];
rd[23:16] <= mem2[addr_i[2+NUM_WORDS_LOG-1:2]];
rd[15:8] <= mem1[addr_i[2+NUM_WORDS_LOG-1:2]];
rd[7:0] <= mem0[addr_i[2+NUM_WORDS_LOG-1:2]];
end*/
//alternate version uses negative edge of clock for memory accesses
always @(negedge clock) begin
rd[31:24] <= mem3[addr_in[2+NUM_WORDS_LOG-1:2]];
rd[23:16] <= mem2[addr_in[2+NUM_WORDS_LOG-1:2]];
rd[15:8] <= mem1[addr_in[2+NUM_WORDS_LOG-1:2]];
rd[7:0] <= mem0[addr_in[2+NUM_WORDS_LOG-1:2]];
end
//decode address and size into byte-enables
reg [3:0] rowWE;
always @(*) begin
case (size_in)
2'b00: rowWE <= {addr_in[1:0] == 3, addr_in[1:0] == 2, addr_in[1:0] == 1, addr_in[1:0] == 0};
2'b01: rowWE <= {{2{addr_in[1:0] == 2}}, {2{addr_in[1:0] == 0}}};
2'b10: rowWE <= 4'b0000; //unaligned write unsupported
2'b11: rowWE <= {{4{addr_in[1:0] == 0}}};
endcase
end
//we need to make sure the write data from the processor ends up in the correct byte location
reg [31:0] write_data;
always @(*) begin
case (size_in)
2'b00: write_data <= {data_in[7:0], data_in[7:0], data_in[7:0], data_in[7:0]};
2'b01: write_data <= {data_in[15:0], data_in[15:0]};
default: write_data <= data_in[31:0];
endcase
end
//on posedge of clock, write data only if wr_en is high
always @(posedge clock) begin
if (reset) begin
end else begin
if (we_in && (addr_in[31:16] == MEM_ADDR)) begin
if (rowWE[3]) mem3[addr_in[2+NUM_WORDS_LOG-1:2]] <= write_data[31:24];
if (rowWE[2]) mem2[addr_in[2+NUM_WORDS_LOG-1:2]] <= write_data[23:16];
if (rowWE[1]) mem1[addr_in[2+NUM_WORDS_LOG-1:2]] <= write_data[15:08];
if (rowWE[0]) mem0[addr_in[2+NUM_WORDS_LOG-1:2]] <= write_data[07:00];
end
end
end
endmodule
| 8.247777 |
module async_ram256x8 (
input wire [7:0] a, // líneas de dirección
inout tri [7:0] d, // líneas de datos (entrada/salida)
input wire we, // escritura (write enable)
input wire oe // lectura (output enable)
);
/* Las señales tipo "tri" son idénticas a "wire". Se suele emplear "tri"
* para señales que puden ser asignadas desde múltiples lugares o que
* pueden quedar sin asignar o en "alta impedancia", como es el caso de
* señales de entrada/salida (en este ejemplo). */
// Contenido de la memoria
/* Una memoria RAM se representa en Verilog mediante un "array" de
* vectores. Cada vector corresponde a un dato almacenado y el índice
* array se usa como dirección del dato. La memoria RAM conserva el valor
* por lo que la señal debe ser de tipo "reg". */
reg [7:0] mem[0:255];
// Carga del contenido inicial
/* En Verilog es posible cargar el contenido inicial de un array mediante la
* las funciónes del sistema "$readmemb()" y "$readmemh()". Estas funciones
* esperan encontrar un archivo de texto con los datos a cargar separados
* en líneas. $readmemb() interpretará los datos en binario y $readmemh()
* en hexadecimal. El archivo de datos puede tener comentarios e
* indicadores de dirección. Los elementos del array no asignados en el
* archivo de datos quedarán como valores desconocidos ("x"). Véase
* archivo "mem.list" como ejemplo. */
initial $readmemh("mem.list", mem);
// Operación de escritura
/* La escritura en la memoria se produce en cualquier momento siempre que
* esté activa la seña "we". */
always @(*) if (we == 1'b1) mem[a] <= d;
// Operación de lectura
/* La lectura de la memoria se activa con la señal "oe" y siempre que no
* se esté haciendo una operación de escritura. En el caso de que no se
* active la operación de lectura, la señal se asigna con el valor "z"
* lo cual significa que queda sin asignar. Una señal a la que no se
* asigna ningún valor se dice que está en "alta impledancia". En una
* implementación práctica, las señales en alta impedancia están debilmente
* conectadas a la fuente de alimentación y son subceptibles de sufrir
* alteraciones por interferencias internas o externas al circuito. */
assign d = (oe && !we) ? mem[a] : 8'bz;
endmodule
| 7.877666 |
module based on the number
of rd/wr ports.
NOTE:
This module does not have reset. Tables can be too big, the state machine to
clear datas should be handled outside (if necessary).
****************************************************************************/
`include "logfunc.h"
module async_ram_1port
#(parameter Width = 64, Size=128)
( input [`log2(Size)-1:0] p0_pos
,input p0_enable
,input [Width-1:0] p0_in_data
,output reg [Width-1:0] p0_out_data
);
reg [Width-1:0] data [Size-1:0]; // synthesis syn_ramstyle = "block_ram"
reg [Width-1:0] d0;
always_comb begin
if (p0_enable) begin
d0 = 'b0;
end else begin
d0 = data[p0_pos];
end
end
always @(p0_pos or p0_in_data or p0_enable) begin
if (p0_enable) begin
data[p0_pos] = p0_in_data;
end
end
always_comb begin
p0_out_data = d0;
end
endmodule
| 7.152734 |
module based on the number
of rd/wr ports.
NOTE:
This module does not have reset. Tables can be too big, the state machine to
clear datas should be handled outside (if necessary).
****************************************************************************/
`include "logfunc.h"
module async_ram_2port
#(parameter Width = 64, Size=128)
( input [`log2(Size)-1:0] p0_pos
,input p0_enable
,input [Width-1:0] p0_in_data
,output reg [Width-1:0] p0_out_data
,input [`log2(Size)-1:0] p1_pos
,input p1_enable
,input [Width-1:0] p1_in_data
,output reg [Width-1:0] p1_out_data
);
reg [Width-1:0] data [Size-1:0]; // synthesis syn_ramstyle = "block_ram"
reg [Width-1:0] d0;
reg [Width-1:0] d1;
always_comb begin
if (p0_enable) begin
d0 = {Width{1'bx}};
end else begin
d0 = data[p0_pos];
end
end
always_comb begin
if (p1_enable) begin
d1 = {Width{1'bx}};
end else begin
d1 = data[p1_pos];
end
end
always @(p0_pos or p0_in_data or p0_enable) begin
if (p0_enable) begin
data[p0_pos] = p0_in_data;
end
end
always @(p1_pos or p1_in_data or p1_enable) begin
if (p1_enable) begin
data[p1_pos] = p1_in_data;
end
end
always_comb begin
p0_out_data = d0;
p1_out_data = d1;
end
endmodule
| 7.152734 |
module async_receiver (
input clk,
input rst,
input RxD,
output RxD_start,
output reg RxD_data_ready,
output reg [7:0]RxD_data // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
);
wire OversamplingTick;
`ifdef IMPLEMENT
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
BaudTickGen #(ClkFrequency, Baud) tickgen (
.clk(clk),
.enable(1'b1),
.BaudTick(OversamplingTick)
);
`else
assign OversamplingTick = clk;
`endif
/*
function integer log2(input integer v);
begin
for (log2=0;v>0;log2=log2+1)
v = v>>1;
log2=log2-1;
end endfunction */
//localparam OversamplingCntWidth = log2(Oversampling);
reg [3:0] RxD_state;
reg SamplingStart;
wire next_bit = OversamplingTick && SamplingStart;
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk) begin
if (rst) begin
RxD_state <= `START;
SamplingStart <= 1'b0;
end else if (OversamplingTick) begin
case (RxD_state)
`START:
if (~RxD) begin
RxD_state <= `BIT0; // start bit found
SamplingStart <= 1'b1;
end
`BIT0: if (next_bit) RxD_state <= `BIT1; // bit 0
`BIT1: if (next_bit) RxD_state <= `BIT2; // bit 1
`BIT2: if (next_bit) RxD_state <= `BIT3; // bit 2
`BIT3: if (next_bit) RxD_state <= `BIT4; // bit 3
`BIT4: if (next_bit) RxD_state <= `BIT5; // bit 4
`BIT5: if (next_bit) RxD_state <= `BIT6; // bit 5
`BIT6: if (next_bit) RxD_state <= `BIT7; // bit 6
`BIT7: if (next_bit) RxD_state <= `STOP; // bit 7
`STOP:
if (next_bit) begin
RxD_state <= `START; // stop bit
SamplingStart <= 1'b0;
end
default: RxD_state <= `START;
endcase
end
end
assign RxD_start = SamplingStart;
always @(posedge clk) begin
if (rst) RxD_data <= 8'd0;
else if (next_bit && RxD_state[3]) RxD_data <= {RxD, RxD_data[7:1]};
end
//RxD_data_ready if bit 7 has received
always @(posedge clk) begin
RxD_data_ready <= (next_bit && RxD_state == `STOP && RxD); // make sure a stop bit is received
end
endmodule
| 7.236243 |
module async_reset (
clock,
reset,
d,
q
);
(* src = "tests/async_reset.v:2.9-2.14" *)
input clock;
wire clock;
(* src = "tests/async_reset.v:4.9-4.10" *)
input d;
wire d;
(* src = "tests/async_reset.v:5.10-5.11" *)
output q;
wire q;
(* src = "tests/async_reset.v:7.7-7.12" *)
reg q_reg;
(* src = "tests/async_reset.v:3.9-3.14" *)
input reset;
wire reset;
(* src = "tests/async_reset.v:9.3-15.6" *)
always @(posedge clock, posedge reset)
if (reset) q_reg <= 1'h0;
else q_reg <= d;
assign q = q_reg;
endmodule
| 6.817445 |
module async_reset (
input rstn_async,
input clk,
output reg rstn
);
reg q1;
always @(posedge clk or negedge rstn_async) begin
if (!rstn_async) begin
q1 <= 1'b0;
end else begin
q1 <= 1'b1;
end
end
always @(posedge clk or negedge rstn_async) begin
if (!rstn_async) begin
rstn <= 1'b0;
end else begin
rstn <= q1;
end
end
endmodule
| 6.817445 |
module async_reset_n (
clock,
reset_n,
d,
q
);
(* src = "tests/async_reset_n.v:2.9-2.14" *)
input clock;
wire clock;
(* src = "tests/async_reset_n.v:4.9-4.10" *)
input d;
wire d;
(* src = "tests/async_reset_n.v:5.10-5.11" *)
output q;
wire q;
(* src = "tests/async_reset_n.v:7.7-7.12" *)
reg q_reg;
(* src = "tests/async_reset_n.v:3.9-3.16" *)
input reset_n;
wire reset_n;
(* src = "tests/async_reset_n.v:9.3-15.6" *)
always @(posedge clock, negedge reset_n)
if (!reset_n) q_reg <= 1'h0;
else q_reg <= d;
assign q = q_reg;
endmodule
| 6.824245 |
module async_reset_n (
input clock,
input reset_n,
input d,
output q
);
reg q_reg;
always @(posedge clock, negedge reset_n) begin
if (~reset_n) begin
q_reg <= 1'b0;
end else begin
q_reg <= d;
end
end
assign q = q_reg;
endmodule
| 6.824245 |
module
* Copyright Robert Schmidt <rschmidt@uni-bremen.de>, 2020
*
* This documentation describes Open Hardware and is licensed under the
* CERN-OHL-W v2.
*
* You may redistribute and modify this documentation under the terms
* of the CERN-OHL-W v2. (https://cern.ch/cern-ohl). This documentation
* is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF
* MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR
* PURPOSE. Please see the CERN-OHL-W v2 for applicable conditions.
*/
module async_reset_sync2(
input wire clk_i,
input wire rst_n_i,
output reg rst_n_o
);
reg rff1;
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) {rst_n_o, rff1} <= 2'b0;
else {rst_n_o, rff1} <= {rff1, 1'b1};
end
endmodule
| 8.161218 |
module async_rstn_glitch_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RSTN
);
wire w_or_1;
//wire w_buf_1;
//buf(w_buf_1, i_RSTN);
or (w_or_1, i_RSTN, i_RSTN);
async_rstn_synchronizer async_rstn_synchronizer (
.i_CLK (i_CLK),
.i_RSTN(w_or_1),
.o_RSTN(o_RSTN)
);
endmodule
| 6.953109 |
module async_rstn_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RSTN
);
reg r_ff;
always @(posedge i_CLK, negedge i_RSTN) begin
if (!i_RSTN) {o_RSTN, r_ff} <= 2'b0;
else {o_RSTN, r_ff} <= {r_ff, 1'b1};
end
endmodule
| 7.291522 |
module async_rst_synchronizer (
input i_CLK,
input i_RSTN,
output reg o_RST
);
reg r_ff;
always @(posedge i_CLK, negedge i_RSTN) begin
if (!i_RSTN) {o_RST, r_ff} <= 2'b11;
else {o_RST, r_ff} <= {r_ff, 1'b0};
end
endmodule
| 6.653778 |
module async_rx (
input clk,
input rst,
input [11:0] data,
output r_en,
input empty,
output reg [11:0] duty_cycle
);
localparam IDLE = 3'b001, READ = 3'b010, LATCH = 3'b100;
reg [2:0] state;
reg [2:0] next_state;
always @(*) begin
case (state)
IDLE:
if (!empty) next_state = READ;
else next_state = IDLE;
READ: next_state = LATCH;
LATCH: next_state = IDLE;
default: next_state = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) state <= IDLE;
else state <= next_state;
end
assign r_en = (state == READ);
always @(posedge clk) begin
if (rst) duty_cycle <= 12'b0;
else if (state == LATCH) duty_cycle <= data;
end
endmodule
| 8.183881 |
module async_send (
input clk,
input TxD_start,
input [7:0] TxD_data,
output reg TxD,
output TxD_busy
);
parameter Clk_Freq = 50000000; //50M
parameter Baud = 115200; //波特率
parameter BaudGeneAccWidth = 16;
reg [BaudGeneAccWidth:0] BaudGeneAcc;
/* 这里是为了避免超过32bit数出错 */
wire [BaudGeneAccWidth:0] BaudGeneInc = ((Baud<<(BaudGeneAccWidth-4))+(Clk_Freq>>5))/(Clk_Freq>>4);//constant
wire BaudTick = BaudGeneAcc[BaudGeneAccWidth];
/**********************************************************************************************************
时钟产生思想：类似计数器cnt从0开始计数，每次递增step = 3，则经过4个周期就计数到12，超出10两个计数
0 3 6 9 12 5 8 11 4 7 10 3 6 9 12 5 8 11
0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1大于等于10则输出高电平
***********************************************************************************************************/
reg [3:0] state;
wire TxD_ready = (state == 0);
assign TxD_busy = ~TxD_ready;
always @(posedge clk) begin
if (TxD_busy) BaudGeneAcc <= BaudGeneAcc[BaudGeneAccWidth-1:0] + BaudGeneInc;
else if (TxD_start)
BaudGeneAcc <= {BaudGeneAccWidth{1'b1}}; //目的是使接收到触发信号后即刻启动发送
end
///////////////////////////
reg TxD_start_tmp1;
reg TxD_start_tmp2;
always @(posedge clk) begin
TxD_start_tmp1 <= TxD_start;
TxD_start_tmp2 <= TxD_start_tmp1;
end
wire TxD_start_pulse = (~TxD_start_tmp2) & TxD_start_tmp1;
reg [7:0] TxD_dataReg;
always @(posedge clk) begin
if (TxD_ready & TxD_start_pulse) //TxD_ready is necessary!
TxD_dataReg <= TxD_data;
end
//state change part
always @(posedge clk)
case (state)
4'd0: if (TxD_start_pulse) state <= 4'd1;
4'd1: if (BaudTick) state <= 4'd2;
4'd2: if (BaudTick) state <= 4'd3; // start
4'd3: if (BaudTick) state <= 4'd4; // bit 0
4'd4: if (BaudTick) state <= 4'd5; // bit 1
4'd5: if (BaudTick) state <= 4'd6; // bit 2
4'd6: if (BaudTick) state <= 4'd7; // bit 3
4'd7: if (BaudTick) state <= 4'd8; // bit 4
4'd8: if (BaudTick) state <= 4'd9; // bit 5
4'd9: if (BaudTick) state <= 4'd10; // bit 6
4'd10: if (BaudTick) state <= 4'd11; // bit 7
4'd11: if (BaudTick) state <= 4'd0; // stop1
default: state <= 4'd0;
endcase
//output part
reg muxbit;
always @(posedge clk)
case (state)
4'd0: muxbit <= 1'b1;
4'd1: muxbit <= 1'b1;
4'd2: muxbit <= 1'b0; // start
4'd3: muxbit <= TxD_dataReg[0]; // bit 0
4'd4: muxbit <= TxD_dataReg[1]; // bit 1
4'd5: muxbit <= TxD_dataReg[2]; // bit 2
4'd6: muxbit <= TxD_dataReg[3]; // bit 3
4'd7: muxbit <= TxD_dataReg[4]; // bit 4
4'd8: muxbit <= TxD_dataReg[5]; // bit 5
4'd9: muxbit <= TxD_dataReg[6]; // bit 6
4'd10: muxbit <= TxD_dataReg[7]; // bit 7
4'd11: muxbit <= 1'b1; // stop1
default: muxbit <= 1'b1;
endcase
always @(posedge clk) begin
TxD <= muxbit;
end
endmodule
| 7.411494 |
module async_seq_writer #(
parameter word_count_top = 2'd3,
parameter read_count_top = 3'd7,
parameter address_step = 30'd4,
parameter address_bottom = 30'h0000_0000,
parameter address_top = 30'h0200_0000 - address_step
) (
input ddr2_clk,
input wr_clk,
input RST,
output reg req,
input ack,
output reg [30:0] addr,
output read,
output fin,
output reg [255:0] data_write,
output [ 31:0] mask,
input valid, // unused
input [127:0] data_read, // unused
input wr_en,
input [127:0] din,
output fifo_full
);
wire fifo_empty;
wire fifo_almost_empty;
wire [255:0] data_write_w;
reg rd_en;
reg req_1;
reg written;
// assign req = !fifo_almost_empty ||
// (!fifo_empty & !written);
assign read = 1'b0;
assign mask = 31'h0;
assign fin = req & fifo_empty;
always @(posedge ddr2_clk or negedge RST)
if (!RST) begin
rd_en <= 1'b0;
end else begin
rd_en <= !fifo_empty && (ack || written);
end
always @(posedge ddr2_clk or negedge RST)
if (!RST) begin
written <= 1'b1;
end else begin
if (ack && fifo_empty) written <= 1'b1;
else if (!fifo_empty) written <= 1'b0;
end
(* MAX_FANOUT = "10" *)
async_fifo_ddr2_x2 async_fifo_ddr2_x2_inst (
.rst(!RST),
.wr_clk(wr_clk),
.rd_clk(ddr2_clk),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(data_write_w),
.full(fifo_full),
.empty(fifo_empty),
.almost_empty(fifo_almost_empty)
);
always @(posedge ddr2_clk or negedge RST)
if (!RST) begin
addr <= address_bottom;
end else begin
if (ack) begin
if (addr == address_top) addr <= address_bottom;
else addr <= addr + address_step;
end
end
always @(posedge ddr2_clk or negedge RST)
if (!RST) begin
req <= 1'b0;
end else begin
if (ack && fifo_empty) req <= 1'b0;
else if (!fifo_empty) req <= 1'b1;
end
always @(posedge ddr2_clk) if (written || ack) data_write <= data_write_w;
endmodule
| 8.14394 |
module async_sram_phy #(
parameter W_ADDR = 18,
parameter W_DATA = 16,
// If 1, register input paths, increasing read latency from 1 to 2 cycles:
parameter DQ_SYNC_IN = 0
) (
// These should be the same clock/reset used by the controller
input wire clk,
input wire rst_n,
// From SRAM controller
input wire [ W_ADDR-1:0] ctrl_addr,
input wire [ W_DATA-1:0] ctrl_dq_out,
input wire [ W_DATA-1:0] ctrl_dq_oe,
output wire [ W_DATA-1:0] ctrl_dq_in,
input wire ctrl_ce_n,
input wire ctrl_we_n,
input wire ctrl_oe_n,
input wire [W_DATA/8-1:0] ctrl_byte_n,
// To external SRAM
output wire [ W_ADDR-1:0] sram_addr,
inout wire [ W_DATA-1:0] sram_dq,
output wire sram_ce_n,
output wire sram_we_n,
output wire sram_oe_n,
output wire [W_DATA/8-1:0] sram_byte_n
);
tristate_io #(
.SYNC_OUT(1),
.SYNC_IN (1)
) addr_buf[W_ADDR-1:0] (
.clk (clk),
.rst_n(rst_n),
.out (ctrl_addr),
.oe ({W_ADDR{1'b1}}),
.in (),
.pad (sram_addr)
);
ddr_out we_ddr (
.clk (clk),
.rst_n (rst_n),
.d_rise(1'b1),
.d_fall(ctrl_we_n),
.q (sram_we_n)
);
tristate_io #(
.SYNC_OUT(1),
.SYNC_IN (1)
) cmd_buf[1 + W_DATA / 8 -1:0] (
.clk (clk),
.rst_n(rst_n),
.out ({ctrl_oe_n, ctrl_byte_n}),
.oe ({1 + W_DATA / 8{1'b1}}),
.in (),
.pad ({sram_oe_n, sram_byte_n})
);
// TODO this is grounded externally on the modified HX8k board, as a
// workaround for a clock enable packing issue on a previous version of the
// hardware. Should really be part of the cmd_buf above:
assign sram_ce_n = 1'b0;
`ifdef FPGA_ICE40
localparam [5:0] DQ_PIN_TYPE = {
// Posedge-registered output enable:
2'b11,
// DDR (OPPOSITE_EDGE in Xilinx terms) output to allow negedge
// registration of AHB HWDATA:
2'b00,
// Optional input register
DQ_SYNC_IN ? 2'b00 : 2'b01
};
genvar g;
generate
for (g = 0; g < W_DATA; g = g + 1) begin : dq_buf_g
// Note we can't use array instantiation for iCE40 cells, possibly because
// Yosys doesn't know their type signature in advance
SB_IO #(
.PIN_TYPE(DQ_PIN_TYPE),
.PULLUP (1'b0)
) dq_buf (
.OUTPUT_CLK (clk),
.INPUT_CLK (clk),
.PACKAGE_PIN (sram_dq[g]),
.OUTPUT_ENABLE(ctrl_dq_oe[g]),
// HWDATA presented on negedge, following half-cycle internal path:
.D_OUT_1 (ctrl_dq_out[g]),
// .. then repeated on the following posedge, to keep it stable as the
// output driver turns off:
.D_OUT_0 (ctrl_dq_out[g]),
.D_IN_0 (ctrl_dq_in[g])
);
end
endgenerate
`else
tristate_io #(
.SYNC_OUT(0),
.SYNC_IN (DQ_SYNC_IN)
) iobuf[W_DATA-1:0] (
.clk (clk),
.rst_n(rst_n),
.out (ctrl_dq_out),
.oe (ctrl_dq_oe),
.in (ctrl_dq_in),
.pad (sram_dq)
);
`endif
endmodule
| 8.359444 |
module fifo_async_tb;
reg wclk, wrst_n;
reg rclk, rrst_n;
reg wq, rq;
reg [7:0] write_data; // data input to be pushed to buffer
wire [7:0] read_data; // port to output the data using pop.
wire rempty, wfull; // buffer empty and full indication
integer idx = 0;
`define TEST_CASE(VAR, VALUE) \
idx = idx + 1; \
if(VAR == VALUE) $display("Case %d passed!", idx); \
else begin $display("Case %d failed!", idx); $finish; end
fifo_async #(
.DSIZE(8),
.ASIZE(4)
) fifo_inst (
.rclk(rclk),
.rrst_n(rrst_n),
.rq(rq),
.wclk(wclk),
.wrst_n(wrst_n),
.wq(wq),
.write_data(write_data),
.read_data(read_data),
.wfull(wfull),
.rempty(rempty)
);
always #10 wclk = ~wclk;
always #20 rclk = ~rclk;
reg [7:0] tempdata = 0;
initial begin
rclk = 0;
wclk = 0;
end
initial begin
wrst_n = 1;
#2;
wrst_n = 0;
#60;
wrst_n = 1;
end
initial begin
rrst_n = 1;
#2;
rrst_n = 0;
#120;
rrst_n = 1;
end
always @(posedge wclk or negedge wrst_n) begin
if (wrst_n == 1'b0) begin
wq <= 0;
rq <= 0;
end else begin
wq <= ~wq;
end
end
always @(posedge rclk or negedge rrst_n)
if (rrst_n == 1'b0) rq <= 0;
else rq <= ~rq;
initial write_data = 0;
always #5 write_data <= write_data + 1;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
initial begin
#110 $display("%d", read_data);
`TEST_CASE(read_data, 8'h11);
#90 `TEST_CASE(read_data, 8'h19);
#90 `TEST_CASE(read_data, 8'h21);
#90 `TEST_CASE(read_data, 8'h29);
#90 `TEST_CASE(read_data, 8'h31);
#90 `TEST_CASE(read_data, 8'h39);
#90 `TEST_CASE(read_data, 8'h41);
#90 `TEST_CASE(read_data, 8'h49);
$display("Success!");
$finish;
end
endmodule
| 7.518899 |
module async_to_sync_reset_shift (
input clk,
input Pinput,
output Poutput
);
parameter LENGTH = 8;
parameter INPUT_POLARITY = 1'b1;
parameter OUTPUT_POLARITY = 1'b1;
reg [LENGTH-1:0] shift = 0;
always @(Pinput or(clk)) begin
if (Pinput == INPUT_POLARITY) begin
shift <= {LENGTH{OUTPUT_POLARITY}};
end else if (clk) begin
shift <= {shift[LENGTH-2:0], ~OUTPUT_POLARITY};
end
end
// Output the result on edge - helps to meet timing
//always @(posedge clk) begin
// Poutput <= shift[LENGTH-1];
//end
assign Poutput = shift[LENGTH-1];
endmodule
| 8.342032 |
module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef DEBUG
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;
`else
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
`endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @( * )
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
| 6.83375 |
module: async_transmitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module async_transmitter_tb;
// Inputs
reg clk;
reg TxD_start;
reg [7:0] TxD_data;
// Outputs
wire TxD;
wire TxD_busy;
// Instantiate the Unit Under Test (UUT)
async_transmitter uut (
.clk(clk),
.TxD_start(TxD_start),
.TxD_data(TxD_data),
.TxD(TxD),
.TxD_busy(TxD_busy)
);
initial begin
// Initialize Inputs
clk = 0;
TxD_start = 0;
TxD_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.14618 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
////////////////////////////////////////////////////////
module async_transmitter(
input clk,
input rst,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
////////////////////////////////
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .rst(rst), .enable(TxD_busy), .tick(BitTick));
reg [3:0] TxD_state;
reg [7:0] TxD_shift;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
TxD_state <= 0;
TxD_shift <= 0;
end
else
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
endmodule
| 6.83375 |
module BaudTickGen (
input clk,
rst,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) begin
if (rst) Acc <= 0;
else if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
end
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module async_up_counter (
input clk_i, // Clock
input rst_i, // Reset
output [3:0] count_o // Count Value
);
wire [3:0] q_n;
// DFF 0
dff dff_1 (
.clk_i(clk_i), // Input Clock
.rst_i(rst_i),
.d_i (q_n[0]),
.q_o (count_o[0]),
.q_n_o(q_n[0])
);
// DFF 1
dff dff_2 (
.clk_i(q_n[0]), // DFF 0 Output
.rst_i(rst_i),
.d_i (q_n[1]),
.q_o (count_o[1]),
.q_n_o(q_n[1])
);
// DFF 2
dff dff_3 (
.clk_i(q_n[1]), // DFF 1 Output
.rst_i(rst_i),
.d_i (q_n[2]),
.q_o (count_o[2]),
.q_n_o(q_n[2])
);
// DFF 3
dff dff_4 (
.clk_i(q_n[2]), // DFF 2 Output
.rst_i(rst_i),
.d_i (q_n[3]),
.q_o (count_o[3]),
.q_n_o(q_n[3])
);
endmodule
| 7.183579 |
module dff (
input clk_i,
input rst_i,
input d_i,
output reg q_o,
output q_n_o
);
assign q_n_o = ~q_o;
always @(posedge clk_i) begin
if (rst_i) begin
q_o <= 1'b0;
end else begin
q_o <= d_i;
end
end
endmodule
| 7.174483 |
module async_wb (
wbm_rst_n,
wbm_clk_i,
wbm_cyc_i,
wbm_stb_i,
wbm_adr_i,
wbm_we_i,
wbm_dat_i,
wbm_sel_i,
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbs_rst_n,
wbs_clk_i,
wbs_cyc_o,
wbs_stb_o,
wbs_adr_o,
wbs_we_o,
wbs_dat_o,
wbs_sel_o,
wbs_dat_i,
wbs_ack_i,
wbs_err_i
);
parameter AW = 32;
parameter BW = 4;
parameter DW = 32;
input wire wbm_rst_n;
input wire wbm_clk_i;
input wire wbm_cyc_i;
input wire wbm_stb_i;
input wire [AW - 1:0] wbm_adr_i;
input wire wbm_we_i;
input wire [DW - 1:0] wbm_dat_i;
input wire [BW - 1:0] wbm_sel_i;
output wire [DW - 1:0] wbm_dat_o;
output wire wbm_ack_o;
output wire wbm_err_o;
input wire wbs_rst_n;
input wire wbs_clk_i;
output wire wbs_cyc_o;
output wire wbs_stb_o;
output wire [AW - 1:0] wbs_adr_o;
output wire wbs_we_o;
output wire [DW - 1:0] wbs_dat_o;
output wire [BW - 1:0] wbs_sel_o;
input wire [DW - 1:0] wbs_dat_i;
input wire wbs_ack_i;
input wire wbs_err_i;
parameter CFW = ((AW + DW) + BW) + 1;
reg PendingRd;
wire m_cmd_wr_en;
wire [CFW - 1:0] m_cmd_wr_data;
wire m_cmd_wr_full;
wire m_cmd_wr_afull;
wire m_resp_rd_empty;
wire m_resp_rd_aempty;
wire m_resp_rd_en;
wire [DW:0] m_resp_rd_data;
assign m_cmd_wr_en = ((!PendingRd && wbm_stb_i) && !m_cmd_wr_full) && !m_cmd_wr_afull;
assign m_cmd_wr_data = {wbm_adr_i, wbm_we_i, wbm_dat_i, wbm_sel_i};
always @(negedge wbm_rst_n or posedge wbm_clk_i)
if (wbm_rst_n == 0) PendingRd <= 1'b0;
else if (((!PendingRd && wbm_stb_i) && !wbm_we_i) && m_cmd_wr_en) PendingRd <= 1'b1;
else if (((PendingRd && wbm_stb_i) && !wbm_we_i) && wbm_ack_o) PendingRd <= 1'b0;
assign wbm_ack_o = (wbm_stb_i && wbm_we_i ? m_cmd_wr_en : (wbm_stb_i && !wbm_we_i ? !m_resp_rd_empty : 1'b0));
assign m_resp_rd_en = !m_resp_rd_empty;
assign wbm_dat_o = m_resp_rd_data[DW-1:0];
assign wbm_err_o = m_resp_rd_data[DW];
wire [CFW - 1:0] s_cmd_rd_data;
wire s_cmd_rd_empty;
wire s_cmd_rd_aempty;
wire s_cmd_rd_en;
wire s_resp_wr_en;
wire [DW:0] s_resp_wr_data;
wire s_resp_wr_full;
wire s_resp_wr_afull;
reg wbs_ack_f;
always @(negedge wbs_rst_n or posedge wbs_clk_i)
if (wbs_rst_n == 0) wbs_ack_f <= 1'b0;
else wbs_ack_f <= wbs_ack_i;
assign {wbs_adr_o, wbs_we_o, wbs_dat_o, wbs_sel_o} = (s_cmd_rd_empty ? {(((0 + AW) + 1) + DW) + BW {1'sb0}} : s_cmd_rd_data);
assign wbs_stb_o = (wbs_ack_f ? 1'b0 : (s_cmd_rd_empty ? 1'b0 : 1'b1));
assign wbs_cyc_o = (wbs_ack_f ? 1'b0 : (s_cmd_rd_empty ? 1'b0 : 1'b1));
assign s_cmd_rd_en = wbs_ack_i;
assign s_resp_wr_en = ((wbs_stb_o & !wbs_we_o) & wbs_ack_i) & !s_resp_wr_full;
assign s_resp_wr_data = {wbs_err_i, wbs_dat_i};
async_fifo #(
.W(CFW),
.DP(4),
.WR_FAST(1),
.RD_FAST(1)
) u_cmd_if (
.wr_clk(wbm_clk_i),
.wr_reset_n(wbm_rst_n),
.wr_en(m_cmd_wr_en),
.wr_data(m_cmd_wr_data),
.full(m_cmd_wr_full),
.afull(m_cmd_wr_afull),
.rd_clk(wbs_clk_i),
.rd_reset_n(wbs_rst_n),
.rd_en(s_cmd_rd_en),
.empty(s_cmd_rd_empty),
.aempty(s_cmd_rd_aempty),
.rd_data(s_cmd_rd_data)
);
async_fifo #(
.W(DW + 1),
.DP(2),
.WR_FAST(1),
.RD_FAST(1)
) u_resp_if (
.wr_clk(wbs_clk_i),
.wr_reset_n(wbs_rst_n),
.wr_en(s_resp_wr_en),
.wr_data(s_resp_wr_data),
.full(s_resp_wr_full),
.afull(s_resp_wr_afull),
.rd_clk(wbm_clk_i),
.rd_reset_n(wbm_rst_n),
.rd_en(m_resp_rd_en),
.empty(m_resp_rd_empty),
.aempty(m_resp_rd_aempty),
.rd_data(m_resp_rd_data)
);
endmodule
| 7.368908 |
module asynrecounter10 (
input wire clk,
input wire reset, //asynchronous active-high reset
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset) q <= 4'b0000;
else if (q == 4'b1001) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 6.946006 |
module asynrecounter10_tb;
`define asynrecounter10_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
asynrecounter10 x_asynrecounter10 (
.clk(clk),
.reset(reset),
.q(q)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
#5 reset <= 1'b0;
#5 `asynrecounter10_TEST(8'd1, 1'b0, 1'b0, 4'b0000);
#5 `asynrecounter10_TEST(8'd2, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter10_TEST(8'd3, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter10_TEST(8'd4, 1'b1, 1'b0, 4'b0001);
#5 `asynrecounter10_TEST(8'd5, 1'b0, 1'b0, 4'b0010);
#5 `asynrecounter10_TEST(8'd6, 1'b1, 1'b0, 4'b0010);
#5 `asynrecounter10_TEST(8'd7, 1'b0, 1'b0, 4'b0011);
#5 `asynrecounter10_TEST(8'd8, 1'b1, 1'b0, 4'b0011);
#5 `asynrecounter10_TEST(8'd9, 1'b0, 1'b0, 4'b0100);
#5 `asynrecounter10_TEST(8'd10, 1'b1, 1'b0, 4'b0100);
#5 `asynrecounter10_TEST(8'd11, 1'b0, 1'b0, 4'b0101);
#5 `asynrecounter10_TEST(8'd12, 1'b1, 1'b0, 4'b0101);
#5 `asynrecounter10_TEST(8'd13, 1'b0, 1'b0, 4'b0110);
#5 `asynrecounter10_TEST(8'd14, 1'b1, 1'b0, 4'b0110);
#5 `asynrecounter10_TEST(8'd15, 1'b0, 1'b0, 4'b0111);
#5 `asynrecounter10_TEST(8'd16, 1'b1, 1'b0, 4'b0111);
#5 `asynrecounter10_TEST(8'd17, 1'b0, 1'b0, 4'b1000);
#5 `asynrecounter10_TEST(8'd18, 1'b1, 1'b0, 4'b1000);
#5 `asynrecounter10_TEST(8'd19, 1'b0, 1'b0, 4'b1001);
#5 `asynrecounter10_TEST(8'd20, 1'b1, 1'b0, 4'b1001)
#5 `asynrecounter10_TEST(8'd21, 1'b0, 1'b0, 4'b0000);
#5 `asynrecounter10_TEST(8'd22, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter10_TEST(8'd23, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter10_TEST(8'd24, 1'b1, 1'b0, 4'b0001);
#5 reset <= 1'b1;
`asynrecounter10_TEST(8'd25, 1'b0, 1'b0, 4'b0010);
#2.5
reset <= 1'b0;
`asynrecounter10_TEST(8'd26, 1'b0, 1'b1, 4'b0000);
#2.5
`asynrecounter10_TEST(8'd27, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter10_TEST(8'd28, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter10_TEST(8'd29, 1'b1, 1'b0, 4'b0001);
#5 `asynrecounter10_TEST(8'd30, 1'b0, 1'b0, 4'b0010);
$display("Success!");
$finish;
end
endmodule
| 6.946006 |
module asynrecounter15 (
input clk,
input reset, //asynchronous active-high reset
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 6.946006 |
module asynrecounter15_tb;
`define asynrecounter15_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
asynrecounter15 x_asynrecounter15 (
.clk(clk),
.reset(reset),
.q(q)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
#5 reset <= 1'b0;
#5 `asynrecounter15_TEST(8'd1, 1'b0, 1'b0, 4'b0000);
#5 `asynrecounter15_TEST(8'd2, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter15_TEST(8'd3, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter15_TEST(8'd4, 1'b1, 1'b0, 4'b0001);
#5 `asynrecounter15_TEST(8'd5, 1'b0, 1'b0, 4'b0010);
#5 `asynrecounter15_TEST(8'd6, 1'b1, 1'b0, 4'b0010);
#5 `asynrecounter15_TEST(8'd7, 1'b0, 1'b0, 4'b0011);
#5 `asynrecounter15_TEST(8'd8, 1'b1, 1'b0, 4'b0011);
#5 `asynrecounter15_TEST(8'd9, 1'b0, 1'b0, 4'b0100);
#5 `asynrecounter15_TEST(8'd10, 1'b1, 1'b0, 4'b0100);
#5 `asynrecounter15_TEST(8'd11, 1'b0, 1'b0, 4'b0101);
#5 `asynrecounter15_TEST(8'd12, 1'b1, 1'b0, 4'b0101);
#5 `asynrecounter15_TEST(8'd13, 1'b0, 1'b0, 4'b0110);
#5 `asynrecounter15_TEST(8'd14, 1'b1, 1'b0, 4'b0110);
#5 `asynrecounter15_TEST(8'd15, 1'b0, 1'b0, 4'b0111);
#5 `asynrecounter15_TEST(8'd16, 1'b1, 1'b0, 4'b0111);
#5 `asynrecounter15_TEST(8'd17, 1'b0, 1'b0, 4'b1000);
#5 `asynrecounter15_TEST(8'd18, 1'b1, 1'b0, 4'b1000);
#5 `asynrecounter15_TEST(8'd19, 1'b0, 1'b0, 4'b1001);
#5 `asynrecounter15_TEST(8'd20, 1'b1, 1'b0, 4'b1001);
#5 `asynrecounter15_TEST(8'd21, 1'b0, 1'b0, 4'b1010);
#5 `asynrecounter15_TEST(8'd22, 1'b1, 1'b0, 4'b1010);
#5 `asynrecounter15_TEST(8'd23, 1'b0, 1'b0, 4'b1011);
#5 `asynrecounter15_TEST(8'd24, 1'b1, 1'b0, 4'b1011);
#5 `asynrecounter15_TEST(8'd25, 1'b0, 1'b0, 4'b1100);
#5 `asynrecounter15_TEST(8'd26, 1'b1, 1'b0, 4'b1100);
#5 `asynrecounter15_TEST(8'd27, 1'b0, 1'b0, 4'b1101);
#5 `asynrecounter15_TEST(8'd28, 1'b1, 1'b0, 4'b1101);
#5 `asynrecounter15_TEST(8'd29, 1'b0, 1'b0, 4'b1110);
#5 `asynrecounter15_TEST(8'd30, 1'b1, 1'b0, 4'b1110);
#5 `asynrecounter15_TEST(8'd31, 1'b0, 1'b0, 4'b1111);
#5 `asynrecounter15_TEST(8'd32, 1'b1, 1'b0, 4'b1111);
#5 `asynrecounter15_TEST(8'd33, 1'b0, 1'b0, 4'b0000);
#5 `asynrecounter15_TEST(8'd34, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter15_TEST(8'd35, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter15_TEST(8'd36, 1'b1, 1'b0, 4'b0001);
#5 reset <= 1'b1;
`asynrecounter15_TEST(8'd37, 1'b0, 1'b0, 4'b0010);
#2.5
reset <= 1'b0;
`asynrecounter15_TEST(8'd38, 1'b0, 1'b1, 4'b0000);
#2.5
`asynrecounter15_TEST(8'd39, 1'b1, 1'b0, 4'b0000);
#5 `asynrecounter15_TEST(8'd40, 1'b0, 1'b0, 4'b0001);
#5 `asynrecounter15_TEST(8'd41, 1'b1, 1'b0, 4'b0001);
#5 `asynrecounter15_TEST(8'd42, 1'b0, 1'b0, 4'b0010);
$display("Success!");
$finish;
end
endmodule
| 6.946006 |
module asynrefsm1 (
input wire clk,
input wire reset, //asynchronous active-high reset
input wire in,
output reg out
);
reg state;
parameter A = 1'b0, B = 1'b1;
always @(posedge clk or posedge reset)
if (reset) begin
state <= B;
out <= 1'b1;
end else if (state == A) begin
if (in == 0) begin
state <= B;
out <= 1'b1;
end
if (in == 1) begin
state <= A;
out <= 1'b0;
end
end else begin
if (in == 0) begin
state <= A;
out <= 1'b0;
end
if (in == 1) begin
state <= B;
out <= 1'b1;
end
end
endmodule
| 7.460022 |
module asynrefsm1_tb;
`define asynrefsm1_TEST(ID, CLK, RESET, IN, OUT)\
clk=CLK;\
reset=RESET;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg in;
wire out;
asynrefsm1 x_asynrefsm1 (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
in <= 1'b1;
#5 reset <= 1'b0;
#5 `asynrefsm1_TEST(8'd1, 1'b0, 1'b0, 1'b1, 1'b1);
#5 `asynrefsm1_TEST(8'd2, 1'b1, 1'b0, 1'b1, 1'b1);
#5 in <= 1'b0;
`asynrefsm1_TEST(8'd3, 1'b0, 1'b0, 1'b1, 1'b1);
#5 `asynrefsm1_TEST(8'd4, 1'b1, 1'b0, 1'b0, 1'b1);
#5 in <= 1'b1;
`asynrefsm1_TEST(8'd5, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `asynrefsm1_TEST(8'd6, 1'b1, 1'b0, 1'b1, 1'b0);
#5 in <= 1'b0;
`asynrefsm1_TEST(8'd7, 1'b0, 1'b0, 1'b1, 1'b0);
#5 `asynrefsm1_TEST(8'd8, 1'b1, 1'b0, 1'b0, 1'b0);
#5 `asynrefsm1_TEST(8'd9, 1'b0, 1'b0, 1'b0, 1'b1);
#5 in <= 1'b1;
`asynrefsm1_TEST(8'd10, 1'b1, 1'b0, 1'b0, 1'b1);
#5 reset <= 1'b1;
`asynrefsm1_TEST(8'd11, 1'b0, 1'b0, 1'b1, 1'b0);
#5 reset <= 1'b0;
`asynrefsm1_TEST(8'd12, 1'b1, 1'b1, 1'b1, 1'b1);
#5 `asynrefsm1_TEST(8'd13, 1'b0, 1'b0, 1'b1, 1'b1);
$display("Success!");
$finish;
end
endmodule
| 7.387525 |
module asynrefsm2 (
input wire clk,
input wire reset, //asynchronous active-high reset
input wire j,
input wire k,
output reg out
);
reg state;
parameter ON = 1'b1, OFF = 1'b0;
always @(posedge clk or posedge reset)
if (reset) begin
state <= OFF;
out <= 1'b0;
end else if (state == OFF) begin
if (j == 1) begin
state <= ON;
out <= 1'b1;
end
if (j == 0) begin
state <= OFF;
out <= 1'b0;
end
end else begin
if (k == 0) begin
state <= ON;
out <= 1'b1;
end
if (k == 1) begin
state <= OFF;
out <= 1'b0;
end
end
endmodule
| 7.606491 |
module asynrefsm2_tb;
`define asynrefsm2_TEST(ID, CLK, RESET, J, K, OUT)\
clk=CLK;\
reset=RESET;\
j=J;\
k=K;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg j;
reg k;
wire out;
asynrefsm2 x_asynrefsm2 (
.clk(clk),
.reset(reset),
.j(j),
.k(k),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
reset <= 1'b1;
j <= 1'b0;
k <= 1'b0;
#5 reset <= 1'b0;
#5 `asynrefsm2_TEST(8'd1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `asynrefsm2_TEST(8'd2, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0);
#5 j <= 1'b1;
`asynrefsm2_TEST(8'd3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
#5 `asynrefsm2_TEST(8'd4, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
#5 j <= 1'b0;
`asynrefsm2_TEST(8'd5, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1);
#5 `asynrefsm2_TEST(8'd6, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1);
#5 k <= 1'b1;
`asynrefsm2_TEST(8'd7, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1);
#5 `asynrefsm2_TEST(8'd8, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1);
#5 k <= 1'b0;
j <= 1'b1;
`asynrefsm2_TEST(8'd9, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0);
#5 `asynrefsm2_TEST(8'd10, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
#5 reset <= 1'b1;
j <= 1'b0;
`asynrefsm2_TEST(8'd11, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1);
#5 reset <= 1'b0;
`asynrefsm2_TEST(8'd12, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0);
#5 `asynrefsm2_TEST(8'd13, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
$display("Success!");
$finish;
end
endmodule
| 6.992946 |
module asynrevem (
input wire clk,
input wire rst, //asynchronous active-high reset
input wire [1:0]in,
output reg [1:0]out
);
reg [2:0] cur_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always @(posedge clk or posedge rst)
if (rst) cur_state <= s0;
else cur_state <= next_state;
always @(cur_state or rst)
if (rst) out = 2'b00;
else
case (cur_state)
s0: out = 2'b00;
s1: out = 2'b00;
s2: out = 2'b00;
s3: out = 2'b10;
s4: out = 2'b11;
default: out = 2'b00;
endcase
always @(cur_state, in[0], in[1])
case (cur_state)
s0: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
s1: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s2;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s3;
else next_state <= s0;
end
s2: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s2;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s3;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s4;
else next_state <= s0;
end
s3: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
s4: begin
if ((in[0] == 0) && (in[1] == 0)) next_state <= s0;
else if ((in[0] == 1) && (in[1] == 0)) next_state <= s1;
else if ((in[0] == 0) && (in[1] == 1)) next_state <= s2;
else next_state <= s0;
end
endcase
endmodule
| 8.505785 |
module asynrevem_tb;
`define asynrevem_TEST(ID, CLK, RST, IN, OUT)\
clk=CLK;\
rst=RST;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg rst;
reg [1:0] in;
wire [1:0] out;
asynrevem x_asynrevem (
.clk(clk),
.rst(rst),
.in (in),
.out(out)
);
always #5 clk = ~clk;
initial begin
clk <= 1'b0;
rst <= 1'b1;
in <= 2'b00;
#5 rst <= 1'b0;
#5 in <= 2'b01;
`asynrevem_TEST(8'd1, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd2, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b01;
`asynrevem_TEST(8'd3, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd4, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b01;
`asynrevem_TEST(8'd5, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd6, 1'b1, 1'b0, 2'b01, 2'b00);
#5 `asynrevem_TEST(8'd7, 1'b0, 1'b0, 2'b00, 2'b10);
#5 `asynrevem_TEST(8'd8, 1'b1, 1'b0, 2'b00, 2'b10);
#5 in <= 2'b10;
`asynrevem_TEST(8'd9, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd10, 1'b1, 1'b0, 2'b10, 2'b00);
#5 in <= 2'b10;
`asynrevem_TEST(8'd11, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd12, 1'b1, 1'b0, 2'b10, 2'b00);
#5 `asynrevem_TEST(8'd13, 1'b0, 1'b0, 2'b00, 2'b11);
#5 `asynrevem_TEST(8'd14, 1'b1, 1'b0, 2'b00, 2'b11);
#5 in <= 2'b01;
`asynrevem_TEST(8'd15, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd16, 1'b1, 1'b0, 2'b01, 2'b00);
#5 in <= 2'b10;
`asynrevem_TEST(8'd17, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd18, 1'b1, 1'b0, 2'b10, 2'b00);
#5 `asynrevem_TEST(8'd19, 1'b0, 1'b0, 2'b00, 2'b10);
#5 `asynrevem_TEST(8'd20, 1'b1, 1'b0, 2'b00, 2'b10);
#5 in <= 2'b10;
`asynrevem_TEST(8'd21, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd22, 1'b1, 1'b0, 2'b10, 2'b00);
#5 in <= 2'b01;
`asynrevem_TEST(8'd23, 1'b0, 1'b0, 2'b00, 2'b00);
#5 in <= 2'b00;
`asynrevem_TEST(8'd24, 1'b1, 1'b0, 2'b01, 2'b00);
#5 rst <= 1'b1;
`asynrevem_TEST(8'd25, 1'b0, 1'b0, 2'b00, 2'b10);
#5 rst <= 1'b0;
`asynrevem_TEST(8'd26, 1'b1, 1'b1, 2'b00, 2'b00);
#5 `asynrevem_TEST(8'd27, 1'b0, 1'b0, 2'b00, 2'b00);
$display("Success!");
$finish;
end
endmodule
| 6.799103 |
module asyn_1024_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output rdempty;
output [10:0] rdusedw;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire sub_wire1;
wire [10:0] sub_wire2;
wire [10:0] sub_wire3;
wire [133:0] q = sub_wire0[133:0];
wire rdempty = sub_wire1;
wire [10:0] rdusedw = sub_wire2[10:0];
wire [10:0] wrusedw = sub_wire3[10:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.wrusedw(sub_wire3),
.rdfull(),
.wrempty(),
.wrfull()
);
defparam dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 2048, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 11, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 7.109215 |
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