code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module asic_nor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = ~(a | b | c | d);
endmodule
| 8.517354 |
module asic_oa21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = (a0 | a1) & b0;
endmodule
| 7.990047 |
module asic_oa211 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input c0,
output z
);
assign z = (a0 | a1) & b0 & c0;
endmodule
| 7.434687 |
module asic_oa22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = (a0 | a1) & (b0 | b1);
endmodule
| 8.161678 |
module asic_oa221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = (a0 | a1) & (b0 | b1) & (c0);
endmodule
| 7.493696 |
module asic_oa222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = (a0 | a1) & (b0 | b1) & (c0 | c1);
endmodule
| 7.232965 |
module asic_oa31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = (a0 | a1 | a2) & b0;
endmodule
| 7.750718 |
module asic_oa311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = (a0 | a1 | a2) & b0 & c0;
endmodule
| 7.140845 |
module asic_oa32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = (a0 | a1 | a2) & (b0 | b1);
endmodule
| 7.844738 |
module asic_oa33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = (a0 | a1 | a2) & (b0 | b1 | b2);
endmodule
| 7.592399 |
module asic_oai21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = ~((a0 | a1) & b0);
endmodule
| 8.273594 |
module asic_oai22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = ~((a0 | a1) & (b0 | b1));
endmodule
| 8.262819 |
module asic_oai221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = ~((a0 | a1) & (b0 | b1) & (c0));
endmodule
| 7.621852 |
module asic_oai222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = ~((a0 | a1) & (b0 | b1) & (c0 | c1));
endmodule
| 7.648115 |
module asic_oai31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = ~((a0 | a1 | a2) & b0);
endmodule
| 7.856051 |
module asic_oai311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = ~((a0 | a1 | a2) & b0 & c0);
endmodule
| 7.629229 |
module asic_oai32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = ~((a0 | a1 | a2) & (b0 | b1));
endmodule
| 8.114832 |
module asic_oai33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = ~((a0 | a1 | a2) & (b0 | b1 | b2));
endmodule
| 7.837044 |
module asic_oddr #(
parameter PROP = "DEFAULT"
) (
input clk, // clock input
input in0, // data for clk=0
input in1, // data for clk=1
output out // dual data rate output
);
//Making in1 stable for clk=1
reg in1_sh;
always @(clk or in1) if (~clk) in1_sh <= in1;
//Using clock as dat... | 7.046166 |
module asic_or2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a | b;
endmodule
| 7.849395 |
module asic_or3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = a | b | c;
endmodule
| 8.120094 |
module asic_or4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = a | b | c | d;
endmodule
| 8.715237 |
module asic_rsync #(
parameter PROP = "DEFAULT"
) (
input clk,
input nrst_in,
output nrst_out
);
localparam SYNCPIPE = 2;
reg [SYNCPIPE-1:0] sync_pipe;
always @(posedge clk or negedge nrst_in)
if (!nrst_in) sync_pipe[SYNCPIPE-1:0] <= 'b0;
else sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNC... | 8.435879 |
module asic_sdffq #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
output reg q
);
always @(posedge clk) q <= se ? si : d;
endmodule
| 6.556008 |
module asic_sdffqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
output reg qn
);
always @(posedge clk) qn <= se ? ~si : ~d;
endmodule
| 7.403095 |
module asic_sdffrq #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nreset,
output reg q
);
always @(posedge clk or negedge nreset)
if (!nreset) q <= 1'b0;
else q <= se ? si : d;
endmodule
| 6.811708 |
module asic_sdffrqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nreset,
output reg qn
);
always @(posedge clk or negedge nreset)
if (!nreset) qn <= 1'b1;
else qn <= se ? ~si : ~d;
endmodule
| 7.59854 |
module asic_sdffsqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nset,
output reg qn
);
always @(posedge clk or negedge nset)
if (!nset) qn <= 1'b0;
else qn <= se ? ~si : ~d;
endmodule
| 7.280029 |
module asic_top (
input osc_in,
output osc_out,
input sys_rst,
input clk_sel,
output clk_core_4div,
output spi_flash_clk,
outpu... | 7.875557 |
module asic_xnor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a ^ b);
endmodule
| 7.643731 |
module asic_xnor3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = ~(a ^ b ^ c);
endmodule
| 7.819451 |
module asic_xnor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = ~(a ^ b ^ c ^ d);
endmodule
| 8.692347 |
module asic_xor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a ^ b;
endmodule
| 8.129466 |
module asic_xor3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = a ^ b ^ c;
endmodule
| 8.472741 |
module asic_xor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = a ^ b ^ c ^ d;
endmodule
| 9.015338 |
module AskDemod (
rst,
clk,
clk32,
din,
dout,
gate,
dataout,
bit_sync
);
input rst; //复位信号，高电平有效
input clk; //数据采样时钟:8MHz
input clk32; //FPGA系统时钟:32MHz
input signed [7:0] din; //基带输入数据
output signed [13:0] dout; //ASK解高后输出的基带数据
output signed [13:0] gate; //解调基带信号的均值输出
... | 7.412038 |
module recieves a bitstream and transmit it through both ASK
* and FSK combined transmission method. Under ASK, two amplitude levels
* are used while under FSK, two frequecies are used. Thus, combining
* both allows two bits to be sent simultaneously.
*
* Written Date: 02/03/2023
* Filename: ASK_FSK.v
* Last Ed... | 6.520243 |
module ask_rcv (
input wire clk,
input wire serialin,
input wire reset,
output wire syncronised,
output wire [7:0] data,
output wire ready
);
symbol_syncroniser sync (
clk,
serialin,
ready,
syncronised
);
serial_rcv rcv (
syncronised,
serialin,
da... | 7.093252 |
module syncgen(input wire clk, input wire sync, output reg syncclk);
parameter PRESCALER = 4;
reg[$clog2(PRESCALER) : 0] counter;
initial counter = 0;
always @(posedge clk or posedge sync)
begin
if(sync)
begin
counter <= 1;
syncclk <= 0;
end
else
begin
counter <= counter == PRESCALER-1 ? 0 :... | 7.129274 |
module symbol_syncroniser (
clk,
serialin,
reset,
syncclk
);
parameter PREAMBLE_WIDTH = 32;
parameter PREAMBLE = 32'hF0F0F0F0;
parameter PREAMBLE_BORDER = 31;
parameter SYNCWORD_WIDTH = 8;
parameter SYNCWORD = 8'b11100101;
parameter SYNCWORD_BORDER = 7;
parameter SYMBCLK_PRESCALER = 4;
... | 7.055143 |
module ASMD_Decryption (
output done,
output [127:0] Dout,
input [127:0] encrypted_text_in,
key_in,
input decrypt,
clock,
reset
);
wire isRound10, isRound9, init, dec_count, en_round_out, en_reg_inv_row_out, en_reg_inv_sub_out, en_reg_inv_col_out, en_Dout, decrypt, count_gt_0, count_eq_9;
... | 7.390016 |
module ASMD_Encryption (
output done,
output [127:0] Dout,
input [127:0] plain_text_in,
key_in,
input encrypt,
clock,
reset
);
wire init, isRound0, en_round_out, inc_count, en_reg_sub_out, en_reg_row_out, en_reg_col_out, en_Dout, count_lt_10, encrypt;
ControlUnit_Enryption cu_enc (
... | 6.769755 |
module asmtest (
input clk,
input rst,
input [29:0] addr,
output reg [31:0] inst
);
reg [29:0] addr_r;
always @(posedge clk) begin
addr_r <= (rst) ? (30'b0) : (addr);
end
always @(*) begin
case (addr_r)
30'h00000000: inst = 32'h93037000;
30'h00000001: inst = 32'h93001000;
... | 6.522234 |
module asm_tb ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
reg bp_enable = 1'b0;
cpu #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)
) cpu (
.clk(clk),
.rst(rst),
... | 7.710058 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
module aso_splitter (
... | 7.702374 |
module ASR128 (
d_in,
d_out
); //128 bit Arithmetic Shift Right (always shift 1 bits)
input [127:0] d_in;
output [127:0] d_out;
assign d_out[126:0] = d_in[127:1]; //Nth bit of shifted bit = N+1th bit of non-shifted bit
assign d_out[127] = d_in[127]; //sign bit of shifted bit = sign bit of not-shif... | 7.824849 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module main (
input [2:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
ASR2 inst0 (
.I({J1[1], J1[0]}),
.S({J1[2]}),
.O(inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'hCA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'hCA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module ASR8 (
d_in,
shamt,
d_out
); //ASR8
input [7:0] d_in; // 8bits input d_in
input [1:0] shamt; // 2bits input shamt
output [7:0] d_out; // 8bits output d_out
mx4 U0_mx4 (
.y (d_out[0]),
.d0(d_in[0]),
.d1(d_in[1]),
.d2(d_in[2]),
.d3(d_in[3]),
.s (shamt)
... | 7.142026 |
module asr8_2 #(
parameter WIDTH_DATA = 8,
parameter N_TAPS = 16
) (
input clk,
clr,
en,
input [$clog2(N_TAPS)-1:0] add,
input [WIDTH_DATA-1:0] d,
output [WIDTH_DATA-1:0] q
);
//creo todos los cables para unir
wire [WIDTH_DATA-1:0] cables[N_TAPS:0];
//asigno con multiplexor la sa... | 7.762157 |
module asram_if (
inout [15:0] sram_dq, // SRAM Data bus 16 Bits
output [17:0] sram_addr, // SRAM Address bus 18 Bits
output sram_ub_n, // SRAM High-byte Data Mask
output sram_lb_n, // SRAM Low-byte Data Mask
output sram_we_n, // SRAM Write Enable
output ... | 8.053831 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Barrel32L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
... | 7.342303 |
module assemble_pack (
clk, //50 Hz clk
player_x,
player_y,
wave1_y,
wave2_y,
wave3_y,
wave1_bitfield,
wave2_bitfield,
wave3_bitfield,
death,
current_score,
high_score,
packet
);
input wire clk, death;
input wire [7:0] player_x;
input wire [7:0] player_y;
in... | 7.149042 |
module assembly_instructions_memory_lbu_new_tb ();
//Tests memory behaviour. Is separated from rest because on the future
//it might spend more than one cycle to coplete each instruction
//localparam PROGRAM_MEMORY_SIZE=100;
//
//x31 register: Checks if expected and as-is inputs are equal by checking if
/... | 8.510675 |
module assembly_instructions_memory_lbu_tb ();
//Tests memory behaviour. Is separated from rest because on the future
//it might spend more than one cycle to coplete each instruction
//localparam PROGRAM_MEMORY_SIZE=100;
//
//x31 register: Checks if expected and as-is inputs are equal by checking if
//the... | 8.510675 |
module assembly_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
Riscv151 #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ),
.BIOS_MIF_HEX ("assembly_tests.mif")
) CPU (
... | 7.323137 |
module assembly_wg_testbench ();
reg clk, rst;
reg [3:0] buttons;
reg [1:0] switches;
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
wire [5:0] leds;
wire aud_pwm, aud_sd;
parameter CPU_CLOCK_PERIOD = 8;
parameter CPU_CLOCK_FREQ = 125_000_000;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk <= ~clk;
z... | 6.82841 |
module assertion_fsm (
input in,
clk,
reset,
mealy_out,
input [3:0] mealy_ps,
mealy_ns
);
property async_reset;
@(posedge clk) !reset |-> mealy_ps[0];
endproperty
property in_idle_input_one;
@(posedge clk) disable iff (!reset) (mealy_ps[0] && in) |=> mealy_ps[1];
endproperty
... | 7.071704 |
module //Required to pair up with already used "`module" in file assert_always_on_edge.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_on_edge_assert (clk, reset_n, test_expr, sampling_event, noedge_type, posedge_type, negedge_type, anye... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_always.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmod... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_change_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_cycle_sequence.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_cycle_sequence_assert (clk, reset_n, event_sequence, seq_queue, xzcheck_enable);
parameter num_cks = 2;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_decrement.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_decrement_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_delta.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_delta_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
par... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_even_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_even_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, rese... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_fifo_index.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_fifo_index_assert (clk, reset_n, push, pop, cnt, xzcheck_enable);
parameter depth=1;
parameter push_w... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_frame.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_frame_assert (clk, reset_n, start_event, test_expr, win,
ignore_new_start, reset_on_new_star... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_handshake.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_handshake_assert (clk, reset_n, req, ack, first_req, xzcheck_enable);
parameter min_ack_cycle = 0;
par... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_implication.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_implication_assert (clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable);
input clk, reset_n, an... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_increment.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_increment_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodul... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_never_unknown_async.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_unknown_async_assert (reset_n, test_expr, xzcheck_enable);
parameter width = 8;
inpu... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_unknown_assert (clk, reset_n, qualifier, test_expr, xzcheck_enable);
parameter width = 8;
input cl... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_next.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_next_assert (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_overflow.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_overflow_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 0... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_transition.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_transition_assert (clk, reset_n, test_expr, start_state, next_state, xzcheck_enable);
parameter width ... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_underflow.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_underflow_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min =... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_odd_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_odd_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_one_cold.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_one_cold_assert (clk, reset_n, test_expr, xzcheck_enable, inactive_val);
parameter width = 8;
paramet... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzc... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_proposition.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_proposition_assert (reset_n, test_expr, xzdetect_bit, xzcheck_enable);
input reset_n, test_expr;
i... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_quiescent_state.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_quiescent_state_assert (clk, reset_n, state_expr, check_value, sample_event, end_of_simulation, xzcheck_enable... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_range.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_range_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
par... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_time.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_time_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_sta... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_transition.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_transition_assert (clk, reset_n, start_state, next_state, test_expr, xzcheck_enable);
parameter width = 8;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_unchange.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_unchange_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_width.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_width_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter min_cks = 1;
parameter max_cks = 2;
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_window.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_window_assert (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, rese... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_win_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_change_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdete... | 6.783873 |
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