code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module asic_nor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = ~(a | b | c | d);
endmodule
| 8.517354 |
module asic_oa21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = (a0 | a1) & b0;
endmodule
| 7.990047 |
module asic_oa211 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input c0,
output z
);
assign z = (a0 | a1) & b0 & c0;
endmodule
| 7.434687 |
module asic_oa22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = (a0 | a1) & (b0 | b1);
endmodule
| 8.161678 |
module asic_oa221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = (a0 | a1) & (b0 | b1) & (c0);
endmodule
| 7.493696 |
module asic_oa222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = (a0 | a1) & (b0 | b1) & (c0 | c1);
endmodule
| 7.232965 |
module asic_oa31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = (a0 | a1 | a2) & b0;
endmodule
| 7.750718 |
module asic_oa311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = (a0 | a1 | a2) & b0 & c0;
endmodule
| 7.140845 |
module asic_oa32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = (a0 | a1 | a2) & (b0 | b1);
endmodule
| 7.844738 |
module asic_oa33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = (a0 | a1 | a2) & (b0 | b1 | b2);
endmodule
| 7.592399 |
module asic_oai21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = ~((a0 | a1) & b0);
endmodule
| 8.273594 |
module asic_oai22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = ~((a0 | a1) & (b0 | b1));
endmodule
| 8.262819 |
module asic_oai221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = ~((a0 | a1) & (b0 | b1) & (c0));
endmodule
| 7.621852 |
module asic_oai222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = ~((a0 | a1) & (b0 | b1) & (c0 | c1));
endmodule
| 7.648115 |
module asic_oai31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = ~((a0 | a1 | a2) & b0);
endmodule
| 7.856051 |
module asic_oai311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = ~((a0 | a1 | a2) & b0 & c0);
endmodule
| 7.629229 |
module asic_oai32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = ~((a0 | a1 | a2) & (b0 | b1));
endmodule
| 8.114832 |
module asic_oai33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = ~((a0 | a1 | a2) & (b0 | b1 | b2));
endmodule
| 7.837044 |
module asic_oddr #(
parameter PROP = "DEFAULT"
) (
input clk, // clock input
input in0, // data for clk=0
input in1, // data for clk=1
output out // dual data rate output
);
//Making in1 stable for clk=1
reg in1_sh;
always @(clk or in1) if (~clk) in1_sh <= in1;
//Using clock as data selctor
assign out = clk ? in1_sh : in0;
endmodule
| 7.046166 |
module asic_or2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a | b;
endmodule
| 7.849395 |
module asic_or3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = a | b | c;
endmodule
| 8.120094 |
module asic_or4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = a | b | c | d;
endmodule
| 8.715237 |
module asic_rsync #(
parameter PROP = "DEFAULT"
) (
input clk,
input nrst_in,
output nrst_out
);
localparam SYNCPIPE = 2;
reg [SYNCPIPE-1:0] sync_pipe;
always @(posedge clk or negedge nrst_in)
if (!nrst_in) sync_pipe[SYNCPIPE-1:0] <= 'b0;
else sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0], 1'b1};
assign nrst_out = sync_pipe[SYNCPIPE-1];
endmodule
| 8.435879 |
module asic_sdffq #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
output reg q
);
always @(posedge clk) q <= se ? si : d;
endmodule
| 6.556008 |
module asic_sdffqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
output reg qn
);
always @(posedge clk) qn <= se ? ~si : ~d;
endmodule
| 7.403095 |
module asic_sdffrq #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nreset,
output reg q
);
always @(posedge clk or negedge nreset)
if (!nreset) q <= 1'b0;
else q <= se ? si : d;
endmodule
| 6.811708 |
module asic_sdffrqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nreset,
output reg qn
);
always @(posedge clk or negedge nreset)
if (!nreset) qn <= 1'b1;
else qn <= se ? ~si : ~d;
endmodule
| 7.59854 |
module asic_sdffsqn #(
parameter PROP = "DEFAULT"
) (
input d,
input si,
input se,
input clk,
input nset,
output reg qn
);
always @(posedge clk or negedge nset)
if (!nset) qn <= 1'b0;
else qn <= se ? ~si : ~d;
endmodule
| 7.280029 |
module asic_top (
input osc_in,
output osc_out,
input sys_rst,
input clk_sel,
output clk_core_4div,
output spi_flash_clk,
output [ 1:0] spi_flash_cs,
output spi_flash_mosi,
input spi_flash_miso,
input uart_rx,
output uart_tx,
input chiplink_rx_clk,
input chiplink_rx_rst,
input chiplink_rx_send,
input [`chiplink_data_w - 1 : 0] chiplink_rx_data,
output chiplink_tx_clk,
output chiplink_tx_rst,
output chiplink_tx_send,
output [`chiplink_data_w - 1 : 0] chiplink_tx_data,
input [ 2:0] pll_cfg,
input [ 4:0] core_dip,
input interrupt
);
wire sys_clk;
wire sys_clk_buf;
wire clk_core;
wire rst_core_n;
wire clk_peri;
wire rst_peri_n;
rcg u_rcg (
.sys_clk (sys_clk_buf),
.sys_rst_n (sys_rst),
.pll_cfg (pll_cfg),
.clk_sel (clk_sel),
.clk_core (clk_core),
.rst_core_n (rst_core_n),
.clk_peri (clk_peri),
.rst_peri_n (rst_peri_n),
.clk_core_4div(clk_core_4div)
);
// oscilator
assign sys_clk = osc_in;
assign osc_out = ~osc_in;
assign sys_clk_buf = sys_clk;
soc_top u_soc_top (
.clk_core (clk_core),
.rst_core_n (rst_core_n),
.clk_peri (clk_peri),
.rst_peri_n (rst_peri_n),
.spi_flash_cs (spi_flash_cs),
.spi_flash_clk (spi_flash_clk),
.spi_flash_mosi (spi_flash_mosi),
.spi_flash_miso (spi_flash_miso),
.uart_rx (uart_rx),
.uart_tx (uart_tx),
.chiplink_rx_clk (chiplink_rx_clk),
.chiplink_rx_rst (chiplink_rx_rst),
.chiplink_rx_send(chiplink_rx_send),
.chiplink_rx_data(chiplink_rx_data),
.chiplink_tx_clk (chiplink_tx_clk),
.chiplink_tx_rst (chiplink_tx_rst),
.chiplink_tx_send(chiplink_tx_send),
.chiplink_tx_data(chiplink_tx_data),
.core_dip (core_dip),
.interrupt (interrupt)
);
endmodule
| 7.875557 |
module asic_xnor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a ^ b);
endmodule
| 7.643731 |
module asic_xnor3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = ~(a ^ b ^ c);
endmodule
| 7.819451 |
module asic_xnor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = ~(a ^ b ^ c ^ d);
endmodule
| 8.692347 |
module asic_xor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a ^ b;
endmodule
| 8.129466 |
module asic_xor3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = a ^ b ^ c;
endmodule
| 8.472741 |
module asic_xor4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = a ^ b ^ c ^ d;
endmodule
| 9.015338 |
module AskDemod (
rst,
clk,
clk32,
din,
dout,
gate,
dataout,
bit_sync
);
input rst; //复位信号，高电平有效
input clk; //数据采样时钟:8MHz
input clk32; //FPGA系统时钟:32MHz
input signed [7:0] din; //基带输入数据
output signed [13:0] dout; //ASK解高后输出的基带数据
output signed [13:0] gate; //解调基带信号的均值输出
output dataout; //判决输出的数据流
output bit_sync; //位同步信号
//对输入的ASK调制数据进行整流处理
reg signed [7:0] abs_din;
always @(posedge clk or posedge rst)
if (rst) abs_din <= 8'd0;
else if (din[7]) abs_din <= -din;
else abs_din <= din;
//实例化lpf滤波器核
wire ast_sink_valid, ast_source_ready, ast_source_valid, ast_sink_ready, reset_n;
wire [1:0] ast_source_error;
wire [1:0] ast_sink_error;
wire signed [21:0] Yout;
assign ast_source_ready = 1'b1;
assign ast_sink_valid = 1'b1;
assign ast_sink_error = 2'd0;
assign reset_n = !rst;
lpf u0 (
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(abs_din),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(Yout),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error)
);
//根据滤波器系数，可知滤波后输出数据最大位宽为输入数据位宽+14位，因此，最高数据位为
assign dout = Yout[21:8];
//实例化均值运算模块：Gate
wire signed [13:0] mean;
Gate u1 (
.rst (rst),
.clk (clk),
.din (Yout[21:8]),
.mean(mean)
);
//对解调后的基信号进行判决输出
wire demod;
wire signed [13:0] demoddata;
assign demoddata = Yout[21:8];
assign demod = (demoddata > mean) ? 1'b1 : 1'b0;
//实例化位同步模块
wire sync;
BitSync u2 (
.rst(rst),
.clk(clk32),
.datain(demod),
.sync(sync)
);
//在位同步信号的驱动下，输出判决后的基带数据流
reg data_out;
always @(posedge sync or posedge rst)
if (rst) data_out <= 1'b0;
else data_out <= demod;
assign dataout = data_out;
assign bit_sync = sync;
assign gate = mean;
endmodule
| 7.412038 |
module recieves a bitstream and transmit it through both ASK
* and FSK combined transmission method. Under ASK, two amplitude levels
* are used while under FSK, two frequecies are used. Thus, combining
* both allows two bits to be sent simultaneously.
*
* Written Date: 02/03/2023
* Filename: ASK_FSK.v
* Last Edited: 27/04/2023
* Author: Asanka Sovis
*
* (C) 2023, Asanka Sovis
* ------------------------------------------------------------------
*/
module ASK_FSK (int_clk, clk, bitstream, out_red, out_green);
input int_clk, clk, bitstream;
output out_red, out_green;
reg count = 1;
reg [1:0] bits = 2'b00;
always @(posedge clk) begin
bits[count] <= bitstream;
count = count + 1;
end
PWM pwm_red(int_clk, !bits[0], out_red);
PWM pwm_green(int_clk, (bits[0] != bits[1]), out_green);
endmodule
| 6.520243 |
module ask_rcv (
input wire clk,
input wire serialin,
input wire reset,
output wire syncronised,
output wire [7:0] data,
output wire ready
);
symbol_syncroniser sync (
clk,
serialin,
ready,
syncronised
);
serial_rcv rcv (
syncronised,
serialin,
data,
ready
);
endmodule
| 7.093252 |
module syncgen(input wire clk, input wire sync, output reg syncclk);
parameter PRESCALER = 4;
reg[$clog2(PRESCALER) : 0] counter;
initial counter = 0;
always @(posedge clk or posedge sync)
begin
if(sync)
begin
counter <= 1;
syncclk <= 0;
end
else
begin
counter <= counter == PRESCALER-1 ? 0 : counter + 1;
<<<<<<< HEAD
syncclk <= counter == (PRESCALER / 2 - 1);
=======
syncclk <= counter ? 0 : 1;
>>>>>>> 38a65153459fc010853102e33625ae1b7515ffd2
end
end
endmodule
| 7.129274 |
module symbol_syncroniser (
clk,
serialin,
reset,
syncclk
);
parameter PREAMBLE_WIDTH = 32;
parameter PREAMBLE = 32'hF0F0F0F0;
parameter PREAMBLE_BORDER = 31;
parameter SYNCWORD_WIDTH = 8;
parameter SYNCWORD = 8'b11100101;
parameter SYNCWORD_BORDER = 7;
parameter SYMBCLK_PRESCALER = 4;
input wire clk;
input wire serialin;
output wire syncclk;
input wire reset;
reg preamble_lock;
reg syncwrd_lock;
wire preamble_sync;
wire syncwrd_sync;
wire [31:0] abstract0, abstract1;
wire abstract2 = symbclk;
correlator #(PREAMBLE_WIDTH, PREAMBLE, PREAMBLE_BORDER) prmbl (
clk,
serialin,
preamble_sync,
abstract0
);
syncgen #(SYMBCLK_PRESCALER) symbgen (
clk,
preamble_sync,
symbclk
);
correlator #(SYNCWORD_WIDTH, SYNCWORD, SYNCWORD_BORDER) syncwrd (
symbclk & preamble_lock,
serialin,
syncwrd_sync,
abstract1
);
assign syncclk = syncwrd_lock & preamble_lock & symbclk;
always @(posedge preamble_sync or posedge reset) preamble_lock <= reset ? 1'b0 : 1'b1;
always @(posedge syncwrd_sync or posedge reset) syncwrd_lock <= reset ? 1'b0 : 1'b1;
endmodule
| 7.055143 |
module ASMD_Decryption (
output done,
output [127:0] Dout,
input [127:0] encrypted_text_in,
key_in,
input decrypt,
clock,
reset
);
wire isRound10, isRound9, init, dec_count, en_round_out, en_reg_inv_row_out, en_reg_inv_sub_out, en_reg_inv_col_out, en_Dout, decrypt, count_gt_0, count_eq_9;
ControlUnit_Decryption cu_dec (
done,
isRound10,
isRound9,
init,
dec_count,
en_round_out,
en_reg_inv_row_out,
en_reg_inv_sub_out,
en_reg_inv_col_out,
en_Dout,
decrypt,
count_gt_0,
count_eq_9,
clock,
reset
);
Datapath_Decryption dp_dec (
Dout,
count_gt_0,
count_eq_9,
encrypted_text_in,
key_in,
isRound10,
isRound9,
init,
dec_count,
en_round_out,
en_reg_inv_row_out,
en_reg_inv_sub_out,
en_reg_inv_col_out,
en_Dout,
clock,
reset
);
endmodule
| 7.390016 |
module ASMD_Encryption (
output done,
output [127:0] Dout,
input [127:0] plain_text_in,
key_in,
input encrypt,
clock,
reset
);
wire init, isRound0, en_round_out, inc_count, en_reg_sub_out, en_reg_row_out, en_reg_col_out, en_Dout, count_lt_10, encrypt;
ControlUnit_Enryption cu_enc (
done,
init,
isRound0,
en_round_out,
inc_count,
en_reg_sub_out,
en_reg_row_out,
en_reg_col_out,
en_Dout,
count_lt_10,
encrypt,
clock,
reset
);
Datapath_Encryption dp_enc (
Dout,
count_lt_10,
key_in,
plain_text_in,
init,
isRound0,
en_round_out,
inc_count,
en_reg_sub_out,
en_reg_row_out,
en_reg_col_out,
en_Dout,
reset,
clock
);
endmodule
| 6.769755 |
module asmtest (
input clk,
input rst,
input [29:0] addr,
output reg [31:0] inst
);
reg [29:0] addr_r;
always @(posedge clk) begin
addr_r <= (rst) ? (30'b0) : (addr);
end
always @(*) begin
case (addr_r)
30'h00000000: inst = 32'h93037000;
30'h00000001: inst = 32'h93001000;
30'h00000002: inst = 32'h13012000;
30'h00000003: inst = 32'h33841300;
30'h00000004: inst = 32'hb3041400;
30'h00000005: inst = 32'h33859000;
30'h00000006: inst = 32'hb70f0080;
30'h00000007: inst = 32'h938f1f00;
30'h00000008: inst = 32'h970f0080;
30'h00000009: inst = 32'hb38f0f00;
30'h0000000a: inst = 32'h638c7300;
30'h0000000b: inst = 32'hb70f0080;
30'h0000000c: inst = 32'h13000000;
30'h0000000d: inst = 32'h13000000;
30'h0000000e: inst = 32'h13000000;
30'h0000000f: inst = 32'h13000000;
30'h00000010: inst = 32'h93051500;
30'h00000011: inst = 32'hef008000;
30'h00000012: inst = 32'h33000000;
30'h00000013: inst = 32'h93800000;
30'h00000014: inst = 32'h93001000;
30'h00000015: inst = 32'h37050010;
30'h00000016: inst = 32'h23201500;
30'h00000017: inst = 32'h23222500;
30'h00000018: inst = 32'h83250500;
30'h00000019: inst = 32'h03264500;
30'h0000001a: inst = 32'h13010600;
30'h0000001b: inst = 32'h93800500;
default: inst = 32'h00000000;
endcase
end
endmodule
| 6.522234 |
module asm_tb ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
reg bp_enable = 1'b0;
cpu #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)
) cpu (
.clk(clk),
.rst(rst),
.bp_enable(bp_enable),
.serial_in(1'b1),
.serial_out()
);
// A task to check if the value contained in a register equals an expected value
task check_reg;
input [4:0] reg_number;
input [31:0] expected_value;
input [10:0] test_num;
if (expected_value !== `RF_PATH.mem[reg_number]) begin
$display("FAIL - test %d, got: %d, expected: %d for reg %d", test_num,
`RF_PATH.mem[reg_number], expected_value, reg_number);
$finish();
end else begin
$display("PASS - test %d, got: %d for reg %d", test_num, expected_value, reg_number);
end
endtask
// A task that runs the simulation until a register contains some value
task wait_for_reg_to_equal;
input [4:0] reg_number;
input [31:0] expected_value;
while (`RF_PATH.mem[reg_number] !== expected_value) @(posedge clk);
endtask
initial begin
$readmemh("../../software/asm/asm.hex", `BIOS_PATH.mem, 0, 4095);
`ifndef IVERILOG
$vcdpluson;
`endif
`ifdef IVERILOG
$dumpfile("asm_tb.fst");
$dumpvars(0, asm_tb);
`endif
rst = 0;
// Reset the CPU
rst = 1;
repeat (10) @(posedge clk); // Hold reset for 10 cycles
@(negedge clk);
rst = 0;
// Your processor should begin executing the code in /software/asm/start.s
// Test ADD
wait_for_reg_to_equal(20, 32'd1); // Run the simulation until the flag is set to 1
check_reg(1, 32'd300, 1); // Verify that x1 contains 300
// Test BEQ
wait_for_reg_to_equal(20, 32'd2); // Run the simulation until the flag is set to 2
check_reg(1, 32'd500, 2); // Verify that x1 contains 500
check_reg(2, 32'd100, 3); // Verify that x2 contains 100
$display("ALL ASSEMBLY TESTS PASSED!");
$finish();
end
initial begin
repeat (100) @(posedge clk);
$display("Failed: timing out");
$fatal();
end
endmodule
| 7.710058 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
module aso_splitter (
input wire clk, // clock_st.clk
input wire reset, // .reset
input wire [31:0] asi_sink_data, // sink.data
output wire asi_sink_ready, // .ready
input wire asi_sink_valid, // .valid
input wire [5:0] asi_sink_error, // .error
input wire asi_sink_startofpacket, // .startofpacket
input wire asi_sink_endofpacket, // .endofpacket
input wire [1:0] asi_sink_empty, // .empty
output wire [31:0] aso_source0_data, // source0.data
input wire aso_source0_ready, // .ready
output wire aso_source0_valid, // .valid
output wire [5:0] aso_source0_error, // .error
output wire aso_source0_startofpacket, // .startofpacket
output wire aso_source0_endofpacket, // .endofpacket
output wire [1:0] aso_source0_empty, // .empty
output wire [31:0] aso_source1_data, // source1.data
input wire aso_source1_ready, // .ready
output wire aso_source1_valid, // .valid
output wire [5:0] aso_source1_error, // .error
output wire aso_source1_startofpacket, // .startofpacket
output wire aso_source1_endofpacket, // .endofpacket
output wire [1:0] aso_source1_empty // .empty
);
assign asi_sink_ready = aso_source0_ready | aso_source1_ready;
assign aso_source0_data = asi_sink_data;
assign aso_source0_valid = asi_sink_valid;
assign aso_source0_error = asi_sink_error;
assign aso_source0_startofpacket = asi_sink_startofpacket;
assign aso_source0_endofpacket = asi_sink_endofpacket;
assign aso_source0_empty = asi_sink_empty;
assign aso_source1_data = asi_sink_data;
assign aso_source1_valid = asi_sink_valid;
assign aso_source1_error = asi_sink_error;
assign aso_source1_startofpacket = asi_sink_startofpacket;
assign aso_source1_endofpacket = asi_sink_endofpacket;
assign aso_source1_empty = asi_sink_empty;
endmodule
| 7.702374 |
module ASR128 (
d_in,
d_out
); //128 bit Arithmetic Shift Right (always shift 1 bits)
input [127:0] d_in;
output [127:0] d_out;
assign d_out[126:0] = d_in[127:1]; //Nth bit of shifted bit = N+1th bit of non-shifted bit
assign d_out[127] = d_in[127]; //sign bit of shifted bit = sign bit of not-shifted bit
endmodule
| 7.824849 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module main (
input [2:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
ASR2 inst0 (
.I({J1[1], J1[0]}),
.S({J1[2]}),
.O(inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'hCA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'hCA)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
Mux2 inst0 (
.I(I),
.S(S),
.O(inst0_O)
);
Mux2 inst1 (
.I({I[1], I[1]}),
.S(S),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] inst0_O;
ASR2_1 inst0 (
.I(I),
.S(S[0]),
.O(inst0_O)
);
assign O = inst0_O;
endmodule
| 7.459007 |
module ASR8 (
d_in,
shamt,
d_out
); //ASR8
input [7:0] d_in; // 8bits input d_in
input [1:0] shamt; // 2bits input shamt
output [7:0] d_out; // 8bits output d_out
mx4 U0_mx4 (
.y (d_out[0]),
.d0(d_in[0]),
.d1(d_in[1]),
.d2(d_in[2]),
.d3(d_in[3]),
.s (shamt)
); // instance by using 8 mx4
mx4 U1_mx4 (
.y (d_out[1]),
.d0(d_in[1]),
.d1(d_in[2]),
.d2(d_in[3]),
.d3(d_in[4]),
.s (shamt)
);
mx4 U2_mx4 (
.y (d_out[2]),
.d0(d_in[2]),
.d1(d_in[3]),
.d2(d_in[4]),
.d3(d_in[5]),
.s (shamt)
);
mx4 U3_mx4 (
.y (d_out[3]),
.d0(d_in[3]),
.d1(d_in[4]),
.d2(d_in[5]),
.d3(d_in[6]),
.s (shamt)
);
mx4 U4_mx4 (
.y (d_out[4]),
.d0(d_in[4]),
.d1(d_in[5]),
.d2(d_in[6]),
.d3(d_in[7]),
.s (shamt)
);
mx4 U5_mx4 (
.y (d_out[5]),
.d0(d_in[5]),
.d1(d_in[6]),
.d2(d_in[7]),
.d3(d_in[7]),
.s (shamt)
);
mx4 U6_mx4 (
.y (d_out[6]),
.d0(d_in[6]),
.d1(d_in[7]),
.d2(d_in[7]),
.d3(d_in[7]),
.s (shamt)
);
mx4 U7_mx4 (
.y (d_out[7]),
.d0(d_in[7]),
.d1(d_in[7]),
.d2(d_in[7]),
.d3(d_in[7]),
.s (shamt)
);
endmodule
| 7.142026 |
module asr8_2 #(
parameter WIDTH_DATA = 8,
parameter N_TAPS = 16
) (
input clk,
clr,
en,
input [$clog2(N_TAPS)-1:0] add,
input [WIDTH_DATA-1:0] d,
output [WIDTH_DATA-1:0] q
);
//creo todos los cables para unir
wire [WIDTH_DATA-1:0] cables[N_TAPS:0];
//asigno con multiplexor la salida y la entrada
assign q = cables[add+1];
assign cables[0] = d;
//genero los registros
genvar i;
generate //creo los registros necesarios
for (i = 0; i < N_TAPS; i = i + 1) begin
register_asr #(
.N(WIDTH_DATA)
) retardos (
.clk(clk),
.clr(clr),
.en (en),
.d (cables[i]),
.q (cables[i+1])
);
end
endgenerate
endmodule
| 7.762157 |
module asram_if (
inout [15:0] sram_dq, // SRAM Data bus 16 Bits
output [17:0] sram_addr, // SRAM Address bus 18 Bits
output sram_ub_n, // SRAM High-byte Data Mask
output sram_lb_n, // SRAM Low-byte Data Mask
output sram_we_n, // SRAM Write Enable
output sram_ce_n, // SRAM Chip Enable
output sram_oe_n, // SRAM Output Enable
input wb_clk_i, // WISHBONE interface
input wb_rst_i,
input [18:0] wb_adr_i,
input [31:0] wb_dat_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
input [ 3:0] wb_sel_i,
output [31:0] wb_dat_o,
output wb_ack_o
);
//---------------------------------------------------
// wb_size_bridge
wire [15:0] wb_lo_dat_o;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o;
wire wb_lo_stb_o;
wire wb_lo_we_o;
wire [ 1:0] wb_lo_sel_o;
wire wb_lo_ack_i = 1'b1;
wire wb_lo_err_i = 1'b0;
wire wb_lo_rty_i = 1'b0;
wb_size_bridge i_wb_size_bridge (
.wb_hi_clk_i(wb_clk_i),
.wb_hi_rst_i(wb_rst_i),
.wb_hi_dat_o(wb_dat_o),
.wb_hi_dat_i(wb_dat_i),
.wb_hi_adr_i({13'h0000, wb_adr_i}),
.wb_hi_cyc_i(wb_cyc_i),
.wb_hi_stb_i(wb_stb_i),
.wb_hi_we_i (wb_we_i),
.wb_hi_sel_i(wb_sel_i),
.wb_hi_ack_o(wb_ack_o),
.wb_hi_err_o(),
.wb_hi_rty_o(),
.wb_lo_clk_o(),
.wb_lo_rst_o(),
.wb_lo_dat_i(sram_dq),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_we_o (wb_lo_we_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
.lo_byte_if_i(1'b0)
);
//---------------------------------------------------
// outputs
assign sram_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
assign sram_addr = wb_lo_adr_o[18:1];
assign sram_ub_n = ~wb_lo_sel_o[1];
assign sram_lb_n = ~wb_lo_sel_o[0];
assign sram_we_n = ~wb_lo_we_o;
assign sram_ce_n = 1'b0;
assign sram_oe_n = wb_lo_we_o;
endmodule
| 8.053831 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Barrel32L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0101: data_o = data_i << 5;
4'b0110: data_o = data_i << 6;
4'b0111: data_o = data_i << 7;
4'b1000: data_o = data_i << 8;
4'b1001: data_o = data_i << 9;
4'b1010: data_o = data_i << 10;
4'b1011: data_o = data_i << 11;
4'b1100: data_o = data_i << 12;
4'b1101: data_o = data_i << 13;
4'b1110: data_o = data_i << 14;
default: data_o = data_i << 15;
endcase
endmodule
| 7.342303 |
module assemble_pack (
clk, //50 Hz clk
player_x,
player_y,
wave1_y,
wave2_y,
wave3_y,
wave1_bitfield,
wave2_bitfield,
wave3_bitfield,
death,
current_score,
high_score,
packet
);
input wire clk, death;
input wire [7:0] player_x;
input wire [7:0] player_y;
input wire [7:0] wave1_y;
input wire [7:0] wave2_y;
input wire [7:0] wave3_y;
input wire [39:0] wave1_bitfield;
input wire [39:0] wave2_bitfield;
input wire [39:0] wave3_bitfield;
input wire [15:0] current_score, high_score;
output reg [175:0] packet;
reg [5:0] death_cnt;
initial begin
packet <= 0;
death_cnt <= 0;
end
always @(posedge clk) begin
packet[15:0] <= 16'h55AA;
if (death == 1 && death_cnt == 5) begin //50 for implementation
packet[31:16] <= 16'hFFFF;
packet[55:40] <= high_score;
packet[71:56] <= current_score;
end else begin
death_cnt <= (death == 1) ? (death_cnt + 1) : 0;
packet[23:16] <= player_x;
packet[31:24] <= player_y;
packet[79:40] <= wave1_bitfield;
end
packet[39:32] <= wave1_y;
packet[87:80] <= wave2_y;
packet[127:88] <= wave2_bitfield;
packet[135:128] <= wave3_y;
packet[175:136] <= wave3_bitfield;
end
endmodule
| 7.149042 |
module assembly_instructions_memory_lbu_new_tb ();
//Tests memory behaviour. Is separated from rest because on the future
//it might spend more than one cycle to coplete each instruction
//localparam PROGRAM_MEMORY_SIZE=100;
//
//x31 register: Checks if expected and as-is inputs are equal by checking if
//their difference is 0, via reg x31
//x1 register: The number of the current test in file (helpful for debugging)
reg clk;
reg reset;
SoC mut (
.clk (clk),
.reset(reset)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
//Some test started, but didnt finish, so there was probably an error jumping instructions and this is bad.
if (mut.cpu.instruction === 32'h xxxxxxxx && mut.cpu.single_instr.reg_mem.memory[31] === 32'd 0) begin
$display("%c[1;31m", 27);
$display(
"Some test didnt finish properly, as x(31) is %d. Its probably linked to a branch/jump test!",
mut.cpu.single_instr.reg_mem.memory[31]);
$fatal();
end
end
integer approximate_clock_count;
integer current_test = -1;
integer last_test = -1;
initial begin
$info(
"Testing memory behaviour from assembly file. x31 is probed for pass, must always be zero!!!");
$dumpfile(`VCDFILEPATH);
$dumpvars(0, mut);
//$monitor("%2t,reset=%b,clk=%b,pc=%d,current instruction=%h, x1=%h, x10=%h,x11=%h, x31=%h",$time,reset,clk,mut.cpu.pc,mut.cpu.instruction,mut.cpu.single_instr.reg_mem.memory[1],mut.cpu.single_instr.reg_mem.memory[10],mut.cpu.single_instr.reg_mem.memory[11],mut.cpu.single_instr.reg_mem.memory[31]);
$readmemh(`MEMFILEPATH, mut.rom.program_memory, 0, PROGRAM_MEMORY_SIZE_WORDS - 1);
reset = 1;
#20;
@(negedge clk) #1;
reset = 0;
approximate_clock_count = 0;
while (approximate_clock_count < PROGRAM_MEMORY_SIZE_WORDS && !(mut.cpu.instruction === 32'h xxxxxxxx)) begin // Stops on invalid instruction or end of memory
current_test = mut.cpu.single_instr.reg_mem.memory[1];
if (current_test !== last_test) begin
last_test = current_test;
$display("Running sub-test number: %d", current_test);
end
$display("PC is %d, instruction: %h", mut.cpu.pc, mut.cpu.instruction);
@(posedge clk) #1;
if (mut.cpu.single_instr.reg_mem.memory[31] !== 32'd0) begin
if (mut.cpu.single_instr.reg_mem.memory[31] !== mut.cpu.single_instr.reg_mem.memory[1]) begin
$display("%c[1;31m", 27);
$display(
"Test %d didnt finish properly and was taken over by %d. Its probably linked to a branch/jump test!",
mut.cpu.single_instr.reg_mem.memory[1], mut.cpu.single_instr.reg_mem.memory[31]);
$fatal();
end
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[29],
mut.cpu.single_instr.reg_mem.memory[30], {
"x29 register should be as x30 (benchmark)"});
end
approximate_clock_count += 1;
// Possible infinite loop is detected
// This onyl makes sense if there is one cycle per instruction
// Otherwise, it makes no sense.
if (PROGRAM_MEMORY_SIZE_WORDS <= approximate_clock_count) begin
$display("%c[1;31m", 27);
$display(
"Probalbe infinite loop. If you are sure this is not a bug, increase the size of program memory");
$fatal();
end
end
#1;
$display("Simulation finished");
$finish;
end
endmodule
| 8.510675 |
module assembly_instructions_memory_lbu_tb ();
//Tests memory behaviour. Is separated from rest because on the future
//it might spend more than one cycle to coplete each instruction
//localparam PROGRAM_MEMORY_SIZE=100;
//
//x31 register: Checks if expected and as-is inputs are equal by checking if
//their difference is 0, via reg x31
//x1 register: The number of the current test in file (helpful for debugging)
reg clk;
reg reset;
SoC mut (
.clk (clk),
.reset(reset)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
integer i;
integer current_test = -1;
integer last_test = -1;
initial begin
$info(
"Testing memory behaviour from assembly file. x31 is probed for pass, must always be zero!!!");
$dumpfile(`VCDFILEPATH);
$dumpvars(0, mut);
//$monitor("%2t,reset=%b,clk=%b,pc=%d,current instruction=%h, x1=%h, x10=%h,x11=%h, x31=%h",$time,reset,clk,mut.cpu.pc,mut.cpu.instruction,mut.cpu.single_instr.reg_mem.memory[1],mut.cpu.single_instr.reg_mem.memory[10],mut.cpu.single_instr.reg_mem.memory[11],mut.cpu.single_instr.reg_mem.memory[31]);
$readmemh(`MEMFILEPATH, mut.rom.program_memory, 0, PROGRAM_MEMORY_SIZE_WORDS - 1);
reset = 1;
#20;
@(negedge clk) #1;
reset = 0;
i = 0;
while (i < PROGRAM_MEMORY_SIZE_WORDS && !(mut.cpu.instruction === 32'h xxxxxxxx)) begin // Stops on invalid instruction or end of memory
current_test = mut.cpu.single_instr.reg_mem.memory[1];
if (current_test !== last_test) begin
last_test = current_test;
$display("Running sub-test number: %d", current_test);
end
$display("PC is %d, instruction: %h", mut.cpu.pc, mut.cpu.instruction);
@(posedge clk) #1;
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[31], 32'd0, {
"x31 register has to be zero"});
i += 1;
end
#1;
$display("Simulation finished");
$finish;
end
endmodule
| 8.510675 |
module assembly_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
Riscv151 #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ),
.BIOS_MIF_HEX ("assembly_tests.mif")
) CPU (
.clk(clk),
.rst(rst),
.FPGA_SERIAL_RX(),
.FPGA_SERIAL_TX(),
.csr()
);
// A task to check if the value contained in a register equals an expected value
task check_reg;
input [4:0] reg_number;
input [31:0] expected_value;
input [10:0] test_num;
if (expected_value !== `RF_PATH.mem[reg_number]) begin
$display("FAIL - test %d, got: %d, expected: %d for reg %d", test_num,
`RF_PATH.mem[reg_number], expected_value, reg_number);
$finish();
end else begin
$display("PASS - test %d, got: %d for reg %d", test_num, expected_value, reg_number);
end
endtask
// A task that runs the simulation until a register contains some value
task wait_for_reg_to_equal;
input [4:0] reg_number;
input [31:0] expected_value;
wait (`RF_PATH.mem[reg_number] === expected_value);
endtask
initial begin
$dumpfile("assembly_testbench.vcd");
$dumpvars;
#0;
rst = 0;
// Reset the CPU
rst = 1;
repeat (10) @(posedge clk); // Hold reset for 10 cycles
@(negedge clk);
rst = 0;
// Your processor should begin executing the code in /software/assembly_tests/start.s
// Test Vector Add
wait_for_reg_to_equal(20, 32'd1); // Run the simulation until the flag is set to 1
check_reg(1, 32'd153, 1); // Verify that x1 contains 28
// Test BEQ
$display("ALL ASSEMBLY TESTS PASSED!");
$finish();
end
integer i;
always @(CPU.instruction_IF) begin
$display("PC_IF = %h, instruction_IF = %h, Time = %10t", CPU.PC_IF, CPU.instruction_IF, $time);
#1;
for (i = 0; i < 32; i = i + 1) begin
$display("x%2d= %h ", i, CPU.rf.mem[i]);
end
end
initial begin
#10000;
$display("Failed: timing out");
$finish();
end
endmodule
| 7.323137 |
module assembly_wg_testbench ();
reg clk, rst;
reg [3:0] buttons;
reg [1:0] switches;
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
wire [5:0] leds;
wire aud_pwm, aud_sd;
parameter CPU_CLOCK_PERIOD = 8;
parameter CPU_CLOCK_FREQ = 125_000_000;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk <= ~clk;
z1top fpga (
.CLK_125MHZ_FPGA(clk),
.BUTTONS(buttons),
.SWITCHES(switches),
.LEDS(leds),
.FPGA_SERIAL_RX(FPGA_SERIAL_RX),
.FPGA_SERIAL_TX(FPGA_SERIAL_TX),
.aud_pwm(aud_pwm),
.aud_sd(aud_sd)
);
// A task to check if the value contained in a register equals an expected value
task check_reg;
input [4:0] reg_number;
input [31:0] expected_value;
input [10:0] test_num;
if (expected_value !== `REGFILE_ARRAY_PATH) begin
$display("FAIL - test %d, got: %d, expected: %d for reg %d", test_num, `REGFILE_ARRAY_PATH,
expected_value, reg_number);
end else begin
$display("PASS - test %d, got: %d for reg %d", test_num, expected_value, reg_number);
end
endtask
// A task that runs the simulation until a register contains some value
task wait_for_reg_to_equal;
input [4:0] reg_number;
input [31:0] expected_value;
while (`REGFILE_ARRAY_PATH !== expected_value) @(posedge clk);
endtask
reg done = 0;
initial begin
$readmemh("../../software/assembly_wg_tests/assembly_tests.hex", fpga.cpu.bios_mem.mem, 0,
4095);
`ifndef IVERILOG
$vcdpluson;
`endif
`ifdef IVERILOG
$dumpfile("assembly_wg_testbench.fst");
$dumpvars(0, assembly_wg_testbench);
//$dumpvars(0,fpga.cpu.handshake_tx.rf.registers[1]);
//$dumpvars(0,CPU.rf.registers[2]);
`endif
buttons[0] = 0;
// Reset the CPU
buttons[0] = 1;
repeat (30) @(posedge clk); // Hold reset for 30 cycles
buttons[0] = 0;
fork
begin
repeat (500000) @(posedge clk);
if (!done) begin
$display("Failed: timing out");
$finish();
end
end
join
`ifndef IVERILOG
$vcdplusoff;
`endif
$finish();
end
endmodule
| 6.82841 |
module assertion_fsm (
input in,
clk,
reset,
mealy_out,
input [3:0] mealy_ps,
mealy_ns
);
property async_reset;
@(posedge clk) !reset |-> mealy_ps[0];
endproperty
property in_idle_input_one;
@(posedge clk) disable iff (!reset) (mealy_ps[0] && in) |=> mealy_ps[1];
endproperty
property in_idle_input_zero;
@(posedge clk) disable iff (!reset) (mealy_ps[0] && !in) |=> $stable(
mealy_ps
);
endproperty
property in_a_input_one;
@(posedge clk) disable iff (!reset) (mealy_ps[1] && in) |=> mealy_ps[2];
endproperty
property in_a_input_zero;
@(posedge clk) disable iff (!reset) (mealy_ps[1] && !in) |=> mealy_ps[0];
endproperty
property in_b_input_one;
@(posedge clk) disable iff (!reset) (mealy_ps[2] && in) |=> $stable(
mealy_ps
);
endproperty
property in_b_input_zero;
@(posedge clk) disable iff (!reset) (mealy_ps[2] && !in) |=> mealy_ps[3];
endproperty
property in_c_input_one;
@(posedge clk) disable iff (!reset) (mealy_ps[3] && in) |=> (mealy_ps[1] |-> mealy_out);
endproperty
property in_c_input_zero;
@(posedge clk) disable iff (!reset) (mealy_ps[3] && !in) |=> $stable(
mealy_ps
);
endproperty
property output_one;
@(posedge clk) disable iff (!reset) mealy_out |-> (mealy_ps[3] && in);
endproperty
assert property (async_reset);
assert property (in_idle_input_one);
assert property (in_idle_input_zero);
assert property (in_a_input_one);
assert property (in_a_input_zero);
assert property (in_b_input_one);
assert property (in_b_input_zero);
assert property (in_c_input_one);
assert property (in_c_input_zero);
assert property (output_one);
endmodule
| 7.071704 |
module //Required to pair up with already used "`module" in file assert_always_on_edge.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_on_edge_assert (clk, reset_n, test_expr, sampling_event, noedge_type, posedge_type, negedge_type, anyedge_type, xzcheck_enable);
input clk, reset_n, test_expr, sampling_event, noedge_type, posedge_type, negedge_type, anyedge_type,
xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_always.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_change_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start,
xzcheck_enable);
parameter width = 8;
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start,
xzcheck_enable;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_cycle_sequence.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_cycle_sequence_assert (clk, reset_n, event_sequence, seq_queue, xzcheck_enable);
parameter num_cks = 2;
parameter necessary_condition = 0;
input clk, reset_n;
input [num_cks-1:0] event_sequence, seq_queue;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_decrement.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_decrement_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_delta.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_delta_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_even_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_even_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_fifo_index.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_fifo_index_assert (clk, reset_n, push, pop, cnt, xzcheck_enable);
parameter depth=1;
parameter push_width = 1;
parameter pop_width = 1;
parameter simultaneous_push_pop = 1;
parameter cnt_reg_width = 1;
input clk, reset_n;
input [push_width-1:0] push;
input [pop_width-1:0] pop;
input [cnt_reg_width-1:0] cnt;
input xzcheck_enable;
//Any required modeling layer code for asserted properties here
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_frame.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_frame_assert (clk, reset_n, start_event, test_expr, win,
ignore_new_start, reset_on_new_start, error_on_new_start,
xzcheck_enable);
parameter min_cks = 1;
parameter max_cks = 2;
input clk, reset_n, start_event, test_expr, win,
ignore_new_start, reset_on_new_start, error_on_new_start,
xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_handshake.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_handshake_assert (clk, reset_n, req, ack, first_req, xzcheck_enable);
parameter min_ack_cycle = 0;
parameter max_ack_cycle = 0;
parameter req_drop = 0;
parameter deassert_count = 0;
parameter max_ack_length = 0;
input clk, reset_n, req, ack, first_req, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_implication.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_implication_assert (clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable);
input clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_increment.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_increment_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_never_unknown_async.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_unknown_async_assert (reset_n, test_expr, xzcheck_enable);
parameter width = 8;
input reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_unknown_assert (clk, reset_n, qualifier, test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, qualifier, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_next.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_next_assert (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
parameter check_overlapping = 1;
parameter check_missing_start = 1;
input clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_overflow.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_overflow_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 0;
parameter max = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_transition.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_transition_assert (clk, reset_n, test_expr, start_state, next_state, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [(width-1):0] test_expr, start_state, next_state;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_no_underflow.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_no_underflow_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 0;
parameter max = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_odd_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_odd_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_one_cold.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_one_cold_assert (clk, reset_n, test_expr, xzcheck_enable, inactive_val);
parameter width = 8;
parameter inactive = `OVL_ONE_COLD;
input clk, reset_n, xzcheck_enable, inactive_val;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_proposition.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_proposition_assert (reset_n, test_expr, xzdetect_bit, xzcheck_enable);
input reset_n, test_expr;
input xzdetect_bit, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_quiescent_state.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_quiescent_state_assert (clk, reset_n, state_expr, check_value, sample_event, end_of_simulation, xzcheck_enable);
parameter width = 8;
input clk, reset_n, sample_event;
input [width-1:0] state_expr, check_value;
input end_of_simulation;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_range.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_range_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_time.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_time_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input test_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_transition.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_transition_assert (clk, reset_n, start_state, next_state, test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n;
input [width-1:0] test_expr, start_state, next_state;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_unchange.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_unchange_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter width = 8;
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_width.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_width_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter min_cks = 1;
parameter max_cks = 2;
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_window.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_window_assert (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_win_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_change_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
| 6.783873 |
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