code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module: ArrMul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ArrMul_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire [7:0] Result;
integer i;
// Instantiate the Uni... | 6.916491 |
module arrow_rom (
addr,
dout
);
input [4:0] addr;
output [7:0] dout;
reg [7:0] dout;
always @(*)
case (addr)
0: dout = 8'h9F;
1: dout = 8'hFF;
2: dout = 8'h8F;
3: dout = 8'hFF;
4: dout = 8'h87;
5: dout = 8'hFF;
6: dout = 8'h83;
7: dout = 8'hFF;
... | 6.537251 |
module arr_mul_tb;
reg [ 7:0] a;
reg [ 7:0] b;
wire [15:0] x;
arr_mul mul_8b (
a,
b,
x
);
initial begin
a = 8'd255;
b = 8'd255;
#20 a = 8'd25;
b = 8'd55;
#20 a = 8'd25;
b = 8'd4;
#20 a = 8'd5;
b = 8'd10;
#20 a = 8'd25;
b = 8'd10;
#20 a = 8'd55;... | 6.712094 |
module arsc_alu #(
parameter N /// Bus width
) (
input wire add_cmd,
input wire comp_cmd,
input wire shr_cmd,
input wire shl_cmd,
input wire and_cmd,
input wire or_cmd,
input wire xor_cmd,
input wire tra1_cmd,
input wire tra2_cmd,
input wire [N-1:0] in1,
in2,
output ... | 7.648483 |
module arsc_bus #(
parameter N = 16 /// Bus width
) (
/// BUS1 (input line)
input wire [ 5:0] bus1_ctrl,
input wire [N-1:0] bus1_node0,
input wire [N-1:0] bus1_node1,
input wire [N-1:0] bus1_node2,
input wire [N-1:0] bus1_node3,
input wire [N-1:0] bus1_node4,
input wire [N-1... | 7.820976 |
module arsc_bus_tb;
localparam T = 20, N = 16;
reg [2:0] i;
/// BUS1 signals
reg [5:0] bus1_ctrl;
reg [N-1:0] bus1_node0, bus1_node1, bus1_node2, bus1_node3, bus1_node4, bus1_node5;
wire [N-1:0] bus1_out;
/// BUS2 signals
reg [ 5:0] bus2_ctrl;
reg [N-1:0] bus2_node0, bus2_node1, bus2_node2, bus2... | 6.722564 |
module arsc_system (
/// Input signals
input wire ref_clk, /// System and SDRAM clks are derived from the reference clk
input wire reset_n,
input wire start_n, /// High -> Low causes ARSC to run (if not already running)
output wire running, /// High if ARSC is currently active
/// SDRAM s... | 7.247179 |
module exists only to separate the arsc_system pins from the actual FPGA pins
/// that will be used
module arsc_system_wrapper
(
input wire CLOCK_50, /// Reference 50MHz clock
input wire [3:0] KEY, /// KEY[0] - reset_n, KEY[1] - start_n
output wire [9:0] LEDR, /// LEDR[0] - ARSC running
/// SDRAM signals
o... | 6.761512 |
module arshift #(.Dsz(1), .Diz(1)) (I, Z , S);
input ${IZ_RANGE} I;
input ${S_RANGE} S;
output ${IZ_RANGE} Z;
specify
(I *> Z) = Diz;
(S *> Z) = Dsz;
endspecify
assign Z = ${invZ} (I >>> S);
endmodule
| 6.782332 |
module arSRLFIFO (
CLK,
RST_N,
ENQ,
DEQ,
FULL_N,
EMPTY_N,
D_IN,
D_OUT,
CLR
);
parameter width = 128;
parameter l2depth = 5;
localparam depth = 2 ** l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input [width-1:... | 7.092947 |
module arSRLFIFOD (
CLK,
RST_N,
ENQ,
DEQ,
FULL_N,
EMPTY_N,
D_IN,
D_OUT,
CLR
);
parameter width = 128;
parameter l2depth = 5;
localparam depth = 2 ** l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input [width-1... | 6.995793 |
module arSRLFIFOD_test1 #(
parameter width = 128,
parameter l2depth = 4
) (
input CLK,
input RST_N,
input CLR,
input ENQ,
input DEQ,
output FULL_N,
output EMPTY_N,
input [width-1:0] D_IN,
... | 7.670875 |
module arSRLFIFO_a (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire empt... | 6.803883 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module arSRLFIFO_c (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire empt... | 6.786832 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module arSRLFIFO_d (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [127:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [127:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire emp... | 6.824399 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module arSRLFIFO_test1 #(
parameter width = 128,
parameter l2depth = 4
) (
input CLK,
input RST_N,
input CLR,
input ENQ,
input DEQ,
output FULL_N,
output EMPTY_N,
input [width-1:0] D_IN,
... | 7.566086 |
module arithmetic_no_div (
input [7:0] a0,
a1,
output [7:0] sum,
output [7:0] min,
output [7:0] mul
//,output[7:0] div
//output[7:0] mod
//output[7:0] pow
);
//Load other module(s)
//Definition for Variables in the module
//Logical
assign sum = a0 + a1;
assign min = a0 - ... | 7.008424 |
module artix7_pll (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
, output clkout1_o
, output clkout2_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire clkfbout_buffered_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
wire pll_clkout1_w;
wire pll_clkout1_buffere... | 6.840162 |
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire ... | 7.233807 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [7:0] sw,
output [15:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_... | 8.460384 |
module ArtyA7 (
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
);
wire [31:0] gpio_i, gpio_o, gpio_ot, gpio;
assign gpio = (gpio_ot) ? gpio_o : 32'hZZZZZZZZ;
assign led = gpio[3:0];
fmrv32im_artya7_wrapper u_fmrv32im_artya7_wrapper (
.CLK100MHZ(CLK100MHZ)... | 6.899416 |
module ArtyA7 (
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
);
wire CLK;
clk_wiz_0 u_clk_wiz_0 (
.clk_in1 (CLK100MHZ),
.clk_out1(CLK)
);
wire [31:0] gpio_i, gpio_o, gpio_ot, gpio;
assign gpio = (gpio_ot) ? gpio_o : 32'hZZZZZZZZ;
assign led =... | 6.899416 |
module artyz (
input CLK,
input xRESET_N,
input [9:0] SW,
output [7:0] LED_A, // OUTPORT
output [7:0] LED_B, // PORTID
output [3:0] IOZ
);
wire xRESET_P = ~xRESET_N;
icf3z ICf3z (
.CLK(CLK),
.xINPORT_P(SW[9:2]),
.xRESET_P(xRESET_P),
.xINT0_P(SW[0]),
.xINT1_P... | 6.786845 |
module arty_a7_clock_gen (
input wire i_clk,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
.STA... | 6.670268 |
module arty_mmcm (
// Clock in ports
input clk_in,
// Clock out ports
output clk_50m,
// Status and control signals
input resetn,
output locked
);
arty_mmcm_clk_wiz inst (
// Clock in ports
.clk_in (clk_in),
// Clock out ports
.clk_50m(clk_50m),
// Status... | 7.586649 |
module arty_mmcm_clk_wiz ( // Clock in ports
input clk_in,
// Clock out ports
output clk_50m,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in_arty_mmcm),
.I(clk_in)
);
... | 8.708173 |
module arty_mmcm (
clk_in,
clk_50m,
resetn,
locked
);
input clk_in;
output clk_50m;
input resetn;
output locked;
wire clk_50m;
(* IBUF_LOW_PWR *)wire clk_in;
wire locked;
wire resetn;
arty_mmcm_arty_mmcm_clk_wiz inst (
.clk_50m(clk_50m),
.clk_in (clk_in),
.locked (l... | 7.586649 |
module arty_picorv32_wb_soc (
input CLK100MHZ,
output [3:0] led,
input [3:0] sw,
input [3:0] btn,
output uart_rxd_out,
input uart_txd_in
);
wire wb_clk;
wire wb_rst;
plle2_base_wb_clkgen #(
.INPUT_FREQUENCY(100),
.DIVCLK_DIVIDE(5),
.CLKFBOUT_MULT(42),
.WB_DIV... | 7.178272 |
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire ... | 7.233807 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [7:0] sw,
output [9:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_j... | 8.460384 |
module arty_top (
input xtal_in, // 100MHz
input [3:0] sw,
input [3:0] btn,
output [3:0] led,
// QSPI
output qspi_clk,
output qspi_cs_n,
inout [3:0] qspi_dq,
// JTAG
input tck_i,
input trstn_i,
input tms_i,
input td_i,
output td_o,
// UART
outpu... | 6.866394 |
module art_fsm #(
// I/O width parameter
parameter fsm_type = 0
) (
//
input Clk,
input Reset,
input i_Mem_Ack,
input i_Art_Req,
output o_serving,
input i_Art_Miss,
input i_I_flag,
input i_R_flag,
input i_X_flag,
input ... | 10.719458 |
module from WCI-Slave to AXI4-Lite Master
// Copyright (c) 2010 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// 2010-09-12 Module declaration in Verilog
// 2010-09-14 20b, 1MB Address Window on both sides of bridge
// 2011-01-15 Switch to 32b 4GB address
module arWCI2A4LM (
input bridge_Clk,
input bri... | 8.718231 |
module aRx (
clk,
rst,
iRx,
oAction,
oDataOut,
oDataReady,
oByteCnt,
oCrcErr
);
//----- PARAMETERS ----------------------
parameter FCLK = 50000; // [kHz] System clock frequency, max freq = 80000 kHz
parameter BRATE = 115200; // [baud] Baudrate, min brate = 9600 baud
paramete... | 8.82391 |
module ARY_MS_DRNG (
port_a,
port_b,
port_c
);
input [3:0] port_a;
input [0:3] port_b;
output [3:0] port_c;
assign port_c = port_a & port_b;
endmodule
| 6.955818 |
module ARY_NR_LBND (
in_a,
in_b,
out_a
);
input [1:0] in_a, in_b;
output [4:1] out_a;
assign out_a = {in_a, in_b};
endmodule
| 7.41692 |
module ARY_NR_LOPR (
x,
a,
b
);
output x;
input [1:0] a, b;
reg y, z;
assign x = !{y, z};
always @(a or b) begin
y = a && 2'b10;
z = 2 || b;
end
endmodule
| 7.080637 |
module AR_Control (
LD,
CLR,
INR,
T,
D,
R,
I
);
input R, I;
input [7:0] T, D;
output LD, CLR, INR;
wire D7n, Rn;
wire a1, a2, a3;
assign D7n = ~D[7];
assign Rn = ~R;
assign a1 = D7n & I & T[3];
assign a2 = T[2] & Rn;
assign a3 = Rn & T[0];
assign CLR = T[0] & R;... | 6.562652 |
module AR_MUX (
input [7:0] ADR_TX,
input [22:0] DAT_TX,
input [7:0] ADR_RX,
input [22:0] DAT_RX,
input [1:0] S,
output wire [15:0] DISPL
);
wire [15:0] d0 = {ADR_TX, ADR_RX};
wire [15:0] d1 = {1'b0, DAT_TX[22:16], 1'b0, DAT_RX[22:16]};
wire [15:0] d2 = {DAT_TX[15:8], DAT_RX[15:8]};
wir... | 6.849001 |
module ar_mux_2to1 (
input areset,
// master 1
input [31:0] araddr_m1,
input [ 3:0] arid_m1,
input [ 1:0] arburst_m1,
input [ 3:0] arlen_m1,
input [ 2:0] arsize_m1,
input [ 1:0] arlock_m1,
input [ 3:0] arcache_m1,
input [ 2:0] arprot_m1,
input arvalid_m1,
... | 6.940971 |
module AR_register (
BIN,
clk,
WR,
DMADDR
);
/*
Control signals:
clk - Clock signal
WR - Control signal to write to the register
Data paths:
DMADDR - Wire that carries the data memory address from AR to data memory
BIN - The BUS to write to the register
*/
input [15:0] BIN;
input clk;
input W... | 6.823568 |
module as (
input [7:0] in_wave,
input [1:0] amp,
output reg [7:0] out_wave
);
always @(in_wave, amp) begin
out_wave = 0;
case (amp)
2'b00: out_wave = in_wave;
2'b01: out_wave = {{1{in_wave[7]}}, in_wave[7:1]};
2'b10: out_wave = {{2{in_wave[7]}}, in_wave[7:2]};
2'b11: out_... | 7.238699 |
module HB1xp67_ASAP7_75t_SL (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
endmodule
| 7.235152 |
module FAx1_ASAP7_75t_SL (
CON,
SN,
A,
B,
CI
);
output CON, SN;
input A, B, CI;
// Function
wire A__bar, B__bar, CI__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire int_fwire_6;
not (CI__bar, CI);
not (B__bar, B);
and (int_fwire... | 7.381443 |
module HAxp5_ASAP7_75t_SL (
CON,
SN,
A,
B
);
output CON, SN;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
or (CON, A__bar, B__bar);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (SN, int_fwire_1, in... | 7.893692 |
module ICGx3_ASAP7_75t_R (
GCLK,
ENA,
SE,
CLK
);
output GCLK;
input ENA, SE, CLK;
reg notifier;
wire delayed_ENA, delayed_SE, delayed_CLK;
// Function
wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
not (int_fwire_clk, delayed_CLK);
or (int_fwire_test, delayed_ENA, delayed_SE);
alt... | 6.911855 |
module AND2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.219768 |
module AND2x4_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.809886 |
module AND2x6_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.841012 |
module AND3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.847744 |
module AND3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.03983 |
module AND3x4_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.71006 |
module AND4x1_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
and (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.34864 |
module AND4x2_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
and (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.620849 |
module AND5x1_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
and (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.496571 |
module AND5x2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
and (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.848884 |
module FAx1_ASAP7_75t_R (
CON,
SN,
A,
B,
CI
);
output CON, SN;
input A, B, CI;
// Function
wire A__bar, B__bar, CI__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire int_fwire_6;
not (CI__bar, CI);
not (B__bar, B);
and (int_fwire_... | 7.381443 |
module HAxp5_ASAP7_75t_R (
CON,
SN,
A,
B
);
output CON, SN;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
or (CON, A__bar, B__bar);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (SN, int_fwire_1, int... | 7.893692 |
module MAJIxp5_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
not (C__bar, C);
not (B__bar, B);
and (int_fwire_0, B__bar, C__bar);
not (A__bar, A);
and (int_fwire_1, A__bar, C__bar);
and (i... | 7.399805 |
module MAJx2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
and (int_fwire_0, B, C);
and (int_fwire_1, A, C);
and (int_fwire_2, A, B);
or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
// Timing
specify
if ((B & ~C)) (... | 7.060583 |
module MAJx3_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
and (int_fwire_0, B, C);
and (int_fwire_1, A, C);
and (int_fwire_2, A, B);
or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
// Timing
specify
if ((B & ~C)) (... | 7.136546 |
module NAND2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.621557 |
module NAND2x1p5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.126562 |
module NAND2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.852236 |
module NAND2xp33_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.347385 |
module NAND2xp5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.236259 |
module NAND2xp67_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.14241 |
module NAND3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endm... | 8.545869 |
module NAND3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endm... | 8.802598 |
module NAND3xp33_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
en... | 8.178327 |
module NAND4xp25_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;... | 8.037681 |
module NAND4xp75_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;... | 7.910677 |
module NAND5xp2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar, E__bar;
not (E__bar, E);
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar, E__ba... | 8.238079 |
module NOR2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.379351 |
module NOR2x1p5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.859676 |
module NOR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.69965 |
module NOR2xp33_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.186936 |
module NOR2xp67_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.981423 |
module NOR3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endm... | 8.668731 |
module NOR3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endm... | 8.916058 |
module NOR3xp33_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
en... | 8.282953 |
module NOR4xp25_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;... | 7.712023 |
module NOR4xp75_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;... | 7.650467 |
module NOR5xp2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar, E__bar;
not (E__bar, E);
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar, E__ba... | 8.163665 |
module OR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.857343 |
module OR2x4_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.360341 |
module OR2x6_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.502604 |
module OR3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.436237 |
module OR3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.574449 |
module OR3x4_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.479961 |
module OR4x2_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
or (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.22738 |
module OR5x1_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
or (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.243287 |
module OR5x2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
or (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.40716 |
module TIEHIx1_ASAP7_75t_R (
H
);
output H;
// Function
buf (H, 1'b1);
// Timing
specify
endspecify
endmodule
| 7.028828 |
module XNOR2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (B... | 7.503261 |
module XNOR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (B... | 7.576248 |
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