code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module: ArrMul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ArrMul_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire [7:0] Result;
integer i;
// Instantiate the Unit Under Test (UUT)
ArrMul uut (
.A(A),
.B(B),
.Result(Result)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
$monitor ("A=%0d B=%0d Result=%0d",A, B, Result);
for ( i= 0; i < 16 ; i=i+1)
begin
#10 A <= $random;
B <= $random;
end
$finish;
end
endmodule
| 6.916491 |
module arrow_rom (
addr,
dout
);
input [4:0] addr;
output [7:0] dout;
reg [7:0] dout;
always @(*)
case (addr)
0: dout = 8'h9F;
1: dout = 8'hFF;
2: dout = 8'h8F;
3: dout = 8'hFF;
4: dout = 8'h87;
5: dout = 8'hFF;
6: dout = 8'h83;
7: dout = 8'hFF;
8: dout = 8'h81;
9: dout = 8'hFF;
10: dout = 8'h80;
11: dout = 8'hfF;
12: dout = 8'h80;
13: dout = 8'h7F;
14: dout = 8'h80;
15: dout = 8'h3F;
16: dout = 8'h80;
17: dout = 8'h1F;
18: dout = 8'h80;
19: dout = 8'h0F;
20: dout = 8'h80;
21: dout = 8'h07;
22: dout = 8'h80;
23: dout = 8'h7f;
24: dout = 8'h88;
25: dout = 8'h7F;
26: dout = 8'h9c;
27: dout = 8'h3F;
28: dout = 8'hbc;
29: dout = 8'h3f;
30: dout = 8'hfe;
default: dout = 8'h1f;
endcase
endmodule
| 6.537251 |
module arr_mul_tb;
reg [ 7:0] a;
reg [ 7:0] b;
wire [15:0] x;
arr_mul mul_8b (
a,
b,
x
);
initial begin
a = 8'd255;
b = 8'd255;
#20 a = 8'd25;
b = 8'd55;
#20 a = 8'd25;
b = 8'd4;
#20 a = 8'd5;
b = 8'd10;
#20 a = 8'd25;
b = 8'd10;
#20 a = 8'd55;
b = 8'd30;
#20 a = 8'd12;
b = 8'd13;
#20 a = 8'd255;
b = 8'd254;
#20 a = 8'd255;
b = 8'd254;
end
endmodule
| 6.712094 |
module arsc_alu #(
parameter N /// Bus width
) (
input wire add_cmd,
input wire comp_cmd,
input wire shr_cmd,
input wire shl_cmd,
input wire and_cmd,
input wire or_cmd,
input wire xor_cmd,
input wire tra1_cmd,
input wire tra2_cmd,
input wire [N-1:0] in1,
in2,
output wire cr,
of,
output wire [N-1:0] out
);
wire [N:0] bus;
assign bus =
(add_cmd) ? in1 + in2 :
(comp_cmd) ? ~in1 :
(shr_cmd) ? { 1'b0, in1[N-1], in1[N-1:1] } :
(shl_cmd) ? { in1[N-1], in1[N-2:0], 1'b0 } :
(and_cmd) ? { 1'b0, in1 & in2 } :
(or_cmd) ? { 1'b0, in1 | in2 } :
(xor_cmd) ? { 1'b0, in1 ^ in2 } :
(tra1_cmd) ? { 1'b0, in1 } :
(tra2_cmd) ? { 1'b0, in2 } :
{ (N+1) { 1'b0 } } ;
assign cr = bus[N] & add_cmd;
assign of =
((add_cmd & ~(in1[N-1] ^ in2[N-1]) & (bus[N-1] ^ in1[N-1])) ||
(shl_cmd & (bus[N] ^ bus[N-1])));
assign out = bus[N-1:0];
endmodule
| 7.648483 |
module arsc_bus #(
parameter N = 16 /// Bus width
) (
/// BUS1 (input line)
input wire [ 5:0] bus1_ctrl,
input wire [N-1:0] bus1_node0,
input wire [N-1:0] bus1_node1,
input wire [N-1:0] bus1_node2,
input wire [N-1:0] bus1_node3,
input wire [N-1:0] bus1_node4,
input wire [N-1:0] bus1_node5,
output wire [N-1:0] bus1_out,
/// BUS2 (input line)
input wire [ 5:0] bus2_ctrl,
input wire [N-1:0] bus2_node0,
input wire [N-1:0] bus2_node1,
input wire [N-1:0] bus2_node2,
input wire [N-1:0] bus2_node3,
input wire [N-1:0] bus2_node4,
input wire [N-1:0] bus2_node5,
output wire [N-1:0] bus2_out,
/// BUS3 (output line)
input wire [ 5:0] bus3_ctrl,
input wire [N-1:0] bus3_in,
input wire [N-1:0] bus3_node0_in,
input wire [N-1:0] bus3_node1_in,
input wire [N-1:0] bus3_node2_in,
input wire [N-1:0] bus3_node3_in,
input wire [N-1:0] bus3_node4_in,
input wire [N-1:0] bus3_node5_in,
output reg [N-1:0] bus3_node0_out,
output reg [N-1:0] bus3_node1_out,
output reg [N-1:0] bus3_node2_out,
output reg [N-1:0] bus3_node3_out,
output reg [N-1:0] bus3_node4_out,
output reg [N-1:0] bus3_node5_out
);
/// Route inputs to BUS1 depending on the control signal
assign bus1_out =
(bus1_ctrl[0] == 1'b1) ? bus1_node0 :
(bus1_ctrl[1] == 1'b1) ? bus1_node1 :
(bus1_ctrl[2] == 1'b1) ? bus1_node2 :
(bus1_ctrl[3] == 1'b1) ? bus1_node3 :
(bus1_ctrl[4] == 1'b1) ? bus1_node4 :
(bus1_ctrl[5] == 1'b1) ? bus1_node5 :
{ N{ 1'b0 } };
/// Route inputs to BUS2 depending on the control signal
assign bus2_out =
(bus2_ctrl[0] == 1'b1) ? bus2_node0 :
(bus2_ctrl[1] == 1'b1) ? bus2_node1 :
(bus2_ctrl[2] == 1'b1) ? bus2_node2 :
(bus2_ctrl[3] == 1'b1) ? bus2_node3 :
(bus2_ctrl[4] == 1'b1) ? bus2_node4 :
(bus2_ctrl[5] == 1'b1) ? bus2_node5 :
{ N{ 1'b0 } };
/// Route input signal of the BUS3 to correct output port
always @* begin
/// Defaults
bus3_node0_out = bus3_node0_in;
bus3_node1_out = bus3_node1_in;
bus3_node2_out = bus3_node2_in;
bus3_node3_out = bus3_node3_in;
bus3_node4_out = bus3_node4_in;
bus3_node5_out = bus3_node5_in;
if (bus3_ctrl[0] == 1'b1) bus3_node0_out = bus3_in;
else if (bus3_ctrl[1] == 1'b1) bus3_node1_out = bus3_in;
else if (bus3_ctrl[2] == 1'b1) bus3_node2_out = bus3_in;
else if (bus3_ctrl[3] == 1'b1) bus3_node3_out = bus3_in;
else if (bus3_ctrl[4] == 1'b1) bus3_node4_out = bus3_in;
else if (bus3_ctrl[5] == 1'b1) bus3_node5_out = bus3_in;
end
endmodule
| 7.820976 |
module arsc_bus_tb;
localparam T = 20, N = 16;
reg [2:0] i;
/// BUS1 signals
reg [5:0] bus1_ctrl;
reg [N-1:0] bus1_node0, bus1_node1, bus1_node2, bus1_node3, bus1_node4, bus1_node5;
wire [N-1:0] bus1_out;
/// BUS2 signals
reg [ 5:0] bus2_ctrl;
reg [N-1:0] bus2_node0, bus2_node1, bus2_node2, bus2_node3, bus2_node4, bus2_node5;
wire [N-1:0] bus2_out;
/// BUS3 signals
reg [ 5:0] bus3_ctrl;
reg [N-1:0] bus3_in;
reg [N-1:0]
bus3_node0_in, bus3_node1_in, bus3_node2_in, bus3_node3_in, bus3_node4_in, bus3_node5_in;
wire [N-1:0]
bus3_node0_out, bus3_node1_out, bus3_node2_out,
bus3_node3_out, bus3_node4_out, bus3_node5_out;
arsc_bus #(
.N(N)
) uut (
.bus1_ctrl(bus1_ctrl)
, .bus1_node0(bus1_node0)
, .bus1_node1(bus1_node1)
, .bus1_node2(bus1_node2)
, .bus1_node3(bus1_node3)
, .bus1_node4(bus1_node4)
, .bus1_node5(bus1_node5)
, .bus1_out(bus1_out)
, .bus2_ctrl(bus2_ctrl)
, .bus2_node0(bus2_node0)
, .bus2_node1(bus2_node1)
, .bus2_node2(bus2_node2)
, .bus2_node3(bus2_node3)
, .bus2_node4(bus2_node4)
, .bus2_node5(bus2_node5)
, .bus2_out(bus2_out)
, .bus3_ctrl(bus3_ctrl)
, .bus3_in(bus3_in)
, .bus3_node0_in(bus3_node0_in)
, .bus3_node1_in(bus3_node1_in)
, .bus3_node2_in(bus3_node2_in)
, .bus3_node3_in(bus3_node3_in)
, .bus3_node4_in(bus3_node4_in)
, .bus3_node5_in(bus3_node5_in)
, .bus3_node0_out(bus3_node0_out)
, .bus3_node1_out(bus3_node1_out)
, .bus3_node2_out(bus3_node2_out)
, .bus3_node3_out(bus3_node3_out)
, .bus3_node4_out(bus3_node4_out)
, .bus3_node5_out(bus3_node5_out)
);
initial begin
/// Test BUS1 and BUS2
bus1_ctrl = 6'b0;
bus2_ctrl = 6'b0;
bus1_node0 = 56;
bus1_node1 = -123;
bus1_node2 = 1234;
bus1_node3 = -6543;
bus1_node4 = 23456;
bus1_node5 = -10000;
bus2_node0 = -888;
bus2_node1 = 7432;
bus2_node2 = 9872;
bus2_node3 = -5;
bus2_node4 = 9911;
bus2_node5 = 11111;
#(T);
/// Activate each input line in turn for BUS1 and BUS2
for (i = 0; i <= 5; i = i + 1) begin
bus1_ctrl = 6'b0;
bus2_ctrl = 6'b0;
bus1_ctrl[i] = 1'b1;
bus2_ctrl[i] = 1'b1;
#(T);
end
/// Test BUS3
bus3_ctrl = 6'b0;
bus3_in = 5461;
bus3_node0_in = 9999;
bus3_node1_in = -439;
bus3_node2_in = 12345;
bus3_node3_in = -777;
bus3_node4_in = -8843;
bus3_node5_in = 29333;
#(T);
/// Activate each output line in turn for BUS3
for (i = 0; i <= 5; i = i + 1) begin
bus3_ctrl = 6'b0;
bus3_ctrl[i] = 1'b1;
#(T);
end
$stop;
end
endmodule
| 6.722564 |
module arsc_system (
/// Input signals
input wire ref_clk, /// System and SDRAM clks are derived from the reference clk
input wire reset_n,
input wire start_n, /// High -> Low causes ARSC to run (if not already running)
output wire running, /// High if ARSC is currently active
/// SDRAM signals
output wire [12:0] dram_addr, /// RAM address generated by the SDRAM controller
output wire [1:0] dram_ba, /// RAM bank address
output wire dram_cas_n, /// Column address strobe
output wire dram_cke, /// Clock enable
output wire dram_cs_n, /// Chip select
inout wire [15:0] dram_dq, /// Data to write to or data read from RAM
output wire [1:0] dram_dqm, /// Data mask
output wire dram_ras_n, /// Row address strobe
output wire dram_we_n, /// Write enable
output wire dram_clk, /// SDRAM clock (to eliminate the clock skew effect its phase is
/// shifted by -3ns compared to the system clock)
/// To VGA
output wire [3:0] vga_r, /// Red color signal
output wire [3:0] vga_g, /// Green color signal
output wire [3:0] vga_b, /// Blue color signal
output wire vga_hs, /// Horizontal sync
output wire vga_vs /// Vertical sync
);
/// ARSC is a 16-bit computer
localparam N = 16, DEBOUNCER_INIT = 1000000;
/// Use on-chip RAM for main memory
localparam MEMORY_TYPE = 0;
wire
sys_clk
, actual_start_n
, read_n
, write_n
, rd_data_valid
, wait_req
, io_done
, rd_indev_n
, wr_outdev_n
, io_device;
wire [N-1:0] wr_data, rd_data, addr, dil;
/// PLL (sys_clk and dram_clk are 50MHz clocks)
pll pll_unit (
.refclk (ref_clk),
.rst (~reset_n),
.outclk_0(sys_clk),
.outclk_1(dram_clk), /// Phase-shifted by -3ns compared to sys_clk
.locked ()
);
/// Debouncer (and edge detector)
debouncer #(
.INIT(DEBOUNCER_INIT)
) db_unit (
.clk(sys_clk)
, .reset_n(reset_n)
, .in(start_n)
, .db_level()
, .db_tick()
, .db_tick_n(actual_start_n)
);
/// Memory controller
memory_controller #(
.MEMORY_TYPE(MEMORY_TYPE)
, .N(N)
) memory_ctrl_unit (
.clk(sys_clk),
.reset_n(reset_n),
.address(addr),
.wr_data(wr_data),
.read_n(read_n),
.write_n(write_n),
.rd_data(rd_data),
.rd_data_valid(rd_data_valid),
.wait_req(wait_req),
/// To SDRAM
.dram_addr(dram_addr),
.dram_ba(dram_ba),
.dram_cas_n(dram_cas_n),
.dram_cke(dram_cke),
.dram_cs_n(dram_cs_n),
.dram_dq(dram_dq),
.dram_dqm(dram_dqm),
.dram_ras_n(dram_ras_n),
.dram_we_n(dram_we_n)
);
/// ARSC CPU
arsc_cpu #(
.N(N)
) cpu_unit (
.clk(sys_clk)
, .reset_n(reset_n)
, .start_n(actual_start_n)
, .rd_data_valid(rd_data_valid)
, .wait_req(wait_req)
, .io_done(io_done)
, .rd_data(rd_data)
, .dil(dil)
, .read_n(read_n)
, .write_n(write_n)
, .rd_indev_n(rd_indev_n)
, .wr_outdev_n(wr_outdev_n)
, .io_dev(io_device)
, .addr(addr)
, .wr_data(wr_data)
, .running(running)
);
/// I/O Controller
io_controller #(
.N(N)
) io_ctrl_unit (
.clk(sys_clk)
, .reset_n(reset_n)
, .start_n(actual_start_n)
, .io_device(io_device)
, .rd_input_n(rd_indev_n)
, .wr_output_n(wr_outdev_n)
, .addr(addr)
, .wr_data(wr_data)
, .io_done(io_done)
, .rd_data(dil)
, .vga_r(vga_r)
, .vga_g(vga_g)
, .vga_b(vga_b)
, .vga_hs(vga_hs)
, .vga_vs(vga_vs)
);
endmodule
| 7.247179 |
module exists only to separate the arsc_system pins from the actual FPGA pins
/// that will be used
module arsc_system_wrapper
(
input wire CLOCK_50, /// Reference 50MHz clock
input wire [3:0] KEY, /// KEY[0] - reset_n, KEY[1] - start_n
output wire [9:0] LEDR, /// LEDR[0] - ARSC running
/// SDRAM signals
output wire [12:0] DRAM_ADDR,
inout wire [15:0] DRAM_DQ,
output wire [1:0] DRAM_BA,
output wire DRAM_LDQM,
output wire DRAM_UDQM,
output wire DRAM_RAS_N,
output wire DRAM_CAS_N,
output wire DRAM_CKE,
output wire DRAM_CLK,
output wire DRAM_WE_N,
output wire DRAM_CS_N,
/// VGA signals
output wire [3:0] VGA_R, /// Red color
output wire [3:0] VGA_G, /// Green color
output wire [3:0] VGA_B, /// Blue color
output wire VGA_HS, /// Horizontal sync
output wire VGA_VS /// Vertical sync
);
arsc_system arsc
(
.ref_clk(CLOCK_50)
, .reset_n(KEY[0])
, .start_n(KEY[1])
, .running(LEDR)
, .dram_addr(DRAM_ADDR)
, .dram_ba(DRAM_BA)
, .dram_cas_n(DRAM_CAS_N)
, .dram_cke(DRAM_CKE)
, .dram_cs_n(DRAM_CS_N)
, .dram_dq(DRAM_DQ)
, .dram_dqm({ DRAM_UDQM, DRAM_LDQM })
, .dram_ras_n(DRAM_RAS_N)
, .dram_we_n(DRAM_WE_N)
, .dram_clk(DRAM_CLK)
, .vga_r(VGA_R)
, .vga_g(VGA_G)
, .vga_b(VGA_B)
, .vga_hs(VGA_HS)
, .vga_vs(VGA_VS)
);
endmodule
| 6.761512 |
module arshift #(.Dsz(1), .Diz(1)) (I, Z , S);
input ${IZ_RANGE} I;
input ${S_RANGE} S;
output ${IZ_RANGE} Z;
specify
(I *> Z) = Diz;
(S *> Z) = Dsz;
endspecify
assign Z = ${invZ} (I >>> S);
endmodule
| 6.782332 |
module arSRLFIFO (
CLK,
RST_N,
ENQ,
DEQ,
FULL_N,
EMPTY_N,
D_IN,
D_OUT,
CLR
);
parameter width = 128;
parameter l2depth = 5;
localparam depth = 2 ** l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input [width-1:0] D_IN;
output [width-1:0] D_OUT;
reg [l2depth-1:0] pos; // head position
reg [ width-1:0] dat [depth-1:0]; // SRL FIFO
reg empty, full;
integer i;
// Note that proper SRL inference in XST 13.4 seems to require that there be
// a separate, not-conditional-upon-reset always block for the SRL data
// array to be updated in...
always @(posedge CLK) begin
if (ENQ) begin
for (i = depth - 1; i > 0; i = i - 1) dat[i] <= dat[i-1];
dat[0] <= D_IN;
end
end
always @(posedge CLK) begin
if (!RST_N || CLR) begin
pos <= 1'b0;
empty <= 1'b1;
full <= 1'b0;
end else begin
if (!ENQ && DEQ) pos <= pos - 1;
if (ENQ && !DEQ) pos <= pos + 1;
empty <= ((pos == 0 && !ENQ) || (pos == 1 && (DEQ && !ENQ)));
full <= ((pos == (depth - 1) && !DEQ) || (pos == (depth - 2) && (ENQ && !DEQ)));
end
end
assign FULL_N = !full;
assign EMPTY_N = !empty;
assign D_OUT = dat[pos-1];
endmodule
| 7.092947 |
module arSRLFIFOD (
CLK,
RST_N,
ENQ,
DEQ,
FULL_N,
EMPTY_N,
D_IN,
D_OUT,
CLR
);
parameter width = 128;
parameter l2depth = 5;
localparam depth = 2 ** l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input [width-1:0] D_IN;
output [width-1:0] D_OUT;
reg [l2depth-1:0] pos; // Head position
reg [ width-1:0] dat [depth-1:0]; // SRL FIFO
reg [ width-1:0] dreg; // Ouput register
reg sempty, sfull, dempty; // Flags
wire sdx; // SRL-DEQ and D-ENQ
integer i;
// Standard stupidity since there is no builtin verilog way to do this
function [l2depth-1:0] trunc(input [31:0] val);
trunc = val[l2depth-1:0];
endfunction
// Note that proper SRL inference in XST 13.4 seems to require that there be
// a separate, not-conditional-upon-reset always block for the SRL data
// array to be updated in...
always @(posedge CLK) begin
if (ENQ) begin // SRL should be inferred here...
for (i = depth - 1; i > 0; i = i - 1) dat[i] <= dat[i-1];
dat[0] <= D_IN;
end
end
// We have also pulled dreg out into its own block as it neither needs to
// have any defined state upon reset; and we do not want it in the reset
// conditional block where it would take on an implicit clock-enable of RST_N...
always @(posedge CLK) begin
if (sdx) begin
dreg <= dat[pos-1]; // transfer the SRL to the D reg
end
end
always @(posedge CLK) begin
if (!RST_N || CLR) begin
pos <= 'b0;
sempty <= 1'b1;
sfull <= 1'b0;
dempty <= 1'b1;
end else begin
if (!ENQ && sdx) pos <= trunc(pos - 1); // suppress warning
if (ENQ && !sdx) pos <= trunc(pos + 1); // suppress warning
sempty <= ((pos == 0 && !ENQ) || (pos == 1 && (sdx && !ENQ)));
sfull <= ((pos == (depth - 1) && !sdx) || (pos == (depth - 2) && (ENQ && !sdx)));
// This registered version of the SRLFIFO operates as if there is 1-deep FIFO
// appended to the output of the SRL FIFO. An ENQ of of the 1-deep FIFO
// must happen with a DEQ of the SRL FIFO, this internal signal is "sdx"
if (sdx) begin
dempty <= 1'b0; // dempty becomes False when we load the 1-deep FIFO
end
if (DEQ && sempty) begin
dempty <= 1'b1; // dempty becomes True when we DEQ and nothing to sdx
end
end
end
assign sdx = ((dempty && !sempty) || (!dempty && DEQ && !sempty));
assign FULL_N = !sfull;
assign EMPTY_N = !dempty;
assign D_OUT = dreg;
endmodule
| 6.995793 |
module arSRLFIFOD_test1 #(
parameter width = 128,
parameter l2depth = 4
) (
input CLK,
input RST_N,
input CLR,
input ENQ,
input DEQ,
output FULL_N,
output EMPTY_N,
input [width-1:0] D_IN,
output [width-1:0] D_OUT
);
arSRLFIFOD #(
.width (width),
.l2depth(l2depth)
) arSRLFIFOD_i0 (
.CLK (CLK),
.RST_N (RST_N),
.CLR (CLR),
.ENQ (ENQ),
.DEQ (DEQ),
.FULL_N (FULL_N),
.EMPTY_N(EMPTY_N),
.D_IN (D_IN),
.D_OUT (D_OUT)
);
endmodule
| 7.670875 |
module arSRLFIFO_a (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire empty_n;
wire full_n_r;
wire empty_n_r;
wire [1:0] level;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_a fifo_1 (
.clk(CLK),
.rst(RST_N),
.clr(CLR),
.din(D_IN),
.we(ENQ),
.dout(D_OUT),
.re(DEQ),
.full(full),
.empty(empty),
.full_n(full_n),
.empty_n(empty_n),
.full_r(FULL_N),
.empty_r(EMPTY_N),
.full_n_r(full_n_r),
.empty_n_r(empty_n_r),
.level(level)
);
endmodule
| 6.803883 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module arSRLFIFO_c (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire empty_n;
wire full_n_r;
wire empty_n_r;
wire [1:0] level;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_c fifo_1 (
.clk(CLK),
.rst(RST_N),
.clr(CLR),
.din(D_IN),
.we(ENQ),
.dout(D_OUT),
.re(DEQ),
.full(full),
.empty(empty),
.full_n(full_n),
.empty_n(empty_n),
.full_r(FULL_N),
.empty_r(EMPTY_N),
.full_n_r(full_n_r),
.empty_n_r(empty_n_r),
.level(level)
);
endmodule
| 6.786832 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module arSRLFIFO_d (
CLK,
RST_N,
D_IN,
ENQ,
DEQ,
CLR,
D_OUT,
EMPTY_N,
FULL_N
);
input CLK;
input RST_N;
input [127:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [127:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire full;
wire empty;
wire full_n;
wire empty_n;
wire full_n_r;
wire empty_n_r;
wire [1:0] level;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_d fifo_1 (
.clk(CLK),
.rst(RST_N),
.clr(CLR),
.din(D_IN),
.we(ENQ),
.dout(D_OUT),
.re(DEQ),
.full(full),
.empty(empty),
.full_n(full_n),
.empty_n(empty_n),
.full_r(FULL_N),
.empty_r(EMPTY_N),
.full_n_r(full_n_r),
.empty_n_r(empty_n_r),
.level(level)
);
endmodule
| 6.824399 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module arSRLFIFO_test1 #(
parameter width = 128,
parameter l2depth = 4
) (
input CLK,
input RST_N,
input CLR,
input ENQ,
input DEQ,
output FULL_N,
output EMPTY_N,
input [width-1:0] D_IN,
output [width-1:0] D_OUT
);
arSRLFIFO #(
.width (width),
.l2depth(l2depth)
) arSRLFIFO_i0 (
.CLK (CLK),
.RST_N (RST_N),
.CLR (CLR),
.ENQ (ENQ),
.DEQ (DEQ),
.FULL_N (FULL_N),
.EMPTY_N(EMPTY_N),
.D_IN (D_IN),
.D_OUT (D_OUT)
);
endmodule
| 7.566086 |
module arithmetic_no_div (
input [7:0] a0,
a1,
output [7:0] sum,
output [7:0] min,
output [7:0] mul
//,output[7:0] div
//output[7:0] mod
//output[7:0] pow
);
//Load other module(s)
//Definition for Variables in the module
//Logical
assign sum = a0 + a1;
assign min = a0 - a1;
assign mul = a0 * a1;
//assign div = a0 / a1;
//assign mod = a0 % a1;
//assign pow = a0 ** a1;
endmodule
| 7.008424 |
module artix7_pll (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
, output clkout1_o
, output clkout2_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire clkfbout_buffered_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
wire pll_clkout1_w;
wire pll_clkout1_buffered_w;
wire pll_clkout2_w;
wire pll_clkout2_buffered_w;
// Input buffering
assign clkref_buffered_w = clkref_i;
// Clocking primitive
PLLE2_BASE #(
.BANDWIDTH ("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
.CLKIN1_PERIOD (10.0), // Input clock period in ns resolution
.CLKFBOUT_MULT (8), // VCO=800MHz
// CLKOUTx_DIVIDE: Divide amount for each CLKOUT(1-128)
.CLKOUT0_DIVIDE(8), // CLK0=100MHz
.CLKOUT1_DIVIDE(4), // CLK1=200MHz
.CLKOUT2_DIVIDE(16), // CLK2=50MHz
// CLKOUTx_DUTY_CYCLE: Duty cycle for each CLKOUT
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
// CLKOUTx_PHASE: Phase offset for each CLKOUT
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value (1-56)
.REF_JITTER1 (0.0), // Ref. input jitter in UI (0.000-0.999)
.STARTUP_WAIT ("TRUE") // Delay DONE until PLL Locks ("TRUE"/"FALSE")
) u_pll (
.CLKFBOUT(clkfbout_w),
.CLKOUT0(pll_clkout0_w),
.CLKOUT1(pll_clkout1_w),
.CLKOUT2(pll_clkout2_w),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKIN1(clkref_buffered_w),
.CLKFBIN(clkfbout_buffered_w)
);
BUFH u_clkfb_buf (
.I(clkfbout_w),
.O(clkfbout_buffered_w)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
assign pll_clkout0_buffered_w = pll_clkout0_w;
assign clkout0_o = pll_clkout0_buffered_w;
//-----------------------------------------------------------------
// CLK_OUT1
//-----------------------------------------------------------------
assign pll_clkout1_buffered_w = pll_clkout1_w;
assign clkout1_o = pll_clkout1_buffered_w;
//-----------------------------------------------------------------
// CLK_OUT2
//-----------------------------------------------------------------
assign pll_clkout2_buffered_w = pll_clkout2_w;
assign clkout2_o = pll_clkout2_buffered_w;
endmodule
| 6.840162 |
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx(tx),
.ser_rx(rx),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule
| 7.233807 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [7:0] sw,
output [15:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_jtag_tms;
wire io_uart_txd;
wire io_uart_rxd;
assign io_led = io_gpioA_write[15:0];
assign io_gpioA_read[7:0] = sw;
Murax murax (
.io_asyncReset (0),
.io_mainClk (io_mainClk),
.io_jtag_tck (1'b0),
.io_jtag_tdi (1'b0),
.io_jtag_tms (1'b0),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd (io_uart_txd),
.io_uart_rxd (io_uart_rxd)
);
endmodule
| 8.460384 |
module ArtyA7 (
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
);
wire [31:0] gpio_i, gpio_o, gpio_ot, gpio;
assign gpio = (gpio_ot) ? gpio_o : 32'hZZZZZZZZ;
assign led = gpio[3:0];
fmrv32im_artya7_wrapper u_fmrv32im_artya7_wrapper (
.CLK100MHZ(CLK100MHZ),
.GPIO_ot(gpio_ot),
.UART_rx(uart_txd_in),
.UART_tx(uart_rxd_out),
.gpio_i(gpio_i),
.gpio_o(gpio_o)
);
endmodule
| 6.899416 |
module ArtyA7 (
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
);
wire CLK;
clk_wiz_0 u_clk_wiz_0 (
.clk_in1 (CLK100MHZ),
.clk_out1(CLK)
);
wire [31:0] gpio_i, gpio_o, gpio_ot, gpio;
assign gpio = (gpio_ot) ? gpio_o : 32'hZZZZZZZZ;
assign led = gpio[3:0];
fmrv32im_artya7_wrapper u_fmrv32im_artya7_wrapper (
.CLK100MHZ(CLK100MHZ),
.GPIO_ot(gpio_ot),
.UART_rx(uart_txd_in),
.UART_tx(uart_rxd_out),
.gpio_i(gpio_i),
.gpio_o(gpio_o)
);
endmodule
| 6.899416 |
module artyz (
input CLK,
input xRESET_N,
input [9:0] SW,
output [7:0] LED_A, // OUTPORT
output [7:0] LED_B, // PORTID
output [3:0] IOZ
);
wire xRESET_P = ~xRESET_N;
icf3z ICf3z (
.CLK(CLK),
.xINPORT_P(SW[9:2]),
.xRESET_P(xRESET_P),
.xINT0_P(SW[0]),
.xINT1_P(SW[1]),
.xPORTID_P(LED_B),
.xOUTPORT_P(LED_A),
.xWSTROBE_P(IOZ[0]),
.xWSTROBEK_P(IOZ[1]),
.xIOSTROBE_P(IOZ[2]),
.xRSTROBE_P(IOZ[3])
);
endmodule
| 6.786845 |
module arty_a7_clock_gen (
input wire i_clk,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(o_clk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb)
);
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule
| 6.670268 |
module arty_mmcm (
// Clock in ports
input clk_in,
// Clock out ports
output clk_50m,
// Status and control signals
input resetn,
output locked
);
arty_mmcm_clk_wiz inst (
// Clock in ports
.clk_in (clk_in),
// Clock out ports
.clk_50m(clk_50m),
// Status and control signals
.resetn (resetn),
.locked (locked)
);
endmodule
| 7.586649 |
module arty_mmcm_clk_wiz ( // Clock in ports
input clk_in,
// Clock out ports
output clk_50m,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in_arty_mmcm),
.I(clk_in)
);
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_arty_mmcm;
wire clkfbout_buf_arty_mmcm;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (25.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_arty_mmcm),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_50m_arty_mmcm),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_arty_mmcm),
.CLKIN1 (clk_in_arty_mmcm),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high)
);
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfbout_buf_arty_mmcm),
.I(clkfbout_arty_mmcm)
);
BUFG clkout1_buf (
.O(clk_50m),
.I(clk_50m_arty_mmcm)
);
endmodule
| 8.708173 |
module arty_mmcm (
clk_in,
clk_50m,
resetn,
locked
);
input clk_in;
output clk_50m;
input resetn;
output locked;
wire clk_50m;
(* IBUF_LOW_PWR *)wire clk_in;
wire locked;
wire resetn;
arty_mmcm_arty_mmcm_clk_wiz inst (
.clk_50m(clk_50m),
.clk_in (clk_in),
.locked (locked),
.resetn (resetn)
);
endmodule
| 7.586649 |
module arty_picorv32_wb_soc (
input CLK100MHZ,
output [3:0] led,
input [3:0] sw,
input [3:0] btn,
output uart_rxd_out,
input uart_txd_in
);
wire wb_clk;
wire wb_rst;
plle2_base_wb_clkgen #(
.INPUT_FREQUENCY(100),
.DIVCLK_DIVIDE(5),
.CLKFBOUT_MULT(42),
.WB_DIVIDE(35)
) wb_clkgen (
.sys_clk_pad_i(CLK100MHZ),
.rst_n_pad_i (~btn[0]),
.wb_clk_o(wb_clk),
.wb_rst_o(wb_rst)
);
assign led[0] = wb_rst;
picorv32_wb_soc #(
.BOOTROM_MEMFILE ("nmon_picorv32-wb-soc_24MHz_115200.txt"),
.BOOTROM_MEMDEPTH(1024)
) soc (
.clock(wb_clk),
.reset(wb_rst),
.uart_rx(uart_txd_in),
.uart_tx(uart_rxd_out)
);
endmodule
| 7.178272 |
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx(tx),
.ser_rx(rx),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule
| 7.233807 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [7:0] sw,
output [9:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_jtag_tms;
wire io_uart_txd;
wire io_uart_rxd;
assign io_led = io_gpioA_write[9:0];
assign io_gpioA_read[7:0] = sw;
Murax murax (
.io_asyncReset (0),
.io_mainClk (io_mainClk),
.io_jtag_tck (1'b0),
.io_jtag_tdi (1'b0),
.io_jtag_tms (1'b0),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd (io_uart_txd),
.io_uart_rxd (io_uart_rxd)
);
endmodule
| 8.460384 |
module arty_top (
input xtal_in, // 100MHz
input [3:0] sw,
input [3:0] btn,
output [3:0] led,
// QSPI
output qspi_clk,
output qspi_cs_n,
inout [3:0] qspi_dq,
// JTAG
input tck_i,
input trstn_i,
input tms_i,
input td_i,
output td_o,
// UART
output uart_tx,
input uart_rx
);
// SPI Master
wire spi_master_clk;
wire [3:0] spi_master_oen;
wire [3:0] spi_master_cs_n;
wire [3:0] spi_master_din;
wire [3:0] spi_master_dout;
wire [1:0] spi_master_mode;
wire module_select;
assign qspi_clk = spi_master_clk;
assign qspi_cs_n = spi_master_cs_n[0];
PULLUP qspi_pullup[3:0] (.O(qspi_dq));
IOBUF qspi_iobuf[3:0] (
.IO(qspi_dq),
.O (spi_master_din),
.I (spi_master_dout),
.T (spi_master_oen)
);
// I2C
wire scl_in = 1'b0;
wire scl_out;
wire scl_oen;
wire sda_in = 1'b0;
wire sda_out;
wire sda_oen;
// GPIO
wire [31:0] gpio_in = 32'd0;
wire [31:0] gpio_out;
wire [31:0] gpio_dir;
// UART
wire uart_rts;
wire uart_dtr;
wire uart_cts = 1'b0;
wire uart_dsr = 1'b0;
// Switches
wire fetch_en = sw[3]; // sw[3] : fetech enable, high active
wire reset_n = ~btn[3]; // btn[3] : global hardware reset, low active
// LEDs
assign led[3] = pll_locked; // LED[3]: pll clocked
assign led[2] = uart_tx; // LED[2]: uart tx
assign led[1] = 1'b1;
assign led[0] = 1'bz;
// clk_wiz
wire clk_cpu;
arty_mmcm u_mmcm (
.clk_in1 (xtal_in),
.clk_out1(clk_cpu), // 50MHz
.resetn (reset_n),
.locked (pll_locked)
);
// PULPino SoC
pulpino u_pulpino (
.clk (clk_cpu),
.rst_n(reset_n),
.fetch_enable_i(fetch_en),
.tck_i (tck_i),
.trstn_i(trstn_i),
.tms_i (tms_i),
.tdi_i (td_i),
.tdo_o (td_o),
.spi_clk_i (1'b0),
.spi_cs_i (1'b0),
.spi_mode_o(2'bz),
.spi_sdi0_i(1'b0),
.spi_sdi1_i(1'b0),
.spi_sdi2_i(1'b0),
.spi_sdi3_i(1'b0),
.spi_sdo0_o(1'bz),
.spi_sdo1_o(1'bz),
.spi_sdo2_o(1'bz),
.spi_sdo3_o(1'bz),
.spi_master_clk_o (spi_master_clk),
.spi_master_oen_o (spi_master_oen),
.spi_master_csn0_o(spi_master_cs_n[0]),
.spi_master_csn1_o(spi_master_cs_n[1]),
.spi_master_csn2_o(spi_master_cs_n[2]),
.spi_master_csn3_o(spi_master_cs_n[3]),
.spi_master_mode_o(spi_master_mode),
.spi_master_sdi0_i(spi_master_din[0]),
.spi_master_sdi1_i(spi_master_din[1]),
.spi_master_sdi2_i(spi_master_din[2]),
.spi_master_sdi3_i(spi_master_din[3]),
.spi_master_sdo0_o(spi_master_dout[0]),
.spi_master_sdo1_o(spi_master_dout[1]),
.spi_master_sdo2_o(spi_master_dout[2]),
.spi_master_sdo3_o(spi_master_dout[3]),
.scl_i (scl_in),
.scl_o (scl_out),
.scl_oen_o(scl_oen),
.sda_i (sda_in),
.sda_o (sda_out),
.sda_oen_o(sda_oen),
.gpio_in (gpio_in),
.gpio_out(gpio_out),
.gpio_dir(gpio_dir),
.uart_tx (uart_tx), // output
.uart_rx (uart_rx), // input
.uart_rts(uart_rts), // output
.uart_dtr(uart_dtr), // output
.uart_cts(uart_cts), // input
.uart_dsr(uart_dsr) // input
);
endmodule
| 6.866394 |
module art_fsm #(
// I/O width parameter
parameter fsm_type = 0
) (
//
input Clk,
input Reset,
input i_Mem_Ack,
input i_Art_Req,
output o_serving,
input i_Art_Miss,
input i_I_flag,
input i_R_flag,
input i_X_flag,
input i_U_flag,
input i_P_flag,
input i_ctl_privileged,
input i_wr_op,
output o_Miss_Fault,
output o_Perm_Fault,
output reg o_Mem_Req,
input i_Fault_Ack,
output o_Fault_Strobe
);
//
parameter IdleSt = 3'b001, WaitMemAck = 3'b010, FaultServ = 3'b100;
//
reg [ 2:0] State;
//
// synthesis translate_off
reg [256:0] StateString;
always @(State) begin
case (State)
IdleSt: StateString = "IdleSt";
WaitMemAck: StateString = "WaitMemAck";
FaultServ: StateString = "FaultServ";
default: StateString = "ERROR";
endcase
end
// synthesis translate_on
wire GotoPermFault;
wire MemAck = i_Mem_Ack;
wire ArtReq = i_Art_Req;
//
// FSM
//
wire GotoFault = GotoPermFault | i_Art_Miss;
//
always @(posedge Clk) begin
if (Reset) State <= #`dh IdleSt;
else begin
case (State)
//
IdleSt: begin
if (ArtReq) begin
if (GotoFault) State <= #`dh FaultServ;
else State <= #`dh WaitMemAck;
end else State <= #`dh IdleSt;
end
//
WaitMemAck: begin
if (MemAck) State <= #`dh IdleSt;
else State <= #`dh WaitMemAck;
end
//
FaultServ: begin
if (i_Fault_Ack) State <= #`dh IdleSt;
else State <= #`dh FaultServ;
end
//
default: State <= #`dh IdleSt;
//
endcase
end
end
//
assign GotoPermFault = fsm_type ?
// fsm_type = 1: D-type
((i_wr_op & i_R_flag) | // Write operation, but read-only region
(i_ctl_privileged & ~i_P_flag) | // Privileged mode, but region non-privileged accessible
(~i_ctl_privileged & ~i_U_flag) // User mode, but region non-user accessible
) :
// fsm_type = 0: I-type
(~i_X_flag | // Region is non-executable
(i_ctl_privileged & ~i_P_flag) | // Privileged mode, but region non-privileged accessible
(~i_ctl_privileged & ~i_U_flag) | // User mode, but region non-user accessible
i_I_flag // Register accesses not permitted from i-side
);
//
always @(posedge Clk) begin
if (Reset) o_Mem_Req <= #`dh 1'b0;
else if ((State == IdleSt) & ArtReq & ~GotoFault) o_Mem_Req <= #`dh 1'b1;
else if (MemAck) o_Mem_Req <= #`dh 1'b0;
end
//
assign o_Perm_Fault = (State == IdleSt) & ArtReq & GotoPermFault & ~i_Art_Miss;
assign o_Miss_Fault = (State == IdleSt) & ArtReq & i_Art_Miss;
assign o_Fault_Strobe = (State == FaultServ) & i_Fault_Ack;
assign o_serving = (State == IdleSt) & ArtReq;
//
endmodule
| 10.719458 |
module from WCI-Slave to AXI4-Lite Master
// Copyright (c) 2010 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// 2010-09-12 Module declaration in Verilog
// 2010-09-14 20b, 1MB Address Window on both sides of bridge
// 2011-01-15 Switch to 32b 4GB address
module arWCI2A4LM (
input bridge_Clk,
input bridge_Reset_n,
input [2:0] wciS0_MCmd, // WCI Slave...
input [0:0] wciS0_MAddrSpace, // MAddrSpace[0]: 0=Control ; 1=Configuration
input [3:0] wciS0_MByteEn,
input [31:0] wciS0_MAddr, // 32b 4GB Address Space
input [31:0] wciS0_MData,
output [1:0] wciS0_SResp,
output [31:0] wciS0_SData,
output [0:0] wciS0_SThreadBusy,
output [0:0] wciS0_SFlag,
input [0:0] wciS0_MFlag,
output axiM0_AWVALID, // AXI4-Lite Write-Address channel...
input axiM0_AWREADY,
output [31:0] axiM0_AWADDR, // 32b 4GB Address Space
output [2:0] axiM0_AWPROT,
output axiM0_WVALID, // AXI4-Lite Write-Data channel...
input axiM0_WREADY,
output [31:0] axiM0_WDATA,
output [3:0] axiM0_WSTRB,
input axiM0_BVALID, // AXI4-Lite Write-Response channel...
output axiM0_BREADY,
input [1:0] axiM0_BRESP,
output axiM0_ARVALID, // AXI4-Lite Read-Address channel...
input axiM0_ARREADY,
output [31:0] axiM0_ARADDR, // 32b 4GB Address Space
output [2:0] axiM0_ARPROT, // ARPROT[2]: 0=Data/Configuration ; 1=Instruction/Control
input axiM0_RVALID, // AXI4-Lite Read-Data channel...
output axiM0_RREADY,
input [31:0] axiM0_RDATA,
input [1:0] axiM0_RRESP
);
wire[34:0] axiM0_wrAddr_data = {axiM0_AWPROT, axiM0_AWADDR};
wire[35:0] axiM0_wrData_data = {axiM0_WSTRB, axiM0_WDATA};
wire[1:0] axiM0_wrResp_data_value = {axiM0_BRESP};
wire[34:0] axiM0_rdAddr_data = {axiM0_ARPROT, axiM0_ARADDR};
wire[33:0] axiM0_rdResp_data_value = {axiM0_RRESP, axiM0_RDATA};
// Instance the BSV module...
mkWCI2A4LM bridge(
.wciS0_Clk (bridge_Clk),
.wciS0_MReset_n (bridge_Reset_n),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MAddrSpace (wciS0_AddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MData (wciS0_MData),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wciS0_MFlag (wciS0_MFlag),
.axiM0_wrAddr_data (axiM0_wrAddr_data),
.axiM0_wrAddr_valid (axiM0_AWVALID),
.axiM0_wrAddr_ready_value (axiM0_AWREADY),
.axiM0_wrData_data (axiM0_wrData_data),
.axiM0_wrData_valid (axiM0_WVALID),
.axiM0_wrData_ready_value (axiM0_WREADY),
.axiM0_wrResp_data_value (axiM0_wrResp_data_value),
.axiM0_wrResp_valid_value (axiM0_BVALID),
.axiM0_wrResp_ready (axiM0_BREADY),
.axiM0_rdAddr_data (axiM0_rdAddr_data),
.axiM0_rdAddr_valid (axiM0_ARVALID),
.axiM0_rdAddr_ready_value (axiM0_ARREADY),
.axiM0_rdResp_data_value (axiM0_rdResp_data_value),
.axiM0_rdResp_valid_value (axiM0_RVALID),
.axiM0_rdResp_ready (axiM0_RREADY)
);
endmodule
| 8.718231 |
module aRx (
clk,
rst,
iRx,
oAction,
oDataOut,
oDataReady,
oByteCnt,
oCrcErr
);
//----- PARAMETERS ----------------------
parameter FCLK = 50000; // [kHz] System clock frequency, max freq = 80000 kHz
parameter BRATE = 115200; // [baud] Baudrate, min brate = 9600 baud
parameter WAIT_TIME = 50; // [us] Data waiting time before reset
parameter BUF_WIDTH = 8; // Buffer size Width, Size = 2**BUF_WIDTH
parameter CRC_ENA = 1; // Enable crc calculation
parameter CRC_POLY = 16'hA001; // Modbus standart crc polynom
//----- PINOUT ---------------------------
input clk;
input rst;
input iRx;
output oAction;
output [7:0] oDataOut;
output reg oDataReady = 0;
output reg [BUF_WIDTH-1:0] oByteCnt = 0;
output reg oCrcErr = 0;
//----- VARIABLES -----------------------
reg [2:0] state = 0;
reg [2:0] next_state = 0;
wire byteCntRst;
reg [9:0] shdata = {10'h3FF};
reg [7:0] previousByte = 8'hFF;
reg [23:0] cnt = 0;
reg [3:0] bcnt = 0;
reg rxd = 0;
reg rxd_i = 0;
reg action = 0;
reg action_i = 0;
reg [15:0] crc = 16'hFFFF;
reg [15:0] crcOut = 16'hFFFF;
//----- Connections -----
assign oDataOut = shdata[8:1];
assign oAction = action | action_i;
always @(negedge clk) begin
action_i <= action;
end
//----- Synchronize ------
always @(posedge clk) begin
rxd_i <= iRx;
rxd <= rxd_i;
end
//----- CRC error latch -----
generate
if (CRC_ENA) begin : crcerr_on
always @(posedge rst or negedge action) begin
if (rst) oCrcErr <= 0;
else oCrcErr <= (crcOut != {shdata[8:1], previousByte});
end
end else begin : crcerr_off
always @* begin
oCrcErr <= ~(&crcOut & &crc & &previousByte);
end
end
endgenerate
//----- Byte counter -----
assign byteCntRst = ~action & (state == 3);
always @(posedge rst or posedge byteCntRst or negedge oDataReady) begin
if (rst) oByteCnt <= 0;
else if (byteCntRst) oByteCnt <= 0;
else oByteCnt <= oByteCnt + 1'b1;
end
//----- FSM -----
always @(posedge rst or posedge clk) begin
if (rst) state <= 0;
else state <= next_state;
end
always @(*) begin
case (state)
0: begin
next_state = 1;
end
1: begin
if (cnt > (FCLK * WAIT_TIME / 1000)) next_state = 0;
else if (!rxd) next_state = 2;
else next_state = 1;
end
2: begin
next_state = 3;
end
3: begin
if (rxd) next_state = 1;
else if (cnt >= (FCLK * 500 / BRATE)) next_state = 4;
else next_state = 3;
end
4: begin
next_state = 5;
end
5: begin
if (bcnt > 9) next_state = 7;
else next_state = 6;
end
6: begin
if (cnt >= (FCLK * 1000 / BRATE)) next_state = 5;
else next_state = 6;
end
7: begin
next_state = 1;
end
default: next_state = 0;
endcase
end
//----- State handler -----
always @(negedge clk) begin
case (state)
0: begin
oDataReady <= 0;
cnt <= 0;
action <= 0;
if (CRC_ENA) crc <= 16'hFFFF;
end
1: begin
if (action) cnt <= cnt + 1'b1;
oDataReady <= 0;
end
2: begin
cnt <= 0;
end
3: begin
cnt <= cnt + 1'b1;
end
4: begin
if (CRC_ENA) begin
if (oByteCnt > 0) crc <= crc ^ {8'b0, shdata[8:1]};
previousByte <= shdata[8:1];
crcOut <= crc;
end
end
5: begin
action <= 1'b1;
cnt <= 0;
bcnt <= bcnt + 1'b1;
shdata[9] <= rxd;
shdata[8:0] <= shdata[9:1];
if (CRC_ENA) begin
if ((oByteCnt > 0) && !bcnt[3])
crc <= crc[0] ? {1'b0, crc[15:1]} ^ CRC_POLY : {1'b0, crc[15:1]};
end
end
6: begin
cnt <= cnt + 1'b1;
end
7: begin
cnt <= 0;
bcnt <= 0;
if (!oByteCnt[BUF_WIDTH-1]) oDataReady <= 1'b1;
end
endcase
end
endmodule
| 8.82391 |
module ARY_MS_DRNG (
port_a,
port_b,
port_c
);
input [3:0] port_a;
input [0:3] port_b;
output [3:0] port_c;
assign port_c = port_a & port_b;
endmodule
| 6.955818 |
module ARY_NR_LBND (
in_a,
in_b,
out_a
);
input [1:0] in_a, in_b;
output [4:1] out_a;
assign out_a = {in_a, in_b};
endmodule
| 7.41692 |
module ARY_NR_LOPR (
x,
a,
b
);
output x;
input [1:0] a, b;
reg y, z;
assign x = !{y, z};
always @(a or b) begin
y = a && 2'b10;
z = 2 || b;
end
endmodule
| 7.080637 |
module AR_Control (
LD,
CLR,
INR,
T,
D,
R,
I
);
input R, I;
input [7:0] T, D;
output LD, CLR, INR;
wire D7n, Rn;
wire a1, a2, a3;
assign D7n = ~D[7];
assign Rn = ~R;
assign a1 = D7n & I & T[3];
assign a2 = T[2] & Rn;
assign a3 = Rn & T[0];
assign CLR = T[0] & R;
assign INR = D[5] & T[4];
assign LD = a1 | a2 | a3;
endmodule
| 6.562652 |
module AR_MUX (
input [7:0] ADR_TX,
input [22:0] DAT_TX,
input [7:0] ADR_RX,
input [22:0] DAT_RX,
input [1:0] S,
output wire [15:0] DISPL
);
wire [15:0] d0 = {ADR_TX, ADR_RX};
wire [15:0] d1 = {1'b0, DAT_TX[22:16], 1'b0, DAT_RX[22:16]};
wire [15:0] d2 = {DAT_TX[15:8], DAT_RX[15:8]};
wire [15:0] d3 = {DAT_TX[7:0], DAT_RX[7:0]};
assign DISPL = (S == 0) ? d0 : (S == 1) ? d1 : (S == 2) ? d2 : d3;
endmodule
| 6.849001 |
module ar_mux_2to1 (
input areset,
// master 1
input [31:0] araddr_m1,
input [ 3:0] arid_m1,
input [ 1:0] arburst_m1,
input [ 3:0] arlen_m1,
input [ 2:0] arsize_m1,
input [ 1:0] arlock_m1,
input [ 3:0] arcache_m1,
input [ 2:0] arprot_m1,
input arvalid_m1,
output arready_m1,
// master 2
input [31:0] araddr_m2,
input [ 3:0] arid_m2,
input [ 1:0] arburst_m2,
input [ 3:0] arlen_m2,
input [ 2:0] arsize_m2,
input [ 1:0] arlock_m2,
input [ 3:0] arcache_m2,
input [ 2:0] arprot_m2,
input arvalid_m2,
output arready_m2,
// slave
output [31:0] araddr_s,
output [ 3:0] arid_s,
output [ 1:0] arburst_s,
output [ 3:0] arlen_s,
output [ 2:0] arsize_s,
output [ 1:0] arlock_s,
output [ 3:0] arcache_s,
output [ 2:0] arprot_s,
output arvalid_s,
input arready_s
);
// AR mux
assign araddr_s = arvalid_m1 ? araddr_m1 : araddr_m2;
assign arid_s = arvalid_m1 ? arid_m1 : arid_m2;
assign arlen_s = arvalid_m1 ? arlen_m1 : arlen_m2;
assign arsize_s = arvalid_m1 ? arsize_m1 : arsize_m2;
assign arburst_s = arvalid_m1 ? arburst_m1 : arburst_m2;
assign arlock_s = arvalid_m1 ? arlock_m1 : arlock_m2;
assign arcache_s = arvalid_m1 ? arcache_m1 : arcache_m2;
assign arprot_s = arvalid_m1 ? arprot_m1 : arprot_m2;
assign arvalid_s = arvalid_m1 ? arvalid_m1 : arvalid_m2 ? arvalid_m2 : 1'b0;
assign arready_m1 = arvalid_m1 ? arready_s : arvalid_m2 ? 1'b0 : 1'b0;
assign arready_m2 = arvalid_m1 ? 1'b0 : arvalid_m2 ? arready_s : 1'b0;
endmodule
| 6.940971 |
module AR_register (
BIN,
clk,
WR,
DMADDR
);
/*
Control signals:
clk - Clock signal
WR - Control signal to write to the register
Data paths:
DMADDR - Wire that carries the data memory address from AR to data memory
BIN - The BUS to write to the register
*/
input [15:0] BIN;
input clk;
input WR;
output [15:0] DMADDR;
reg unsigned [15:0] register;
assign DMADDR = register;
always @(posedge clk) begin
if (WR == 1) register <= BIN;
end
endmodule
| 6.823568 |
module as (
input [7:0] in_wave,
input [1:0] amp,
output reg [7:0] out_wave
);
always @(in_wave, amp) begin
out_wave = 0;
case (amp)
2'b00: out_wave = in_wave;
2'b01: out_wave = {{1{in_wave[7]}}, in_wave[7:1]};
2'b10: out_wave = {{2{in_wave[7]}}, in_wave[7:2]};
2'b11: out_wave = {{3{in_wave[7]}}, in_wave[7:3]};
endcase
end
endmodule
| 7.238699 |
module HB1xp67_ASAP7_75t_SL (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
endmodule
| 7.235152 |
module FAx1_ASAP7_75t_SL (
CON,
SN,
A,
B,
CI
);
output CON, SN;
input A, B, CI;
// Function
wire A__bar, B__bar, CI__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire int_fwire_6;
not (CI__bar, CI);
not (B__bar, B);
and (int_fwire_0, B__bar, CI__bar);
not (A__bar, A);
and (int_fwire_1, A__bar, CI__bar);
and (int_fwire_2, A__bar, B__bar);
or (CON, int_fwire_2, int_fwire_1, int_fwire_0);
and (int_fwire_3, A__bar, B__bar, CI__bar);
and (int_fwire_4, A__bar, B, CI);
and (int_fwire_5, A, B__bar, CI);
and (int_fwire_6, A, B, CI__bar);
or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
endmodule
| 7.381443 |
module HAxp5_ASAP7_75t_SL (
CON,
SN,
A,
B
);
output CON, SN;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
or (CON, A__bar, B__bar);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (SN, int_fwire_1, int_fwire_0);
endmodule
| 7.893692 |
module ICGx3_ASAP7_75t_R (
GCLK,
ENA,
SE,
CLK
);
output GCLK;
input ENA, SE, CLK;
reg notifier;
wire delayed_ENA, delayed_SE, delayed_CLK;
// Function
wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
not (int_fwire_clk, delayed_CLK);
or (int_fwire_test, delayed_ENA, delayed_SE);
altos_latch(
int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test
);
and (GCLK, delayed_CLK, int_fwire_IQ);
// Timing
// Additional timing wires
wire adacond0, adacond1, ENA__bar;
wire int_twire_0, SE__bar;
// Additional timing gates
not (ENA__bar, ENA);
and (int_twire_0, ENA__bar, SE);
or (adacond0, ENA, int_twire_0);
not (SE__bar, SE);
and (adacond1, ENA__bar, SE__bar);
specify
if ((ENA) | (~ENA & SE)) (negedge CLK => (GCLK +: 1'b0)) = 0;
if ((~ENA & ~SE)) (negedge CLK => (GCLK +: 1'b0)) = 0;
ifnone (CLK => GCLK) = 0;
$setuphold (posedge CLK &&& ~SE, posedge ENA &&& ~SE, 0, 0, notifier,,, delayed_CLK, delayed_ENA);
$setuphold (posedge CLK &&& ~SE, negedge ENA &&& ~SE, 0, 0, notifier,,, delayed_CLK, delayed_ENA);
$setuphold(posedge CLK, posedge ENA, 0, 0, notifier,,, delayed_CLK, delayed_ENA);
$setuphold(posedge CLK, negedge ENA, 0, 0, notifier,,, delayed_CLK, delayed_ENA);
$setuphold (posedge CLK &&& ~ENA, posedge SE &&& ~ENA, 0, 0, notifier,,, delayed_CLK, delayed_SE);
$setuphold (posedge CLK &&& ~ENA, negedge SE &&& ~ENA, 0, 0, notifier,,, delayed_CLK, delayed_SE);
$setuphold(posedge CLK, posedge SE, 0, 0, notifier,,, delayed_CLK, delayed_SE);
$setuphold(posedge CLK, negedge SE, 0, 0, notifier,,, delayed_CLK, delayed_SE);
$width(posedge CLK &&& adacond0, 0, 0, notifier);
$width(negedge CLK &&& adacond0, 0, 0, notifier);
$width(negedge CLK &&& adacond1, 0, 0, notifier);
endspecify
endmodule
| 6.911855 |
module AND2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.219768 |
module AND2x4_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.809886 |
module AND2x6_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.841012 |
module AND3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.847744 |
module AND3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.03983 |
module AND3x4_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
and (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.71006 |
module AND4x1_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
and (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.34864 |
module AND4x2_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
and (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.620849 |
module AND5x1_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
and (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.496571 |
module AND5x2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
and (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.848884 |
module FAx1_ASAP7_75t_R (
CON,
SN,
A,
B,
CI
);
output CON, SN;
input A, B, CI;
// Function
wire A__bar, B__bar, CI__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire int_fwire_6;
not (CI__bar, CI);
not (B__bar, B);
and (int_fwire_0, B__bar, CI__bar);
not (A__bar, A);
and (int_fwire_1, A__bar, CI__bar);
and (int_fwire_2, A__bar, B__bar);
or (CON, int_fwire_2, int_fwire_1, int_fwire_0);
and (int_fwire_3, A__bar, B__bar, CI__bar);
and (int_fwire_4, A__bar, B, CI);
and (int_fwire_5, A, B__bar, CI);
and (int_fwire_6, A, B, CI__bar);
or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
// Timing
specify
if ((B & ~CI)) (A => CON) = 0;
if ((~B & CI)) (A => CON) = 0;
ifnone (A => CON) = 0;
if ((A & ~CI)) (B => CON) = 0;
if ((~A & CI)) (B => CON) = 0;
ifnone (B => CON) = 0;
if ((A & ~B)) (CI => CON) = 0;
if ((~A & B)) (CI => CON) = 0;
ifnone (CI => CON) = 0;
if ((B & ~CI)) (A => SN) = 0;
if ((~B & CI)) (A => SN) = 0;
ifnone (A => SN) = 0;
if ((B & CI)) (A => SN) = 0;
if ((~B & ~CI)) (A => SN) = 0;
if ((A & ~CI)) (B => SN) = 0;
if ((~A & CI)) (B => SN) = 0;
ifnone (B => SN) = 0;
if ((A & CI)) (B => SN) = 0;
if ((~A & ~CI)) (B => SN) = 0;
if ((A & ~B)) (CI => SN) = 0;
if ((~A & B)) (CI => SN) = 0;
ifnone (CI => SN) = 0;
if ((A & B)) (CI => SN) = 0;
if ((~A & ~B)) (CI => SN) = 0;
endspecify
endmodule
| 7.381443 |
module HAxp5_ASAP7_75t_R (
CON,
SN,
A,
B
);
output CON, SN;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
or (CON, A__bar, B__bar);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (SN, int_fwire_1, int_fwire_0);
// Timing
specify
(A => CON) = 0;
(B => CON) = 0;
if (B) (A => SN) = 0;
if (~B) (A => SN) = 0;
if (A) (B => SN) = 0;
if (~A) (B => SN) = 0;
endspecify
endmodule
| 7.893692 |
module MAJIxp5_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
wire int_fwire_0, int_fwire_1, int_fwire_2;
not (C__bar, C);
not (B__bar, B);
and (int_fwire_0, B__bar, C__bar);
not (A__bar, A);
and (int_fwire_1, A__bar, C__bar);
and (int_fwire_2, A__bar, B__bar);
or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
// Timing
specify
if ((B & ~C)) (A => Y) = 0;
if ((~B & C)) (A => Y) = 0;
ifnone (A => Y) = 0;
if ((A & ~C)) (B => Y) = 0;
if ((~A & C)) (B => Y) = 0;
ifnone (B => Y) = 0;
if ((A & ~B)) (C => Y) = 0;
if ((~A & B)) (C => Y) = 0;
ifnone (C => Y) = 0;
endspecify
endmodule
| 7.399805 |
module MAJx2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
and (int_fwire_0, B, C);
and (int_fwire_1, A, C);
and (int_fwire_2, A, B);
or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
// Timing
specify
if ((B & ~C)) (A => Y) = 0;
if ((~B & C)) (A => Y) = 0;
ifnone (A => Y) = 0;
if ((A & ~C)) (B => Y) = 0;
if ((~A & C)) (B => Y) = 0;
ifnone (B => Y) = 0;
if ((A & ~B)) (C => Y) = 0;
if ((~A & B)) (C => Y) = 0;
ifnone (C => Y) = 0;
endspecify
endmodule
| 7.060583 |
module MAJx3_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
and (int_fwire_0, B, C);
and (int_fwire_1, A, C);
and (int_fwire_2, A, B);
or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
// Timing
specify
if ((B & ~C)) (A => Y) = 0;
if ((~B & C)) (A => Y) = 0;
ifnone (A => Y) = 0;
if ((A & ~C)) (B => Y) = 0;
if ((~A & C)) (B => Y) = 0;
ifnone (B => Y) = 0;
if ((A & ~B)) (C => Y) = 0;
if ((~A & B)) (C => Y) = 0;
ifnone (C => Y) = 0;
endspecify
endmodule
| 7.136546 |
module NAND2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.621557 |
module NAND2x1p5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.126562 |
module NAND2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.852236 |
module NAND2xp33_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.347385 |
module NAND2xp5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.236259 |
module NAND2xp67_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.14241 |
module NAND3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.545869 |
module NAND3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.802598 |
module NAND3xp33_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.178327 |
module NAND4xp25_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 8.037681 |
module NAND4xp75_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.910677 |
module NAND5xp2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar, E__bar;
not (E__bar, E);
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
or (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 8.238079 |
module NOR2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.379351 |
module NOR2x1p5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.859676 |
module NOR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.69965 |
module NOR2xp33_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 8.186936 |
module NOR2xp67_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar;
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.981423 |
module NOR3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.668731 |
module NOR3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.916058 |
module NOR3xp33_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
wire A__bar, B__bar, C__bar;
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 8.282953 |
module NOR4xp25_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.712023 |
module NOR4xp75_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar;
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.650467 |
module NOR5xp2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
wire A__bar, B__bar, C__bar;
wire D__bar, E__bar;
not (E__bar, E);
not (D__bar, D);
not (C__bar, C);
not (B__bar, B);
not (A__bar, A);
and (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 8.163665 |
module OR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.857343 |
module OR2x4_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.360341 |
module OR2x6_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 7.502604 |
module OR3x1_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.436237 |
module OR3x2_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.574449 |
module OR3x4_ASAP7_75t_R (
Y,
A,
B,
C
);
output Y;
input A, B, C;
// Function
or (Y, A, B, C);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
endspecify
endmodule
| 7.479961 |
module OR4x2_ASAP7_75t_R (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
// Function
or (Y, A, B, C, D);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
endspecify
endmodule
| 7.22738 |
module OR5x1_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
or (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.243287 |
module OR5x2_ASAP7_75t_R (
Y,
A,
B,
C,
D,
E
);
output Y;
input A, B, C, D, E;
// Function
or (Y, A, B, C, D, E);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(D => Y) = 0;
(E => Y) = 0;
endspecify
endmodule
| 7.40716 |
module TIEHIx1_ASAP7_75t_R (
H
);
output H;
// Function
buf (H, 1'b1);
// Timing
specify
endspecify
endmodule
| 7.028828 |
module XNOR2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (B) (A => Y) = 0;
if (~B) (A => Y) = 0;
if (A) (B => Y) = 0;
if (~A) (B => Y) = 0;
endspecify
endmodule
| 7.503261 |
module XNOR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (B) (A => Y) = 0;
if (~B) (A => Y) = 0;
if (A) (B => Y) = 0;
if (~A) (B => Y) = 0;
endspecify
endmodule
| 7.576248 |
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