code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add_full_648 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1296 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1295 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.86966 |
module Add_full_649 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1298 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1297 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.803594 |
module Add_full_650 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1300 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1299 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.709223 |
module Add_full_651 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1302 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1301 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.77779 |
module Add_full_652 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1304 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1303 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.711028 |
module Add_full_653 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1306 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1305 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.403901 |
module Add_full_654 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1308 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1307 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.651679 |
module Add_full_655 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1310 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1309 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.14565 |
module Add_full_656 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1312 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1311 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.500263 |
module Add_full_657 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1314 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1313 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.760878 |
module Add_full_658 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1316 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1315 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.405943 |
module Add_full_659 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1318 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1317 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.212063 |
module Add_full_660 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1320 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1319 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.484111 |
module Add_full_661 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1322 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1321 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.687411 |
module Add_full_662 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1324 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1323 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.824928 |
module Add_full_663 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1326 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1325 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.336248 |
module Add_full_664 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1328 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1327 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.928611 |
module Add_full_665 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1330 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1329 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.897662 |
module Add_full_666 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1332 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1331 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.425562 |
module Add_full_667 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1334 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1333 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.68905 |
module Add_full_668 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1336 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1335 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.709531 |
module Add_full_669 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1338 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1337 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.580983 |
module Add_full_670 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1340 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1339 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.733691 |
module Add_full_671 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1342 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1341 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.837523 |
module Add_full_672 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1344 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1343 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.837926 |
module Add_full_673 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1346 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1345 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.386918 |
module Add_full_674 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1348 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1347 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.313358 |
module Add_full_675 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1350 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1349 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.90786 |
module Add_full_676 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1352 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1351 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.741487 |
module Add_full_677 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1354 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1353 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.544182 |
module Add_full_678 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1356 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1355 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.629071 |
module Add_full_679 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1358 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1357 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.644852 |
module Add_full_680 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1360 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1359 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.672541 |
module Add_full_681 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1362 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1361 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.693709 |
module Add_full_682 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1364 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1363 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.935799 |
module Add_full_685 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1370 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1369 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.727294 |
module Add_full_686 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1372 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1371 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.865758 |
module Add_full_689 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1378 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1377 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.848932 |
module Add_full_690 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1380 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1379 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.134711 |
module Add_full_691 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1382 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1381 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.602181 |
module Add_full_692 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1384 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1383 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.065903 |
module Add_full_693 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1386 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1385 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.937923 |
module Add_full_694 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1388 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1387 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.181248 |
module Add_full_695 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1390 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1389 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.849806 |
module Add_full_696 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1392 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1391 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.730634 |
module Add_full_697 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1394 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1393 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.716969 |
module Add_full_698 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1396 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1395 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.76328 |
module Add_full_701 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1402 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1401 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.381448 |
module Add_full_702 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1404 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1403 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.543149 |
module Add_full_705 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1410 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1409 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.520491 |
module Add_full_706 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1412 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1411 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.934894 |
module Add_full_709 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1418 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1417 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.561906 |
module Add_full_710 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1420 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1419 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.834328 |
module Add_full_713 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1426 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1425 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.840474 |
module Add_full_714 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1428 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1427 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.263485 |
module Add_full_717 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1434 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1433 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.906274 |
module Add_full_718 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1436 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1435 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.64387 |
module Add_full_721 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1442 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1441 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.431379 |
module Add_full_722 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1444 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1443 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.499405 |
module Add_full_725 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1450 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1449 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.272825 |
module Add_full_726 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1452 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1451 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.733875 |
module Add_full_730 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1460 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1459 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.45946 |
module Add_full_732 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1464 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1463 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.215543 |
module Add_full_733 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1466 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1465 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.918162 |
module Add_full_734 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1468 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1467 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.00599 |
module Add_full_737 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1474 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1473 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.997208 |
module Add_full_738 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1476 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1475 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.545488 |
module Add_full_741 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1482 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1481 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.977409 |
module Add_full_742 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1484 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1483 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.703744 |
module Add_full_745 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1490 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1489 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.731942 |
module Add_full_746 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1492 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1491 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.920734 |
module Add_full_747 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1494 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1493 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.941248 |
module Add_full_748 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1496 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1495 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.107967 |
module Add_full_749 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1498 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1497 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.909137 |
module Add_full_750 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1500 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1499 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.696231 |
module Add_full_751 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1502 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1501 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.765349 |
module Add_full_752 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1504 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1503 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.948182 |
module Add_full_753 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1506 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1505 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.750871 |
module Add_full_757 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1514 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1513 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.735808 |
module Add_full_758 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1516 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1515 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.803357 |
module Add_full_761 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1522 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1521 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.744487 |
module Add_full_762 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1524 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1523 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.799129 |
module Add_full_763 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1526 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1525 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.745489 |
module Add_full_764 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1528 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1527 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 8.16004 |
module Add_full_765 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1530 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1529 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.848936 |
module Add_full_766 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1532 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1531 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.69472 |
module Add_full_767 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1534 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1533 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.89324 |
module Add_full_768 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1536 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1535 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
... | 7.512943 |
module bit16_6 (
a16,
b16,
sum16,
c_out16,
c_in16
);
input [15:0] a16;
input [15:0] b16;
output [15:0] sum16;
input c_in16;
output c_out16;
wire c1;
bit8_12 A161 (
.sum8(sum16[7:0]),
.c_out8(c1),
.a8(a16[7:0]),
.b8(b16[7:0]),
.c_in8(c_in16)
);
bit8_11... | 6.813191 |
module Array_Shift (
input wire CLK,
input wire RST_N,
input wire shift_start,
output reg read_en,
output reg [ 31:0] read_addr,
input wire signed [`DATA_WIDTH-1:0] m1,
input wire [`DATA_WIDTH-1:0] m_temp,
output wire ... | 8.515749 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module array_top #(
parameter COL_WIDTH = 13,
parameter ARRAY_SIZE = 8
) (
input clk,
input [(ARRAY_SIZE*ARRAY_SIZE)-1:0][7:0] weights,
input [ARRAY_SIZE-1:0][7:0] inputs,
input [3:0] in_width,
input [3:0] weight_width,
input s_in,
input s_weight,
output reg [ARRAY_SIZE-1:0][... | 7.06647 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module Arreglo_2DMesh (
input RST, // Reset maestro
input CLK, // Reloj maestro
input [3:0] A00,
A10, // Coef Matriz A
input [3:0] B00,
B01, // Coef Matriz B
input ENp, // Habilitaciones Rp
input ENq, // Habilitaciones Rp 11
input [3:0] ENa, // Habilitaciones Ra
input [3:... | 6.742206 |
module \$paramod\rca_n\n=32 (
a,
b,
ci,
s,
co
);
input [31:0] a;
input [31:0] b;
wire [32:0] c;
input ci;
output co;
output [31:0] s;
FA \addbit[0].f (
.A(a[0]),
.B(b[0]),
.S(s[0]),
.cin(ci),
.cout(c[1])
);
FA \addbit[10].f (
.A(a[10]),
.B(... | 6.728147 |
module arrMult_nxm (
a,
b,
p
);
parameter n = 32;
parameter m = 32;
input [n-1:0] a;
input [m-1:0] b;
output [n+m-1:0] p;
wire [((n-1)*m)-1:0] s_i;
wire [m-1:0] c;
assign c[0] = 1'd0;
assign p[0] = a[0] & b[0];
assign p[n+m-1] = c[m-1];
wire [(n*(m-1))-1:0] b_rca;
genvar i, j;
gen... | 6.966087 |
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