code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add_full_648 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1296 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1295 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.86966 |
module Add_full_649 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1298 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1297 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.803594 |
module Add_full_650 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1300 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1299 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.709223 |
module Add_full_651 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1302 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1301 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.77779 |
module Add_full_652 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1304 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1303 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.711028 |
module Add_full_653 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1306 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1305 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.403901 |
module Add_full_654 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1308 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1307 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.651679 |
module Add_full_655 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1310 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1309 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.14565 |
module Add_full_656 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1312 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1311 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.500263 |
module Add_full_657 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1314 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1313 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.760878 |
module Add_full_658 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1316 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1315 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.405943 |
module Add_full_659 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1318 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1317 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.212063 |
module Add_full_660 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1320 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1319 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.484111 |
module Add_full_661 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1322 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1321 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.687411 |
module Add_full_662 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1324 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1323 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.824928 |
module Add_full_663 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1326 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1325 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.336248 |
module Add_full_664 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1328 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1327 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.928611 |
module Add_full_665 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1330 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1329 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.897662 |
module Add_full_666 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1332 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1331 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.425562 |
module Add_full_667 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1334 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1333 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.68905 |
module Add_full_668 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1336 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1335 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.709531 |
module Add_full_669 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1338 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1337 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.580983 |
module Add_full_670 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1340 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1339 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.733691 |
module Add_full_671 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1342 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1341 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.837523 |
module Add_full_672 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1344 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1343 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.837926 |
module Add_full_673 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1346 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1345 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.386918 |
module Add_full_674 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1348 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1347 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 8.313358 |
module Add_full_675 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1350 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1349 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.90786 |
module Add_full_676 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1352 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1351 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.741487 |
module Add_full_677 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1354 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1353 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.544182 |
module Add_full_678 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1356 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1355 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.629071 |
module Add_full_679 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1358 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1357 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.644852 |
module Add_full_680 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1360 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1359 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.672541 |
module Add_full_681 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1362 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1361 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.693709 |
module Add_full_682 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1364 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1363 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.935799 |
module Add_full_685 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1370 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1369 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.727294 |
module Add_full_686 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1372 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1371 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.865758 |
module Add_full_689 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1378 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1377 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.848932 |
module Add_full_690 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1380 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1379 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 8.134711 |
module Add_full_691 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1382 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1381 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.602181 |
module Add_full_692 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1384 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1383 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.065903 |
module Add_full_693 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1386 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1385 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.937923 |
module Add_full_694 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1388 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1387 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 8.181248 |
module Add_full_695 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1390 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1389 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.849806 |
module Add_full_696 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1392 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1391 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.730634 |
module Add_full_697 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1394 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1393 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.716969 |
module Add_full_698 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1396 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1395 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.76328 |
module Add_full_701 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1402 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1401 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.381448 |
module Add_full_702 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1404 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1403 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.543149 |
module Add_full_705 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1410 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1409 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.520491 |
module Add_full_706 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1412 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1411 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.934894 |
module Add_full_709 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1418 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1417 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.561906 |
module Add_full_710 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1420 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1419 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.834328 |
module Add_full_713 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1426 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1425 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.840474 |
module Add_full_714 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1428 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1427 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.263485 |
module Add_full_717 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1434 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1433 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.906274 |
module Add_full_718 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1436 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1435 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.64387 |
module Add_full_721 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1442 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1441 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.431379 |
module Add_full_722 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1444 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1443 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.499405 |
module Add_full_725 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1450 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1449 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.272825 |
module Add_full_726 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1452 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1451 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.733875 |
module Add_full_730 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1460 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1459 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.45946 |
module Add_full_732 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1464 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1463 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.215543 |
module Add_full_733 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1466 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1465 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.918162 |
module Add_full_734 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1468 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1467 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.00599 |
module Add_full_737 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1474 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1473 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.997208 |
module Add_full_738 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1476 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1475 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.545488 |
module Add_full_741 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1482 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1481 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.977409 |
module Add_full_742 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1484 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1483 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.703744 |
module Add_full_745 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1490 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1489 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.731942 |
module Add_full_746 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1492 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1491 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.920734 |
module Add_full_747 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1494 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1493 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.941248 |
module Add_full_748 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1496 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1495 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 8.107967 |
module Add_full_749 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1498 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1497 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.909137 |
module Add_full_750 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1500 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1499 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.696231 |
module Add_full_751 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1502 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1501 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.765349 |
module Add_full_752 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1504 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1503 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.948182 |
module Add_full_753 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1506 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1505 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.750871 |
module Add_full_757 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1514 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1513 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.735808 |
module Add_full_758 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1516 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1515 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.803357 |
module Add_full_761 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1522 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1521 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.744487 |
module Add_full_762 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1524 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1523 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.799129 |
module Add_full_763 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1526 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1525 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.745489 |
module Add_full_764 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1528 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1527 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 8.16004 |
module Add_full_765 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1530 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1529 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.848936 |
module Add_full_766 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1532 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1531 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.69472 |
module Add_full_767 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1534 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1533 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.89324 |
module Add_full_768 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_1536 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1535 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.512943 |
module bit16_6 (
a16,
b16,
sum16,
c_out16,
c_in16
);
input [15:0] a16;
input [15:0] b16;
output [15:0] sum16;
input c_in16;
output c_out16;
wire c1;
bit8_12 A161 (
.sum8(sum16[7:0]),
.c_out8(c1),
.a8(a16[7:0]),
.b8(b16[7:0]),
.c_in8(c_in16)
);
bit8_11 A162 (
.sum8(sum16[15:8]),
.c_out8(c_out16),
.a8(a16[15:8]),
.b8(b16[15:8]),
.c_in8(c1)
);
endmodule
| 6.813191 |
module Array_Shift (
input wire CLK,
input wire RST_N,
input wire shift_start,
output reg read_en,
output reg [ 31:0] read_addr,
input wire signed [`DATA_WIDTH-1:0] m1,
input wire [`DATA_WIDTH-1:0] m_temp,
output wire shift_valid,
output reg [ 31:0] shift_addr,
output reg signed [`DATA_WIDTH-1:0] shift_m1,
output reg [`DATA_WIDTH-1:0] shift_m_temp,
output wire shift_ok
);
parameter IDEL = 5'd0;
parameter START_SHIFT = 5'd1;
parameter SHIFT_TEMP = 5'd2;
parameter SHIFT_TEMP1 = 5'd3;
parameter SHIFT_OK = 6'd4;
reg [4:0] state;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
state <= IDEL;
read_en <= 0;
end else begin
case (state)
IDEL: begin
if (shift_start) begin
state <= START_SHIFT;
read_en <= 1;
end
end
START_SHIFT: begin
if (read_addr == `TOTAL_ADDR * 2) begin
state <= SHIFT_TEMP;
read_en <= 0;
end
end
SHIFT_TEMP: begin
state <= SHIFT_TEMP1;
end
SHIFT_TEMP1: begin
state <= SHIFT_OK;
end
SHIFT_OK: begin
state <= IDEL;
end
endcase
end
end
assign shift_ok = state == SHIFT_OK;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
read_addr <= 0;
end else if (read_en) begin
read_addr <= read_addr + 1;
end else begin
read_addr <= 0;
end
end
reg signed [`DATA_WIDTH-1:0] m1_buffer;
reg [`DATA_WIDTH-1:0] m_temp_buffer;
reg read_en_reg, read_en_reg_reg, read_en_reg_reg_reg;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
m1_buffer <= 0;
m_temp_buffer <= 0;
end else begin
m1_buffer <= m1;
m_temp_buffer <= m_temp;
end
end
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
read_en_reg <= 0;
read_en_reg_reg <= 0;
read_en_reg_reg_reg <= 0;
end else begin
read_en_reg <= read_en;
read_en_reg_reg <= read_en_reg;
read_en_reg_reg_reg <= read_en_reg_reg;
end
end
assign shift_valid = read_en_reg_reg_reg;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
shift_addr <= 0;
end else if (shift_valid) begin
shift_addr <= shift_addr + 1;
end else begin
shift_addr <= 0;
end
end
wire signed [`DATA_WIDTH-1:0] shift_temp0 = m1_buffer >>> 1;
wire [`DATA_WIDTH-1:0] shift_temp1 = m_temp_buffer >>> 1;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
shift_m1 <= 0;
shift_m_temp <= 0;
end else if (shift_addr + 1 == `TOTAL_ADDR * 2) begin
shift_m1 <= m1_buffer >>> 1;
shift_m_temp <= shift_temp1;
end else begin
shift_m1 <= {m1[0], shift_temp0[`DATA_WIDTH-2:0]};
shift_m_temp <= {m_temp[0], shift_temp1[`DATA_WIDTH-2:0]};
end
end
endmodule
| 8.515749 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module array_top #(
parameter COL_WIDTH = 13,
parameter ARRAY_SIZE = 8
) (
input clk,
input [(ARRAY_SIZE*ARRAY_SIZE)-1:0][7:0] weights,
input [ARRAY_SIZE-1:0][7:0] inputs,
input [3:0] in_width,
input [3:0] weight_width,
input s_in,
input s_weight,
output reg [ARRAY_SIZE-1:0][(COL_WIDTH*4)-1:0] psum
);
//need to mux inputs??
reg [ARRAY_SIZE-1:0][7:0] in_reg;
reg [(ARRAY_SIZE*ARRAY_SIZE)-1:0][7:0] weight_reg;
reg [(COL_WIDTH*4)-1:0] psum_in_reg;
reg [3:0] in_width_reg;
reg [3:0] weight_width_reg;
reg s_in_reg;
reg s_weight_reg;
wire [ARRAY_SIZE-1:0][(COL_WIDTH*4)-1:0] psum_out;
systolic_array sa0 (
.clk(clk),
.inputs(in_reg),
.weights(weight_reg),
.in_width(in_width_reg),
.weight_width(weight_width_reg),
.s_in(s_in_reg),
.s_weight(s_weight_reg),
.psums(psum_out)
);
always @(posedge clk) begin
in_reg <= inputs;
weight_reg <= weights;
in_width_reg <= in_width;
weight_width_reg <= weight_width;
s_in_reg <= s_in;
s_weight_reg <= s_weight;
psum <= psum_out;
end
endmodule
| 7.06647 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module Arreglo_2DMesh (
input RST, // Reset maestro
input CLK, // Reloj maestro
input [3:0] A00,
A10, // Coef Matriz A
input [3:0] B00,
B01, // Coef Matriz B
input ENp, // Habilitaciones Rp
input ENq, // Habilitaciones Rp 11
input [3:0] ENa, // Habilitaciones Ra
input [3:0] ENr, // Habilitaciones Rr
output [7:0] MTX00,
MTX01, // Salida
output [7:0] MTX10,
MTX11
);
wire [3:0] Ar01, Ar10, Ar11;
wire [3:0] Br01, Br10, Br11;
// Coef OO
MAC MAC00 (
RST,
CLK,
ENa[0],
ENr[0],
A00,
B00,
MTX00
);
// Coef 01
Registro_4b RpA01 (
RST,
CLK,
ENp,
A00,
Ar01
);
Registro_4b RpB01 (
RST,
CLK,
ENp,
B01,
Br01
);
MAC MAC01 (
RST,
CLK,
ENa[1],
ENr[1],
Ar01,
Br01,
MTX01
);
// Coef 10
Registro_4b RpA10 (
RST,
CLK,
ENp,
A10,
Ar10
);
Registro_4b RpB10 (
RST,
CLK,
ENp,
B00,
Br10
);
MAC MAC10 (
RST,
CLK,
ENa[2],
ENr[2],
Ar10,
Br10,
MTX10
);
// Coef 11
Registro_4b RpA11 (
RST,
CLK,
ENq,
Ar10,
Ar11
);
Registro_4b RpB11 (
RST,
CLK,
ENq,
Br01,
Br11
);
MAC MAC11 (
RST,
CLK,
ENa[3],
ENr[3],
Ar11,
Br11,
MTX11
);
endmodule
| 6.742206 |
module \$paramod\rca_n\n=32 (
a,
b,
ci,
s,
co
);
input [31:0] a;
input [31:0] b;
wire [32:0] c;
input ci;
output co;
output [31:0] s;
FA \addbit[0].f (
.A(a[0]),
.B(b[0]),
.S(s[0]),
.cin(ci),
.cout(c[1])
);
FA \addbit[10].f (
.A(a[10]),
.B(b[10]),
.S(s[10]),
.cin(c[10]),
.cout(c[11])
);
FA \addbit[11].f (
.A(a[11]),
.B(b[11]),
.S(s[11]),
.cin(c[11]),
.cout(c[12])
);
FA \addbit[12].f (
.A(a[12]),
.B(b[12]),
.S(s[12]),
.cin(c[12]),
.cout(c[13])
);
FA \addbit[13].f (
.A(a[13]),
.B(b[13]),
.S(s[13]),
.cin(c[13]),
.cout(c[14])
);
FA \addbit[14].f (
.A(a[14]),
.B(b[14]),
.S(s[14]),
.cin(c[14]),
.cout(c[15])
);
FA \addbit[15].f (
.A(a[15]),
.B(b[15]),
.S(s[15]),
.cin(c[15]),
.cout(c[16])
);
FA \addbit[16].f (
.A(a[16]),
.B(b[16]),
.S(s[16]),
.cin(c[16]),
.cout(c[17])
);
FA \addbit[17].f (
.A(a[17]),
.B(b[17]),
.S(s[17]),
.cin(c[17]),
.cout(c[18])
);
FA \addbit[18].f (
.A(a[18]),
.B(b[18]),
.S(s[18]),
.cin(c[18]),
.cout(c[19])
);
FA \addbit[19].f (
.A(a[19]),
.B(b[19]),
.S(s[19]),
.cin(c[19]),
.cout(c[20])
);
FA \addbit[1].f (
.A(a[1]),
.B(b[1]),
.S(s[1]),
.cin(c[1]),
.cout(c[2])
);
FA \addbit[20].f (
.A(a[20]),
.B(b[20]),
.S(s[20]),
.cin(c[20]),
.cout(c[21])
);
FA \addbit[21].f (
.A(a[21]),
.B(b[21]),
.S(s[21]),
.cin(c[21]),
.cout(c[22])
);
FA \addbit[22].f (
.A(a[22]),
.B(b[22]),
.S(s[22]),
.cin(c[22]),
.cout(c[23])
);
FA \addbit[23].f (
.A(a[23]),
.B(b[23]),
.S(s[23]),
.cin(c[23]),
.cout(c[24])
);
FA \addbit[24].f (
.A(a[24]),
.B(b[24]),
.S(s[24]),
.cin(c[24]),
.cout(c[25])
);
FA \addbit[25].f (
.A(a[25]),
.B(b[25]),
.S(s[25]),
.cin(c[25]),
.cout(c[26])
);
FA \addbit[26].f (
.A(a[26]),
.B(b[26]),
.S(s[26]),
.cin(c[26]),
.cout(c[27])
);
FA \addbit[27].f (
.A(a[27]),
.B(b[27]),
.S(s[27]),
.cin(c[27]),
.cout(c[28])
);
FA \addbit[28].f (
.A(a[28]),
.B(b[28]),
.S(s[28]),
.cin(c[28]),
.cout(c[29])
);
FA \addbit[29].f (
.A(a[29]),
.B(b[29]),
.S(s[29]),
.cin(c[29]),
.cout(c[30])
);
FA \addbit[2].f (
.A(a[2]),
.B(b[2]),
.S(s[2]),
.cin(c[2]),
.cout(c[3])
);
FA \addbit[30].f (
.A(a[30]),
.B(b[30]),
.S(s[30]),
.cin(c[30]),
.cout(c[31])
);
FA \addbit[31].f (
.A(a[31]),
.B(b[31]),
.S(s[31]),
.cin(c[31]),
.cout(co)
);
FA \addbit[3].f (
.A(a[3]),
.B(b[3]),
.S(s[3]),
.cin(c[3]),
.cout(c[4])
);
FA \addbit[4].f (
.A(a[4]),
.B(b[4]),
.S(s[4]),
.cin(c[4]),
.cout(c[5])
);
FA \addbit[5].f (
.A(a[5]),
.B(b[5]),
.S(s[5]),
.cin(c[5]),
.cout(c[6])
);
FA \addbit[6].f (
.A(a[6]),
.B(b[6]),
.S(s[6]),
.cin(c[6]),
.cout(c[7])
);
FA \addbit[7].f (
.A(a[7]),
.B(b[7]),
.S(s[7]),
.cin(c[7]),
.cout(c[8])
);
FA \addbit[8].f (
.A(a[8]),
.B(b[8]),
.S(s[8]),
.cin(c[8]),
.cout(c[9])
);
FA \addbit[9].f (
.A(a[9]),
.B(b[9]),
.S(s[9]),
.cin(c[9]),
.cout(c[10])
);
endmodule
| 6.728147 |
module arrMult_nxm (
a,
b,
p
);
parameter n = 32;
parameter m = 32;
input [n-1:0] a;
input [m-1:0] b;
output [n+m-1:0] p;
wire [((n-1)*m)-1:0] s_i;
wire [m-1:0] c;
assign c[0] = 1'd0;
assign p[0] = a[0] & b[0];
assign p[n+m-1] = c[m-1];
wire [(n*(m-1))-1:0] b_rca;
genvar i, j;
generate
for (i = 0; i < n - 1; i = i + 1) begin : addbit
assign s_i[i] = a[i+1] & b[0];
end
for (i = 0; i < m - 1; i = i + 1) begin : addbit2
for (j = 0; j < n; j = j + 1) begin : addbit3
assign b_rca[(i*n)+j] = a[j] & b[i+1];
end
rca_n #(n) rca (
{c[i], s_i[((n-1)*(i+1))-1:i*(n-1)]},
b_rca[((i+1)*n)-1:i*n],
1'b0,
{s_i[((n-1)*(i+2))-1:(i+1)*(n-1)], p[i+1]},
c[i+1]
);
if (i == m - 2) begin
assign p[n+m-2:i+2] = s_i[(m*(n-1))-1:((i+1)*(n-1))];
end
end
endgenerate
endmodule
| 6.966087 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.