code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module //Required to pair up with already used "`module" in file assert_win_unchange.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_unchange_assert (clk, reset_n, start_event, end_event, test_expr, window,
... | 6.783873 |
module //Required to pair up with already used "`module" in file assert_zero_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_zero_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, re... | 6.783873 |
module half_sub (
input ha,
hb,
output hby,
hd
);
assign hd = ha ^ hb;
assign hby = ~(ha) & hb;
endmodule
| 7.195826 |
module full_sub (
input a,
b,
c,
output by,
d
);
wire x, y, z;
half_sub hs1 (
a,
b,
x,
y
);
half_sub hs2 (
y,
c,
z,
d
);
or (by, z, x);
endmodule
| 7.064028 |
module test (
output c
);
wire a;
wire b;
always @(*) begin
a = 0;
b = 0;
c = a + b;
end
endmodule
| 6.644084 |
module ASSIGN1 (
IN,
OUT
);
output OUT;
input IN;
assign OUT = IN;
endmodule
| 6.518691 |
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output sum, carry;
assign sum = a ^ b ^ c;
assign carry = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module flip_flop16 (
d1,
q1,
clk,
reset
);
input [15:0] d1;
input clk, reset;
output [15:0] q1;
reg [15:0] q1;
always @(posedge clk) begin
if (reset == 1'b1) q1 <= 16'b0;
else q1 <= d1;
end
endmodule
| 6.674598 |
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output sum, carry;
assign sum = a ^ b ^ c;
assign carry = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module flip_flop (
d,
q,
clk,
reset
);
input d, clk, reset;
output reg q;
always @(posedge clk) begin
if (reset == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.373981 |
module ripple (
a,
b,
c,
sum,
carry
);
input [15:0] a, b;
output [15:0] sum;
output [15:0] c;
output carry;
full_adder mod0 (
a[0],
b[0],
1'b0,
sum[0],
c[0]
);
full_adder mod1 (
a[1],
b[1],
c[0],
sum[1],
c[1]
);
full_adde... | 6.679037 |
module assignm2_tb;
reg [15:0] a, b;
wire [15:0] sum, c;
wire carry;
wire [17:0] sum_final;
ripple mod16 (
a,
b,
c,
sum,
carry,
sum_final
);
initial begin
$dumpfile("assi.vcd");
$dumpvars(0, assignm2_tb);
a = 16'b1001111011111011;
b = 16'b1111001100011... | 7.074257 |
module assignment (
input [3:0] KEY,
input [6:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output reg [3:0] LEDR
);
wire [31:0] ALU_result;
wire [31:0] PC;
... | 7.31878 |
module assignment1_frame (
input CLOCK_50,
input RESET_N,
input [3:0] KEY,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [9:0] LEDR
);
wire clk;
wire rst;
reg [9:0] red_lights;
reg... | 6.623045 |
module assignment2B (
clk,
rstn,
w,
Q,
c
);
input clk, rstn;
input [1:0] w;
output reg Q;
output reg [1:0] c;
reg [1:0] y, Y;
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
always @(w, y)
case (y)
A:
if (w[1] == 0 && w[0] == 0) begin
Q = 0;
y = A;... | 6.701994 |
module coca (
sw,
c,
o,
a,
x,
show
);
input [2:0] sw, o, c, a, x;
output [2:0] show;
assign show = (sw == 3'b000) ? c : (sw == 3'b001) ? o : (sw == 3'b010) ? a : x;
endmodule
| 7.44236 |
module assignments (
input wire clk,
input wire rst,
output reg [7:0] data_nba,
output reg [7:0] data_ba
);
reg [7:0] nba_buffer;
reg [7:0] ba_buffer;
always @(posedge clk) begin
if (~rst) begin
nba_buffer <= 0;
data_nba <= 0;
end else begin
nba_buffer <= nba_buffer +... | 7.327347 |
module assignments_tb ();
reg clk;
reg rst;
wire [7:0] data_nba;
wire [7:0] data_ba;
assignments uut (
.clk(clk),
.rst(rst),
.data_nba(data_nba),
.data_ba(data_ba)
);
initial begin
rst = 1;
clk = 0;
#200 rst = 0;
#200 rst = 1;
end
always begin
#50 clk <=... | 6.671331 |
module final_sub (
S,
B,
A,
COUT
);
//: interface /sz:(117, 103) /bd:[ Li0>B[7:0](68/103) Li1>A[7:0](34/103) Ro0<S[7:0](68/103) Ro1<COUT(34/103) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1
input [7:0] B; //: /sn:0 {0}(#:603,295)(460,295)(460,295)(450,295){1}
//: {2}(448,293)(448,235)(448,235)(448,163){3}
//... | 6.522966 |
module dec_4to16 (
y4,
y14,
y5,
a,
y11,
y12,
y6,
y13,
y10,
y0,
y2,
y9,
y7,
y8,
y3,
y15,
y1
);
//: interface /sz:(189, 590) /bd:[ Li0>a[3:0](34/590) Ro0<y0(573/590) Ro1<y1(544/590) Ro2<y2(515/590) Ro3<y3(481/590) Ro4<y4(450/590) Ro5<y5(416/590) Ro6<y... | 7.346636 |
module tb ();
reg I0, I1, I2, I3, I4, I5, I6, I7, I8;
wire Y;
cf dut (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
Y
);
initial begin
$monitor("@time %3d : when input is %b %b %b %b %b %b %b %b %b output is %b", $time, I0, I1,
I2, I3, I4, I5... | 7.002324 |
module Assignp (
input p0,
p1,
p2,
p3,
output w
);
assign #(24) w = ((p0 & p1) & (p2 & p3));
endmodule
| 6.769987 |
module assign_deassign ();
reg clk, rst, d, preset;
wire q;
initial begin
$monitor("@%g clk %b rst %b preset %b d %b q %b", $time, clk, rst, preset, d, q);
clk = 0;
rst = 0;
d = 0;
preset = 0;
#10 rst = 1;
#10 rst = 0;
repeat (10) begin
@(posedge clk);
d <= $random;
... | 6.779608 |
module d_ff (
clk,
rst,
d,
q
);
input clk, rst, d;
output q;
reg q;
always @(posedge clk)
if (rst) begin
q <= 0;
end else begin
q <= d;
end
endmodule
| 6.915651 |
module test;
wire a;
reg b;
assign #10 a = b;
initial begin
b = 0;
#20 b = 1;
#5
if (a !== 0) begin
$display("FAILED -- a is %b", a);
$finish;
end
#6
if (a !== 1) begin
$display("FAILED -- a is %b, should be 1", a);
$finish;
end
$display("PASSED")... | 6.964054 |
module assign_inital #(
parameter data_width = 16,
cordic_steps = 16
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input [1:0] quad_in,
output signed [data_width-1:0] x_vec_out,
output signed [data_wid... | 7.831914 |
module stages_rotation #(
parameter data_width = 16,
angle_width = 16,
cordic_steps = 16,
stage_number = 1
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input signed [angle_width-1:0] angle_in,
inp... | 7.019811 |
module hang_on_ternary (
clk
);
input wire clk;
parameter WIDTH = 56;
parameter WIDTH_LOG = 6;
wire [WIDTH_LOG - 1:0] msb;
genvar i;
for (i = 1; i < WIDTH_LOG; i = i + 1) begin : ORS
wire [WIDTH - 1:0] oi;
assign oi = msb[i-1] ? 0 : 1;
assign msb[i] = |oi;
end
endmodule
| 6.607141 |
module assign_zero_32bit (
data
);
output [31:0] data;
reg [31:0] data;
initial data = 32'b0;
endmodule
| 7.659389 |
module assign_one_32bit (
data
);
output [31:0] data;
reg [31:0] data;
initial data = 32'b1;
endmodule
| 6.886693 |
module fulladd42 (
sum,
c_out,
a,
b,
c_in
);
output [15:0] sum;
output c_out;
input [15:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
| 7.446875 |
module fulladd42 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a - b - c_in;
endmodule
| 7.446875 |
module AssistanceAlg (
probe,
source
);
input [12:0] probe;
output source;
wire sub_wire0;
wire source = sub_wire0;
altsource_probe altsource_probe_component (
.probe(probe),
.source(sub_wire0)
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(... | 7.257029 |
module associative_single_port_array #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 64,
parameter NUM_SET = 64,
parameter NUM_WAY = 16,
parameter SET_PTR_WIDTH_IN_BITS = $clog2(NUM_SET) + 1,
parameter WRITE_MASK_LEN = SINGLE_ENTRY_SIZE_IN_BITS / `BYTE_LEN... | 7.591966 |
module oscillator_s1 (
OSC_CLK_EN,
OSC_CLK
);
parameter T_CYCLE_CLK = (1000.0 / 7.3728);
input OSC_CLK_EN;
output OSC_CLK;
wire OSC_CLK_EN;
wire OSC_CLK;
reg osc_int_clk;
assign OSC_CLK = OSC_CLK_EN ? osc_int_clk : 1'bZ;
initial begin
osc_int_clk = 0;
`ifdef GSIM
forever begin
... | 7.450477 |
module Assume4R_Controller #(
parameter N = 16
) (
input start,
getA,
getX,
overflow,
clk,
rst,
input [2:0] lsb3,
output reg lmA,
lmX,
ldA,
ldX,
ldP,
shX,
shP,
clrP,
sub,
ready,
shSignExtend,
ldCo,
ldOv,
output reg [1:0] coefSel
);
... | 7.158342 |
module Assume4R_Datapath #(
parameter N = 16
) (
input [N/2 - 1:0] inBus,
input lmA,
lmX,
ldA,
ldX,
ldP,
shX,
shP,
clrP,
sub,
putOut,
shSignExtend,
ldCo,
ldOv,
clk,
rst,
input [1:0] coefSel,
output overflow,
output [2:0] lsb3,
output [N... | 6.857891 |
module assume_areset_sync_release #(
parameter reset_inverted = 1'b1
) (
input wire clk,
input wire async_reset
);
wire reset_asserted;
generate
if (reset_inverted) assign reset_asserted = !async_reset;
else assign reset_asserted = async_reset;
endgenerate
(* gclk *) reg formal_timestep;
... | 8.123857 |
module Ass_3_1_v (
input [15:0] input1,
output reg [7:0] seg_out,
output [7:0] seg_en,
output [15:0] output1
);
assign seg_en = ~8'hff;
assign output1 = input1;
always @* begin
casex (input1)
16'bxxxxxxxxxxxxxxx1: seg_out = 8'b01000000; //0
16'bxxxxxxxxxxxxxx10: seg_out = 8'b0111... | 7.020376 |
module Ass_3_2_v (
input EI,
input A,
B,
C,
D,
output outputa,
outputb,
outputc,
outputd,
output F,
output EO
);
assign {outputa, outputb, outputc, outputd} = {A, B, C, D};
Mux_74151 Mux1 (
.EI(EI),
.S2(A),
.S1(B),
.S0(C),
.D0(1'b1),
... | 6.893941 |
module Ass_4_3_D (
input clk,
input D,
input reset,
output wire Q,
output wire Qtran
);
reg Qtemp;
always @(posedge clk, posedge reset, negedge reset) begin
if (reset) begin
Qtemp = 0;
end else begin
Qtemp = D;
end
end
assign Q = Qtemp;
assign Qtran = ~Q;
endmodule
... | 7.116415 |
module Ass_4_3_ff (
input x_in,
input clk,
input reset,
output [1:0] state
);
wire useless;
Ass_4_3_D test1 (
.D((x_in & ~state[1]) | (~x_in & state[0])),
.clk(clk),
.reset(reset),
.Q(state[0]),
.Qtran(useless)
);
Ass_4_3_D test2 (
.D((x_in & state[0]) | (~x_i... | 6.5985 |
module AStep_Mux (
data0x,
data1x,
data2x,
data3x,
data4x,
data5x,
data6x,
data7x,
sel,
result
);
input [2:0] data0x;
input [2:0] data1x;
input [2:0] data2x;
input [2:0] data3x;
input [2:0] data4x;
input [2:0] data5x;
input [2:0] data6x;
input [2:0] data7x;
inp... | 6.736366 |
modules
`include "Ghost_unit.sv"
// "Ghost_unit.sv" submodules
`include "sin_cos.sv"
`include "sincos_alt_model.v"
`include "Move_Ghost.sv"
`include "Draw_Ghost.sv"
`include "rot_sin_cos.v"
`include "ghost_alt_model.v"
`include "Drawing_priority.sv"
`include "vga_controller.v"
modul... | 7.63501 |
module asteroids_8bitworkshop_top (
input clk,
reset,
output hsync,
vsync,
output [31:0] rgb,
input [7:0] keycode,
output keystrobe
);
localparam WIDTH = 640;
localparam HEIGHT = 480;
//=======================================================
// REG/WIRE declarations
//=========... | 8.725301 |
module asu (
x,
y,
mode,
carry,
out
);
input [7:0] x, y;
input mode;
output carry;
output [7:0] out;
wire [7:0] w_1, w_2;
adder add0 (
x,
y,
w_0,
w_1
);
barrel_shifter shift0 (
x,
y[2:0],
w_2
);
assign out = mode ? w_1 : w_2;
assign... | 7.348659 |
module asu_gate (
x,
y,
mode,
carry,
out
);
input [7:0] x, y;
input mode;
output carry;
output [7:0] out;
wire [7:0] w_1, w_2;
// ks_adder_gate_8 add0 (x, y, w_0, w_1);
adder_gate add0 (
x,
y,
w_0,
w_1
);
barrel_shifter_gate shift0 (
x,
y[2... | 8.118231 |
module asu_gate_test;
parameter pattern_num = 11;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg mode;
reg clk;
reg stop;
integer i, num, error;
reg [8:0] ans_out;
reg [8:0] mux_out;
reg [1:0] data_base0[0:100];
reg [7:0] data_base1[0:100];
reg [8:0] data_base2[0:100];
asu_gate t (
... | 6.692072 |
module asyclr (
input en,
input clk,
input clr,
input in_data,
output reg out_asy
);
always @(posedge clk or posedge clr) begin
if (clr)
if (en) out_asy <= 0;
else out_asy <= out_asy;
else begin
if (en) out_asy <= in_data;
else out_asy <= out_asy;
end
end
end... | 7.123689 |
module TT (
q,
notq,
t,
clk,
reset
);
output reg q = 0;
output notq;
input t, clk, reset;
assign notq = ~q;
always @(posedge clk, negedge reset) begin
if (~reset) // Reset to zero
q <= 0;
else if (t) // Flip
q <= ~q;
end
endmodule
| 7.108227 |
module TT (
q,
notq,
t,
clk,
reset
);
output reg q = 0;
output notq;
input t, clk, reset;
assign notq = ~q;
always @(posedge clk, negedge reset) begin
if (~reset) // Reset to zero
q <= 0;
else if (t) // Flip
q <= ~q;
end
endmodule
| 7.108227 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk_0;
reg clk_1;
reg rce;
reg [`ADDR_WIDTH1-1:0] ra;
wire [`DATA_WIDTH1-1:0] rq;
reg wce;
reg [`ADDR_WIDTH0-1:0] wa;
reg [`DATA_WIDTH0-1:0] wd;
initial clk_0 = 0;
initial clk_1 = 0;
initial ra = 0;
initial wa = 0;
initial ... | 7.277485 |
module spram_9x4096_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wir... | 6.729965 |
module spram_18x2048_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 2;
input wire WEN_i;
input w... | 6.524103 |
module spram_18x2048_9x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 9;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wir... | 6.524103 |
module spram_36x1024_18x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 36;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 4;
input wire WEN_i;
input w... | 6.683816 |
module buffer_hdl_core #(
parameter WIDTHA = 8,
parameter SIZEA = 512,
parameter ADDRWIDTHA = 9,
parameter WIDTHB = 16,
parameter SIZEB = 256,
parameter ADDRWIDTHB = 8
) (
input wire buffer_clk_a,
input wire buffer_clk_b,
input ... | 9.410364 |
module asymm_bram_min_wr #(
parameter minWIDTH = 8,
parameter RATIO = 4,
parameter maxDEPTH = 512,
parameter INIT = 0
) (
input wr_clk,
input [minWIDTH-1:0] din,
input wr_en,
input [`MSB(maxDEPTH*RATIO-1) : 0] wr_addr,
input rd_clk,
output reg [minWIDTH*RATIO-1:0] dout = INIT,
... | 8.706965 |
module asymm_bram_min_rd #(
parameter minWIDTH = 8,
parameter RATIO = 4,
parameter maxDEPTH = 512,
parameter INIT = 0
) (
input wr_clk,
input [minWIDTH*RATIO-1:0] din,
input wr_en,
input [`MSB(maxDEPTH-1) : 0] wr_addr,
input rd_clk,
output reg [minWIDTH-1:0] dout = INIT,
inp... | 8.706965 |
module asym_ram_sdp_read_wider (
clkA,
clkB,
enaA,
weA,
enaB,
addrA,
addrB,
diA,
doB
);
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
input clkA;
input clkB;
input we... | 7.681152 |
module asym_ram_sdp_write_wider (
clkA,
clkB,
weA,
enaA,
enaB,
addrA,
addrB,
diA,
doB
);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
... | 7.681152 |
module asym_ram_tdp_read_first (
clkA,
clkB,
enaA,
weA,
enaB,
weB,
addrA,
addrB,
diA,
doA,
diB,
doB
);
parameter WIDTHB = 4;
parameter SIZEB = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA = 16;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA... | 8.166984 |
module asym_ram_tdp_write_first (
clkA,
clkB,
enaA,
weA,
enaB,
weB,
addrA,
addrB,
diA,
doA,
diB,
doB
);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 32;
pa... | 8.166984 |
module to be used in designs.
//
// Notes:
// - w_* means something is in the "write clock domain"
// - r_* means something is in the "read clock domain"
// - Single memory element is DATA_SIZE bits wide
// - Memory is 2^ADDR_SIZE elements deep
//
// Date: December 11, 2021
// Author: Shawn Hymel
// License: 0BSD
... | 7.785841 |
module async_fifo_tb ();
// Settings
localparam DATA_SIZE = 8;
localparam ADDR_SIZE = 4;
// Internal signals
wire [DATA_SIZE-1:0] r_data;
wire r_empty;
wire r_full;
// Internal storage elements
reg r_en = 0;
reg r_cl... | 6.523155 |
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are se... | 7.236243 |
module async_transmitter (
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
/*
* Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
* TxD_data is latched so that it doesn't have to stay valid while it is being sent
*/
parameter C... | 7.250028 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX... | 6.83375 |
module BaudTickGen (
input wire clk,
enable,
output wire tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >>... | 7.463142 |
module async2sync (
input async,
input clk,
output reg clk_en = 0
);
reg async_r;
always @(posedge clk or posedge async)
if (async) async_r <= 1'b1;
else if (done || !init_done) async_r <= 0;
reg done = 0;
reg init_done = 0;
always @(posedge clk) begin
if (!async && !init_done) init... | 6.632058 |
module async2syncRst (
input clk,
input rst_async_n,
output rst_sync
);
reg rst_s1, rst_s2;
always @(posedge clk, negedge rst_async_n) begin
if (!rst_async_n) begin
rst_s1 <= 1'b0;
rst_s2 <= 1'b0;
end else begin
rst_s1 <= 1'b1;
rst_s2 <= rst_s1;
end
end
// as... | 6.734188 |
module sync_async (
in1,
in2,
out1,
out2,
reset,
clock
);
input in1;
input in2;
output out1;
output out2;
input reset;
input clock;
reg out1, out2;
// Synchronous : Depend on clock.
always @(posedge clock) begin
if (reset) out1 = 0;
else out1 = in1;
end
// Asynchr... | 6.510019 |
module master (
input ready,
w,
output [15:0] address,
inout [15:0] data
);
reg [15:0] ar, dr;
assign address = ar;
assign data = (w) ? dr : 16'hzzzz;
always @(*) begin
if (!w) dr = #1 data;
end
endmodule
| 7.034859 |
module
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wir... | 9.001229 |
module async_counter_top (
enable,
clock,
resetp,
q
);
input enable, clock, resetp;
output [2:0] q;
wire [2:0] c;
t_flipflop v1 (
enable,
resetp,
clock,
c[0]
);
t_flipflop v2 (
enable,
resetp,
~c[0],
c[1]
);
t_flipflop v3 (
enable,
... | 6.77988 |
module name is : async_fifo
module <:$mod_name:>
(
// FIFO
parameter data_width = <:$dwd:>,// FIFO
parameter data_depth = <:$depth:>,// FIFO
parameter address_width = <:$awd:>, // ַȣΪ2^nFIFOҪĶ/дָλΪ(n+1)λһλΪ۷־λ
input rst_wr,
input ... | 7.351375 |
module AsyncFifo #(
parameter DEPTH = 1,
parameter WIDTH = 1,
parameter ALMOST = 1
) ( /*AUTOARG*/
// Outputs
rd_dat,
empty,
full,
// Inputs
iclk,
oclk,
iclk_rst_b,
oclk_rst_b,
wr_en,
rd_en,
wr_dat
);
`include "clog2.vh"
`define ADDR_WIDTH (clog2(DEPTH)... | 7.501757 |
module ASYNCFIFOGA #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
input wrst_n, //async reset
input wclk,
input winc, //write enable
input [DSIZE-1:0] wdata,
output wfull,
input rrst_n,
input rclk,
... | 7.497331 |
module fifomem_ga #(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4) // Number of mem address bits
(
output [DATASIZE-1:0] rdata ,
input [DATASIZE-1:0] wdata ,
input [ADDRSIZE-1:0] waddr ,
input [ADDRSIZE-1:0] raddr ,
input ... | 7.485738 |
module sync_r2w_ga #(
parameter ADDRSIZE = 4
) (
output [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk,
input wrst_n
);
DFF_ #(
.DATA_WIDTH(ADDRSIZE + 1)
) rptr_sync (
.i_iSig(rptr),
.i_aOReset_N(wrst_n),
.i_OClk(wclk),
.o_o... | 6.826209 |
module rptr_empty_ga #(
parameter ADDRSIZE = 4)
(
output reg rempty ,
output [ADDRSIZE-1:0] raddr ,
output reg [ADDRSIZE :0] rptr ,
input [ADDRSIZE :0] rq2_wptr,
input rinc ,
input rclk ,
inp... | 7.029665 |
module wptr_full_ga #(
parameter ADDRSIZE = 4)
(
output reg wfull ,
output [ADDRSIZE-1:0] waddr ,
output reg [ADDRSIZE :0] wptr ,
input [ADDRSIZE :0] wq2_rptr,
input winc ,
input wclk ,
inpu... | 7.240763 |
module asyfifo (
rd_clk,
wr_clk,
rst,
wr_en,
rd_en,
w_data,
r_data,
full,
empty,
wr_err,
rd_err
);
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR_PTR_WIDTH = 4;
input rd_clk, wr_clk, rst, wr_en, rd_en;
input [WIDTH-1:0] w_data;
output reg [WIDTH-1:0] ... | 6.586786 |
module tb;
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR_PTR_WIDTH = 4;
parameter MAX_WR_DELAY = 8;
parameter MAX_RD_DELAY = 12;
reg rd_clk, wr_clk, rst, wr_en, rd_en;
reg [WIDTH-1:0] w_data;
wire [WIDTH-1:0] r_data;
wire wr_err, rd_err, full, empty;
integer i, j, p, q;
reg [3:0] w... | 6.612288 |
module asyncfifo_tb; //testbench module
reg write_clk, read_clk, reset, write_en, read_en; //register declaration
reg [7:0] data_in;
wire mem_full, mem_empty;
wire [7:0] out;
//instantiation of design module
asyncfifo dut (
.write_clk(write_clk), //input write clock
.read_clk (read_clk), ... | 8.462746 |
module ASYNCH_DRIVER (
input ASYNCH_CLK,
input [7:0] ASYNCH_BYTE_TO_SEND,
input ASYNCH_ENABLE,
input ASYNCH_TX_LINE,
output reg ASYNCH_RX_LINE = 1'b1,
output reg ASYNCH_READY = 1'b1,
output [7:0] ASYNCH_BYTE_RECEIVED,
output reg ASYNCH_DATA_OK = 1'b0,
output reg ASYNCH_TEST_PIN = 1'b... | 7.604342 |
module asynchronus_ram
#(parameter ADDR_WDITH = 8, DATA_WDITH =1)
(
clk, we, addr, din, dout
)
input wire clk, we;
input wire [ADDR_WDITH-1:0] addr;
input wire [DATA_WDITH-1:0] din;
output wire [DATA_WDITH-1:0] dout;
reg [DATA_WDITH-1:0] ram [2*ADDR_WDITH-1:0]
always @(posedge clk) begin
if (we)
ram[addr] <= di... | 7.327964 |
module asynchronus_rom (
addr,
data
);
input wire [3:0] addr;
output reg [7:0] data;
always @(*) begin
case (addr)
4'h0: data = 7'b0000001;
4'h1: data = 7'b1001111;
4'h2: data = 7'b0010010;
4'h3: data = 7'b0000110;
4'h4: data = 7'b1001100;
4'h5: data = 7'b0100100;... | 7.327964 |
module asynchronousWriteToHBM_HBM_m_axi_flushManager
#(parameter
NUM_READ_OUTSTANDING = 2,
NUM_WRITE_OUTSTANDING = 2
)(
input clk,
input reset,
input clk_en,
input flush,
output flush_done,
input in_AWVALID,
output out_AWVALID,
input in_AWREADY,
output out_AWREAD... | 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_reg_slice #(
parameter DATA_WIDTH = 8
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire ... | 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_srl #(
parameter DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [DATA_... | 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_mem #(
parameter MEM_STYLE = "auto",
DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire ... | 7.46464 |
module asynchronousWriteToHBM_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_sta... | 7.46464 |
module asynchronousWriteToHBM_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_d... | 7.46464 |
module asynchronous_fifo(
output full,empty, [7:0]d_out,
input wr_clk,wr_en,rd_en,rst,[7:0]d_in);
wire gen_clk;
wire [4:0]wr_addr,rd_addr;
wire wen;
wire [5:0]wr_ptr,rd_ptr,wq2_rd_ptr,rq2_wr_ptr;
clk_wiz_0 clocking
(
.clk_out1(gen_clk),
.clk_in1(wr_clk));
and(wen,wr_en,~full);
dual_port_sram bram(.wr_c... | 6.759178 |
module asynch_edge_detect (
input SYNC_CLK_IN,
input ASYNC_IN,
output DETECT_OUT
);
wire detect;
wire signal_in;
reg signal_in_prev;
assign detect = signal_in & ~signal_in_prev;
assign DETECT_OUT = detect;
always @(posedge SYNC_CLK_IN) begin
signal_in_prev <= signal_in;
end
s... | 7.200684 |
module asynch_up_counter (
input clk,
input reset_n,
output [3:0] Q
);
T_FF FF0 (
.clk(clk),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[0])
);
T_FF FF1 (
.clk(~Q[0]),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[1])
);
T_FF FF2 (
.clk(~Q[1]),
.T(1'b1),
... | 6.685081 |
module asynch_up_counter_tb ();
reg clk, reset_n;
wire [3:0] Q;
// Instantiate module under test
asynch_up_counter uut (
.clk(clk),
.reset_n(reset_n),
.Q(Q)
);
// timer
initial #200 $stop;
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk ... | 6.685081 |
module name is : async_fifo
module <:$mod_name:>
(
// FIFO
parameter data_width = <:$dwd:>,// FIFO
parameter data_depth = <:$depth:>,// FIFO
parameter address_width = <:$awd:>, // ַȣΪ2^nFIFOҪĶ/дָλΪ(n+1)λһλΪ۷־λ
input rst_wr,
input ... | 7.351375 |
module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset
);
wire [7:0] _zz_5;
wire [4:0] _zz_6;
wire [4:0] _zz_7;
wire [7:0] _zz_8;
wire _zz_9;
reg [4:0] head;
reg [4:0] tail;
reg ... | 6.757216 |
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