code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module //Required to pair up with already used "`module" in file assert_win_unchange.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_unchange_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
| 6.783873 |
module //Required to pair up with already used "`module" in file assert_zero_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_zero_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
| 6.783873 |
module half_sub (
input ha,
hb,
output hby,
hd
);
assign hd = ha ^ hb;
assign hby = ~(ha) & hb;
endmodule
| 7.195826 |
module full_sub (
input a,
b,
c,
output by,
d
);
wire x, y, z;
half_sub hs1 (
a,
b,
x,
y
);
half_sub hs2 (
y,
c,
z,
d
);
or (by, z, x);
endmodule
| 7.064028 |
module test (
output c
);
wire a;
wire b;
always @(*) begin
a = 0;
b = 0;
c = a + b;
end
endmodule
| 6.644084 |
module ASSIGN1 (
IN,
OUT
);
output OUT;
input IN;
assign OUT = IN;
endmodule
| 6.518691 |
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output sum, carry;
assign sum = a ^ b ^ c;
assign carry = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module flip_flop16 (
d1,
q1,
clk,
reset
);
input [15:0] d1;
input clk, reset;
output [15:0] q1;
reg [15:0] q1;
always @(posedge clk) begin
if (reset == 1'b1) q1 <= 16'b0;
else q1 <= d1;
end
endmodule
| 6.674598 |
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output sum, carry;
assign sum = a ^ b ^ c;
assign carry = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module flip_flop (
d,
q,
clk,
reset
);
input d, clk, reset;
output reg q;
always @(posedge clk) begin
if (reset == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.373981 |
module ripple (
a,
b,
c,
sum,
carry
);
input [15:0] a, b;
output [15:0] sum;
output [15:0] c;
output carry;
full_adder mod0 (
a[0],
b[0],
1'b0,
sum[0],
c[0]
);
full_adder mod1 (
a[1],
b[1],
c[0],
sum[1],
c[1]
);
full_adder mod2 (
a[2],
b[2],
c[1],
sum[2],
c[2]
);
full_adder mod3 (
a[3],
b[3],
c[2],
sum[3],
c[3]
);
full_adder mod4 (
a[4],
b[4],
c[3],
sum[4],
c[4]
);
full_adder mod5 (
a[5],
b[5],
c[4],
sum[5],
c[5]
);
full_adder mod6 (
a[6],
b[6],
c[5],
sum[6],
c[6]
);
full_adder mod7 (
a[7],
b[7],
c[6],
sum[7],
c[7]
);
full_adder mod8 (
a[8],
b[8],
c[7],
sum[8],
c[8]
);
full_adder mod9 (
a[9],
b[9],
c[8],
sum[9],
c[9]
);
full_adder mod10 (
a[10],
b[10],
c[9],
sum[10],
c[10]
);
full_adder mod11 (
a[11],
b[11],
c[10],
sum[11],
c[11]
);
full_adder mod12 (
a[12],
b[12],
c[11],
sum[12],
c[12]
);
full_adder mod13 (
a[13],
b[13],
c[12],
sum[13],
c[13]
);
full_adder mod14 (
a[14],
b[14],
c[13],
sum[14],
c[14]
);
full_adder mod15 (
a[15],
b[15],
c[14],
sum[15],
c[15]
);
assign carry = c[15];
endmodule
| 6.679037 |
module assignm2_tb;
reg [15:0] a, b;
wire [15:0] sum, c;
wire carry;
wire [17:0] sum_final;
ripple mod16 (
a,
b,
c,
sum,
carry,
sum_final
);
initial begin
$dumpfile("assi.vcd");
$dumpvars(0, assignm2_tb);
a = 16'b1001111011111011;
b = 16'b1111001100011000;
#2 a = 16'b1101111011111011;
#4 b = 16'b1011001100011000;
#6 a = 16'b1111111011111011;
b = 16'b1111001100011110;
end
always begin
#20 $finish;
end
initial $monitor($time, "a=%d,b=%d,sum_final=%d", a, b, sum_final);
endmodule
| 7.074257 |
module assignment (
input [3:0] KEY,
input [6:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output reg [3:0] LEDR
);
wire [31:0] ALU_result;
wire [31:0] PC;
wire [31:0] Instr;
wire Branch;
wire RegWrite;
wire RegDst;
wire ALUSrc;
wire [1:0] ALUOp;
reg [31:0] displace;
wire [31:0] REG_Output_1;
wire [31:0] ALUsource;
wire [3:0] ALU_control;
wire [31:0] Immediate;
wire [31:0] PC_next;
wire [31:0] PC_plus_offset;
MIPS(
KEY[3],
KEY[2],
KEY[1],
SW[6:0],
ALU_result,
PC,
Instr,
Branch,
RegWrite,
RegDst,
ALUSrc,
ALUOp,
REG_Output_1,
ALUsource,
ALU_control,
Immediate,
PC_next,
PC_plus_offset
);
always @* begin
case (LEDR)
4'b0000: displace <= PC;
4'b0001: displace <= ALU_result;
4'b0010: displace <= Instr;
4'b0011: displace <= {31'b0, Branch};
4'b0100: displace <= {31'b0, RegWrite};
4'b0101: displace <= {31'b0, RegDst};
4'b0110: displace <= {31'b0, ALUSrc};
4'b0111: displace <= {30'b0, ALUOp};
4'b1000: displace <= REG_Output_1;
4'b1001: displace <= ALUsource;
4'b1010: displace <= ALU_control;
4'b1011: displace <= Immediate;
4'b1100: displace <= PC_next;
4'b1101: displace <= PC_plus_offset;
endcase
end
always @(negedge KEY[0], negedge KEY[2]) begin
if (!KEY[2]) LEDR <= 3'b0;
else if (LEDR < 13) LEDR <= LEDR + 1;
else LEDR <= 0;
end
hex_decoder(
displace[3:0], HEX0
); hex_decoder(
displace[7:4], HEX1
); hex_decoder(
displace[11:8], HEX2
); hex_decoder(
displace[15:12], HEX3
); hex_decoder(
displace[19:16], HEX4
); hex_decoder(
displace[23:20], HEX5
); hex_decoder(
displace[27:24], HEX6
); hex_decoder(
displace[31:28], HEX7
);
endmodule
| 7.31878 |
module assignment1_frame (
input CLOCK_50,
input RESET_N,
input [3:0] KEY,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [9:0] LEDR
);
wire clk;
wire rst;
reg [9:0] red_lights;
reg [3:0] multiplier = 32'd2;
reg [31:0] blink_timer = 32'd12500000;
reg [31:0] count = 32'd1;
reg [4:0] state = 32'd0;
reg [0:0] is_pressed = 1'b0;
wire [31:0] full_timer = blink_timer * multiplier;
assign clk = CLOCK_50;
assign rst = ~RESET_N;
always @(posedge clk or posedge rst) begin
if (rst) begin
multiplier <= 2;
end else if (!KEY[0] && !is_pressed && multiplier < 8) begin
is_pressed <= 1;
multiplier <= multiplier + 1;
end else if (!KEY[1] && !is_pressed && multiplier > 1) begin
is_pressed <= 1;
multiplier <= multiplier - 1;
end else if (KEY[0] && KEY[1]) begin
is_pressed <= 0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= 0;
count <= 0;
end else if (full_timer <= count) begin
count <= 0;
state <= state + 1;
if (state == 17) begin
state <= 0;
end
end else begin
if (state == 0 || state == 2 || state == 4 || state == 12 || state == 14 || state == 16) begin
red_lights = 10'b1111100000;
end
if(state == 6 || state == 8 || state == 10 || state == 13 || state == 15 || state == 17) begin
red_lights = 10'b0000011111;
end
if (state == 1 || state == 3 || state == 5 || state == 7 || state == 9 || state == 11) begin
red_lights = 10'b0000000000;
end
count <= count + 1;
end
end
assign LEDR = red_lights;
SevenSeg ss0 (
.IN (state),
.OFF(1'b0),
.OUT(HEX0)
);
SevenSeg ss1 (
.IN ((state >> 4) & 1'b0001),
.OFF(1'b0),
.OUT(HEX1)
);
SevenSeg ss2 (
.IN (multiplier),
.OFF(1'b0),
.OUT(HEX3)
);
SevenSeg ss3 (
.IN (is_pressed),
.OFF(1'b0),
.OUT(HEX4)
);
endmodule
| 6.623045 |
module assignment2B (
clk,
rstn,
w,
Q,
c
);
input clk, rstn;
input [1:0] w;
output reg Q;
output reg [1:0] c;
reg [1:0] y, Y;
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
always @(w, y)
case (y)
A:
if (w[1] == 0 && w[0] == 0) begin
Q = 0;
y = A;
c = 2'b00;
end else if (w[1] == 0 && w[0] == 1) begin
Q = 0;
Y = B;
c = 2'b00;
end else if (w[1] == 1 && w[0] == 0) begin
Q = 0;
Y = D;
c = 2'b00;
end
endcase
endmodule
| 6.701994 |
module coca (
sw,
c,
o,
a,
x,
show
);
input [2:0] sw, o, c, a, x;
output [2:0] show;
assign show = (sw == 3'b000) ? c : (sw == 3'b001) ? o : (sw == 3'b010) ? a : x;
endmodule
| 7.44236 |
module assignments (
input wire clk,
input wire rst,
output reg [7:0] data_nba,
output reg [7:0] data_ba
);
reg [7:0] nba_buffer;
reg [7:0] ba_buffer;
always @(posedge clk) begin
if (~rst) begin
nba_buffer <= 0;
data_nba <= 0;
end else begin
nba_buffer <= nba_buffer + 1;
data_nba <= nba_buffer;
end
end
always @(posedge clk) begin
if (~rst) begin
data_ba = 0;
ba_buffer = 0;
end else begin
ba_buffer = ba_buffer + 1;
data_ba = ba_buffer;
end
end
endmodule
| 7.327347 |
module assignments_tb ();
reg clk;
reg rst;
wire [7:0] data_nba;
wire [7:0] data_ba;
assignments uut (
.clk(clk),
.rst(rst),
.data_nba(data_nba),
.data_ba(data_ba)
);
initial begin
rst = 1;
clk = 0;
#200 rst = 0;
#200 rst = 1;
end
always begin
#50 clk <= ~clk;
end
endmodule
| 6.671331 |
module final_sub (
S,
B,
A,
COUT
);
//: interface /sz:(117, 103) /bd:[ Li0>B[7:0](68/103) Li1>A[7:0](34/103) Ro0<S[7:0](68/103) Ro1<COUT(34/103) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1
input [7:0] B; //: /sn:0 {0}(#:603,295)(460,295)(460,295)(450,295){1}
//: {2}(448,293)(448,235)(448,235)(448,163){3}
//: {4}(450,161)(#:602,161){5}
//: {6}(448,159)(448,113){7}
//: {8}(448,297)(448,303)(448,303)(#:448,375){9}
output COUT; //: /sn:0 {0}(698,267)(837,267)(837,259)(847,259){1}
//: {2}(851,259)(861,259)(861,259)(910,259){3}
//: {4}(849,257)(849,251){5}
//: {6}(849,261)(849,268){7}
input [7:0] A; //: /sn:0 {0}(#:603,267)(417,267)(417,267)(413,267){1}
//: {2}(411,265)(411,233)(411,233)(411,191){3}
//: {4}(413,189)(#:602,189){5}
//: {6}(411,187)(411,108){7}
//: {8}(411,269)(411,286)(411,286)(#:411,372){9}
output [7:0] S; //: /sn:0 {0}(#:862,228)(888,228)(888,228)(903,228){1}
wire w4; //: /sn:0 {0}(697,161)(761,161)(761,108)(771,108){1}
//: {2}(775,108)(822,108)(822,107){3}
//: {4}(773,110)(773,115){5}
wire [7:0] w1; //: /sn:0 {0}(#:697,189)(809,189)(809,218)(833,218){1}
wire [7:0] w2; //: /sn:0 {0}(#:698,295)(818,295)(818,238)(833,238){1}
//: enddecls
sub_8 g8 (
.A(B),
.B(A),
.cout(w4),
.s(w1)
); //: @(603, 134) /sz:(93, 83) /sn:0 /p:[ Li0>5 Li1>5 Ro0<0 Ro1<0 ]
//: OUT g4 (S) @(900,228) /sn:0 /w:[ 1 ]
//: IN g3 (B) @(448,377) /sn:0 /R:1 /w:[ 9 ]
//: IN g2 (A) @(411,374) /sn:0 /R:1 /w:[ 9 ]
//: joint g1 (COUT) @(849, 259) /w:[ 2 4 1 6 ]
//: joint g10 (B) @(448, 161) /w:[ 4 6 -1 3 ]
//: LED g6 (w4) @(822,100) /sn:0 /w:[ 3 ] /type:0
sub_8 g9 (
.A(A),
.B(B),
.cout(COUT),
.s(w2)
); //: @(604, 240) /sz:(93, 83) /sn:0 /p:[ Li0>0 Li1>0 Ro0<0 Ro1<0 ]
//: joint g7 (w4) @(773, 108) /w:[ 2 -1 1 4 ]
//: joint g12 (A) @(411, 267) /w:[ 1 2 -1 8 ]
//: joint g11 (A) @(411, 189) /w:[ 4 6 -1 3 ]
//: OUT g5 (COUT) @(907,259) /sn:0 /w:[ 3 ]
_GGMUX2x8 #(8, 8) g0 (
.I0(w2),
.I1(w1),
.S (COUT),
.Z (S)
); //: @(849,228) /sn:0 /R:1 /w:[ 1 1 5 0 ] /ss:0 /do:0
//: joint g13 (B) @(448, 295) /w:[ 1 2 -1 8 ]
endmodule
| 6.522966 |
module dec_4to16 (
y4,
y14,
y5,
a,
y11,
y12,
y6,
y13,
y10,
y0,
y2,
y9,
y7,
y8,
y3,
y15,
y1
);
//: interface /sz:(189, 590) /bd:[ Li0>a[3:0](34/590) Ro0<y0(573/590) Ro1<y1(544/590) Ro2<y2(515/590) Ro3<y3(481/590) Ro4<y4(450/590) Ro5<y5(416/590) Ro6<y6(370/590) Ro7<y7(321/590) Ro8<y8(280/590) Ro9<y9(237/590) Ro10<y10(200/590) Ro11<y11(166/590) Ro12<y12(126/590) Ro13<y13(90/590) Ro14<y14(59/590) Ro15<y15(26/590) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1
output y11; //: /sn:0 {0}(360,172)(423,172)(423,175)(474,175){1}
output y13; //: /sn:0 {0}(474,125)(395,125)(395,159)(360,159){1}
output y4; //: /sn:0 {0}(474,378)(399,378)(399,389)(360,389){1}
output y0; //: /sn:0 {0}(474,487)(377,487)(377,416)(360,416){1}
output y12; //: /sn:0 {0}(360,165)(423,165)(423,149)(474,149){1}
output y8; //: /sn:0 {0}(474,258)(375,258)(375,192)(360,192){1}
output y15; //: /sn:0 {0}(474,79)(376,79)(376,145)(360,145){1}
output y10; //: /sn:0 {0}(474,202)(395,202)(395,179)(360,179){1}
output y1; //: /sn:0 {0}(474,460)(384,460)(384,409)(360,409){1}
output y2; //: /sn:0 {0}(473,431)(392,431)(392,402)(360,402){1}
output y3; //: /sn:0 {0}(474,404)(399,404)(399,396)(360,396){1}
output y9; //: /sn:0 {0}(474,231)(382,231)(382,185)(360,185){1}
input [3:0] a; //: /sn:0 {0}(#:250,503)(250,449)(250,449)(250,393){1}
//: {2}(250,392)(250,203){3}
//: {4}(250,202)(250,169){5}
//: {6}(250,168)(250,-11){7}
output y5; //: /sn:0 {0}(474,354)(392,354)(392,382)(360,382){1}
output y7; //: /sn:0 {0}(474,308)(377,308)(377,369)(360,369){1}
output y14; //: /sn:0 {0}(474,101)(384,101)(384,152)(360,152){1}
output y6; //: /sn:0 {0}(474,330)(384,330)(384,376)(360,376){1}
wire w16; //: /sn:0 {0}(306,281)(306,430)(344,430)(344,415){1}
wire [2:0] w4; //: /sn:0 {0}(254,169)(#:262,169)(262,169)(331,169){1}
wire [2:0] w15; //: /sn:0 {0}(254,393)(#:262,393)(262,393)(331,393){1}
wire w5; //: /sn:0 {0}(254,203)(279,203)(279,203)(304,203){1}
//: {2}(308,203)(344,203)(344,191){3}
//: {4}(306,205)(306,215)(306,215)(306,265){5}
//: enddecls
assign w4 = a[2:0]; //: TAP g4 @(248,169) /sn:0 /R:2 /w:[ 0 5 6 ] /ss:1
assign w15 = a[2:0]; //: TAP g3 @(248,393) /sn:0 /R:2 /w:[ 0 1 2 ] /ss:1
//: OUT g16 (y4) @(471,378) /sn:0 /w:[ 0 ]
//: OUT g26 (y14) @(471,101) /sn:0 /w:[ 0 ]
//: OUT g17 (y5) @(471,354) /sn:0 /w:[ 0 ]
//: IN g2 (a) @(250,505) /sn:0 /R:1 /w:[ 0 ]
//: OUT g23 (y11) @(471,175) /sn:0 /w:[ 1 ]
_GGDECODER8 #(6, 6) g1 (
.I (w15),
.E (w16),
.Z0(y0),
.Z1(y1),
.Z2(y2),
.Z3(y3),
.Z4(y4),
.Z5(y5),
.Z6(y6),
.Z7(y7)
); //: @(344,393) /sn:0 /R:1 /w:[ 1 1 1 1 1 1 1 1 1 1 ] /ss:0 /do:0
//: OUT g24 (y12) @(471,149) /sn:0 /w:[ 1 ]
//: OUT g18 (y6) @(471,330) /sn:0 /w:[ 0 ]
//: OUT g25 (y13) @(471,125) /sn:0 /w:[ 0 ]
_GGNBUF #(2) g6 (
.I(w5),
.Z(w16)
); //: @(306,271) /sn:0 /R:3 /w:[ 5 0 ]
//: joint g7 (w5) @(306, 203) /w:[ 2 -1 1 4 ]
//: OUT g22 (y10) @(471,202) /sn:0 /w:[ 0 ]
//: OUT g12 (y0) @(471,487) /sn:0 /w:[ 0 ]
assign w5 = a[3]; //: TAP g5 @(248,203) /sn:0 /R:2 /w:[ 0 3 4 ] /ss:1
//: OUT g14 (y2) @(470,431) /sn:0 /w:[ 0 ]
//: OUT g21 (y9) @(471,231) /sn:0 /w:[ 0 ]
//: OUT g19 (y7) @(471,308) /sn:0 /w:[ 0 ]
//: OUT g20 (y8) @(471,258) /sn:0 /w:[ 0 ]
_GGDECODER8 #(6, 6) g0 (
.I (w4),
.E (w5),
.Z0(y8),
.Z1(y9),
.Z2(y10),
.Z3(y11),
.Z4(y12),
.Z5(y13),
.Z6(y14),
.Z7(y15)
); //: @(344,169) /sn:0 /R:1 /w:[ 1 3 1 1 1 0 0 1 1 1 ] /ss:0 /do:0
//: OUT g15 (y3) @(471,404) /sn:0 /w:[ 0 ]
//: OUT g27 (y15) @(471,79) /sn:0 /w:[ 0 ]
//: OUT g13 (y1) @(471,460) /sn:0 /w:[ 0 ]
endmodule
| 7.346636 |
module tb ();
reg I0, I1, I2, I3, I4, I5, I6, I7, I8;
wire Y;
cf dut (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
Y
);
initial begin
$monitor("@time %3d : when input is %b %b %b %b %b %b %b %b %b output is %b", $time, I0, I1,
I2, I3, I4, I5, I6, I7, I8, Y);
#5 I0 = 0;
I1 = 1;
I2 = 0;
I3 = 1;
I4 = 0;
I5 = 1;
I6 = 0;
I7 = 1;
I8 = 1;
#10 I0 = 1;
I1 = 1;
I2 = 0;
I3 = 1;
I4 = 1;
I5 = 1;
I6 = 0;
I7 = 0;
I8 = 1;
$finish;
end
endmodule
| 7.002324 |
module Assignp (
input p0,
p1,
p2,
p3,
output w
);
assign #(24) w = ((p0 & p1) & (p2 & p3));
endmodule
| 6.769987 |
module assign_deassign ();
reg clk, rst, d, preset;
wire q;
initial begin
$monitor("@%g clk %b rst %b preset %b d %b q %b", $time, clk, rst, preset, d, q);
clk = 0;
rst = 0;
d = 0;
preset = 0;
#10 rst = 1;
#10 rst = 0;
repeat (10) begin
@(posedge clk);
d <= $random;
@(negedge clk);
preset <= ~preset;
end
#1 $finish;
end
// Clock generator
always #1 clk = ~clk;
// assign and deassign q of flip flop module
always @(preset)
if (preset) begin
assign U.q = 1; // assign procedural statement
end else begin
deassign U.q; // deassign procedural statement
end
d_ff U (
clk,
rst,
d,
q
);
endmodule
| 6.779608 |
module d_ff (
clk,
rst,
d,
q
);
input clk, rst, d;
output q;
reg q;
always @(posedge clk)
if (rst) begin
q <= 0;
end else begin
q <= d;
end
endmodule
| 6.915651 |
module test;
wire a;
reg b;
assign #10 a = b;
initial begin
b = 0;
#20 b = 1;
#5
if (a !== 0) begin
$display("FAILED -- a is %b", a);
$finish;
end
#6
if (a !== 1) begin
$display("FAILED -- a is %b, should be 1", a);
$finish;
end
$display("PASSED");
end
endmodule
| 6.964054 |
module assign_inital #(
parameter data_width = 16,
cordic_steps = 16
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input [1:0] quad_in,
output signed [data_width-1:0] x_vec_out,
output signed [data_width-1:0] y_vec_out,
output reg [cordic_steps-1:0] micro_rotation_out,
output reg [1:0] quad_out,
output reg done
);
reg [data_width-1:0] x_temp_out, y_temp_out;
assign x_vec_out = x_temp_out;
assign y_vec_out = y_temp_out;
always @(posedge clk or negedge nreset) begin
if (~nreset) begin
x_temp_out <= {data_width{1'b0}};
y_temp_out <= {data_width{1'b0}};
micro_rotation_out <= {cordic_steps{1'b0}};
done <= 1'b0;
end else begin
if (enable) begin
x_temp_out <= x_vec_in + y_vec_in;
y_temp_out <= y_vec_in - x_vec_in;
micro_rotation_out <= {{(cordic_steps - 1) {1'b0}}, 1'b1};
quad_out <= quad_in;
done <= 1'b1;
end else begin
done <= 1'b0;
end
end
end
endmodule
| 7.831914 |
module stages_rotation #(
parameter data_width = 16,
angle_width = 16,
cordic_steps = 16,
stage_number = 1
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input signed [angle_width-1:0] angle_in,
input signed [angle_width-1:0] target_angle,
output signed [data_width-1:0] x_vec_out,
output signed [data_width-1:0] y_vec_out,
output reg signed [angle_width-1:0] angle_out,
output reg signed [angle_width-1:0] target_angle_out,
output reg done
);
wire signed [angle_width-1:0] atan[cordic_steps-1:0];
assign atan[0] = 20'h02000; // pi/4
assign atan[1] = 20'h012E4;
assign atan[2] = 20'h009FB;
assign atan[3] = 20'h00511;
assign atan[4] = 20'h0028B;
assign atan[5] = 20'h00145;
assign atan[6] = 20'h000A2;
assign atan[7] = 20'h00051;
assign atan[8] = 20'h00028;
assign atan[9] = 20'h00014;
assign atan[10] = 20'h0000A;
assign atan[11] = 20'h00005;
assign atan[12] = 20'h00002;
assign atan[13] = 20'h00001;
assign atan[14] = 20'h00000;
assign atan[15] = 20'h00000;
reg signed [data_width-1:0] x_temp_out, y_temp_out;
assign x_vec_out = x_temp_out;
assign y_vec_out = y_temp_out;
always @(posedge clk) begin
if (~nreset) begin
x_temp_out <= $signed({data_width{1'b0}});
y_temp_out <= $signed({data_width{1'b0}});
angle_out <= 0;
done <= 1'b0;
end else begin
if (enable) begin
if ($signed(target_angle) <= $signed(angle_in)) begin
x_temp_out <= x_vec_in + (y_vec_in >>> (stage_number - 1));
y_temp_out <= y_vec_in - (x_vec_in >>> (stage_number - 1));
angle_out <= angle_in - atan[stage_number-1];
end else begin
x_temp_out <= x_vec_in - (y_vec_in >>> (stage_number - 1));
y_temp_out <= y_vec_in + (x_vec_in >>> (stage_number - 1));
angle_out <= angle_in + atan[(stage_number-1)];
end
target_angle_out <= target_angle;
done <= 1'b1;
end else begin
x_temp_out <= $signed({data_width{1'b0}});
y_temp_out <= $signed({data_width{1'b0}});
angle_out <= 0;
done <= 1'b0;
end
end
end
endmodule
| 7.019811 |
module hang_on_ternary (
clk
);
input wire clk;
parameter WIDTH = 56;
parameter WIDTH_LOG = 6;
wire [WIDTH_LOG - 1:0] msb;
genvar i;
for (i = 1; i < WIDTH_LOG; i = i + 1) begin : ORS
wire [WIDTH - 1:0] oi;
assign oi = msb[i-1] ? 0 : 1;
assign msb[i] = |oi;
end
endmodule
| 6.607141 |
module assign_zero_32bit (
data
);
output [31:0] data;
reg [31:0] data;
initial data = 32'b0;
endmodule
| 7.659389 |
module assign_one_32bit (
data
);
output [31:0] data;
reg [31:0] data;
initial data = 32'b1;
endmodule
| 6.886693 |
module fulladd42 (
sum,
c_out,
a,
b,
c_in
);
output [15:0] sum;
output c_out;
input [15:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
| 7.446875 |
module fulladd42 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a - b - c_in;
endmodule
| 7.446875 |
module AssistanceAlg (
probe,
source
);
input [12:0] probe;
output source;
wire sub_wire0;
wire source = sub_wire0;
altsource_probe altsource_probe_component (
.probe(probe),
.source(sub_wire0)
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam altsource_probe_component.enable_metastability = "NO",
altsource_probe_component.instance_id = "HR", altsource_probe_component.probe_width = 13,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 0;
endmodule
| 7.257029 |
module associative_single_port_array #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 64,
parameter NUM_SET = 64,
parameter NUM_WAY = 16,
parameter SET_PTR_WIDTH_IN_BITS = $clog2(NUM_SET) + 1,
parameter WRITE_MASK_LEN = SINGLE_ENTRY_SIZE_IN_BITS / `BYTE_LEN_IN_BITS,
parameter STORAGE_TYPE = "LUTRAM"
) (
input reset_in,
input clk_in,
input access_en_in,
input [WRITE_MASK_LEN - 1 : 0] write_en_in,
input [SET_PTR_WIDTH_IN_BITS - 1 : 0] access_set_addr_in,
input [NUM_WAY - 1 : 0] way_select_in,
output [SINGLE_ENTRY_SIZE_IN_BITS * NUM_WAY - 1 : 0] read_set_out,
output [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] read_single_entry_out,
input [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] write_single_entry_in
);
wire [SINGLE_ENTRY_SIZE_IN_BITS * NUM_WAY - 1 : 0] data_to_mux;
assign read_set_out = data_to_mux;
generate
genvar gen;
if (STORAGE_TYPE == "LUTRAM") begin
for (gen = 0; gen < NUM_WAY; gen = gen + 1) begin
single_port_lutram #(
.SINGLE_ENTRY_SIZE_IN_BITS(SINGLE_ENTRY_SIZE_IN_BITS),
.NUM_SET (NUM_SET),
.SET_PTR_WIDTH_IN_BITS (SET_PTR_WIDTH_IN_BITS)
) entry_way (
.reset_in(reset_in),
.clk_in (clk_in),
.access_en_in(access_en_in & way_select_in[gen]),
.write_en_in (write_en_in & {(WRITE_MASK_LEN) {way_select_in[gen]}}),
.access_set_addr_in(access_set_addr_in),
.write_entry_in(write_single_entry_in),
.read_entry_out(data_to_mux[gen*SINGLE_ENTRY_SIZE_IN_BITS+:SINGLE_ENTRY_SIZE_IN_BITS])
);
end
end else if (STORAGE_TYPE == "BRAM") begin
for (gen = 0; gen < NUM_WAY; gen = gen + 1) begin
single_port_blockram #(
.SINGLE_ENTRY_SIZE_IN_BITS(SINGLE_ENTRY_SIZE_IN_BITS),
.NUM_SET (NUM_SET),
.SET_PTR_WIDTH_IN_BITS (SET_PTR_WIDTH_IN_BITS)
) entry_way (
.clk_in(clk_in),
.access_en_in(access_en_in & way_select_in[gen]),
.write_en_in (write_en_in & {(WRITE_MASK_LEN) {way_select_in[gen]}}),
.access_set_addr_in(access_set_addr_in),
.write_entry_in(write_single_entry_in),
.read_entry_out(data_to_mux[gen*SINGLE_ENTRY_SIZE_IN_BITS+:SINGLE_ENTRY_SIZE_IN_BITS])
);
end
end
endgenerate
reg [NUM_WAY - 1 : 0] way_select_stage;
always @(posedge clk_in or posedge reset_in) begin
if (reset_in) begin
way_select_stage <= {(NUM_WAY) {1'b0}};
end else begin
way_select_stage <= way_select_in;
end
end
mux_decoded_8 #(
.NUM_WAY(NUM_WAY),
.SINGLE_ENTRY_SIZE_IN_BITS(SINGLE_ENTRY_SIZE_IN_BITS)
) mux_8 (
.way_flatted_in (data_to_mux),
.sel_in (way_select_stage),
.way_flatted_out(read_single_entry_out)
);
endmodule
| 7.591966 |
module oscillator_s1 (
OSC_CLK_EN,
OSC_CLK
);
parameter T_CYCLE_CLK = (1000.0 / 7.3728);
input OSC_CLK_EN;
output OSC_CLK;
wire OSC_CLK_EN;
wire OSC_CLK;
reg osc_int_clk;
assign OSC_CLK = OSC_CLK_EN ? osc_int_clk : 1'bZ;
initial begin
osc_int_clk = 0;
`ifdef GSIM
forever begin
#(T_CYCLE_CLK / 2) osc_int_clk = 1;
#(T_CYCLE_CLK / 2) osc_int_clk = 0;
end
`endif
end
endmodule
| 7.450477 |
module Assume4R_Controller #(
parameter N = 16
) (
input start,
getA,
getX,
overflow,
clk,
rst,
input [2:0] lsb3,
output reg lmA,
lmX,
ldA,
ldX,
ldP,
shX,
shP,
clrP,
sub,
ready,
shSignExtend,
ldCo,
ldOv,
output reg [1:0] coefSel
);
reg [3:0] ps, ns;
reg cntEn, cntClr;
wire cntCo;
CounterModN #(
.N(N / 2),
.BITS(3)
) counter (
.en (cntEn),
.clr(cntClr),
.clk(clk),
.rst(rst),
.co (cntCo)
);
always @(posedge clk or posedge rst) begin
if (rst) ps <= `Idle;
else ps <= ns;
end
always @(ps or getA or getX or cntCo or start) begin
case (ps)
`Idle: ns = start ? `Idle : `LsbA;
`LsbA: ns = getA ? `LsbA : `WaitA;
`WaitA: ns = getA ? `MsbA : `WaitA;
`MsbA: ns = getA ? `MsbA : `LsbX;
`LsbX: ns = getX ? `LsbX : `WaitX;
`WaitX: ns = getX ? `MsbX : `WaitX;
`MsbX: ns = getX ? `MsbX : `Init;
`Init: ns = `Calc;
`Calc: ns = `Sh1;
`Sh1: ns = `Sh2;
`Sh2: ns = cntCo ? `Idle : `Calc;
default: ns = `Idle;
endcase
end
always @(ps or lsb3 or getA or getX or overflow) begin
{ready, lmA, lmX, ldA, ldX, ldP, shX, shP, clrP, sub} = 10'd0;
{cntEn, cntClr} = 2'b00;
{shSignExtend, ldCo, ldOv} = 3'd0;
coefSel = 2'b00;
case (ps)
`Idle: ready = 1'b1;
`LsbA: begin
{clrP, lmA} = 2'b10;
if (getA == 1'b0) ldA = 1'b1;
end
`WaitA: ;
`MsbA: begin
lmA = 1'b1;
if (getA == 1'b0) ldA = 1'b1;
end
`LsbX: begin
lmX = 1'b0;
if (getX == 1'b0) ldX = 1'b1;
end
`WaitX: ;
`MsbX: begin
lmX = 1'b1;
if (getX == 1'b0) ldX = 1'b1;
end
`Init: cntClr = 1'b1;
`Calc: begin
ldP = 1'b1;
ldCo = 1'b1;
ldOv = 1'b1;
sub = lsb3[2];
coefSel = lsb3[2] ? ~lsb3[1:0] : lsb3[1:0];
end
`Sh1: begin
{shX, shP} = 2'b11;
if (~overflow) shSignExtend = 1'b1;
end
`Sh2: {shX, shP, shSignExtend, cntEn} = 4'b1111;
default: ;
endcase
end
endmodule
| 7.158342 |
module Assume4R_Datapath #(
parameter N = 16
) (
input [N/2 - 1:0] inBus,
input lmA,
lmX,
ldA,
ldX,
ldP,
shX,
shP,
clrP,
sub,
putOut,
shSignExtend,
ldCo,
ldOv,
clk,
rst,
input [1:0] coefSel,
output overflow,
output [2:0] lsb3,
output [N-1:0] outBus
);
wire [N-1:0] aRegOut, pRegOut, aRegIn, pRegIn;
wire [N:0] xRegOut, xRegIn;
wire [N-1:0] coef;
wire co, ov, ovOut, serInP, coRegOut;
assign serInP = shSignExtend ? pRegOut[N-1] : coRegOut;
Mux2to1 #(N) lmAmux (
.sel(lmA),
.a0 ({{(N / 2) {1'b0}}, inBus}),
.a1 ({inBus, aRegOut[N/2-1:0]}),
.out(aRegIn)
);
Mux2to1 #(N + 1) lmXmux (
.sel(lmX),
.a0 ({{(N / 2) {1'b0}}, inBus, 1'b0}),
.a1 ({inBus, xRegOut[N/2:0]}),
.out(xRegIn)
);
Reg #(N) aReg (
.ld(ldA),
.ldData(aRegIn),
.clk(clk),
.rst(rst),
.out(aRegOut)
);
DFlipFlop carryAdder (
.ld(ldCo),
.ldData(co),
.clk(clk),
.rst(rst),
.out(coRegOut)
);
DFlipFlop ovFF (
.ld(ldOv),
.ldData(ov),
.clk(clk),
.rst(rst),
.out(ovOut)
);
ShiftReg #(N + 1) xReg (
.ld(ldX),
.ldData(xRegIn),
.sh(shX),
.serIn(pRegOut[0]),
.clr(1'b0),
.clk(clk),
.rst(rst),
.out(xRegOut)
);
ShiftReg #(N) pReg (
.ld(ldP),
.ldData(pRegIn),
.sh(shP),
.serIn(serInP),
.clr(clrP),
.clk(clk),
.rst(rst),
.out(pRegOut)
);
Mux4to1 #(N) coefMux (
.sel(coefSel),
.a00({N{1'b0}}),
.a01(aRegOut),
.a10(aRegOut),
.a11({aRegOut[N-2:0], 1'b0}),
.out(coef)
);
AdderSub #(N) adder (
.sub(sub),
.a (pRegOut),
.b (coef),
.co (co),
.out(pRegIn),
.ov (ov)
);
Mux2to1 #(N) outMux (
.sel(putOut),
.a0 (pRegOut),
.a1 (xRegOut[N:1]),
.out(outBus)
);
assign lsb3 = xRegOut[2:0];
assign overflow = ovOut;
endmodule
| 6.857891 |
module assume_areset_sync_release #(
parameter reset_inverted = 1'b1
) (
input wire clk,
input wire async_reset
);
wire reset_asserted;
generate
if (reset_inverted) assign reset_asserted = !async_reset;
else assign reset_asserted = async_reset;
endgenerate
(* gclk *) reg formal_timestep;
always @(posedge formal_timestep) begin
if ($fell(reset_asserted)) begin
assume ($rose(clk));
end
end
endmodule
| 8.123857 |
module Ass_3_1_v (
input [15:0] input1,
output reg [7:0] seg_out,
output [7:0] seg_en,
output [15:0] output1
);
assign seg_en = ~8'hff;
assign output1 = input1;
always @* begin
casex (input1)
16'bxxxxxxxxxxxxxxx1: seg_out = 8'b01000000; //0
16'bxxxxxxxxxxxxxx10: seg_out = 8'b01111001; //1
16'bxxxxxxxxxxxxx100: seg_out = 8'b00100100; //2
16'bxxxxxxxxxxxx1000: seg_out = 8'b00110000; //3
16'bxxxxxxxxxxx10000: seg_out = 8'b00011001; //4
16'bxxxxxxxxxx100000: seg_out = 8'b00010010; //5
16'bxxxxxxxxx1000000: seg_out = 8'b00000010; //6
16'bxxxxxxxx10000000: seg_out = 8'b01111000; //7
16'bxxxxxxx100000000: seg_out = 8'b00000000; //8
16'bxxxxxx1000000000: seg_out = 8'b00010000; //9
16'bxxxxx10000000000: seg_out = 8'b00001000; //A
16'bxxxx100000000000: seg_out = 8'b00000011; //B
16'bxxx1000000000000: seg_out = 8'b01000110; //C
16'bxx10000000000000: seg_out = 8'b00100001; //D
16'bx100000000000000: seg_out = 8'b00000110; //E
16'b1000000000000000: seg_out = 8'b00001110; //F
default: seg_out = 8'b0000000;
endcase
end
endmodule
| 7.020376 |
module Ass_3_2_v (
input EI,
input A,
B,
C,
D,
output outputa,
outputb,
outputc,
outputd,
output F,
output EO
);
assign {outputa, outputb, outputc, outputd} = {A, B, C, D};
Mux_74151 Mux1 (
.EI(EI),
.S2(A),
.S1(B),
.S0(C),
.D0(1'b1),
.D1(1'b1),
.D2(1'b1),
.D3(1'b1),
.D4(1'b1),
.D5(1'b1),
.D6(1'b0),
.D7(D),
.Y (F),
.EO(EO)
);
endmodule
| 6.893941 |
module Ass_4_3_D (
input clk,
input D,
input reset,
output wire Q,
output wire Qtran
);
reg Qtemp;
always @(posedge clk, posedge reset, negedge reset) begin
if (reset) begin
Qtemp = 0;
end else begin
Qtemp = D;
end
end
assign Q = Qtemp;
assign Qtran = ~Q;
endmodule
| 7.116415 |
module Ass_4_3_ff (
input x_in,
input clk,
input reset,
output [1:0] state
);
wire useless;
Ass_4_3_D test1 (
.D((x_in & ~state[1]) | (~x_in & state[0])),
.clk(clk),
.reset(reset),
.Q(state[0]),
.Qtran(useless)
);
Ass_4_3_D test2 (
.D((x_in & state[0]) | (~x_in & state[1])),
.clk(clk),
.reset(reset),
.Q(state[1]),
.Qtran(useless)
);
endmodule
| 6.5985 |
module AStep_Mux (
data0x,
data1x,
data2x,
data3x,
data4x,
data5x,
data6x,
data7x,
sel,
result
);
input [2:0] data0x;
input [2:0] data1x;
input [2:0] data2x;
input [2:0] data3x;
input [2:0] data4x;
input [2:0] data5x;
input [2:0] data6x;
input [2:0] data7x;
input [2:0] sel;
output [2:0] result;
wire [2:0] sub_wire0;
wire [2:0] sub_wire9 = data7x[2:0];
wire [2:0] sub_wire8 = data5x[2:0];
wire [2:0] sub_wire7 = data4x[2:0];
wire [2:0] sub_wire6 = data3x[2:0];
wire [2:0] sub_wire5 = data2x[2:0];
wire [2:0] sub_wire4 = data1x[2:0];
wire [2:0] sub_wire3 = data0x[2:0];
wire [2:0] result = sub_wire0[2:0];
wire [2:0] sub_wire1 = data6x[2:0];
wire [23:0] sub_wire2 = {
sub_wire9, sub_wire1, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3
};
lpm_mux lpm_mux_component (
.sel(sel),
.data(sub_wire2),
.result(sub_wire0)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam lpm_mux_component.lpm_size = 8, lpm_mux_component.lpm_type = "LPM_MUX",
lpm_mux_component.lpm_width = 3, lpm_mux_component.lpm_widths = 3;
endmodule
| 6.736366 |
modules
`include "Ghost_unit.sv"
// "Ghost_unit.sv" submodules
`include "sin_cos.sv"
`include "sincos_alt_model.v"
`include "Move_Ghost.sv"
`include "Draw_Ghost.sv"
`include "rot_sin_cos.v"
`include "ghost_alt_model.v"
`include "Drawing_priority.sv"
`include "vga_controller.v"
module Screens_dispaly # (
parameter WIDTH=640,
parameter HEIGHT=480,
parameter RGB_LAT = 0
) (
input clk_25,
input [3:0] Red_level,
input [3:0] Green_level,
input [3:0] Blue_level,
output [$clog2(WIDTH )-1:0]pxl_x,
output [$clog2(HEIGHT)-1:0]pxl_y,
output [3:0] Red,
output [3:0] Green,
output [3:0] Blue,
output h_sync,
output v_sync
);
wire [3:0] Red_i;
wire [3:0] Green_i;
wire [3:0] Blue_i;
wire disp_ena;
wire h_sync_d;
wire v_sync_d;
// VGA controller
vga_controller VGA_interface (
.pixel_clk (clk_25),
.reset_n (1),
.h_sync (h_sync_d),
.v_sync (v_sync_d),
.disp_ena (disp_ena),
.column (pxl_x),
.row (pxl_y)
);
// screen out display picker / enable
assign Red_i = (disp_ena == 1'b1) ? Red_level : 4'b0000 ;
assign Green_i = (disp_ena == 1'b1) ? Green_level : 4'b0000 ;
assign Blue_i = (disp_ena == 1'b1) ? Blue_level : 4'b0000 ;
// outputs assigns
assign Red = Red_i;
assign Green = Green_i;
assign Blue = Blue_i;
// delay h/v sync as requested
generate
if (RGB_LAT == 0)
begin
assign h_sync = h_sync_d;
assign v_sync = v_sync_d;
end
else
begin
reg [RGB_LAT-1:0]h_dly;
reg [RGB_LAT-1:0]v_dly;
wire [RGB_LAT:0]tmp_h = {h_sync_d, h_dly};
wire [RGB_LAT:0]tmp_v = {v_sync_d, v_dly};
always @(posedge clk_25)
begin
h_dly <= tmp_h[RGB_LAT:1];
v_dly <= tmp_v[RGB_LAT:1];
end
assign h_sync = h_dly[0];
assign v_sync = v_dly[0];
end
endgenerate
endmodule
| 7.63501 |
module asteroids_8bitworkshop_top (
input clk,
reset,
output hsync,
vsync,
output [31:0] rgb,
input [7:0] keycode,
output keystrobe
);
localparam WIDTH = 640;
localparam HEIGHT = 480;
//=======================================================
// REG/WIRE declarations
//=======================================================
// Screens signals
wire [$clog2(WIDTH )-1:0]pxl_x;
wire [$clog2(HEIGHT)-1:0]pxl_y;
wire [3:0] vga_r_wire;
wire [3:0] vga_g_wire;
wire [3:0] vga_b_wire;
wire [3:0] Red_level;
wire [3:0] Green_level;
wire [3:0] Blue_level;
// Ghost module move and draw signals
wire [3:0] r_ghost;
wire [3:0] g_ghost;
wire [3:0] b_ghost;
wire draw_ghost;
wire [31:0] topLeft_x_ghost;
wire [31:0] topLeft_y_ghost;
// Periphery signals
reg A;
reg B;
reg Select;
reg Start;
reg Right;
reg Left;
reg Up;
reg Down;
reg [11:0] Wheel;
always @(posedge clk) begin
keystrobe <= keycode[7];
A <= 1'b0;
B <= 1'b0;
Select <= 1'b0;
Start <= 1'b0;
Right <= 1'b0;
Left <= 1'b0;
Up <= 1'b0;
Down <= 1'b0;
if (reset) Wheel <= 12'b0;
if (keycode[7]) begin
if ((keycode & 8'h7f) == "A") A <= 1'b1;
if ((keycode & 8'h7f) == "B") B <= 1'b1;
if ((keycode & 8'h7f) == 45) // INSERT
Select <= 1'b1;
if ((keycode & 8'h7f) == 46) // DELETE
Start <= 1'b1;
if ((keycode & 8'h7f) == 39) Right <= 1'b1;
if ((keycode & 8'h7f) == 37) Left <= 1'b1;
if ((keycode & 8'h7f) == 38) Up <= 1'b1;
if ((keycode & 8'h7f) == 40) Down <= 1'b1;
if (((keycode & 8'h7f) >= 48) && ((keycode & 8'h7f) <= 57)) Wheel <= keycode[3:0] * 227;
end
end
// Screens Assigns
// convert 12 bit rgb to 32 bit rgba
assign rgb = {8'b1, vga_r_wire, 4'b0000, vga_g_wire, 4'b0000, vga_b_wire, 4'b0000};
// VGA controller (LCD removed)
Screens_dispaly #(
.WIDTH (WIDTH),
.HEIGHT (HEIGHT),
.RGB_LAT(2)
) Screen_control (
.clk_25(clk),
.Red_level(Red_level),
.Green_level(Green_level),
.Blue_level(Blue_level),
.pxl_x(pxl_x),
.pxl_y(pxl_y),
.Red(vga_r_wire),
.Green(vga_g_wire),
.Blue(vga_b_wire),
.h_sync(hsync),
.v_sync(vsync)
);
// Priority mux for the RGB
Drawing_priority drawing_mux (
.clk(clk),
.resetN(~Select),
.RGB_1(12'h000),
.draw_1(1'b0),
.RGB_2({r_ghost, g_ghost, b_ghost}),
.draw_2(draw_ghost),
.RGB_bg(12'hFFF),
.Red_level(Red_level),
.Green_level(Green_level),
.Blue_level(Blue_level)
);
// Ghost unit
Ghost_unit #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT)
) Ghost_unit_inst (
.clk(clk),
.resetN(~Select),
.collision(1'b0 && draw_ghost),
.B(B),
.pxl_x(pxl_x),
.pxl_y(pxl_y),
.wheel(Wheel),
.Red(r_ghost),
.Green(g_ghost),
.Blue(b_ghost),
.Draw(draw_ghost)
);
endmodule
| 8.725301 |
module asu (
x,
y,
mode,
carry,
out
);
input [7:0] x, y;
input mode;
output carry;
output [7:0] out;
wire [7:0] w_1, w_2;
adder add0 (
x,
y,
w_0,
w_1
);
barrel_shifter shift0 (
x,
y[2:0],
w_2
);
assign out = mode ? w_1 : w_2;
assign carry = mode ? w_0 : 1'b0;
endmodule
| 7.348659 |
module asu_gate (
x,
y,
mode,
carry,
out
);
input [7:0] x, y;
input mode;
output carry;
output [7:0] out;
wire [7:0] w_1, w_2;
// ks_adder_gate_8 add0 (x, y, w_0, w_1);
adder_gate add0 (
x,
y,
w_0,
w_1
);
barrel_shifter_gate shift0 (
x,
y[2:0],
w_2
);
assign #(`MODE_MUX_DELAY) out = mode ? w_1 : w_2;
assign #(`MODE_MUX_DELAY) carry = mode ? w_0 : 1'b0;
endmodule
| 8.118231 |
module asu_gate_test;
parameter pattern_num = 11;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg mode;
reg clk;
reg stop;
integer i, num, error;
reg [8:0] ans_out;
reg [8:0] mux_out;
reg [1:0] data_base0[0:100];
reg [7:0] data_base1[0:100];
reg [8:0] data_base2[0:100];
asu_gate t (
x,
y,
mode,
carry,
out
);
initial begin
$readmemh(`SELFILE, data_base0);
$readmemh(`INFILE, data_base1);
$readmemh(`OUTFILE, data_base2);
clk = 1'b1;
error = 0;
stop = 0;
i = 0;
end
always begin
#(`CYCLE * 0.5) clk = ~clk;
end
initial begin
mode = data_base0[0];
x[7:0] = data_base1[0];
y[7:0] = data_base1[1];
for (num = 2; num < (pattern_num * 2); num = num + 2) begin
@(posedge clk) begin
mode = data_base0[num/2];
x[7:0] = data_base1[num];
y[7:0] = data_base1[num+1];
end
end
end
always @(posedge clk) begin
i <= i + 1;
if (i >= pattern_num) stop <= 1;
end
always @(posedge clk) begin
mux_out <= {carry, out};
ans_out <= data_base2[i];
if (mux_out !== ans_out) begin
error <= error + 1;
$display("An ERROR occurs at no.%d pattern: Output %b != answer %b.\n", i, mux_out, ans_out);
end
end
initial begin
@(posedge stop) begin
if (error == 0) begin
$display("==========================================\n");
$display("====== Congratulation! You Pass! =======\n");
$display("==========================================\n");
end else begin
$display("===============================\n");
$display("There are %d errors.", error);
$display("===============================\n");
end
$finish;
end
end
/*================Dumping Waveform files====================*/
initial begin
$dumpfile("mux.vcd");
$dumpvars;
/* $fsdbDumpfile("mux.fsdb");
$fsdbDumpvars; */
end
endmodule
| 6.692072 |
module asyclr (
input en,
input clk,
input clr,
input in_data,
output reg out_asy
);
always @(posedge clk or posedge clr) begin
if (clr)
if (en) out_asy <= 0;
else out_asy <= out_asy;
else begin
if (en) out_asy <= in_data;
else out_asy <= out_asy;
end
end
endmodule
| 7.123689 |
module TT (
q,
notq,
t,
clk,
reset
);
output reg q = 0;
output notq;
input t, clk, reset;
assign notq = ~q;
always @(posedge clk, negedge reset) begin
if (~reset) // Reset to zero
q <= 0;
else if (t) // Flip
q <= ~q;
end
endmodule
| 7.108227 |
module TT (
q,
notq,
t,
clk,
reset
);
output reg q = 0;
output notq;
input t, clk, reset;
assign notq = ~q;
always @(posedge clk, negedge reset) begin
if (~reset) // Reset to zero
q <= 0;
else if (t) // Flip
q <= ~q;
end
endmodule
| 7.108227 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk_0;
reg clk_1;
reg rce;
reg [`ADDR_WIDTH1-1:0] ra;
wire [`DATA_WIDTH1-1:0] rq;
reg wce;
reg [`ADDR_WIDTH0-1:0] wa;
reg [`DATA_WIDTH0-1:0] wd;
initial clk_0 = 0;
initial clk_1 = 0;
initial ra = 0;
initial wa = 0;
initial wd = 0;
initial rce = 0;
initial wce = 0;
initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
initial begin
#(PERIOD / 4.0);
forever #(PERIOD / 2.0) clk_1 = ~clk_1;
end
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
integer b;
reg done_0;
initial done_0 = 1'b0;
wire done_sim = done_0;
reg [`DATA_WIDTH1-1:0] expected_0;
reg read_test_0;
initial read_test_0 = 0;
wire error_0 = (read_test_0) ? (rq !== expected_0) : 0;
integer error_0_cnt = 0;
always @(posedge clk_1) begin
if (error_0) error_0_cnt <= error_0_cnt + 1'b1;
end
case (
`STRINGIFY(`TOP)
)
"spram_9x2048_18x1024": begin
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR) begin
@(negedge clk_0) begin
wa = a[`ADDR_WIDTH0-1:0];
wd = a[9:1];
wce = 1;
end
@(posedge clk_0) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test_0 = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(negedge clk_1) begin
ra = a;
rce = 1;
end
@(posedge clk_1) begin
expected_0 <= {a[8], a[8], a[7:0], a[7:0]};
#(PERIOD / 10) rce = 0;
if (rq !== expected_0) begin
$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0,
a);
end else begin
$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
end
end
end
done_0 = 1'b1;
a = 0;
end
end
"spram_18x1024_9x2048": begin
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR) begin
@(negedge clk_0) begin
wa = a[`ADDR_WIDTH0-1:0];
wd = {a[8], a[8], a[7:0], a[7:0]};
wce = 1;
end
@(posedge clk_0) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test_0 = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(negedge clk_1) begin
ra = a;
rce = 1;
end
@(posedge clk_1) begin
expected_0 <= {a[9:1]};
#(PERIOD / 10) rce = 0;
if (rq !== expected_0) begin
$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0,
a);
end else begin
$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
end
end
end
done_0 = 1'b1;
a = 0;
end
end
endcase
// Scan for simulation finish
always @(posedge clk_1) begin
if (done_sim) $finish_and_return((error_0_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"spram_9x2048_18x1024": begin
spram_9x2048_18x1024 #() bram (
.clock0(clk_0),
.clock1(clk_1),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_18x1024_9x2048": begin
spram_18x1024_9x2048 #() bram (
.clock0(clk_0),
.clock1(clk_1),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
endcase
endmodule
| 7.277485 |
module spram_9x4096_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(1'b1),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.729965 |
module spram_18x2048_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(2'b11),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.524103 |
module spram_18x2048_9x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 9;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(2'b11),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.524103 |
module spram_36x1024_18x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 36;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 4;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(4'b1111),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.683816 |
module buffer_hdl_core #(
parameter WIDTHA = 8,
parameter SIZEA = 512,
parameter ADDRWIDTHA = 9,
parameter WIDTHB = 16,
parameter SIZEB = 256,
parameter ADDRWIDTHB = 8
) (
input wire buffer_clk_a,
input wire buffer_clk_b,
input wire buffer_we_a,
input wire buffer_we_b,
input wire [ADDRWIDTHA-1:0] buffer_addr_a,
input wire [ADDRWIDTHB-1:0] buffer_addr_b,
input wire [ WIDTHA-1:0] buffer_din_a,
input wire [ WIDTHB-1:0] buffer_din_b,
output reg [ WIDTHA-1:0] buffer_dout_a = 0,
output reg [ WIDTHB-1:0] buffer_dout_b = 0
);
`define max(a, b) {(a) > (b) ? (a) : (b)}
`define min(a, b) {(a) < (b) ? (a) : (b)}
wire enA;
wire enB;
assign enA = 1;
assign enB = 1;
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2) log2 = value;
else begin
shifted = value - 1;
for (res = 0; shifted > 0; res = res + 1) shifted = shifted >> 1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
// An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
// array of array reg. Its aspect ratio corresponds to the port with the
// lower data width (larger depth)
reg [minWIDTH-1:0] buffer_core[0:maxSIZE-1];
genvar i;
// Describe the port with the smaller data width exactly as you are used to
// for symmetric block RAMs
always @(posedge buffer_clk_b) begin : portB
if (enB)
if (buffer_we_b) begin
buffer_core[buffer_addr_b] <= buffer_din_b;
buffer_dout_b <= buffer_din_b;
end else buffer_dout_b <= buffer_core[buffer_addr_b];
end
// A generate-for is used to describe the port with the larger data width in a
// generic and compact way
`define BIGEND 1
`ifndef BIGEND
`define LITTLEEND 1
`endif
generate
for (i = 0; i < RATIO; i = i + 1) begin : portA
`ifdef LITTLEEND
localparam [log2RATIO-1:0] lsbaddr = i;
`elsif BIGEND
localparam [log2RATIO-1:0] lsbaddr = RATIO - i - 1;
`endif
always @(posedge buffer_clk_a)
if (enA) begin
if (buffer_we_a) begin
buffer_core[{buffer_addr_a, lsbaddr}] <= buffer_din_a[(i+1)*minWIDTH-1:i*minWIDTH];
buffer_dout_a[(i+1)*minWIDTH-1:i*minWIDTH] <= buffer_din_a[(i+1)*minWIDTH-1:i*minWIDTH];
end else
buffer_dout_a[(i+1)*minWIDTH-1:i*minWIDTH] <= buffer_core[{buffer_addr_a, lsbaddr}];
end
end
endgenerate
endmodule
| 9.410364 |
module asymm_bram_min_wr #(
parameter minWIDTH = 8,
parameter RATIO = 4,
parameter maxDEPTH = 512,
parameter INIT = 0
) (
input wr_clk,
input [minWIDTH-1:0] din,
input wr_en,
input [`MSB(maxDEPTH*RATIO-1) : 0] wr_addr,
input rd_clk,
output reg [minWIDTH*RATIO-1:0] dout = INIT,
input rd_en,
input [`MSB(maxDEPTH-1) : 0] rd_addr
);
localparam log2RATIO = `MSB(RATIO);
(* RAM_STYLE="BLOCK" *)
reg [minWIDTH-1:0] mem[0:RATIO*maxDEPTH-1];
genvar i;
// Describe the port with the smaller data width exactly as you are used to
// for symmetric block RAMs
always @(posedge wr_clk) if (wr_en) mem[wr_addr] <= din;
// A generate-for is used to describe the port with the larger data width in a
// generic and compact way
generate
for (i = 0; i < RATIO; i = i + 1) begin : portB
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge rd_clk)
if (rd_en)
dout[(i+1)*minWIDTH-1:i*minWIDTH] <= mem[{rd_addr, lsbaddr}];
end
endgenerate
endmodule
| 8.706965 |
module asymm_bram_min_rd #(
parameter minWIDTH = 8,
parameter RATIO = 4,
parameter maxDEPTH = 512,
parameter INIT = 0
) (
input wr_clk,
input [minWIDTH*RATIO-1:0] din,
input wr_en,
input [`MSB(maxDEPTH-1) : 0] wr_addr,
input rd_clk,
output reg [minWIDTH-1:0] dout = INIT,
input rd_en,
input [`MSB(maxDEPTH*RATIO-1) : 0] rd_addr
);
localparam log2RATIO = `MSB(RATIO);
(* RAM_STYLE="BLOCK" *)
reg [minWIDTH-1:0] mem[0:RATIO*maxDEPTH-1];
genvar i;
// Describe the port with the smaller data width exactly as you are used to
// for symmetric block RAMs
always @(posedge rd_clk) if (rd_en) dout <= mem[rd_addr];
// A generate-for is used to describe the port with the larger data width in a
// generic and compact way
generate
for (i = 0; i < RATIO; i = i + 1) begin : portB
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge wr_clk)
if (wr_en)
mem[{wr_addr, lsbaddr}] <= din[(i+1)*minWIDTH-1:i*minWIDTH];
end
endgenerate
endmodule
| 8.706965 |
module asym_ram_sdp_read_wider (
clkA,
clkB,
enaA,
weA,
enaB,
addrA,
addrB,
diA,
doB
);
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a, b) {(a) > (b) ? (a) : (b)}
`define min(a, b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2) log2 = value;
else begin
shifted = value - 1;
for (res = 0; shifted > 0; res = res + 1) shifted = shifted >> 1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM[0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkA) begin
if (enaA) begin
if (weA) RAM[addrA] <= diA;
end
end
always @(posedge clkB) begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (enaB) begin
for (i = 0; i < RATIO; i = i + 1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1-:minWIDTH] <= RAM[{addrB, lsbaddr}];
end
end
end
assign doB = readB;
endmodule
| 7.681152 |
module asym_ram_sdp_write_wider (
clkA,
clkB,
weA,
enaA,
enaB,
addrA,
addrB,
diA,
doB
);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
//parameter WIDTHA = 8;
parameter WIDTHA = 4;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a, b) {(a) > (b) ? (a) : (b)}
`define min(a, b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2) log2 = value;
else begin
shifted = value - 1;
for (res = 0; shifted > 0; res = res + 1) shifted = shifted >> 1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM[0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
readB <= RAM[addrB];
end
end
assign doB = readB;
always @(posedge clkA) begin : ramwrite
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i = 0; i < RATIO; i = i + 1) begin : write1
lsbaddr = i;
if (enaA) begin
if (weA) RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1-:minWIDTH];
end
end
end
endmodule
| 7.681152 |
module asym_ram_tdp_read_first (
clkA,
clkB,
enaA,
weA,
enaB,
weB,
addrA,
addrB,
diA,
doA,
diB,
doB
);
parameter WIDTHB = 4;
parameter SIZEB = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA = 16;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a, b) {(a) > (b) ? (a) : (b)}
`define min(a, b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2) log2 = value;
else begin
shifted = value - 1;
for (res = 0; shifted > 0; res = res + 1) shifted = shifted >> 1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM[0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
readB <= RAM[addrB];
if (weB) RAM[addrB] <= diB;
end
end
always @(posedge clkA) begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i = 0; i < RATIO; i = i + 1) begin
lsbaddr = i;
if (enaA) begin
readA[(i+1)*minWIDTH-1-:minWIDTH] <= RAM[{addrA, lsbaddr}];
if (weA) RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1-:minWIDTH];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
| 8.166984 |
module asym_ram_tdp_write_first (
clkA,
clkB,
enaA,
weA,
enaB,
weB,
addrA,
addrB,
diA,
doA,
diB,
doB
);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 32;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
parameter WIDTHA = 4;
//parameter SIZEA = 256;
parameter SIZEA = 32;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a, b) {(a) > (b) ? (a) : (b)}
`define min(a, b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2) log2 = value;
else begin
shifted = value - 1;
for (res = 0; shifted > 0; res = res + 1) shifted = shifted >> 1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM[0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
if (weB) RAM[addrB] = diB;
readB = RAM[addrB];
end
end
always @(posedge clkA) begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i = 0; i < RATIO; i = i + 1) begin
lsbaddr = i;
if (enaA) begin
if (weA) RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1-:minWIDTH];
readA[(i+1)*minWIDTH-1-:minWIDTH] = RAM[{addrA, lsbaddr}];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
| 8.166984 |
module to be used in designs.
//
// Notes:
// - w_* means something is in the "write clock domain"
// - r_* means something is in the "read clock domain"
// - Single memory element is DATA_SIZE bits wide
// - Memory is 2^ADDR_SIZE elements deep
//
// Date: December 11, 2021
// Author: Shawn Hymel
// License: 0BSD
// Asynchronous FIFO module
module async_fifo #(
// Parameters
parameter DATA_SIZE = 8, // Number of data bits
parameter ADDR_SIZE = 4 // Number of bits for address
) (
// Inputs
input [DATA_SIZE-1:0] w_data, // Data to be written to FIFO
input w_en, // Write data and increment addr.
input w_clk, // Write domain clock
input w_rst, // Write domain reset
input r_en, // Read data and increment addr.
input r_clk, // Read domain clock
input r_rst, // Read domain reset
// Outputs
output w_full, // Flag: 1 if FIFO is full
output reg [DATA_SIZE-1:0] r_data, // Data to be read from FIFO
output r_empty // Flag: 1 if FIFO is empty
);
// Constants
localparam FIFO_DEPTH = (1 << ADDR_SIZE);
// Internal signals
wire [ADDR_SIZE-1:0] w_addr;
wire [ADDR_SIZE:0] w_gray;
wire [ADDR_SIZE-1:0] r_addr;
wire [ADDR_SIZE:0] r_gray;
// Internal storage elements
reg [ADDR_SIZE:0] w_syn_r_gray;
reg [ADDR_SIZE:0] w_syn_r_gray_pipe;
reg [ADDR_SIZE:0] r_syn_w_gray;
reg [ADDR_SIZE:0] r_syn_w_gray_pipe;
// Declare memory
reg [DATA_SIZE-1:0] mem [0:FIFO_DEPTH-1];
//--------------------------------------------------------------------------
// Dual-port memory (should be inferred as block RAM)
// Write data logic for dual-port memory (separate write clock)
// Do not write if FIFO is full!
always @ (posedge w_clk) begin
if (w_en & ~w_full) begin
mem[w_addr] <= w_data;
end
end
// Read data logic for dual-port memory (separate read clock)
// Do not read if FIFO is empty!
always @ (posedge r_clk) begin
if (r_en & ~r_empty) begin
r_data <= mem[r_addr];
end
end
//--------------------------------------------------------------------------
// Synchronizer logic
// Pass read-domain Gray code pointer to write domain
always @ (posedge w_clk or posedge w_rst) begin
if (w_rst == 1'b1) begin
w_syn_r_gray_pipe <= 0;
w_syn_r_gray <= 0;
end else begin
w_syn_r_gray_pipe <= r_gray;
w_syn_r_gray <= w_syn_r_gray_pipe;
end
end
// Pass write-domain Gray code pointer to read domain
always @ (posedge r_clk or posedge r_rst) begin
if (r_rst == 1'b1) begin
r_syn_w_gray_pipe <= 0;
r_syn_w_gray <= 0;
end else begin
r_syn_w_gray_pipe <= w_gray;
r_syn_w_gray <= r_syn_w_gray_pipe;
end
end
//--------------------------------------------------------------------------
// Instantiate incrementer and full/empty checker modules
// Write address increment and full check module
w_ptr_full #(.ADDR_SIZE(ADDR_SIZE)) w_ptr_full (
.w_syn_r_gray(w_syn_r_gray),
.w_inc(w_en),
.w_clk(w_clk),
.w_rst(w_rst),
.w_addr(w_addr),
.w_gray(w_gray),
.w_full(w_full)
);
// Read address increment and empty check module
r_ptr_empty #(.ADDR_SIZE(ADDR_SIZE)) r_ptr_empty (
.r_syn_w_gray(r_syn_w_gray),
.r_inc(r_en),
.r_clk(r_clk),
.r_rst(r_rst),
.r_addr(r_addr),
.r_gray(r_gray),
.r_empty(r_empty)
);
endmodule
| 7.785841 |
module async_fifo_tb ();
// Settings
localparam DATA_SIZE = 8;
localparam ADDR_SIZE = 4;
// Internal signals
wire [DATA_SIZE-1:0] r_data;
wire r_empty;
wire r_full;
// Internal storage elements
reg r_en = 0;
reg r_clk = 0;
reg r_rst = 0;
reg [DATA_SIZE-1:0] w_data;
reg w_en = 0;
reg w_clk = 0;
reg w_rst = 0;
// Variables
integer i;
// Simulation time: 10000 * 1 us = 10 ms
localparam DURATION = 10000;
// Generate read clock signal (about 12 MHz)
always begin
#0.04167
r_clk = ~r_clk;
end
// Generate write clock signal (5 MHz)
always begin
#0.1
w_clk = ~w_clk;
end
// Instantiate FIFO
async_fifo #(
.DATA_SIZE(DATA_SIZE),
.ADDR_SIZE(ADDR_SIZE)
) uut (
.w_data(w_data),
.w_en(w_en),
.w_clk(w_clk),
.w_rst(w_rst),
.r_en(r_en),
.r_clk(r_clk),
.r_rst(r_rst),
.w_full(w_full),
.r_data(r_data),
.r_empty(r_empty)
);
// Test control: write and read data to/from FIFO
initial begin
// Pulse resets high to initialize memory and counters
#0.1
w_rst = 1;
r_rst = 1;
#0.01
w_rst = 0;
r_rst = 0;
// Write some data to the FIFO
for (i = 0; i < 4; i = i + 1) begin
#0.2
w_data = i;
w_en = 1'b1;
end
#0.2
w_en = 1'b0;
// Try to read more than what's in the FIFO
for (i = 0; i < 6; i = i + 1) begin
#0.08334
r_en = 1'b1;
end
#0.08334
r_en = 1'b0;
// Fill up FIFO (and then some)
for (i = 0; i < 18; i = i + 1) begin
#0.2
w_en = 1'b1;
w_data = i;
end
#0.2
w_en = 1'b0;
// Read everything in the FIFO (and then some)
for (i = 0; i < 18; i = i + 1) begin
#0.08334
r_en = 1'b1;
end
#0.08334
r_en = 1'b0;
end
// Run simulation
initial begin
// Create simulation output file
$dumpfile("async-fifo_tb.vcd");
$dumpvars(0, async_fifo_tb);
// Wait for given amount of time for simulation to complete
#(DURATION)
// Notify and end simulation
$display(
"Finished!"
);
$finish;
end
endmodule
| 6.523155 |
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 8; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
| 7.236243 |
module async_transmitter (
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
/*
* Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
* TxD_data is latched so that it doesn't have to stay valid while it is being sent
*/
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 9600;
generate
if (ClkFrequency < Baud * 8 && (ClkFrequency % Baud != 0))
ASSERTION_ERROR PARAMETER_OUT_OF_RANGE ("Frequency incompatible with requested Baud rate");
endgenerate
/* ============================== */
`ifdef SIMULATION
/* output one bit per clock cycle */
wire BitTick = 1'b1;
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen (
.clk(clk),
.enable(TxD_busy),
.tick(BitTick)
);
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state == 0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk) begin
if (TxD_ready & TxD_start) TxD_shift <= TxD_data;
else if (TxD_state[3] & BitTick) TxD_shift <= (TxD_shift >> 1);
case (TxD_state)
4'b0000: if (TxD_start) TxD_state <= 4'b0100;
4'b0100: if (BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if (BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if (BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if (BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if (BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if (BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if (BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if (BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if (BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if (BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if (BitTick) TxD_state <= 4'b0000; // stop2
default: if (BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state < 4) | (TxD_state[3] & TxD_shift[0]);
endmodule
| 7.250028 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
module async_transmitter(
input wire clk,
input wire TxD_start,
input wire [7:0] TxD_data,
output wire TxD,
output wire TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
// generate
// if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
// endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0000; // stop1
//4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
| 6.83375 |
module BaudTickGen (
input wire clk,
enable,
output wire tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module async2sync (
input async,
input clk,
output reg clk_en = 0
);
reg async_r;
always @(posedge clk or posedge async)
if (async) async_r <= 1'b1;
else if (done || !init_done) async_r <= 0;
reg done = 0;
reg init_done = 0;
always @(posedge clk) begin
if (!async && !init_done) init_done <= 1;
if (async_r && init_done)
if (!clk_en && !done) begin
clk_en <= 1;
done <= 1;
end else clk_en <= 0;
else done <= 0;
end
endmodule
| 6.632058 |
module async2syncRst (
input clk,
input rst_async_n,
output rst_sync
);
reg rst_s1, rst_s2;
always @(posedge clk, negedge rst_async_n) begin
if (!rst_async_n) begin
rst_s1 <= 1'b0;
rst_s2 <= 1'b0;
end else begin
rst_s1 <= 1'b1;
rst_s2 <= rst_s1;
end
end
// assign rst_sync = ~rst_s2;
assign rst_sync = ~rst_async_n;
endmodule
| 6.734188 |
module sync_async (
in1,
in2,
out1,
out2,
reset,
clock
);
input in1;
input in2;
output out1;
output out2;
input reset;
input clock;
reg out1, out2;
// Synchronous : Depend on clock.
always @(posedge clock) begin
if (reset) out1 = 0;
else out1 = in1;
end
// Asynchronous : Independent of clock.
always @(posedge clock or reset) begin
if (reset) out2 = 0;
else out2 = in2;
end
endmodule
| 6.510019 |
module master (
input ready,
w,
output [15:0] address,
inout [15:0] data
);
reg [15:0] ar, dr;
assign address = ar;
assign data = (w) ? dr : 16'hzzzz;
always @(*) begin
if (!w) dr = #1 data;
end
endmodule
| 7.034859 |
module
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wire [6:0] HEX4,
output wire [6:0] HEX5,
output wire [9:0] LEDR, // LEDs
output wire [7:0] x, // VGA pixel coordinates
output wire [6:0] y,
output wire [2:0] colour, // VGA pixel colour (0-7)
output wire plot, // Pixel drawn when this is pulsed
output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
);
async_counter_top u1(SW[8], SW[9], SW[7], LEDR[2:0]);
endmodule
| 9.001229 |
module async_counter_top (
enable,
clock,
resetp,
q
);
input enable, clock, resetp;
output [2:0] q;
wire [2:0] c;
t_flipflop v1 (
enable,
resetp,
clock,
c[0]
);
t_flipflop v2 (
enable,
resetp,
~c[0],
c[1]
);
t_flipflop v3 (
enable,
resetp,
~c[1],
c[2]
);
assign q = c;
endmodule
| 6.77988 |
module name is : async_fifo
module <:$mod_name:>
(
// FIFO
parameter data_width = <:$dwd:>,// FIFO
parameter data_depth = <:$depth:>,// FIFO
parameter address_width = <:$awd:>, // ַȣΪ2^nFIFOҪĶ/дָλΪ(n+1)λһλΪ۷־λ
input rst_wr,
input wr_clk,
input wr_en,
input [data_width-1:0] wr_din,
input rst_rd,
input rd_clk,
input rd_en,
output reg [data_width-1:0] rd_dout,
output empty,
output full
);
reg [address_width:0] wr_addr_p;//дַָ
reg [address_width:0] rd_addr_p;//ַָ
wire [address_width-1:0] wr_addr;//дRAM ַ
wire [address_width-1:0] rd_addr;//RAM ַ
wire [address_width:0] wr_addr_gray;//дַָӦĸ
reg [address_width:0] wr_addr_gray_d1;
reg [address_width:0] wr_addr_gray_d2;//дַָͬʱӦĸ
wire [address_width:0] rd_addr_gray;//ַָӦĸ
reg [address_width:0] rd_addr_gray_d1;
reg [address_width:0] rd_addr_gray_d2;//ַָͬдʱӦĸ";
<:
if ($noram == 1) {
$OUT .= " reg [data_width-1:0] FIFO_DFF_ARRAY [data_depth-1:0];// DFF ArrayڴFIFO";
}
:>
// дָ仯
always@(posedge write_clk or negedge rst_n)begin
if(!rst_n)
wr_addr_p <='h0;
else if(write_en && (~full))// дʹҷ
wr_addr_p <= wr_addr_p + 1;
else
wr_addr_p <= wr_addr_p;
end
assign wr_addr = wr_addr_p[address_width-1:0];// дRAMַڶдָĵaddress_widthλ
// д
always@(posedge write_clk) begin
if(write_en && (~full))// дʹҷ
FIFO_RAM[wr_addr] <= data_in;
else
FIFO_RAM[wr_addr] <= FIFO_RAM[wr_addr];
end
// ָ仯
always@(posedge read_clk or negedge rst_n)begin
if(!rst_n)
rd_addr_p <='h0;
else if(read_en && (~empty))// ʹҷǿ
rd_addr_p <= rd_addr_p + 1;
else
rd_addr_p <= rd_addr_p;
end
assign rd_addr = rd_addr_p[address_width-1:0];// дRAMַڶдָĵaddress_widthλ
<:
if ($noram == 1) {
$OUT .= "
//
always@(posedge read_clk)begin
if(read_en && (~empty))// ʹҷǿ
data_out <= FIFO_DFF_ARRAY[rd_addr];
else
data_out <='h0;
end
";
} else {
$OUT .= "
// You need to replace your sram for you project a/o foundary
mem_foundary_wrap mem_inst (
.wclk(wr_clk),
.rclk(rd_clk),
.wen(wr_en),
.ren(rd_en),
.waddr(wr_ptr),
.raddr(rd_ptr),
.din(wr_din),
.dout(rd_dout)
);
";
}
:>
// дַָתΪ
assign wr_addr_gray = (wr_addr_p >> 1) ^ wr_addr_p;
assign rd_addr_gray = (rd_addr_p >> 1) ^ rd_addr_p;
//ָͬ->дʱ
always@(posedge write_clk)begin//
rd_addr_gray_d1 <= rd_addr_gray;
rd_addr_gray_d2 <= rd_addr_gray_d1;
end
// дָ->ʱ
always@(posedge read_clk )begin//
wr_addr_gray_d1 <= wr_addr_gray;
wr_addr_gray_d2 <= wr_addr_gray_d1;
end
//־ж
assign full = (wr_addr_gray == {~(rd_addr_gray_d2[address_width:address_width-1]),rd_addr_gray_d2[address_width-2:0]}) ;//λͬλͬ
assign empty = (rd_addr_gray == wr_addr_gray_d2 );// дʱÿһλͬ
endmodule
| 7.351375 |
module AsyncFifo #(
parameter DEPTH = 1,
parameter WIDTH = 1,
parameter ALMOST = 1
) ( /*AUTOARG*/
// Outputs
rd_dat,
empty,
full,
// Inputs
iclk,
oclk,
iclk_rst_b,
oclk_rst_b,
wr_en,
rd_en,
wr_dat
);
`include "clog2.vh"
`define ADDR_WIDTH (clog2(DEPTH)-1)
`define FULL_G_INIT (DEPTH ^ (DEPTH >> 1))
input iclk;
input oclk;
input iclk_rst_b;
input oclk_rst_b;
input wr_en;
input rd_en;
input [WIDTH-1:0] wr_dat;
output reg [WIDTH-1:0] rd_dat;
output wire empty;
output wire full;
reg [WIDTH-1:0] fifo[DEPTH-1:0];
reg [`ADDR_WIDTH:0] wpos_iclk = 0;
wire [`ADDR_WIDTH:0] wpos_iclk_next = wr_en ? (wpos_iclk + 1) : wpos_iclk;
reg [`ADDR_WIDTH:0] rpos_oclk = 0;
wire [`ADDR_WIDTH:0] rpos_oclk_next = rd_en ? (rpos_oclk + 1) : rpos_oclk;
reg [`ADDR_WIDTH:0] wpos_empty_g_iclk = 0;
reg [`ADDR_WIDTH:0] wpos_empty_g_oclk_1 = 0;
reg [`ADDR_WIDTH:0] wpos_empty_g_oclk_2 = 0;
wire [`ADDR_WIDTH:0] rpos_empty_g_oclk = rpos_oclk ^ (rpos_oclk >> 1);
/* verilator lint_off WIDTH */
wire [`ADDR_WIDTH:0] rpos_full_oclk = rpos_oclk_next + DEPTH;
reg [`ADDR_WIDTH:0] rpos_full_g_oclk = `FULL_G_INIT;
reg [`ADDR_WIDTH:0] rpos_full_g_iclk_1 = `FULL_G_INIT;
reg [`ADDR_WIDTH:0] rpos_full_g_iclk_2 = `FULL_G_INIT;
/* verilator lint_on WIDTH */
wire [`ADDR_WIDTH:0] wpos_full_g_iclk = wpos_iclk ^ (wpos_iclk >> 1);
/* There is no issue here with empty showing up too late, because
* only the write pointer is delayed; the read pointer remains
* synchronous with the read operation. So, 'empty' might return
* empty for too long, but never for too short.
*/
assign empty = (rpos_empty_g_oclk == wpos_empty_g_oclk_2);
/* Same deal the other way around for full. */
assign full = (rpos_full_g_iclk_2 == wpos_full_g_iclk);
always @(posedge iclk or negedge iclk_rst_b) begin
if (~iclk_rst_b) begin
wpos_iclk <= 0;
wpos_empty_g_iclk <= 0;
/* verilator lint_off WIDTH */
rpos_full_g_iclk_1 <= `FULL_G_INIT;
rpos_full_g_iclk_2 <= `FULL_G_INIT;
/* verilator lint_on WIDTH */
end else begin
if (wr_en) begin
fifo[wpos_iclk[`ADDR_WIDTH-1:0]] <= wr_dat;
end
wpos_iclk <= wpos_iclk_next;
wpos_empty_g_iclk <= wpos_iclk_next ^ (wpos_iclk_next >> 1);
rpos_full_g_iclk_1 <= rpos_full_g_oclk;
rpos_full_g_iclk_2 <= rpos_full_g_iclk_1;
end
end
always @(posedge oclk or negedge oclk_rst_b) begin
if (~oclk_rst_b) begin
rpos_oclk <= 0;
/* verilator lint_off WIDTH */
rpos_full_g_oclk <= `FULL_G_INIT;
/* verilator lint_on WIDTH */
wpos_empty_g_oclk_1 <= 0;
wpos_empty_g_oclk_2 <= 0;
end else begin
if (rd_en) begin
rd_dat <= fifo[rpos_oclk[`ADDR_WIDTH-1:0]];
end
rpos_oclk <= rpos_oclk_next;
rpos_full_g_oclk <= rpos_full_oclk ^ (rpos_full_oclk >> 1);
wpos_empty_g_oclk_1 <= wpos_empty_g_iclk;
wpos_empty_g_oclk_2 <= wpos_empty_g_oclk_1;
end
end
endmodule
| 7.501757 |
module ASYNCFIFOGA #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
input wrst_n, //async reset
input wclk,
input winc, //write enable
input [DSIZE-1:0] wdata,
output wfull,
input rrst_n,
input rclk,
input rinc, //read enable, rdata will change for next reading
output [DSIZE-1:0] rdata, //always output the valid data
output rempty
);
wire [ASIZE-1:0] waddr;
wire [ASIZE-1:0] raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
wire [DSIZE-1:0] rdata_int;
sync_r2w_ga #(ASIZE) sync_r2w (
.wq2_rptr(wq2_rptr),
.rptr(rptr),
.wclk(wclk),
.wrst_n(wrst_n)
);
sync_w2r_ga #(ASIZE) sync_w2r (
.rq2_wptr(rq2_wptr),
.wptr(wptr),
.rclk(rclk),
.rrst_n(rrst_n)
);
fifomem_ga #(DSIZE, ASIZE) fifomem (
.rdata (rdata_int),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken(winc),
.wfull (wfull),
.wclk (wclk)
);
rptr_empty_ga #(ASIZE) rptr_empty (
.rempty(rempty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n)
);
wptr_full_ga #(ASIZE) wptr_full (
.wfull(wfull),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n)
);
//20170627-twu: make read data '0' when fifo is not reading
// to avoid the metastable caused to the read side by writing empty fifo
assign rdata = rinc ? rdata_int : {DSIZE{1'b0}};
endmodule
| 7.497331 |
module fifomem_ga #(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4) // Number of mem address bits
(
output [DATASIZE-1:0] rdata ,
input [DATASIZE-1:0] wdata ,
input [ADDRSIZE-1:0] waddr ,
input [ADDRSIZE-1:0] raddr ,
input wclken ,
input wfull ,
input wclk );
`ifdef VENDORRAM
// instantiation of a vendor's dual-port RAM
vendor_ram mem (
.dout(rdata),
.din(wdata),
.waddr(waddr),
.raddr(raddr),
.wclken(wclken),
.wclken_n(wfull),
.clk(wclk));
`else
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull)
mem[waddr] <= `DELAY wdata;
`endif
endmodule
| 7.485738 |
module sync_r2w_ga #(
parameter ADDRSIZE = 4
) (
output [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk,
input wrst_n
);
DFF_ #(
.DATA_WIDTH(ADDRSIZE + 1)
) rptr_sync (
.i_iSig(rptr),
.i_aOReset_N(wrst_n),
.i_OClk(wclk),
.o_oSig(wq2_rptr)
);
// reg [ADDRSIZE:0] wq1_rptr;
//
// always @(posedge wclk or negedge wrst_n)
// if (!wrst_n)
// {wq2_rptr,wq1_rptr} <= `DELAY 0;
// else
// {wq2_rptr,wq1_rptr} <= `DELAY {wq1_rptr,rptr};
endmodule
| 6.826209 |
module rptr_empty_ga #(
parameter ADDRSIZE = 4)
(
output reg rempty ,
output [ADDRSIZE-1:0] raddr ,
output reg [ADDRSIZE :0] rptr ,
input [ADDRSIZE :0] rq2_wptr,
input rinc ,
input rclk ,
input rrst_n );
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n)
{rbin, rptr} <= `DELAY 0;
else
{rbin, rptr} <= `DELAY {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + {{ADDRSIZE{1'b0}}, (rinc & ~rempty)};
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
wire [ADDRSIZE:0] rgray;
assign rgray = {1'b0, rbin[ADDRSIZE:1]}^rbin[ADDRSIZE:0];
//assign rempty_val = (rgraynext == rq2_wptr);
//always @(posedge rclk or negedge rrst_n)
// if (!rrst_n)
// rempty <= `DELAY 1'b1;
// else
// rempty <= `DELAY rempty_val;
//this empty generate circuit vs previous one
//same: assert empty the same
//pros: deassert empty 1 clock earlier in some case
//cons: logic output instead of register output
always @ ( * ) begin
rempty = (rgray == rq2_wptr);
end
endmodule
| 7.029665 |
module wptr_full_ga #(
parameter ADDRSIZE = 4)
(
output reg wfull ,
output [ADDRSIZE-1:0] waddr ,
output reg [ADDRSIZE :0] wptr ,
input [ADDRSIZE :0] wq2_rptr,
input winc ,
input wclk ,
input wrst_n );
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
{wbin, wptr} <= `DELAY 0;
else
{wbin, wptr} <= `DELAY {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + {{ADDRSIZE{1'b0}}, (winc & ~wfull)};
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
//assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
//always @(posedge wclk or negedge wrst_n)
// if (!wrst_n)
// wfull <= `DELAY 1'b0;
// else
// wfull <= `DELAY wfull_val;
wire [ADDRSIZE:0] wgray;
assign wgray = {1'b0, wbin[ADDRSIZE:1]} ^ wbin[ADDRSIZE:0];
always @ ( * ) begin
wfull = (wgray=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
end
endmodule
| 7.240763 |
module asyfifo (
rd_clk,
wr_clk,
rst,
wr_en,
rd_en,
w_data,
r_data,
full,
empty,
wr_err,
rd_err
);
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR_PTR_WIDTH = 4;
input rd_clk, wr_clk, rst, wr_en, rd_en;
input [WIDTH-1:0] w_data;
output reg [WIDTH-1:0] r_data;
output reg wr_err, rd_err, full, empty;
reg [ADDR_PTR_WIDTH-1:0] wr_ptr, rd_ptr;
reg wr_f, rd_f;
reg wr_ptr_gray, rd_ptr_gray;
reg wr_ptr_gray_rd_clk, wr_f_rd_clk;
reg rd_ptr_gray_wr_clk, rd_f_wr_clk;
integer i;
reg [WIDTH-1:0] mem[DEPTH-1:0];
//write block
always @(posedge wr_clk) begin
if (rst) begin
wr_ptr = 0;
rd_ptr = 0;
full = 0;
empty = 1;
wr_err = 0;
rd_err = 0;
wr_f = 0;
rd_f = 0;
r_data = 0;
for (i = 0; i < DEPTH; i = i + 1) mem[i] = 0;
end else begin
wr_err = 0;
if (wr_en) begin
if (~full) begin
mem[wr_ptr] = w_data;
if (wr_ptr == DEPTH - 1) begin
wr_f = ~wr_f;
wr_ptr = 0;
end else begin
wr_ptr = wr_ptr + 1;
wr_ptr_gray = bin2gray(wr_ptr);
end
end else wr_err = 1;
end
end
end
//read block
always @(posedge rd_clk) begin
if (rst == 0) begin
rd_err = 0;
if (rd_en) begin
if (~empty) begin
r_data = mem[rd_ptr];
if (rd_ptr == DEPTH - 1) begin
rd_f = ~rd_f;
rd_ptr = 0;
end else begin
rd_ptr = rd_ptr + 1;
rd_ptr_gray = bin2gray(rd_ptr);
end
end else rd_err = 1;
end
end
end
//synchronization block
always @(posedge rd_clk) begin
wr_ptr_gray_rd_clk <= wr_ptr_gray;
wr_f_rd_clk <= wr_f;
end
always @(posedge wr_clk) begin
rd_ptr_gray_wr_clk <= rd_ptr_gray;
rd_f_wr_clk <= rd_f;
end
//comparison block
always @(*) begin
full = 0;
empty = 0;
if (wr_ptr_gray_rd_clk == rd_ptr && wr_f_rd_clk == rd_f) begin
empty = 1;
//full=0;
end
if (wr_ptr == rd_ptr_gray_wr_clk && wr_f != rd_f_wr_clk) begin
full = 1;
// empty=0;
end
end
// function to convert binary to gray code
function reg [ADDR_PTR_WIDTH-1:0] bin2gray(input [ADDR_PTR_WIDTH-1:0] bin);
begin
bin2gray = {bin[ADDR_PTR_WIDTH-1], bin[ADDR_PTR_WIDTH-1:1] ^ bin[ADDR_PTR_WIDTH-2:0]};
end
endfunction
endmodule
| 6.586786 |
module tb;
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR_PTR_WIDTH = 4;
parameter MAX_WR_DELAY = 8;
parameter MAX_RD_DELAY = 12;
reg rd_clk, wr_clk, rst, wr_en, rd_en;
reg [WIDTH-1:0] w_data;
wire [WIDTH-1:0] r_data;
wire wr_err, rd_err, full, empty;
integer i, j, p, q;
reg [3:0] wr_delay, rd_delay;
reg [50*8:1] testname;
asyfifo #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.ADDR_PTR_WIDTH(ADDR_PTR_WIDTH)
) dut (
rd_clk,
wr_clk,
rst,
wr_en,
rd_en,
w_data,
r_data,
full,
empty,
wr_err,
rd_err
);
initial begin
rd_clk = 0;
forever #10 rd_clk = ~rd_clk;
end
initial begin
wr_clk = 0;
forever #5 wr_clk = ~wr_clk;
end
initial begin
$value$plusargs("testname=%s", testname);
//$display("testname=%s", testname);
rst = 1;
wr_en = 0;
rd_en = 0;
w_data = 0;
@(posedge wr_clk); //reset is acting on wr_clk
rst = 0;
case (testname)
"test_fifo_full_err": begin
write_fifo(DEPTH + 1);
end
"test_fifo_full": begin
write_fifo(DEPTH);
end
"test_empty_error": begin
// write_fifo(10);
read_fifo(12);
end
"test_fifo_empty": begin
write_fifo(DEPTH);
read_fifo(DEPTH);
end
"concurrent_rd_wr": begin
fork
for (p = 0; p < 200; p = p + 1) begin
write_fifo(1); //person entering a bank
wr_delay = $urandom_range(1, MAX_WR_DELAY);
repeat (wr_delay) @(posedge wr_clk); //delay for which no person enters
end
for (q = 0; q < 200; q = q + 1) begin
read_fifo(1); //person entering a bank
rd_delay = $urandom_range(1, MAX_RD_DELAY);
repeat (rd_delay) @(posedge rd_clk); //delay for which no person enters
end
join
end
endcase
#100;
$finish;
end
task write_fifo(input integer num_loc);
begin
for (i = 0; i < num_loc; i = i + 1) begin
@(posedge wr_clk);
wr_en = 1;
w_data = $random;
end
@(posedge wr_clk);
wr_en = 0;
w_data = 0;
end
endtask
task read_fifo(input integer num_loc);
begin
for (
p = 0; p < num_loc; p = p + 1
) begin //different variable j is taken to avoid ambiguity that can arise in case of concurrent read write operations
@(posedge rd_clk);
rd_en = 1;
end
@(posedge rd_clk);
rd_en = 0;
end
endtask
endmodule
| 6.612288 |
module asyncfifo_tb; //testbench module
reg write_clk, read_clk, reset, write_en, read_en; //register declaration
reg [7:0] data_in;
wire mem_full, mem_empty;
wire [7:0] out;
//instantiation of design module
asyncfifo dut (
.write_clk(write_clk), //input write clock
.read_clk (read_clk), //input read clock
.reset (reset), //input reset
.write_en (write_en), //write enable
.read_en (read_en), //read enable
.data_in (data_in), //data input
.mem_full (mem_full), //memory full
.mem_empty(mem_empty), //memory empty
.out (out) //output
);
//generates clock for write operation
initial begin
write_clk = 1'b0;
forever #5 write_clk = ~write_clk;
end
//generates clock for read operation
initial begin
read_clk = 1'b0;
forever #10 read_clk = ~read_clk;
end
//calling the write and read operations
initial begin
reset = 1'b1;
write_en = 1'b0;
read_en = 1'b0;
data_in = 8'b0;
#10;
reset = 1'b0;
#10;
reset = 1'b1;
write_task;
#20; //calling the task write
read_task;
#20; //calling the task read
write_task;
#20;
write_task;
#200 $finish; //finish simulation
end
task write_task; //task
begin
write_en = 1'b1;
read_en = 1'b0;
data_in = $random;
#20;
$display(
"write_en = %b , read_en = %b , data_in = %b , out = %b , mem_full = %b , mem_empty = %b",
write_en, read_en, data_in, out, mem_full, mem_empty); //display statement
end
endtask
task read_task; //task
begin
write_en = 1'b0;
read_en = 1'b1;
#20;
$display(
"write_en = %b , read_en = %b , data_in = %b , out = %b , mem_full = %b , mem_empty = %b",
write_en, read_en, data_in, out, mem_full, mem_empty); //display statement
end
endtask
endmodule
| 8.462746 |
module ASYNCH_DRIVER (
input ASYNCH_CLK,
input [7:0] ASYNCH_BYTE_TO_SEND,
input ASYNCH_ENABLE,
input ASYNCH_TX_LINE,
output reg ASYNCH_RX_LINE = 1'b1,
output reg ASYNCH_READY = 1'b1,
output [7:0] ASYNCH_BYTE_RECEIVED,
output reg ASYNCH_DATA_OK = 1'b0,
output reg ASYNCH_TEST_PIN = 1'b0
);
reg [ 3:0] ASYNCH_RX_TIMER = 4'hA;
reg [10:0] ASYNCH_RX_BUFFER = 11'b11000000000;
always @(ASYNCH_TX_TIMER or ASYNCH_RX_TIMER) begin
ASYNCH_READY <= (ASYNCH_RX_TIMER == 4'hA) ? ((ASYNCH_TX_TIMER == 4'hA) ? 1'b1 : 1'b0) : 1'b0;
end
//
//Tick generator
//
localparam timier_value = 8'd52; //8'd47;
reg [14:0] TickAcc = 15'd0;
reg ASYNCH_TIC_ENABLE = 1'b1;
reg TickAcc10_old = 1'b1;
wire BAUD_GEN_tick;
wire BAUD_OVER_tick;
wire BAUD_SYNCH_tick;
reg BAUD_SYNCH_tick_reg = 1'b0;
reg BAUD_OVER_counter_synch = 1'b0;
reg [3:0] BAUD_OVER_counter = 4'h0;
always @(BAUD_SYNCH_tick) ASYNCH_TEST_PIN <= BAUD_SYNCH_tick;
assign BAUD_SYNCH_tick = BAUD_SYNCH_tick_reg & BAUD_OVER_tick;
always @(BAUD_OVER_counter) begin
if (BAUD_OVER_counter == 4'hF) BAUD_SYNCH_tick_reg <= #1 1'b1;
else BAUD_SYNCH_tick_reg <= #1 1'b0;
end
always @(posedge ASYNCH_CLK) begin
if (BAUD_OVER_counter_synch == 1'b1) begin
BAUD_OVER_counter <= #1 4'hF;
end else begin
if (BAUD_OVER_tick == 1'b1) begin
BAUD_OVER_counter <= #1 BAUD_OVER_counter + 4'h1;
end else begin
BAUD_OVER_counter <= #1 BAUD_OVER_counter;
end
end
end
always @(posedge ASYNCH_CLK) begin
if (ASYNCH_TIC_ENABLE) TickAcc <= TickAcc[13:0] + timier_value;
else TickAcc <= timier_value;
end
always @(posedge ASYNCH_CLK) TickAcc10_old <= TickAcc[10];
assign BAUD_GEN_tick = TickAcc[14];
assign BAUD_OVER_tick = TickAcc10_old ^ TickAcc[10];
//
//Transmiter
//
always @(posedge ASYNCH_CLK) begin
if ((ASYNCH_RX_TIMER < 4'hA) && (BAUD_GEN_tick == 1'b1))
ASYNCH_RX_TIMER <= #1 ASYNCH_RX_TIMER + 1;
else if ((ASYNCH_ENABLE == 1'b1) && (BAUD_GEN_tick == 1'b1)) ASYNCH_RX_TIMER <= #1 4'h0;
else ASYNCH_RX_TIMER <= #1 ASYNCH_RX_TIMER;
end
always @(ASYNCH_BYTE_TO_SEND or ASYNCH_RX_TIMER) begin
if (ASYNCH_RX_TIMER == 4'hA) ASYNCH_RX_BUFFER[8:1] <= #1 ASYNCH_BYTE_TO_SEND;
else ASYNCH_RX_BUFFER <= #1 ASYNCH_RX_BUFFER;
end
always @(ASYNCH_RX_TIMER) ASYNCH_RX_LINE = ASYNCH_RX_BUFFER[ASYNCH_RX_TIMER];
//
//Receiver
//
reg [ 7:0] TX_DATA_SAMPLES = 8'h55;
reg [ 3:0] ASYNCH_TX_TIMER = 4'hA;
reg [10:0] ASYNCH_TX_BUFFER = 11'b00000000000;
always @(posedge ASYNCH_CLK)
if (BAUD_OVER_tick) TX_DATA_SAMPLES <= {TX_DATA_SAMPLES[6:0], ASYNCH_TX_LINE};
else TX_DATA_SAMPLES <= TX_DATA_SAMPLES;
always @(posedge ASYNCH_CLK) begin
if (ASYNCH_TX_TIMER < 4'hA) begin
BAUD_OVER_counter_synch <= #1 1'b0;
if (BAUD_SYNCH_tick == 1'b1) ASYNCH_TX_TIMER <= #1 ASYNCH_TX_TIMER + 1;
end else begin
if (TX_DATA_SAMPLES == 8'h00) begin
ASYNCH_TX_TIMER <= #1 4'h0;
BAUD_OVER_counter_synch <= #1 1'b1;
end
end
end
always @(posedge ASYNCH_CLK)
if (BAUD_SYNCH_tick == 1'b1 && ASYNCH_TX_TIMER < 4'hA) begin
ASYNCH_TX_BUFFER[ASYNCH_TX_TIMER] <= #1 TX_DATA_SAMPLES[0];
end
//else ASYNCH_TEST_PIN <= #1 1'b0;
assign ASYNCH_BYTE_RECEIVED = ASYNCH_TX_BUFFER[8:1];
endmodule
| 7.604342 |
module asynchronus_ram
#(parameter ADDR_WDITH = 8, DATA_WDITH =1)
(
clk, we, addr, din, dout
)
input wire clk, we;
input wire [ADDR_WDITH-1:0] addr;
input wire [DATA_WDITH-1:0] din;
output wire [DATA_WDITH-1:0] dout;
reg [DATA_WDITH-1:0] ram [2*ADDR_WDITH-1:0]
always @(posedge clk) begin
if (we)
ram[addr] <= din;
end
assign dout = ram[addr];
endmodule
| 7.327964 |
module asynchronus_rom (
addr,
data
);
input wire [3:0] addr;
output reg [7:0] data;
always @(*) begin
case (addr)
4'h0: data = 7'b0000001;
4'h1: data = 7'b1001111;
4'h2: data = 7'b0010010;
4'h3: data = 7'b0000110;
4'h4: data = 7'b1001100;
4'h5: data = 7'b0100100;
4'h6: data = 7'b0100000;
4'h7: data = 7'b0001111;
4'h8: data = 7'b0000000;
4'h9: data = 7'b0000100;
4'ha: data = 7'b0001000;
4'hb: data = 7'b1100000;
4'hc: data = 7'b0110001;
4'hd: data = 7'b1000010;
4'he: data = 7'b0110000;
4'hf: data = 7'b0111000;
endcase
end
endmodule
| 7.327964 |
module asynchronousWriteToHBM_HBM_m_axi_flushManager
#(parameter
NUM_READ_OUTSTANDING = 2,
NUM_WRITE_OUTSTANDING = 2
)(
input clk,
input reset,
input clk_en,
input flush,
output flush_done,
input in_AWVALID,
output out_AWVALID,
input in_AWREADY,
output out_AWREADY,
input in_WVALID,
output out_WVALID,
input in_BREADY,
output out_BREADY,
input in_BVALID,
input in_ARVALID,
output out_ARVALID,
input in_ARREADY,
input in_RREADY,
output out_RREADY,
input in_RVALID,
input in_RLAST);
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg flushStart;
reg flushReg;
wire oneWBurstLaunch;
wire oneWBurstFinish;
wire flush_AWVALID;
wire flush_BREADY;
wire WBurstEmpty_n;
wire wFlushDone;
wire oneRBurstLaunch;
wire oneRBurstFinish;
wire flush_ARVALID;
wire flush_RREADY;
wire RBurstEmpty_n;
wire rFlushDone;
//------------------------Instantiation------------------
asynchronousWriteToHBM_HBM_m_axi_fifo #(
.DATA_WIDTH (1),
.ADDR_WIDTH (log2(NUM_WRITE_OUTSTANDING)),
.DEPTH (NUM_WRITE_OUTSTANDING)
) WFlushManager (
.clk (clk),
.reset (reset),
.clk_en (clk_en),
.if_full_n (),
.if_write (oneWBurstLaunch),
.if_din (1'b1),
.if_empty_n (WBurstEmpty_n),
.if_read (oneWBurstFinish),
.if_dout (),
.if_num_data_valid());
asynchronousWriteToHBM_HBM_m_axi_fifo #(
.DATA_WIDTH (1),
.ADDR_WIDTH (log2(NUM_READ_OUTSTANDING)),
.DEPTH (NUM_READ_OUTSTANDING)
) RFlushManager (
.clk (clk),
.reset (reset),
.clk_en (clk_en),
.if_full_n (),
.if_write (oneRBurstLaunch),
.if_din (1'b1),
.if_empty_n (RBurstEmpty_n),
.if_read (oneRBurstFinish),
.if_dout (),
.if_num_data_valid());
//------------------------Body---------------------------
assign oneWBurstLaunch = flush_AWVALID & in_AWREADY;
assign oneWBurstFinish = flush_BREADY & in_BVALID;
assign oneRBurstLaunch = flush_ARVALID & in_ARREADY;
assign oneRBurstFinish = flush_RREADY & in_RLAST & in_RVALID;
assign flush_AWVALID = flush ? 0 : in_AWVALID;
assign out_AWVALID = flush_AWVALID;
assign out_AWREADY = flush ? 0 : in_AWREADY;
assign out_WVALID = wFlushDone ? 0 : in_WVALID;
assign flush_BREADY = flush ? 1 : in_BREADY;
assign out_BREADY = flush_BREADY;
assign flush_ARVALID = flush ? 0 : in_ARVALID;
assign out_ARVALID = flush_ARVALID;
assign flush_RREADY = flush ? 1 : in_RREADY;
assign out_RREADY = flush_RREADY;
assign wFlushDone = flushStart & ~WBurstEmpty_n;
assign rFlushDone = flushStart & ~RBurstEmpty_n;
assign flush_done = wFlushDone & rFlushDone;
always @ (posedge clk) begin
if (reset)
flushReg <= 1'b0;
else if (clk_en)
flushReg <= flush;
end
always @ (posedge clk) begin
if (reset)
flushStart <= 1'b0;
else if (clk_en) begin
if (flush && ~flushReg)
flushStart <= 1'b1;
else if (~flush && flushReg)
flushStart <= 1'b0;
end
end
endmodule
| 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_reg_slice #(
parameter DATA_WIDTH = 8
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [DATA_WIDTH-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [DATA_WIDTH-1:0] data_p1;
reg [DATA_WIDTH-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_srl #(
parameter DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [DATA_WIDTH-1:0] din,
input wire [ADDR_WIDTH-1:0] raddr,
input wire re,
output reg [DATA_WIDTH-1:0] dout
);
generate
if (DEPTH > 1) begin
reg [DATA_WIDTH-1:0] mem[0:DEPTH-2];
integer i;
always @(posedge clk) begin
if (clk_en & we) begin
for (i = 0; i < DEPTH - 2; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= din;
end
end
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & re) begin
dout <= mem[raddr];
end
end
end else begin
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & we) begin
dout <= din;
end
end
end
endgenerate
endmodule
| 7.46464 |
module asynchronousWriteToHBM_HBM_m_axi_mem #(
parameter MEM_STYLE = "auto",
DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
input wire [ADDR_WIDTH-1:0] raddr,
input wire re,
output reg [DATA_WIDTH-1:0] dout
);
(* ram_style = MEM_STYLE, rw_addr_collision = "yes" *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-2];
reg [ADDR_WIDTH-1:0] raddr_reg;
//write to ram
always @(posedge clk) begin
if (clk_en & we) mem[waddr] <= din;
end
//buffer the raddr
always @(posedge clk) begin
if (clk_en) raddr_reg <= raddr;
end
//read from ram
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & re) dout <= mem[raddr_reg];
end
endmodule
| 7.46464 |
module asynchronousWriteToHBM_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 7.46464 |
module asynchronousWriteToHBM_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 7.46464 |
module asynchronous_fifo(
output full,empty, [7:0]d_out,
input wr_clk,wr_en,rd_en,rst,[7:0]d_in);
wire gen_clk;
wire [4:0]wr_addr,rd_addr;
wire wen;
wire [5:0]wr_ptr,rd_ptr,wq2_rd_ptr,rq2_wr_ptr;
clk_wiz_0 clocking
(
.clk_out1(gen_clk),
.clk_in1(wr_clk));
and(wen,wr_en,~full);
dual_port_sram bram(.wr_clk(wr_clk),.rd_en(rd_en),.wr_en(wen),.wr_addr(wr_addr),.d_in(d_in),
.rd_clk(gen_clk),.rd_addr(rd_addr),.d_out(d_out));
r_ptr_and_empty r1 (.rd_rst(rst),.rd_clk(gen_clk),.rd_en(rd_en),.rq2_wptr(rq2_wr_ptr),
.empty(empty),.rd_addr(rd_addr),.rd_ptr(rd_ptr));
w_ptr_and_full w1 (.full(full),.wr_addr(wr_addr),.wr_ptr(wr_ptr),.wr_en(wr_en),
.wr_rst(rst),.wr_clk(wr_clk),.wq2_rptr(wq2_rd_ptr));
sync_w2r r2w(.rq2_wr_ptr(rq2_wr_ptr),.wr_ptr(wr_ptr),.rd_rst(rst),.rd_clk(gen_clk));
sync_r2w w2r(.wq2_rd_ptr(wq2_rd_ptr),.rd_ptr(rd_ptr), .wr_rst(rst), .wr_clk(wr_clk));
endmodule
| 6.759178 |
module asynch_edge_detect (
input SYNC_CLK_IN,
input ASYNC_IN,
output DETECT_OUT
);
wire detect;
wire signal_in;
reg signal_in_prev;
assign detect = signal_in & ~signal_in_prev;
assign DETECT_OUT = detect;
always @(posedge SYNC_CLK_IN) begin
signal_in_prev <= signal_in;
end
synchronizer synch_inst (
.asynch_input(ASYNC_IN),
.synch_clk(SYNC_CLK_IN),
.synch_output(signal_in)
);
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
// Clock Enable (posedge clk).
// All families.
// Xilinx HDL Language Template, version 14.7
/*FDCE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDCE_inst_a (
.Q(async_clk_prev), // Data output
.C(SYNC_CLK_IN), // Clock input
.CE(1'b1), // Clock enable input
.CLR(1'b0), // Asynchronous clear input
.D(ASYNC_IN) // Data input
);
FDCE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDCE_inst_b (
.Q(DETECT_OUT), // Data output
.C(neg_sync_clk), // Clock input
.CE(1'b1), // Clock enable input
.CLR(1'b0), // Asynchronous clear input
.D(detect) // Data input
);
*/
// End of FDCE_inst instantiation
endmodule
| 7.200684 |
module asynch_up_counter (
input clk,
input reset_n,
output [3:0] Q
);
T_FF FF0 (
.clk(clk),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[0])
);
T_FF FF1 (
.clk(~Q[0]),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[1])
);
T_FF FF2 (
.clk(~Q[1]),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[2])
);
T_FF FF4 (
.clk(~Q[2]),
.T(1'b1),
.reset_n(reset_n),
.Q(Q[3])
);
endmodule
| 6.685081 |
module asynch_up_counter_tb ();
reg clk, reset_n;
wire [3:0] Q;
// Instantiate module under test
asynch_up_counter uut (
.clk(clk),
.reset_n(reset_n),
.Q(Q)
);
// timer
initial #200 $stop;
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
initial begin
// issue a quick reset for 2 ns
reset_n = 1'b0;
#2 reset_n = 1'b1;
end
endmodule
| 6.685081 |
module name is : async_fifo
module <:$mod_name:>
(
// FIFO
parameter data_width = <:$dwd:>,// FIFO
parameter data_depth = <:$depth:>,// FIFO
parameter address_width = <:$awd:>, // ַȣΪ2^nFIFOҪĶ/дָλΪ(n+1)λһλΪ۷־λ
input rst_wr,
input wr_clk,
input wr_en,
input [data_width-1:0] wr_din,
input rst_rd,
input rd_clk,
input rd_en,
output reg [data_width-1:0] rd_dout
);
reg [address_width:0] wr_addr_p;//дַָ
reg [address_width:0] rd_addr_p;//ַָ
wire [address_width-1:0] wr_addr;//дRAM ַ
wire [address_width-1:0] rd_addr;//RAM ַ
wire [address_width:0] wr_addr_gray;//дַָӦĸ
reg [address_width:0] wr_addr_gray_d1;
reg [address_width:0] wr_addr_gray_d2;//дַָͬʱӦĸ
wire [address_width:0] rd_addr_gray;//ַָӦĸ
reg [address_width:0] rd_addr_gray_d1;
reg [address_width:0] rd_addr_gray_d2;//ַָͬдʱӦĸ";
<:
if ($test == 1) {
$OUT .= " // test line ";
}
:>
//=======================================================================================================================
// Please add your implement logic below ,
// Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var}
//=======================================================================================================================
endmodule
| 7.351375 |
module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset
);
wire [7:0] _zz_5;
wire [4:0] _zz_6;
wire [4:0] _zz_7;
wire [7:0] _zz_8;
wire _zz_9;
reg [4:0] head;
reg [4:0] tail;
reg full;
reg empty;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg _zz_4;
reg [7:0] mem[0:31];
assign _zz_6 = (head + (5'b00001));
assign _zz_7 = (tail + (5'b00001));
assign _zz_8 = io_dataIn;
assign _zz_9 = ((!full) && io_write);
always @(posedge clk) begin
if (_zz_9) begin
mem[head] <= _zz_8;
end
end
assign _zz_5 = mem[tail];
assign io_dataOut = _zz_5;
assign io_empty = empty;
assign io_full = full;
always @(posedge clk or posedge reset) begin
if (reset) begin
head <= (5'b00000);
tail <= (5'b00000);
full <= 1'b0;
empty <= 1'b1;
end else begin
if (((io_write && (!_zz_1)) && (!io_read))) begin
if ((!full)) begin
head <= (head + (5'b00001));
full <= (_zz_6 == tail);
empty <= 1'b0;
end
end
if (((!io_write) && (io_read && (!_zz_2)))) begin
if ((!empty)) begin
tail <= (tail + (5'b00001));
empty <= (_zz_7 == head);
full <= 1'b0;
end
end
if (((io_write && (!_zz_3)) && (io_read && (!_zz_4)))) begin
if (full) begin
tail <= (tail + (5'b00001));
full <= 1'b0;
end
if (empty) begin
head <= (head + (5'b00001));
empty <= 1'b0;
end
if (((!full) && (!empty))) begin
tail <= (tail + (5'b00001));
head <= (head + (5'b00001));
end
end
end
end
always @(posedge clk) begin
_zz_1 <= io_write;
_zz_2 <= io_read;
_zz_3 <= io_write;
_zz_4 <= io_read;
end
endmodule
| 6.757216 |
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