code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Back_Light (
input Sys_Clk,
input Sys_Rst,
input Left,
Right,
Emer,
output reg LED_G1,
LED_G2,
LED_R1,
LED_R2
);
reg [23:0] Cnt_1Hz;
parameter Diveider = 24'h5B8D80;
always @(posedge Sys_Clk or negedge Sys_Rst) begin
if (!Sys_Rst) Cnt_1Hz <= 24'h0;
else if (Cnt... | 6.772116 |
module bACS_213.v
ACS Block for (2,1,3) backward label decoder
============================================================*/
`timescale 1 ns/1 ns
module bACS_213 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
ae, clock, reset);
`include... | 6.550346 |
module bACS_322.v
ACS Block for (3,2,2) backward label decoder
============================================================*/
`timescale 1 ns/1 ns
module bACS_322 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
acs_ppm_inc, HD_inc, acs_ppm_ind, HD_ind,
... | 6.549033 |
module fsm (
clock,
reset,
start,
done_flag,
match_address,
inc_flag,
location,
outcell
);
input clock; // 100 Mhz clock
input reset; // resets the fsm
input start; // starts the search
input [8:0] match_address; // address for the pattern match
input done_flag; // signa... | 7.229634 |
module for fsm
module test_fsm;
reg reset, clock, start, done_flag;
reg [8:0] match_address;
wire [8:0] location, outcell;
initial
begin
/* Comments to include for Unix */
$shm_open("waves.shm"); // save shm data base to mem.sav
$shm_probe ("AS"); // save all signals in the hierarchy, A = ... | 7.007712 |
module badge_trace (
// Diagnostic input
input badge_clk,
input badge_stb,
input [7:0] badge_data,
// Arbitrary domain
input trace_reset,
// Local bus side
input lb_clk,
input [23:0] lb_addr,
input lb_rd,
output [7:0] lb_result
);
// Time since boot, wrap every 34.4 second... | 7.434011 |
module badge_trace_tb;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("badge_trace.vcd");
$dumpvars(5, badge_trace_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 150; cc = cc + 1) begin
clk = 0;
#4;
cl... | 6.792362 |
module bad_block_manage (
input rst,
clk,
input [23:0] erase_addr_row,
input en_erase_page,
input [4:0] state,
output reg end_bad_block_renew, //£״̬
output [11:0] bad_block_renew_addr,
output reg we_bad_block_renew,
output bad_block_renew_datain,... | 7.107635 |
module addbit (
a,
b,
ci,
sum,
co
);
input a, b, ci;
output sum co;
wire a, b, ci, sum, co;
endmodule
| 7.120785 |
module bad_xor32 (
X,
Y,
Z
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] Z;
assign Z = X & ~Y; //this is not an xor!!!
endmodule
| 7.776366 |
module baggage_drop (
output [6 : 0] seven_seg1,
output [6 : 0] seven_seg2,
output [6 : 0] seven_seg3,
output [6 : 0] seven_seg4,
output [0 : 0] drop_activated,
input [7 : 0] sensor1,
input [7 : 0] sensor2,
input [7 : 0] sensor3,
input [7 : 0] sensor4,
input [ 15:0] t_lim,
... | 7.194924 |
module implements the filter window,mask, in addition to the row buffers
........................
By: Abdullah Al-Dujaili
NTU, 2012
.......................
Importantn note :=============================
This filter mask is designed espeically for 7*7 filter mask
as there are multiplexers that are difficult to make... | 7.842559 |
module bakingState (
input clk,
input [1:0] state,
input [9:0] timerVal,
input [9:0] inputTemp,
output reg [3:0] tempVal0,
tempVal1,
tempVal2,
tempVal3,
output reg readyLight = 0
);
reg [9:0] currentTemp = 65; //variable to store temp, default temp is 65
reg [9:0] counter = 0; ... | 6.935915 |
module balanced_adder_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_... | 6.768636 |
module balanced_adder_test #(
parameter data_width = 8,
N = 4
) (
input wire clk,
output wire [data_width*N - 1:0] outp,
output wire [(2**N)*data_width-1:0] outp_inps
);
reg [(2**N)*data_width-1:0] count;
initial begin
count = 0;
end
initial count = 32;
always @(posedge clk) count <=... | 6.768636 |
module balance_tree_adder #(
parameter N = 4,
DW = 8
) (
input wire clk,
input wire [(2**N)*DW - 1 : 0] inp,
output reg [N*DW - 1 : 0] outp
);
reg [DW*N-1:0] regs[2:2**N]; //
reg [N-1:0] k;
reg [10:0] m;
reg [10:0] j;
genvar i;
wire [DW-1:0] arra[0:2**N-1];
generate
for (i = 0... | 7.963914 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // ... | 8.621551 |
module control_ball (
input clk,
resetn,
go,
draw_done,
move_done,
output reg enable_color,
enable_move,
writeEn,
draw,
output reg done
// output hold, hold1
);
wire hold, hold1;
timer_l t002 (
.clk(clk),
.resetn(reset),
.enable(1'b1),
.dividend(... | 7.010699 |
module datapath_ball (
input clk,
resetn,
enable_color,
enable_move,
draw,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out,
output draw_done,
move_done
);
wire [7:0] x_pos;
wire [6:0] y_pos;
xy_counter_ball movement (
.clk(clk),
.resetn(resetn),
... | 7.247038 |
module ball_draw (
input clk,
draw,
input [7:0] x_in,
input [6:0] y_in,
output [7:0] x_out,
output [6:0] y_out,
output done
);
reg [3:0] count;
assign resetn = draw;
always @(posedge clk) begin
if (!resetn) count <= 4'b0000;
else if (count == 1111) count <= 4'b0000;
else c... | 7.306498 |
module xy_counter_ball (
input clk,
resetn,
enable_move,
output reg [7:0] x_out,
output reg [6:0] y_out
// output move_done
);
// x_counter
reg done;
wire enable_move1;
assign enable_move1 = enable_move;
always @(posedge enable_move, negedge resetn) begin
if (!resetn) begin
... | 7.032243 |
module ball (
input wire px_clk, // Pixel clock.
input wire [25:0] strRGB_i, // Input RGB stream.
input wire [ 9:0] pos_x, // X ball position.
input wire [ 9:0] pos_y, // Y ball position.
output wire [25:0] strRGB_o // Output RGB stream.
);
// Bits address alias.
`defi... | 6.888453 |
module balloon( rst, clk, frame_end, x, y, bullet_x, bullet_y, bomb_x, bomb_y, en);
parameter START = 4;
parameter MAXV = 480;
parameter MAXH = 640;
parameter NUM_BULLETS = 10;
parameter NUM_BOMBS = 2;
//parameter MINX = 40;
//parameter MAXX = 550;
input clk, frame_end, rst;
//input [11*NUM_BULLETS-1:0] min;
input [11... | 7.467564 |
module BallUpdate #(
parameter SIZE_BALL = 16
) (
input wire px_clk, // pixel clock.
input wire endframe, // end of frame
output reg [9:0] x_ball, // X ball position.
output reg [9:0] y_ball // Y ball position.
);
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0]... | 8.61795 |
module top (
input RST, // active low
input CLK, // 12MHz clock
// VGA
output VGA_BLUE,
output VGA_GREEN,
output VGA_RED,
output VGA_HSYNC,
output VGA_VSYNC,
output LED1
);
// RST - pull up
wire reset;
SB_IO
#(
.PIN_TYPE(6'b0000_01),
.PULLU... | 7.429197 |
module ball_absolute_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
input wire [0 : 0] hpaddle, //
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/******************... | 7.998896 |
module ball_cltr #(
parameter GAME_WIDTH = 480,
parameter GAME_HEIGHT = 272,
parameter BALL_SIZE = 10,
parameter CORR_X = 43, // hDE = 44~523 High
parameter CORR_Y = 12 // vDE = 13~284 High
) (
input clk,
input nrst,
input [9:0] vcnt,
input [9:0] hcnt,
input de,
input game_... | 7.222789 |
module looks at the video, selects red pixels, low-pass filters that, and
// then finds the center of the red object.
// The output is the placement of a marker (+ like symbol) overlaying the camera video.
module ball_detector (
input reset,
input [23:0] video_in, // RGB camera video, post-de-Bayer
i... | 8.319226 |
module ball (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // ... | 7.911761 |
module datapath (
clock,
reset_n,
x_out,
y_out,
enable_erase,
enable_update,
colour_out,
enable,
enable_fcounter,
y_count_done
);
input clock, reset_n, enable, enable_erase, enable_update, enable_fcounter;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] colour_out;
... | 6.91752 |
module control_draw (
go,
next_boxx,
clock,
reset_n,
write_en,
enable,
enable_erase,
enable_update,
enable_fcounter,
next_box,
y_count_done,
clear_sig
);
input clock, reset_n, next_box, next_boxx, y_count_done, go;
output reg enable, write_en, enable_erase, enable_upd... | 7.972248 |
module ball_lab9 (
clock,
reset_n,
x_out,
y_out,
colour_out
);
input clock, reset_n;
wire enable, write_en, enable_erase, enable_update, go, next_boxx, enable_fcounter, next_box, y_count_done, clear_sig;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] colour_out;
datapath d0 (
... | 7.438299 |
module ball_slipping_counter_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
input wire [0 : 0] hpaddle, //
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/**********... | 8.856362 |
module BrzAdapt_8_9_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inp_0r;
input inp_0a;
input [8:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[0] = inp_0d... | 6.541301 |
module BrzAdapt_17_9_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output inp_0r;
input inp_0a;
input [8:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[9] = exte... | 6.657468 |
module BrzAdapt_17_18_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output inp_0r;
input inp_0a;
input [17:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[0] = in... | 6.571943 |
module BrzBinaryFunc_1_8_8_s11_GreaterThan_s5_fal_m43m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d,
inpB_0r,
inpB_0a,
inpB_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
output inpB_0r;
input inpB_0a;
in... | 6.615161 |
module BrzBinaryFunc_10_9_9_s3_Add_s4_true_s4_tru_m44m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d,
inpB_0r,
inpB_0a,
inpB_0d
);
input out_0r;
output out_0a;
output [9:0] out_0d;
output inpA_0r;
input inpA_0a;
input [8:0] inpA_0d;
output inpB_0r;
input inpB_0a... | 6.615161 |
module BrzBinaryFuncConstR_1_3_1_s9_NotEquals_s5__m25m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [2:0] inpA_0d;
wire start_0n;
wire nStart_0n;
wire [3:0] nCv_0n;
wire [3:0] c_0n;
w... | 6.615161 |
module BrzBinaryFuncConstR_1_8_1_s11_GreaterThan__m45m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [5:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_... | 6.615161 |
module BrzBinaryFuncConstR_3_3_1_s8_Subtract_s5_f_m27m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [2:0] out_0d;
output inpA_0r;
input inpA_0a;
input [2:0] inpA_0d;
wire start_0n;
wire nStart_0n;
wire [3:0] nCv_0n;
wire [3:0] c_0... | 6.615161 |
module BrzBinaryFuncConstR_8_8_1_s3_Add_s5_false__m46m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0... | 6.615161 |
module BrzBinaryFuncConstR_8_8_1_s8_Subtract_s5_f_m47m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0... | 6.615161 |
module BrzCallDemuxPush_1_2 (
inp_0r,
inp_0a,
inp_0d,
out_0r,
out_0a,
out_0d,
out_1r,
out_1a,
out_1d
);
input inp_0r;
output inp_0a;
input inp_0d;
output out_0r;
input out_0a;
output out_0d;
output out_1r;
input out_1a;
output out_1d;
OR2_A I0 (
inp_0a,
... | 6.641334 |
module demux2 (
i,
o0,
o1,
s
);
input i;
output o0;
output o1;
input s;
wire ns_0n;
AND2_A I0 (
o1,
i,
s
);
AND2_A I1 (
o0,
i,
ns_0n
);
INV_A I2 (
ns_0n,
s
);
endmodule
| 6.863824 |
module BrzCombine_8_7_1 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [6:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input MSInp_0d;
... | 6.832518 |
module BrzCombine_16_8_8 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [15:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [7:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [7:0] MS... | 6.935249 |
module BrzCombine_17_1_16 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [15:0] MSInp_... | 6.936519 |
module BrzCombine_17_8_9 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [7:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [8:0] MS... | 6.936519 |
module c3 (
q,
i0,
i1,
i2
);
output q;
input i0;
input i1;
input i2;
wire qint_0n;
c2 I0 (
q,
i2,
qint_0n
);
c2 I1 (
qint_0n,
i0,
i1
);
endmodule
| 6.803047 |
module acu0d1 (
q,
i0,
i1
);
output q;
input i0;
input i1;
wire int_0n;
OR2_A I0 (
q,
i0,
int_0n
);
AND2_A I1 (
int_0n,
i1,
q
);
endmodule
| 6.712457 |
module BrzContinue (
inp_0r,
inp_0a
);
input inp_0r;
output inp_0a;
assign inp_0a = inp_0r;
endmodule
| 6.699402 |
module nc2p (
q,
i0,
i1
);
output q;
input i0;
input i1;
wire nq_0n;
AOI22_A I0 (
q,
i0,
i1,
i0,
nq_0n
);
INV_A I1 (
nq_0n,
q
);
endmodule
| 6.887623 |
module selem (
Ar,
Aa,
Br,
Ba
);
input Ar;
output Aa;
output Br;
input Ba;
wire s_0n;
nc2p I0 (
s_0n,
Ar,
Ba
);
NOR2_A I1 (
Aa,
Ba,
s_0n
);
AND2_A I2 (
Br,
Ar,
s_0n
);
endmodule
| 6.536596 |
module BrzWireFork_2 (
inp_0r,
inp_0a,
out_0r,
out_0a,
out_1r,
out_1a
);
input inp_0r;
output inp_0a;
output out_0r;
input out_0a;
output out_1r;
input out_1a;
supply0 gnd;
assign inp_0a = gnd;
assign out_0r = inp_0r;
assign out_1r = inp_0r;
endmodule
| 6.71441 |
module BAM (
i_clk,
i_arst,
i_on,
i_presc_mode,
i_duty_cycle,
o_bam_enable,
o_signal
);
input i_clk; // Input clock signal, 50MHz system clock on Altera DE2 FPGA board, for example
input i_arst; // Reset
input i_on; // CONFIG[0]
input [2:0] i_presc_mode; // CONFIG[3:1]
input [... | 8.059804 |
module bambu_getchar (
input clock,
input reset,
input start_port,
output reg done_port,
output reg [7:0] return_port,
input [7:0] RX_DATA,
input RX_VALID
);
reg [7:0] data_reg;
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fif... | 6.651577 |
module bambu_putchar (
input clock,
input reset,
input start_port,
output reg done_port,
input [7:0] c,
output reg [7:0] TX_DATA,
output reg TX_ENABLE,
input TX_READY
);
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write... | 6.832514 |
module bambu_single_ram_axi_wrapper (
clock,
reset,
master_tdata,
master_tvalid,
slave_tready,
slave_tdata,
slave_tvalid,
master_tready
);
input wire clock;
input wire reset;
input wire [95:0] master_tdata;
input wire master_tvalid;
input wire master_tready;
output reg [71:... | 7.330918 |
module AND2_44 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.915464 |
module FA_44 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire A;
assign S = A;
endmodule
| 6.871119 |
module CSA_Cell_44 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_44 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_44 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 7.019059 |
module AND2_38 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.695829 |
module AND2_30 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.021831 |
module AND2_1 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.595903 |
module CSA_Cell_1 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_1 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_1 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
... | 6.708587 |
module AND2_2 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.948015 |
module CSA_Cell_2 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_2 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_2 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodu... | 7.535071 |
module AND2_3 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.570512 |
module CSA_Cell_3 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_3 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_3 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
... | 6.97547 |
module FA_4 (
A,
B,
CI,
S,
CO_BAR
);
input A, B, CI;
output S, CO_BAR;
wire n1;
XOR2_X1 U1 (
.A1(A),
.A2(B),
.Z (n1)
);
AOI22_X1 U2 (
.A1(A),
.A2(B),
.B1(n1),
.B2(CI),
.ZN(CO_BAR)
);
XOR2_X1 U3 (
.A1(n1),
.A2(CI),
.Z ... | 6.626139 |
module AND2_4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.779641 |
module CSA_Cell_4 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_4 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_4 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
... | 7.227021 |
module AND2_5 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.939218 |
module CSA_Cell_5 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_5 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_5 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodu... | 7.49635 |
module AND2_6 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.701088 |
module CSA_Cell_6 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_6 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_6 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodu... | 6.809643 |
module FA_7 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire n1, n2;
XOR2_X1 U1 (
.A1(A),
.A2(B),
.Z (n2)
);
AOI22_X1 U2 (
.A1(A),
.A2(B),
.B1(n2),
.B2(CI),
.ZN(n1)
);
INV_X1 U3 (
.I (n1),
.ZN(CO)
);
XOR2_X1 U4 (... | 6.624434 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module CSA_Cell_7 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_7 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_7 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodu... | 6.646269 |
module AND2_9 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.884729 |
module CSA_Cell_9 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_9 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_9 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodu... | 6.633226 |
module AND2_10 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.486296 |
module AND2_11 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.443228 |
module AND2_12 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.990184 |
module CSA_Cell_12 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_12 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_12 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 7.063742 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_14 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.558896 |
module CSA_Cell_14 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_14 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_14 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.954598 |
module AND2_15 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.821494 |
module CSA_Cell_15 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_15 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_15 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.642819 |
module AND2_17 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.742214 |
module CSA_Cell_17 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_17 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_17 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.861753 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module CSA_Cell_19 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_19 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_19 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.517123 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module CSA_Cell_20 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_20 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_20 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.543769 |
module AND2_21 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.110455 |
module CSA_Cell_21 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_21 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_21 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endm... | 6.682578 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.