code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Back_Light (
input Sys_Clk,
input Sys_Rst,
input Left,
Right,
Emer,
output reg LED_G1,
LED_G2,
LED_R1,
LED_R2
);
reg [23:0] Cnt_1Hz;
parameter Diveider = 24'h5B8D80;
always @(posedge Sys_Clk or negedge Sys_Rst) begin
if (!Sys_Rst) Cnt_1Hz <= 24'h0;
else if (Cnt_1Hz < Diveider) Cnt_1Hz <= Cnt_1Hz + 1'b1;
else Cnt_1Hz <= 24'h0;
end
always @(posedge Sys_Clk or negedge Sys_Rst) begin
if (!Sys_Rst) begin
LED_G1 <= 1'b1;
LED_G2 <= 1'b1;
LED_R1 <= 1'b1;
LED_R2 <= 1'b1;
end else if (Left == 1'b0 && Right == 1'b1 && Emer == 1'b1) begin
if (Cnt_1Hz == Diveider) begin
LED_G1 <= ~LED_G1;
LED_G2 <= 1'b1;
LED_R1 <= ~LED_R1;
LED_R2 <= 1'b1;
end else begin
LED_G1 <= LED_G1;
LED_G2 <= 1'b1;
LED_R1 <= LED_R1;
LED_R2 <= 1'b1;
end
end else if (Left == 1'b1 && Right == 1'b0 && Emer == 1'b1) begin
if (Cnt_1Hz == Diveider) begin
LED_G1 <= 1'b1;
LED_G2 <= ~LED_G2;
LED_R1 <= 1'b1;
LED_R2 <= ~LED_R2;
end else begin
LED_G1 <= 1'b1;
LED_G2 <= LED_G2;
LED_R1 <= 1'b1;
LED_R2 <= LED_R2;
end
end else if (Left == 1'b1 && Right == 1'b1 && Emer == 1'b0) begin
if (Cnt_1Hz == Diveider) begin
LED_G1 <= 1'b1;
LED_G2 <= 1'b1;
LED_R1 <= ~LED_R1;
LED_R2 <= ~LED_R2;
end else begin
LED_G1 <= 1'b1;
LED_G2 <= 1'b1;
LED_R1 <= LED_R1;
LED_R2 <= LED_R2;
end
end else begin
LED_G1 <= 1'b1;
LED_G2 <= 1'b1;
LED_R1 <= 1'b1;
LED_R2 <= 1'b1;
end
end
endmodule
| 6.772116 |
module bACS_213.v
ACS Block for (2,1,3) backward label decoder
============================================================*/
`timescale 1 ns/1 ns
module bACS_213 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
ae, clock, reset);
`include "params_b213.inc.v"
output [`W-1:0] acs_ppm_out;
output [`k-1:0] acs_Bx_out;
input [`W-1:0] acs_ppm_ina;
input [`W-1:0] acs_ppm_inb;
input [1:0] HD_ina;
input [1:0] HD_inb;
input ae;
input clock;
input reset;
reg [`W-1:0] acs_ppm_out;
reg [`k-1:0] acs_Bx_out;
reg [`W-1:0] suma;
reg [`W-1:0] sumb;
always @(posedge clock or posedge reset)
begin
if (reset)
suma <=0;
else
begin
if (ae && acs_ppm_ina==4'b1111)
suma <= acs_ppm_ina;
else if (ae)
suma <= acs_ppm_ina + HD_ina;
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
sumb <=0;
else
begin
if (ae && acs_ppm_inb ==4'b1111)
sumb <=acs_ppm_inb;
else if (ae)
sumb <= acs_ppm_inb + HD_inb;
end
end
always @(suma or sumb)
begin
if (suma <=sumb && ae)
begin
acs_ppm_out =suma;
acs_Bx_out =1'b0; //Select Upper Backward Path
end
else
begin
acs_ppm_out =sumb;
acs_Bx_out =1'b1; //Select Lower Backward Path
end
end
endmodule
| 6.550346 |
module bACS_322.v
ACS Block for (3,2,2) backward label decoder
============================================================*/
`timescale 1 ns/1 ns
module bACS_322 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
acs_ppm_inc, HD_inc, acs_ppm_ind, HD_ind,
ae, reset, clock);
`include "params_b322.inc"
output [`W-1:0] acs_ppm_out;
output [`k-1:0] acs_Bx_out;
input [`W-1:0] acs_ppm_ina;
input [`W-1:0] acs_ppm_inb;
input [`W-1:0] acs_ppm_inc;
input [`W-1:0] acs_ppm_ind;
input [`W-1:0] HD_ina;
input [`W-1:0] HD_inb;
input [`W-1:0] HD_inc;
input [`W-1:0] HD_ind;
input ae;
input reset;
input clock;
reg [`W-1:0] acs_ppm_out;
reg [`W-1:0] acs_ppm_ab;
reg [`W-1:0] acs_ppm_cd;
reg [`k-1:0] acs_Bx_out;
reg [`k-1:0] acs_Bx_ab;
reg [`k-1:0] acs_Bx_cd;
reg [`W-1:0] suma;
reg [`W-1:0] sumb;
reg [`W-1:0] sumc;
reg [`W-1:0] sumd;
always @(posedge clock or posedge reset)
begin
if (reset)
suma <=0;
else
begin
if (ae && acs_ppm_ina==4'b1111)
suma <= acs_ppm_ina;
else if (ae)
suma <= acs_ppm_ina + HD_ina;
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
sumb <=0;
else
begin
if (ae && acs_ppm_inb==4'b1111)
sumb <= acs_ppm_inb;
else if (ae)
sumb <= acs_ppm_inb + HD_inb;
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
sumc <=0;
else
begin
if (ae && acs_ppm_inc==4'b1111)
sumc <= acs_ppm_inc;
else if (ae)
sumc <= acs_ppm_inc + HD_inc;
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
sumd <=0;
else
begin
if (ae && acs_ppm_ind==4'b1111)
sumd <= acs_ppm_ind;
else if (ae)
sumd <= acs_ppm_ind + HD_ind;
end
end
always @(suma or sumb or sumc or sumd)
begin
if (suma <=sumb)
begin
acs_ppm_ab =suma;
acs_Bx_ab =2'b00;
end
else
begin
acs_ppm_ab =sumb;
acs_Bx_ab =2'b01;
end
if (sumc <=sumd)
begin
acs_ppm_cd =sumc;
acs_Bx_cd =2'b10;
end
else
begin
acs_ppm_cd =sumd;
acs_Bx_cd =2'b11;
end
end
always @(acs_ppm_ab or acs_ppm_cd)
begin
if (acs_ppm_ab <= acs_ppm_cd)
begin
acs_ppm_out = acs_ppm_ab;
acs_Bx_out = acs_Bx_ab;
end
else
begin
acs_ppm_out = acs_ppm_cd;
acs_Bx_out = acs_Bx_cd;
end
end
endmodule
| 6.549033 |
module fsm (
clock,
reset,
start,
done_flag,
match_address,
inc_flag,
location,
outcell
);
input clock; // 100 Mhz clock
input reset; // resets the fsm
input start; // starts the search
input [8:0] match_address; // address for the pattern match
input done_flag; // signal from compare module saying it has finished
// its search
output inc_flag; // used to increment the address location
output [8:0] location; // location output for pattern match
output [8:0] outcell; // A hash on location
reg [8:0] location, outcell;
reg current_state, next_state;
reg inc_flag;
reg signal;
parameter s0 = 0, s1 = 1;
always @(posedge clock or negedge reset) begin
if (!reset) current_state = s0;
else begin
current_state = next_state;
end
end
always @(current_state or start or done_flag or match_address) begin
case (current_state)
s0: begin
if (start) begin
next_state = s1;
end else begin
location = 9'd0;
inc_flag = 0;
next_state = s0;
end
end
s1: begin
location = match_address;
inc_flag = 1;
if (done_flag) begin
next_state = s0;
end else begin
next_state = s1;
end
end
endcase
end
always @(posedge clock) outcell = location ^ (location << 1);
always @(done_flag) signal = done_flag & (^location[4:2]);
endmodule
| 7.229634 |
module for fsm
module test_fsm;
reg reset, clock, start, done_flag;
reg [8:0] match_address;
wire [8:0] location, outcell;
initial
begin
/* Comments to include for Unix */
$shm_open("waves.shm"); // save shm data base to mem.sav
$shm_probe ("AS"); // save all signals in the hierarchy, A = save all top level signals
/* Comments to include for Windows
$vw_dumpfile("test.vwf");
$vw_dumpvars();
*/
clock = 0;
reset = 1;
done_flag = 0;
start = 0;
match_address = 9'd0;
#1 reset = 0;
#9 reset = 1;
#40 start = 1;
#10 start = 0;
match_address = 9'd1;
#10 match_address = 9'd2;
#10 match_address = 9'd3;
#10 match_address = 9'd4;
#10 match_address = 9'd5;
#10 match_address = 9'd6;
#10 match_address = 9'd7;
#10 match_address = 9'd8;
#10 match_address = 9'd9;
#10 match_address = 9'd511;
done_flag = 1;
#40 reset = 0;
#10 reset = 1;
#40 $finish;
/* Comment to include for Unix */
$shm_close();
end
always #5 clock = ~clock;
fsm u1 (clock, reset, start, done_flag, match_address, inc_flag, location, outcell);
endmodule
| 7.007712 |
module badge_trace (
// Diagnostic input
input badge_clk,
input badge_stb,
input [7:0] badge_data,
// Arbitrary domain
input trace_reset,
// Local bus side
input lb_clk,
input [23:0] lb_addr,
input lb_rd,
output [7:0] lb_result
);
// Time since boot, wrap every 34.4 seconds
// runs in badge_clk domain so it can be written along with the badge
reg [31:0] tick_counter = 0; // 32'h03ffffc0;
always @(posedge badge_clk) tick_counter <= tick_counter + 1;
reg [31:0] time_sr = 0;
reg badge_stb_r = 0;
reg [7:0] badge_stb_chain = 0;
wire first_stb = badge_stb & ~(|badge_stb_chain[7:0]);
wire times_stb = |badge_stb_chain[6:3];
always @(posedge badge_clk) begin
badge_stb_chain <= {badge_stb_chain[6:0], first_stb};
if (first_stb) time_sr <= tick_counter;
if (times_stb) time_sr <= {time_sr[23:0], 8'b0};
end
// Debug trace memory
parameter daw = 12; // debug address width
reg dbg_rst = 0;
reg [daw-1:0] badge_cnt = 0;
reg [7:0] dbg_mem[0:(1<<daw)-1];
reg trace_reset_r = 0; // 1-bit absorb into badge_clk domain
wire [7:0] write_data = times_stb ? time_sr[31:24] : badge_data;
always @(posedge badge_clk) begin
trace_reset_r <= trace_reset;
if (trace_reset_r) badge_cnt <= 0;
if (badge_stb | times_stb) begin
dbg_mem[badge_cnt] <= write_data;
// once memory is filled up, stop
if (~(&badge_cnt)) badge_cnt <= badge_cnt + 1;
end
end
// Readout of memory plane
reg [7:0] result_r = 0;
always @(posedge lb_clk) if (lb_rd) result_r <= dbg_mem[lb_addr[daw-1:0]];
assign lb_result = result_r;
endmodule
| 7.434011 |
module badge_trace_tb;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("badge_trace.vcd");
$dumpvars(5, badge_trace_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 150; cc = cc + 1) begin
clk = 0;
#4;
clk = 1;
#4;
end
$display("PASS");
$finish(0);
end
wire ibadge_clk = clk;
reg dbg_rst = 0;
reg ibadge_stb = 0;
reg [7:0] ibadge_data;
wire pre_stb = (cc + 10) % 30 < 4;
always @(posedge clk) begin
ibadge_stb <= pre_stb;
ibadge_data <= pre_stb ? $random : 8'bx;
end
// Local bus not (yet?) used
wire lb_clk = clk;
reg [23:0] lb_addr = 0;
reg do_rd = 0;
wire [7:0] lb_result;
badge_trace dut (
.badge_clk(ibadge_clk),
.trace_reset(dbg_rst),
.badge_stb(ibadge_stb),
.badge_data(ibadge_data),
.lb_clk(lb_clk),
.lb_addr(lb_addr),
.lb_rd(do_rd),
.lb_result(lb_result)
);
endmodule
| 6.792362 |
module bad_block_manage (
input rst,
clk,
input [23:0] erase_addr_row,
input en_erase_page,
input [4:0] state,
output reg end_bad_block_renew, //£״̬
output [11:0] bad_block_renew_addr,
output reg we_bad_block_renew,
output bad_block_renew_datain,
output reg en_bad_block_renew_transfer //MCUºĻ־ź
);
reg [11:0] bad_block_addr;
reg [ 1:0] i;
assign bad_block_renew_addr = bad_block_addr;
assign bad_block_renew_datain = (state == 17) ? 1 : 0;
always @(posedge clk or posedge rst) //ȷַ
begin
if (rst) bad_block_addr <= 0;
else if (state == 17) begin
if (en_erase_page) bad_block_addr <= erase_addr_row[18:7];
end else bad_block_addr <= 0;
end
always @(posedge clk or posedge rst) //weֵԱ֤ÿдramڵַѾֵΪַ
begin
if (rst) begin
we_bad_block_renew <= 0;
end_bad_block_renew <= 0;
en_bad_block_renew_transfer <= 0;
i <= 0;
end else if (state == 17)
if (i < 2) begin
we_bad_block_renew <= 0;
i <= i + 1;
end else if (i == 2) begin
we_bad_block_renew <= 1;
en_bad_block_renew_transfer <= 1;
i <= 3;
end else begin
end_bad_block_renew <= 1;
we_bad_block_renew <= 0;
en_bad_block_renew_transfer <= 0;
end
else begin
i <= 0;
we_bad_block_renew <= 0;
end_bad_block_renew <= 0;
en_bad_block_renew_transfer <= 0;
end
end
endmodule
| 7.107635 |
module addbit (
a,
b,
ci,
sum,
co
);
input a, b, ci;
output sum co;
wire a, b, ci, sum, co;
endmodule
| 7.120785 |
module bad_xor32 (
X,
Y,
Z
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] Z;
assign Z = X & ~Y; //this is not an xor!!!
endmodule
| 7.776366 |
module baggage_drop (
output [6 : 0] seven_seg1,
output [6 : 0] seven_seg2,
output [6 : 0] seven_seg3,
output [6 : 0] seven_seg4,
output [0 : 0] drop_activated,
input [7 : 0] sensor1,
input [7 : 0] sensor2,
input [7 : 0] sensor3,
input [7 : 0] sensor4,
input [ 15:0] t_lim,
input drop_en
);
wire [ 7:0] height;
wire [15:0] aux;
sensors_input modulul1_sensors_input (
.height (height),
.sensor1(sensor1),
.sensor2(sensor2),
.sensor3(sensor3),
.sensor4(sensor4)
);
square_root modulul2_square_root (
.out(aux),
.in (height)
);
display_and_drop modulul3_display_drop (
.seven_seg1(seven_seg1),
.seven_seg2(seven_seg2),
.seven_seg3(seven_seg3),
.seven_seg4(seven_seg4),
.drop_activated(drop_activated),
.t_lim(t_lim),
.t_act(aux / 2),
.drop_en(drop_en)
);
endmodule
| 7.194924 |
module implements the filter window,mask, in addition to the row buffers
........................
By: Abdullah Al-Dujaili
NTU, 2012
.......................
Importantn note :=============================
This filter mask is designed espeically for 7*7 filter mask
as there are multiplexers that are difficult to make them parameterize for the time being
*/
module bailey_scheme_mask
#( parameter ROW_WIDTH = 100, // # pixel per row
PIX_BIT = 8, // # pixel bits
MASK_WIDTH= 7 // # mask Width
)
(
input wire clk,reset, // clk and reset
input wire ctrl2buf_valid, // indicates if the incoming pixel is valid
input wire sel_top_row, // selector signal for mux that deals with top pixel cases
input wire [1:0] sel_btm_row, // selector signal for mux that deals with btm pixel cases
input wire [PIX_BIT-1:0] data_cu2bufcf, // incoming pixel
input wire [1:0] sel_right_col, // selector signal to deal with pixels along the most right column through mirror without duplicate scheme
input wire sel_left_col, // selector signal to deal with pixels along the most left column through mirror without duplication scheme
output wire [PIX_BIT*(MASK_WIDTH**2)-1:0] p_m2f // actual/mirrored pixels to be routed to the filter function
);
// Internal signals between mask and row buffers:
wire [PIX_BIT*MASK_WIDTH-1:0] sngl_col_masked_pixs_buf2msk;
//Unit Instantiations of both row buffers and window mask using bailey border scheme:
//----------------------------------------------------------------------------------
//1. Row buffers (to store incoming pixels to do the necessary convolution)
row_buffers//_no_temp
#(.ROW_WIDTH(ROW_WIDTH), // # pixel per row
.PIX_BIT(PIX_BIT), // # pixel bits
.MASK_WIDTH(MASK_WIDTH)) // # mask Width
row_buffers_u
(
.clk(clk),.reset(reset), // clk and reset
.pix_in_valid(ctrl2buf_valid), // indicates if the incoming pixel is valid
.sel_top_row(sel_top_row), // selector signal for mux that deals with top pixel cases
.sel_btm_row(sel_btm_row), // selector signal for mux that deals with btm pixel cases
.pix_in(data_cu2bufcf), // incoming pixel
.sngl_col_masked_pixs_out(sngl_col_masked_pixs_buf2msk) //masked pixels out of the row buffers (one from each row)/ one column of the mask
);
//----------------------------------------------------------------------
//2. Filter Mask:
filter_mask
#(.PIX_BIT(PIX_BIT), //# pixel bits
.MASK_WIDTH(MASK_WIDTH) // mask width
) mask_u
(
.clk(clk),.reset(reset), // clk reset signals
.sngl_col_masked_pixs_in(sngl_col_masked_pixs_buf2msk), // pixels coming from each row of the buffers & the incoming pixel (one pixel each)
.sel_right_col(sel_right_col), // selector signal to deal with pixels along the most right column through mirror without duplicate scheme
.sel_left_col(sel_left_col), // selector signal to deal with pixels along the most left column through mirror without duplication scheme
.masked_pixs_out(p_m2f) // actual/mirrored pixels to be routed to the filter function
);
//----------------------------------------------------------------------------
endmodule
| 7.842559 |
module bakingState (
input clk,
input [1:0] state,
input [9:0] timerVal,
input [9:0] inputTemp,
output reg [3:0] tempVal0,
tempVal1,
tempVal2,
tempVal3,
output reg readyLight = 0
);
reg [9:0] currentTemp = 65; //variable to store temp, default temp is 65
reg [9:0] counter = 0; //counter variable
reg [1:0] timerComplete = 0; //timer complete variable to check when timer is done
secondsClock clock4 (
clk,
clock
);
always @(posedge clock) begin
if (state == 2) begin //make sure baking state is enabled
if(currentTemp == inputTemp) begin //check to make sure that the oven has reached the defined temp before starting the clock
if (counter < timerVal) begin //every second add 1 to the timer
counter = counter + 1;
end else if(timerComplete == 0) begin //make sure that timerComplete is not already set to 1
timerComplete = 1; //if counter is equal to the inputted value set timerComplete to 1
end
tempVal3 = ((timerVal - counter) / 60) / 10; //calculate hour (10s) for seven seg
tempVal2 = ((timerVal - counter) / 60) % 10; //calculate hour for seven seg
tempVal1 = ((timerVal - counter) % 60) / 10; //calculate minute (10s) for seven seg
tempVal0 = ((timerVal - counter) % 60) % 10; //calculate minute for seven seg
readyLight <= 1; //turn on bake light
end
if (timerComplete == 0 && currentTemp != inputTemp) begin
if (currentTemp + 2 >= inputTemp) begin //if the currentTemp + 2 is going to be higher then the inputTemp then set the currentTemp to the inputTemp so it does not go over
currentTemp <= inputTemp;
end else if (currentTemp < inputTemp) begin //every second add 2 to the temp input
currentTemp <= currentTemp + 2;
end
tempVal0 <= currentTemp % 10; //turn the current temp values into seperate digits to be displayed by the sevenSeg
tempVal1 <= (currentTemp / 10) % 10;
tempVal2 <= (currentTemp / 100) % 10;
tempVal3 <= 11;
end else if(timerComplete == 1) begin //if timer is complete then lower the oven temp by 2 every second until it reaches 65.
if(currentTemp - 2 <= 65) begin //if the currentTemp - 2 is going to be lower then the 65 (ambient) then set the currentTemp to the 65 as so it does not go under
currentTemp <= 65;
end else if (currentTemp > 65) begin //remove 2 from the current temp every second
readyLight <= 0; //turn off bake light
currentTemp <= currentTemp - 2;
end
tempVal0 <= currentTemp % 10; //turn the current temp values into seperate digits to be displayed by the sevenSeg
tempVal1 <= (currentTemp / 10) % 10;
tempVal2 <= (currentTemp / 100) % 10;
tempVal3 <= 11;
end
end
end
endmodule
| 6.935915 |
module balanced_adder_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / 2) tb_clk = ~tb_clk;
//reg[10:0] k;
// DUT
wire [`DATA_WIDTH*`N-1 : 0] outp;
wire [`DATA_WIDTH*(2**`N) - 1 : 0] inps;
balanced_adder_test #(
.data_width(`DATA_WIDTH),
.N(`N)
) my_adder (
.clk(tb_clk),
.outp(outp),
.outp_inps(inps)
);
// display inputs and output on each clock cycle
always @(posedge tb_clk) begin
$display("inps = ", inps, " => outp = ", outp);
// for (k = 1; k <= 2**(N-1); k = k + 1) begin
//$display("inps = ", inps[k*`DATA_WIDTH-1:(k-1)*`DATA_WIDTH], " => outp = ", outp);
// end
end
endmodule
| 6.768636 |
module balanced_adder_test #(
parameter data_width = 8,
N = 4
) (
input wire clk,
output wire [data_width*N - 1:0] outp,
output wire [(2**N)*data_width-1:0] outp_inps
);
reg [(2**N)*data_width-1:0] count;
initial begin
count = 0;
end
initial count = 32;
always @(posedge clk) count <= count + 1;
assign outp_inps = count;
balance_tree_adder #(
.N (N),
.DW(data_width)
) my_past_sequence_adder (
.clk (clk),
.inp (count),
.outp(outp)
);
endmodule
| 6.768636 |
module balance_tree_adder #(
parameter N = 4,
DW = 8
) (
input wire clk,
input wire [(2**N)*DW - 1 : 0] inp,
output reg [N*DW - 1 : 0] outp
);
reg [DW*N-1:0] regs[2:2**N]; //
reg [N-1:0] k;
reg [10:0] m;
reg [10:0] j;
genvar i;
wire [DW-1:0] arra[0:2**N-1];
generate
for (i = 0; i <= 2 ** N - 1; i = i + 1) begin : input_partition
assign arra[i] = inp[i*DW+DW-1:i*DW];
end
endgenerate
always @(posedge clk) begin
// j=N-1
outp <= regs[2] + regs[3];
for (j = 1; j <= N - 2; j = j + 1) begin
for (k = 0; k <= 2 ** j - 1; k = k + 1) begin
regs[2**j+k] <= regs[2**(j+1)+2*k] + regs[2**(j+1)+2*k+1];
end
end
for (m = 0; m <= 2 ** (N - 1) - 1; m = m + 1) begin
regs[2**(N-1)+m] <= arra[2*m] + arra[2*m+1];
end
end
endmodule
| 7.963914 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
LEDR,
HEX0,
HEX1,
HEX2,
HEX3
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [9:0] LEDR;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
// hex_decoder hex0(x[3:0], HEX0[6:0]);
// hex_decoder hex1(x[7:4], HEX1[6:0]);
// hex_decoder hex2(y[3:0], HEX2[6:0]);
// hex_decoder hex3(y[6:4], HEX3[6:0]);
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// wire left, right;
// assign left = !KEY[3];
// assign right = !KEY[2];
wire draw_done, draw, move_done;
control_ball c1 (
.clk(CLOCK_50),
.resetn(resetn),
.go(1'b1),
.draw_done(draw_done),
.move_done(move_done),
.enable_color(enable_color_ball),
.enable_move(enable_move_ball),
.writeEn(writeEn),
.draw(draw),
.done(ball_done)
);
datapath_ball p0 (
.clk(CLOCK_50),
.resetn(resetn),
.enable_color(enable_color_ball),
.enable_move(enable_move_ball),
.draw(draw),
.x_out(x),
.y_out(y),
.color_out(colour),
.draw_done(draw_done),
.move_done(move_done)
);
// assign LEDR[1] = en_pad;
// assign LEDR[2] = paddle_done;
assign LEDR[1] = ball_done;
assign LEDR[0] = move_done;
// assign LEDR[7] = hold;
// assign LEDR[8] = hold1;
// assign LEDR[9] = draw_hold;
// assign LEDR[9] = hold;
// assign LEDR[0] = enable_color;
// assign LEDR[1] = enable_move;
// assign LEDR[2] = writeEn;
endmodule
| 8.621551 |
module control_ball (
input clk,
resetn,
go,
draw_done,
move_done,
output reg enable_color,
enable_move,
writeEn,
draw,
output reg done
// output hold, hold1
);
wire hold, hold1;
timer_l t002 (
.clk(clk),
.resetn(reset),
.enable(1'b1),
.dividend(26'd16),
.time_up(hold)
);
timer_l t003 (
.clk(clk),
.resetn(reset1),
.enable(1'b1),
.dividend(26'd1000000),
.time_up(hold1)
);
reg [2:0] current_state, next_state;
always @(posedge clk) begin
if (!resetn) current_state <= DONE1;
else current_state <= next_state;
end
localparam WAIT = 4'd0, ERASE = 4'd1, MOVE = 4'd2, DRAW = 4'd3, DONE1 = 4'd4;
//state table
always @(*) begin : state_table
case (current_state)
WAIT: next_state = go ? ERASE : WAIT;
ERASE: next_state = draw_done ? MOVE : ERASE;
MOVE: next_state = hold1 ? DRAW : MOVE;
DRAW: next_state = draw_done ? DONE1 : DRAW;
DONE1: next_state = hold ? WAIT : DONE1;
endcase
end
reg reset, reset1;
always @(*) begin
writeEn = 1'b0;
enable_color = 1'b0;
enable_move = 1'b0;
writeEn = 1'b0;
draw = 1'b0;
reset = 1'b0;
done = 1'b0;
case (current_state)
WAIT: begin
end
ERASE: begin
writeEn = 1'b1;
draw = 1'b1;
// reset_erase_hold = 1'b1;
end
MOVE: begin
enable_move = 1'b1;
reset1 = 1'b1;
// reset_move_hold = 1'b1;
end
DRAW: begin
// reset_draw_hold = 1'b1;
enable_color = 1'b1;
writeEn = 1'b1;
draw = 1'b1;
end
DONE1: begin
done = 1'b1;
reset = 1'b1;
end
endcase
end
endmodule
| 7.010699 |
module datapath_ball (
input clk,
resetn,
enable_color,
enable_move,
draw,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out,
output draw_done,
move_done
);
wire [7:0] x_pos;
wire [6:0] y_pos;
xy_counter_ball movement (
.clk(clk),
.resetn(resetn),
.enable_move(enable_move),
.x_out(x_pos),
.y_out(y_pos)
// .move_done(move_done)
);
ball_draw data (
.clk (clk),
.draw (draw),
.x_in (x_pos),
.y_in (y_pos),
.x_out(x_out),
.y_out(y_out),
.done (draw_done)
);
assign color_out = enable_color ? 3'b111 : 3'b011;
endmodule
| 7.247038 |
module ball_draw (
input clk,
draw,
input [7:0] x_in,
input [6:0] y_in,
output [7:0] x_out,
output [6:0] y_out,
output done
);
reg [3:0] count;
assign resetn = draw;
always @(posedge clk) begin
if (!resetn) count <= 4'b0000;
else if (count == 1111) count <= 4'b0000;
else count <= count + 1'b1;
end
assign done = (count == 4'b1111); //// add more time; need reset time
assign x_out = x_in + count[1:0];
assign y_out = y_in + count[3:2];
endmodule
| 7.306498 |
module xy_counter_ball (
input clk,
resetn,
enable_move,
output reg [7:0] x_out,
output reg [6:0] y_out
// output move_done
);
// x_counter
reg done;
wire enable_move1;
assign enable_move1 = enable_move;
always @(posedge enable_move, negedge resetn) begin
if (!resetn) begin
x_out <= 8'd50;
y_out <= 7'd60;
end else begin
if (x_direction) x_out <= x_out + 1'b1;
else if (!x_direction) x_out <= x_out - 1'b1;
if (y_direction) y_out <= y_out + 1'b1;
else if (!y_direction) y_out <= y_out - 1'b1;
// done <= 1'b1;
end
// else if (!enable_move1)
// done <= 1'b0;
end
// assign move_done = enable_move & done;
// y_counter
// always@(posedge enable_move, negedge resetn) begin
// if (!resetn)
// else begin
// if (y_direction)
// y_out <= y_out + 1'b1;
// else
// y_out <= y_out - 1'b1;
// end
// end
reg x_direction;
reg y_direction;
// x_direction
always @(posedge clk) begin
if (!resetn) x_direction <= 1;
else begin
if (x_direction) begin
if (x_out + 1'b1 > 8'd156) x_direction <= 1'b0;
else x_direction <= 1'b1;
end else begin
if (x_out == 8'd2) x_direction <= 1'b1;
else x_direction <= 1'b0;
end
end
end
// y_direction
always @(posedge clk) begin
if (!resetn) y_direction <= 1;
else begin
if (y_direction) begin
if (y_out + 1'b1 > 7'd116) y_direction <= 1'b0;
else y_direction <= 1'b1;
end else begin
if (y_out == 7'b0000000) y_direction <= 1'b1;
else y_direction <= 1'b0;
end
end
end
endmodule
| 7.032243 |
module ball (
input wire px_clk, // Pixel clock.
input wire [25:0] strRGB_i, // Input RGB stream.
input wire [ 9:0] pos_x, // X ball position.
input wire [ 9:0] pos_y, // Y ball position.
output wire [25:0] strRGB_o // Output RGB stream.
);
// Bits address alias.
`define YC 12:3
`define XC 22:13
`define RGB 25:23
`define VGA 22:0
// Ball color and dimension.
parameter [2:0] white = 3'b111;
parameter size_ball = 10;
// Output pipeline RGB stream register.
reg [25:0] strRGB_reg;
// Follow pipeline.
assign strRGB_o = strRGB_reg;
// Draw a ball in a RGB stream.
always @(posedge px_clk) begin
// Clone VGA stream input in a RGB stream register.
strRGB_reg[`VGA] <= strRGB_i[`VGA];
// Draw ball.
strRGB_reg[`RGB] <= (
(strRGB_i[`YC] > pos_y) && (strRGB_i[`YC] < pos_y+size_ball) &&
(strRGB_i[`XC] > pos_x) && (strRGB_i[`XC] < pos_x+size_ball)
) ? white : strRGB_i[`RGB];
end
endmodule
| 6.888453 |
module balloon( rst, clk, frame_end, x, y, bullet_x, bullet_y, bomb_x, bomb_y, en);
parameter START = 4;
parameter MAXV = 480;
parameter MAXH = 640;
parameter NUM_BULLETS = 10;
parameter NUM_BOMBS = 2;
//parameter MINX = 40;
//parameter MAXX = 550;
input clk, frame_end, rst;
//input [11*NUM_BULLETS-1:0] min;
input [11*NUM_BULLETS-1:0] bullet_x, bullet_y;
input [11*NUM_BOMBS-1:0] bomb_x, bomb_y;
output reg [10:0] x;
output reg [10:0] y;
output en;
//output reg [11:0] color;
localparam BWIDTH = 18;
localparam BHEIGHT = 24;
localparam BOMBH = 24;
localparam BOMBW = 16;
//`include "bl_colors.vh"
reg [31:0] frame_count;
wire [10:0] x_loc;
wire mov_en, change_x;
wire [10:0] x_loc_range;
reg [NUM_BULLETS-1:0] en_r;
reg [NUM_BOMBS-1:0] reverse_r;
wire reverse;
reg score_detected;
reg balloon_exit;
LFSR lfsr
(.i_Clk(clk),
.i_Enable(1'b1),
.i_Seed_DV(1'b0),
.i_Seed_Data(START), // Replication
.o_LFSR_Data(x_loc),
.o_LFSR_Done()
);
//always@(posedge clk) begin
// if (frame_count >= START) begin
// mov_en <= 1;
// end
// else begin
// mov_en <= 0;
// end
//end
assign mov_en = (frame_count >= START) ? 1'b1 : 1'b0;
assign change_x = (y==MAXV) ? 1'b1 : 1'b0;
assign x_loc_range = (x_loc < 510) ? x_loc : (x_loc%510);
always@(posedge clk) begin
if (rst) begin
frame_count <= 0;
x <= x_loc_range;
y <= MAXV;
end
else if (frame_end) begin
frame_count <= frame_count + 1;
x <= x;
if (mov_en & reverse)
y <= y + 1;
else if (mov_en)
y <= y - 1;
else
y <= y;
end
else if (change_x) begin
frame_count <= frame_count;
x <= x_loc_range;
y <= y;
end
else if (y==-11'd20) begin
frame_count <= frame_count;
x <= x;
y <= MAXV+20;
end
else if (y==MAXV+21 & reverse) begin
frame_count <= 0;
x <= x;
y <= MAXV+20;
end
// else if (mov_en) begin
// frame_count <= frame_count;
// x <= x;
// y <= y - 1;
// end
else begin
frame_count <= frame_count;
x <= x;
y <= y;
end
end
genvar i;
// collision detect
generate
for (i=0; i<NUM_BULLETS; i=i+1) begin
always@(posedge clk) begin
if (rst) begin
en_r[i] <= 1;
end
else if ((bullet_x[((i+1)*11)-1:i*11] > x) & (bullet_x[((i+1)*11)-1:i*11] < x+BWIDTH) & (bullet_y[((i+1)*11)-1:i*11] > y-10) & (bullet_y[((i+1)*11)-1:i*11] < y+BHEIGHT) & (en)) begin
en_r[i] <= 0;
end
else if (~en & y==-11'd20) begin
en_r[i] <= 1;
end
else begin
en_r[i] <= en_r[i];
end
end
end
endgenerate
genvar j;
// collision with bomb detect
generate
for (j=0; j<NUM_BOMBS; j=j+1) begin
always@(posedge clk) begin
if (rst) begin
reverse_r[j] <= 0;
end
else if ( ( (bomb_x[((j+1)*11)-1:j*11]-BWIDTH<x) & (bomb_x[((j+1)*11)-1:j*11]+BOMBW > x) ) & (bomb_y[((j+1)*11)-1:j*11]+BOMBH -y < 3) ) begin
reverse_r[j] <= 1;
end
else if (reverse & y==MAXV+20) begin
reverse_r[j] <= 0;
end
else begin
reverse_r[j] <= reverse_r[j];
end
end
end
endgenerate
assign en = &en_r;
assign reverse = |reverse_r;
always@(posedge clk)begin
if(rst)begin
score_detected <= 0;
balloon_exit <= 1;
end
else if(~en && score_detected==0 && balloon_exit==1)begin
score_detected <= 1;
balloon_exit <= 0;
end
else if(score_detected == 1)
score_detected <= 0;
else if(change_x)
balloon_exit <= 1;
else
score_detected <= 0;
// balloon_exit <= balloon_exit;
end
endmodule
| 7.467564 |
module BallUpdate #(
parameter SIZE_BALL = 16
) (
input wire px_clk, // pixel clock.
input wire endframe, // end of frame
output reg [9:0] x_ball, // X ball position.
output reg [9:0] y_ball // Y ball position.
);
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
// Border definition.
parameter border = 0;
parameter [9:0] x_ball_min = border;
parameter [9:0] x_ball_max = VISIBLECOLS - SIZE_BALL - border;
parameter [9:0] y_ball_min = border;
parameter [9:0] y_ball_max = VISIBLEROWS - SIZE_BALL - border;
//speed and direction regs;
reg [4:0] speed;
reg dx, dy;
// initialization of ball location, direction and speed
initial begin
x_ball <= (640 - SIZE_BALL) / 4;
y_ball <= (480 - SIZE_BALL) / 2;
dx <= 0;
dy <= 0;
speed <= 1;
end
//Block: Update Ball parameters
always @(posedge px_clk) begin
if (endframe) begin
// bounce with vertical borders
if (x_ball>=x_ball_max || x_ball>=(VISIBLECOLS-speed-border) || x_ball<border || x_ball<speed)
begin
dx = ~dx;
//mute = 0;
//code_sound <= pong;
end
// bounce with horizontal borders
if (y_ball>=y_ball_max || y_ball>=(VISIBLEROWS-speed-border) || y_ball<border || y_ball<speed)
begin
dy = ~dy;
//mute = 0;
//code_sound <= pong;
end
// update the X coordinate
if (dx == 0) x_ball = x_ball + speed;
else x_ball = x_ball - speed;
//update the X coordinate
if (dy == 0) y_ball = y_ball + speed;
else y_ball = y_ball - speed;
//inc velocities
// if (inc_vel && speed < 20)
// speed = speed +1;
// else
// if (dec_vel && speed > 0)
// speed = speed -1;
end
end
endmodule
| 8.61795 |
module top (
input RST, // active low
input CLK, // 12MHz clock
// VGA
output VGA_BLUE,
output VGA_GREEN,
output VGA_RED,
output VGA_HSYNC,
output VGA_VSYNC,
output LED1
);
// RST - pull up
wire reset;
SB_IO
#(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
)
reset_t
(
.PACKAGE_PIN(RST),
.D_IN_0(reset)
);
assign LED1 = !reset;
// -- VGA --
`ifdef VGAMODE1
parameter VGA_HSIZE = 640;
parameter VGA_VSIZE = 480;
`elsif VGAMODE2
parameter VGA_HSIZE = 1024;
parameter VGA_VSIZE = 600;
`elsif VGAMODE3
parameter VGA_HSIZE = 1024;
parameter VGA_VSIZE = 768;
`endif
wire vsync = VGA_VSYNC;
wire hsync = VGA_HSYNC;
wire red = VGA_RED;
wire green = VGA_GREEN;
wire blue = VGA_BLUE;
wire pclk;
reg [10:0] hpos;
reg [10:0] vpos;
wire display_on;
wire vsync, hsync;
VGASyncGen
`ifdef VGAMODE1
// 640x480@73Hz
#(.FDivider(83),
.QDivider(5),
.activeHvideo(640),
.activeVvideo(480),
.hfp(24),
.hpulse(40),
.hbp(128),
.vfp(9),
.vpulse(2),
.vbp(29))
`elsif VGAMODE2
// 1024x600@60Hz
#(.FDivider(66),
.QDivider(4),
.activeHvideo(1024),
.activeVvideo(600),
.hfp(48),
.hpulse(32),
.hbp(240),
.vfp(3),
.vpulse(10),
.vbp(12))
`elsif VGAMODE3
// 1024x768@60Hz (65MHz pixel clock)
#(.FDivider(49), // 12MHz base clock
.QDivider(3), //
.activeHvideo(1024),
.activeVvideo(768),
.hfp(24),
.hpulse(136),
.hbp(133),
.vfp(3),
.vpulse(6),
.vbp(29))
`endif
vga_generator(.clk(CLK),
.hsync(hsync),
.vsync(vsync),
.x_px(hpos),
.y_px(vpos),
.activevideo(display_on),
.px_clk(pclk));
// --
localparam BALL_SPEED = 2;
localparam BALL_SIZE = 4;
localparam ball_horiz_initial = VGA_HSIZE / 2;
localparam ball_vert_initial = VGA_VSIZE / 2;
// ball position
reg [10:0] ball_hpos = ball_horiz_initial;
reg [10:0] ball_vpos = ball_vert_initial;
// ball velocity vector
reg [10:0] ball_horiz_move = BALL_SPEED;
reg [10:0] ball_vert_move = BALL_SPEED;
wire ball_hgfx = ((hpos - ball_hpos) < BALL_SIZE) && ((hpos - ball_hpos) >= 0);
wire ball_vgfx = ((vpos - ball_vpos) < BALL_SIZE) && ((vpos - ball_vpos) >= 0);
// wire ball_gfx = ball_hgfx && ball_vgfx;
wire grid_gfx = (((hpos&7)==0) && ((vpos&7)==0));
reg prev_vsync;
always @(posedge pclk) begin
prev_vsync <= vsync;
if (prev_vsync && !vsync) begin
// ball collide
if (ball_hpos >= (VGA_HSIZE - BALL_SIZE)) ball_horiz_move = -BALL_SPEED;
else if (ball_hpos <= 0) ball_horiz_move = BALL_SPEED;
if (ball_vpos >= (VGA_VSIZE - BALL_SIZE)) ball_vert_move = -BALL_SPEED;
else if (ball_vpos <= 0) ball_vert_move = BALL_SPEED;
if (reset) begin
// add velocity vector to ball position
ball_hpos <= ball_hpos + ball_horiz_move;
ball_vpos <= ball_vpos + ball_vert_move;
end else begin
// reset ball position
ball_hpos <= ball_horiz_initial;
ball_vpos <= ball_vert_initial;
end
end
if (display_on) begin
red <= ball_hgfx;
green <= (grid_gfx | (ball_hgfx & ball_vgfx));
blue <= ball_vgfx;
end else begin
red <= 0;
green <= 0;
blue <= 0;
end
end
endmodule
| 7.429197 |
module ball_absolute_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
input wire [0 : 0] hpaddle, //
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
wire display_on;
wire [15:0] hpos;
wire [15:0] vpos;
reg [15:0] ball_hpos; // ball current X position
reg [15:0] ball_vpos; // ball current Y position
reg [15:0] ball_horiz_move = -2; // ball current X velocity
reg [15:0] ball_vert_move = 2; // ball current Y velocity
localparam ball_horiz_initial = 64; // ball initial X position
localparam ball_vert_initial = 64; // ball initial Y position
localparam BALL_SIZE = 4; // ball size (in pixels)
// video sync generator
hvsync_generator hvsync_gen (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
// update horizontal timer
always @(posedge vsync or posedge reset) begin
if (reset) begin
// reset ball position to center
ball_vpos <= ball_vert_initial;
ball_hpos <= ball_horiz_initial;
end else begin
// add velocity vector to ball position
ball_hpos <= ball_hpos + ball_horiz_move;
ball_vpos <= ball_vpos + ball_vert_move;
end
end
// vertical bounce
always @(posedge ball_vert_collide) begin
ball_vert_move <= -ball_vert_move;
end
// horizontal bounce
always @(posedge ball_horiz_collide) begin
ball_horiz_move <= -ball_horiz_move;
end
// offset of ball position from video beam
wire [15:0] ball_hdiff = hpos - ball_hpos;
wire [15:0] ball_vdiff = vpos - ball_vpos;
// ball graphics output
wire ball_hgfx = ball_hdiff < BALL_SIZE;
wire ball_vgfx = ball_vdiff < BALL_SIZE;
wire ball_gfx = ball_hgfx && ball_vgfx;
// collide with vertical and horizontal boundaries
// these are set when the ball touches a border
wire ball_vert_collide = ball_vpos >= (480 - (BALL_SIZE * 2));
wire ball_horiz_collide = ball_hpos >= (640 - (BALL_SIZE * 2));
// combine signals to RGB output
wire grid_gfx = (((hpos & 7) == 0) && ((vpos & 7) == 0));
wire r = display_on && (ball_hgfx | ball_gfx);
wire g = display_on && (grid_gfx | ball_gfx);
wire b = display_on && (ball_vgfx | ball_gfx);
assign rgb = {b, g, r};
endmodule
| 7.998896 |
module ball_cltr #(
parameter GAME_WIDTH = 480,
parameter GAME_HEIGHT = 272,
parameter BALL_SIZE = 10,
parameter CORR_X = 43, // hDE = 44~523 High
parameter CORR_Y = 12 // vDE = 13~284 High
) (
input clk,
input nrst,
input [9:0] vcnt,
input [9:0] hcnt,
input de,
input game_active,
output reg draw_Ball,
output reg [8:0] ball_X,
output reg [8:0] ball_Y
);
// Draw or Not
always @(de, hcnt, vcnt, nrst) begin
if (nrst == 1'd0) begin
draw_Ball <= 1'd0;
ball_X <= GAME_WIDTH / 2 - BALL_SIZE / 2 + CORR_X; // 279
ball_Y <= GAME_HEIGHT / 2 - BALL_SIZE / 2 + CORR_Y; // 144
end
else if (de == 1'd1) // Data is Valid
begin
if(hcnt > ball_X && hcnt <= ball_X + BALL_SIZE) // Ball X Location
begin
if (vcnt > ball_Y && vcnt <= ball_Y + BALL_SIZE) // Ball Y Location
draw_Ball <= 1'd1;
else draw_Ball <= 1'd0;
end else draw_Ball <= 1'd0;
end else // Data is Invalid
draw_Ball <= 1'd0;
end
// Ball Moving Logic
endmodule
| 7.222789 |
module looks at the video, selects red pixels, low-pass filters that, and
// then finds the center of the red object.
// The output is the placement of a marker (+ like symbol) overlaying the camera video.
module ball_detector (
input reset,
input [23:0] video_in, // RGB camera video, post-de-Bayer
input [19:0] vAddress, // Address of the current pixel being displayed. Pixel pointer.
input h_sync,
input v_sync,
input ball_clock,
input freeze, // Stop filling the ball_ram RAM with new image data. Freezes the display.
input active_area, // high when VGA is in the active area (not Hsync,Vsync...)
input vid_select, // Selects camera video, or ball_ram video image.
output reg [23:0] video_out, // output to VGA generator
//
output [6:0] EX_IO, // De-bug signals out to pins
input [17:0] SW
);
wire [8:0] horz_line; // row number of the middle of the red object.
wire [9:0] vert_line;
wire seems_red;
wire [7:0] RED;
wire [7:0] GREEN;
wire [7:0] BLUE;
wire ram_seems_red; // stored value of seems_red in the ball_ram.
wire [9:0] h_value;
wire [8:0] v_value;
assign RED = video_in[23:16];
assign GREEN = video_in[15:8];
assign BLUE = video_in[7:0];
red_frame u1 (
.VGA_clock( ball_clock ),
.reset( reset ),
.pixel_data( video_in ),
.h_sync( h_sync ),
.v_sync( v_sync ),
.x_cont( h_value ),
.y_cont( v_value ),
.red_pixel( seems_red ), // This is the output of red_frame. Low-pass filtered red detection.
.horz_line( horz_line ),
.vert_line( vert_line ),
.filter_on( SW[15] ),
.EX_IO( EX_IO )
);
// Mux. Combinatorial logic to select the camera video, or, the red ball detector video frame.
always @(*) begin
if( vid_select == 1'b0 ) begin
if( (h_value == vert_line) || (v_value == horz_line) )
video_out = { 8'b0111_1111, 8'b0111_1111, 8'b0111_1111 };
else
video_out = { RED[7:0], GREEN[7:0], BLUE[7:0] };
end
else begin
if( (h_value == vert_line) || (v_value == horz_line) )
video_out = { 8'b0111_1111, 8'b0111_1111, 8'b0111_1111 };
else
video_out = { 1'b0, {7{ram_seems_red}}, {2{1'b0}}, {6{ram_seems_red}}, {2{1'b0}}, {6{ram_seems_red}} };
end
end
// Create a two-port RAM (ball_ram)). 1x640x480 bits.
// Input = Camera image, but red-detected and low-pass filtered by red_frame.v.
// Each pixel is 1 or 0, depending on red value.
// Output feeds the VGA waveform generator.
ball_ram this_ball_ram(
.clock( ball_clock ),
.data( seems_red ),
.rdaddress( vAddress ),
.rden( h_sync || v_sync ), // is high when VGA generator is in the active area
.wraddress( vAddress /*>= 1 ? VGA_ADDRESS-1 : VGA_ADDRESS*/ ), // counters that track the output of the SDRAM
.wren( active_area & ~freeze ),
.q( ram_seems_red )
);
Mod_counter #(.N(10), .M(640)) h_count (
.clk( ball_clock ),
.clk_en( h_sync ),
.reset( ~h_sync ),
.max_tick( ), // output when final count is reached
.q( h_value ) // horizontal (column) pixel counter, 0 to 639
);
Mod_counter #(.N(9), .M(480)) v_count (
.clk( h_sync ),
.clk_en( v_sync ),
.reset( ~v_sync ),
.max_tick( ), // output when final count is reached
.q( v_value ) // vertical (row) pixel counter, 0 to 479
);
Mod_counter #(.N(19), .M(307200)) pixel_count (
.clk( ball_clock ),
.clk_en( h_sync & v_sync ),
.reset( ~v_sync ),
.max_tick( ), // output when final count is reached
.q() // counter output [N-1:0]
);
//assign EX_IO[0] = ball_clock;
//assign EX_IO[1] = h_sync;
//assign EX_IO[2] = h_value[0];
//assign EX_IO[3] = h_value[1];
//assign EX_IO[4] = h_value[2];
//assign EX_IO[5] = h_value[3];
//assign EX_IO[6] = h_value==5 ? 1'b1 : 1'b0;
endmodule
| 8.319226 |
module ball (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn; //VGA reset low
assign resetn = SW[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(~resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
wire clear_signal, enable, enable_erase, enable_update, enable_fcounter, next_box, y_count_done, next_boxx;
// Instansiate datapath
// datapath d0(...);
datapath d1 (
.clock(CLOCK_50),
.reset_n(resetn),
.enable(enable),
.enable_erase(enable_erase),
.enable_update(enable_update),
.enable_fcounter(enable_fcounter),
.x_out(x),
.y_out(y),
.colour_out(colour),
.y_count_done(y_count_done)
);
control_draw c1 (
.go(~KEY[1]),
.clock(CLOCK_50),
.reset_n(resetn),
.enable(enable),
.write_en(writeEn),
.enable_erase(enable_erase),
.enable_update(enable_update),
.enable_fcounter(enable_fcounter),
.next_box(next_box),
.y_count_done(y_count_done),
.clear_signal(clear_signal)
);
frame_counter f1 (
.clock(CLOCK_50),
.enable(enable_fcounter),
.resetn(resetn),
.signal_out(next_box),
.clear_signal(clear_signal)
);
frame_counter f2 (
.clock(CLOCK_50),
.enable(enable_fcounter),
.resetn(resetn),
.signal_out(next_boxx),
.clear_signal(clear_signal)
);
endmodule
| 7.911761 |
module datapath (
clock,
reset_n,
x_out,
y_out,
enable_erase,
enable_update,
colour_out,
enable,
enable_fcounter,
y_count_done
);
input clock, reset_n, enable, enable_erase, enable_update, enable_fcounter;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] colour_out;
output reg y_count_done;
reg [7:0] x_inside;
reg [6:0] y_inside;
reg [2:0] colour_inside;
reg vertical;
reg horizontal;
reg [1:0] x_count;
reg [1:0] y_count;
//Register for x, y, colour
always @(posedge clock) begin
if (reset_n) begin
x_inside <= 8'b00000000;
y_inside <= 60;
colour_inside <= 3'b100;
vertical <= 1; //up
horizontal <= 1; //right
x_count = 2'b00;
y_count = 2'b00;
end else begin
if (enable_erase) begin
colour_inside <= 3'b010;
end
if (!enable_erase) begin
colour_inside <= 3'b100;
end
if (enable_update) begin
//update x_insde, y_inside
if (vertical == 1'b1) begin
y_inside <= y_inside - 1'b1;
end
if (horizontal == 1'b1) begin
x_inside <= x_inside + 1'b1;
end
end
if (y_count_done == 1 || enable_fcounter) begin
x_count <= 2'b00;
y_count <= 2'b00;
end
end
end
wire y_enable;
assign y_enable = (x_count == 2'b11) ? 1'b1 : 1'b0;
//Counter for x keeping the y coordinate the same.
always @(posedge clock) begin
if (reset_n) begin
x_count <= 2'b000;
y_count <= 2'b000;
end else if (enable == 1'b1) begin
if (y_enable == 1'b1) begin
if (y_count == 2'b11) begin
y_count_done <= 1'b1;
y_count <= 2'b00;
end else begin
y_count <= y_count + 1'b1;
y_count_done <= 0;
end
end
if (x_count == 2'b11) begin
x_count <= 2'b00;
end else begin
x_count <= x_count + 1'b1;
y_count_done <= 0;
end
end
end
//Now fixing x, we add all the y pixels.
//Counter for y
// always @(posedge clock)
// begin
// if(reset_n)
// begin
// //y_count_done <= 0;
// y_count <= 2'b000;
// //x_count <= 2'b000;
// end
// else if (y_enable == 1'b1 && enable == 1'b1)
// begin
// if (y_count == 2'b11) begin
// y_count_done <= 1'b1;
// y_count <= 2'b00;
// end
// else
// begin
// y_count <= y_count + 1'b1;
// y_count_done <= 0;
// end
// end
// end
// assign y_count_done = (y_count == 2'b11) ? 1 : 0;
assign colour_out = colour_inside;
assign x_out = x_inside + x_count;
assign y_out = y_inside + y_count;
endmodule
| 6.91752 |
module control_draw (
go,
next_boxx,
clock,
reset_n,
write_en,
enable,
enable_erase,
enable_update,
enable_fcounter,
next_box,
y_count_done,
clear_sig
);
input clock, reset_n, next_box, next_boxx, y_count_done, go;
output reg enable, write_en, enable_erase, enable_update, enable_fcounter, clear_sig;
reg [3:0] curr_state, next_state;
localparam DRAW = 4'd0, RESET_COUNTER = 4'd1, ERASE = 4'd2, UPDATE = 4'd3, RESET_COUNTERX = 4'd4;
// Next state logic aka our stRESET_COUNTERate table
always @(*) begin : state_table
case (curr_state)
DRAW: next_state = (y_count_done == 1) ? RESET_COUNTER : DRAW;
RESET_COUNTER: next_state = (next_box == 1) ? ERASE : RESET_COUNTER;
ERASE: next_state = (y_count_done == 1) ? UPDATE : ERASE;
//RESET_COUNTERX: next_state = (next_boxx == 1) ? DRAW : RESET_COUNTERX;
UPDATE: next_state = DRAW;
default: next_state = DRAW;
endcase
end // state_table
// Output logic aka all of our datapath control signals
always @(*) begin : enable_signalsmodule
// By default make all our signals 0
enable = 1'b0;
enable_erase = 1'b0;
write_en = 1'b0;
enable_update <= 0;
enable_fcounter <= 0;
clear_sig <= 0;
case (curr_state)
DRAW: begin
enable <= 1;
write_en <= 1;
end
RESET_COUNTER: begin
enable_fcounter <= 1;
end
ERASE: begin
write_en <= 1;
enable <= 1;
enable_erase <= 1;
clear_sig <= 1;
end
UPDATE: begin
enable_update <= 1;
end
// default: // don't need default since we already made sure all of our outputs were assigned a value at the start of the always block
endcase
end // enable_signals
// current_state registers
always @(posedge clock) begin : state_FFs
if (reset_n) curr_state <= DRAW;
else curr_state <= next_state;
end // state_FFS
endmodule
| 7.972248 |
module ball_lab9 (
clock,
reset_n,
x_out,
y_out,
colour_out
);
input clock, reset_n;
wire enable, write_en, enable_erase, enable_update, go, next_boxx, enable_fcounter, next_box, y_count_done, clear_sig;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] colour_out;
datapath d0 (
.clock(clock),
.reset_n(reset_n),
.enable(enable),
.enable_erase(enable_erase),
.enable_update(enable_update),
.enable_fcounter(enable_fcounter),
.x_out(x_out),
.y_out(y_out),
.colour_out(colour_out),
.y_count_done(y_count_done)
);
control_draw c0 (
.clock(clock),
.reset_n(reset_n),
.enable(enable),
.write_en(write_en),
.enable_erase(enable_erase),
.enable_update(enable_update),
.enable_fcounter(enable_fcounter),
.next_box(next_box),
.y_count_done(y_count_done),
.clear_sig(clear_sig),
.next_boxx(next_boxx),
.go(go)
);
frame_counter f0 (
.clock(clock),
.enable(enable_fcounter),
.resetn(reset_n),
.signal_out(next_box),
.clear_sig(clear_sig)
);
endmodule
| 7.438299 |
module ball_slipping_counter_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
input wire [0 : 0] hpaddle, //
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
wire display_on;
wire [15:0] hpos;
wire [15:0] vpos;
// 9-bit ball timers
reg [8:0] ball_htimer;
reg [8:0] ball_vtimer;
// 4-bit motion codes
reg [3:0] ball_horiz_move;
reg [3:0] ball_vert_move;
// 4-bit stop codes
localparam ball_horiz_stop = 4'd11;
localparam ball_vert_stop = 4'd10;
// 5-bit constants to load into counters
localparam ball_horiz_prefix = 5'b01100; // 192
localparam ball_vert_prefix = 5'b01111; // 240
// reset ball; will be unset when video beam reaches center position
reg ball_reset;
// video sync generator
hvsync_generator hvsync_gen (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
// update horizontal timer
always @(posedge clk or posedge ball_reset) begin
if (ball_reset || &ball_htimer) begin
if (ball_reset || &ball_vtimer) ball_htimer <= {ball_horiz_prefix, ball_horiz_move};
else ball_htimer <= {ball_horiz_prefix, ball_horiz_stop};
end else ball_htimer <= ball_htimer + 1;
end
always @(posedge hsync or posedge ball_reset) begin
if (ball_reset || &ball_vtimer) // reset timer
ball_vtimer <= {ball_vert_prefix, ball_vert_move};
else ball_vtimer <= ball_vtimer + 1;
end
always @(posedge clk or posedge reset) begin
if (reset) ball_reset <= 1;
else if (hpos == 128 && vpos == 128) ball_reset <= 0;
end
wire ball_vert_collide = ball_vgfx && vpos >= 240;
wire ball_horiz_collide = ball_hgfx && hpos >= 256 && vpos == 255;
always @(posedge ball_vert_collide or posedge reset) begin
if (reset) ball_vert_move <= 4'd9;
else ball_vert_move <= (4'd9 ^ 4'd11) ^ ball_vert_move;
end
always @(posedge ball_horiz_collide or posedge reset) begin
if (reset) ball_horiz_move <= 4'd10; // initial horizontal velocity
else ball_horiz_move <= (4'd10 ^ 4'd12) ^ ball_horiz_move; // change dir.
end
wire ball_hgfx = ball_htimer >= 508;
wire ball_vgfx = ball_vtimer >= 508;
wire ball_gfx = ball_hgfx && ball_vgfx;
// combine signals to RGB output
wire grid_gfx = (((hpos & 7) == 0) && ((vpos & 7) == 0));
wire r = display_on && (ball_hgfx | ball_gfx);
wire g = display_on && (grid_gfx | ball_gfx);
wire b = display_on && (ball_vgfx | ball_gfx);
assign rgb = {b, g, r};
endmodule
| 8.856362 |
module BrzAdapt_8_9_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inp_0r;
input inp_0a;
input [8:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[0] = inp_0d[0];
assign out_0d[1] = inp_0d[1];
assign out_0d[2] = inp_0d[2];
assign out_0d[3] = inp_0d[3];
assign out_0d[4] = inp_0d[4];
assign out_0d[5] = inp_0d[5];
assign out_0d[6] = inp_0d[6];
assign out_0d[7] = inp_0d[7];
endmodule
| 6.541301 |
module BrzAdapt_17_9_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output inp_0r;
input inp_0a;
input [8:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[9] = extend_0n;
assign out_0d[10] = extend_0n;
assign out_0d[11] = extend_0n;
assign out_0d[12] = extend_0n;
assign out_0d[13] = extend_0n;
assign out_0d[14] = extend_0n;
assign out_0d[15] = extend_0n;
assign out_0d[16] = extend_0n;
assign extend_0n = inp_0d[8];
assign out_0d[0] = inp_0d[0];
assign out_0d[1] = inp_0d[1];
assign out_0d[2] = inp_0d[2];
assign out_0d[3] = inp_0d[3];
assign out_0d[4] = inp_0d[4];
assign out_0d[5] = inp_0d[5];
assign out_0d[6] = inp_0d[6];
assign out_0d[7] = inp_0d[7];
assign out_0d[8] = inp_0d[8];
endmodule
| 6.657468 |
module BrzAdapt_17_18_s4_true_s4_true (
out_0r,
out_0a,
out_0d,
inp_0r,
inp_0a,
inp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output inp_0r;
input inp_0a;
input [17:0] inp_0d;
wire extend_0n;
assign out_0a = inp_0a;
assign inp_0r = out_0r;
assign out_0d[0] = inp_0d[0];
assign out_0d[1] = inp_0d[1];
assign out_0d[2] = inp_0d[2];
assign out_0d[3] = inp_0d[3];
assign out_0d[4] = inp_0d[4];
assign out_0d[5] = inp_0d[5];
assign out_0d[6] = inp_0d[6];
assign out_0d[7] = inp_0d[7];
assign out_0d[8] = inp_0d[8];
assign out_0d[9] = inp_0d[9];
assign out_0d[10] = inp_0d[10];
assign out_0d[11] = inp_0d[11];
assign out_0d[12] = inp_0d[12];
assign out_0d[13] = inp_0d[13];
assign out_0d[14] = inp_0d[14];
assign out_0d[15] = inp_0d[15];
assign out_0d[16] = inp_0d[16];
endmodule
| 6.571943 |
module BrzBinaryFunc_1_8_8_s11_GreaterThan_s5_fal_m43m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d,
inpB_0r,
inpB_0a,
inpB_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [7:0] inpB_0d;
wire [5:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_0n;
wire [8:0] c_0n;
wire [7:0] eq_0n;
wire [7:0] addOut_0n;
wire [7:0] w_0n;
wire [7:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply1 vdd;
NOR2_A I0 (
out_0d,
z_0n,
nxv_0n
);
XOR2_A I1 (
nxv_0n,
v_0n,
addOut_0n[7]
);
NOR3_A I2 (
internal_0n[0],
addOut_0n[0],
addOut_0n[1],
addOut_0n[2]
);
NOR3_A I3 (
internal_0n[1],
addOut_0n[3],
addOut_0n[4],
addOut_0n[5]
);
NOR2_A I4 (
internal_0n[2],
addOut_0n[6],
addOut_0n[7]
);
AND3_A I5 (
z_0n,
internal_0n[0],
internal_0n[1],
internal_0n[2]
);
NOR3_A I6 (
internal_0n[3],
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
NOR3_A I7 (
internal_0n[4],
nCv_0n[4],
nCv_0n[5],
nCv_0n[6]
);
NOR2_A I8 (
internal_0n[5],
nCv_0n[7],
nCv_0n[8]
);
AND3_A I9 (
done_0n,
internal_0n[3],
internal_0n[4],
internal_0n[5]
);
XOR2_A I10 (
v_0n,
c_0n[7],
c_0n[8]
);
balsa_fa I11 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I12 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I13 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
balsa_fa I14 (
nStart_0n,
n_0n[3],
w_0n[3],
nCv_0n[3],
c_0n[3],
nCv_0n[4],
c_0n[4],
addOut_0n[3]
);
balsa_fa I15 (
nStart_0n,
n_0n[4],
w_0n[4],
nCv_0n[4],
c_0n[4],
nCv_0n[5],
c_0n[5],
addOut_0n[4]
);
balsa_fa I16 (
nStart_0n,
n_0n[5],
w_0n[5],
nCv_0n[5],
c_0n[5],
nCv_0n[6],
c_0n[6],
addOut_0n[5]
);
balsa_fa I17 (
nStart_0n,
n_0n[6],
w_0n[6],
nCv_0n[6],
c_0n[6],
nCv_0n[7],
c_0n[7],
addOut_0n[6]
);
balsa_fa I18 (
nStart_0n,
n_0n[7],
w_0n[7],
nCv_0n[7],
c_0n[7],
nCv_0n[8],
c_0n[8],
addOut_0n[7]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vdd;
INV_A I21 (
nStart_0n,
start_0n
);
INV_A I22 (
n_0n[0],
inpB_0d[0]
);
INV_A I23 (
n_0n[1],
inpB_0d[1]
);
INV_A I24 (
n_0n[2],
inpB_0d[2]
);
INV_A I25 (
n_0n[3],
inpB_0d[3]
);
INV_A I26 (
n_0n[4],
inpB_0d[4]
);
INV_A I27 (
n_0n[5],
inpB_0d[5]
);
INV_A I28 (
n_0n[6],
inpB_0d[6]
);
INV_A I29 (
n_0n[7],
inpB_0d[7]
);
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign out_0a = done_0n;
c2 I39 (
start_0n,
inpA_0a,
inpB_0a
);
assign inpA_0r = out_0r;
assign inpB_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFunc_10_9_9_s3_Add_s4_true_s4_tru_m44m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d,
inpB_0r,
inpB_0a,
inpB_0d
);
input out_0r;
output out_0a;
output [9:0] out_0d;
output inpA_0r;
input inpA_0a;
input [8:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [8:0] inpB_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [9:0] nCv_0n;
wire [9:0] c_0n;
wire [8:0] eq_0n;
wire [8:0] addOut_0n;
wire [8:0] w_0n;
wire [8:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
NOR3_A I0 (
internal_0n[0],
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
NOR3_A I1 (
internal_0n[1],
nCv_0n[4],
nCv_0n[5],
nCv_0n[6]
);
NOR3_A I2 (
internal_0n[2],
nCv_0n[7],
nCv_0n[8],
nCv_0n[9]
);
AND3_A I3 (
done_0n,
internal_0n[0],
internal_0n[1],
internal_0n[2]
);
assign out_0d[0] = addOut_0n[0];
assign out_0d[1] = addOut_0n[1];
assign out_0d[2] = addOut_0n[2];
assign out_0d[3] = addOut_0n[3];
assign out_0d[4] = addOut_0n[4];
assign out_0d[5] = addOut_0n[5];
assign out_0d[6] = addOut_0n[6];
assign out_0d[7] = addOut_0n[7];
assign out_0d[8] = addOut_0n[8];
assign out_0d[9] = c_0n[9];
balsa_fa I14 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I15 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I16 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
balsa_fa I17 (
nStart_0n,
n_0n[3],
w_0n[3],
nCv_0n[3],
c_0n[3],
nCv_0n[4],
c_0n[4],
addOut_0n[3]
);
balsa_fa I18 (
nStart_0n,
n_0n[4],
w_0n[4],
nCv_0n[4],
c_0n[4],
nCv_0n[5],
c_0n[5],
addOut_0n[4]
);
balsa_fa I19 (
nStart_0n,
n_0n[5],
w_0n[5],
nCv_0n[5],
c_0n[5],
nCv_0n[6],
c_0n[6],
addOut_0n[5]
);
balsa_fa I20 (
nStart_0n,
n_0n[6],
w_0n[6],
nCv_0n[6],
c_0n[6],
nCv_0n[7],
c_0n[7],
addOut_0n[6]
);
balsa_fa I21 (
nStart_0n,
n_0n[7],
w_0n[7],
nCv_0n[7],
c_0n[7],
nCv_0n[8],
c_0n[8],
addOut_0n[7]
);
balsa_fa I22 (
nStart_0n,
n_0n[8],
w_0n[8],
nCv_0n[8],
c_0n[8],
nCv_0n[9],
c_0n[9],
addOut_0n[8]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = gnd;
INV_A I25 (
nStart_0n,
start_0n
);
assign n_0n[0] = inpB_0d[0];
assign n_0n[1] = inpB_0d[1];
assign n_0n[2] = inpB_0d[2];
assign n_0n[3] = inpB_0d[3];
assign n_0n[4] = inpB_0d[4];
assign n_0n[5] = inpB_0d[5];
assign n_0n[6] = inpB_0d[6];
assign n_0n[7] = inpB_0d[7];
assign n_0n[8] = inpB_0d[8];
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign w_0n[8] = inpA_0d[8];
assign out_0a = done_0n;
c2 I45 (
start_0n,
inpA_0a,
inpB_0a
);
assign inpA_0r = out_0r;
assign inpB_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFuncConstR_1_3_1_s9_NotEquals_s5__m25m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [2:0] inpA_0d;
wire start_0n;
wire nStart_0n;
wire [3:0] nCv_0n;
wire [3:0] c_0n;
wire [2:0] eq_0n;
wire [2:0] addOut_0n;
wire [2:0] w_0n;
wire [2:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
OR3_A I0 (
out_0d,
eq_0n[0],
eq_0n[1],
eq_0n[2]
);
XOR2_A I1 (
eq_0n[0],
w_0n[0],
n_0n[0]
);
XOR2_A I2 (
eq_0n[1],
w_0n[1],
n_0n[1]
);
XOR2_A I3 (
eq_0n[2],
w_0n[2],
n_0n[2]
);
assign done_0n = start_0n;
assign n_0n[1] = gnd;
assign n_0n[2] = gnd;
assign n_0n[0] = gnd;
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign out_0a = done_0n;
assign start_0n = inpA_0a;
assign inpA_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFuncConstR_1_8_1_s11_GreaterThan__m45m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [5:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_0n;
wire [8:0] c_0n;
wire [7:0] eq_0n;
wire [7:0] addOut_0n;
wire [7:0] w_0n;
wire [7:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply1 vdd;
AND2_A I0 (
out_0d,
c_0n[8],
nz_0n
);
NOR3_A I1 (
internal_0n[0],
addOut_0n[0],
addOut_0n[1],
addOut_0n[2]
);
NOR3_A I2 (
internal_0n[1],
addOut_0n[3],
addOut_0n[4],
addOut_0n[5]
);
NOR2_A I3 (
internal_0n[2],
addOut_0n[6],
addOut_0n[7]
);
NAND3_A I4 (
nz_0n,
internal_0n[0],
internal_0n[1],
internal_0n[2]
);
NOR3_A I5 (
internal_0n[3],
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
NOR3_A I6 (
internal_0n[4],
nCv_0n[4],
nCv_0n[5],
nCv_0n[6]
);
NOR2_A I7 (
internal_0n[5],
nCv_0n[7],
nCv_0n[8]
);
AND3_A I8 (
done_0n,
internal_0n[3],
internal_0n[4],
internal_0n[5]
);
balsa_fa I9 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I10 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I11 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
balsa_fa I12 (
nStart_0n,
n_0n[3],
w_0n[3],
nCv_0n[3],
c_0n[3],
nCv_0n[4],
c_0n[4],
addOut_0n[3]
);
balsa_fa I13 (
nStart_0n,
n_0n[4],
w_0n[4],
nCv_0n[4],
c_0n[4],
nCv_0n[5],
c_0n[5],
addOut_0n[4]
);
balsa_fa I14 (
nStart_0n,
n_0n[5],
w_0n[5],
nCv_0n[5],
c_0n[5],
nCv_0n[6],
c_0n[6],
addOut_0n[5]
);
balsa_fa I15 (
nStart_0n,
n_0n[6],
w_0n[6],
nCv_0n[6],
c_0n[6],
nCv_0n[7],
c_0n[7],
addOut_0n[6]
);
balsa_fa I16 (
nStart_0n,
n_0n[7],
w_0n[7],
nCv_0n[7],
c_0n[7],
nCv_0n[8],
c_0n[8],
addOut_0n[7]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vdd;
INV_A I19 (
nStart_0n,
start_0n
);
assign n_0n[2] = vdd;
assign n_0n[3] = vdd;
assign n_0n[4] = vdd;
assign n_0n[5] = vdd;
assign n_0n[6] = vdd;
assign n_0n[7] = vdd;
assign n_0n[0] = vdd;
assign n_0n[1] = vdd;
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign out_0a = done_0n;
assign start_0n = inpA_0a;
assign inpA_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFuncConstR_3_3_1_s8_Subtract_s5_f_m27m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [2:0] out_0d;
output inpA_0r;
input inpA_0a;
input [2:0] inpA_0d;
wire start_0n;
wire nStart_0n;
wire [3:0] nCv_0n;
wire [3:0] c_0n;
wire [2:0] eq_0n;
wire [2:0] addOut_0n;
wire [2:0] w_0n;
wire [2:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
supply1 vdd;
NOR3_A I0 (
done_0n,
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
assign out_0d[0] = addOut_0n[0];
assign out_0d[1] = addOut_0n[1];
assign out_0d[2] = addOut_0n[2];
balsa_fa I4 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I5 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I6 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vdd;
INV_A I9 (
nStart_0n,
start_0n
);
assign n_0n[2] = n_0n[1];
assign n_0n[0] = gnd;
assign n_0n[1] = vdd;
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign out_0a = done_0n;
assign start_0n = inpA_0a;
assign inpA_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFuncConstR_8_8_1_s3_Add_s5_false__m46m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_0n;
wire [8:0] c_0n;
wire [7:0] eq_0n;
wire [7:0] addOut_0n;
wire [7:0] w_0n;
wire [7:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
supply1 vdd;
NOR3_A I0 (
internal_0n[0],
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
NOR3_A I1 (
internal_0n[1],
nCv_0n[4],
nCv_0n[5],
nCv_0n[6]
);
NOR2_A I2 (
internal_0n[2],
nCv_0n[7],
nCv_0n[8]
);
AND3_A I3 (
done_0n,
internal_0n[0],
internal_0n[1],
internal_0n[2]
);
assign out_0d[0] = addOut_0n[0];
assign out_0d[1] = addOut_0n[1];
assign out_0d[2] = addOut_0n[2];
assign out_0d[3] = addOut_0n[3];
assign out_0d[4] = addOut_0n[4];
assign out_0d[5] = addOut_0n[5];
assign out_0d[6] = addOut_0n[6];
assign out_0d[7] = addOut_0n[7];
balsa_fa I12 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I13 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I14 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
balsa_fa I15 (
nStart_0n,
n_0n[3],
w_0n[3],
nCv_0n[3],
c_0n[3],
nCv_0n[4],
c_0n[4],
addOut_0n[3]
);
balsa_fa I16 (
nStart_0n,
n_0n[4],
w_0n[4],
nCv_0n[4],
c_0n[4],
nCv_0n[5],
c_0n[5],
addOut_0n[4]
);
balsa_fa I17 (
nStart_0n,
n_0n[5],
w_0n[5],
nCv_0n[5],
c_0n[5],
nCv_0n[6],
c_0n[6],
addOut_0n[5]
);
balsa_fa I18 (
nStart_0n,
n_0n[6],
w_0n[6],
nCv_0n[6],
c_0n[6],
nCv_0n[7],
c_0n[7],
addOut_0n[6]
);
balsa_fa I19 (
nStart_0n,
n_0n[7],
w_0n[7],
nCv_0n[7],
c_0n[7],
nCv_0n[8],
c_0n[8],
addOut_0n[7]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = gnd;
INV_A I22 (
nStart_0n,
start_0n
);
assign n_0n[1] = gnd;
assign n_0n[2] = gnd;
assign n_0n[3] = gnd;
assign n_0n[4] = gnd;
assign n_0n[5] = gnd;
assign n_0n[6] = gnd;
assign n_0n[7] = gnd;
assign n_0n[0] = vdd;
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign out_0a = done_0n;
assign start_0n = inpA_0a;
assign inpA_0r = out_0r;
endmodule
| 6.615161 |
module BrzBinaryFuncConstR_8_8_1_s8_Subtract_s5_f_m47m (
out_0r,
out_0a,
out_0d,
inpA_0r,
inpA_0a,
inpA_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_0n;
wire [8:0] c_0n;
wire [7:0] eq_0n;
wire [7:0] addOut_0n;
wire [7:0] w_0n;
wire [7:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
supply1 vdd;
NOR3_A I0 (
internal_0n[0],
nCv_0n[1],
nCv_0n[2],
nCv_0n[3]
);
NOR3_A I1 (
internal_0n[1],
nCv_0n[4],
nCv_0n[5],
nCv_0n[6]
);
NOR2_A I2 (
internal_0n[2],
nCv_0n[7],
nCv_0n[8]
);
AND3_A I3 (
done_0n,
internal_0n[0],
internal_0n[1],
internal_0n[2]
);
assign out_0d[0] = addOut_0n[0];
assign out_0d[1] = addOut_0n[1];
assign out_0d[2] = addOut_0n[2];
assign out_0d[3] = addOut_0n[3];
assign out_0d[4] = addOut_0n[4];
assign out_0d[5] = addOut_0n[5];
assign out_0d[6] = addOut_0n[6];
assign out_0d[7] = addOut_0n[7];
balsa_fa I12 (
nStart_0n,
n_0n[0],
w_0n[0],
nCv_0n[0],
c_0n[0],
nCv_0n[1],
c_0n[1],
addOut_0n[0]
);
balsa_fa I13 (
nStart_0n,
n_0n[1],
w_0n[1],
nCv_0n[1],
c_0n[1],
nCv_0n[2],
c_0n[2],
addOut_0n[1]
);
balsa_fa I14 (
nStart_0n,
n_0n[2],
w_0n[2],
nCv_0n[2],
c_0n[2],
nCv_0n[3],
c_0n[3],
addOut_0n[2]
);
balsa_fa I15 (
nStart_0n,
n_0n[3],
w_0n[3],
nCv_0n[3],
c_0n[3],
nCv_0n[4],
c_0n[4],
addOut_0n[3]
);
balsa_fa I16 (
nStart_0n,
n_0n[4],
w_0n[4],
nCv_0n[4],
c_0n[4],
nCv_0n[5],
c_0n[5],
addOut_0n[4]
);
balsa_fa I17 (
nStart_0n,
n_0n[5],
w_0n[5],
nCv_0n[5],
c_0n[5],
nCv_0n[6],
c_0n[6],
addOut_0n[5]
);
balsa_fa I18 (
nStart_0n,
n_0n[6],
w_0n[6],
nCv_0n[6],
c_0n[6],
nCv_0n[7],
c_0n[7],
addOut_0n[6]
);
balsa_fa I19 (
nStart_0n,
n_0n[7],
w_0n[7],
nCv_0n[7],
c_0n[7],
nCv_0n[8],
c_0n[8],
addOut_0n[7]
);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vdd;
INV_A I22 (
nStart_0n,
start_0n
);
assign n_0n[2] = n_0n[1];
assign n_0n[3] = n_0n[1];
assign n_0n[4] = n_0n[1];
assign n_0n[5] = n_0n[1];
assign n_0n[6] = n_0n[1];
assign n_0n[7] = n_0n[1];
assign n_0n[0] = gnd;
assign n_0n[1] = vdd;
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign out_0a = done_0n;
assign start_0n = inpA_0a;
assign inpA_0r = out_0r;
endmodule
| 6.615161 |
module BrzCallDemuxPush_1_2 (
inp_0r,
inp_0a,
inp_0d,
out_0r,
out_0a,
out_0d,
out_1r,
out_1a,
out_1d
);
input inp_0r;
output inp_0a;
input inp_0d;
output out_0r;
input out_0a;
output out_0d;
output out_1r;
input out_1a;
output out_1d;
OR2_A I0 (
inp_0a,
out_0a,
out_1a
);
assign out_0r = inp_0r;
assign out_1r = inp_0r;
assign out_0d = inp_0d;
assign out_1d = inp_0d;
endmodule
| 6.641334 |
module demux2 (
i,
o0,
o1,
s
);
input i;
output o0;
output o1;
input s;
wire ns_0n;
AND2_A I0 (
o1,
i,
s
);
AND2_A I1 (
o0,
i,
ns_0n
);
INV_A I2 (
ns_0n,
s
);
endmodule
| 6.863824 |
module BrzCombine_8_7_1 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [7:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [6:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input MSInp_0d;
c2 I0 (
out_0a,
LSInp_0a,
MSInp_0a
);
assign LSInp_0r = out_0r;
assign MSInp_0r = out_0r;
assign out_0d[0] = LSInp_0d[0];
assign out_0d[1] = LSInp_0d[1];
assign out_0d[2] = LSInp_0d[2];
assign out_0d[3] = LSInp_0d[3];
assign out_0d[4] = LSInp_0d[4];
assign out_0d[5] = LSInp_0d[5];
assign out_0d[6] = LSInp_0d[6];
assign out_0d[7] = MSInp_0d;
endmodule
| 6.832518 |
module BrzCombine_16_8_8 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [15:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [7:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [7:0] MSInp_0d;
c2 I0 (
out_0a,
LSInp_0a,
MSInp_0a
);
assign LSInp_0r = out_0r;
assign MSInp_0r = out_0r;
assign out_0d[0] = LSInp_0d[0];
assign out_0d[1] = LSInp_0d[1];
assign out_0d[2] = LSInp_0d[2];
assign out_0d[3] = LSInp_0d[3];
assign out_0d[4] = LSInp_0d[4];
assign out_0d[5] = LSInp_0d[5];
assign out_0d[6] = LSInp_0d[6];
assign out_0d[7] = LSInp_0d[7];
assign out_0d[8] = MSInp_0d[0];
assign out_0d[9] = MSInp_0d[1];
assign out_0d[10] = MSInp_0d[2];
assign out_0d[11] = MSInp_0d[3];
assign out_0d[12] = MSInp_0d[4];
assign out_0d[13] = MSInp_0d[5];
assign out_0d[14] = MSInp_0d[6];
assign out_0d[15] = MSInp_0d[7];
endmodule
| 6.935249 |
module BrzCombine_17_1_16 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [15:0] MSInp_0d;
c2 I0 (
out_0a,
LSInp_0a,
MSInp_0a
);
assign LSInp_0r = out_0r;
assign MSInp_0r = out_0r;
assign out_0d[0] = LSInp_0d;
assign out_0d[1] = MSInp_0d[0];
assign out_0d[2] = MSInp_0d[1];
assign out_0d[3] = MSInp_0d[2];
assign out_0d[4] = MSInp_0d[3];
assign out_0d[5] = MSInp_0d[4];
assign out_0d[6] = MSInp_0d[5];
assign out_0d[7] = MSInp_0d[6];
assign out_0d[8] = MSInp_0d[7];
assign out_0d[9] = MSInp_0d[8];
assign out_0d[10] = MSInp_0d[9];
assign out_0d[11] = MSInp_0d[10];
assign out_0d[12] = MSInp_0d[11];
assign out_0d[13] = MSInp_0d[12];
assign out_0d[14] = MSInp_0d[13];
assign out_0d[15] = MSInp_0d[14];
assign out_0d[16] = MSInp_0d[15];
endmodule
| 6.936519 |
module BrzCombine_17_8_9 (
out_0r,
out_0a,
out_0d,
LSInp_0r,
LSInp_0a,
LSInp_0d,
MSInp_0r,
MSInp_0a,
MSInp_0d
);
input out_0r;
output out_0a;
output [16:0] out_0d;
output LSInp_0r;
input LSInp_0a;
input [7:0] LSInp_0d;
output MSInp_0r;
input MSInp_0a;
input [8:0] MSInp_0d;
c2 I0 (
out_0a,
LSInp_0a,
MSInp_0a
);
assign LSInp_0r = out_0r;
assign MSInp_0r = out_0r;
assign out_0d[0] = LSInp_0d[0];
assign out_0d[1] = LSInp_0d[1];
assign out_0d[2] = LSInp_0d[2];
assign out_0d[3] = LSInp_0d[3];
assign out_0d[4] = LSInp_0d[4];
assign out_0d[5] = LSInp_0d[5];
assign out_0d[6] = LSInp_0d[6];
assign out_0d[7] = LSInp_0d[7];
assign out_0d[8] = MSInp_0d[0];
assign out_0d[9] = MSInp_0d[1];
assign out_0d[10] = MSInp_0d[2];
assign out_0d[11] = MSInp_0d[3];
assign out_0d[12] = MSInp_0d[4];
assign out_0d[13] = MSInp_0d[5];
assign out_0d[14] = MSInp_0d[6];
assign out_0d[15] = MSInp_0d[7];
assign out_0d[16] = MSInp_0d[8];
endmodule
| 6.936519 |
module c3 (
q,
i0,
i1,
i2
);
output q;
input i0;
input i1;
input i2;
wire qint_0n;
c2 I0 (
q,
i2,
qint_0n
);
c2 I1 (
qint_0n,
i0,
i1
);
endmodule
| 6.803047 |
module acu0d1 (
q,
i0,
i1
);
output q;
input i0;
input i1;
wire int_0n;
OR2_A I0 (
q,
i0,
int_0n
);
AND2_A I1 (
int_0n,
i1,
q
);
endmodule
| 6.712457 |
module BrzContinue (
inp_0r,
inp_0a
);
input inp_0r;
output inp_0a;
assign inp_0a = inp_0r;
endmodule
| 6.699402 |
module nc2p (
q,
i0,
i1
);
output q;
input i0;
input i1;
wire nq_0n;
AOI22_A I0 (
q,
i0,
i1,
i0,
nq_0n
);
INV_A I1 (
nq_0n,
q
);
endmodule
| 6.887623 |
module selem (
Ar,
Aa,
Br,
Ba
);
input Ar;
output Aa;
output Br;
input Ba;
wire s_0n;
nc2p I0 (
s_0n,
Ar,
Ba
);
NOR2_A I1 (
Aa,
Ba,
s_0n
);
AND2_A I2 (
Br,
Ar,
s_0n
);
endmodule
| 6.536596 |
module BrzWireFork_2 (
inp_0r,
inp_0a,
out_0r,
out_0a,
out_1r,
out_1a
);
input inp_0r;
output inp_0a;
output out_0r;
input out_0a;
output out_1r;
input out_1a;
supply0 gnd;
assign inp_0a = gnd;
assign out_0r = inp_0r;
assign out_1r = inp_0r;
endmodule
| 6.71441 |
module BAM (
i_clk,
i_arst,
i_on,
i_presc_mode,
i_duty_cycle,
o_bam_enable,
o_signal
);
input i_clk; // Input clock signal, 50MHz system clock on Altera DE2 FPGA board, for example
input i_arst; // Reset
input i_on; // CONFIG[0]
input [2:0] i_presc_mode; // CONFIG[3:1]
input [7:0] i_duty_cycle; // DCYCLE[7:0] - input value of duty cycle. DUTY CYCLE CAN BE 0%!
output o_bam_enable; // Signaling that the module is working - if CONFIG[0] == 1.
output o_signal; // Output binary angle modulated signal
wire clock_enable; // Output signal from clk_prescaler module, which will be used for clock gating
reg [7:0] counter; // Main counter
reg [2:0] current_bit; // Counter for moving through indexes of duty_cycle bits, from 0 to 7
assign o_bam_enable = i_on; // Will be used in GPIO to change output signal select
assign o_signal = ((i_duty_cycle[current_bit]) & i_on) ? 1'b1 : 1'b0;
/*
** Input clock prescale - i_presc_mode - select bits:
** 111 = 1:128 prescale
** 110 = 1:64 prescale
** 101 = 1:32 prescale
** 100 = 1:16 prescale
** 011 = 1:8 prescale
** 010 = 1:4 prescale
** 001 = 1:2 prescale
** 000 = 1:1 prescale
*/
wire [6:0] divide_by;
assign divide_by = 2 ** i_presc_mode - 1;
reg [6:0] divide_by_buff;
always @(posedge i_clk, posedge i_arst) begin
if (i_arst) begin
divide_by_buff <= {7{1'b0}}; // Default state after Reset signal, all bits equal to "0".
end else if (~i_on) begin
divide_by_buff <= {7{1'b0}};
end else begin
divide_by_buff <= divide_by; // Saved!
end
end
wire divide_by_state;
assign divide_by_state = (~(divide_by_buff == divide_by) & clock_enable); // Is current "divide by" value actual?
clk_prescaler prescaler_inst (
.i_clk(i_clk),
.i_arst(i_arst),
.i_on(i_on),
.i_divide_by(divide_by),
.o_clk_enable(clock_enable)
);
wire [7:0] max_cnt; // Max value for counting for current bit: 256, 128, 64, etc.
assign max_cnt = 2 ** current_bit - 1;
wire max_cnt_rst; // Signal to move to the next duty_cycle bit
assign max_cnt_rst = ((counter == max_cnt) & clock_enable); // Yeah, we can simplify it as "counter == (2**current_bit - 1)", but I want to have both this variables
reg [7:0] duty_cycle_buff; // Duty cycle buffer.
always @(posedge i_clk, posedge i_arst) begin
if (i_arst) begin
duty_cycle_buff <= {8{1'b0}}; // Default state after Reset signal, all bits equal to "0". DUTY CYCLE CAN BE 0%!
end else if (~i_on) begin
duty_cycle_buff <= {8{1'b0}};
end else begin
duty_cycle_buff <= i_duty_cycle; // Saved!
end
end
wire duty_cycle_state;
assign duty_cycle_state = (~(duty_cycle_buff == i_duty_cycle) & clock_enable); // Is current input value of duty cycle actual?
always @(posedge i_clk, posedge i_arst) begin
if (i_arst) begin
counter <= {8{1'b0}};
end else if ((~i_on) | max_cnt_rst | duty_cycle_state | divide_by_state) begin
counter <= {8{1'b0}};
end else begin
if (clock_enable) begin
counter <= counter + 1'b1;
end else begin
counter <= counter; // Just save the state
end
end
end
always @(posedge i_clk, posedge i_arst) begin
if (i_arst) begin
current_bit <= {3{1'b1}}; // 7 in decimal, 0b111 in binary
end else if ((~i_on) | duty_cycle_state | divide_by_state) begin
current_bit <= {3{1'b1}};
end else begin
if (max_cnt_rst) begin
current_bit <= current_bit - 1'b1; // Moving to the next digit (bit) after overflow
end else begin
current_bit <= current_bit; // Just save the state
end
end
end
endmodule
| 8.059804 |
module bambu_getchar (
input clock,
input reset,
input start_port,
output reg done_port,
output reg [7:0] return_port,
input [7:0] RX_DATA,
input RX_VALID
);
reg [7:0] data_reg;
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write;
wire fifo_full;
sync_fifo #(
.width(8)
) the_fifo (
.clk(clock),
.reset(reset),
.wr_enable(fifo_write),
.rd_enable(fifo_read),
.empty(fifo_empty),
.full(fifo_full),
.rd_data(fifo_out),
.wr_data(fifo_in),
.count()
);
reg [1:0] fifo_state;
reg [2:0] rx_state;
localparam FIFO_STATE_IDLE = 2'b01, FIFO_STATE_WRITE = 2'b10;
localparam RX_STATE_IDLE = 3'b01, RX_STATE_WAIT_DATA = 3'b10, RX_DONE = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset) begin
fifo_write <= 1'b0;
fifo_state <= FIFO_STATE_IDLE;
end else begin
fifo_write <= 1'b0;
if (fifo_state == FIFO_STATE_IDLE) begin
if (RX_VALID) begin
fifo_in <= RX_DATA;
fifo_state <= FIFO_STATE_WRITE;
end
end else begin
if (fifo_full == 1'b0) begin
fifo_write <= 1'b1;
fifo_state <= FIFO_STATE_IDLE;
end
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rx_state <= RX_STATE_IDLE;
fifo_read <= 1'b0;
done_port <= 1'b0;
return_port <= 8'b0;
end else begin
fifo_read <= 1'b0;
done_port <= 1'b0;
case (rx_state)
RX_STATE_IDLE: begin
if (start_port) begin
rx_state <= RX_STATE_WAIT_DATA;
end
end
RX_STATE_WAIT_DATA: begin
if (fifo_empty == 1'b0) begin
fifo_read <= 1'b1;
rx_state <= RX_DONE;
end
end
RX_DONE: begin
done_port <= 1'b1;
return_port <= fifo_out;
rx_state <= RX_STATE_IDLE;
end
endcase
end
end
endmodule
| 6.651577 |
module bambu_putchar (
input clock,
input reset,
input start_port,
output reg done_port,
input [7:0] c,
output reg [7:0] TX_DATA,
output reg TX_ENABLE,
input TX_READY
);
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write;
wire fifo_full;
sync_fifo #(
.width(8)
) the_fifo (
.clk(clock),
.reset(reset),
.wr_enable(fifo_write),
.rd_enable(fifo_read),
.empty(fifo_empty),
.full(fifo_full),
.rd_data(fifo_out),
.wr_data(fifo_in),
.count()
);
reg [1:0] fifo_state;
reg [2:0] tx_state;
reg TX_READY_reg;
wire TX_READY_posedge;
localparam FIFO_STATE_IDLE = 2'b01, FIFO_STATE_WRITE = 2'b10;
localparam TX_STATE_IDLE = 3'b001, TX_STATE_TX_BYTE = 3'b010, TX_STATE_WAIT_TX_READY = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset) begin
fifo_write <= 1'b0;
done_port <= 1'b0;
fifo_state <= FIFO_STATE_IDLE;
end else begin
done_port <= 1'b0;
fifo_write <= 1'b0;
if (fifo_state == FIFO_STATE_IDLE) begin
if (start_port) begin
fifo_in <= c;
fifo_state <= FIFO_STATE_WRITE;
end
end else begin
if (fifo_full == 1'b0) begin
fifo_write <= 1'b1;
fifo_state <= FIFO_STATE_IDLE;
done_port <= 1'b1;
end
end
end
end
assign TX_READY_posedge = TX_READY & ~TX_READY_reg;
always @(posedge clock or posedge reset) begin
if (reset) begin
tx_state <= TX_STATE_IDLE;
TX_DATA <= 8'b0;
TX_ENABLE <= 1'b0;
fifo_read <= 1'b0;
TX_READY_reg <= 1'b0;
end else begin
fifo_read <= 1'b0;
TX_ENABLE <= 1'b0;
TX_READY_reg <= TX_READY;
case (tx_state)
TX_STATE_IDLE: begin
if (fifo_empty == 1'b0 && TX_READY == 1'b1) begin
fifo_read <= 1'b1;
tx_state <= TX_STATE_TX_BYTE;
end
end
TX_STATE_TX_BYTE: begin
TX_DATA <= fifo_out;
TX_ENABLE <= 1'b1;
tx_state <= TX_STATE_WAIT_TX_READY;
end
TX_STATE_WAIT_TX_READY: begin
if (TX_READY_posedge == 1'b1) tx_state <= TX_STATE_IDLE;
end
endcase
end
end
endmodule
| 6.832514 |
module bambu_single_ram_axi_wrapper (
clock,
reset,
master_tdata,
master_tvalid,
slave_tready,
slave_tdata,
slave_tvalid,
master_tready
);
input wire clock;
input wire reset;
input wire [95:0] master_tdata;
input wire master_tvalid;
input wire master_tready;
output reg [71:0] slave_tdata;
output reg slave_tvalid;
output wire slave_tready;
reg [15:0] internal_matrix[0:63];
reg [8:0] output_matrix[0:63];
reg [3:0] input_row_count;
reg [3:0] output_row_count;
reg busy;
wire dev_out_write, dev_out_read, out_done, full, finished;
wire [31:0] dev_out_addr;
wire [15:0] dev_out_data;
wire [ 4:0] out_data_size;
wire [15:0] mask;
assign mask = (1 << out_data_size) - 1;
assign slave_tready = ~busy;
assign full = input_row_count > 4'd7;
assign finished = output_row_count > 4'd7;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
always @(posedge clock) if (out_done) output_matrix[i] = internal_matrix[i][8:0];
end
endgenerate
always @(posedge clock) begin
if (reset) slave_tvalid <= 1'b0;
else begin
if (out_done) slave_tvalid <= 1'b1;
if (finished) slave_tvalid <= 1'b0;
end
end
always @(posedge clock) begin
if (reset) begin
output_row_count <= 4'b0;
slave_tdata <= 72'b0;
end else begin
if ((out_done | slave_tvalid) & master_tready & !full) begin
slave_tdata <= {
output_matrix[output_row_count*8+7],
output_matrix[output_row_count*8+6],
output_matrix[output_row_count*8+5],
output_matrix[output_row_count*8+4],
output_matrix[output_row_count*8+3],
output_matrix[output_row_count*8+2],
output_matrix[output_row_count*8+1],
output_matrix[output_row_count*8+0]
};
output_row_count <= output_row_count + 4'b1;
end else if (finished) output_row_count <= 4'b0;
end
end
always @(posedge clock) begin
if (reset) begin
input_row_count <= 4'b0;
busy <= 1'b0;
end else begin
if (master_tvalid & slave_tready) begin
internal_matrix[input_row_count*8+0] <= {{4{master_tdata[11]}}, master_tdata[11:0]};
internal_matrix[input_row_count*8+1] <= {{4{master_tdata[23]}}, master_tdata[23:12]};
internal_matrix[input_row_count*8+2] <= {{4{master_tdata[35]}}, master_tdata[35:24]};
internal_matrix[input_row_count*8+3] <= {{4{master_tdata[47]}}, master_tdata[47:36]};
internal_matrix[input_row_count*8+4] <= {{4{master_tdata[59]}}, master_tdata[59:48]};
internal_matrix[input_row_count*8+5] <= {{4{master_tdata[71]}}, master_tdata[71:60]};
internal_matrix[input_row_count*8+6] <= {{4{master_tdata[83]}}, master_tdata[83:72]};
internal_matrix[input_row_count*8+7] <= {{4{master_tdata[95]}}, master_tdata[95:84]};
input_row_count <= input_row_count + 4'b1;
end else if (busy & !dev_out_read & dev_out_write)
internal_matrix[dev_out_addr>>1] <= dev_out_data & mask;
if (full) begin
input_row_count <= 4'b0;
busy <= 1'b1;
end
end
end
Fast_IDCT idct (
.clock(clock),
.reset(~reset),
.start_port(full),
.block(32'b0),
.M_Rdata_ram((dev_out_read & !dev_out_write) ? internal_matrix[dev_out_addr >> 1] & mask : 16'b0),
.M_DataRdy((dev_out_read | dev_out_write) ? 1'b1 : 1'b0),
.done_port(out_done),
.Mout_oe_ram(dev_out_read),
.Mout_we_ram(dev_out_write),
.Mout_addr_ram(dev_out_addr),
.Mout_Wdata_ram(dev_out_data),
.Mout_data_ram_size(out_data_size)
);
endmodule
| 7.330918 |
module AND2_44 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.915464 |
module FA_44 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire A;
assign S = A;
endmodule
| 6.871119 |
module CSA_Cell_44 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_44 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_44 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 7.019059 |
module AND2_38 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.695829 |
module AND2_30 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.021831 |
module AND2_1 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.595903 |
module CSA_Cell_1 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_1 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_1 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
.S(S_out),
.CO_BAR(C_out)
);
endmodule
| 6.708587 |
module AND2_2 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.948015 |
module CSA_Cell_2 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_2 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_2 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 7.535071 |
module AND2_3 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.570512 |
module CSA_Cell_3 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_3 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_3 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
.S(S_out),
.CO_BAR(C_out)
);
endmodule
| 6.97547 |
module FA_4 (
A,
B,
CI,
S,
CO_BAR
);
input A, B, CI;
output S, CO_BAR;
wire n1;
XOR2_X1 U1 (
.A1(A),
.A2(B),
.Z (n1)
);
AOI22_X1 U2 (
.A1(A),
.A2(B),
.B1(n1),
.B2(CI),
.ZN(CO_BAR)
);
XOR2_X1 U3 (
.A1(n1),
.A2(CI),
.Z (S)
);
endmodule
| 6.626139 |
module AND2_4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.779641 |
module CSA_Cell_4 (
X,
Y,
S_in,
C_in,
S_out,
C_out_BAR
);
input X, Y, S_in, C_in;
output S_out, C_out_BAR;
wire C_out, And_XY;
assign C_out_BAR = C_out;
AND2_4 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_4 U1 (
.A(And_XY),
.B(S_in),
.CI(C_in),
.S(S_out),
.CO_BAR(C_out)
);
endmodule
| 7.227021 |
module AND2_5 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.939218 |
module CSA_Cell_5 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_5 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_5 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 7.49635 |
module AND2_6 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.701088 |
module CSA_Cell_6 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_6 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_6 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.809643 |
module FA_7 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire n1, n2;
XOR2_X1 U1 (
.A1(A),
.A2(B),
.Z (n2)
);
AOI22_X1 U2 (
.A1(A),
.A2(B),
.B1(n2),
.B2(CI),
.ZN(n1)
);
INV_X1 U3 (
.I (n1),
.ZN(CO)
);
XOR2_X1 U4 (
.A1(n2),
.A2(CI),
.Z (S)
);
endmodule
| 6.624434 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module CSA_Cell_7 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_7 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_7 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.646269 |
module AND2_9 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.884729 |
module CSA_Cell_9 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_9 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_9 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.633226 |
module AND2_10 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.486296 |
module AND2_11 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.443228 |
module AND2_12 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.990184 |
module CSA_Cell_12 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_12 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_12 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 7.063742 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_14 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.558896 |
module CSA_Cell_14 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_14 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_14 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.954598 |
module AND2_15 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.821494 |
module CSA_Cell_15 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_15 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_15 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.642819 |
module AND2_17 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.742214 |
module CSA_Cell_17 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_17 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_17 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.861753 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module CSA_Cell_19 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_19 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_19 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.517123 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module CSA_Cell_20 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_20 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_20 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.543769 |
module AND2_21 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.110455 |
module CSA_Cell_21 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_21 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_21 U1 (
.A (And_XY),
.B (S_in),
.CI(C_in),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.682578 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.