signature
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3.44k
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1.41M
| docstring
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@property<EOL><INDENT>def operation(self):<DEDENT>
|
return self._operation<EOL>
|
Get gadgets operation.
|
f3294:c1:m12
|
@operation.setter<EOL><INDENT>def operation(self, value):<DEDENT>
|
self._operation = value<EOL>
|
Set gadgets operation.
|
f3294:c1:m13
|
def __eq__(self, other):
|
if type(other) is type(self):<EOL><INDENT>same_sources = self._sources == other._sources<EOL>same_destination = self._destination == other._destination<EOL>same_modified = self._modified_regs == other._modified_regs<EOL>same_operation = self._operation == other._operation<EOL>return same_sources and same_destination and same_modified andsame_operation<EOL><DEDENT>else:<EOL><INDENT>return False<EOL><DEDENT>
|
Return self == other.
|
f3294:c1:m16
|
def __ne__(self, other):
|
return not self.__eq__(other)<EOL>
|
Return self != other.
|
f3294:c1:m17
|
def find(self, start_address, end_address, byte_depth=<NUM_LIT:20>, instrs_depth=<NUM_LIT:2>):
|
self._max_bytes = byte_depth<EOL>self._instrs_depth = instrs_depth<EOL>if self._architecture == ARCH_X86:<EOL><INDENT>candidates = self._find_x86_candidates(start_address, end_address)<EOL><DEDENT>elif self._architecture == ARCH_ARM:<EOL><INDENT>candidates = self._find_arm_candidates(start_address, end_address)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return sorted(candidates, key=lambda g: g.address)<EOL>
|
Find gadgets.
|
f3295:c0:m1
|
def _find_x86_candidates(self, start_address, end_address):
|
roots = []<EOL>for addr in xrange(start_address, end_address + <NUM_LIT:1>):<EOL><INDENT>op_codes = [<EOL><NUM_LIT>, <EOL><NUM_LIT>, <EOL><NUM_LIT>, <EOL><NUM_LIT>, <EOL><NUM_LIT>, <EOL><NUM_LIT>, <EOL>]<EOL>if self._mem[addr] not in op_codes:<EOL><INDENT>continue<EOL><DEDENT>try:<EOL><INDENT>asm_instr = self._disasm.disassemble(<EOL>self._mem[addr:min(addr+<NUM_LIT:16>, end_address + <NUM_LIT:1>)],<EOL>addr<EOL>)<EOL><DEDENT>except:<EOL><INDENT>asm_instr = None<EOL><DEDENT>if not asm_instr:<EOL><INDENT>continue<EOL><DEDENT>self._ir_trans.reset()<EOL>try:<EOL><INDENT>ins_ir = self._ir_trans.translate(asm_instr)<EOL><DEDENT>except:<EOL><INDENT>continue<EOL><DEDENT>if ins_ir[-<NUM_LIT:1>] and (ins_ir[-<NUM_LIT:1>].mnemonic == ReilMnemonic.JCC and isinstance(ins_ir[-<NUM_LIT:1>].operands[<NUM_LIT:2>], ReilRegisterOperand)):<EOL><INDENT>if ins_ir[-<NUM_LIT:1>].mnemonic == ReilMnemonic.JCC:<EOL><INDENT>try:<EOL><INDENT>asm_instr_1 = self._disasm.disassemble(<EOL>self._mem[addr-<NUM_LIT:1>:min(addr+<NUM_LIT:15>, end_address + <NUM_LIT:1>)],<EOL>addr<EOL>)<EOL>self._ir_trans.reset()<EOL>ins_ir_1 = self._ir_trans.translate(asm_instr_1)<EOL>if ins_ir_1[-<NUM_LIT:1>].mnemonic == ReilMnemonic.JCC:<EOL><INDENT>addr = addr - <NUM_LIT:1><EOL>asm_instr = asm_instr_1<EOL>ins_ir = ins_ir_1<EOL><DEDENT><DEDENT>except:<EOL><INDENT>pass<EOL><DEDENT><DEDENT>asm_instr.ir_instrs = ins_ir<EOL>root = GadgetTreeNode(asm_instr)<EOL>roots.append(root)<EOL>self._build_from(addr, root, start_address, self._instrs_depth)<EOL><DEDENT><DEDENT>roots = [r for r in roots if len(r.get_children()) > <NUM_LIT:0>]<EOL>root_gadgets = [self._build_gadgets(r) for r in roots]<EOL>candidates = [item for l in root_gadgets for item in l]<EOL>return candidates<EOL>
|
Finds possible 'RET-ended' gadgets.
|
f3295:c0:m2
|
def _find_arm_candidates(self, start_address, end_address):
|
roots = []<EOL>gadget_tail_addr = []<EOL>free_jump_gadgets = [<EOL>b"<STR_LIT>", <EOL>b"<STR_LIT>", <EOL>b"<STR_LIT>", <EOL>]<EOL>for addr in xrange(start_address, end_address + <NUM_LIT:1>):<EOL><INDENT>gad_found = False<EOL>for gad in free_jump_gadgets:<EOL><INDENT>if len(re.findall(gad, self._mem[addr:min(addr+<NUM_LIT:4>, end_address + <NUM_LIT:1>)])) > <NUM_LIT:0>: <EOL><INDENT>gad_found = True<EOL>break<EOL><DEDENT><DEDENT>if not gad_found:<EOL><INDENT>continue<EOL><DEDENT>gadget_tail_addr.append(addr)<EOL><DEDENT>for addr in gadget_tail_addr:<EOL><INDENT>try:<EOL><INDENT>asm_instr = self._disasm.disassemble(<EOL>self._mem[addr:min(addr+<NUM_LIT:4>, end_address + <NUM_LIT:1>)], <EOL>addr,<EOL>architecture_mode=self._architecture_mode<EOL>)<EOL><DEDENT>except:<EOL><INDENT>asm_instr = None<EOL><DEDENT>if not asm_instr:<EOL><INDENT>continue<EOL><DEDENT>self._ir_trans.reset()<EOL>try:<EOL><INDENT>ins_ir = self._ir_trans.translate(asm_instr)<EOL><DEDENT>except:<EOL><INDENT>continue<EOL><DEDENT>asm_instr.ir_instrs = ins_ir<EOL>root = GadgetTreeNode(asm_instr)<EOL>roots.append(root)<EOL>self._build_from(addr, root, start_address, self._instrs_depth)<EOL><DEDENT>roots = [r for r in roots if len(r.get_children()) > <NUM_LIT:0>]<EOL>root_gadgets = [self._build_gadgets(r) for r in roots]<EOL>candidates = [item for l in root_gadgets for item in l]<EOL>return candidates<EOL>
|
Finds possible 'RET-ended' gadgets.
|
f3295:c0:m3
|
def _build_from(self, address, root, base_address, depth=<NUM_LIT:2>):
|
if depth == <NUM_LIT:0>:<EOL><INDENT>return<EOL><DEDENT>end_addr = address<EOL>for step in range(<NUM_LIT:1>, self._max_bytes + <NUM_LIT:1>):<EOL><INDENT>start_addr = address - step<EOL>if start_addr < <NUM_LIT:0> or start_addr < base_address:<EOL><INDENT>break<EOL><DEDENT>raw_bytes = self._mem[start_addr:end_addr]<EOL>if self._architecture == ARCH_ARM:<EOL><INDENT>try:<EOL><INDENT>asm_instr = self._disasm.disassemble(raw_bytes, start_addr, architecture_mode=self._architecture_mode)<EOL><DEDENT>except InvalidDisassemblerData:<EOL><INDENT>continue<EOL><DEDENT><DEDENT>else:<EOL><INDENT>try:<EOL><INDENT>asm_instr = self._disasm.disassemble(raw_bytes, start_addr)<EOL><DEDENT>except:<EOL><INDENT>asm_instr = None<EOL><DEDENT><DEDENT>if not asm_instr or asm_instr.size != step:<EOL><INDENT>continue<EOL><DEDENT>try:<EOL><INDENT>ir_instrs = self._ir_trans.translate(asm_instr)<EOL><DEDENT>except:<EOL><INDENT>continue<EOL><DEDENT>if self._is_valid_ins(ir_instrs):<EOL><INDENT>asm_instr.ir_instrs = ir_instrs<EOL>child = GadgetTreeNode(asm_instr)<EOL>root.add_child(child)<EOL>self._build_from(address - step, child, base_address, depth - <NUM_LIT:1>)<EOL><DEDENT><DEDENT>
|
Build gadgets recursively.
|
f3295:c0:m4
|
def _build_gadgets(self, gadget_tree_root):
|
node_list = self._build_gadgets_rec(gadget_tree_root)<EOL>return [RawGadget(n) for n in node_list]<EOL>
|
Return a gadgets list.
|
f3295:c0:m5
|
def _build_gadgets_rec(self, gadget_tree_root):
|
root = gadget_tree_root.get_root()<EOL>children = gadget_tree_root.get_children()<EOL>node_list = []<EOL>root_gadget_ins = root<EOL>if not children:<EOL><INDENT>node_list += [[root_gadget_ins]]<EOL><DEDENT>else:<EOL><INDENT>for child in children:<EOL><INDENT>node_list_rec = self._build_gadgets_rec(child)<EOL>node_list += [n + [root_gadget_ins] for n in node_list_rec]<EOL><DEDENT><DEDENT>return node_list<EOL>
|
Build a gadgets from a gadgets tree.
|
f3295:c0:m6
|
def _is_valid_ins(self, ins_ir):
|
invalid_instrs = [<EOL>ReilMnemonic.JCC,<EOL>ReilMnemonic.UNDEF,<EOL>ReilMnemonic.UNKN,<EOL>]<EOL>return not any([i.mnemonic in invalid_instrs for i in ins_ir])<EOL>
|
Check for instruction validity as a gadgets.
|
f3295:c0:m7
|
def get_root(self):
|
return self._root<EOL>
|
Get node root.
|
f3295:c1:m1
|
def add_child(self, child):
|
self._children.append(child)<EOL>
|
Add a child to the node.
|
f3295:c1:m2
|
def get_children(self):
|
return self._children<EOL>
|
Get node's children.
|
f3295:c1:m3
|
def reset(self):
|
self._translator.reset()<EOL>
|
Reset current state of the analyzer.
|
f3297:c0:m1
|
def get_operand_expr(self, operand, mode="<STR_LIT>"):
|
if isinstance(operand, ReilRegisterOperand):<EOL><INDENT>if operand.name in self._arch_info.registers_all:<EOL><INDENT>expr = self.get_register_expr(operand.name, mode=mode)<EOL><DEDENT>else:<EOL><INDENT>var_name = self._get_var_name(operand.name, mode)<EOL>expr = self._translator.make_bitvec(operand.size, var_name)<EOL><DEDENT><DEDENT>elif isinstance(operand, ReilImmediateOperand):<EOL><INDENT>expr = smtsymbol.Constant(operand.size, operand.immediate)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>" % str(operand))<EOL><DEDENT>return expr<EOL>
|
Return a smt bit vector that represents a register (architectural or
temporal).
|
f3297:c0:m2
|
def get_register_expr(self, register_name, mode="<STR_LIT>"):
|
reg_info = self._arch_info.alias_mapper.get(register_name, None)<EOL>if reg_info:<EOL><INDENT>var_base_name, offset = reg_info<EOL><DEDENT>else:<EOL><INDENT>var_base_name = register_name<EOL><DEDENT>var_name = self._get_var_name(var_base_name, mode)<EOL>var_size = self._arch_info.registers_size[var_base_name]<EOL>ret_val = self._translator.make_bitvec(var_size, var_name)<EOL>if reg_info:<EOL><INDENT>ret_val = smtfunction.extract(ret_val, offset, self._arch_info.registers_size[register_name])<EOL><DEDENT>return ret_val<EOL>
|
Return a smt bit vector that represents an architectural (native)
register.
|
f3297:c0:m3
|
def get_memory_expr(self, address, size, mode="<STR_LIT>"):
|
mem = self.get_memory(mode)<EOL>return smtfunction.concat(<NUM_LIT:8>, *reversed([mem[address + i] for i in range(size)]))<EOL>
|
Return a smt bit vector that represents a memory location.
|
f3297:c0:m4
|
def get_memory(self, mode):
|
mem = {<EOL>"<STR_LIT>": self._translator.get_memory_init(),<EOL>"<STR_LIT>": self._translator.get_memory_curr(),<EOL>}<EOL>return mem[mode]<EOL>
|
Return a smt bit vector that represents a memory location.
|
f3297:c0:m5
|
def add_instruction(self, reil_instruction):
|
for expr in self._translator.translate(reil_instruction):<EOL><INDENT>self._solver.add(expr)<EOL><DEDENT>
|
Add an instruction for analysis.
|
f3297:c0:m6
|
def add_constraint(self, constraint):
|
self._solver.add(constraint)<EOL>
|
Add constraint to the current set of formulas.
|
f3297:c0:m7
|
def check(self):
|
return self._solver.check()<EOL>
|
Check if the instructions and restrictions added so far are
satisfiable.
|
f3297:c0:m8
|
def get_expr_value(self, expr):
|
return self._solver.get_value(expr)<EOL>
|
Get a value for an expression.
|
f3297:c0:m9
|
def _get_var_name(self, register_name, mode):
|
var_name = {<EOL>"<STR_LIT>": self._translator.get_name_init(register_name),<EOL>"<STR_LIT>": self._translator.get_name_curr(register_name),<EOL>}<EOL>return var_name[mode]<EOL>
|
Get variable name for a register considering pre and post mode.
|
f3297:c0:m10
|
def bb_get_instr_max_width(basic_block):
|
asm_mnemonic_max_width = <NUM_LIT:0><EOL>for instr in basic_block:<EOL><INDENT>if len(instr.mnemonic) > asm_mnemonic_max_width:<EOL><INDENT>asm_mnemonic_max_width = len(instr.mnemonic)<EOL><DEDENT><DEDENT>return asm_mnemonic_max_width<EOL>
|
Get maximum instruction mnemonic width
|
f3298:m1
|
@property<EOL><INDENT>def label(self):<DEDENT>
|
return self._label<EOL>
|
Get basic block label.
|
f3298:c0:m1
|
@label.setter<EOL><INDENT>def label(self, value):<DEDENT>
|
self._label = value<EOL>
|
Set basic block label.
|
f3298:c0:m2
|
@property<EOL><INDENT>def is_entry(self):<DEDENT>
|
return self._is_entry<EOL>
|
Get basic block is_entry.
|
f3298:c0:m3
|
@is_entry.setter<EOL><INDENT>def is_entry(self, value):<DEDENT>
|
self._is_entry = value<EOL>
|
Set basic block is_entry.
|
f3298:c0:m4
|
@property<EOL><INDENT>def is_exit(self):<DEDENT>
|
return self._is_exit<EOL>
|
Get basic block is_exit.
|
f3298:c0:m5
|
@is_exit.setter<EOL><INDENT>def is_exit(self, value):<DEDENT>
|
self._is_exit = value<EOL>
|
Set basic block is_exit.
|
f3298:c0:m6
|
@property<EOL><INDENT>def instrs(self):<DEDENT>
|
return self._instrs<EOL>
|
Get basic block instructions.
|
f3298:c0:m7
|
@property<EOL><INDENT>def address(self):<DEDENT>
|
if len(self._instrs) == <NUM_LIT:0>:<EOL><INDENT>return None<EOL><DEDENT>return self._instrs[<NUM_LIT:0>].address<EOL>
|
Get basic block start address.
|
f3298:c0:m8
|
@property<EOL><INDENT>def start_address(self):<DEDENT>
|
if self._instrs is []:<EOL><INDENT>return None<EOL><DEDENT>return self._instrs[<NUM_LIT:0>].address<EOL>
|
Get basic block start address.
|
f3298:c0:m9
|
@property<EOL><INDENT>def end_address(self):<DEDENT>
|
if self._instrs is []:<EOL><INDENT>return None<EOL><DEDENT>return self._instrs[-<NUM_LIT:1>].address + self._instrs[-<NUM_LIT:1>].size - <NUM_LIT:1><EOL>
|
Get basic block end address.
|
f3298:c0:m10
|
@property<EOL><INDENT>def size(self):<DEDENT>
|
if self._instrs is []:<EOL><INDENT>return None<EOL><DEDENT>return sum([instr.size for instr in self._instrs])<EOL>
|
Get basic block size.
|
f3298:c0:m11
|
@property<EOL><INDENT>def taken_branch(self):<DEDENT>
|
return self._taken_branch<EOL>
|
Get basic block taken branch.
|
f3298:c0:m12
|
@taken_branch.setter<EOL><INDENT>def taken_branch(self, value):<DEDENT>
|
self._taken_branch = value<EOL>
|
Set basic block taken branch.
|
f3298:c0:m13
|
@property<EOL><INDENT>def not_taken_branch(self):<DEDENT>
|
return self._not_taken_branch<EOL>
|
Get basic block not taken branch.
|
f3298:c0:m14
|
@not_taken_branch.setter<EOL><INDENT>def not_taken_branch(self, value):<DEDENT>
|
self._not_taken_branch = value<EOL>
|
Set basic block not taken branch.
|
f3298:c0:m15
|
@property<EOL><INDENT>def direct_branch(self):<DEDENT>
|
return self._direct_branch<EOL>
|
Get basic block direct branch.
|
f3298:c0:m16
|
@direct_branch.setter<EOL><INDENT>def direct_branch(self, value):<DEDENT>
|
self._direct_branch = value<EOL>
|
Set basic block direct branch.
|
f3298:c0:m17
|
@property<EOL><INDENT>def branches(self):<DEDENT>
|
branches = []<EOL>if self._taken_branch:<EOL><INDENT>branches += [(self._taken_branch, '<STR_LIT>')]<EOL><DEDENT>if self._not_taken_branch:<EOL><INDENT>branches += [(self._not_taken_branch, '<STR_LIT>')]<EOL><DEDENT>if self._direct_branch:<EOL><INDENT>branches += [(self._direct_branch, '<STR_LIT>')]<EOL><DEDENT>return branches<EOL>
|
Get basic block branches.
|
f3298:c0:m18
|
def contains(self, address):
|
return self.address <= address <= self.end_address<EOL>
|
Check if an address is within the range of a basic block.
|
f3298:c0:m19
|
def empty(self):
|
return len(self._instrs) == <NUM_LIT:0><EOL>
|
Check if a basic block is empty.
|
f3298:c0:m20
|
def all_simple_bb_paths(self, start_address, end_address):
|
bb_start = self._find_basic_block(start_address)<EOL>bb_end = self._find_basic_block(end_address)<EOL>paths = networkx.all_simple_paths(self._graph, source=bb_start.address, target=bb_end.address)<EOL>return ([self._bb_by_addr[addr] for addr in path] for path in paths)<EOL>
|
Return a list of path between start and end address.
|
f3299:c0:m9
|
def build(self, start, end, symbols=None):
|
symbols = {} if not symbols else symbols<EOL>bbs = self._recover_bbs(start, end, symbols)<EOL>bbs = self._split_bbs(bbs, symbols)<EOL>call_targets = self._extract_call_targets(bbs)<EOL>return bbs, call_targets<EOL>
|
Return the list of basic blocks.
:int start: Start address of the disassembling process.
:int end: End address of the disassembling process.
|
f3299:c1:m1
|
def save(self, cfg, filename, print_ir=False, format='<STR_LIT>', options=None):
|
if options is None:<EOL><INDENT>options = {}<EOL><DEDENT>try:<EOL><INDENT>dot_graph = Dot(**self.graph_format)<EOL>nodes = {}<EOL>for bb in cfg.basic_blocks:<EOL><INDENT>nodes[bb.address] = self._create_node(bb, cfg.name, print_ir, options)<EOL>dot_graph.add_node(nodes[bb.address])<EOL><DEDENT>for bb_src in cfg.basic_blocks:<EOL><INDENT>for bb_dst_addr, branch_type in bb_src.branches:<EOL><INDENT>if bb_dst_addr in nodes:<EOL><INDENT>edge = self._create_edge(nodes[bb_src.address], nodes[bb_dst_addr], branch_type)<EOL>dot_graph.add_edge(edge)<EOL><DEDENT>else:<EOL><INDENT>logger.warning("<STR_LIT>", bb_dst_addr)<EOL><DEDENT><DEDENT><DEDENT>dot_graph.write("<STR_LIT>".format(filename, format), format=format)<EOL><DEDENT>except Exception:<EOL><INDENT>logger.error("<STR_LIT>", filename, format, exc_info=True)<EOL><DEDENT>
|
Save basic block graph into a file.
|
f3299:c6:m0
|
def save(self, cfg, filename, print_ir=False, format='<STR_LIT>', options=None):
|
if options is None:<EOL><INDENT>options = {}<EOL><DEDENT>try:<EOL><INDENT>dot_graph = Dot(**self.graph_format)<EOL>nodes = {}<EOL>for bb in cfg.basic_blocks:<EOL><INDENT>nodes[bb.address] = self._create_node(bb, cfg.name, print_ir, options)<EOL>dot_graph.add_node(nodes[bb.address])<EOL><DEDENT>for bb_src in cfg.basic_blocks:<EOL><INDENT>for bb_dst_addr, branch_type in bb_src.branches:<EOL><INDENT>if bb_dst_addr in nodes:<EOL><INDENT>edge = self._create_edge(nodes[bb_src.address], nodes[bb_dst_addr], branch_type)<EOL>dot_graph.add_edge(edge)<EOL><DEDENT>else:<EOL><INDENT>logger.warning("<STR_LIT>", bb_dst_addr)<EOL><DEDENT><DEDENT><DEDENT>dot_graph.write("<STR_LIT>".format(filename, format), format=format)<EOL><DEDENT>except Exception:<EOL><INDENT>logger.error("<STR_LIT>", filename, format, exc_info=True)<EOL><DEDENT>
|
Save basic block graph into a file.
|
f3299:c7:m0
|
def simple_paths_by_name(self, start_name, end_name):
|
cfg_start = self.find_function_by_name(start_name)<EOL>cfg_end = self.find_function_by_name(end_name)<EOL>if not cfg_start or not cfg_end:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>start_address = cfg_start.start_address<EOL>end_address = cfg_end.start_address<EOL>paths = networkx.all_simple_paths(self._graph, source=start_address, target=end_address)<EOL>return ([self._cfg_by_addr[addr] for addr in path] for path in paths)<EOL>
|
Return a list of paths between start and end functions.
|
f3300:c0:m3
|
def simple_paths_by_address(self, start_address, end_address):
|
cfg_start = self.find_function_by_address(start_address)<EOL>cfg_end = self.find_function_by_address(end_address)<EOL>if not cfg_start or not cfg_end:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>start_address = cfg_start.start_address<EOL>end_address = cfg_end.start_address<EOL>paths = networkx.all_simple_paths(self._graph, source=start_address, target=end_address)<EOL>return ([self._cfg_by_addr[addr] for addr in path] for path in paths)<EOL>
|
Return a list of paths between start and end functions.
|
f3300:c0:m4
|
def find_function_by_name(self, name):
|
cfg_rv = None<EOL>for cfg in self._cfgs:<EOL><INDENT>if cfg.name == name:<EOL><INDENT>cfg_rv = cfg<EOL>break<EOL><DEDENT><DEDENT>return cfg_rv<EOL>
|
Return the cfg of the requested function by name.
|
f3300:c0:m5
|
def find_function_by_address(self, address):
|
cfg_rv = None<EOL>for cfg in self._cfgs:<EOL><INDENT>if cfg.start_address == address:<EOL><INDENT>cfg_rv = cfg<EOL>break<EOL><DEDENT><DEDENT>return cfg_rv<EOL>
|
Return the cfg of the requested function by address.
|
f3300:c0:m6
|
def save(self, cf, filename, format='<STR_LIT>'):
|
try:<EOL><INDENT>dot_graph = Dot(**self.graph_format)<EOL>nodes = {}<EOL>for cfg_addr in cf._graph.node.keys():<EOL><INDENT>nodes[cfg_addr] = self._create_node(cfg_addr, cf)<EOL>dot_graph.add_node(nodes[cfg_addr])<EOL><DEDENT>for cfg_src_addr in cf._graph.node.keys():<EOL><INDENT>for cfg_dst_addr in cf._edges.get(cfg_src_addr, []):<EOL><INDENT>edge = self._create_edge(nodes, cfg_src_addr, cfg_dst_addr)<EOL>dot_graph.add_edge(edge)<EOL><DEDENT><DEDENT>dot_graph.write("<STR_LIT>".format(filename, format), format=format)<EOL><DEDENT>except Exception:<EOL><INDENT>logger.error("<STR_LIT>", filename, format, exc_info=True)<EOL><DEDENT>
|
Save basic block graph into a file.
|
f3300:c2:m0
|
def find_address(self, container, start=None, end=None, find=None, avoid=None, initial_state=None):
|
<EOL>self.__set_cpu_state(initial_state)<EOL>start = to_reil_address(start) if start else None<EOL>end = to_reil_address(end) if end else None<EOL>find = to_reil_address(find) if find else None<EOL>avoid = [to_reil_address(addr) for addr in avoid] if avoid else []<EOL>ip = start if start else container[<NUM_LIT:0>].address<EOL>execution_state = Queue()<EOL>trace_current = []<EOL>trace_final = []<EOL>self.__fa_process_container(container, find, ip, end, avoid, initial_state, execution_state, trace_current,<EOL>trace_final)<EOL>assert execution_state.empty()<EOL>return trace_final<EOL>
|
Execute instructions.
|
f3302:c2:m1
|
def find_state(self, container, start=None, end=None, avoid=None, initial_state=None, final_state=None):
|
self.__set_cpu_state(initial_state)<EOL>start = to_reil_address(start) if start else None<EOL>end = to_reil_address(end) if end else None<EOL>avoid = [to_reil_address(addr) for addr in avoid] if avoid else []<EOL>ip = start if start else container[<NUM_LIT:0>].address<EOL>execution_state = Queue()<EOL>trace_current = []<EOL>trace_final = []<EOL>self.__fs_process_container(container, final_state, ip, end, avoid, initial_state, execution_state,<EOL>trace_current, trace_final)<EOL>assert execution_state.empty()<EOL>return trace_final<EOL>
|
Execute instructions.
|
f3302:c2:m2
|
def __process_instr(self, instr, avoid, next_addr, initial_state, execution_state, trace_current):
|
<EOL>if instr.mnemonic == ReilMnemonic.JCC:<EOL><INDENT>not_taken_addr = next_addr<EOL>address, index = split_address(instr.address)<EOL>logger.debug("<STR_LIT>".format(address, index, instr))<EOL>if isinstance(instr.operands[<NUM_LIT:0>], ReilRegisterOperand):<EOL><INDENT>next_ip = self.__process_branch_cond(instr, avoid, initial_state, execution_state, trace_current, not_taken_addr)<EOL><DEDENT>else:<EOL><INDENT>next_ip = self.__process_branch_uncond(instr, trace_current, not_taken_addr)<EOL><DEDENT><DEDENT>else:<EOL><INDENT>trace_current += [(instr, None)]<EOL>self.__cpu.execute(instr)<EOL>next_ip = next_addr<EOL><DEDENT>return next_ip<EOL>
|
Process a REIL instruction.
Args:
instr (ReilInstruction): Instruction to process.
avoid (list): List of addresses to avoid while executing the code.
next_addr (int): Address of the following instruction.
initial_state (State): Initial execution state.
execution_state (Queue): Queue of execution states.
trace_current (list): Current trace.
Returns:
int: Returns the next address to execute.
|
f3302:c2:m10
|
def __fa_process_sequence(self, sequence, avoid, initial_state, execution_state, trace_current, next_addr):
|
<EOL>ip = sequence.address<EOL>next_ip = None<EOL>while ip:<EOL><INDENT>try:<EOL><INDENT>instr = sequence.fetch(ip)<EOL><DEDENT>except ReilSequenceInvalidAddressError:<EOL><INDENT>assert split_address(ip)[<NUM_LIT:1>] == <NUM_LIT><EOL>next_ip = ip<EOL>break<EOL><DEDENT>try:<EOL><INDENT>target_addr = sequence.get_next_address(ip)<EOL><DEDENT>except ReilSequenceInvalidAddressError:<EOL><INDENT>target_addr = next_addr<EOL><DEDENT>next_ip = self.__process_instr(instr, avoid, target_addr, initial_state, execution_state, trace_current)<EOL>try:<EOL><INDENT>ip = next_ip if next_ip else sequence.get_next_address(ip)<EOL><DEDENT>except ReilSequenceInvalidAddressError:<EOL><INDENT>break<EOL><DEDENT><DEDENT>return next_ip<EOL>
|
Process a REIL sequence.
Args:
sequence (ReilSequence): A REIL sequence to process.
avoid (list): List of address to avoid.
initial_state: Initial state.
execution_state: Execution state queue.
trace_current (list): Current trace.
next_addr: Address of the next instruction following the current one.
Returns:
Returns the next instruction to execute in case there is one, otherwise returns None.
|
f3302:c2:m12
|
def __fa_process_container(self, container, find, start, end, avoid, initial_state, execution_state, trace_current,<EOL>trace_final):
|
ip = start<EOL>while ip:<EOL><INDENT>try:<EOL><INDENT>instr = container.fetch(ip)<EOL><DEDENT>except ReilContainerInvalidAddressError:<EOL><INDENT>logger.debug("<STR_LIT>".format(ip))<EOL>raise ReilContainerInvalidAddressError<EOL><DEDENT>try:<EOL><INDENT>next_addr = container.get_next_address(ip)<EOL><DEDENT>except Exception:<EOL><INDENT>logger.debug("<STR_LIT>".format(ip))<EOL>raise ReilContainerInvalidAddressError<EOL><DEDENT>next_ip = self.__process_instr(instr, avoid, next_addr, initial_state, execution_state, trace_current)<EOL>if find and next_ip and next_ip == find:<EOL><INDENT>logger.debug("<STR_LIT>")<EOL>trace_final.append(list(trace_current))<EOL>next_ip = None<EOL><DEDENT>if end and next_ip and next_ip == end:<EOL><INDENT>logger.debug("<STR_LIT>")<EOL>next_ip = None<EOL><DEDENT>ip = next_ip if next_ip else None<EOL>while not ip:<EOL><INDENT>if not execution_state.empty():<EOL><INDENT>ip, trace_current, registers, memory = execution_state.get()<EOL>if split_address(ip)[<NUM_LIT:1>] == <NUM_LIT>:<EOL><INDENT>logger.debug("<STR_LIT>".format(ip))<EOL><DEDENT>else:<EOL><INDENT>logger.debug("<STR_LIT>".format(ip))<EOL><DEDENT>self.__cpu.registers = registers<EOL>self.__cpu.memory = memory<EOL>logger.debug("<STR_LIT>".format(ip >> <NUM_LIT:8>, ip & <NUM_LIT>))<EOL><DEDENT>else:<EOL><INDENT>logger.debug("<STR_LIT>")<EOL>break<EOL><DEDENT>if find and ip == find:<EOL><INDENT>logger.debug("<STR_LIT>")<EOL>trace_final.append(list(trace_current))<EOL>ip = None<EOL><DEDENT>if end and ip == end:<EOL><INDENT>logger.debug("<STR_LIT>")<EOL>ip = None<EOL><DEDENT><DEDENT><DEDENT>
|
Process a REIL container.
Args:
avoid (list): List of addresses to avoid while executing the code.
container (ReilContainer): REIL container to execute.
end (int): End address.
execution_state (Queue): Queue of execution states.
find (int): Address to find.
initial_state (State): Initial state.
start (int): Start address.
trace_current:
trace_final:
|
f3302:c2:m13
|
def translate(self, instruction):
|
try:<EOL><INDENT>trans_instrs = self._translate(instruction)<EOL><DEDENT>except Exception:<EOL><INDENT>self._log_translation_exception(instruction)<EOL>raise TranslationError("<STR_LIT>")<EOL><DEDENT>return trans_instrs<EOL>
|
Return REIL representation of an instruction.
|
f3304:c3:m1
|
def reset(self):
|
self._ir_name_generator.reset()<EOL>
|
Restart REIL register name generator.
|
f3304:c3:m2
|
def infer_operands_size(operands):
|
size = None<EOL>for oprnd in operands:<EOL><INDENT>if oprnd.size:<EOL><INDENT>size = oprnd.size<EOL>break<EOL><DEDENT><DEDENT>if size:<EOL><INDENT>for oprnd in operands:<EOL><INDENT>if not oprnd.size:<EOL><INDENT>oprnd.size = size<EOL><DEDENT><DEDENT><DEDENT>else:<EOL><INDENT>for oprnd in operands:<EOL><INDENT>if isinstance(oprnd, X86ImmediateOperand) and not oprnd.size:<EOL><INDENT>oprnd.size = arch_info.architecture_size<EOL><DEDENT><DEDENT><DEDENT>
|
Infer x86 instruction operand size based on other operands.
|
f3305:m0
|
def parse_operand(string, location, tokens):
|
mod = "<STR_LIT:U+0020>".join(tokens.get("<STR_LIT>", "<STR_LIT>"))<EOL>if "<STR_LIT>" in tokens:<EOL><INDENT>imm = parse_immediate("<STR_LIT>".join(tokens["<STR_LIT>"]))<EOL>size = modifier_size.get(mod, None)<EOL>oprnd = X86ImmediateOperand(imm, size)<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>name = tokens["<STR_LIT>"]<EOL>size = arch_info.registers_size[tokens["<STR_LIT>"]]<EOL>oprnd = X86RegisterOperand(name, size)<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>seg_reg = tokens.get("<STR_LIT>", None)<EOL>base_reg = tokens.get("<STR_LIT>", None)<EOL>index_reg = tokens.get("<STR_LIT:index>", None)<EOL>scale_imm = int(tokens.get("<STR_LIT>", "<STR_LIT>"), <NUM_LIT:16>)<EOL>displ_imm = int("<STR_LIT>".join(tokens.get("<STR_LIT>", "<STR_LIT>")), <NUM_LIT:16>)<EOL>oprnd = X86MemoryOperand(seg_reg, base_reg, index_reg, scale_imm, displ_imm)<EOL><DEDENT>oprnd.modifier = mod<EOL>if not oprnd.size and oprnd.modifier:<EOL><INDENT>oprnd.size = modifier_size[oprnd.modifier]<EOL><DEDENT>return oprnd<EOL>
|
Parse an x86 instruction operand.
|
f3305:m2
|
def parse_instruction(string, location, tokens):
|
prefix_str = tokens.get("<STR_LIT>", None)<EOL>mnemonic_str = tokens.get("<STR_LIT>")<EOL>operands = [op for op in tokens.get("<STR_LIT>", [])]<EOL>infer_operands_size(operands)<EOL>if prefix_str == "<STR_LIT>" and (mnemonic_str.startswith("<STR_LIT>") or mnemonic_str.startswith("<STR_LIT>")):<EOL><INDENT>prefix_str = "<STR_LIT>"<EOL><DEDENT>instr = X86Instruction(<EOL>prefix_str,<EOL>mnemonic_str,<EOL>operands,<EOL>arch_info.architecture_mode<EOL>)<EOL>return instr<EOL>
|
Parse an x86 instruction.
|
f3305:m3
|
def parse(self, instr):
|
try:<EOL><INDENT>instr_lower = instr.lower()<EOL>if instr_lower not in self._cache:<EOL><INDENT>instr_asm = instruction.parseString(instr_lower)[<NUM_LIT:0>]<EOL>self._cache[instr_lower] = instr_asm<EOL><DEDENT>instr_asm = copy.deepcopy(self._cache[instr_lower])<EOL><DEDENT>except Exception:<EOL><INDENT>instr_asm = None<EOL>error_msg = "<STR_LIT>"<EOL>logger.error(error_msg, instr, exc_info=True)<EOL><DEDENT>return instr_asm<EOL>
|
Parse an x86 instruction.
|
f3305:c0:m1
|
@property<EOL><INDENT>def registers(self):<DEDENT>
|
return self._registers_all<EOL>
|
Return all registers.
|
f3306:c0:m5
|
@property<EOL><INDENT>def registers_all(self):<DEDENT>
|
return self._registers_all<EOL>
|
Return all registers.
|
f3306:c0:m6
|
@property<EOL><INDENT>def registers_gp_all(self):<DEDENT>
|
return self._registers_gp_all<EOL>
|
Return all general purpose registers.
|
f3306:c0:m7
|
@property<EOL><INDENT>def registers_gp_base(self):<DEDENT>
|
return self._registers_gp_base<EOL>
|
Return base general purpose registers.
|
f3306:c0:m8
|
@property<EOL><INDENT>def registers_flags(self):<DEDENT>
|
return self._registers_flags<EOL>
|
Return flag registers.
|
f3306:c0:m9
|
@property<EOL><INDENT>def registers_size(self):<DEDENT>
|
return self._registers_size<EOL>
|
Return the size of all registers.
|
f3306:c0:m10
|
@property<EOL><INDENT>def alias_mapper(self):<DEDENT>
|
return self._alias_mapper<EOL>
|
Return registers alias mapper.
|
f3306:c0:m11
|
@property<EOL><INDENT>def max_instruction_size(self):<DEDENT>
|
instruction_size_map = {<EOL>ARCH_X86_MODE_32: <NUM_LIT:16>,<EOL>ARCH_X86_MODE_64: <NUM_LIT:16>,<EOL>}<EOL>return instruction_size_map[self._arch_mode]<EOL>
|
Return the maximum instruction size in bytes.
|
f3306:c0:m12
|
@property<EOL><INDENT>def prefix(self):<DEDENT>
|
return self._prefix<EOL>
|
Get instruction prefix.
|
f3306:c1:m1
|
@property<EOL><INDENT>def mnemonic(self):<DEDENT>
|
return self._mnemonic<EOL>
|
Get instruction mnemonic.
|
f3306:c1:m2
|
@property<EOL><INDENT>def operands(self):<DEDENT>
|
return self._operands<EOL>
|
Get instruction operands.
|
f3306:c1:m3
|
@property<EOL><INDENT>def bytes(self):<DEDENT>
|
return self._bytes<EOL>
|
Get instruction byte representation.
|
f3306:c1:m4
|
@bytes.setter<EOL><INDENT>def bytes(self, value):<DEDENT>
|
self._bytes = value<EOL>
|
Set instruction byte representation.
|
f3306:c1:m5
|
@property<EOL><INDENT>def size(self):<DEDENT>
|
return self._size<EOL>
|
Get instruction size.
|
f3306:c1:m6
|
@size.setter<EOL><INDENT>def size(self, value):<DEDENT>
|
self._size = value<EOL>
|
Set instruction size.
|
f3306:c1:m7
|
@property<EOL><INDENT>def address(self):<DEDENT>
|
return self._address<EOL>
|
Get instruction address.
|
f3306:c1:m8
|
@address.setter<EOL><INDENT>def address(self, value):<DEDENT>
|
self._address = value<EOL>
|
Set instruction address.
|
f3306:c1:m9
|
@property<EOL><INDENT>def modifier(self):<DEDENT>
|
return self._modifier<EOL>
|
Get operand modifier.
|
f3306:c2:m1
|
@modifier.setter<EOL><INDENT>def modifier(self, value):<DEDENT>
|
self._modifier = value<EOL>
|
Set operand modifier.
|
f3306:c2:m2
|
@property<EOL><INDENT>def size(self):<DEDENT>
|
return self._size<EOL>
|
Get operand size.
|
f3306:c2:m3
|
@size.setter<EOL><INDENT>def size(self, value):<DEDENT>
|
self._size = value<EOL>
|
Set operand size.
|
f3306:c2:m4
|
@property<EOL><INDENT>def immediate(self):<DEDENT>
|
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._immediate<EOL>
|
Get immediate.
|
f3306:c3:m1
|
@property<EOL><INDENT>def name(self):<DEDENT>
|
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._name<EOL>
|
Get register name.
|
f3306:c4:m1
|
@property<EOL><INDENT>def segment(self):<DEDENT>
|
return self._segment<EOL>
|
Get segment selector register.
|
f3306:c5:m1
|
@property<EOL><INDENT>def base(self):<DEDENT>
|
return self._base<EOL>
|
Get base register.
|
f3306:c5:m2
|
@property<EOL><INDENT>def index(self):<DEDENT>
|
return self._index<EOL>
|
Get index register.
|
f3306:c5:m3
|
@property<EOL><INDENT>def scale(self):<DEDENT>
|
return self._scale<EOL>
|
Get scale value.
|
f3306:c5:m4
|
@property<EOL><INDENT>def displacement(self):<DEDENT>
|
return self._displacement<EOL>
|
Get displacement value.
|
f3306:c5:m5
|
def resolve_memory_access(self, tb, x86_mem_operand):
|
size = self.__get_memory_access_size(x86_mem_operand)<EOL>addr = None<EOL>if x86_mem_operand.base:<EOL><INDENT>addr = ReilRegisterOperand(x86_mem_operand.base, size)<EOL><DEDENT>if x86_mem_operand.index and x86_mem_operand.scale != <NUM_LIT>:<EOL><INDENT>index = ReilRegisterOperand(x86_mem_operand.index, size)<EOL>scale = ReilImmediateOperand(x86_mem_operand.scale, size)<EOL>scaled_index = tb.temporal(size)<EOL>tb.add(tb._builder.gen_mul(index, scale, scaled_index))<EOL>if addr:<EOL><INDENT>tmp = tb.temporal(size)<EOL>tb.add(tb._builder.gen_add(addr, scaled_index, tmp))<EOL>addr = tmp<EOL><DEDENT>else:<EOL><INDENT>addr = scaled_index<EOL><DEDENT><DEDENT>if x86_mem_operand.displacement != <NUM_LIT>:<EOL><INDENT>disp = ReilImmediateOperand(x86_mem_operand.displacement, size)<EOL>if addr:<EOL><INDENT>tmp = tb.temporal(size)<EOL>tb.add(tb._builder.gen_add(addr, disp, tmp))<EOL>addr = tmp<EOL><DEDENT>else:<EOL><INDENT>addr = disp<EOL><DEDENT><DEDENT>else:<EOL><INDENT>if not addr:<EOL><INDENT>disp = ReilImmediateOperand(x86_mem_operand.displacement, size)<EOL>addr = disp<EOL><DEDENT><DEDENT>if x86_mem_operand.segment in ["<STR_LIT>", "<STR_LIT>"]:<EOL><INDENT>seg_base_addr_map = {<EOL>"<STR_LIT>": "<STR_LIT>",<EOL>"<STR_LIT>": "<STR_LIT>",<EOL>}<EOL>seg_base = ReilRegisterOperand(seg_base_addr_map[x86_mem_operand.segment], size)<EOL>if addr:<EOL><INDENT>tmp = tb.temporal(size)<EOL>tb.add(tb._builder.gen_add(addr, seg_base, tmp))<EOL>addr = tmp<EOL><DEDENT>else:<EOL><INDENT>addr = seg_base<EOL><DEDENT><DEDENT>return addr<EOL>
|
Return operand memory access translation.
|
f3307:c1:m3
|
def disassemble(self, data, address, architecture_mode=ARCH_X86_MODE_32):
|
asm, size = self._cs_disassemble_one(data, address)<EOL>instr = self._parser.parse(asm) if asm else None<EOL>if instr:<EOL><INDENT>instr.address = address<EOL>instr.size = size<EOL>instr.bytes = data[<NUM_LIT:0>:size]<EOL><DEDENT>else:<EOL><INDENT>raise DisassemblerError()<EOL><DEDENT>return instr<EOL>
|
Disassemble the data into an instruction.
|
f3308:c0:m1
|
def disassemble_all(self, data, address):
|
raise NotImplementedError()<EOL>
|
Disassemble the data into multiple instructions.
|
f3308:c0:m2
|
def _cs_disassemble_one(self, data, address):
|
asm, size = "<STR_LIT>", <NUM_LIT:0><EOL>disasm = list(self._disassembler.disasm_lite(bytes(data), address))<EOL>if len(disasm) > <NUM_LIT:0>:<EOL><INDENT>address, size, mnemonic, op_str = disasm[<NUM_LIT:0>]<EOL>asm = str(mnemonic + "<STR_LIT:U+0020>" + op_str).strip()<EOL><DEDENT>if asm in ["<STR_LIT>", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>"]:<EOL><INDENT>asm, size = "<STR_LIT>", <NUM_LIT:0><EOL><DEDENT>return asm, size<EOL>
|
Disassemble the data into an instruction in string form.
|
f3308:c0:m3
|
def disassemble(self, data, address):
|
raise NotImplementedError()<EOL>
|
Disassemble raw bytes into an instruction.
|
f3323:c2:m0
|
def disassemble_all(self, data, address):
|
raise NotImplementedError()<EOL>
|
Disassemble raw bytes into multiple instructions.
|
f3323:c2:m1
|
def parse_operand(string, location, tokens):
|
if "<STR_LIT>" in tokens:<EOL><INDENT>size = arch_info.operand_size<EOL>oprnd = ArmImmediateOperand("<STR_LIT>".join(tokens["<STR_LIT>"]), size)<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>oprnd = process_register(tokens["<STR_LIT>"])<EOL>if "<STR_LIT:wb>" in tokens["<STR_LIT>"]:<EOL><INDENT>oprnd.wb = True<EOL><DEDENT><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>mem_oprnd = tokens["<STR_LIT>"]<EOL>if "<STR_LIT>" in mem_oprnd:<EOL><INDENT>index_type = ARM_MEMORY_INDEX_OFFSET<EOL>mem_oprnd = mem_oprnd["<STR_LIT>"]<EOL><DEDENT>elif "<STR_LIT>" in mem_oprnd:<EOL><INDENT>index_type = ARM_MEMORY_INDEX_PRE<EOL>mem_oprnd = mem_oprnd["<STR_LIT>"]<EOL><DEDENT>elif "<STR_LIT>" in mem_oprnd:<EOL><INDENT>index_type = ARM_MEMORY_INDEX_POST<EOL>mem_oprnd = mem_oprnd["<STR_LIT>"]<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>reg_base = process_register(mem_oprnd["<STR_LIT>"])<EOL>disp = mem_oprnd.get("<STR_LIT>", None)<EOL>disp_minus = True if mem_oprnd.get("<STR_LIT>") else False<EOL>if disp:<EOL><INDENT>if "<STR_LIT>" in disp:<EOL><INDENT>displ_imm = process_shifted_register(disp["<STR_LIT>"])<EOL><DEDENT>elif "<STR_LIT>" in disp:<EOL><INDENT>displ_imm = process_register(disp["<STR_LIT>"])<EOL><DEDENT>elif "<STR_LIT>" in disp:<EOL><INDENT>displ_imm = ArmImmediateOperand("<STR_LIT>".join(disp["<STR_LIT>"]), arch_info.operand_size)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT><DEDENT>else:<EOL><INDENT>displ_imm = None<EOL><DEDENT>size = arch_info.operand_size<EOL>oprnd = ArmMemoryOperand(reg_base, index_type, displ_imm, disp_minus, size)<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>oprnd = process_shifted_register(tokens["<STR_LIT>"])<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>parsed_reg_list = tokens["<STR_LIT>"]<EOL>reg_list = []<EOL>for reg_range in parsed_reg_list:<EOL><INDENT>start_reg = process_register(reg_range[<NUM_LIT:0>])<EOL>if len(reg_range) > <NUM_LIT:1>:<EOL><INDENT>end_reg = process_register(reg_range[<NUM_LIT:1>])<EOL>reg_list.append([start_reg, end_reg])<EOL><DEDENT>else:<EOL><INDENT>reg_list.append([start_reg])<EOL><DEDENT><DEDENT>oprnd = ArmRegisterListOperand(reg_list, reg_list[<NUM_LIT:0>][<NUM_LIT:0>].size)<EOL><DEDENT>return oprnd<EOL>
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Parse an ARM instruction operand.
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f3324:m2
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