signature
stringlengths 8
3.44k
| body
stringlengths 0
1.41M
| docstring
stringlengths 1
122k
| id
stringlengths 5
17
|
|---|---|---|---|
def acceleration(self):
|
if not self.awake:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>raw = self.i2c_read_register(<NUM_LIT>, <NUM_LIT:6>)<EOL>x, y, z = struct.unpack('<STR_LIT>', raw)<EOL>scales = {<EOL>self.RANGE_ACCEL_2G: <NUM_LIT>,<EOL>self.RANGE_ACCEL_4G: <NUM_LIT>,<EOL>self.RANGE_ACCEL_8G: <NUM_LIT>,<EOL>self.RANGE_ACCEL_16G: <NUM_LIT><EOL>}<EOL>scale = scales[self.accel_range]<EOL>return x / scale, y / scale, z / scale<EOL>
|
Return the acceleration in G's
:returns: Acceleration for every axis as a tuple
:Example:
>>> sensor = MPU6050I2C(gw)
>>> sensor.wakeup()
>>> sensor.acceleration()
(0.6279296875, 0.87890625, 1.1298828125)
|
f3219:c0:m6
|
def angular_rate(self):
|
if not self.awake:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>raw = self.i2c_read_register(<NUM_LIT>, <NUM_LIT:6>)<EOL>x, y, z = struct.unpack('<STR_LIT>', raw)<EOL>scales = {<EOL>self.RANGE_GYRO_250DEG: <NUM_LIT>,<EOL>self.RANGE_GYRO_500DEG: <NUM_LIT>,<EOL>self.RANGE_GYRO_1000DEG: <NUM_LIT>,<EOL>self.RANGE_GYRO_2000DEG: <NUM_LIT><EOL>}<EOL>scale = scales[self.gyro_range]<EOL>return x / scale, y / scale, z / scale<EOL>
|
Return the angular rate for every axis in degree/second.
:returns: Angular rate for every axis as a tuple
:Example:
>>> sensor = MPU6050I2C(gw)
>>> sensor.wakeup()
>>> sensor.angular_rate()
(1.380859375, 1.6318359375, 1.8828125)
|
f3219:c0:m7
|
def temperature(self):
|
result = self.i2c_read(<NUM_LIT:2>)<EOL>value = struct.unpack('<STR_LIT>', result)[<NUM_LIT:0>]<EOL>if value < <NUM_LIT>:<EOL><INDENT>return value / <NUM_LIT><EOL><DEDENT>else:<EOL><INDENT>return (value - <NUM_LIT>) / <NUM_LIT><EOL><DEDENT>
|
Get the temperature in degree celcius
|
f3220:c0:m1
|
def load_calibration(self):
|
registers = self.i2c_read_register(<NUM_LIT>, <NUM_LIT>)<EOL>(<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>'],<EOL>self.cal['<STR_LIT>']<EOL>) = struct.unpack('<STR_LIT>', registers)<EOL>
|
Load factory calibration data from device.
|
f3221:c0:m1
|
def temperature(self):
|
ut = self.get_raw_temp()<EOL>x1 = ((ut - self.cal['<STR_LIT>']) * self.cal['<STR_LIT>']) >> <NUM_LIT:15><EOL>x2 = (self.cal['<STR_LIT>'] << <NUM_LIT:11>) // (x1 + self.cal['<STR_LIT>'])<EOL>b5 = x1 + x2<EOL>return ((b5 + <NUM_LIT:8>) >> <NUM_LIT:4>) / <NUM_LIT:10><EOL>
|
Get the temperature from the sensor.
:returns: The temperature in degree celcius as a float
:example:
>>> sensor = BMP180(gw)
>>> sensor.load_calibration()
>>> sensor.temperature()
21.4
|
f3221:c0:m4
|
def pressure(self):
|
ut = self.get_raw_temp()<EOL>up = self.get_raw_pressure()<EOL>x1 = ((ut - self.cal['<STR_LIT>']) * self.cal['<STR_LIT>']) >> <NUM_LIT:15><EOL>x2 = (self.cal['<STR_LIT>'] << <NUM_LIT:11>) // (x1 + self.cal['<STR_LIT>'])<EOL>b5 = x1 + x2<EOL>b6 = b5 - <NUM_LIT><EOL>x1 = (self.cal['<STR_LIT>'] * (b6 * b6) >> <NUM_LIT:12>) >> <NUM_LIT:11><EOL>x2 = (self.cal['<STR_LIT>'] * b6) >> <NUM_LIT:11><EOL>x3 = x1 + x2<EOL>b3 = (((self.cal['<STR_LIT>'] * <NUM_LIT:4> + x3) << self.mode) + <NUM_LIT:2>) // <NUM_LIT:4><EOL>x1 = (self.cal['<STR_LIT>'] * b6) >> <NUM_LIT><EOL>x2 = (self.cal['<STR_LIT>'] * ((b6 * b6) >> <NUM_LIT:12>)) >> <NUM_LIT:16><EOL>x3 = ((x1 + x2) + <NUM_LIT:2>) >> <NUM_LIT:2><EOL>b4 = (self.cal['<STR_LIT>'] * (x3 + <NUM_LIT>)) >> <NUM_LIT:15><EOL>b7 = (up - b3) * (<NUM_LIT> >> self.mode)<EOL>if b7 < <NUM_LIT>:<EOL><INDENT>p = (b7 * <NUM_LIT:2>) // b4<EOL><DEDENT>else:<EOL><INDENT>p = (b7 // b4) * <NUM_LIT:2><EOL><DEDENT>x1 = (p >> <NUM_LIT:8>) * (p >> <NUM_LIT:8>)<EOL>x1 = (x1 * <NUM_LIT>) >> <NUM_LIT:16><EOL>x2 = (-<NUM_LIT> * p) >> <NUM_LIT:16><EOL>p += (x1 + x2 + <NUM_LIT>) >> <NUM_LIT:4><EOL>return p<EOL>
|
Get barometric pressure in milibar
:returns: The pressure in milibar as a int
:example:
>>> sensor = BMP180(gw)
>>> sensor.load_calibration()
>>> sensor.pressure()
75216
|
f3221:c0:m5
|
def read(self, pin):
|
port, pin = self.pin_to_port(pin)<EOL>self.i2c_write([<NUM_LIT> + port])<EOL>raw = self.i2c_read(<NUM_LIT:1>)<EOL>value = struct.unpack('<STR_LIT>', raw)[<NUM_LIT:0>]<EOL>return (value & (<NUM_LIT:1> << pin)) > <NUM_LIT:0><EOL>
|
Read the pin state of an input pin.
Make sure you put the pin in input modus with the IODIR* register or direction_* attribute first.
:Example:
>>> expander = MCP23017I2C(gw)
>>> # Read the logic level on pin B3
>>> expander.read('B3')
False
>>> # Read the logic level on pin A1
>>> expander.read('A1')
True
:param pin: The label for the pin to read. (Ex. A0)
:return: Boolean representing the input level
|
f3222:c0:m3
|
def read_port(self, port):
|
if port == '<STR_LIT:A>':<EOL><INDENT>raw = self.i2c_read_register(<NUM_LIT>, <NUM_LIT:1>)<EOL><DEDENT>elif port == '<STR_LIT:B>':<EOL><INDENT>raw = self.i2c_read_register(<NUM_LIT>, <NUM_LIT:1>)<EOL><DEDENT>return struct.unpack('<STR_LIT>', raw)[<NUM_LIT:0>]<EOL>
|
Read the pin state of a whole port (8 pins)
:Example:
>>> expander = MCP23017I2C(gw)
>>> # Read pin A0-A7 as a int (A0 and A1 are high)
>>> expander.read_port('A')
3
>>> # Read pin B0-B7 as a int (B2 is high)
>>> expander.read_port('B')
4
:param port: use 'A' to read port A and 'B' for port b
:return: An int where every bit represents the input level.
|
f3222:c0:m4
|
def write(self, pin, value):
|
port, pin = self.pin_to_port(pin)<EOL>portname = '<STR_LIT:A>'<EOL>if port == <NUM_LIT:1>:<EOL><INDENT>portname = '<STR_LIT:B>'<EOL><DEDENT>self._update_register('<STR_LIT>' + portname, pin, value)<EOL>self.sync()<EOL>
|
Set the pin state.
Make sure you put the pin in output mode first.
:param pin: The label for the pin to write to. (Ex. A0)
:param value: Boolean representing the new state
|
f3222:c0:m5
|
def write_port(self, port, value):
|
if port == '<STR_LIT:A>':<EOL><INDENT>self.GPIOA = value<EOL><DEDENT>elif port == '<STR_LIT:B>':<EOL><INDENT>self.GPIOB = value<EOL><DEDENT>else:<EOL><INDENT>raise AttributeError('<STR_LIT>'.format(port))<EOL><DEDENT>self.sync()<EOL>
|
Use a whole port as a bus and write a byte to it.
:param port: Name of the port ('A' or 'B')
:param value: Value to write (0-255)
|
f3222:c0:m6
|
def sync(self):
|
registers = {<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>',<EOL><NUM_LIT>: '<STR_LIT>'<EOL>}<EOL>for reg in registers:<EOL><INDENT>name = registers[reg]<EOL>if getattr(self, name) != getattr(self, '<STR_LIT:_>' + name):<EOL><INDENT>self.i2c_write_register(reg, [getattr(self, name)])<EOL>setattr(self, '<STR_LIT:_>' + name, getattr(self, name))<EOL><DEDENT><DEDENT>
|
Upload the changed registers to the chip
This will check which register have been changed since the last sync and send them to the chip.
You need to call this method if you modify one of the register attributes (mcp23017.IODIRA for example) or
if you use one of the helper attributes (mcp23017.direction_A0 for example)
|
f3222:c0:m7
|
def get_pins(self):
|
result = []<EOL>for a in range(<NUM_LIT:0>, <NUM_LIT:7>):<EOL><INDENT>result.append(GPIOPin(self, '<STR_LIT>', {'<STR_LIT>': '<STR_LIT>'.format(a)}, name='<STR_LIT>'.format(a)))<EOL><DEDENT>for b in range(<NUM_LIT:0>, <NUM_LIT:7>):<EOL><INDENT>result.append(GPIOPin(self, '<STR_LIT>', {'<STR_LIT>': '<STR_LIT>'.format(b)}, name='<STR_LIT>'.format(b)))<EOL><DEDENT>return result<EOL>
|
Get a list containing references to all 16 pins of the chip.
:Example:
>>> expander = MCP23017I2C(gw)
>>> pins = expander.get_pins()
>>> pprint.pprint(pins)
[<GPIOPin A0 on MCP23017I2C>,
<GPIOPin A1 on MCP23017I2C>,
<GPIOPin A2 on MCP23017I2C>,
<GPIOPin A3 on MCP23017I2C>,
<GPIOPin A4 on MCP23017I2C>,
<GPIOPin A5 on MCP23017I2C>,
<GPIOPin A6 on MCP23017I2C>,
<GPIOPin B0 on MCP23017I2C>,
<GPIOPin B1 on MCP23017I2C>,
<GPIOPin B2 on MCP23017I2C>,
<GPIOPin B3 on MCP23017I2C>,
<GPIOPin B4 on MCP23017I2C>,
<GPIOPin B5 on MCP23017I2C>,
<GPIOPin B6 on MCP23017I2C>]
|
f3222:c0:m10
|
def get_pin(self, name):
|
return GPIOPin(self, '<STR_LIT>', {'<STR_LIT>': name}, name=name)<EOL>
|
Get a reference to a named pin on the chip.
:Example:
>>> expander = MCP23017I2C(gw)
>>> expander.get_pin('B3')
<GPIOPin B3 on MCP23017I2C>
:param name: Name of the pin (Ex: B3)
:return: GPIOPin instance for the pin
|
f3222:c0:m11
|
def config(self, averaging=<NUM_LIT:1>, datarate=<NUM_LIT:15>, mode=MODE_NORMAL):
|
averaging_conf = {<EOL><NUM_LIT:1>: <NUM_LIT:0>,<EOL><NUM_LIT:2>: <NUM_LIT:1>,<EOL><NUM_LIT:4>: <NUM_LIT:2>,<EOL><NUM_LIT:8>: <NUM_LIT:3><EOL>}<EOL>if averaging not in averaging_conf.keys():<EOL><INDENT>raise Exception('<STR_LIT>')<EOL><DEDENT>datarates = {<EOL><NUM_LIT>: <NUM_LIT:0>,<EOL><NUM_LIT>: <NUM_LIT:1>,<EOL><NUM_LIT:3>: <NUM_LIT:2>,<EOL><NUM_LIT>: <NUM_LIT:4>,<EOL><NUM_LIT:15>: <NUM_LIT:5>,<EOL><NUM_LIT:30>: <NUM_LIT:6>,<EOL><NUM_LIT>: <NUM_LIT:7><EOL>}<EOL>if datarate not in datarates.keys():<EOL><INDENT>raise Exception(<EOL>'<STR_LIT>'.format(datarate, '<STR_LIT:U+002CU+0020>'.join(datarates.keys())))<EOL><DEDENT>config_a = <NUM_LIT:0><EOL>config_a &= averaging_conf[averaging] << <NUM_LIT:5><EOL>config_a &= datarates[datarate] << <NUM_LIT:2><EOL>config_a &= mode<EOL>self.i2c_write_register(<NUM_LIT>, config_a)<EOL>
|
Set the base config for sensor
:param averaging: Sets the numer of samples that are internally averaged
:param datarate: Datarate in hertz
:param mode: one of the MODE_* constants
|
f3224:c0:m1
|
def set_resolution(self, resolution=<NUM_LIT>):
|
options = {<EOL><NUM_LIT>: <NUM_LIT:0>,<EOL><NUM_LIT>: <NUM_LIT:1>,<EOL><NUM_LIT>: <NUM_LIT:2>,<EOL><NUM_LIT>: <NUM_LIT:3>,<EOL><NUM_LIT>: <NUM_LIT:4>,<EOL><NUM_LIT>: <NUM_LIT:5>,<EOL><NUM_LIT>: <NUM_LIT:6>,<EOL><NUM_LIT>: <NUM_LIT:7><EOL>}<EOL>if resolution not in options.keys():<EOL><INDENT>raise Exception('<STR_LIT>'.format(resolution))<EOL><DEDENT>self.resolution = resolution<EOL>config_b = <NUM_LIT:0><EOL>config_b &= options[resolution] << <NUM_LIT:5><EOL>self.i2c_write_register(<NUM_LIT>, config_b)<EOL>
|
Set the resolution of the sensor
The resolution value is the amount of steps recorded in a single Gauss. The possible options are:
======================= ========== =============
Recommended Gauss range Resolution Gauss per bit
======================= ========== =============
0.88 Ga 1370 0.73 mGa
1.3 Ga 1090 0.92 mGa
1.9 Ga 820 1.22 mGa
2.5 Ga 660 1.52 mGa
4.0 Ga 440 2.27 mGa
4.7 Ga 390 2.56 mGa
5.6 Ga 330 3.03 mGa
8.1 Ga 230 4.35 mGa
======================= ========== =============
:param resolution: The resolution of the sensor
|
f3224:c0:m2
|
def raw(self):
|
result = self.i2c_read_register(<NUM_LIT>, <NUM_LIT:6>)<EOL>return struct.unpack('<STR_LIT>', result)<EOL>
|
Get the magnetometer values as raw data from the sensor as tuple (x,y,z)
:example:
>>> sensor = HMC5883L(gw)
>>> sensor.raw()
(3342, 3856, 4370)
|
f3224:c0:m3
|
def gauss(self):
|
raw = self.raw()<EOL>factors = {<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT>,<EOL><NUM_LIT>: <NUM_LIT><EOL>}<EOL>factor = factors[self.resolution] / <NUM_LIT:100><EOL>return raw[<NUM_LIT:0>] * factor, raw[<NUM_LIT:1>] * factor, raw[<NUM_LIT:2>] * factor<EOL>
|
Get the magnetometer values as gauss for each axis as a tuple (x,y,z)
:example:
>>> sensor = HMC5883L(gw)
>>> sensor.gauss()
(16.56, 21.2888, 26.017599999999998)
|
f3224:c0:m4
|
def __init__(self, segments):
|
if isinstance(segments, list):<EOL><INDENT>segments = GPIOBus(segments)<EOL><DEDENT>if segments.width == <NUM_LIT:7>:<EOL><INDENT>self.font = SevenSegmentDisplayFont()<EOL><DEDENT>if segments.width == <NUM_LIT>:<EOL><INDENT>self.font = FourteenSegmentDisplayFont()<EOL><DEDENT>else:<EOL><INDENT>raise AttributeError('<STR_LIT>')<EOL><DEDENT>self.segments = segments<EOL>
|
:param segments: GPIOBus instance with the pins or array of pins
|
f3225:c2:m0
|
def write(self, char):
|
char = str(char).lower()<EOL>self.segments.write(self.font[char])<EOL>
|
Display a single character on the display
:type char: str or int
:param char: Character to display
|
f3225:c2:m1
|
def read(self):
|
m = getattr(self.chip, self.method)<EOL>return m(**self.arguments)<EOL>
|
Get the logic input level for the pin
:return: True if the input is high
|
f3226:c1:m0
|
def write(self, value):
|
m = getattr(self.chip, self.method)<EOL>m(value, **self.arguments)<EOL>
|
Set the logic output level for the pin.
:type value: bool
:param value: True for a logic high
|
f3226:c2:m0
|
def read(self):
|
m = getattr(self.chip, self.method)<EOL>return m(value=None, **self.arguments)<EOL>
|
Get the logic input level for the pin
:return: True if the input is high
|
f3226:c3:m2
|
def write(self, value):
|
if self.inverted:<EOL><INDENT>value = not value<EOL><DEDENT>m = getattr(self.chip, self.method)<EOL>m(value=value, **self.arguments)<EOL>
|
Set the logic output level for the pin.
:type value: bool
:param value: True for a logic high
|
f3226:c3:m3
|
def close(self):
|
self.device.close()<EOL>
|
disconnect from the hardware and make it available again.
|
f3229:c0:m1
|
def switch_mode(self, new_mode):
|
packet = bytearray()<EOL>packet.append(new_mode)<EOL>self.device.write(packet)<EOL>possible_responses = {<EOL>self.MODE_I2C: b'<STR_LIT>',<EOL>self.MODE_RAW: b'<STR_LIT>',<EOL>self.MODE_SPI: b'<STR_LIT>',<EOL>self.MODE_UART: b'<STR_LIT>',<EOL>self.MODE_ONEWIRE: b'<STR_LIT>'<EOL>}<EOL>expected = possible_responses[new_mode]<EOL>response = self.device.read(<NUM_LIT:4>)<EOL>if response != expected:<EOL><INDENT>raise Exception('<STR_LIT>')<EOL><DEDENT>self.mode = new_mode<EOL>self.set_peripheral()<EOL>if self.i2c_speed:<EOL><INDENT>self._set_i2c_speed(self.i2c_speed)<EOL><DEDENT>
|
Explicitly switch the Bus Pirate mode
:param new_mode: The mode to switch to. Use the buspirate.MODE_* constants
|
f3229:c0:m2
|
def set_peripheral(self, power=None, pullup=None, aux=None, chip_select=None):
|
if power is not None:<EOL><INDENT>self.power = power<EOL><DEDENT>if pullup is not None:<EOL><INDENT>self.pullup = pullup<EOL><DEDENT>if aux is not None:<EOL><INDENT>self.aux = aux<EOL><DEDENT>if chip_select is not None:<EOL><INDENT>self.chip_select = chip_select<EOL><DEDENT>peripheral_byte = <NUM_LIT:64><EOL>if self.chip_select:<EOL><INDENT>peripheral_byte |= <NUM_LIT><EOL><DEDENT>if self.aux:<EOL><INDENT>peripheral_byte |= <NUM_LIT><EOL><DEDENT>if self.pullup:<EOL><INDENT>peripheral_byte |= <NUM_LIT><EOL><DEDENT>if self.power:<EOL><INDENT>peripheral_byte |= <NUM_LIT><EOL><DEDENT>self.device.write(bytearray([peripheral_byte]))<EOL>response = self.device.read(<NUM_LIT:1>)<EOL>if response != b"<STR_LIT>":<EOL><INDENT>raise Exception("<STR_LIT>".format(repr(response)))<EOL><DEDENT>
|
Set the peripheral config at runtime.
If a parameter is None then the config will not be changed.
:param power: Set to True to enable the power supply or False to disable
:param pullup: Set to True to enable the internal pull-up resistors. False to disable
:param aux: Set the AUX pin output state
:param chip_select: Set the CS pin output state
|
f3229:c0:m3
|
def get_aux_pin(self):
|
return DigitalOutputPin(self, '<STR_LIT>')<EOL>
|
Get reference to the aux output on the Bus Pirate
:return: DigitalOutputPin instance
|
f3229:c0:m9
|
def get_chip_select_pin(self):
|
return DigitalOutputPin(self, '<STR_LIT>')<EOL>
|
Get reference to the chip select output on the Bus Pirate
:return: DigitalOutputPin instance
|
f3229:c0:m10
|
def _set_i2c_speed(self, i2c_speed):
|
lower_bits_mapping = {<EOL>'<STR_LIT>': <NUM_LIT:3>,<EOL>'<STR_LIT>': <NUM_LIT:2>,<EOL>'<STR_LIT>': <NUM_LIT:1>,<EOL>'<STR_LIT>': <NUM_LIT:0>,<EOL>}<EOL>if i2c_speed not in lower_bits_mapping:<EOL><INDENT>raise ValueError('<STR_LIT>')<EOL><DEDENT>speed_byte = <NUM_LIT> | lower_bits_mapping[i2c_speed]<EOL>self.device.write(bytearray([speed_byte]))<EOL>response = self.device.read(<NUM_LIT:1>)<EOL>if response != b"<STR_LIT>":<EOL><INDENT>raise Exception("<STR_LIT>".format(repr(response)))<EOL><DEDENT>
|
Set I2C speed to one of '400kHz', '100kHz', 50kHz', '5kHz'
|
f3229:c0:m13
|
def _init_context(self):
|
if os.path.isfile(self.context_filename):<EOL><INDENT>context = self._load_failing_context()<EOL><DEDENT>else:<EOL><INDENT>context = self._create_random_context()<EOL><DEDENT>return context<EOL>
|
Initialize register with random values.
|
f3254:c0:m1
|
def __init_context(self):
|
context = self.__create_random_context()<EOL>return context<EOL>
|
Initialize register with random values.
|
f3262:c0:m1
|
def load_symbols_elf(filename):
|
f = open(filename, '<STR_LIT:rb>')<EOL>elffile = ELFFile(f)<EOL>symbols = []<EOL>for section in elffile.iter_sections():<EOL><INDENT>if not isinstance(section, SymbolTableSection):<EOL><INDENT>continue<EOL><DEDENT>if section['<STR_LIT>'] == <NUM_LIT:0>:<EOL><INDENT>logger.warn("<STR_LIT>".format(section.name))<EOL>continue<EOL><DEDENT>logger.info("<STR_LIT>".format(section.name, section.num_symbols()))<EOL>for _, symbol in enumerate(section.iter_symbols()):<EOL><INDENT>if describe_symbol_shndx(symbol['<STR_LIT>']) != "<STR_LIT>" anddescribe_symbol_type(symbol['<STR_LIT>']['<STR_LIT:type>']) == "<STR_LIT>":<EOL><INDENT>symbols.append((symbol['<STR_LIT>'], symbol['<STR_LIT>'], symbol.name))<EOL><DEDENT><DEDENT><DEDENT>f.close()<EOL>symbols_by_addr = {<EOL>addr: (name, size, True) for addr, size, name in symbols<EOL>}<EOL>return symbols_by_addr<EOL>
|
Load the symbol tables contained in the file
|
f3270:m1
|
def translate(self, instr):
|
try:<EOL><INDENT>translator = self._instr_translators[instr.mnemonic]<EOL>return translator(*instr.operands)<EOL><DEDENT>except Exception:<EOL><INDENT>logger.error("<STR_LIT>", instr, exc_info=True)<EOL>raise<EOL><DEDENT>
|
Return the SMT representation of a REIL instruction.
|
f3272:c0:m1
|
def get_name_init(self, name):
|
self._register_name(name)<EOL>return self._var_name_mappers[name].get_init()<EOL>
|
Get initial name of symbol.
|
f3272:c0:m2
|
def get_name_curr(self, name):
|
self._register_name(name)<EOL>return self._var_name_mappers[name].get_current()<EOL>
|
Get current name of symbol.
|
f3272:c0:m3
|
def get_memory_curr(self):
|
return self._mem_curr<EOL>
|
Get SMT memory representation.
|
f3272:c0:m4
|
def get_memory_init(self):
|
return self._mem_init<EOL>
|
Get SMT memory representation.
|
f3272:c0:m5
|
def reset(self):
|
self._solver.reset()<EOL>self._mem_instance = <NUM_LIT:0><EOL>self._mem_init = smtsymbol.BitVecArray(self._address_size, <NUM_LIT:8>, "<STR_LIT>".format(self._mem_instance))<EOL>self._mem_curr = self.make_array(self._address_size, "<STR_LIT>".format(self._mem_instance))<EOL>self._var_name_mappers = {}<EOL>
|
Reset internal state.
|
f3272:c0:m6
|
def set_arch_alias_mapper(self, alias_mapper):
|
self._arch_alias_mapper = alias_mapper<EOL>
|
Set native register alias mapper.
This is necessary as some architecture has register alias. For
example, in Intel x86 (32 bits), *ax* refers to the lower half
of the *eax* register, so when *ax* is modified so it is *eax*.
Then, this alias_mapper is a dictionary where its keys are
registers (names, only) and each associated value is a tuple
of the form (base register name, offset).
This information is used to modified the correct register at
the correct location (within the register) when a register alias
value is changed.
|
f3272:c0:m7
|
def set_arch_registers_size(self, registers_size):
|
self._arch_regs_size = registers_size<EOL>
|
Set registers.
|
f3272:c0:m8
|
def _register_name(self, name):
|
if name not in self._var_name_mappers:<EOL><INDENT>self._var_name_mappers[name] = VariableNamer(name)<EOL><DEDENT>
|
Get register name.
|
f3272:c0:m11
|
def _get_var_name(self, name, fresh=False):
|
if name not in self._var_name_mappers:<EOL><INDENT>self._var_name_mappers[name] = VariableNamer(name)<EOL><DEDENT>if fresh:<EOL><INDENT>var_name = self._var_name_mappers[name].get_next()<EOL><DEDENT>else:<EOL><INDENT>var_name = self._var_name_mappers[name].get_current()<EOL><DEDENT>return var_name<EOL>
|
Get variable name.
|
f3272:c0:m12
|
def _translate_src_oprnd(self, operand):
|
if isinstance(operand, ReilRegisterOperand):<EOL><INDENT>return self._translate_src_register_oprnd(operand)<EOL><DEDENT>elif isinstance(operand, ReilImmediateOperand):<EOL><INDENT>return smtsymbol.Constant(operand.size, operand.immediate)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>
|
Translate source operand to a SMT expression.
|
f3272:c0:m13
|
def _translate_dst_oprnd(self, operand):
|
if isinstance(operand, ReilRegisterOperand):<EOL><INDENT>return self._translate_dst_register_oprnd(operand)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>
|
Translate destination operand to a SMT expression.
|
f3272:c0:m14
|
def _translate_src_register_oprnd(self, operand):
|
reg_info = self._arch_alias_mapper.get(operand.name, None)<EOL>if reg_info:<EOL><INDENT>var_base_name, offset = reg_info<EOL>var_size = self._arch_regs_size[var_base_name]<EOL><DEDENT>else:<EOL><INDENT>var_base_name = operand.name<EOL>var_size = operand.size<EOL><DEDENT>var_name = self._get_var_name(var_base_name)<EOL>ret_val = self.make_bitvec(var_size, var_name)<EOL>if reg_info:<EOL><INDENT>ret_val = smtfunction.extract(ret_val, offset, operand.size)<EOL><DEDENT>return ret_val<EOL>
|
Translate source register operand to SMT expr.
|
f3272:c0:m15
|
def _translate_dst_register_oprnd(self, operand):
|
reg_info = self._arch_alias_mapper.get(operand.name, None)<EOL>parent_reg_constrs = []<EOL>if reg_info:<EOL><INDENT>var_base_name, offset = reg_info<EOL>var_name_old = self._get_var_name(var_base_name, fresh=False)<EOL>var_name_new = self._get_var_name(var_base_name, fresh=True)<EOL>var_size = self._arch_regs_size[var_base_name]<EOL>ret_val_old = self.make_bitvec(var_size, var_name_old)<EOL>ret_val_new = self.make_bitvec(var_size, var_name_new)<EOL>ret_val = smtfunction.extract(ret_val_new, offset, operand.size)<EOL>if <NUM_LIT:0> < offset < var_size - <NUM_LIT:1>:<EOL><INDENT>lower_expr_1 = smtfunction.extract(ret_val_new, <NUM_LIT:0>, offset)<EOL>lower_expr_2 = smtfunction.extract(ret_val_old, <NUM_LIT:0>, offset)<EOL>parent_reg_constrs += [lower_expr_1 == lower_expr_2]<EOL>upper_expr_1 = smtfunction.extract(ret_val_new, offset + operand.size, var_size - offset - operand.size)<EOL>upper_expr_2 = smtfunction.extract(ret_val_old, offset + operand.size, var_size - offset - operand.size)<EOL>parent_reg_constrs += [upper_expr_1 == upper_expr_2]<EOL><DEDENT>elif offset == <NUM_LIT:0>:<EOL><INDENT>upper_expr_1 = smtfunction.extract(ret_val_new, offset + operand.size, var_size - offset - operand.size)<EOL>upper_expr_2 = smtfunction.extract(ret_val_old, offset + operand.size, var_size - offset - operand.size)<EOL>parent_reg_constrs += [upper_expr_1 == upper_expr_2]<EOL><DEDENT>elif offset == var_size-<NUM_LIT:1>:<EOL><INDENT>lower_expr_1 = smtfunction.extract(ret_val_new, <NUM_LIT:0>, offset)<EOL>lower_expr_2 = smtfunction.extract(ret_val_old, <NUM_LIT:0>, offset)<EOL>parent_reg_constrs += [lower_expr_1 == lower_expr_2]<EOL><DEDENT><DEDENT>else:<EOL><INDENT>var_name_new = self._get_var_name(operand.name, fresh=True)<EOL>ret_val = self.make_bitvec(operand.size, var_name_new)<EOL><DEDENT>return ret_val, parent_reg_constrs<EOL>
|
Translate destination register operand to SMT expr.
|
f3272:c0:m16
|
def _translate_add(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var, oprnd3.size) + smtfunction.zero_extend(op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var + op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var + op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an ADD instruction.
|
f3272:c0:m17
|
def _translate_sub(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var, oprnd3.size) - smtfunction.zero_extend(op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var - op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var - op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an SUB instruction.
|
f3272:c0:m18
|
def _translate_mul(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var, oprnd3.size) * smtfunction.zero_extend(op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var * op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var * op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an MUL instruction.
|
f3272:c0:m19
|
def _translate_div(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_zx = smtfunction.zero_extend(op1_var, oprnd3.size)<EOL>op2_var_zx = smtfunction.zero_extend(op2_var, oprnd3.size)<EOL>result = op1_var_zx.udiv(op2_var_zx)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var.udiv(op2_var), <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var.udiv(op2_var)<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an DIV instruction.
|
f3272:c0:m20
|
def _translate_mod(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_zx = smtfunction.zero_extend(op1_var, oprnd3.size)<EOL>op2_var_zx = smtfunction.zero_extend(op2_var, oprnd3.size)<EOL>result = op1_var_zx.umod(op2_var_zx)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var.umod(op2_var), <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var.umod(op2_var)<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an MOD instruction.
|
f3272:c0:m21
|
def _translate_bsh(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_zx = smtfunction.zero_extend(op1_var, oprnd3.size)<EOL>op2_var_zx = smtfunction.zero_extend(op2_var, oprnd3.size)<EOL>op2_var_neg_sx = smtfunction.sign_extend(-op2_var, oprnd3.size)<EOL>shr = smtfunction.extract(op1_var_zx >> op2_var_neg_sx, <NUM_LIT:0>, op3_var.size)<EOL>shl = smtfunction.extract(op1_var_zx << op2_var_zx, <NUM_LIT:0>, op3_var.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>shr = smtfunction.extract(op1_var >> -op2_var, <NUM_LIT:0>, op3_var.size)<EOL>shl = smtfunction.extract(op1_var << op2_var, <NUM_LIT:0>, op3_var.size)<EOL><DEDENT>else:<EOL><INDENT>shr = op1_var >> -op2_var<EOL>shl = op1_var << op2_var<EOL><DEDENT>result = smtfunction.ite(oprnd3.size, op2_var >= <NUM_LIT:0>, shl, shr)<EOL>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a BSH instruction.
|
f3272:c0:m22
|
def _translate_and(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var & op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var & op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var & op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a AND instruction.
|
f3272:c0:m23
|
def _translate_or(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var | op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var | op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var | op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a OR instruction.
|
f3272:c0:m24
|
def _translate_xor(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var ^ op2_var, oprnd3.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var ^ op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var ^ op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a AND instruction.
|
f3272:c0:m25
|
def _translate_ldm(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>assert oprnd1.size == self._address_size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>exprs = []<EOL>for i in reversed(range(<NUM_LIT:0>, oprnd3.size, <NUM_LIT:8>)):<EOL><INDENT>exprs += [self._mem_curr[op1_var + i // <NUM_LIT:8>] == smtfunction.extract(op3_var, i, <NUM_LIT:8>)]<EOL><DEDENT>return exprs + op3_var_constrs<EOL>
|
Return a formula representation of a LDM instruction.
|
f3272:c0:m26
|
def _translate_stm(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>assert oprnd3.size == self._address_size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op3_var = self._translate_src_oprnd(oprnd3)<EOL>for i in range(<NUM_LIT:0>, oprnd1.size, <NUM_LIT:8>):<EOL><INDENT>self._mem_curr[op3_var + i//<NUM_LIT:8>] = smtfunction.extract(op1_var, i, <NUM_LIT:8>)<EOL><DEDENT>self._mem_instance += <NUM_LIT:1><EOL>mem_old = self._mem_curr<EOL>mem_new = self.make_array(self._address_size, "<STR_LIT>".format(self._mem_instance))<EOL>self._mem_curr = mem_new<EOL>return [mem_new == mem_old]<EOL>
|
Return a formula representation of a STM instruction.
|
f3272:c0:m27
|
def _translate_str(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.zero_extend(op1_var, op3_var.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var, <NUM_LIT:0>, op3_var.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a STR instruction.
|
f3272:c0:m28
|
def _translate_bisz(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>result = smtfunction.ite(oprnd3.size, op1_var == <NUM_LIT>, smtsymbol.Constant(oprnd3.size, <NUM_LIT>),<EOL>smtsymbol.Constant(oprnd3.size, <NUM_LIT>))<EOL>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a BISZ instruction.
|
f3272:c0:m29
|
def _translate_jcc(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>return [op1_var != <NUM_LIT>]<EOL>
|
Return a formula representation of a JCC instruction.
|
f3272:c0:m30
|
def _translate_unkn(self, oprnd1, oprnd2, oprnd3):
|
raise Exception("<STR_LIT>")<EOL>
|
Return a formula representation of a UNKN instruction.
|
f3272:c0:m31
|
def _translate_undef(self, oprnd1, oprnd2, oprnd3):
|
raise Exception("<STR_LIT>")<EOL>
|
Return a formula representation of a UNDEF instruction.
|
f3272:c0:m32
|
def _translate_nop(self, oprnd1, oprnd2, oprnd3):
|
return []<EOL>
|
Return a formula representation of a NOP instruction.
|
f3272:c0:m33
|
def _translate_sext(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd3.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>result = smtfunction.sign_extend(op1_var, op3_var.size)<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>else:<EOL><INDENT>result = op1_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of a SEXT instruction.
|
f3272:c0:m34
|
def _translate_sdiv(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_sx = smtfunction.sign_extend(op1_var, oprnd3.size)<EOL>op2_var_sx = smtfunction.sign_extend(op2_var, oprnd3.size)<EOL>result = op1_var_sx // op2_var_sx<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var // op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var // op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an DIV instruction.
|
f3272:c0:m35
|
def _translate_smod(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_sx = smtfunction.sign_extend(op1_var, oprnd3.size)<EOL>op2_var_sx = smtfunction.sign_extend(op2_var, oprnd3.size)<EOL>result = op1_var_sx % op2_var_sx<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var % op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var % op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an MOD instruction.
|
f3272:c0:m36
|
def _translate_smul(self, oprnd1, oprnd2, oprnd3):
|
assert oprnd1.size and oprnd2.size and oprnd3.size<EOL>assert oprnd1.size == oprnd2.size<EOL>op1_var = self._translate_src_oprnd(oprnd1)<EOL>op2_var = self._translate_src_oprnd(oprnd2)<EOL>op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)<EOL>if oprnd3.size > oprnd1.size:<EOL><INDENT>op1_var_sx = smtfunction.sign_extend(op1_var, oprnd3.size)<EOL>op2_var_sx = smtfunction.sign_extend(op2_var, oprnd3.size)<EOL>result = op1_var_sx * op2_var_sx<EOL><DEDENT>elif oprnd3.size < oprnd1.size:<EOL><INDENT>result = smtfunction.extract(op1_var * op2_var, <NUM_LIT:0>, oprnd3.size)<EOL><DEDENT>else:<EOL><INDENT>result = op1_var * op2_var<EOL><DEDENT>return [op3_var == result] + op3_var_constrs<EOL>
|
Return a formula representation of an MUL instruction.
|
f3272:c0:m37
|
def parse_operand(string, location, tokens):
|
sizes = {<EOL>"<STR_LIT>": <NUM_LIT>,<EOL>"<STR_LIT>": <NUM_LIT>,<EOL>"<STR_LIT>": <NUM_LIT:64>,<EOL>"<STR_LIT>": <NUM_LIT>,<EOL>"<STR_LIT>": <NUM_LIT:32>,<EOL>"<STR_LIT>": <NUM_LIT:16>,<EOL>"<STR_LIT>": <NUM_LIT:8>,<EOL>"<STR_LIT>": <NUM_LIT:1>,<EOL>}<EOL>if "<STR_LIT>" in tokens:<EOL><INDENT>imm_str = "<STR_LIT>".join(tokens["<STR_LIT>"])<EOL>base = <NUM_LIT:16> if imm_str.startswith("<STR_LIT>") or imm_str.startswith("<STR_LIT>") else <NUM_LIT:10><EOL>imm = int(imm_str, base)<EOL>oprnd = ReilImmediateOperand(imm)<EOL><DEDENT>if "<STR_LIT>" in tokens:<EOL><INDENT>if tokens["<STR_LIT>"] in ["<STR_LIT:e>", "<STR_LIT>"]:<EOL><INDENT>oprnd = ReilEmptyOperand()<EOL>oprnd.size = <NUM_LIT:0><EOL><DEDENT>else:<EOL><INDENT>name = tokens["<STR_LIT>"]<EOL>oprnd = ReilRegisterOperand(name)<EOL><DEDENT><DEDENT>if "<STR_LIT:size>" in tokens:<EOL><INDENT>oprnd.size = int(sizes[tokens["<STR_LIT:size>"]])<EOL><DEDENT>return [oprnd]<EOL>
|
Parse instruction operand.
|
f3275:m0
|
def parse_instruction(string, location, tokens):
|
mnemonic_str = ReilMnemonic.from_string(tokens["<STR_LIT>"])<EOL>oprnd1 = tokens["<STR_LIT>"][<NUM_LIT:0>]<EOL>oprnd2 = tokens["<STR_LIT>"][<NUM_LIT:0>]<EOL>oprnd3 = tokens["<STR_LIT>"][<NUM_LIT:0>]<EOL>ins_builder = ReilBuilder()<EOL>return ins_builder.build(mnemonic_str, oprnd1, oprnd2, oprnd3)<EOL>
|
Parse instruction.
|
f3275:m1
|
def parse(self, instrs):
|
instrs_reil = []<EOL>try:<EOL><INDENT>for instr in instrs:<EOL><INDENT>instr_lower = instr.lower()<EOL>if instr_lower not in self._cache:<EOL><INDENT>self._cache[instr_lower] = instruction.parseString(<EOL>instr_lower)[<NUM_LIT:0>]<EOL><DEDENT>instrs_reil += [copy.deepcopy(self._cache[instr_lower])]<EOL><DEDENT><DEDENT>except:<EOL><INDENT>error_msg = "<STR_LIT>"<EOL>logger.error(error_msg, instr, exc_info=True)<EOL><DEDENT>return instrs_reil<EOL>
|
Parse an IR instruction.
|
f3275:c0:m1
|
@staticmethod<EOL><INDENT>def gen_add(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.ADD, src1, src2, dst)<EOL>
|
Return an ADD instruction.
|
f3276:c0:m0
|
@staticmethod<EOL><INDENT>def gen_sub(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.SUB, src1, src2, dst)<EOL>
|
Return a SUB instruction.
|
f3276:c0:m1
|
@staticmethod<EOL><INDENT>def gen_mul(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.MUL, src1, src2, dst)<EOL>
|
Return a MUL instruction.
|
f3276:c0:m2
|
@staticmethod<EOL><INDENT>def gen_div(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.DIV, src1, src2, dst)<EOL>
|
Return a DIV instruction.
|
f3276:c0:m3
|
@staticmethod<EOL><INDENT>def gen_mod(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.MOD, src1, src2, dst)<EOL>
|
Return a MOD instruction.
|
f3276:c0:m4
|
@staticmethod<EOL><INDENT>def gen_bsh(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.BSH, src1, src2, dst)<EOL>
|
Return a BSH instruction.
|
f3276:c0:m5
|
@staticmethod<EOL><INDENT>def gen_and(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.AND, src1, src2, dst)<EOL>
|
Return an AND instruction.
|
f3276:c0:m6
|
@staticmethod<EOL><INDENT>def gen_or(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.OR, src1, src2, dst)<EOL>
|
Return an OR instruction.
|
f3276:c0:m7
|
@staticmethod<EOL><INDENT>def gen_xor(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.XOR, src1, src2, dst)<EOL>
|
Return a XOR instruction.
|
f3276:c0:m8
|
@staticmethod<EOL><INDENT>def gen_ldm(src, dst):<DEDENT>
|
return ReilBuilder.build(ReilMnemonic.LDM, src, ReilEmptyOperand(), dst)<EOL>
|
Return a LDM instruction.
|
f3276:c0:m9
|
@staticmethod<EOL><INDENT>def gen_stm(src, dst):<DEDENT>
|
return ReilBuilder.build(ReilMnemonic.STM, src, ReilEmptyOperand(), dst)<EOL>
|
Return a STM instruction.
|
f3276:c0:m10
|
@staticmethod<EOL><INDENT>def gen_str(src, dst):<DEDENT>
|
return ReilBuilder.build(ReilMnemonic.STR, src, ReilEmptyOperand(), dst)<EOL>
|
Return a STR instruction.
|
f3276:c0:m11
|
@staticmethod<EOL><INDENT>def gen_bisz(src, dst):<DEDENT>
|
return ReilBuilder.build(ReilMnemonic.BISZ, src, ReilEmptyOperand(), dst)<EOL>
|
Return a BISZ instruction.
|
f3276:c0:m12
|
@staticmethod<EOL><INDENT>def gen_jcc(src, dst):<DEDENT>
|
return ReilBuilder.build(ReilMnemonic.JCC, src, ReilEmptyOperand(), dst)<EOL>
|
Return a JCC instruction.
|
f3276:c0:m13
|
@staticmethod<EOL><INDENT>def gen_unkn():<DEDENT>
|
empty_reg = ReilEmptyOperand()<EOL>return ReilBuilder.build(ReilMnemonic.UNKN, empty_reg, empty_reg, empty_reg)<EOL>
|
Return an UNKN instruction.
|
f3276:c0:m14
|
@staticmethod<EOL><INDENT>def gen_undef():<DEDENT>
|
empty_reg = ReilEmptyOperand()<EOL>return ReilBuilder.build(ReilMnemonic.UNDEF, empty_reg, empty_reg, empty_reg)<EOL>
|
Return an UNDEF instruction.
|
f3276:c0:m15
|
@staticmethod<EOL><INDENT>def gen_nop():<DEDENT>
|
empty_reg = ReilEmptyOperand()<EOL>return ReilBuilder.build(ReilMnemonic.NOP, empty_reg, empty_reg, empty_reg)<EOL>
|
Return a NOP instruction.
|
f3276:c0:m16
|
@staticmethod<EOL><INDENT>def gen_sext(src, dst):<DEDENT>
|
assert src.size <= dst.size<EOL>empty_reg = ReilEmptyOperand()<EOL>return ReilBuilder.build(ReilMnemonic.SEXT, src, empty_reg, dst)<EOL>
|
Return a SEXT instruction.
|
f3276:c0:m17
|
@staticmethod<EOL><INDENT>def gen_sdiv(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.SDIV, src1, src2, dst)<EOL>
|
Return a SDIV instruction.
|
f3276:c0:m18
|
@staticmethod<EOL><INDENT>def gen_smod(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.SMOD, src1, src2, dst)<EOL>
|
Return a SMOD instruction.
|
f3276:c0:m19
|
@staticmethod<EOL><INDENT>def gen_smul(src1, src2, dst):<DEDENT>
|
assert src1.size == src2.size<EOL>return ReilBuilder.build(ReilMnemonic.SMUL, src1, src2, dst)<EOL>
|
Return a SMUL instruction.
|
f3276:c0:m20
|
@staticmethod<EOL><INDENT>def build(mnemonic, oprnd1, oprnd2, oprnd3):<DEDENT>
|
ins = ReilInstruction()<EOL>ins.mnemonic = mnemonic<EOL>ins.operands = [oprnd1, oprnd2, oprnd3]<EOL>return ins<EOL>
|
Return the specified instruction.
|
f3276:c0:m21
|
def execute(self, container, start=None, end=None, registers=None):
|
if registers:<EOL><INDENT>self.__cpu.registers = dict(registers)<EOL><DEDENT>ip = start if start else container[<NUM_LIT:0>].address<EOL>while ip and ip != end:<EOL><INDENT>try:<EOL><INDENT>instr = container.fetch(ip)<EOL><DEDENT>except ReilContainerInvalidAddressError:<EOL><INDENT>logger.info("<STR_LIT>".format(ip >> <NUM_LIT:8>, ip & <NUM_LIT>))<EOL>raise ReilCpuInvalidAddressError()<EOL><DEDENT>next_ip = self.__execute_one(instr)<EOL>ip = next_ip if next_ip else container.get_next_address(ip)<EOL><DEDENT>return dict(self.__cpu.registers), self.__mem<EOL>
|
Execute instructions.
|
f3277:c0:m1
|
def execute_lite(self, instructions, context=None):
|
if context:<EOL><INDENT>self.__cpu.registers = dict(context)<EOL><DEDENT>for instr in instructions:<EOL><INDENT>self.__execute_one(instr)<EOL><DEDENT>return dict(self.__cpu.registers), self.__mem<EOL>
|
Execute a list of instructions. It does not support loops.
|
f3277:c0:m2
|
def reset(self):
|
self.__mem.reset()<EOL>self.__cpu.reset()<EOL>self.__tainter.reset()<EOL>self.__instr_handler_pre = None, None<EOL>self.__instr_handler_post = None, None<EOL>self.__set_default_handlers()<EOL>
|
Reset emulator. All registers and memory are reset.
|
f3277:c0:m5
|
@property<EOL><INDENT>def registers(self):<DEDENT>
|
return self.__cpu.registers<EOL>
|
Return registers.
|
f3277:c0:m25
|
@registers.setter<EOL><INDENT>def registers(self, value):<DEDENT>
|
self.__cpu.registers = value<EOL>
|
Return registers.
|
f3277:c0:m26
|
@property<EOL><INDENT>def memory(self):<DEDENT>
|
return self.__mem<EOL>
|
Return memory.
|
f3277:c0:m27
|
@property<EOL><INDENT>def cpu(self):<DEDENT>
|
return self.__cpu<EOL>
|
Return memory.
|
f3277:c0:m28
|
@property<EOL><INDENT>def read_registers(self):<DEDENT>
|
return self.__cpu.read_registers<EOL>
|
Return read (native) registers.
|
f3277:c0:m29
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.