signature
stringlengths 8
3.44k
| body
stringlengths 0
1.41M
| docstring
stringlengths 1
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stringlengths 5
17
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@property<EOL><INDENT>def written_registers(self):<DEDENT>
|
return self.__cpu.written_registers<EOL>
|
Return written (native) registers.
|
f3277:c0:m30
|
def read(self, address, size):
|
value = <NUM_LIT><EOL>for i in range(<NUM_LIT:0>, size):<EOL><INDENT>value |= self._read_byte(address + i) << (i * <NUM_LIT:8>)<EOL><DEDENT>return value<EOL>
|
Read arbitrary size content from memory.
|
f3278:c0:m2
|
def _read_byte(self, address):
|
<EOL>if address not in self._memory:<EOL><INDENT>self._memory[address] = random.randint(<NUM_LIT>, <NUM_LIT>)<EOL><DEDENT>return self._memory[address]<EOL>
|
Read a byte from memory.
|
f3278:c0:m3
|
def write(self, address, size, value):
|
for i in range(<NUM_LIT:0>, size):<EOL><INDENT>self.__write_byte(address + i, (value >> (i * <NUM_LIT:8>)) & <NUM_LIT>)<EOL><DEDENT>
|
Write arbitrary size content to memory.
|
f3278:c0:m4
|
def __write_byte(self, address, value):
|
self._memory[address] = value & <NUM_LIT><EOL>
|
Write byte in memory.
|
f3278:c0:m5
|
def read_inverse(self, value, size):
|
addr_candidates = [addr for addr, val in self._memory.items() if val == (value & <NUM_LIT>)]<EOL>addr_matches = []<EOL>for addr in addr_candidates:<EOL><INDENT>match = True<EOL>for i in range(<NUM_LIT:0>, size):<EOL><INDENT>byte_curr = (value >> (i * <NUM_LIT:8>)) & <NUM_LIT><EOL>try:<EOL><INDENT>match = self._memory[addr + i] == byte_curr<EOL><DEDENT>except KeyError:<EOL><INDENT>match = False<EOL><DEDENT>if not match:<EOL><INDENT>break<EOL><DEDENT><DEDENT>if match:<EOL><INDENT>addr_matches += [addr]<EOL><DEDENT><DEDENT>return addr_matches<EOL>
|
Return a list of memory addresses that contain the specified
value.
|
f3278:c1:m1
|
def try_read(self, address, size):
|
value = <NUM_LIT><EOL>for i in range(<NUM_LIT:0>, size):<EOL><INDENT>addr = address + i<EOL>if addr in self._memory:<EOL><INDENT>value |= self._read_byte(addr) << (i * <NUM_LIT:8>)<EOL><DEDENT>else:<EOL><INDENT>return False, None<EOL><DEDENT><DEDENT>return True, value<EOL>
|
Try to read memory content at specified address.
If any location was not written before, it returns a tuple
(False, None). Otherwise, it returns (True, memory content).
|
f3278:c1:m2
|
def try_read_prev(self, address, size):
|
value = <NUM_LIT><EOL>for i in range(<NUM_LIT:0>, size):<EOL><INDENT>addr = address + i<EOL>if addr in self.__memory_prev:<EOL><INDENT>_, val_byte = self.__try_read_byte_prev(addr)<EOL>value |= val_byte << (i * <NUM_LIT:8>)<EOL><DEDENT>else:<EOL><INDENT>return False, None<EOL><DEDENT><DEDENT>return True, value<EOL>
|
Try to read previous memory content at specified address.
If any location was not written before, it returns a tuple
(False, None). Otherwise, it returns (True, memory content).
|
f3278:c1:m3
|
def __try_read_byte_prev(self, address):
|
<EOL>if address not in self.__memory_prev:<EOL><INDENT>return False, None<EOL><DEDENT>return True, self.__memory_prev[address]<EOL>
|
Read previous value for memory location.
Return a tuple (True, Byte) in case of successful read,
(False, None) otherwise.
|
f3278:c1:m4
|
def write(self, address, size, value):
|
for i in range(<NUM_LIT:0>, size):<EOL><INDENT>self.__write_byte(address + i, (value >> (i * <NUM_LIT:8>)) & <NUM_LIT>)<EOL><DEDENT>self.__write_count += <NUM_LIT:1><EOL>
|
Write arbitrary size content to memory.
|
f3278:c1:m5
|
def __write_byte(self, address, value):
|
<EOL>if address in self._memory:<EOL><INDENT>self.__memory_prev[address] = self._memory[address]<EOL><DEDENT>self._memory[address] = value & <NUM_LIT><EOL>
|
Write byte in memory.
|
f3278:c1:m6
|
def get_addresses(self):
|
return list(self._memory.keys())<EOL>
|
Get accessed addresses.
|
f3278:c1:m8
|
def get_write_count(self):
|
return self.__write_count<EOL>
|
Get number of write operations performed on the memory.
|
f3278:c1:m9
|
def __taint_load(self, instr):
|
<EOL>op0_val = self.__emu.read_operand(instr.operands[<NUM_LIT:0>])<EOL>op0_taint = self.get_memory_taint(op0_val, instr.operands[<NUM_LIT:2>].size // <NUM_LIT:8>)<EOL>self.set_operand_taint(instr.operands[<NUM_LIT:2>], op0_taint)<EOL>
|
Taint LDM instruction.
|
f3280:c0:m14
|
def __taint_store(self, instr):
|
<EOL>op2_val = self.__emu.read_operand(instr.operands[<NUM_LIT:2>])<EOL>op0_size = instr.operands[<NUM_LIT:0>].size<EOL>op0_taint = self.get_operand_taint(instr.operands[<NUM_LIT:0>])<EOL>self.set_memory_taint(op2_val, op0_size // <NUM_LIT:8>, op0_taint)<EOL>
|
Taint STM instruction.
|
f3280:c0:m15
|
def __taint_move(self, instr):
|
<EOL>op0_taint = self.get_operand_taint(instr.operands[<NUM_LIT:0>])<EOL>self.set_operand_taint(instr.operands[<NUM_LIT:2>], op0_taint)<EOL>
|
Taint registers move instruction.
|
f3280:c0:m16
|
def __taint_undef(self, instr):
|
<EOL>self.set_operand_taint(instr.operands[<NUM_LIT:2>], False)<EOL>
|
Taint UNDEF instruction.
|
f3280:c0:m17
|
def __taint_nothing(self, instr):
|
pass<EOL>
|
Taint nothing.
|
f3280:c0:m18
|
def __execute_bsh(self, instr):
|
op0_val = self.read_operand(instr.operands[<NUM_LIT:0>])<EOL>op1_val = self.read_operand(instr.operands[<NUM_LIT:1>])<EOL>op1_size = instr.operands[<NUM_LIT:1>].size<EOL>if extract_sign_bit(op1_val, op1_size) == <NUM_LIT:0>:<EOL><INDENT>op2_val = op0_val << op1_val<EOL><DEDENT>else:<EOL><INDENT>op2_val = op0_val >> twos_complement(op1_val, op1_size)<EOL><DEDENT>self.write_operand(instr.operands[<NUM_LIT:2>], op2_val)<EOL>return None<EOL>
|
Execute BSH instruction.
|
f3281:c3:m21
|
def __execute_ldm(self, instr):
|
assert instr.operands[<NUM_LIT:0>].size == self.__mem.address_size<EOL>assert instr.operands[<NUM_LIT:2>].size in [<NUM_LIT:8>, <NUM_LIT:16>, <NUM_LIT:32>, <NUM_LIT:64>, <NUM_LIT>, <NUM_LIT>]<EOL>op0_val = self.read_operand(instr.operands[<NUM_LIT:0>])<EOL>op2_val = self.read_memory(op0_val, instr.operands[<NUM_LIT:2>].size // <NUM_LIT:8>)<EOL>self.write_operand(instr.operands[<NUM_LIT:2>], op2_val)<EOL>return None<EOL>
|
Execute LDM instruction.
|
f3281:c3:m26
|
def __execute_stm(self, instr):
|
assert instr.operands[<NUM_LIT:0>].size in [<NUM_LIT:8>, <NUM_LIT:16>, <NUM_LIT:32>, <NUM_LIT:64>, <NUM_LIT>, <NUM_LIT>]<EOL>assert instr.operands[<NUM_LIT:2>].size == self.__mem.address_size<EOL>op0_val = self.read_operand(instr.operands[<NUM_LIT:0>]) <EOL>op2_val = self.read_operand(instr.operands[<NUM_LIT:2>]) <EOL>op0_size = instr.operands[<NUM_LIT:0>].size<EOL>self.write_memory(op2_val, op0_size // <NUM_LIT:8>, op0_val)<EOL>return None<EOL>
|
Execute STM instruction.
|
f3281:c3:m27
|
def __execute_str(self, instr):
|
op0_val = self.read_operand(instr.operands[<NUM_LIT:0>])<EOL>self.write_operand(instr.operands[<NUM_LIT:2>], op0_val)<EOL>return None<EOL>
|
Execute STR instruction.
|
f3281:c3:m28
|
def __execute_bisz(self, instr):
|
op0_val = self.read_operand(instr.operands[<NUM_LIT:0>])<EOL>op2_val = <NUM_LIT:1> if op0_val == <NUM_LIT:0> else <NUM_LIT:0><EOL>self.write_operand(instr.operands[<NUM_LIT:2>], op2_val)<EOL>return None<EOL>
|
Execute BISZ instruction.
|
f3281:c3:m29
|
def __execute_jcc(self, instr):
|
op0_val = self.read_operand(instr.operands[<NUM_LIT:0>]) <EOL>op2_val = self.read_operand(instr.operands[<NUM_LIT:2>]) <EOL>return op2_val if op0_val != <NUM_LIT:0> else None<EOL>
|
Execute JCC instruction.
|
f3281:c3:m30
|
def __execute_undef(self, instr):
|
op2_val = random.randint(<NUM_LIT:0>, instr.operands[<NUM_LIT:2>].size)<EOL>self.write_operand(instr.operands[<NUM_LIT:2>], op2_val)<EOL>return None<EOL>
|
Execute UNDEF instruction.
|
f3281:c3:m31
|
def __execute_unkn(self, instr):
|
raise ReilCpuInvalidInstruction()<EOL>
|
Execute UNKN instruction.
|
f3281:c3:m32
|
def __execute_skip(self, instr):
|
return None<EOL>
|
Skip instruction.
|
f3281:c3:m33
|
def __execute_sext(self, instr):
|
op0_size = instr.operands[<NUM_LIT:0>].size<EOL>op2_size = instr.operands[<NUM_LIT:2>].size<EOL>op0_val = self.read_operand(instr.operands[<NUM_LIT:0>])<EOL>op0_msb = extract_sign_bit(op0_val, op0_size)<EOL>op2_mask = (<NUM_LIT:2>**op2_size-<NUM_LIT:1>) & ~(<NUM_LIT:2>**op0_size-<NUM_LIT:1>) if op0_msb == <NUM_LIT:1> else <NUM_LIT><EOL>op2_val = op0_val | op2_mask<EOL>self.write_operand(instr.operands[<NUM_LIT:2>], op2_val)<EOL>return None<EOL>
|
Execute SEXT instruction.
|
f3281:c3:m34
|
@staticmethod<EOL><INDENT>def to_string(mnemonic):<DEDENT>
|
strings = {<EOL>ReilMnemonic.ADD: "<STR_LIT>",<EOL>ReilMnemonic.SUB: "<STR_LIT>",<EOL>ReilMnemonic.MUL: "<STR_LIT>",<EOL>ReilMnemonic.DIV: "<STR_LIT>",<EOL>ReilMnemonic.MOD: "<STR_LIT>",<EOL>ReilMnemonic.BSH: "<STR_LIT>",<EOL>ReilMnemonic.AND: "<STR_LIT>",<EOL>ReilMnemonic.OR: "<STR_LIT>",<EOL>ReilMnemonic.XOR: "<STR_LIT>",<EOL>ReilMnemonic.LDM: "<STR_LIT>",<EOL>ReilMnemonic.STM: "<STR_LIT>",<EOL>ReilMnemonic.STR: "<STR_LIT:str>",<EOL>ReilMnemonic.BISZ: "<STR_LIT>",<EOL>ReilMnemonic.JCC: "<STR_LIT>",<EOL>ReilMnemonic.UNKN: "<STR_LIT>",<EOL>ReilMnemonic.UNDEF: "<STR_LIT>",<EOL>ReilMnemonic.NOP: "<STR_LIT>",<EOL>ReilMnemonic.SEXT: "<STR_LIT>",<EOL>ReilMnemonic.SDIV: "<STR_LIT>",<EOL>ReilMnemonic.SMOD: "<STR_LIT>",<EOL>ReilMnemonic.SMUL: "<STR_LIT>",<EOL>}<EOL>return strings[mnemonic]<EOL>
|
Return the string representation of the given mnemonic.
|
f3285:c0:m0
|
@staticmethod<EOL><INDENT>def from_string(string):<DEDENT>
|
mnemonics = {<EOL>"<STR_LIT>": ReilMnemonic.ADD,<EOL>"<STR_LIT>": ReilMnemonic.SUB,<EOL>"<STR_LIT>": ReilMnemonic.MUL,<EOL>"<STR_LIT>": ReilMnemonic.DIV,<EOL>"<STR_LIT>": ReilMnemonic.MOD,<EOL>"<STR_LIT>": ReilMnemonic.BSH,<EOL>"<STR_LIT>": ReilMnemonic.AND,<EOL>"<STR_LIT>": ReilMnemonic.OR,<EOL>"<STR_LIT>": ReilMnemonic.XOR,<EOL>"<STR_LIT>": ReilMnemonic.LDM,<EOL>"<STR_LIT>": ReilMnemonic.STM,<EOL>"<STR_LIT:str>": ReilMnemonic.STR,<EOL>"<STR_LIT>": ReilMnemonic.BISZ,<EOL>"<STR_LIT>": ReilMnemonic.JCC,<EOL>"<STR_LIT>": ReilMnemonic.UNKN,<EOL>"<STR_LIT>": ReilMnemonic.UNDEF,<EOL>"<STR_LIT>": ReilMnemonic.NOP,<EOL>"<STR_LIT>": ReilMnemonic.SEXT,<EOL>"<STR_LIT>": ReilMnemonic.SDIV,<EOL>"<STR_LIT>": ReilMnemonic.SMOD,<EOL>"<STR_LIT>": ReilMnemonic.SMUL,<EOL>}<EOL>return mnemonics[string]<EOL>
|
Return the mnemonic represented by the given string.
|
f3285:c0:m1
|
@property<EOL><INDENT>def mnemonic(self):<DEDENT>
|
return self._mnemonic<EOL>
|
Get instruction mnemonic.
|
f3285:c1:m1
|
@property<EOL><INDENT>def mnemonic_str(self):<DEDENT>
|
return ReilMnemonic.to_string(self._mnemonic)<EOL>
|
Get instruction mnemonic as string.
|
f3285:c1:m2
|
@mnemonic.setter<EOL><INDENT>def mnemonic(self, value):<DEDENT>
|
if value not in REIL_MNEMONICS:<EOL><INDENT>raise Exception("<STR_LIT>" % str(value))<EOL><DEDENT>self._mnemonic = value<EOL>
|
Set instruction mnemonic.
|
f3285:c1:m3
|
@property<EOL><INDENT>def operands(self):<DEDENT>
|
return self._operands<EOL>
|
Get instruction operands.
|
f3285:c1:m4
|
@operands.setter<EOL><INDENT>def operands(self, value):<DEDENT>
|
if len(value) != <NUM_LIT:3>:<EOL><INDENT>raise Exception("<STR_LIT>" % str(value))<EOL><DEDENT>self._operands = value<EOL>
|
Set instruction operands.
|
f3285:c1:m5
|
@property<EOL><INDENT>def address(self):<DEDENT>
|
return self._address<EOL>
|
Get instruction address.
|
f3285:c1:m6
|
@address.setter<EOL><INDENT>def address(self, value):<DEDENT>
|
self._address = value<EOL>
|
Set instruction address.
|
f3285:c1:m7
|
@property<EOL><INDENT>def comment(self):<DEDENT>
|
return self._comment<EOL>
|
Get instruction comment.
|
f3285:c1:m8
|
@comment.setter<EOL><INDENT>def comment(self, value):<DEDENT>
|
self._comment = value<EOL>
|
Set instruction comment.
|
f3285:c1:m9
|
@property<EOL><INDENT>def size(self):<DEDENT>
|
return self._size<EOL>
|
Get operand size.
|
f3285:c2:m1
|
@size.setter<EOL><INDENT>def size(self, value):<DEDENT>
|
self._size = value<EOL>
|
Set operand size.
|
f3285:c2:m2
|
@property<EOL><INDENT>def immediate(self):<DEDENT>
|
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._immediate & <NUM_LIT:2>**self._size-<NUM_LIT:1><EOL>
|
Get immediate.
|
f3285:c3:m1
|
@property<EOL><INDENT>def name(self):<DEDENT>
|
return self._name<EOL>
|
Get IR register operand name.
|
f3285:c4:m1
|
@property<EOL><INDENT>def name(self):<DEDENT>
|
return self._name<EOL>
|
Get label name.
|
f3285:c6:m1
|
@property<EOL><INDENT>def ea_start(self):<DEDENT>
|
return self._section_text_start<EOL>
|
Get start address of section .text.
|
f3286:c3:m1
|
@property<EOL><INDENT>def ea_end(self):<DEDENT>
|
return self._section_text_end<EOL>
|
Get end address of section .text (last addressable byte
address).
|
f3286:c3:m2
|
@property<EOL><INDENT>def architecture(self):<DEDENT>
|
return self._arch<EOL>
|
Get architecture name.
|
f3286:c3:m3
|
@property<EOL><INDENT>def architecture_mode(self):<DEDENT>
|
return self._arch_mode<EOL>
|
Get architecture mode name.
|
f3286:c3:m4
|
@property<EOL><INDENT>def filename(self):<DEDENT>
|
return self._filename<EOL>
|
Get file name.
|
f3286:c3:m5
|
@property<EOL><INDENT>def file_format(self):<DEDENT>
|
raise NotImplementedError()<EOL>
|
Get file format.
|
f3286:c3:m6
|
@property<EOL><INDENT>def text_section(self):<DEDENT>
|
return self._section_text_memory<EOL>
|
Get section .text.
|
f3286:c3:m7
|
@property<EOL><INDENT>def data_section(self):<DEDENT>
|
return self._section_data_memory<EOL>
|
Get section .data.
|
f3286:c3:m8
|
@property<EOL><INDENT>def entry_point(self):<DEDENT>
|
return self._entry_point<EOL>
|
Get entry point.
|
f3286:c3:m9
|
@staticmethod<EOL><INDENT>def _extract_section(sect_req, elffile, mem=None):<DEDENT>
|
for nseg, section in enumerate(elffile.iter_sections()):<EOL><INDENT>request = sect_req.get(section.name, None)<EOL>if request:<EOL><INDENT>request.set_found(True)<EOL>request.set_sect_properties(section.header.sh_addr,<EOL>section.header.sh_size)<EOL>if mem:<EOL><INDENT>mem.add_vma(section.header.sh_addr, section.data())<EOL><DEDENT>else:<EOL><INDENT>request.memory.add_vma(section.header.sh_addr, section.data())<EOL><DEDENT><DEDENT><DEDENT>
|
:sect_req dictionary of section names as strings and SectionRequest objects
:mem if mem is not null, it serves as an accumulator rather than using the memory
in SectionRequests
:returns nothing
|
f3286:c3:m11
|
def get_init(self):
|
suffix = self._separator + "<STR_LIT:%s>" % str(self._counter_init)<EOL>return self._base_name + suffix<EOL>
|
Return initial name.
|
f3287:c0:m1
|
def get_current(self):
|
suffix = self._separator + "<STR_LIT:%s>" % str(self._counter_curr)<EOL>return self._base_name + suffix<EOL>
|
Return current name.
|
f3287:c0:m2
|
def get_next(self):
|
self._counter_curr += <NUM_LIT:1><EOL>suffix = self._separator + "<STR_LIT:%s>" % str(self._counter_curr)<EOL>return self._base_name + suffix<EOL>
|
Return next name.
|
f3287:c0:m3
|
def reset(self):
|
self._counter_curr = self._counter_init<EOL>
|
Restart name counter.
|
f3287:c0:m4
|
def classify(self, gadget):
|
typed_gadgets = []<EOL>for g_type, g_classifier in self._classifiers.items():<EOL><INDENT>try:<EOL><INDENT>typed_gadgets += self._classify(gadget, g_classifier, g_type, self._emu_iters)<EOL><DEDENT>except:<EOL><INDENT>import traceback<EOL>print("<STR_LIT>")<EOL>print(gadget)<EOL>print("<STR_LIT>")<EOL>print(traceback.format_exc())<EOL><DEDENT><DEDENT>return sorted(typed_gadgets, key=lambda g: str(g))<EOL>
|
Classify gadgets.
|
f3291:c0:m1
|
def _classify_no_operation(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
<EOL>matches = []<EOL>regs_changed = any(regs_init[r] != regs_fini[r] for r in regs_init)<EOL>flags_changed = False<EOL>mem_changed = mem_fini.get_write_count() != <NUM_LIT:0><EOL>if not regs_changed and not flags_changed and not mem_changed:<EOL><INDENT>matches.append({<EOL>"<STR_LIT>": "<STR_LIT>",<EOL>})<EOL><DEDENT>return matches<EOL>
|
Classify no-operation gadgets.
|
f3291:c0:m2
|
def _classify_jump(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
<EOL>matches = []<EOL>return matches<EOL>
|
Classify jump gadgets.
|
f3291:c0:m3
|
def _classify_move_register(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>regs_init_inv = self._invert_dictionary(regs_init)<EOL>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs:<EOL><INDENT>continue<EOL><DEDENT>for src_reg in regs_init_inv.get(dst_val, []):<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_reg] != self._arch_regs_size[dst_reg]:<EOL><INDENT>continue<EOL><DEDENT>if src_reg == dst_reg:<EOL><INDENT>continue<EOL><DEDENT>if regs_init[dst_reg] == regs_init[src_reg]:<EOL><INDENT>continue<EOL><DEDENT>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [src_reg_ir],<EOL>"<STR_LIT>": [dst_reg_ir]<EOL>})<EOL><DEDENT><DEDENT>return matches<EOL>
|
Classify move-register gadgets.
|
f3291:c0:m4
|
def _classify_load_constant(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs:<EOL><INDENT>continue<EOL><DEDENT>if dst_val == regs_init[dst_reg]:<EOL><INDENT>continue<EOL><DEDENT>dst_val_ir = ReilImmediateOperand(dst_val, self._arch_regs_size[dst_reg])<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [dst_val_ir],<EOL>"<STR_LIT>": [dst_reg_ir]<EOL>})<EOL><DEDENT>return matches<EOL>
|
Classify load-constant gadgets.
|
f3291:c0:m5
|
def _classify_arithmetic(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>op_restrictions = {<EOL>"<STR_LIT:+>": lambda x, y: False,<EOL>"<STR_LIT:->": lambda x, y: x == y,<EOL>"<STR_LIT:|>": lambda x, y: x == y,<EOL>"<STR_LIT:&>": lambda x, y: x == y,<EOL>"<STR_LIT>": lambda x, y: x == y,<EOL>}<EOL>for op_name, op_fn in self._binary_ops.items():<EOL><INDENT>for src_1_reg, src_1_val in regs_init.items():<EOL><INDENT>if src_1_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>for src_2_reg, src_2_val in regs_init.items():<EOL><INDENT>if src_2_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_1_reg] != self._arch_regs_size[src_2_reg] orself._arch_regs_size[src_1_reg] != self._arch_regs_size[dst_reg]:<EOL><INDENT>continue<EOL><DEDENT>if op_restrictions[op_name](src_1_reg, src_2_reg):<EOL><INDENT>continue<EOL><DEDENT>size = self._arch_regs_size[src_1_reg]<EOL>if dst_val == op_fn(src_1_val, src_2_val) & (<NUM_LIT:2>**size - <NUM_LIT:1>):<EOL><INDENT>src = sorted([src_1_reg, src_2_reg])<EOL>src_ir = [<EOL>ReilRegisterOperand(src[<NUM_LIT:0>], self._arch_regs_size[src[<NUM_LIT:0>]]),<EOL>ReilRegisterOperand(src[<NUM_LIT:1>], self._arch_regs_size[src[<NUM_LIT:1>]])<EOL>]<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": src_ir,<EOL>"<STR_LIT>": [dst_reg_ir],<EOL>"<STR_LIT>": op_name<EOL>})<EOL><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT>return matches<EOL>
|
Classify binary-operation gadgets.
|
f3291:c0:m6
|
def _classify_load_memory(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>regs_init_inv = self._invert_dictionary(regs_init)<EOL>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs:<EOL><INDENT>continue<EOL><DEDENT>dst_size = self._arch_regs_size[dst_reg]<EOL>for src_addr in mem_fini.read_inverse(dst_val, dst_size // <NUM_LIT:8>):<EOL><INDENT>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_reg] != self._address_size:<EOL><INDENT>continue<EOL><DEDENT>offset = (src_addr - src_val) & (<NUM_LIT:2>**self._address_size - <NUM_LIT:1>)<EOL>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>src_off_ir = ReilImmediateOperand(offset, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [src_reg_ir, src_off_ir],<EOL>"<STR_LIT>": [dst_reg_ir]<EOL>})<EOL><DEDENT><DEDENT><DEDENT>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs:<EOL><INDENT>continue<EOL><DEDENT>dst_size = self._arch_regs_size[dst_reg]<EOL>for src_addr in mem_fini.read_inverse(dst_val, dst_size // <NUM_LIT:8>):<EOL><INDENT>src_reg_ir = ReilEmptyOperand()<EOL>src_off_ir = ReilImmediateOperand(src_addr, self._address_size)<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [src_reg_ir, src_off_ir],<EOL>"<STR_LIT>": [dst_reg_ir]<EOL>})<EOL><DEDENT><DEDENT>return matches<EOL>
|
Classify load-memory gadgets.
|
f3291:c0:m7
|
def _classify_store_memory(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>regs_init_inv = self._invert_dictionary(regs_init)<EOL>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>src_size = self._arch_regs_size[src_reg]<EOL>for addr in mem_fini.read_inverse(src_val, src_size // <NUM_LIT:8>):<EOL><INDENT>for dst_reg, dst_val in regs_init.items():<EOL><INDENT>if dst_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[dst_reg] != self._address_size:<EOL><INDENT>continue<EOL><DEDENT>offset = (addr - dst_val) & (<NUM_LIT:2>**self._address_size - <NUM_LIT:1>)<EOL>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>dst_off_ir = ReilImmediateOperand(offset, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [src_reg_ir],<EOL>"<STR_LIT>": [dst_reg_ir, dst_off_ir]<EOL>})<EOL><DEDENT><DEDENT><DEDENT>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>src_size = self._arch_regs_size[src_reg]<EOL>for addr in mem_fini.read_inverse(src_val, src_size // <NUM_LIT:8>):<EOL><INDENT>offset = addr & (<NUM_LIT:2>**self._address_size - <NUM_LIT:1>)<EOL>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilEmptyOperand()<EOL>dst_off_ir = ReilImmediateOperand(offset, self._address_size)<EOL>matches.append({<EOL>"<STR_LIT:src>": [src_reg_ir],<EOL>"<STR_LIT>": [dst_reg_ir, dst_off_ir]<EOL>})<EOL><DEDENT><DEDENT>return matches<EOL>
|
Classify store-memory gadgets.
|
f3291:c0:m8
|
def _classify_arithmetic_load(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>for op_name, op_fn in self._binary_ops.items():<EOL><INDENT>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs or dst_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>dst_size = self._arch_regs_size[dst_reg]<EOL>for addr in mem_fini.get_addresses():<EOL><INDENT>success, val = mem_fini.try_read(addr, dst_size // <NUM_LIT:8>)<EOL>if success and dst_val == op_fn(regs_init[dst_reg], val) & (<NUM_LIT:2>**dst_size - <NUM_LIT:1>):<EOL><INDENT>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_reg] != self._address_size:<EOL><INDENT>continue<EOL><DEDENT>offset = (addr - src_val) & (<NUM_LIT:2>**self._address_size - <NUM_LIT:1>)<EOL>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>src_off_ir = ReilImmediateOperand(offset, self._address_size)<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [dst_reg_ir, src_reg_ir, src_off_ir],<EOL>"<STR_LIT>": [dst_reg_ir],<EOL>"<STR_LIT>": op_name<EOL>})<EOL><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT>for op_name, op_fn in self._binary_ops.items():<EOL><INDENT>for dst_reg, dst_val in regs_fini.items():<EOL><INDENT>if dst_reg not in written_regs or dst_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>dst_size = self._arch_regs_size[dst_reg]<EOL>for addr in mem_fini.get_addresses():<EOL><INDENT>success, val = mem_fini.try_read(addr, dst_size // <NUM_LIT:8>)<EOL>if success and dst_val == op_fn(regs_init[dst_reg], val) & (<NUM_LIT:2>**dst_size - <NUM_LIT:1>):<EOL><INDENT>src_reg_ir = ReilEmptyOperand()<EOL>src_off_ir = ReilImmediateOperand(addr, self._address_size)<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>matches.append({<EOL>"<STR_LIT:src>": [dst_reg_ir, src_reg_ir, src_off_ir],<EOL>"<STR_LIT>": [dst_reg_ir],<EOL>"<STR_LIT>": op_name<EOL>})<EOL><DEDENT><DEDENT><DEDENT><DEDENT>return matches<EOL>
|
Classify arithmetic-load gadgets.
|
f3291:c0:m9
|
def _classify_arithmetic_store(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
|
matches = []<EOL>for op_name, op_fn in self._binary_ops.items():<EOL><INDENT>for size in [<NUM_LIT:8>, <NUM_LIT:16>, <NUM_LIT:32>, <NUM_LIT:64>]:<EOL><INDENT>for addr in mem_fini.get_addresses():<EOL><INDENT>success_read_curr, val_curr = mem_fini.try_read(addr, size // <NUM_LIT:8>)<EOL>success_read_prev, val_prev = mem_fini.try_read_prev(addr, size // <NUM_LIT:8>)<EOL>if success_read_curr and success_read_prev:<EOL><INDENT>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_reg] != size:<EOL><INDENT>continue<EOL><DEDENT>if val_curr == op_fn(src_val, val_prev) & (<NUM_LIT:2>**size - <NUM_LIT:1>):<EOL><INDENT>for dst_reg, dst_val in regs_init.items():<EOL><INDENT>if dst_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[dst_reg] != self._address_size:<EOL><INDENT>continue<EOL><DEDENT>offset = (addr - dst_val) & (<NUM_LIT:2>**self._address_size - <NUM_LIT:1>)<EOL>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])<EOL>dst_off_ir = ReilImmediateOperand(offset, self._address_size)<EOL>matches.append({<EOL>"<STR_LIT:src>": [dst_reg_ir, dst_off_ir, src_reg_ir],<EOL>"<STR_LIT>": [dst_reg_ir, dst_off_ir],<EOL>"<STR_LIT>": op_name<EOL>})<EOL><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT>for op_name, op_fn in self._binary_ops.items():<EOL><INDENT>for size in [<NUM_LIT:8>, <NUM_LIT:16>, <NUM_LIT:32>, <NUM_LIT:64>]:<EOL><INDENT>for addr in mem_fini.get_addresses():<EOL><INDENT>success_read_curr, val_curr = mem_fini.try_read(addr, size // <NUM_LIT:8>)<EOL>success_read_prev, val_prev = mem_fini.try_read_prev(addr, size // <NUM_LIT:8>)<EOL>if success_read_curr and success_read_prev:<EOL><INDENT>for src_reg, src_val in regs_init.items():<EOL><INDENT>if src_reg not in read_regs:<EOL><INDENT>continue<EOL><DEDENT>if self._arch_regs_size[src_reg] != size:<EOL><INDENT>continue<EOL><DEDENT>if val_curr == op_fn(src_val, val_prev) & (<NUM_LIT:2>**size - <NUM_LIT:1>):<EOL><INDENT>src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])<EOL>dst_reg_ir = ReilEmptyOperand()<EOL>dst_off_ir = ReilImmediateOperand(addr, self._address_size)<EOL>matches.append({<EOL>"<STR_LIT:src>": [dst_reg_ir, dst_off_ir, src_reg_ir],<EOL>"<STR_LIT>": [dst_reg_ir, dst_off_ir],<EOL>"<STR_LIT>": op_name<EOL>})<EOL><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT><DEDENT>return matches<EOL>
|
Classify arithmetic-store gadgets.
|
f3291:c0:m10
|
def _classify(self, gadget, classifier, gadget_type, iters):
|
<EOL>instrs = [ir_instr for asm_instr in gadget.instrs for ir_instr in asm_instr.ir_instrs]<EOL>results = []<EOL>for _ in range(iters):<EOL><INDENT>self._ir_emulator.reset()<EOL>regs_initial = self._init_regs_random()<EOL>try:<EOL><INDENT>regs_final, mem_final = self._ir_emulator.execute_lite(<EOL>instrs,<EOL>regs_initial<EOL>)<EOL><DEDENT>except:<EOL><INDENT>results += [([], [])]<EOL>continue<EOL><DEDENT>regs_initial_full = self._compute_full_context(regs_initial)<EOL>regs_final_full = self._compute_full_context(regs_final)<EOL>regs_written = self._ir_emulator.written_registers<EOL>regs_read = self._ir_emulator.read_registers<EOL>mod_regs = self._compute_mod_regs(<EOL>regs_initial_full,<EOL>regs_final_full<EOL>)<EOL>matches = classifier(<EOL>regs_initial_full,<EOL>regs_final_full,<EOL>mem_final,<EOL>regs_written,<EOL>regs_read<EOL>)<EOL>results += [(matches, mod_regs)]<EOL><DEDENT>candidates, mod_regs = self._analyze_execution_results(results)<EOL>classified = self._create_typed_gadgets(<EOL>gadget,<EOL>candidates,<EOL>mod_regs,<EOL>gadget_type<EOL>)<EOL>return classified<EOL>
|
Classify gadgets.
|
f3291:c0:m11
|
def _init_regs_random(self):
|
<EOL>values = set()<EOL>while len(values) != len(self._arch_regs_parent):<EOL><INDENT>values.add(random.randint(<NUM_LIT:0>, <NUM_LIT:2>**self._arch_info.operand_size - <NUM_LIT:1>))<EOL><DEDENT>values = list(values)<EOL>regs = {}<EOL>for idx, reg in enumerate(self._arch_regs_parent):<EOL><INDENT>regs[reg] = values[idx] & (<NUM_LIT:2>**self._arch_regs_size[reg] - <NUM_LIT:1>)<EOL><DEDENT>return regs<EOL>
|
Initialize register with random values.
|
f3291:c0:m14
|
def _compute_mod_regs(self, regs_init, regs_fini):
|
assert regs_init.keys() == regs_fini.keys()<EOL>modified_regs = []<EOL>for reg in regs_init:<EOL><INDENT>if regs_init[reg] != regs_fini[reg]:<EOL><INDENT>modified_regs.append(reg)<EOL><DEDENT><DEDENT>return modified_regs<EOL>
|
Compute modified registers.
|
f3291:c0:m15
|
def _invert_dictionary(self, d):
|
inv_dict = {}<EOL>for k, v in d.items():<EOL><INDENT>inv_dict[v] = inv_dict.get(v, [])<EOL>inv_dict[v] += [k]<EOL><DEDENT>return inv_dict<EOL>
|
Invert a dictionary.
|
f3291:c0:m16
|
def _print_memory(self, memory):
|
for addr, value in memory.items():<EOL><INDENT>print("<STR_LIT>" % (addr, value, value))<EOL><DEDENT>
|
Print memory.
|
f3291:c0:m17
|
def _print_registers(self, registers):
|
for reg, value in registers.items():<EOL><INDENT>print("<STR_LIT>" % (reg, value, value))<EOL><DEDENT>
|
Print registers.
|
f3291:c0:m18
|
def verify(self, gadget):
|
<EOL>self.analyzer.reset()<EOL>for reil_instr in gadget.ir_instrs:<EOL><INDENT>self.analyzer.add_instruction(reil_instr)<EOL><DEDENT>constrs = self._constraints_generators[gadget.type](gadget)<EOL>if not constrs:<EOL><INDENT>return False<EOL><DEDENT>for constr in constrs:<EOL><INDENT>self.analyzer.add_constraint(constr)<EOL><DEDENT>return self.analyzer.check() == '<STR_LIT>'<EOL>
|
Verify gadgets.
|
f3292:c0:m1
|
def _get_constrs_no_operation(self, gadget):
|
<EOL>mem_constrs = [self.analyzer.get_memory_curr("<STR_LIT>").__neq__(self.analyzer.get_memory_curr("<STR_LIT>"))]<EOL>flags_constrs = []<EOL>for name in self._arch_info.registers_flags:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>flags_constrs += [var_initial != var_final]<EOL><DEDENT>reg_constrs = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>reg_constrs += [var_initial != var_final]<EOL><DEDENT>constrs = mem_constrs + flags_constrs + reg_constrs<EOL>constrs = [reduce(lambda c, acc: acc | c, constrs[<NUM_LIT:1>:], constrs[<NUM_LIT:0>])]<EOL>return constrs<EOL>
|
Verify NoOperation gadgets.
|
f3292:c0:m2
|
def _get_constrs_jump(self, gadget):
|
return None<EOL>
|
Verify Jump gadgets.
|
f3292:c0:m3
|
def _get_constrs_move_register(self, gadget):
|
<EOL>dst = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>src = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return [dst != src] + constrs_mod<EOL>
|
Generate constraints for the MoveRegister gadgets:
dst <- src
|
f3292:c0:m4
|
def _get_constrs_load_constant(self, gadget):
|
<EOL>dst = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>src = gadget.sources[<NUM_LIT:0>].immediate<EOL>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return [dst != src] + constrs_mod<EOL>
|
Generate constraints for the LoadConstant gadgets:
dst <- constant
|
f3292:c0:m5
|
def _get_constrs_arithmetic(self, gadget):
|
<EOL>dst = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>src1 = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>src2 = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:1>].name, mode="<STR_LIT>")<EOL>op = self._arithmetic_ops[gadget.operation]<EOL>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return [dst != op(src1, src2)] + constrs_mod<EOL>
|
Generate constraints for the BinaryOperation gadgets:
dst <- src1 OP src2
|
f3292:c0:m6
|
def _get_constrs_load_memory(self, gadget):
|
dst = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>size = gadget.destination[<NUM_LIT:0>].size<EOL>if isinstance(gadget.sources[<NUM_LIT:0>], ReilRegisterOperand):<EOL><INDENT>base_addr = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>offset = gadget.sources[<NUM_LIT:1>].immediate<EOL>addr = base_addr + offset<EOL><DEDENT>else:<EOL><INDENT>addr = gadget.sources[<NUM_LIT:1>].immediate<EOL><DEDENT>constrs = []<EOL>for i in reversed(range(<NUM_LIT:0>, size, <NUM_LIT:8>)):<EOL><INDENT>bytes_exprs_1 = self.analyzer.get_memory_expr(addr + i // <NUM_LIT:8>, <NUM_LIT:8> // <NUM_LIT:8>)<EOL>bytes_exprs_2 = smtfunction.extract(dst, i, <NUM_LIT:8>)<EOL>constrs += [bytes_exprs_1 != bytes_exprs_2]<EOL><DEDENT>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return constrs + constrs_mod<EOL>
|
Generate constraints for the LoadMemory gadgets: dst_reg <- mem[src_reg + offset]
|
f3292:c0:m7
|
def _get_constrs_store_memory(self, gadget):
|
if isinstance(gadget.destination[<NUM_LIT:0>], ReilRegisterOperand):<EOL><INDENT>base_addr = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>offset = gadget.destination[<NUM_LIT:1>].immediate<EOL>addr = base_addr + offset<EOL><DEDENT>else:<EOL><INDENT>addr = gadget.destination[<NUM_LIT:1>].immediate<EOL><DEDENT>src = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>size = gadget.sources[<NUM_LIT:0>].size<EOL>constrs = []<EOL>for i in reversed(range(<NUM_LIT:0>, size, <NUM_LIT:8>)):<EOL><INDENT>bytes_exprs_1 = self.analyzer.get_memory_expr(addr + i // <NUM_LIT:8>, <NUM_LIT:8> // <NUM_LIT:8>)<EOL>bytes_exprs_2 = smtfunction.extract(src, i, <NUM_LIT:8>)<EOL>constrs += [bytes_exprs_1 != bytes_exprs_2]<EOL><DEDENT>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return constrs + constrs_mod<EOL>
|
Generate constraints for the StoreMemory gadgets: mem[dst_reg + offset] <- src_reg
|
f3292:c0:m8
|
def _get_constrs_arithmetic_load(self, gadget):
|
op = self._arithmetic_ops[gadget.operation]<EOL>dst = self.analyzer.get_register_expr(gadget.destination[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>size = gadget.destination[<NUM_LIT:0>].size<EOL>if isinstance(gadget.sources[<NUM_LIT:1>], ReilRegisterOperand):<EOL><INDENT>base_addr = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:1>].name, mode="<STR_LIT>")<EOL>offset = gadget.sources[<NUM_LIT:2>].immediate<EOL>addr = base_addr + offset<EOL><DEDENT>else:<EOL><INDENT>addr = gadget.sources[<NUM_LIT:2>].immediate<EOL><DEDENT>src1 = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>src2 = self.analyzer.get_memory_expr(addr, size // <NUM_LIT:8>)<EOL>result = op(src1, src2)<EOL>constrs = []<EOL>for i in reversed(range(<NUM_LIT:0>, size, <NUM_LIT:8>)):<EOL><INDENT>bytes_exprs_1 = smtfunction.extract(result, i, <NUM_LIT:8>)<EOL>bytes_exprs_2 = smtfunction.extract(dst, i, <NUM_LIT:8>)<EOL>constrs += [bytes_exprs_1 != bytes_exprs_2]<EOL><DEDENT>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return constrs + constrs_mod<EOL>
|
Generate constraints for the ArithmeticLoad gadgets: dst_reg <- dst_reg OP mem[src_reg + offset]
|
f3292:c0:m9
|
def _get_constrs_arithmetic_store(self, gadget):
|
if isinstance(gadget.sources[<NUM_LIT:0>], ReilRegisterOperand):<EOL><INDENT>base_addr = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:0>].name, mode="<STR_LIT>")<EOL>offset = gadget.sources[<NUM_LIT:1>].immediate<EOL>addr = base_addr + offset<EOL><DEDENT>else:<EOL><INDENT>addr = gadget.sources[<NUM_LIT:1>].immediate<EOL><DEDENT>op = self._arithmetic_ops[gadget.operation]<EOL>size = gadget.sources[<NUM_LIT:2>].size<EOL>src1 = self.analyzer.get_register_expr(gadget.sources[<NUM_LIT:2>].name, mode="<STR_LIT>")<EOL>src2 = self.analyzer.get_memory_expr(addr, size // <NUM_LIT:8>, mode="<STR_LIT>")<EOL>dst = self.analyzer.get_memory_expr(addr, size // <NUM_LIT:8>, mode="<STR_LIT>")<EOL>result = op(src1, src2)<EOL>constrs = []<EOL>for i in reversed(range(<NUM_LIT:0>, size, <NUM_LIT:8>)):<EOL><INDENT>bytes_exprs_1 = smtfunction.extract(result, i, <NUM_LIT:8>)<EOL>bytes_exprs_2 = smtfunction.extract(dst, i, <NUM_LIT:8>)<EOL>constrs += [bytes_exprs_1 != bytes_exprs_2]<EOL><DEDENT>constrs_mod = []<EOL>for name in self._arch_info.registers_gp_base:<EOL><INDENT>if name not in [r.name for r in gadget.modified_registers]:<EOL><INDENT>var_initial = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>var_final = self.analyzer.get_register_expr(name, mode="<STR_LIT>")<EOL>constrs_mod += [var_initial != var_final]<EOL><DEDENT><DEDENT>if constrs_mod:<EOL><INDENT>constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[<NUM_LIT:1>:], constrs_mod[<NUM_LIT:0>])]<EOL><DEDENT>return constrs + constrs_mod<EOL>
|
Generate constraints for the ArithmeticStore gadgets: m[dst_reg + offset] <- m[dst_reg + offset] OP src_reg
|
f3292:c0:m10
|
@property<EOL><INDENT>def address(self):<DEDENT>
|
return self._instrs[<NUM_LIT:0>].address<EOL>
|
Get gadgets start address.
|
f3294:c0:m1
|
@property<EOL><INDENT>def instrs(self):<DEDENT>
|
return self._instrs<EOL>
|
Get gadgets instructions.
|
f3294:c0:m2
|
@property<EOL><INDENT>def ir_instrs(self):<DEDENT>
|
ir_instrs = []<EOL>for asm_instr in self._instrs:<EOL><INDENT>ir_instrs += asm_instr.ir_instrs<EOL><DEDENT>return ir_instrs<EOL>
|
Get gadgets IR instructions.
|
f3294:c0:m3
|
@property<EOL><INDENT>def id(self):<DEDENT>
|
return self._id<EOL>
|
Get gadgets validity status.
|
f3294:c0:m4
|
@id.setter<EOL><INDENT>def id(self, value):<DEDENT>
|
self._id = value<EOL>
|
Set gadgets validity status.
|
f3294:c0:m5
|
@property<EOL><INDENT>def sources(self):<DEDENT>
|
return self._sources<EOL>
|
Get gadgets sources.
|
f3294:c1:m1
|
@sources.setter<EOL><INDENT>def sources(self, value):<DEDENT>
|
self._sources = value<EOL>
|
Set gadgets sources.
|
f3294:c1:m2
|
@property<EOL><INDENT>def destination(self):<DEDENT>
|
return self._destination<EOL>
|
Get gadgets destination.
|
f3294:c1:m3
|
@destination.setter<EOL><INDENT>def destination(self, value):<DEDENT>
|
self._destination = value<EOL>
|
Set gadgets destination.
|
f3294:c1:m4
|
@property<EOL><INDENT>def modified_registers(self):<DEDENT>
|
return self._modified_regs<EOL>
|
Get gadgets modified registers.
|
f3294:c1:m5
|
@modified_registers.setter<EOL><INDENT>def modified_registers(self, value):<DEDENT>
|
self._modified_regs = value<EOL>
|
Set gadgets modified registers.
|
f3294:c1:m6
|
@property<EOL><INDENT>def verified(self):<DEDENT>
|
return self._verified<EOL>
|
Get gadgets verification status.
|
f3294:c1:m7
|
@verified.setter<EOL><INDENT>def verified(self, value):<DEDENT>
|
self._verified = value<EOL>
|
Set gadgets verification status.
|
f3294:c1:m8
|
@property<EOL><INDENT>def is_valid(self):<DEDENT>
|
if not self._verified:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._is_valid<EOL>
|
Get gadgets validity status.
|
f3294:c1:m9
|
@is_valid.setter<EOL><INDENT>def is_valid(self, value):<DEDENT>
|
self._verified = True<EOL>self._is_valid = value<EOL>
|
Set gadgets validity status.
|
f3294:c1:m10
|
@property<EOL><INDENT>def type(self):<DEDENT>
|
return self._gadget_type<EOL>
|
Get gadgets type.
|
f3294:c1:m11
|
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