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def parse_instruction(string, location, tokens):
mnemonic_str = tokens.get("<STR_LIT>")<EOL>operands = [op for op in tokens.get("<STR_LIT>", [])]<EOL>instr = ArmInstruction(<EOL>string,<EOL>mnemonic_str["<STR_LIT>"],<EOL>operands,<EOL>arch_info.architecture_mode<EOL>)<EOL>if "<STR_LIT>" in mnemonic_str:<EOL><INDENT>instr.condition_code = cc_mapper[mnemonic_str["<STR_LIT>"]]<EOL><DEDENT>if "<STR_LIT>" in mnemonic_str:<EOL><INDENT>instr.update_flags = True<EOL><DEDENT>if "<STR_LIT>" in mnemonic_str:<EOL><INDENT>instr.ldm_stm_addr_mode = ldm_stm_am_mapper[mnemonic_str["<STR_LIT>"]]<EOL><DEDENT>return instr<EOL>
Parse an ARM instruction.
f3324:m3
def parse(self, instr):
<EOL>try:<EOL><INDENT>instr_lower = instr.lower()<EOL>if instr_lower not in self._cache:<EOL><INDENT>instr_asm = instruction.parseString(instr_lower)[<NUM_LIT:0>]<EOL>self._cache[instr_lower] = instr_asm<EOL><DEDENT>instr_asm = copy.deepcopy(self._cache[instr_lower])<EOL><DEDENT>except Exception:<EOL><INDENT>instr_asm = None<EOL>error_msg = "<STR_LIT>"<EOL>logger.error(error_msg, instr, exc_info=True)<EOL><INDENT>print("<STR_LIT>" + instr)<EOL>print("<STR_LIT>" + str(e))<EOL><DEDENT><DEDENT>return instr_asm<EOL>
Parse an ARM instruction.
f3324:c0:m1
def _compute_memory_address(self, mem_operand):
base = ReilRegisterOperand(mem_operand.base_reg.name, mem_operand.size)<EOL>if mem_operand.displacement:<EOL><INDENT>address = self.temporal(mem_operand.size)<EOL>if isinstance(mem_operand.displacement, ArmRegisterOperand):<EOL><INDENT>disp = ReilRegisterOperand(mem_operand.displacement.name, mem_operand.size)<EOL><DEDENT>elif isinstance(mem_operand.displacement, ArmImmediateOperand):<EOL><INDENT>disp = ReilImmediateOperand(mem_operand.displacement.immediate, mem_operand.size)<EOL><DEDENT>elif isinstance(mem_operand.displacement, ArmShiftedRegisterOperand):<EOL><INDENT>disp = self._compute_shifted_register(mem_operand.displacement)<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>if mem_operand.index_type == ARM_MEMORY_INDEX_PRE:<EOL><INDENT>if mem_operand.disp_minus:<EOL><INDENT>self.add(self._builder.gen_sub(base, disp, address))<EOL><DEDENT>else:<EOL><INDENT>self.add(self._builder.gen_add(base, disp, address))<EOL><DEDENT>self.add(self._builder.gen_str(address, base))<EOL><DEDENT>elif mem_operand.index_type == ARM_MEMORY_INDEX_OFFSET:<EOL><INDENT>if mem_operand.disp_minus:<EOL><INDENT>self.add(self._builder.gen_sub(base, disp, address))<EOL><DEDENT>else:<EOL><INDENT>self.add(self._builder.gen_add(base, disp, address))<EOL><DEDENT><DEDENT>elif mem_operand.index_type == ARM_MEMORY_INDEX_POST:<EOL><INDENT>self.add(self._builder.gen_str(base, address))<EOL>tmp = self.temporal(base.size)<EOL>if mem_operand.disp_minus:<EOL><INDENT>self.add(self._builder.gen_sub(base, disp, tmp))<EOL><DEDENT>else:<EOL><INDENT>self.add(self._builder.gen_add(base, disp, tmp))<EOL><DEDENT>self.add(self._builder.gen_str(tmp, base))<EOL><DEDENT>else:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT><DEDENT>else:<EOL><INDENT>address = base<EOL><DEDENT>return address<EOL>
Return operand memory access translation.
f3325:c0:m4
def _compute_register_list(self, operand):
ret = []<EOL>for reg_range in operand.reg_list:<EOL><INDENT>if len(reg_range) == <NUM_LIT:1>:<EOL><INDENT>ret.append(ReilRegisterOperand(reg_range[<NUM_LIT:0>].name, reg_range[<NUM_LIT:0>].size))<EOL><DEDENT>else:<EOL><INDENT>reg_num = int(reg_range[<NUM_LIT:0>].name[<NUM_LIT:1>:]) <EOL>reg_end = int(reg_range[<NUM_LIT:1>].name[<NUM_LIT:1>:])<EOL>if reg_num > reg_end:<EOL><INDENT>raise NotImplementedError("<STR_LIT>")<EOL><DEDENT>while reg_num <= reg_end:<EOL><INDENT>ret.append(ReilRegisterOperand(reg_range[<NUM_LIT:0>].name[<NUM_LIT:0>] + str(reg_num), reg_range[<NUM_LIT:0>].size))<EOL>reg_num = reg_num + <NUM_LIT:1><EOL><DEDENT><DEDENT><DEDENT>return ret<EOL>
Return operand register list.
f3325:c0:m5
def translate(self, instruction):
try:<EOL><INDENT>trans_instrs = self.__translate(instruction)<EOL><DEDENT>except NotImplementedError:<EOL><INDENT>unkn_instr = self._builder.gen_unkn()<EOL>unkn_instr.address = instruction.address << <NUM_LIT:8> | (<NUM_LIT> & <NUM_LIT>)<EOL>trans_instrs = [unkn_instr]<EOL>self._log_not_supported_instruction(instruction)<EOL><DEDENT>except Exception:<EOL><INDENT>self._log_translation_exception(instruction)<EOL>raise<EOL><DEDENT>return trans_instrs<EOL>
Return IR representation of an instruction.
f3325:c1:m1
def disassemble(self, data, address, architecture_mode=None):
<EOL>if architecture_mode is None:<EOL><INDENT>if self._arch_mode is None:<EOL><INDENT>architecture_mode = ARCH_ARM_MODE_THUMB<EOL><DEDENT>else:<EOL><INDENT>architecture_mode = self._arch_mode<EOL><DEDENT><DEDENT>self._disassembler = self._available_disassemblers[architecture_mode]<EOL>disasm = self._cs_disassemble_one(data, address)<EOL>instr = self._cs_translate_insn(disasm)<EOL>if instr:<EOL><INDENT>instr.address = address<EOL>instr.size = disasm.size<EOL>instr.bytes = data[<NUM_LIT:0>:disasm.size]<EOL><DEDENT>else:<EOL><INDENT>raise DisassemblerError()<EOL><DEDENT>return instr<EOL>
Disassemble the data into an instruction.
f3326:c1:m1
def disassemble_all(self, data, address):
raise NotImplementedError()<EOL>
Disassemble the data into multiple instructions.
f3326:c1:m2
def _cs_disassemble_one(self, data, address):
disasm = list(self._disassembler.disasm(bytes(data), address))<EOL>if len(disasm) > <NUM_LIT:0>:<EOL><INDENT>return disasm[<NUM_LIT:0>]<EOL><DEDENT>else:<EOL><INDENT>cs_arm = Cs(CS_ARCH_ARM, CS_MODE_ARM)<EOL>cs_arm.detail = True<EOL>disasm = list(cs_arm.disasm(bytes(data), address))<EOL>if len(disasm) > <NUM_LIT:0>:<EOL><INDENT>return disasm[<NUM_LIT:0>]<EOL><DEDENT>else:<EOL><INDENT>raise InvalidDisassemblerData("<STR_LIT>".format(hex(address)))<EOL><DEDENT><DEDENT>
Disassemble the data into an instruction in string form.
f3326:c1:m3
@property<EOL><INDENT>def registers_all(self):<DEDENT>
return self._registers_all<EOL>
Return all registers.
f3327:c0:m5
@property<EOL><INDENT>def registers_gp_all(self):<DEDENT>
return self._registers_gp_all<EOL>
Return all general purpose registers.
f3327:c0:m6
@property<EOL><INDENT>def registers_gp_base(self):<DEDENT>
return self._registers_gp_base<EOL>
Return base general purpose registers.
f3327:c0:m7
@property<EOL><INDENT>def registers_flags(self):<DEDENT>
return self._registers_flags<EOL>
Return flag registers.
f3327:c0:m8
@property<EOL><INDENT>def registers_size(self):<DEDENT>
return self._registers_size<EOL>
Return the size of all registers.
f3327:c0:m9
@property<EOL><INDENT>def alias_mapper(self):<DEDENT>
return self._alias_mapper<EOL>
Return registers alias mapper.
f3327:c0:m10
@property<EOL><INDENT>def max_instruction_size(self):<DEDENT>
instruction_size_map = {<EOL>ARCH_ARM_MODE_ARM: <NUM_LIT:4>,<EOL>ARCH_ARM_MODE_THUMB: <NUM_LIT:4>,<EOL>}<EOL>return instruction_size_map[self._arch_mode]<EOL>
Return the maximum instruction size in bytes.
f3327:c0:m11
@property<EOL><INDENT>def orig_instr(self):<DEDENT>
return self._orig_instr<EOL>
Get instruction string before parsing.
f3327:c1:m1
@property<EOL><INDENT>def mnemonic(self):<DEDENT>
return self._mnemonic<EOL>
Get instruction mnemonic.
f3327:c1:m2
@property<EOL><INDENT>def mnemonic_full(self):<DEDENT>
return self._mnemonic + cc_inverse_mapper[self.condition_code]<EOL>
Get instruction mnemonic with condition code.
f3327:c1:m3
@property<EOL><INDENT>def operands(self):<DEDENT>
return self._operands<EOL>
Get instruction operands.
f3327:c1:m4
@operands.setter<EOL><INDENT>def operands(self, value):<DEDENT>
self._operands = value<EOL>
Set instruction operands.
f3327:c1:m5
@property<EOL><INDENT>def bytes(self):<DEDENT>
return self._bytes<EOL>
Get instruction byte representation.
f3327:c1:m6
@bytes.setter<EOL><INDENT>def bytes(self, value):<DEDENT>
self._bytes = value<EOL>
Set instruction byte representation.
f3327:c1:m7
@property<EOL><INDENT>def size(self):<DEDENT>
return self._size<EOL>
Get instruction size.
f3327:c1:m8
@size.setter<EOL><INDENT>def size(self, value):<DEDENT>
self._size = value<EOL>
Set instruction size.
f3327:c1:m9
@property<EOL><INDENT>def address(self):<DEDENT>
return self._address<EOL>
Get instruction address.
f3327:c1:m10
@address.setter<EOL><INDENT>def address(self, value):<DEDENT>
self._address = value<EOL>
Set instruction address.
f3327:c1:m11
@property<EOL><INDENT>def modifier(self):<DEDENT>
return self._modifier<EOL>
Get operand modifier.
f3327:c2:m1
@modifier.setter<EOL><INDENT>def modifier(self, value):<DEDENT>
self._modifier = value<EOL>
Set operand modifier.
f3327:c2:m2
@property<EOL><INDENT>def size(self):<DEDENT>
return self._size<EOL>
Get operand size.
f3327:c2:m3
@size.setter<EOL><INDENT>def size(self, value):<DEDENT>
self._size = value<EOL>
Set operand size.
f3327:c2:m4
@property<EOL><INDENT>def immediate(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._immediate<EOL>
Get immediate.
f3327:c3:m1
@property<EOL><INDENT>def name(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._name<EOL>
Get register name.
f3327:c4:m1
@property<EOL><INDENT>def reg_list(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._reg_list<EOL>
Get register list.
f3327:c5:m1
@property<EOL><INDENT>def base_reg(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._base_reg<EOL>
Get base register.
f3327:c6:m1
@property<EOL><INDENT>def shift_type(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._shift_type<EOL>
Get shift type.
f3327:c6:m2
@property<EOL><INDENT>def shift_amount(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._shift_amount<EOL>
Get shift amount.
f3327:c6:m3
@property<EOL><INDENT>def base_reg(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._base_reg<EOL>
Get base register.
f3327:c7:m1
@property<EOL><INDENT>def displacement(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._displacement<EOL>
Get displacement to the base register.
f3327:c7:m2
@property<EOL><INDENT>def index_type(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._index_type<EOL>
Get type of memory indexing.
f3327:c7:m3
@property<EOL><INDENT>def disp_minus(self):<DEDENT>
if not self._size:<EOL><INDENT>raise Exception("<STR_LIT>")<EOL><DEDENT>return self._disp_minus<EOL>
Get sign of displacement.
f3327:c7:m4
def execute(self, asm_instr):
<EOL>self.ir_emulator.registers[self.ip] = asm_instr.address + asm_instr.size<EOL>if self.arch_info.instr_is_syscall(asm_instr):<EOL><INDENT>raise Syscall()<EOL><DEDENT>return self.__execute(asm_instr)<EOL>
Execute an assembler instruction. Args: asm_instr (X86Instruction): A instruction to execute. Returns: A int. The address of the next instruction to execute.
f3333:c2:m6
def _setup_arch(self, arch_mode=None):
<EOL>self.arch_info = None<EOL>if self.binary.architecture == ARCH_X86:<EOL><INDENT>self._setup_x86_arch(arch_mode)<EOL><DEDENT>else:<EOL><INDENT>self._setup_arm_arch(arch_mode)<EOL><DEDENT>
Set up architecture.
f3337:c0:m2
def _setup_arm_arch(self, arch_mode=None):
if arch_mode is None:<EOL><INDENT>arch_mode = ARCH_ARM_MODE_THUMB<EOL><DEDENT>self.name = "<STR_LIT>"<EOL>self.arch_info = ArmArchitectureInformation(arch_mode)<EOL>self.disassembler = ArmDisassembler(architecture_mode=arch_mode)<EOL>self.ir_translator = ArmTranslator(architecture_mode=arch_mode)<EOL>
Set up ARM architecture.
f3337:c0:m3
def _setup_x86_arch(self, arch_mode=None):
if arch_mode is None:<EOL><INDENT>arch_mode = self.binary.architecture_mode<EOL><DEDENT>self.name = "<STR_LIT>"<EOL>self.arch_info = X86ArchitectureInformation(arch_mode)<EOL>self.disassembler = X86Disassembler(arch_mode)<EOL>self.ir_translator = X86Translator(arch_mode)<EOL>
Set up x86 architecture.
f3337:c0:m4
def _setup_core_modules(self):
self.ir_emulator = None<EOL>self.smt_solver = None<EOL>self.smt_translator = None<EOL>if self.arch_info:<EOL><INDENT>self.ir_emulator = ReilEmulator(self.arch_info)<EOL>self.smt_solver = None<EOL>if SMT_SOLVER not in ("<STR_LIT>", "<STR_LIT>"):<EOL><INDENT>raise Exception("<STR_LIT>".format(SMT_SOLVER))<EOL><DEDENT>try:<EOL><INDENT>if SMT_SOLVER == "<STR_LIT>":<EOL><INDENT>self.smt_solver = Z3Solver()<EOL><DEDENT>elif SMT_SOLVER == "<STR_LIT>":<EOL><INDENT>self.smt_solver = CVC4Solver()<EOL><DEDENT><DEDENT>except SmtSolverNotFound:<EOL><INDENT>logger.warn("<STR_LIT>".format(SMT_SOLVER))<EOL><DEDENT>self.smt_translator = None<EOL>if self.smt_solver:<EOL><INDENT>self.smt_translator = SmtTranslator(self.smt_solver, self.arch_info.address_size)<EOL>self.smt_translator.set_arch_alias_mapper(self.arch_info.alias_mapper)<EOL>self.smt_translator.set_arch_registers_size(self.arch_info.registers_size)<EOL><DEDENT><DEDENT>
Set up core modules.
f3337:c0:m5
def _setup_analysis_modules(self):
<EOL>self.bb_builder = CFGRecoverer(RecursiveDescent(self.disassembler, self.text_section, self.ir_translator,<EOL>self.arch_info))<EOL>self.code_analyzer = None<EOL>if self.smt_translator:<EOL><INDENT>self.code_analyzer = CodeAnalyzer(self.smt_solver, self.smt_translator, self.arch_info)<EOL><DEDENT>self.gadget_classifier = GadgetClassifier(self.ir_emulator, self.arch_info)<EOL>self.gadget_finder = GadgetFinder(self.disassembler, self.text_section, self.ir_translator,<EOL>self.binary.architecture, self.binary.architecture_mode)<EOL>self.gadget_verifier = None<EOL>if self.code_analyzer:<EOL><INDENT>self.gadget_verifier = GadgetVerifier(self.code_analyzer, self.arch_info)<EOL><DEDENT>self.emulator = Emulator(self.arch_info, self.ir_emulator, self.ir_translator, self.disassembler)<EOL>
Set up analysis modules.
f3337:c0:m6
def open(self, filename):
if filename:<EOL><INDENT>self.binary = BinaryFile(filename)<EOL>self.text_section = self.binary.text_section<EOL>self._load(arch_mode=self.binary.architecture_mode)<EOL><DEDENT>
Open a file for analysis. Args: filename (str): Name of an executable file.
f3337:c0:m7
def load_architecture(self, name, arch_info, disassembler, translator):
<EOL>self.name = name<EOL>self.arch_info = arch_info<EOL>self.disassembler = disassembler<EOL>self.ir_translator = translator<EOL>self._setup_analysis_modules()<EOL>
Translate to REIL instructions. Args: name (str): Architecture's name. arch_info (ArchitectureInformation): Architecture information object. disassembler (Disassembler): Disassembler for the architecture. translator (Translator): Translator for the architecture.
f3337:c0:m8
def translate(self, start=None, end=None, arch_mode=None):
start_addr = start if start else self.binary.ea_start<EOL>end_addr = end if end else self.binary.ea_end<EOL>self.ir_translator.reset()<EOL>for addr, asm, _ in self.disassemble(start=start_addr, end=end_addr, arch_mode=arch_mode):<EOL><INDENT>yield addr, asm, self.ir_translator.translate(asm)<EOL><DEDENT>
Translate to REIL instructions. Args: start (int): Start address. end (int): End address. arch_mode (int): Architecture mode. Returns: (int, Instruction, list): A tuple of the form (address, assembler instruction, REIL instructions).
f3337:c0:m9
def disassemble(self, start=None, end=None, arch_mode=None):
if arch_mode is None:<EOL><INDENT>arch_mode = self.binary.architecture_mode<EOL><DEDENT>curr_addr = start if start else self.binary.ea_start<EOL>end_addr = end if end else self.binary.ea_end<EOL>while curr_addr < end_addr:<EOL><INDENT>encoding = self.__fetch_instr(curr_addr)<EOL>asm_instr = self.disassembler.disassemble(encoding, curr_addr, architecture_mode=arch_mode)<EOL>if not asm_instr:<EOL><INDENT>return<EOL><DEDENT>yield curr_addr, asm_instr, asm_instr.size<EOL>curr_addr += asm_instr.size<EOL><DEDENT>
Disassemble native instructions. Args: start (int): Start address. end (int): End address. arch_mode (int): Architecture mode. Returns: (int, Instruction, int): A tuple of the form (address, assembler instruction, instruction size).
f3337:c0:m10
def recover_cfg(self, start=None, end=None, symbols=None, callback=None, arch_mode=None):
<EOL>if arch_mode is None:<EOL><INDENT>arch_mode = self.binary.architecture_mode<EOL><DEDENT>self._load(arch_mode=arch_mode)<EOL>start = start if start else self.binary.entry_point<EOL>cfg, _ = self._recover_cfg(start=start, end=end, symbols=symbols, callback=callback)<EOL>return cfg<EOL>
Recover CFG. Args: start (int): Start address. end (int): End address. symbols (dict): Symbol table. callback (function): A callback function which is called after each successfully recovered CFG. arch_mode (int): Architecture mode. Returns: ControlFlowGraph: A CFG.
f3337:c0:m11
def recover_cfg_all(self, entries, symbols=None, callback=None, arch_mode=None):
<EOL>if arch_mode is None:<EOL><INDENT>arch_mode = self.binary.architecture_mode<EOL><DEDENT>self._load(arch_mode=arch_mode)<EOL>symbols = {} if not symbols else symbols<EOL>cfgs = []<EOL>addrs_processed = set()<EOL>calls = entries<EOL>while len(calls) > <NUM_LIT:0>:<EOL><INDENT>start, calls = calls[<NUM_LIT:0>], calls[<NUM_LIT:1>:]<EOL>cfg, calls_tmp = self._recover_cfg(start=start, symbols=symbols, callback=callback)<EOL>addrs_processed.add(start)<EOL>cfgs.append(cfg)<EOL>for addr in sorted(calls_tmp):<EOL><INDENT>if addr not in addrs_processed and addr not in calls:<EOL><INDENT>calls.append(addr)<EOL><DEDENT><DEDENT><DEDENT>return cfgs<EOL>
Recover CFG for all functions from an entry point and/or symbol table. Args: entries (list): A list of function addresses' to start the CFG recovery process. symbols (dict): Symbol table. callback (function): A callback function which is called after each successfully recovered CFG. arch_mode (int): Architecture mode. Returns: list: A list of recovered CFGs.
f3337:c0:m12
def _recover_cfg(self, start=None, end=None, symbols=None, callback=None):
<EOL>if symbols and start in symbols:<EOL><INDENT>name = symbols[start][<NUM_LIT:0>]<EOL>size = symbols[start][<NUM_LIT:1>] - <NUM_LIT:1> if symbols[start][<NUM_LIT:1>] != <NUM_LIT:0> else <NUM_LIT:0><EOL><DEDENT>else:<EOL><INDENT>name = "<STR_LIT>".format(start)<EOL>size = <NUM_LIT:0><EOL><DEDENT>start_addr = start if start else self.binary.ea_start<EOL>end_addr = end if end else self.binary.ea_end<EOL>if callback:<EOL><INDENT>callback(start, name, size)<EOL><DEDENT>bbs, calls = self.bb_builder.build(start_addr, end_addr, symbols)<EOL>cfg = ControlFlowGraph(bbs, name=name)<EOL>return cfg, calls<EOL>
Recover CFG
f3337:c0:m13
def emulate(self, context=None, start=None, end=None, arch_mode=None, hooks=None, max_instrs=None, print_asm=False):
if arch_mode is not None:<EOL><INDENT>self._load(arch_mode=arch_mode)<EOL><DEDENT>context = context if context else {}<EOL>start_addr = start if start else self.binary.ea_start<EOL>end_addr = end if end else self.binary.ea_end<EOL>hooks = hooks if hooks else {}<EOL>for reg, val in context.get('<STR_LIT>', {}).items():<EOL><INDENT>self.ir_emulator.registers[reg] = val<EOL><DEDENT>for addr, val in context.get('<STR_LIT>', {}).items():<EOL><INDENT>self.ir_emulator.memory.write(addr, <NUM_LIT:4>, val)<EOL><DEDENT>self.emulator.emulate(start_addr, end_addr, hooks, max_instrs, print_asm)<EOL>context_out = {<EOL>'<STR_LIT>': {},<EOL>'<STR_LIT>': {}<EOL>}<EOL>for reg, val in self.ir_emulator.registers.items():<EOL><INDENT>context_out['<STR_LIT>'][reg] = val<EOL><DEDENT>return context_out<EOL>
Emulate native code. Args: context (dict): Processor context (register and/or memory). start (int): Start address. end (int): End address. arch_mode (int): Architecture mode. hooks (dict): Hooks by address. max_instrs (int): Maximum number of instructions to execute. print_asm (bool): Print asm. Returns: dict: Processor context.
f3337:c0:m14
def check_path_satisfiability(code_analyzer, path, start_address):
start_instr_found = False<EOL>sat = False<EOL>for bb_curr, bb_next in zip(path[:-<NUM_LIT:1>], path[<NUM_LIT:1>:]):<EOL><INDENT>logger.info("<STR_LIT>".format(bb_curr.address))<EOL>for instr in bb_curr:<EOL><INDENT>if not start_instr_found:<EOL><INDENT>if instr.address == start_address:<EOL><INDENT>start_instr_found = True<EOL><DEDENT>else:<EOL><INDENT>continue<EOL><DEDENT><DEDENT>logger.info("<STR_LIT>".format(instr.address, instr))<EOL>for reil_instr in instr.ir_instrs:<EOL><INDENT>logger.info("<STR_LIT>".format(reil_instr.address >> <NUM_LIT>, reil_instr.address & <NUM_LIT>,<EOL>reil_instr))<EOL>if reil_instr.mnemonic == ReilMnemonic.JCC:<EOL><INDENT>if instr.address + instr.size - <NUM_LIT:1> != bb_curr.end_address:<EOL><INDENT>logger.error("<STR_LIT>".format(instr.address,<EOL>instr,<EOL>reil_instr))<EOL>continue<EOL><DEDENT>assert(bb_curr.taken_branch == bb_next.address or<EOL>bb_curr.not_taken_branch == bb_next.address or<EOL>bb_curr.direct_branch == bb_next.address)<EOL>if bb_curr.taken_branch == bb_next.address:<EOL><INDENT>branch_var_goal = <NUM_LIT><EOL><DEDENT>elif bb_curr.not_taken_branch == bb_next.address:<EOL><INDENT>branch_var_goal = <NUM_LIT><EOL><DEDENT>else:<EOL><INDENT>continue<EOL><DEDENT>code_analyzer.add_constraint(code_analyzer.get_operand_expr(reil_instr.operands[<NUM_LIT:0>]) == branch_var_goal)<EOL>break<EOL><DEDENT>code_analyzer.add_instruction(reil_instr)<EOL><DEDENT><DEDENT>sat = code_analyzer.check() == '<STR_LIT>'<EOL>logger.info("<STR_LIT>".format(bb_curr.address, sat))<EOL>if not sat:<EOL><INDENT>break<EOL><DEDENT><DEDENT>return sat<EOL>
Check satisfiability of a basic block path.
f3343:m0
def isuri(uristring):
return urisplit(uristring).isuri()<EOL>
Return :const:`True` if `uristring` is a URI.
f3358:m0
def isabsuri(uristring):
return urisplit(uristring).isabsuri()<EOL>
Return :const:`True` if `uristring` is an absolute URI.
f3358:m1
def isnetpath(uristring):
return urisplit(uristring).isnetpath()<EOL>
Return :const:`True` if `uristring` is a network-path reference.
f3358:m2
def isabspath(uristring):
return urisplit(uristring).isabspath()<EOL>
Return :const:`True` if `uristring` is an absolute-path reference.
f3358:m3
def isrelpath(uristring):
return urisplit(uristring).isrelpath()<EOL>
Return :const:`True` if `uristring` is a relative-path reference.
f3358:m4
def issamedoc(uristring):
return urisplit(uristring).issamedoc()<EOL>
Return :const:`True` if `uristring` is a same-document reference.
f3358:m5
def uridefrag(uristring):
if isinstance(uristring, bytes):<EOL><INDENT>parts = uristring.partition(b'<STR_LIT:#>')<EOL><DEDENT>else:<EOL><INDENT>parts = uristring.partition(u'<STR_LIT:#>')<EOL><DEDENT>return DefragResult(parts[<NUM_LIT:0>], parts[<NUM_LIT:2>] if parts[<NUM_LIT:1>] else None)<EOL>
Remove an existing fragment component from a URI reference string.
f3359:m0
def geturi(self):
fragment = self.fragment<EOL>if fragment is None:<EOL><INDENT>return self.uri<EOL><DEDENT>elif isinstance(fragment, bytes):<EOL><INDENT>return self.uri + b'<STR_LIT:#>' + fragment<EOL><DEDENT>else:<EOL><INDENT>return self.uri + u'<STR_LIT:#>' + fragment<EOL><DEDENT>
Return the recombined version of the original URI as a string.
f3359:c0:m0
def getfragment(self, default=None, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
fragment = self.fragment<EOL>if fragment is not None:<EOL><INDENT>return uridecode(fragment, encoding, errors)<EOL><DEDENT>else:<EOL><INDENT>return default<EOL><DEDENT>
Return the decoded fragment identifier, or `default` if the original URI did not contain a fragment component.
f3359:c0:m1
def urijoin(base, ref, strict=False):
if isinstance(base, type(ref)):<EOL><INDENT>return urisplit(base).transform(ref, strict).geturi()<EOL><DEDENT>elif isinstance(base, bytes):<EOL><INDENT>return urisplit(base.decode()).transform(ref, strict).geturi()<EOL><DEDENT>else:<EOL><INDENT>return urisplit(base).transform(ref.decode(), strict).geturi()<EOL><DEDENT>
Convert a URI reference relative to a base URI to its target URI string.
f3360:m0
def uricompose(scheme=None, authority=None, path='<STR_LIT>', query=None,<EOL>fragment=None, userinfo=None, host=None, port=None,<EOL>querysep='<STR_LIT:&>', encoding='<STR_LIT:utf-8>'):
<EOL>if isinstance(scheme, bytes):<EOL><INDENT>scheme = _scheme(scheme)<EOL><DEDENT>elif scheme is not None:<EOL><INDENT>scheme = _scheme(scheme.encode())<EOL><DEDENT>if authority is None:<EOL><INDENT>authority = (None, None, None)<EOL><DEDENT>elif isinstance(authority, bytes):<EOL><INDENT>authority = _AUTHORITY_RE_BYTES.match(authority).groups()<EOL><DEDENT>elif isinstance(authority, _unicode):<EOL><INDENT>authority = _AUTHORITY_RE_UNICODE.match(authority).groups()<EOL><DEDENT>elif not isinstance(authority, collections.Iterable):<EOL><INDENT>raise TypeError('<STR_LIT>')<EOL><DEDENT>elif len(authority) != <NUM_LIT:3>:<EOL><INDENT>raise ValueError('<STR_LIT>')<EOL><DEDENT>authority = _authority(<EOL>userinfo if userinfo is not None else authority[<NUM_LIT:0>],<EOL>host if host is not None else authority[<NUM_LIT:1>],<EOL>port if port is not None else authority[<NUM_LIT:2>],<EOL>encoding<EOL>)<EOL>path = uriencode(path, _SAFE_PATH, encoding)<EOL>if authority is not None and path and not path.startswith(b'<STR_LIT:/>'):<EOL><INDENT>raise ValueError('<STR_LIT>')<EOL><DEDENT>if authority is None and path.startswith(b'<STR_LIT>'):<EOL><INDENT>raise ValueError('<STR_LIT>')<EOL><DEDENT>if scheme is None and authority is None and not path.startswith(b'<STR_LIT:/>'):<EOL><INDENT>if b'<STR_LIT::>' in path.partition(b'<STR_LIT:/>')[<NUM_LIT:0>]:<EOL><INDENT>path = b'<STR_LIT>' + path<EOL><DEDENT><DEDENT>if isinstance(query, _strtypes):<EOL><INDENT>query = uriencode(query, _SAFE_QUERY, encoding)<EOL><DEDENT>elif isinstance(query, collections.Mapping):<EOL><INDENT>query = _querydict(query, querysep, encoding)<EOL><DEDENT>elif isinstance(query, collections.Iterable):<EOL><INDENT>query = _querylist(query, querysep, encoding)<EOL><DEDENT>elif query is not None:<EOL><INDENT>raise TypeError('<STR_LIT>')<EOL><DEDENT>if fragment is not None:<EOL><INDENT>fragment = uriencode(fragment, _SAFE_FRAGMENT, encoding)<EOL><DEDENT>result = uriunsplit((scheme, authority, path, query, fragment))<EOL>return result if isinstance(result, str) else result.decode()<EOL>
Compose a URI reference string from its individual components.
f3362:m7
def uriencode(uristring, safe='<STR_LIT>', encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
if not isinstance(uristring, bytes):<EOL><INDENT>uristring = uristring.encode(encoding, errors)<EOL><DEDENT>if not isinstance(safe, bytes):<EOL><INDENT>safe = safe.encode('<STR_LIT:ascii>')<EOL><DEDENT>try:<EOL><INDENT>encoded = _encoded[safe]<EOL><DEDENT>except KeyError:<EOL><INDENT>encoded = _encoded[b'<STR_LIT>'][:]<EOL>for i in _tointseq(safe):<EOL><INDENT>encoded[i] = _fromint(i)<EOL><DEDENT>_encoded[safe] = encoded<EOL><DEDENT>return b'<STR_LIT>'.join(map(encoded.__getitem__, _tointseq(uristring)))<EOL>
Encode a URI string or string component.
f3363:m1
def uridecode(uristring, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
if not isinstance(uristring, bytes):<EOL><INDENT>uristring = uristring.encode(encoding or '<STR_LIT:ascii>', errors)<EOL><DEDENT>parts = uristring.split(b'<STR_LIT:%>')<EOL>result = [parts[<NUM_LIT:0>]]<EOL>append = result.append<EOL>decode = _decoded.get<EOL>for s in parts[<NUM_LIT:1>:]:<EOL><INDENT>append(decode(s[:<NUM_LIT:2>], b'<STR_LIT:%>' + s[:<NUM_LIT:2>]))<EOL>append(s[<NUM_LIT:2>:])<EOL><DEDENT>if encoding is not None:<EOL><INDENT>return b'<STR_LIT>'.join(result).decode(encoding, errors)<EOL><DEDENT>else:<EOL><INDENT>return b'<STR_LIT>'.join(result)<EOL><DEDENT>
Decode a URI string or string component.
f3363:m2
def urisplit(uristring):
if isinstance(uristring, bytes):<EOL><INDENT>result = SplitResultBytes<EOL><DEDENT>else:<EOL><INDENT>result = SplitResultUnicode<EOL><DEDENT>return result(*result.RE.match(uristring).groups())<EOL>
Split a well-formed URI reference string into a tuple with five components corresponding to a URI's general structure:: <scheme>://<authority>/<path>?<query>#<fragment>
f3364:m2
def uriunsplit(parts):
scheme, authority, path, query, fragment = parts<EOL>if isinstance(path, bytes):<EOL><INDENT>result = SplitResultBytes<EOL><DEDENT>else:<EOL><INDENT>result = SplitResultUnicode<EOL><DEDENT>return result(scheme, authority, path, query, fragment).geturi()<EOL>
Combine the elements of a five-item iterable into a URI reference's string representation.
f3364:m3
def geturi(self):
scheme, authority, path, query, fragment = self<EOL>result = []<EOL>if scheme is not None:<EOL><INDENT>result.extend([scheme, self.COLON])<EOL><DEDENT>if authority is not None:<EOL><INDENT>result.extend([self.SLASH, self.SLASH, authority])<EOL><DEDENT>result.append(path)<EOL>if query is not None:<EOL><INDENT>result.extend([self.QUEST, query])<EOL><DEDENT>if fragment is not None:<EOL><INDENT>result.extend([self.HASH, fragment])<EOL><DEDENT>return self.EMPTY.join(result)<EOL>
Return the re-combined version of the original URI reference as a string.
f3364:c0:m3
def getscheme(self, default=None):
scheme = self.scheme<EOL>if scheme is None:<EOL><INDENT>return default<EOL><DEDENT>elif isinstance(scheme, bytes):<EOL><INDENT>return scheme.decode('<STR_LIT:ascii>').lower()<EOL><DEDENT>else:<EOL><INDENT>return scheme.lower()<EOL><DEDENT>
Return the URI scheme in canonical (lowercase) form, or `default` if the original URI reference did not contain a scheme component.
f3364:c0:m4
def getauthority(self, default=None, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
<EOL>if default is None:<EOL><INDENT>default = (None, None, None)<EOL><DEDENT>elif not isinstance(default, collections.Iterable):<EOL><INDENT>raise TypeError('<STR_LIT>')<EOL><DEDENT>elif len(default) != <NUM_LIT:3>:<EOL><INDENT>raise ValueError('<STR_LIT>')<EOL><DEDENT>return (<EOL>self.getuserinfo(default[<NUM_LIT:0>], encoding, errors),<EOL>self.gethost(default[<NUM_LIT:1>], errors),<EOL>self.getport(default[<NUM_LIT:2>])<EOL>)<EOL>
Return the decoded userinfo, host and port subcomponents of the URI authority as a three-item tuple.
f3364:c0:m5
def getuserinfo(self, default=None, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
userinfo = self.userinfo<EOL>if userinfo is None:<EOL><INDENT>return default<EOL><DEDENT>else:<EOL><INDENT>return uridecode(userinfo, encoding, errors)<EOL><DEDENT>
Return the decoded userinfo subcomponent of the URI authority, or `default` if the original URI reference did not contain a userinfo field.
f3364:c0:m6
def gethost(self, default=None, errors='<STR_LIT:strict>'):
host = self.host<EOL>if host is None or (not host and default is not None):<EOL><INDENT>return default<EOL><DEDENT>elif host.startswith(self.LBRACKET) and host.endswith(self.RBRACKET):<EOL><INDENT>return _ip_literal(host[<NUM_LIT:1>:-<NUM_LIT:1>])<EOL><DEDENT>elif host.startswith(self.LBRACKET) or host.endswith(self.RBRACKET):<EOL><INDENT>raise ValueError('<STR_LIT>' % host)<EOL><DEDENT>return _ipv4_address(host) or uridecode(host, '<STR_LIT:utf-8>', errors).lower()<EOL>
Return the decoded host subcomponent of the URI authority as a string or an :mod:`ipaddress` address object, or `default` if the original URI reference did not contain a host.
f3364:c0:m7
def getport(self, default=None):
port = self.port<EOL>if port:<EOL><INDENT>return int(port)<EOL><DEDENT>else:<EOL><INDENT>return default<EOL><DEDENT>
Return the port subcomponent of the URI authority as an :class:`int`, or `default` if the original URI reference did not contain a port or if the port was empty.
f3364:c0:m8
def getpath(self, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
path = self.__remove_dot_segments(self.path)<EOL>return uridecode(path, encoding, errors)<EOL>
Return the normalized decoded URI path.
f3364:c0:m9
def getquery(self, default=None, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
query = self.query<EOL>if query is None:<EOL><INDENT>return default<EOL><DEDENT>else:<EOL><INDENT>return uridecode(query, encoding, errors)<EOL><DEDENT>
Return the decoded query string, or `default` if the original URI reference did not contain a query component.
f3364:c0:m10
def getquerydict(self, sep='<STR_LIT:&>', encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
dict = collections.defaultdict(list)<EOL>for name, value in self.getquerylist(sep, encoding, errors):<EOL><INDENT>dict[name].append(value)<EOL><DEDENT>return dict<EOL>
Split the query component into individual `name=value` pairs separated by `sep` and return a dictionary of query variables. The dictionary keys are the unique query variable names and the values are lists of values for each name.
f3364:c0:m11
def getquerylist(self, sep='<STR_LIT:&>', encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
if not self.query:<EOL><INDENT>return []<EOL><DEDENT>elif isinstance(sep, type(self.query)):<EOL><INDENT>qsl = self.query.split(sep)<EOL><DEDENT>elif isinstance(sep, bytes):<EOL><INDENT>qsl = self.query.split(sep.decode('<STR_LIT:ascii>'))<EOL><DEDENT>else:<EOL><INDENT>qsl = self.query.split(sep.encode('<STR_LIT:ascii>'))<EOL><DEDENT>items = []<EOL>for parts in [qs.partition(self.EQ) for qs in qsl if qs]:<EOL><INDENT>name = uridecode(parts[<NUM_LIT:0>], encoding, errors)<EOL>if parts[<NUM_LIT:1>]:<EOL><INDENT>value = uridecode(parts[<NUM_LIT:2>], encoding, errors)<EOL><DEDENT>else:<EOL><INDENT>value = None<EOL><DEDENT>items.append((name, value))<EOL><DEDENT>return items<EOL>
Split the query component into individual `name=value` pairs separated by `sep`, and return a list of `(name, value)` tuples.
f3364:c0:m12
def getfragment(self, default=None, encoding='<STR_LIT:utf-8>', errors='<STR_LIT:strict>'):
fragment = self.fragment<EOL>if fragment is None:<EOL><INDENT>return default<EOL><DEDENT>else:<EOL><INDENT>return uridecode(fragment, encoding, errors)<EOL><DEDENT>
Return the decoded fragment identifier, or `default` if the original URI reference did not contain a fragment component.
f3364:c0:m13
def isuri(self):
return self.scheme is not None<EOL>
Return :const:`True` if this is a URI.
f3364:c0:m14
def isabsuri(self):
return self.scheme is not None and self.fragment is None<EOL>
Return :const:`True` if this is an absolute URI.
f3364:c0:m15
def isnetpath(self):
return self.scheme is None and self.authority is not None<EOL>
Return :const:`True` if this is a network-path reference.
f3364:c0:m16
def isabspath(self):
return (self.scheme is None and self.authority is None and<EOL>self.path.startswith(self.SLASH))<EOL>
Return :const:`True` if this is an absolute-path reference.
f3364:c0:m17
def isrelpath(self):
return (self.scheme is None and self.authority is None and<EOL>not self.path.startswith(self.SLASH))<EOL>
Return :const:`True` if this is a relative-path reference.
f3364:c0:m18
def issamedoc(self):
return (self.scheme is None and self.authority is None and<EOL>not self.path and self.query is None)<EOL>
Return :const:`True` if this is a same-document reference.
f3364:c0:m19
def transform(self, ref, strict=False):
scheme, authority, path, query, fragment = self.RE.match(ref).groups()<EOL>if scheme is not None and (strict or scheme != self.scheme):<EOL><INDENT>path = self.__remove_dot_segments(path)<EOL><DEDENT>elif authority is not None:<EOL><INDENT>scheme = self.scheme<EOL>path = self.__remove_dot_segments(path)<EOL><DEDENT>elif not path:<EOL><INDENT>scheme = self.scheme<EOL>authority = self.authority<EOL>path = self.path<EOL>query = self.query if query is None else query<EOL><DEDENT>elif path.startswith(self.SLASH):<EOL><INDENT>scheme = self.scheme<EOL>authority = self.authority<EOL>path = self.__remove_dot_segments(path)<EOL><DEDENT>else:<EOL><INDENT>scheme = self.scheme<EOL>authority = self.authority<EOL>path = self.__remove_dot_segments(self.__merge(path))<EOL><DEDENT>return type(self)(scheme, authority, path, query, fragment)<EOL>
Transform a URI reference relative to `self` into a :class:`SplitResult` representing its target URI.
f3364:c0:m20
@staticmethod<EOL><INDENT>def build_get_parameter(origName, rwName):<DEDENT>
return {<EOL>'<STR_LIT>': '<STR_LIT>'.format(origName),<EOL>'<STR_LIT:name>': rwName,<EOL>'<STR_LIT>': False,<EOL>'<STR_LIT>': [],<EOL>'<STR_LIT:type>': '<STR_LIT>',<EOL>'<STR_LIT>': '<STR_LIT>',<EOL>'<STR_LIT>': '<STR_LIT>',<EOL>'<STR_LIT>': None<EOL>}<EOL>
Builds parameter description in the format returned by gquery.get_parameters
f3369:c0:m9
def init_cache():
cache_obj = json.loads("<STR_LIT:{}>")<EOL>try:<EOL><INDENT>with open(CACHE_NAME, '<STR_LIT:r>') as cache_file:<EOL><INDENT>try:<EOL><INDENT>cache_obj = json.load(cache_file)<EOL><DEDENT>except ValueError:<EOL><INDENT>print("<STR_LIT>")<EOL><DEDENT><DEDENT><DEDENT>except IOError:<EOL><INDENT>print("<STR_LIT>")<EOL><DEDENT>print("<STR_LIT>")<EOL>return cache_obj<EOL>
Initializes the grlc cache (json file)
f3376:m0
def getProjectionForQueryName(self, query_name):
projectionFileName = query_name + '<STR_LIT>'<EOL>projectionText = self._getText(projectionFileName)<EOL>return projectionText<EOL>
TODO: DOCUMENT !! Returns None if no such projection exists
f3377:c0:m1
def fetchFiles(self):
print("<STR_LIT>".format(self.baseDir))<EOL>files = glob(path.join(self.baseDir, '<STR_LIT:*>'))<EOL>filesDef = []<EOL>for f in files:<EOL><INDENT>print("<STR_LIT>".format(f))<EOL>relative = f.replace(self.baseDir, '<STR_LIT>')<EOL>filesDef.append({<EOL>'<STR_LIT>': relative,<EOL>'<STR_LIT:name>': relative<EOL>})<EOL><DEDENT>return filesDef<EOL>
Returns a list of file items contained on the local repo.
f3377:c2:m1
def getRawRepoUri(self):
return '<STR_LIT>'<EOL>
Returns the root url of the local repo.
f3377:c2:m2
def getTextFor(self, fileItem):
return self._getText(fileItem['<STR_LIT>'])<EOL>
Returns the contents of the given file item on the local repo.
f3377:c2:m3
def getResponseText(endpoint, query, requestedMimeType):
retFormat = _mimeTypeToSparqlFormat(requestedMimeType)<EOL>client = SPARQLWrapper(endpoint)<EOL>client.setQuery(query)<EOL>client.setReturnFormat(retFormat)<EOL>client.setCredentials(static.DEFAULT_ENDPOINT_USER, static.DEFAULT_ENDPOINT_PASSWORD)<EOL>result = client.queryAndConvert()<EOL>if retFormat==JSON:<EOL><INDENT>result = jsonify(result)<EOL><DEDENT>return result, MIME_FORMAT[retFormat]<EOL>
endpoint - URL of sparql endpoint query - SPARQL query to be executed requestedMimeType Type of content requested. can be: 'text/csv; q=1.0, */*; q=0.1' 'application/json' etc. Returns result + mimetype
f3378:m0
def get_blank_spec():
swag = {}<EOL>swag['<STR_LIT>'] = '<STR_LIT>'<EOL>swag['<STR_LIT>'] = [] <EOL>swag['<STR_LIT>'] = {}<EOL>swag['<STR_LIT>'] = {<EOL>'<STR_LIT>': {'<STR_LIT:type>': '<STR_LIT:string>'}<EOL>}<EOL>return swag<EOL>
Creates the base (blank) structure of swagger specification.
f3379:m0
def get_repo_info(loader, sha, prov_g):
user_repo = loader.getFullName()<EOL>repo_title = loader.getRepoTitle()<EOL>contact_name = loader.getContactName()<EOL>contact_url = loader.getContactUrl()<EOL>commit_list = loader.getCommitList()<EOL>licence_url = loader.getLicenceURL()<EOL>if prov_g:<EOL><INDENT>prov_g.add_used_entity(loader.getRepoURI())<EOL><DEDENT>prev_commit = None<EOL>next_commit = None<EOL>version = sha if sha else commit_list[<NUM_LIT:0>]<EOL>if commit_list.index(version) < len(commit_list) - <NUM_LIT:1>:<EOL><INDENT>prev_commit = commit_list[commit_list.index(version) + <NUM_LIT:1>]<EOL><DEDENT>if commit_list.index(version) > <NUM_LIT:0>:<EOL><INDENT>next_commit = commit_list[commit_list.index(version) - <NUM_LIT:1>]<EOL><DEDENT>info = {<EOL>'<STR_LIT:version>': version,<EOL>'<STR_LIT:title>': repo_title,<EOL>'<STR_LIT>': {<EOL>'<STR_LIT:name>': contact_name,<EOL>'<STR_LIT:url>': contact_url<EOL>},<EOL>'<STR_LIT>': {<EOL>'<STR_LIT:name>': '<STR_LIT>',<EOL>'<STR_LIT:url>': licence_url<EOL>}<EOL>}<EOL>basePath = '<STR_LIT>' + user_repo + '<STR_LIT:/>'<EOL>basePath += ('<STR_LIT>' + sha + '<STR_LIT:/>') if sha else '<STR_LIT>'<EOL>return prev_commit, next_commit, info, basePath<EOL>
Generate swagger information from the repo being used.
f3379:m1
def build_spec(user, repo, sha=None, prov=None, extraMetadata=[]):
loader = grlc.utils.getLoader(user, repo, sha=sha, prov=prov)<EOL>files = loader.fetchFiles()<EOL>raw_repo_uri = loader.getRawRepoUri()<EOL>items = []<EOL>allowed_ext = ["<STR_LIT>", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>"]<EOL>for c in files:<EOL><INDENT>glogger.debug('<STR_LIT>'.format(c['<STR_LIT:name>']))<EOL>extension = c['<STR_LIT:name>'].split('<STR_LIT:.>')[-<NUM_LIT:1>]<EOL>if extension in allowed_ext:<EOL><INDENT>call_name = c['<STR_LIT:name>'].split('<STR_LIT:.>')[<NUM_LIT:0>]<EOL>query_text = loader.getTextFor(c)<EOL>item = None<EOL>if extension == "<STR_LIT>":<EOL><INDENT>query_text = json.loads(query_text)<EOL><DEDENT>if extension in ["<STR_LIT>", "<STR_LIT>", "<STR_LIT>"]:<EOL><INDENT>glogger.debug("<STR_LIT>")<EOL>glogger.debug("<STR_LIT>".format(c['<STR_LIT:name>']))<EOL>glogger.debug("<STR_LIT>")<EOL>item = process_sparql_query_text(query_text, loader, call_name, extraMetadata)<EOL><DEDENT>elif "<STR_LIT>" == extension:<EOL><INDENT>glogger.debug("<STR_LIT>")<EOL>glogger.debug("<STR_LIT>".format(c['<STR_LIT:name>']))<EOL>glogger.debug("<STR_LIT>")<EOL>item = process_tpf_query_text(query_text, raw_repo_uri, call_name, extraMetadata)<EOL><DEDENT>else:<EOL><INDENT>glogger.info("<STR_LIT>".format(c['<STR_LIT:name>']))<EOL><DEDENT>if item:<EOL><INDENT>items.append(item)<EOL><DEDENT><DEDENT><DEDENT>return items<EOL>
Build grlc specification for the given github user / repo.
f3379:m3
def getSwaggerPaginationDef(resultsPerPage):
return {<EOL>"<STR_LIT:name>": "<STR_LIT>",<EOL>"<STR_LIT:type>": "<STR_LIT:int>",<EOL>"<STR_LIT>": "<STR_LIT>",<EOL>"<STR_LIT:description>": "<STR_LIT>".format(resultsPerPage)<EOL>}<EOL>
Build swagger spec section for pagination
f3381:m0
def buildPaginationHeader(resultCount, resultsPerPage, pageArg, url):
lastPage = resultCount / resultsPerPage<EOL>if pageArg:<EOL><INDENT>page = int(pageArg)<EOL>next_url = re.sub("<STR_LIT>", "<STR_LIT>".format(page + <NUM_LIT:1>), url)<EOL>prev_url = re.sub("<STR_LIT>", "<STR_LIT>".format(page - <NUM_LIT:1>), url)<EOL>first_url = re.sub("<STR_LIT>", "<STR_LIT>", url)<EOL>last_url = re.sub("<STR_LIT>", "<STR_LIT>".format(lastPage), url)<EOL><DEDENT>else:<EOL><INDENT>page = <NUM_LIT:1><EOL>next_url = url + "<STR_LIT>"<EOL>prev_url = "<STR_LIT>"<EOL>first_url = url + "<STR_LIT>"<EOL>last_url = url + "<STR_LIT>".format(lastPage)<EOL><DEDENT>if page == <NUM_LIT:1>:<EOL><INDENT>headerLink = "<STR_LIT>".format(next_url, last_url)<EOL><DEDENT>elif page == lastPage:<EOL><INDENT>headerLink = "<STR_LIT>".format(prev_url, first_url)<EOL><DEDENT>else:<EOL><INDENT>headerLink = "<STR_LIT>".format(next_url, prev_url, first_url, last_url)<EOL><DEDENT>return headerLink<EOL>
Build link header for result pagination
f3381:m1